| 1 | /* Test of <bitrotate.h> substitute.
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| 2 | Copyright (C) 2007-2021 Free Software Foundation, Inc.
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| 3 |
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| 4 | This program is free software: you can redistribute it and/or modify
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| 5 | it under the terms of the GNU General Public License as published by
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| 6 | the Free Software Foundation; either version 3 of the License, or
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| 7 | (at your option) any later version.
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| 8 |
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| 9 | This program is distributed in the hope that it will be useful,
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| 10 | but WITHOUT ANY WARRANTY; without even the implied warranty of
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| 11 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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| 12 | GNU General Public License for more details.
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| 13 |
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| 14 | You should have received a copy of the GNU General Public License
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| 15 | along with this program. If not, see <https://www.gnu.org/licenses/>. */
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| 16 |
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| 17 | /* Written by Simon Josefsson <[email protected]>, 2008. */
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| 18 |
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| 19 | #include <config.h>
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| 20 |
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| 21 | #include "bitrotate.h"
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| 22 |
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| 23 | #include "macros.h"
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| 24 |
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| 25 | int
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| 26 | main (void)
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| 27 | {
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| 28 | ASSERT (rotl8 (42, 0) == 42);
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| 29 | ASSERT (rotl8 (42, 1) == 84);
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| 30 | ASSERT (rotl8 (42, 2) == 168);
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| 31 | ASSERT (rotl8 (42, 3) == 81);
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| 32 | ASSERT (rotl8 (42, 4) == 162);
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| 33 | ASSERT (rotl8 (42, 5) == 69);
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| 34 | ASSERT (rotl8 (42, 6) == 138);
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| 35 | ASSERT (rotl8 (42, 7) == 21);
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| 36 | ASSERT (rotl8 (42, 8) == 42);
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| 37 |
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| 38 | ASSERT (rotr8 (42, 0) == 42);
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| 39 | ASSERT (rotr8 (42, 1) == 21);
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| 40 | ASSERT (rotr8 (42, 2) == 138);
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| 41 | ASSERT (rotr8 (42, 3) == 69);
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| 42 | ASSERT (rotr8 (42, 4) == 162);
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| 43 | ASSERT (rotr8 (42, 5) == 81);
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| 44 | ASSERT (rotr8 (42, 6) == 168);
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| 45 | ASSERT (rotr8 (42, 7) == 84);
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| 46 | ASSERT (rotr8 (42, 8) == 42);
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| 47 |
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| 48 | ASSERT (rotl16 (43981, 0) == 43981);
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| 49 | ASSERT (rotl16 (43981, 1) == 22427);
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| 50 | ASSERT (rotl16 (43981, 2) == 44854);
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| 51 | ASSERT (rotl16 (43981, 3) == 24173);
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| 52 | ASSERT (rotl16 (43981, 4) == 48346);
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| 53 | ASSERT (rotl16 (43981, 5) == 31157);
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| 54 | ASSERT (rotl16 (43981, 6) == 62314);
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| 55 | ASSERT (rotl16 (43981, 7) == 59093);
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| 56 | ASSERT (rotl16 (43981, 8) == 52651);
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| 57 | ASSERT (rotl16 (43981, 9) == 39767);
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| 58 | ASSERT (rotl16 (43981, 10) == 13999);
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| 59 | ASSERT (rotl16 (43981, 11) == 27998);
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| 60 | ASSERT (rotl16 (43981, 12) == 55996);
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| 61 | ASSERT (rotl16 (43981, 13) == 46457);
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| 62 | ASSERT (rotl16 (43981, 14) == 27379);
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| 63 | ASSERT (rotl16 (43981, 15) == 54758);
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| 64 | ASSERT (rotl16 (43981, 16) == 43981);
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| 65 |
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| 66 | ASSERT (rotr16 (43981, 0) == 43981);
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| 67 | ASSERT (rotr16 (43981, 1) == 54758);
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| 68 | ASSERT (rotr16 (43981, 2) == 27379);
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| 69 | ASSERT (rotr16 (43981, 3) == 46457);
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| 70 | ASSERT (rotr16 (43981, 4) == 55996);
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| 71 | ASSERT (rotr16 (43981, 5) == 27998);
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| 72 | ASSERT (rotr16 (43981, 6) == 13999);
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| 73 | ASSERT (rotr16 (43981, 7) == 39767);
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| 74 | ASSERT (rotr16 (43981, 8) == 52651);
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| 75 | ASSERT (rotr16 (43981, 9) == 59093);
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| 76 | ASSERT (rotr16 (43981, 10) == 62314);
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| 77 | ASSERT (rotr16 (43981, 11) == 31157);
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| 78 | ASSERT (rotr16 (43981, 12) == 48346);
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| 79 | ASSERT (rotr16 (43981, 13) == 24173);
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| 80 | ASSERT (rotr16 (43981, 14) == 44854);
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| 81 | ASSERT (rotr16 (43981, 15) == 22427);
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| 82 | ASSERT (rotr16 (43981, 16) == 43981);
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| 83 |
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| 84 | ASSERT (rotl32 (2309737967U, 1) == 324508639U);
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| 85 | ASSERT (rotl32 (2309737967U, 2) == 649017278U);
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| 86 | ASSERT (rotl32 (2309737967U, 3) == 1298034556U);
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| 87 | ASSERT (rotl32 (2309737967U, 4) == 2596069112U);
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| 88 | ASSERT (rotl32 (2309737967U, 5) == 897170929U);
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| 89 | ASSERT (rotl32 (2309737967U, 6) == 1794341858U);
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| 90 | ASSERT (rotl32 (2309737967U, 7) == 3588683716U);
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| 91 | ASSERT (rotl32 (2309737967U, 8) == 2882400137U);
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| 92 | ASSERT (rotl32 (2309737967U, 9) == 1469832979U);
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| 93 | ASSERT (rotl32 (2309737967U, 10) == 2939665958U);
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| 94 | ASSERT (rotl32 (2309737967U, 11) == 1584364621U);
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| 95 | ASSERT (rotl32 (2309737967U, 12) == 3168729242U);
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| 96 | ASSERT (rotl32 (2309737967U, 13) == 2042491189U);
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| 97 | ASSERT (rotl32 (2309737967U, 14) == 4084982378U);
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| 98 | ASSERT (rotl32 (2309737967U, 15) == 3874997461U);
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| 99 | ASSERT (rotl32 (2309737967U, 16) == 3455027627U);
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| 100 | ASSERT (rotl32 (2309737967U, 17) == 2615087959U);
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| 101 | ASSERT (rotl32 (2309737967U, 18) == 935208623U);
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| 102 | ASSERT (rotl32 (2309737967U, 19) == 1870417246U);
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| 103 | ASSERT (rotl32 (2309737967U, 20) == 3740834492U);
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| 104 | ASSERT (rotl32 (2309737967U, 21) == 3186701689U);
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| 105 | ASSERT (rotl32 (2309737967U, 22) == 2078436083U);
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| 106 | ASSERT (rotl32 (2309737967U, 23) == 4156872166U);
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| 107 | ASSERT (rotl32 (2309737967U, 24) == 4018777037U);
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| 108 | ASSERT (rotl32 (2309737967U, 25) == 3742586779U);
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| 109 | ASSERT (rotl32 (2309737967U, 26) == 3190206263U);
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| 110 | ASSERT (rotl32 (2309737967U, 27) == 2085445231U);
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| 111 | ASSERT (rotl32 (2309737967U, 28) == 4170890462U);
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| 112 | ASSERT (rotl32 (2309737967U, 29) == 4046813629U);
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| 113 | ASSERT (rotl32 (2309737967U, 30) == 3798659963U);
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| 114 | ASSERT (rotl32 (2309737967U, 31) == 3302352631U);
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| 115 |
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| 116 | ASSERT (rotr32 (2309737967U, 1) == 3302352631lU);
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| 117 | ASSERT (rotr32 (2309737967U, 2) == 3798659963lU);
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| 118 | ASSERT (rotr32 (2309737967U, 3) == 4046813629lU);
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| 119 | ASSERT (rotr32 (2309737967U, 4) == 4170890462lU);
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| 120 | ASSERT (rotr32 (2309737967U, 5) == 2085445231lU);
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| 121 | ASSERT (rotr32 (2309737967U, 6) == 3190206263lU);
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| 122 | ASSERT (rotr32 (2309737967U, 7) == 3742586779lU);
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| 123 | ASSERT (rotr32 (2309737967U, 8) == 4018777037lU);
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| 124 | ASSERT (rotr32 (2309737967U, 9) == 4156872166lU);
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| 125 | ASSERT (rotr32 (2309737967U, 10) == 2078436083lU);
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| 126 | ASSERT (rotr32 (2309737967U, 11) == 3186701689lU);
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| 127 | ASSERT (rotr32 (2309737967U, 12) == 3740834492lU);
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| 128 | ASSERT (rotr32 (2309737967U, 13) == 1870417246lU);
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| 129 | ASSERT (rotr32 (2309737967U, 14) == 935208623lU);
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| 130 | ASSERT (rotr32 (2309737967U, 15) == 2615087959lU);
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| 131 | ASSERT (rotr32 (2309737967U, 16) == 3455027627lU);
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| 132 | ASSERT (rotr32 (2309737967U, 17) == 3874997461lU);
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| 133 | ASSERT (rotr32 (2309737967U, 18) == 4084982378lU);
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| 134 | ASSERT (rotr32 (2309737967U, 19) == 2042491189lU);
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| 135 | ASSERT (rotr32 (2309737967U, 20) == 3168729242lU);
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| 136 | ASSERT (rotr32 (2309737967U, 21) == 1584364621lU);
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| 137 | ASSERT (rotr32 (2309737967U, 22) == 2939665958lU);
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| 138 | ASSERT (rotr32 (2309737967U, 23) == 1469832979lU);
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| 139 | ASSERT (rotr32 (2309737967U, 24) == 2882400137lU);
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| 140 | ASSERT (rotr32 (2309737967U, 25) == 3588683716lU);
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| 141 | ASSERT (rotr32 (2309737967U, 26) == 1794341858lU);
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| 142 | ASSERT (rotr32 (2309737967U, 27) == 897170929lU);
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| 143 | ASSERT (rotr32 (2309737967U, 28) == 2596069112lU);
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| 144 | ASSERT (rotr32 (2309737967U, 29) == 1298034556lU);
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| 145 | ASSERT (rotr32 (2309737967U, 30) == 649017278lU);
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| 146 | ASSERT (rotr32 (2309737967U, 31) == 324508639lU);
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| 147 |
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| 148 | #ifdef UINT64_MAX
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| 149 | ASSERT (rotl64 (16045690984503098046ULL, 1) == 13644637895296644477ULL);
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| 150 | ASSERT (rotl64 (16045690984503098046ULL, 2) == 8842531716883737339ULL);
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| 151 | ASSERT (rotl64 (16045690984503098046ULL, 3) == 17685063433767474678ULL);
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| 152 | ASSERT (rotl64 (16045690984503098046ULL, 4) == 16923382793825397741ULL);
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| 153 | ASSERT (rotl64 (16045690984503098046ULL, 5) == 15400021513941243867ULL);
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| 154 | ASSERT (rotl64 (16045690984503098046ULL, 6) == 12353298954172936119ULL);
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| 155 | ASSERT (rotl64 (16045690984503098046ULL, 7) == 6259853834636320623ULL);
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| 156 | ASSERT (rotl64 (16045690984503098046ULL, 8) == 12519707669272641246ULL);
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| 157 | ASSERT (rotl64 (16045690984503098046ULL, 9) == 6592671264835730877ULL);
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| 158 | ASSERT (rotl64 (16045690984503098046ULL, 10) == 13185342529671461754ULL);
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| 159 | ASSERT (rotl64 (16045690984503098046ULL, 11) == 7923940985633371893ULL);
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| 160 | ASSERT (rotl64 (16045690984503098046ULL, 12) == 15847881971266743786ULL);
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| 161 | ASSERT (rotl64 (16045690984503098046ULL, 13) == 13249019868823935957ULL);
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| 162 | ASSERT (rotl64 (16045690984503098046ULL, 14) == 8051295663938320299ULL);
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| 163 | ASSERT (rotl64 (16045690984503098046ULL, 15) == 16102591327876640598ULL);
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| 164 | ASSERT (rotl64 (16045690984503098046ULL, 16) == 13758438582043729581ULL);
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| 165 | ASSERT (rotl64 (16045690984503098046ULL, 17) == 9070133090377907547ULL);
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| 166 | ASSERT (rotl64 (16045690984503098046ULL, 18) == 18140266180755815094ULL);
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| 167 | ASSERT (rotl64 (16045690984503098046ULL, 19) == 17833788287802078573ULL);
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| 168 | ASSERT (rotl64 (16045690984503098046ULL, 20) == 17220832501894605531ULL);
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| 169 | ASSERT (rotl64 (16045690984503098046ULL, 21) == 15994920930079659447ULL);
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| 170 | ASSERT (rotl64 (16045690984503098046ULL, 22) == 13543097786449767279ULL);
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| 171 | ASSERT (rotl64 (16045690984503098046ULL, 23) == 8639451499189982943ULL);
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| 172 | ASSERT (rotl64 (16045690984503098046ULL, 24) == 17278902998379965886ULL);
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| 173 | ASSERT (rotl64 (16045690984503098046ULL, 25) == 16111061923050380157ULL);
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| 174 | ASSERT (rotl64 (16045690984503098046ULL, 26) == 13775379772391208699ULL);
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| 175 | ASSERT (rotl64 (16045690984503098046ULL, 27) == 9104015471072865783ULL);
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| 176 | ASSERT (rotl64 (16045690984503098046ULL, 28) == 18208030942145731566ULL);
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| 177 | ASSERT (rotl64 (16045690984503098046ULL, 29) == 17969317810581911517ULL);
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| 178 | ASSERT (rotl64 (16045690984503098046ULL, 30) == 17491891547454271419ULL);
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| 179 | ASSERT (rotl64 (16045690984503098046ULL, 31) == 16537039021198991223ULL);
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| 180 | ASSERT (rotl64 (16045690984503098046ULL, 32) == 14627333968688430831ULL);
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| 181 | ASSERT (rotl64 (16045690984503098046ULL, 33) == 10807923863667310047ULL);
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| 182 | ASSERT (rotl64 (16045690984503098046ULL, 34) == 3169103653625068479ULL);
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| 183 | ASSERT (rotl64 (16045690984503098046ULL, 35) == 6338207307250136958ULL);
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| 184 | ASSERT (rotl64 (16045690984503098046ULL, 36) == 12676414614500273916ULL);
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| 185 | ASSERT (rotl64 (16045690984503098046ULL, 37) == 6906085155290996217ULL);
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| 186 | ASSERT (rotl64 (16045690984503098046ULL, 38) == 13812170310581992434ULL);
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| 187 | ASSERT (rotl64 (16045690984503098046ULL, 39) == 9177596547454433253ULL);
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| 188 | ASSERT (rotl64 (16045690984503098046ULL, 40) == 18355193094908866506ULL);
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| 189 | ASSERT (rotl64 (16045690984503098046ULL, 41) == 18263642116108181397ULL);
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| 190 | ASSERT (rotl64 (16045690984503098046ULL, 42) == 18080540158506811179ULL);
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| 191 | ASSERT (rotl64 (16045690984503098046ULL, 43) == 17714336243304070743ULL);
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| 192 | ASSERT (rotl64 (16045690984503098046ULL, 44) == 16981928412898589871ULL);
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| 193 | ASSERT (rotl64 (16045690984503098046ULL, 45) == 15517112752087628127ULL);
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| 194 | ASSERT (rotl64 (16045690984503098046ULL, 46) == 12587481430465704639ULL);
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| 195 | ASSERT (rotl64 (16045690984503098046ULL, 47) == 6728218787221857663ULL);
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| 196 | ASSERT (rotl64 (16045690984503098046ULL, 48) == 13456437574443715326ULL);
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| 197 | ASSERT (rotl64 (16045690984503098046ULL, 49) == 8466131075177879037ULL);
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| 198 | ASSERT (rotl64 (16045690984503098046ULL, 50) == 16932262150355758074ULL);
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| 199 | ASSERT (rotl64 (16045690984503098046ULL, 51) == 15417780227001964533ULL);
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| 200 | ASSERT (rotl64 (16045690984503098046ULL, 52) == 12388816380294377451ULL);
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| 201 | ASSERT (rotl64 (16045690984503098046ULL, 53) == 6330888686879203287ULL);
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| 202 | ASSERT (rotl64 (16045690984503098046ULL, 54) == 12661777373758406574ULL);
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| 203 | ASSERT (rotl64 (16045690984503098046ULL, 55) == 6876810673807261533ULL);
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| 204 | ASSERT (rotl64 (16045690984503098046ULL, 56) == 13753621347614523066ULL);
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| 205 | ASSERT (rotl64 (16045690984503098046ULL, 57) == 9060498621519494517ULL);
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| 206 | ASSERT (rotl64 (16045690984503098046ULL, 58) == 18120997243038989034ULL);
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| 207 | ASSERT (rotl64 (16045690984503098046ULL, 59) == 17795250412368426453ULL);
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| 208 | ASSERT (rotl64 (16045690984503098046ULL, 60) == 17143756751027301291ULL);
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| 209 | ASSERT (rotl64 (16045690984503098046ULL, 61) == 15840769428345050967ULL);
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| 210 | ASSERT (rotl64 (16045690984503098046ULL, 62) == 13234794782980550319ULL);
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| 211 | ASSERT (rotl64 (16045690984503098046ULL, 63) == 8022845492251549023ULL);
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| 212 |
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| 213 | ASSERT (rotr64 (16045690984503098046ULL, 1) == 8022845492251549023ULL);
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| 214 | ASSERT (rotr64 (16045690984503098046ULL, 2) == 13234794782980550319ULL);
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| 215 | ASSERT (rotr64 (16045690984503098046ULL, 3) == 15840769428345050967ULL);
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| 216 | ASSERT (rotr64 (16045690984503098046ULL, 4) == 17143756751027301291ULL);
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| 217 | ASSERT (rotr64 (16045690984503098046ULL, 5) == 17795250412368426453ULL);
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| 218 | ASSERT (rotr64 (16045690984503098046ULL, 6) == 18120997243038989034ULL);
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| 219 | ASSERT (rotr64 (16045690984503098046ULL, 7) == 9060498621519494517ULL);
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| 220 | ASSERT (rotr64 (16045690984503098046ULL, 8) == 13753621347614523066ULL);
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| 221 | ASSERT (rotr64 (16045690984503098046ULL, 9) == 6876810673807261533ULL);
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| 222 | ASSERT (rotr64 (16045690984503098046ULL, 10) == 12661777373758406574ULL);
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| 223 | ASSERT (rotr64 (16045690984503098046ULL, 11) == 6330888686879203287ULL);
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| 224 | ASSERT (rotr64 (16045690984503098046ULL, 12) == 12388816380294377451ULL);
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| 225 | ASSERT (rotr64 (16045690984503098046ULL, 13) == 15417780227001964533ULL);
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| 226 | ASSERT (rotr64 (16045690984503098046ULL, 14) == 16932262150355758074ULL);
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| 227 | ASSERT (rotr64 (16045690984503098046ULL, 15) == 8466131075177879037ULL);
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| 228 | ASSERT (rotr64 (16045690984503098046ULL, 16) == 13456437574443715326ULL);
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| 229 | ASSERT (rotr64 (16045690984503098046ULL, 17) == 6728218787221857663ULL);
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| 230 | ASSERT (rotr64 (16045690984503098046ULL, 18) == 12587481430465704639ULL);
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| 231 | ASSERT (rotr64 (16045690984503098046ULL, 19) == 15517112752087628127ULL);
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| 232 | ASSERT (rotr64 (16045690984503098046ULL, 20) == 16981928412898589871ULL);
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| 233 | ASSERT (rotr64 (16045690984503098046ULL, 21) == 17714336243304070743ULL);
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| 234 | ASSERT (rotr64 (16045690984503098046ULL, 22) == 18080540158506811179ULL);
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| 235 | ASSERT (rotr64 (16045690984503098046ULL, 23) == 18263642116108181397ULL);
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| 236 | ASSERT (rotr64 (16045690984503098046ULL, 24) == 18355193094908866506ULL);
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| 237 | ASSERT (rotr64 (16045690984503098046ULL, 25) == 9177596547454433253ULL);
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| 238 | ASSERT (rotr64 (16045690984503098046ULL, 26) == 13812170310581992434ULL);
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| 239 | ASSERT (rotr64 (16045690984503098046ULL, 27) == 6906085155290996217ULL);
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| 240 | ASSERT (rotr64 (16045690984503098046ULL, 28) == 12676414614500273916ULL);
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| 241 | ASSERT (rotr64 (16045690984503098046ULL, 29) == 6338207307250136958ULL);
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| 242 | ASSERT (rotr64 (16045690984503098046ULL, 30) == 3169103653625068479ULL);
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| 243 | ASSERT (rotr64 (16045690984503098046ULL, 31) == 10807923863667310047ULL);
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| 244 | ASSERT (rotr64 (16045690984503098046ULL, 32) == 14627333968688430831ULL);
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| 245 | ASSERT (rotr64 (16045690984503098046ULL, 33) == 16537039021198991223ULL);
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| 246 | ASSERT (rotr64 (16045690984503098046ULL, 34) == 17491891547454271419ULL);
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| 247 | ASSERT (rotr64 (16045690984503098046ULL, 35) == 17969317810581911517ULL);
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| 248 | ASSERT (rotr64 (16045690984503098046ULL, 36) == 18208030942145731566ULL);
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| 249 | ASSERT (rotr64 (16045690984503098046ULL, 37) == 9104015471072865783ULL);
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| 250 | ASSERT (rotr64 (16045690984503098046ULL, 38) == 13775379772391208699ULL);
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| 251 | ASSERT (rotr64 (16045690984503098046ULL, 39) == 16111061923050380157ULL);
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| 252 | ASSERT (rotr64 (16045690984503098046ULL, 40) == 17278902998379965886ULL);
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| 253 | ASSERT (rotr64 (16045690984503098046ULL, 41) == 8639451499189982943ULL);
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| 254 | ASSERT (rotr64 (16045690984503098046ULL, 42) == 13543097786449767279ULL);
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| 255 | ASSERT (rotr64 (16045690984503098046ULL, 43) == 15994920930079659447ULL);
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| 256 | ASSERT (rotr64 (16045690984503098046ULL, 44) == 17220832501894605531ULL);
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| 257 | ASSERT (rotr64 (16045690984503098046ULL, 45) == 17833788287802078573ULL);
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| 258 | ASSERT (rotr64 (16045690984503098046ULL, 46) == 18140266180755815094ULL);
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| 259 | ASSERT (rotr64 (16045690984503098046ULL, 47) == 9070133090377907547ULL);
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| 260 | ASSERT (rotr64 (16045690984503098046ULL, 48) == 13758438582043729581ULL);
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| 261 | ASSERT (rotr64 (16045690984503098046ULL, 49) == 16102591327876640598ULL);
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| 262 | ASSERT (rotr64 (16045690984503098046ULL, 50) == 8051295663938320299ULL);
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| 263 | ASSERT (rotr64 (16045690984503098046ULL, 51) == 13249019868823935957ULL);
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| 264 | ASSERT (rotr64 (16045690984503098046ULL, 52) == 15847881971266743786ULL);
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| 265 | ASSERT (rotr64 (16045690984503098046ULL, 53) == 7923940985633371893ULL);
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| 266 | ASSERT (rotr64 (16045690984503098046ULL, 54) == 13185342529671461754ULL);
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| 267 | ASSERT (rotr64 (16045690984503098046ULL, 55) == 6592671264835730877ULL);
|
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| 268 | ASSERT (rotr64 (16045690984503098046ULL, 56) == 12519707669272641246ULL);
|
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| 269 | ASSERT (rotr64 (16045690984503098046ULL, 57) == 6259853834636320623ULL);
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| 270 | ASSERT (rotr64 (16045690984503098046ULL, 58) == 12353298954172936119ULL);
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|---|
| 271 | ASSERT (rotr64 (16045690984503098046ULL, 59) == 15400021513941243867ULL);
|
|---|
| 272 | ASSERT (rotr64 (16045690984503098046ULL, 60) == 16923382793825397741ULL);
|
|---|
| 273 | ASSERT (rotr64 (16045690984503098046ULL, 61) == 17685063433767474678ULL);
|
|---|
| 274 | ASSERT (rotr64 (16045690984503098046ULL, 62) == 8842531716883737339ULL);
|
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| 275 | ASSERT (rotr64 (16045690984503098046ULL, 63) == 13644637895296644477ULL);
|
|---|
| 276 | #endif /* UINT64_MAX */
|
|---|
| 277 |
|
|---|
| 278 | return 0;
|
|---|
| 279 | }
|
|---|
