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1/** @file
2 * X86 (and AMD64) Local APIC registers (VMM,++).
3 *
4 * apic.mac is generated from this file by running 'kmk incs' in the root.
5 */
6
7/*
8 * Copyright (C) 2010-2022 Oracle Corporation
9 *
10 * This file is part of VirtualBox Open Source Edition (OSE), as
11 * available from http://www.virtualbox.org. This file is free software;
12 * you can redistribute it and/or modify it under the terms of the GNU
13 * General Public License (GPL) as published by the Free Software
14 * Foundation, in version 2 as it comes in the "COPYING" file of the
15 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
16 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
17 *
18 * The contents of this file may alternatively be used under the terms
19 * of the Common Development and Distribution License Version 1.0
20 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
21 * VirtualBox OSE distribution, in which case the provisions of the
22 * CDDL are applicable instead of those of the GPL.
23 *
24 * You may elect to license modified versions of this file under the
25 * terms and conditions of either the GPL or the CDDL or both.
26 */
27
28#ifndef VBOX_INCLUDED_apic_h
29#define VBOX_INCLUDED_apic_h
30#ifndef RT_WITHOUT_PRAGMA_ONCE
31# pragma once
32#endif
33
34#include <iprt/types.h>
35#include <iprt/x86.h>
36
37/** @todo These are defines used by CPUM and perhaps some assembly code. Remove
38 * these and use the XAPIC counterpart defines below later. */
39#define APIC_REG_VERSION 0x0030
40#define APIC_REG_VERSION_GET_VER(u32) (u32 & 0xff)
41#define APIC_REG_VERSION_GET_MAX_LVT(u32) ((u32 & 0xff0000) >> 16)
42
43/* Defines according to Figure 10-8 of the Intel Software Developers Manual Vol 3A */
44#define APIC_REG_LVT_LINT0 0x0350
45#define APIC_REG_LVT_LINT1 0x0360
46#define APIC_REG_LVT_ERR 0x0370
47#define APIC_REG_LVT_PC 0x0340
48#define APIC_REG_LVT_THMR 0x0330
49#define APIC_REG_LVT_CMCI 0x02F0
50#define APIC_REG_EILVT0 0x0500
51#define APIC_REG_EILVT1 0x0510
52#define APIC_REG_EILVT2 0x0520
53#define APIC_REG_EILVT3 0x0530
54#define APIC_REG_LVT_MODE_MASK (RT_BIT(8) | RT_BIT(9) | RT_BIT(10))
55#define APIC_REG_LVT_MODE_FIXED 0
56#define APIC_REG_LVT_MODE_NMI RT_BIT(10)
57#define APIC_REG_LVT_MODE_EXTINT (RT_BIT(8) | RT_BIT(9) | RT_BIT(10))
58#define APIC_REG_LVT_PIN_POLARIY RT_BIT(13)
59#define APIC_REG_LVT_REMOTE_IRR RT_BIT(14)
60#define APIC_REG_LVT_LEVEL_TRIGGER RT_BIT(15)
61#define APIC_REG_LVT_MASKED RT_BIT(16)
62
63/** The APIC hardware version number for Pentium 4. */
64#define XAPIC_HARDWARE_VERSION_P4 UINT8_C(0x14)
65/** Maximum number of LVT entries for Pentium 4. */
66#define XAPIC_MAX_LVT_ENTRIES_P4 UINT8_C(6)
67/** Size of the APIC ID bits for Pentium 4. */
68#define XAPIC_APIC_ID_BIT_COUNT_P4 UINT8_C(8)
69
70/** The APIC hardware version number for Pentium 6. */
71#define XAPIC_HARDWARE_VERSION_P6 UINT8_C(0x10)
72/** Maximum number of LVT entries for Pentium 6. */
73#define XAPIC_MAX_LVT_ENTRIES_P6 UINT8_C(4)
74/** Size of the APIC ID bits for Pentium 6. */
75#define XAPIC_APIC_ID_BIT_COUNT_P6 UINT8_C(4)
76
77/** Illegal APIC vector value start. */
78#define XAPIC_ILLEGAL_VECTOR_START UINT8_C(0)
79/** Illegal APIC vector value end (inclusive). */
80#define XAPIC_ILLEGAL_VECTOR_END UINT8_C(15)
81/** Reserved APIC vector value start. */
82#define XAPIC_RSVD_VECTOR_START UINT8_C(16)
83/** Reserved APIC vector value end (inclusive). */
84#define XAPIC_RSVD_VECTOR_END UINT8_C(31)
85
86/** ESR - Send checksum error for Pentium 6. */
87# define XAPIC_ESR_SEND_CHKSUM_ERROR_P6 RT_BIT(0)
88/** ESR - Send accept error for Pentium 6. */
89# define XAPIC_ESR_RECV_CHKSUM_ERROR_P6 RT_BIT(1)
90/** ESR - Send accept error for Pentium 6. */
91# define XAPIC_ESR_SEND_ACCEPT_ERROR_P6 RT_BIT(2)
92/** ESR - Receive accept error for Pentium 6. */
93# define XAPIC_ESR_RECV_ACCEPT_ERROR_P6 RT_BIT(3)
94
95/** ESR - Redirectable IPI. */
96#define XAPIC_ESR_REDIRECTABLE_IPI RT_BIT(4)
97/** ESR - Send accept error. */
98#define XAPIC_ESR_SEND_ILLEGAL_VECTOR RT_BIT(5)
99/** ESR - Send accept error. */
100#define XAPIC_ESR_RECV_ILLEGAL_VECTOR RT_BIT(6)
101/** ESR - Send accept error. */
102#define XAPIC_ESR_ILLEGAL_REG_ADDRESS RT_BIT(7)
103/** ESR - Valid write-only bits. */
104#define XAPIC_ESR_WO_VALID UINT32_C(0x0)
105
106/** TPR - Valid bits. */
107#define XAPIC_TPR_VALID UINT32_C(0xff)
108/** TPR - Task-priority class. */
109#define XAPIC_TPR_TP UINT32_C(0xf0)
110/** TPR - Task-priority subclass. */
111#define XAPIC_TPR_TP_SUBCLASS UINT32_C(0x0f)
112/** TPR - Gets the task-priority class. */
113#define XAPIC_TPR_GET_TP(a_Tpr) ((a_Tpr) & XAPIC_TPR_TP)
114/** TPR - Gets the task-priority subclass. */
115#define XAPIC_TPR_GET_TP_SUBCLASS(a_Tpr) ((a_Tpr) & XAPIC_TPR_TP_SUBCLASS)
116
117/** PPR - Valid bits. */
118#define XAPIC_PPR_VALID UINT32_C(0xff)
119/** PPR - Processor-priority class. */
120#define XAPIC_PPR_PP UINT32_C(0xf0)
121/** PPR - Processor-priority subclass. */
122#define XAPIC_PPR_PP_SUBCLASS UINT32_C(0x0f)
123/** PPR - Get the processor-priority class. */
124#define XAPIC_PPR_GET_PP(a_Ppr) ((a_Ppr) & XAPIC_PPR_PP)
125/** PPR - Get the processor-priority subclass. */
126#define XAPIC_PPR_GET_PP_SUBCLASS(a_Ppr) ((a_Ppr) & XAPIC_PPR_PP_SUBCLASS)
127
128/** Timer mode - One-shot. */
129#define XAPIC_TIMER_MODE_ONESHOT UINT32_C(0)
130/** Timer mode - Periodic. */
131#define XAPIC_TIMER_MODE_PERIODIC UINT32_C(1)
132/** Timer mode - TSC deadline. */
133#define XAPIC_TIMER_MODE_TSC_DEADLINE UINT32_C(2)
134
135/** LVT - The vector. */
136#define XAPIC_LVT_VECTOR UINT32_C(0xff)
137/** LVT - Gets the vector from an LVT entry. */
138#define XAPIC_LVT_GET_VECTOR(a_Lvt) ((a_Lvt) & XAPIC_LVT_VECTOR)
139/** LVT - The mask. */
140#define XAPIC_LVT_MASK RT_BIT(16)
141/** LVT - Is the LVT masked? */
142#define XAPIC_LVT_IS_MASKED(a_Lvt) RT_BOOL((a_Lvt) & XAPIC_LVT_MASK)
143/** LVT - Timer mode. */
144#define XAPIC_LVT_TIMER_MODE RT_BIT(17)
145/** LVT - Timer TSC-deadline timer mode. */
146#define XAPIC_LVT_TIMER_TSCDEADLINE RT_BIT(18)
147/** LVT - Gets the timer mode. */
148#define XAPIC_LVT_GET_TIMER_MODE(a_Lvt) (XAPICTIMERMODE)(((a_Lvt) >> 17) & UINT32_C(3))
149/** LVT - Delivery mode. */
150#define XAPIC_LVT_DELIVERY_MODE (RT_BIT(8) | RT_BIT(9) | RT_BIT(10))
151/** LVT - Gets the delivery mode. */
152#define XAPIC_LVT_GET_DELIVERY_MODE(a_Lvt) (XAPICDELIVERYMODE)(((a_Lvt) >> 8) & UINT32_C(7))
153/** LVT - Delivery status. */
154#define XAPIC_LVT_DELIVERY_STATUS RT_BIT(12)
155/** LVT - Trigger mode. */
156#define XAPIC_LVT_TRIGGER_MODE RT_BIT(15)
157/** LVT - Gets the trigger mode. */
158#define XAPIC_LVT_GET_TRIGGER_MODE(a_Lvt) (XAPICTRIGGERMODE)(((a_Lvt) >> 15) & UINT32_C(1))
159/** LVT - Remote IRR. */
160#define XAPIC_LVT_REMOTE_IRR RT_BIT(14)
161/** LVT - Gets the Remote IRR. */
162#define XAPIC_LVT_GET_REMOTE_IRR(a_Lvt) (((a_Lvt) >> 14) & 1)
163/** LVT - Interrupt Input Pin Polarity. */
164#define XAPIC_LVT_POLARITY RT_BIT(13)
165/** LVT - Gets the Interrupt Input Pin Polarity. */
166#define XAPIC_LVT_GET_POLARITY(a_Lvt) (((a_Lvt) >> 13) & 1)
167/** LVT - Valid bits common to all LVTs. */
168#define XAPIC_LVT_COMMON_VALID (XAPIC_LVT_VECTOR | XAPIC_LVT_DELIVERY_STATUS | XAPIC_LVT_MASK)
169/** LVT CMCI - Valid bits. */
170#define XAPIC_LVT_CMCI_VALID (XAPIC_LVT_COMMON_VALID | XAPIC_LVT_DELIVERY_MODE)
171/** LVT Timer - Valid bits. */
172#define XAPIC_LVT_TIMER_VALID (XAPIC_LVT_COMMON_VALID | XAPIC_LVT_TIMER_MODE | XAPIC_LVT_TIMER_TSCDEADLINE)
173/** LVT Thermal - Valid bits. */
174#define XAPIC_LVT_THERMAL_VALID (XAPIC_LVT_COMMON_VALID | XAPIC_LVT_DELIVERY_MODE)
175/** LVT Perf - Valid bits. */
176#define XAPIC_LVT_PERF_VALID (XAPIC_LVT_COMMON_VALID | XAPIC_LVT_DELIVERY_MODE)
177/** LVT LINTx - Valid bits. */
178#define XAPIC_LVT_LINT_VALID ( XAPIC_LVT_COMMON_VALID | XAPIC_LVT_DELIVERY_MODE | XAPIC_LVT_DELIVERY_STATUS \
179 | XAPIC_LVT_POLARITY | XAPIC_LVT_REMOTE_IRR | XAPIC_LVT_TRIGGER_MODE)
180/** LVT Error - Valid bits. */
181#define XAPIC_LVT_ERROR_VALID (XAPIC_LVT_COMMON_VALID)
182
183/** SVR - The vector. */
184#define XAPIC_SVR_VECTOR UINT32_C(0xff)
185/** SVR - APIC Software enable. */
186#define XAPIC_SVR_SOFTWARE_ENABLE RT_BIT(8)
187/** SVR - Supress EOI broadcast. */
188#define XAPIC_SVR_SUPRESS_EOI_BROADCAST RT_BIT(12)
189/** SVR - Valid bits for Pentium 4. */
190# define XAPIC_SVR_VALID_P4 (XAPIC_SVR_VECTOR | XAPIC_SVR_SOFTWARE_ENABLE)
191/** @todo SVR - Valid bits for Pentium 6. */
192
193/** DFR - Valid bits. */
194#define XAPIC_DFR_VALID UINT32_C(0xf0000000)
195/** DFR - Reserved bits that must always remain set. */
196#define XAPIC_DFR_RSVD_MB1 UINT32_C(0x0fffffff)
197/** DFR - The model. */
198#define XAPIC_DFR_MODEL UINT32_C(0xf)
199/** DFR - Gets the destination model. */
200#define XAPIC_DFR_GET_MODEL(a_uReg) (((a_uReg) >> 28) & XAPIC_DFR_MODEL)
201
202/** LDR - Valid bits. */
203#define XAPIC_LDR_VALID UINT32_C(0xff000000)
204/** LDR - Cluster ID mask (x2APIC). */
205#define X2APIC_LDR_CLUSTER_ID UINT32_C(0xffff0000)
206/** LDR - Mask of the LDR cluster ID (x2APIC). */
207#define X2APIC_LDR_GET_CLUSTER_ID(a_uReg) ((a_uReg) & X2APIC_LDR_CLUSTER_ID)
208/** LDR - Mask of the LDR logical ID (x2APIC). */
209#define X2APIC_LDR_LOGICAL_ID UINT32_C(0x0000ffff)
210
211/** LDR - Flat mode logical ID mask. */
212#define XAPIC_LDR_FLAT_LOGICAL_ID UINT32_C(0xff)
213/** LDR - Clustered mode cluster ID mask. */
214#define XAPIC_LDR_CLUSTERED_CLUSTER_ID UINT32_C(0xf0)
215/** LDR - Clustered mode logical ID mask. */
216#define XAPIC_LDR_CLUSTERED_LOGICAL_ID UINT32_C(0x0f)
217/** LDR - Gets the clustered mode cluster ID. */
218#define XAPIC_LDR_CLUSTERED_GET_CLUSTER_ID(a_uReg) ((a_uReg) & XAPIC_LDR_CLUSTERED_CLUSTER_ID)
219
220
221/** EOI - Valid write-only bits. */
222#define XAPIC_EOI_WO_VALID UINT32_C(0x0)
223/** Timer ICR - Valid bits. */
224#define XAPIC_TIMER_ICR_VALID UINT32_C(0xffffffff)
225/** Timer DCR - Valid bits. */
226#define XAPIC_TIMER_DCR_VALID (RT_BIT(0) | RT_BIT(1) | RT_BIT(3))
227
228/** Self IPI - Valid bits. */
229#define XAPIC_SELF_IPI_VALID UINT32_C(0xff)
230/** Self IPI - The vector. */
231#define XAPIC_SELF_IPI_VECTOR UINT32_C(0xff)
232/** Self IPI - Gets the vector. */
233#define XAPIC_SELF_IPI_GET_VECTOR(a_uReg) ((a_uReg) & XAPIC_SELF_IPI_VECTOR)
234
235/** ICR Low - The Vector. */
236#define XAPIC_ICR_LO_VECTOR UINT32_C(0xff)
237/** ICR Low - Gets the vector. */
238#define XAPIC_ICR_LO_GET_VECTOR(a_uIcr) ((a_uIcr) & XAPIC_ICR_LO_VECTOR)
239/** ICR Low - The delivery mode. */
240#define XAPIC_ICR_LO_DELIVERY_MODE (RT_BIT(8) | RT_BIT(9) | RT_BIT(10))
241/** ICR Low - The destination mode. */
242#define XAPIC_ICR_LO_DEST_MODE RT_BIT(11)
243/** ICR Low - The delivery status. */
244#define XAPIC_ICR_LO_DELIVERY_STATUS RT_BIT(12)
245/** ICR Low - The level. */
246#define XAPIC_ICR_LO_LEVEL RT_BIT(14)
247/** ICR Low - The trigger mode. */
248#define XAPIC_ICR_TRIGGER_MODE RT_BIT(15)
249/** ICR Low - The destination shorthand. */
250#define XAPIC_ICR_LO_DEST_SHORTHAND (RT_BIT(18) | RT_BIT(19))
251/** ICR Low - Valid write bits. */
252#define XAPIC_ICR_LO_WR_VALID ( XAPIC_ICR_LO_VECTOR | XAPIC_ICR_LO_DELIVERY_MODE | XAPIC_ICR_LO_DEST_MODE \
253 | XAPIC_ICR_LO_LEVEL | XAPIC_ICR_TRIGGER_MODE | XAPIC_ICR_LO_DEST_SHORTHAND)
254
255/** ICR High - The destination field. */
256#define XAPIC_ICR_HI_DEST UINT32_C(0xff000000)
257/** ICR High - Get the destination field. */
258#define XAPIC_ICR_HI_GET_DEST(a_u32IcrHi) (((a_u32IcrHi) >> 24) & XAPIC_ICR_HI_DEST)
259/** ICR High - Valid write bits in xAPIC mode. */
260#define XAPIC_ICR_HI_WR_VALID XAPIC_ICR_HI_DEST
261
262/** APIC ID broadcast mask - x2APIC mode. */
263#define X2APIC_ID_BROADCAST_MASK UINT32_C(0xffffffff)
264/** APIC ID broadcast mask - xAPIC mode for Pentium 4. */
265# define XAPIC_ID_BROADCAST_MASK_P4 UINT32_C(0xff)
266/** @todo Broadcast mask for Pentium 6. */
267
268/** Get an xAPIC page offset for an x2APIC MSR value. */
269#define X2APIC_GET_XAPIC_OFF(a_uMsr) ((((a_uMsr) - MSR_IA32_X2APIC_START) << 4) & UINT32_C(0xff0))
270/** Get an x2APIC MSR for an xAPIC page offset. */
271#define XAPIC_GET_X2APIC_MSR(a_offReg) ((((a_offReg) & UINT32_C(0xff0)) >> 4) | MSR_IA32_X2APIC_START)
272
273/** @name xAPIC and x2APIC register offsets.
274 * See Intel spec. 10.4.1 "The Local APIC Block Diagram".
275 * @{ */
276/** Offset of APIC ID Register. */
277#define XAPIC_OFF_ID 0x020
278/** Offset of APIC Version Register. */
279#define XAPIC_OFF_VERSION 0x030
280/** Offset of Task Priority Register. */
281#define XAPIC_OFF_TPR 0x080
282/** Offset of Arbitrartion Priority register. */
283#define XAPIC_OFF_APR 0x090
284/** Offset of Processor Priority register. */
285#define XAPIC_OFF_PPR 0x0A0
286/** Offset of End Of Interrupt register. */
287#define XAPIC_OFF_EOI 0x0B0
288/** Offset of Remote Read Register. */
289#define XAPIC_OFF_RRD 0x0C0
290/** Offset of Logical Destination Register. */
291#define XAPIC_OFF_LDR 0x0D0
292/** Offset of Destination Format Register. */
293#define XAPIC_OFF_DFR 0x0E0
294/** Offset of Spurious Interrupt Vector Register. */
295#define XAPIC_OFF_SVR 0x0F0
296/** Offset of In-service Register (bits 31:0). */
297#define XAPIC_OFF_ISR0 0x100
298/** Offset of In-service Register (bits 63:32). */
299#define XAPIC_OFF_ISR1 0x110
300/** Offset of In-service Register (bits 95:64). */
301#define XAPIC_OFF_ISR2 0x120
302/** Offset of In-service Register (bits 127:96). */
303#define XAPIC_OFF_ISR3 0x130
304/** Offset of In-service Register (bits 159:128). */
305#define XAPIC_OFF_ISR4 0x140
306/** Offset of In-service Register (bits 191:160). */
307#define XAPIC_OFF_ISR5 0x150
308/** Offset of In-service Register (bits 223:192). */
309#define XAPIC_OFF_ISR6 0x160
310/** Offset of In-service Register (bits 255:224). */
311#define XAPIC_OFF_ISR7 0x170
312/** Offset of Trigger Mode Register (bits 31:0). */
313#define XAPIC_OFF_TMR0 0x180
314/** Offset of Trigger Mode Register (bits 63:32). */
315#define XAPIC_OFF_TMR1 0x190
316/** Offset of Trigger Mode Register (bits 95:64). */
317#define XAPIC_OFF_TMR2 0x1A0
318/** Offset of Trigger Mode Register (bits 127:96). */
319#define XAPIC_OFF_TMR3 0x1B0
320/** Offset of Trigger Mode Register (bits 159:128). */
321#define XAPIC_OFF_TMR4 0x1C0
322/** Offset of Trigger Mode Register (bits 191:160). */
323#define XAPIC_OFF_TMR5 0x1D0
324/** Offset of Trigger Mode Register (bits 223:192). */
325#define XAPIC_OFF_TMR6 0x1E0
326/** Offset of Trigger Mode Register (bits 255:224). */
327#define XAPIC_OFF_TMR7 0x1F0
328/** Offset of Interrupt Request Register (bits 31:0). */
329#define XAPIC_OFF_IRR0 0x200
330/** Offset of Interrupt Request Register (bits 63:32). */
331#define XAPIC_OFF_IRR1 0x210
332/** Offset of Interrupt Request Register (bits 95:64). */
333#define XAPIC_OFF_IRR2 0x220
334/** Offset of Interrupt Request Register (bits 127:96). */
335#define XAPIC_OFF_IRR3 0x230
336/** Offset of Interrupt Request Register (bits 159:128). */
337#define XAPIC_OFF_IRR4 0x240
338/** Offset of Interrupt Request Register (bits 191:160). */
339#define XAPIC_OFF_IRR5 0x250
340/** Offset of Interrupt Request Register (bits 223:192). */
341#define XAPIC_OFF_IRR6 0x260
342/** Offset of Interrupt Request Register (bits 255:224). */
343#define XAPIC_OFF_IRR7 0x270
344/** Offset of Error Status Register. */
345#define XAPIC_OFF_ESR 0x280
346/** Offset of LVT CMCI Register. */
347#define XAPIC_OFF_LVT_CMCI 0x2F0
348/** Offset of Interrupt Command Register - Lo. */
349#define XAPIC_OFF_ICR_LO 0x300
350/** Offset of Interrupt Command Register - Hi. */
351#define XAPIC_OFF_ICR_HI 0x310
352/** Offset of LVT Timer Register. */
353#define XAPIC_OFF_LVT_TIMER 0x320
354/** Offset of LVT Thermal Sensor Register. */
355#define XAPIC_OFF_LVT_THERMAL 0x330
356/** Offset of LVT Performance Counter Register. */
357#define XAPIC_OFF_LVT_PERF 0x340
358/** Offset of LVT LINT0 Register. */
359#define XAPIC_OFF_LVT_LINT0 0x350
360/** Offset of LVT LINT1 Register. */
361#define XAPIC_OFF_LVT_LINT1 0x360
362/** Offset of LVT Error Register . */
363#define XAPIC_OFF_LVT_ERROR 0x370
364/** Offset of Timer Initial Count Register. */
365#define XAPIC_OFF_TIMER_ICR 0x380
366/** Offset of Timer Current Count Register. */
367#define XAPIC_OFF_TIMER_CCR 0x390
368/** Offset of Timer Divide Configuration Register. */
369#define XAPIC_OFF_TIMER_DCR 0x3E0
370/** Offset of Self-IPI Register (x2APIC only). */
371#define X2APIC_OFF_SELF_IPI 0x3F0
372
373/** Offset of LVT range start. */
374#define XAPIC_OFF_LVT_START XAPIC_OFF_LVT_TIMER
375/** Offset of LVT range end (inclusive). */
376#define XAPIC_OFF_LVT_END XAPIC_OFF_LVT_ERROR
377/** Offset of LVT extended range start. */
378#define XAPIC_OFF_LVT_EXT_START XAPIC_OFF_LVT_CMCI
379/** Offset of LVT extended range end (inclusive). */
380#define XAPIC_OFF_LVT_EXT_END XAPIC_OFF_LVT_CMCI
381/** Offset of the last register (incl. reserved) in the xAPIC/x2APIC range. */
382#define XAPIC_OFF_END 0x3F0
383/** @} */
384
385/** @name xAPIC Destination Format Register bits.
386 * See Intel spec. 10.6.2.2 "Logical Destination Mode".
387 * @{ */
388typedef enum XAPICDESTFORMAT
389{
390 XAPICDESTFORMAT_FLAT = 0xf,
391 XAPICDESTFORMAT_CLUSTER = 0
392} XAPICDESTFORMAT;
393/** @} */
394
395/** @name xAPIC Timer Mode bits.
396 * See Intel spec. 10.5.1 "Local Vector Table".
397 * @{ */
398typedef enum XAPICTIMERMODE
399{
400 XAPICTIMERMODE_ONESHOT = XAPIC_TIMER_MODE_ONESHOT,
401 XAPICTIMERMODE_PERIODIC = XAPIC_TIMER_MODE_PERIODIC,
402 XAPICTIMERMODE_TSC_DEADLINE = XAPIC_TIMER_MODE_TSC_DEADLINE
403} XAPICTIMERMODE;
404/** @} */
405
406/** @name xAPIC Interrupt Command Register bits.
407 * See Intel spec. 10.6.1 "Interrupt Command Register (ICR)".
408 * See Intel spec. 10.5.1 "Local Vector Table".
409 * @{ */
410/**
411 * xAPIC destination shorthand.
412 */
413typedef enum XAPICDESTSHORTHAND
414{
415 XAPICDESTSHORTHAND_NONE = 0,
416 XAPICDESTSHORTHAND_SELF,
417 XAPIDDESTSHORTHAND_ALL_INCL_SELF,
418 XAPICDESTSHORTHAND_ALL_EXCL_SELF
419} XAPICDESTSHORTHAND;
420
421/**
422 * xAPIC INIT level de-assert delivery mode.
423 */
424typedef enum XAPICINITLEVEL
425{
426 XAPICINITLEVEL_DEASSERT = 0,
427 XAPICINITLEVEL_ASSERT
428} XAPICLEVEL;
429
430/**
431 * xAPIC destination mode.
432 */
433typedef enum XAPICDESTMODE
434{
435 XAPICDESTMODE_PHYSICAL = 0,
436 XAPICDESTMODE_LOGICAL
437} XAPICDESTMODE;
438
439/**
440 * xAPIC delivery mode type.
441 */
442typedef enum XAPICDELIVERYMODE
443{
444 XAPICDELIVERYMODE_FIXED = 0,
445 XAPICDELIVERYMODE_LOWEST_PRIO = 1,
446 XAPICDELIVERYMODE_SMI = 2,
447 XAPICDELIVERYMODE_NMI = 4,
448 XAPICDELIVERYMODE_INIT = 5,
449 XAPICDELIVERYMODE_STARTUP = 6,
450 XAPICDELIVERYMODE_EXTINT = 7
451} XAPICDELIVERYMODE;
452
453/**
454 * xAPIC trigger mode.
455 */
456typedef enum XAPICTRIGGERMODE
457{
458 XAPICTRIGGERMODE_EDGE = 0,
459 XAPICTRIGGERMODE_LEVEL
460} XAPICTRIGGERMODE;
461/** @} */
462
463
464DECLINLINE(uint32_t) ApicRegRead(void *pvBase, uint32_t offReg)
465{
466 return *(const volatile uint32_t *)((uintptr_t)pvBase + offReg);
467}
468
469
470#ifdef IPRT_INCLUDED_asm_amd64_x86_h
471/**
472 * Reads an X2APIC register.
473 *
474 * @param offReg MMIO offset, APIC_REG_XXX.
475 */
476DECLINLINE(uint32_t) ApicX2RegRead32(uint32_t offReg)
477{
478 return ASMRdMsr((offReg >> 4) + MSR_IA32_X2APIC_START);
479}
480#endif
481
482#endif /* !VBOX_INCLUDED_apic_h */
483
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