VirtualBox

source: vbox/trunk/include/VBox/cpum.h@ 10273

Last change on this file since 10273 was 9987, checked in by vboxsync, 16 years ago

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1/** @file
2 * CPUM - CPU Monitor(/ Manager).
3 */
4
5/*
6 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * The contents of this file may alternatively be used under the terms
17 * of the Common Development and Distribution License Version 1.0
18 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19 * VirtualBox OSE distribution, in which case the provisions of the
20 * CDDL are applicable instead of those of the GPL.
21 *
22 * You may elect to license modified versions of this file under the
23 * terms and conditions of either the GPL or the CDDL or both.
24 *
25 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
26 * Clara, CA 95054 USA or visit http://www.sun.com if you need
27 * additional information or have any questions.
28 */
29
30#ifndef ___VBox_cpum_h
31#define ___VBox_cpum_h
32
33#include <VBox/cdefs.h>
34#include <VBox/types.h>
35#include <VBox/x86.h>
36
37
38__BEGIN_DECLS
39
40/** @defgroup grp_cpum The CPU Monitor(/Manager) API
41 * @{
42 */
43
44/**
45 * Selector hidden registers.
46 */
47typedef struct CPUMSELREGHID
48{
49 /** Base register.
50 *
51 * Long mode remarks:
52 * - Unused in long mode for CS, DS, ES, SS
53 * - 32 bits for FS & GS; FS(GS)_BASE msr used for the base address
54 * - 64 bits for TR & LDTR
55 */
56 uint64_t u64Base;
57 /** Limit (expanded). */
58 uint32_t u32Limit;
59 /** Flags.
60 * This is the high 32-bit word of the descriptor entry.
61 * Only the flags, dpl and type are used. */
62 X86DESCATTR Attr;
63} CPUMSELREGHID;
64
65
66/**
67 * The sysenter register set.
68 */
69typedef struct CPUMSYSENTER
70{
71 /** Ring 0 cs.
72 * This value + 8 is the Ring 0 ss.
73 * This value + 16 is the Ring 3 cs.
74 * This value + 24 is the Ring 3 ss.
75 */
76 uint64_t cs;
77 /** Ring 0 eip. */
78 uint64_t eip;
79 /** Ring 0 esp. */
80 uint64_t esp;
81} CPUMSYSENTER;
82
83
84/**
85 * CPU context core.
86 */
87#pragma pack(1)
88typedef struct CPUMCTXCORE
89{
90 union
91 {
92 uint32_t edi;
93 uint64_t rdi;
94 };
95 union
96 {
97 uint32_t esi;
98 uint64_t rsi;
99 };
100 union
101 {
102 uint32_t ebp;
103 uint64_t rbp;
104 };
105 union
106 {
107 uint32_t eax;
108 uint64_t rax;
109 };
110 union
111 {
112 uint32_t ebx;
113 uint64_t rbx;
114 };
115 union
116 {
117 uint32_t edx;
118 uint64_t rdx;
119 };
120 union
121 {
122 uint32_t ecx;
123 uint64_t rcx;
124 };
125 union
126 {
127 uint32_t esp;
128 uint64_t rsp;
129 };
130 /* Note: lss esp, [] in the switcher needs some space, so we reserve it here instead of relying on the exact esp & ss layout as before. */
131 uint32_t lss_esp;
132 RTSEL ss;
133 RTSEL ssPadding;
134
135 RTSEL gs;
136 RTSEL gsPadding;
137 RTSEL fs;
138 RTSEL fsPadding;
139 RTSEL es;
140 RTSEL esPadding;
141 RTSEL ds;
142 RTSEL dsPadding;
143 RTSEL cs;
144 RTSEL csPadding[3]; /* 3 words to force 8 byte alignment for the remainder */
145
146 union
147 {
148 X86EFLAGS eflags;
149 X86RFLAGS rflags;
150 };
151 union
152 {
153 uint32_t eip;
154 uint64_t rip;
155 };
156
157 uint64_t r8;
158 uint64_t r9;
159 uint64_t r10;
160 uint64_t r11;
161 uint64_t r12;
162 uint64_t r13;
163 uint64_t r14;
164 uint64_t r15;
165
166 /** Hidden selector registers.
167 * @{ */
168 CPUMSELREGHID esHid;
169 CPUMSELREGHID csHid;
170 CPUMSELREGHID ssHid;
171 CPUMSELREGHID dsHid;
172 CPUMSELREGHID fsHid;
173 CPUMSELREGHID gsHid;
174 /** @} */
175
176} CPUMCTXCORE;
177#pragma pack()
178
179
180/**
181 * CPU context.
182 */
183#pragma pack(1)
184typedef struct CPUMCTX
185{
186 /** FPU state. (16-byte alignment)
187 * @todo This doesn't have to be in X86FXSTATE on CPUs without fxsr - we need a type for the
188 * actual format or convert it (waste of time). */
189 X86FXSTATE fpu;
190
191 /** CPUMCTXCORE Part.
192 * @{ */
193 union
194 {
195 uint32_t edi;
196 uint64_t rdi;
197 };
198 union
199 {
200 uint32_t esi;
201 uint64_t rsi;
202 };
203 union
204 {
205 uint32_t ebp;
206 uint64_t rbp;
207 };
208 union
209 {
210 uint32_t eax;
211 uint64_t rax;
212 };
213 union
214 {
215 uint32_t ebx;
216 uint64_t rbx;
217 };
218 union
219 {
220 uint32_t edx;
221 uint64_t rdx;
222 };
223 union
224 {
225 uint32_t ecx;
226 uint64_t rcx;
227 };
228 union
229 {
230 uint32_t esp;
231 uint64_t rsp;
232 };
233 /* Note: lss esp, [] in the switcher needs some space, so we reserve it here instead of relying on the exact esp & ss layout as before (prevented us from using a union with rsp). */
234 uint32_t lss_esp;
235 RTSEL ss;
236 RTSEL ssPadding;
237
238 RTSEL gs;
239 RTSEL gsPadding;
240 RTSEL fs;
241 RTSEL fsPadding;
242 RTSEL es;
243 RTSEL esPadding;
244 RTSEL ds;
245 RTSEL dsPadding;
246 RTSEL cs;
247 RTSEL csPadding[3]; /* 3 words to force 8 byte alignment for the remainder */
248
249 union
250 {
251 X86EFLAGS eflags;
252 X86RFLAGS rflags;
253 };
254 union
255 {
256 uint32_t eip;
257 uint64_t rip;
258 };
259
260 uint64_t r8;
261 uint64_t r9;
262 uint64_t r10;
263 uint64_t r11;
264 uint64_t r12;
265 uint64_t r13;
266 uint64_t r14;
267 uint64_t r15;
268
269 /** Hidden selector registers.
270 * @{ */
271 CPUMSELREGHID esHid;
272 CPUMSELREGHID csHid;
273 CPUMSELREGHID ssHid;
274 CPUMSELREGHID dsHid;
275 CPUMSELREGHID fsHid;
276 CPUMSELREGHID gsHid;
277 /** @} */
278
279 /** @} */
280
281 /** Control registers.
282 * @{ */
283 uint64_t cr0;
284 uint64_t cr2;
285 uint64_t cr3;
286 uint64_t cr4;
287 uint64_t cr8;
288 /** @} */
289
290 /** Debug registers.
291 * @{ */
292 uint64_t dr0;
293 uint64_t dr1;
294 uint64_t dr2;
295 uint64_t dr3;
296 uint64_t dr4; /**< @todo remove dr4 and dr5. */
297 uint64_t dr5;
298 uint64_t dr6;
299 uint64_t dr7;
300 /* DR8-15 are currently not supported */
301 /** @} */
302
303 /** Global Descriptor Table register. */
304 VBOXGDTR gdtr;
305 uint16_t gdtrPadding;
306 /** Interrupt Descriptor Table register. */
307 VBOXIDTR idtr;
308 uint16_t idtrPadding;
309 /** The task register.
310 * Only the guest context uses all the members. */
311 RTSEL ldtr;
312 RTSEL ldtrPadding;
313 /** The task register.
314 * Only the guest context uses all the members. */
315 RTSEL tr;
316 RTSEL trPadding;
317
318 /** The sysenter msr registers.
319 * This member is not used by the hypervisor context. */
320 CPUMSYSENTER SysEnter;
321
322 /** System MSRs.
323 * @{ */
324 uint64_t msrEFER;
325 uint64_t msrSTAR; /* legacy syscall eip, cs & ss */
326 uint64_t msrPAT;
327 uint64_t msrLSTAR; /* 64 bits mode syscall rip */
328 uint64_t msrCSTAR; /* compatibility mode syscall rip */
329 uint64_t msrSFMASK; /* syscall flag mask */
330 uint64_t msrKERNELGSBASE;/* swapgs exchange value */
331 /** @} */
332
333 /** Hidden selector registers.
334 * @{ */
335 CPUMSELREGHID ldtrHid;
336 CPUMSELREGHID trHid;
337 /** @} */
338
339 /* padding to get 32byte aligned size */
340 uint32_t padding[6];
341} CPUMCTX;
342#pragma pack()
343
344/**
345 * Gets the CPUMCTXCORE part of a CPUMCTX.
346 */
347#define CPUMCTX2CORE(pCtx) ((PCPUMCTXCORE)(void *)&(pCtx)->edi)
348
349/**
350 * The register set returned by a CPUID operation.
351 */
352typedef struct CPUMCPUID
353{
354 uint32_t eax;
355 uint32_t ebx;
356 uint32_t ecx;
357 uint32_t edx;
358} CPUMCPUID;
359/** Pointer to a CPUID leaf. */
360typedef CPUMCPUID *PCPUMCPUID;
361/** Pointer to a const CPUID leaf. */
362typedef const CPUMCPUID *PCCPUMCPUID;
363
364/**
365 * CPUID feature to set or clear.
366 */
367typedef enum CPUMCPUIDFEATURE
368{
369 CPUMCPUIDFEATURE_INVALID = 0,
370 /** The APIC feature bit. (Std+Ext) */
371 CPUMCPUIDFEATURE_APIC,
372 /** The sysenter/sysexit feature bit. (Std) */
373 CPUMCPUIDFEATURE_SEP,
374 /** The SYSCALL/SYSEXIT feature bit (64 bits mode only for Intel CPUs). (Ext) */
375 CPUMCPUIDFEATURE_SYSCALL,
376 /** The PAE feature bit. (Std+Ext) */
377 CPUMCPUIDFEATURE_PAE,
378 /** The NXE feature bit. (Ext) */
379 CPUMCPUIDFEATURE_NXE,
380 /** The LAHF/SAHF feature bit (64 bits mode only). (Ext) */
381 CPUMCPUIDFEATURE_LAHF,
382 /** The LONG MODE feature bit. (Ext) */
383 CPUMCPUIDFEATURE_LONG_MODE
384} CPUMCPUIDFEATURE;
385
386/*
387 * CPU Vendor.
388 */
389typedef enum CPUMCPUVENDOR
390{
391 CPUMCPUVENDOR_INVALID = 0,
392 CPUMCPUVENDOR_INTEL,
393 CPUMCPUVENDOR_AMD,
394 CPUMCPUVENDOR_VIA,
395 CPUMCPUVENDOR_UNKNOWN,
396 /** 32bit hackishness. */
397 CPUMCPUVENDOR_32BIT_HACK = 0x7fffffff
398} CPUMCPUVENDOR;
399
400
401/** @name Guest Register Getters.
402 * @{ */
403CPUMDECL(void) CPUMGetGuestGDTR(PVM pVM, PVBOXGDTR pGDTR);
404CPUMDECL(RTGCPTR) CPUMGetGuestIDTR(PVM pVM, uint16_t *pcbLimit);
405CPUMDECL(RTSEL) CPUMGetGuestTR(PVM pVM);
406CPUMDECL(RTSEL) CPUMGetGuestLDTR(PVM pVM);
407CPUMDECL(uint64_t) CPUMGetGuestCR0(PVM pVM);
408CPUMDECL(uint64_t) CPUMGetGuestCR2(PVM pVM);
409CPUMDECL(uint64_t) CPUMGetGuestCR3(PVM pVM);
410CPUMDECL(uint64_t) CPUMGetGuestCR4(PVM pVM);
411CPUMDECL(int) CPUMGetGuestCRx(PVM pVM, unsigned iReg, uint64_t *pValue);
412CPUMDECL(uint32_t) CPUMGetGuestEFlags(PVM pVM);
413CPUMDECL(uint32_t) CPUMGetGuestEIP(PVM pVM);
414CPUMDECL(uint64_t) CPUMGetGuestRIP(PVM pVM);
415CPUMDECL(uint32_t) CPUMGetGuestEAX(PVM pVM);
416CPUMDECL(uint32_t) CPUMGetGuestEBX(PVM pVM);
417CPUMDECL(uint32_t) CPUMGetGuestECX(PVM pVM);
418CPUMDECL(uint32_t) CPUMGetGuestEDX(PVM pVM);
419CPUMDECL(uint32_t) CPUMGetGuestESI(PVM pVM);
420CPUMDECL(uint32_t) CPUMGetGuestEDI(PVM pVM);
421CPUMDECL(uint32_t) CPUMGetGuestESP(PVM pVM);
422CPUMDECL(uint32_t) CPUMGetGuestEBP(PVM pVM);
423CPUMDECL(RTSEL) CPUMGetGuestCS(PVM pVM);
424CPUMDECL(RTSEL) CPUMGetGuestDS(PVM pVM);
425CPUMDECL(RTSEL) CPUMGetGuestES(PVM pVM);
426CPUMDECL(RTSEL) CPUMGetGuestFS(PVM pVM);
427CPUMDECL(RTSEL) CPUMGetGuestGS(PVM pVM);
428CPUMDECL(RTSEL) CPUMGetGuestSS(PVM pVM);
429CPUMDECL(uint64_t) CPUMGetGuestDR0(PVM pVM);
430CPUMDECL(uint64_t) CPUMGetGuestDR1(PVM pVM);
431CPUMDECL(uint64_t) CPUMGetGuestDR2(PVM pVM);
432CPUMDECL(uint64_t) CPUMGetGuestDR3(PVM pVM);
433CPUMDECL(uint64_t) CPUMGetGuestDR6(PVM pVM);
434CPUMDECL(uint64_t) CPUMGetGuestDR7(PVM pVM);
435CPUMDECL(int) CPUMGetGuestDRx(PVM pVM, uint32_t iReg, uint64_t *pValue);
436CPUMDECL(void) CPUMGetGuestCpuId(PVM pVM, uint32_t iLeaf, uint32_t *pEax, uint32_t *pEbx, uint32_t *pEcx, uint32_t *pEdx);
437CPUMDECL(RCPTRTYPE(PCCPUMCPUID)) CPUMGetGuestCpuIdStdGCPtr(PVM pVM);
438CPUMDECL(RCPTRTYPE(PCCPUMCPUID)) CPUMGetGuestCpuIdExtGCPtr(PVM pVM);
439CPUMDECL(RCPTRTYPE(PCCPUMCPUID)) CPUMGetGuestCpuIdCentaurGCPtr(PVM pVM);
440CPUMDECL(RCPTRTYPE(PCCPUMCPUID)) CPUMGetGuestCpuIdDefGCPtr(PVM pVM);
441CPUMDECL(uint32_t) CPUMGetGuestCpuIdStdMax(PVM pVM);
442CPUMDECL(uint32_t) CPUMGetGuestCpuIdExtMax(PVM pVM);
443CPUMDECL(uint32_t) CPUMGetGuestCpuIdCentaurMax(PVM pVM);
444CPUMDECL(CPUMSELREGHID *) CPUMGetGuestTRHid(PVM pVM);
445CPUMDECL(uint64_t) CPUMGetGuestEFER(PVM pVM);
446CPUMDECL(uint64_t) CPUMGetGuestMsr(PVM pVM, unsigned idMsr);
447/** @} */
448
449/** @name Guest Register Setters.
450 * @{ */
451CPUMDECL(int) CPUMSetGuestGDTR(PVM pVM, uint32_t addr, uint16_t limit);
452CPUMDECL(int) CPUMSetGuestIDTR(PVM pVM, uint32_t addr, uint16_t limit);
453CPUMDECL(int) CPUMSetGuestTR(PVM pVM, uint16_t tr);
454CPUMDECL(int) CPUMSetGuestLDTR(PVM pVM, uint16_t ldtr);
455CPUMDECL(int) CPUMSetGuestCR0(PVM pVM, uint64_t cr0);
456CPUMDECL(int) CPUMSetGuestCR2(PVM pVM, uint64_t cr2);
457CPUMDECL(int) CPUMSetGuestCR3(PVM pVM, uint64_t cr3);
458CPUMDECL(int) CPUMSetGuestCR4(PVM pVM, uint64_t cr4);
459CPUMDECL(int) CPUMSetGuestDR0(PVM pVM, uint64_t uDr0);
460CPUMDECL(int) CPUMSetGuestDR1(PVM pVM, uint64_t uDr1);
461CPUMDECL(int) CPUMSetGuestDR2(PVM pVM, uint64_t uDr2);
462CPUMDECL(int) CPUMSetGuestDR3(PVM pVM, uint64_t uDr3);
463CPUMDECL(int) CPUMSetGuestDR6(PVM pVM, uint64_t uDr6);
464CPUMDECL(int) CPUMSetGuestDR7(PVM pVM, uint64_t uDr7);
465CPUMDECL(int) CPUMSetGuestDRx(PVM pVM, uint32_t iReg, uint64_t Value);
466CPUMDECL(int) CPUMSetGuestEFlags(PVM pVM, uint32_t eflags);
467CPUMDECL(int) CPUMSetGuestEIP(PVM pVM, uint32_t eip);
468CPUMDECL(int) CPUMSetGuestEAX(PVM pVM, uint32_t eax);
469CPUMDECL(int) CPUMSetGuestEBX(PVM pVM, uint32_t ebx);
470CPUMDECL(int) CPUMSetGuestECX(PVM pVM, uint32_t ecx);
471CPUMDECL(int) CPUMSetGuestEDX(PVM pVM, uint32_t edx);
472CPUMDECL(int) CPUMSetGuestESI(PVM pVM, uint32_t esi);
473CPUMDECL(int) CPUMSetGuestEDI(PVM pVM, uint32_t edi);
474CPUMDECL(int) CPUMSetGuestESP(PVM pVM, uint32_t esp);
475CPUMDECL(int) CPUMSetGuestEBP(PVM pVM, uint32_t ebp);
476CPUMDECL(int) CPUMSetGuestCS(PVM pVM, uint16_t cs);
477CPUMDECL(int) CPUMSetGuestDS(PVM pVM, uint16_t ds);
478CPUMDECL(int) CPUMSetGuestES(PVM pVM, uint16_t es);
479CPUMDECL(int) CPUMSetGuestFS(PVM pVM, uint16_t fs);
480CPUMDECL(int) CPUMSetGuestGS(PVM pVM, uint16_t gs);
481CPUMDECL(int) CPUMSetGuestSS(PVM pVM, uint16_t ss);
482CPUMDECL(void) CPUMSetGuestEFER(PVM pVM, uint64_t val);
483CPUMDECL(void) CPUMSetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature);
484CPUMDECL(void) CPUMClearGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature);
485CPUMDECL(bool) CPUMGetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature);
486CPUMDECL(void) CPUMSetGuestCtx(PVM pVM, const PCPUMCTX pCtx);
487/** @} */
488
489/** @name Misc Guest Predicate Functions.
490 * @{ */
491
492/**
493 * Tests if the guest is running in real mode or not.
494 *
495 * @returns true if in real mode, otherwise false.
496 * @param pVM The VM handle.
497 */
498DECLINLINE(bool) CPUMIsGuestInRealMode(PVM pVM)
499{
500 return !(CPUMGetGuestCR0(pVM) & X86_CR0_PE);
501}
502
503/**
504 * Tests if the guest is running in protected or not.
505 *
506 * @returns true if in protected mode, otherwise false.
507 * @param pVM The VM handle.
508 */
509DECLINLINE(bool) CPUMIsGuestInProtectedMode(PVM pVM)
510{
511 return !!(CPUMGetGuestCR0(pVM) & X86_CR0_PE);
512}
513
514/**
515 * Tests if the guest is running in paged protected or not.
516 *
517 * @returns true if in paged protected mode, otherwise false.
518 * @param pVM The VM handle.
519 */
520DECLINLINE(bool) CPUMIsGuestInPagedProtectedMode(PVM pVM)
521{
522 return (CPUMGetGuestCR0(pVM) & (X86_CR0_PE | X86_CR0_PG)) == (X86_CR0_PE | X86_CR0_PG);
523}
524
525/**
526 * Tests if the guest is running in long mode or not.
527 *
528 * @returns true if in long mode, otherwise false.
529 * @param pVM The VM handle.
530 */
531DECLINLINE(bool) CPUMIsGuestInLongMode(PVM pVM)
532{
533 return (CPUMGetGuestEFER(pVM) & MSR_K6_EFER_LMA) == MSR_K6_EFER_LMA;
534}
535
536/**
537 * Tests if the guest is running in long mode or not.
538 *
539 * @returns true if in long mode, otherwise false.
540 * @param pCtx Current CPU context
541 */
542DECLINLINE(bool) CPUMIsGuestInLongModeEx(PCPUMCTX pCtx)
543{
544 return (pCtx->msrEFER & MSR_K6_EFER_LMA) == MSR_K6_EFER_LMA;
545}
546
547/**
548 * Tests if the guest is running in 16 bits paged protected or not.
549 *
550 * @returns true if in paged protected mode, otherwise false.
551 * @param pVM The VM handle.
552 */
553CPUMDECL(bool) CPUMIsGuestIn16BitCode(PVM pVM);
554
555/**
556 * Tests if the guest is running in 32 bits paged protected or not.
557 *
558 * @returns true if in paged protected mode, otherwise false.
559 * @param pVM The VM handle.
560 */
561CPUMDECL(bool) CPUMIsGuestIn32BitCode(PVM pVM);
562
563/**
564 * Tests if the guest is running in 64 bits mode or not.
565 *
566 * @returns true if in 64 bits protected mode, otherwise false.
567 * @param pVM The VM handle.
568 * @param pCtx Current CPU context
569 */
570DECLINLINE(bool) CPUMIsGuestIn64BitCode(PVM pVM, PCCPUMCTXCORE pCtx)
571{
572 if (!CPUMIsGuestInLongMode(pVM))
573 return false;
574
575 return pCtx->csHid.Attr.n.u1Long;
576}
577
578/**
579 * Tests if the guest is running in 64 bits mode or not.
580 *
581 * @returns true if in 64 bits protected mode, otherwise false.
582 * @param pVM The VM handle.
583 * @param pCtx Current CPU context
584 */
585DECLINLINE(bool) CPUMIsGuestIn64BitCodeEx(PCCPUMCTX pCtx)
586{
587 if (!(pCtx->msrEFER & MSR_K6_EFER_LMA))
588 return false;
589
590 return pCtx->csHid.Attr.n.u1Long;
591}
592
593/**
594 * Gets the CPU vendor
595 *
596 * @returns CPU vendor
597 * @param pVM The VM handle.
598 */
599CPUMDECL(CPUMCPUVENDOR) CPUMGetCPUVendor(PVM pVM);
600
601
602/** @} */
603
604
605
606/** @name Hypervisor Register Getters.
607 * @{ */
608CPUMDECL(RTSEL) CPUMGetHyperCS(PVM pVM);
609CPUMDECL(RTSEL) CPUMGetHyperDS(PVM pVM);
610CPUMDECL(RTSEL) CPUMGetHyperES(PVM pVM);
611CPUMDECL(RTSEL) CPUMGetHyperFS(PVM pVM);
612CPUMDECL(RTSEL) CPUMGetHyperGS(PVM pVM);
613CPUMDECL(RTSEL) CPUMGetHyperSS(PVM pVM);
614#if 0 /* these are not correct. */
615CPUMDECL(uint32_t) CPUMGetHyperCR0(PVM pVM);
616CPUMDECL(uint32_t) CPUMGetHyperCR2(PVM pVM);
617CPUMDECL(uint32_t) CPUMGetHyperCR3(PVM pVM);
618CPUMDECL(uint32_t) CPUMGetHyperCR4(PVM pVM);
619#endif
620/** This register is only saved on fatal traps. */
621CPUMDECL(uint32_t) CPUMGetHyperEAX(PVM pVM);
622CPUMDECL(uint32_t) CPUMGetHyperEBX(PVM pVM);
623/** This register is only saved on fatal traps. */
624CPUMDECL(uint32_t) CPUMGetHyperECX(PVM pVM);
625/** This register is only saved on fatal traps. */
626CPUMDECL(uint32_t) CPUMGetHyperEDX(PVM pVM);
627CPUMDECL(uint32_t) CPUMGetHyperESI(PVM pVM);
628CPUMDECL(uint32_t) CPUMGetHyperEDI(PVM pVM);
629CPUMDECL(uint32_t) CPUMGetHyperEBP(PVM pVM);
630CPUMDECL(uint32_t) CPUMGetHyperESP(PVM pVM);
631CPUMDECL(uint32_t) CPUMGetHyperEFlags(PVM pVM);
632CPUMDECL(uint32_t) CPUMGetHyperEIP(PVM pVM);
633CPUMDECL(uint64_t) CPUMGetHyperRIP(PVM pVM);
634CPUMDECL(uint32_t) CPUMGetHyperIDTR(PVM pVM, uint16_t *pcbLimit);
635CPUMDECL(uint32_t) CPUMGetHyperGDTR(PVM pVM, uint16_t *pcbLimit);
636CPUMDECL(RTSEL) CPUMGetHyperLDTR(PVM pVM);
637CPUMDECL(RTGCUINTREG) CPUMGetHyperDR0(PVM pVM);
638CPUMDECL(RTGCUINTREG) CPUMGetHyperDR1(PVM pVM);
639CPUMDECL(RTGCUINTREG) CPUMGetHyperDR2(PVM pVM);
640CPUMDECL(RTGCUINTREG) CPUMGetHyperDR3(PVM pVM);
641CPUMDECL(RTGCUINTREG) CPUMGetHyperDR6(PVM pVM);
642CPUMDECL(RTGCUINTREG) CPUMGetHyperDR7(PVM pVM);
643CPUMDECL(void) CPUMGetHyperCtx(PVM pVM, PCPUMCTX pCtx);
644/** @} */
645
646/** @name Hypervisor Register Setters.
647 * @{ */
648CPUMDECL(void) CPUMSetHyperGDTR(PVM pVM, uint32_t addr, uint16_t limit);
649CPUMDECL(void) CPUMSetHyperLDTR(PVM pVM, RTSEL SelLDTR);
650CPUMDECL(void) CPUMSetHyperIDTR(PVM pVM, uint32_t addr, uint16_t limit);
651CPUMDECL(void) CPUMSetHyperCR3(PVM pVM, uint32_t cr3);
652CPUMDECL(void) CPUMSetHyperTR(PVM pVM, RTSEL SelTR);
653CPUMDECL(void) CPUMSetHyperCS(PVM pVM, RTSEL SelCS);
654CPUMDECL(void) CPUMSetHyperDS(PVM pVM, RTSEL SelDS);
655CPUMDECL(void) CPUMSetHyperES(PVM pVM, RTSEL SelDS);
656CPUMDECL(void) CPUMSetHyperFS(PVM pVM, RTSEL SelDS);
657CPUMDECL(void) CPUMSetHyperGS(PVM pVM, RTSEL SelDS);
658CPUMDECL(void) CPUMSetHyperSS(PVM pVM, RTSEL SelSS);
659CPUMDECL(void) CPUMSetHyperESP(PVM pVM, uint32_t u32ESP);
660CPUMDECL(int) CPUMSetHyperEFlags(PVM pVM, uint32_t Efl);
661CPUMDECL(void) CPUMSetHyperEIP(PVM pVM, uint32_t u32EIP);
662CPUMDECL(void) CPUMSetHyperDR0(PVM pVM, RTGCUINTREG uDr0);
663CPUMDECL(void) CPUMSetHyperDR1(PVM pVM, RTGCUINTREG uDr1);
664CPUMDECL(void) CPUMSetHyperDR2(PVM pVM, RTGCUINTREG uDr2);
665CPUMDECL(void) CPUMSetHyperDR3(PVM pVM, RTGCUINTREG uDr3);
666CPUMDECL(void) CPUMSetHyperDR6(PVM pVM, RTGCUINTREG uDr6);
667CPUMDECL(void) CPUMSetHyperDR7(PVM pVM, RTGCUINTREG uDr7);
668CPUMDECL(void) CPUMSetHyperCtx(PVM pVM, const PCPUMCTX pCtx);
669CPUMDECL(int) CPUMRecalcHyperDRx(PVM pVM);
670/** @} */
671
672CPUMDECL(void) CPUMPushHyper(PVM pVM, uint32_t u32);
673
674/**
675 * Sets or resets an alternative hypervisor context core.
676 *
677 * This is called when we get a hypervisor trap set switch the context
678 * core with the trap frame on the stack. It is called again to reset
679 * back to the default context core when resuming hypervisor execution.
680 *
681 * @param pVM The VM handle.
682 * @param pCtxCore Pointer to the alternative context core or NULL
683 * to go back to the default context core.
684 */
685CPUMDECL(void) CPUMHyperSetCtxCore(PVM pVM, PCPUMCTXCORE pCtxCore);
686
687
688/**
689 * Queries the pointer to the internal CPUMCTX structure
690 *
691 * @returns VBox status code.
692 * @param pVM Handle to the virtual machine.
693 * @param ppCtx Receives the CPUMCTX pointer when successful.
694 */
695CPUMDECL(int) CPUMQueryGuestCtxPtr(PVM pVM, PCPUMCTX *ppCtx);
696
697/**
698 * Queries the pointer to the internal CPUMCTX structure for the hypervisor.
699 *
700 * @returns VBox status code.
701 * @param pVM Handle to the virtual machine.
702 * @param ppCtx Receives the hyper CPUMCTX pointer when successful.
703 */
704CPUMDECL(int) CPUMQueryHyperCtxPtr(PVM pVM, PCPUMCTX *ppCtx);
705
706
707/**
708 * Gets the pointer to the internal CPUMCTXCORE structure.
709 * This is only for reading in order to save a few calls.
710 *
711 * @param pVM Handle to the virtual machine.
712 */
713CPUMDECL(PCCPUMCTXCORE) CPUMGetGuestCtxCore(PVM pVM);
714
715/**
716 * Gets the pointer to the internal CPUMCTXCORE structure for the hypervisor.
717 * This is only for reading in order to save a few calls.
718 *
719 * @param pVM Handle to the virtual machine.
720 */
721CPUMDECL(PCCPUMCTXCORE) CPUMGetHyperCtxCore(PVM pVM);
722
723/**
724 * Sets the guest context core registers.
725 *
726 * @param pVM Handle to the virtual machine.
727 * @param pCtxCore The new context core values.
728 */
729CPUMDECL(void) CPUMSetGuestCtxCore(PVM pVM, PCCPUMCTXCORE pCtxCore);
730
731
732/**
733 * Transforms the guest CPU state to raw-ring mode.
734 *
735 * This function will change the any of the cs and ss register with DPL=0 to DPL=1.
736 *
737 * @returns VBox status. (recompiler failure)
738 * @param pVM VM handle.
739 * @param pCtxCore The context core (for trap usage).
740 * @see @ref pg_raw
741 */
742CPUMDECL(int) CPUMRawEnter(PVM pVM, PCPUMCTXCORE pCtxCore);
743
744/**
745 * Transforms the guest CPU state from raw-ring mode to correct values.
746 *
747 * This function will change any selector registers with DPL=1 to DPL=0.
748 *
749 * @returns Adjusted rc.
750 * @param pVM VM handle.
751 * @param rc Raw mode return code
752 * @param pCtxCore The context core (for trap usage).
753 * @see @ref pg_raw
754 */
755CPUMDECL(int) CPUMRawLeave(PVM pVM, PCPUMCTXCORE pCtxCore, int rc);
756
757/**
758 * Gets the EFLAGS while we're in raw-mode.
759 *
760 * @returns The eflags.
761 * @param pVM The VM handle.
762 * @param pCtxCore The context core.
763 */
764CPUMDECL(uint32_t) CPUMRawGetEFlags(PVM pVM, PCPUMCTXCORE pCtxCore);
765
766/**
767 * Updates the EFLAGS while we're in raw-mode.
768 *
769 * @param pVM The VM handle.
770 * @param pCtxCore The context core.
771 * @param eflags The new EFLAGS value.
772 */
773CPUMDECL(void) CPUMRawSetEFlags(PVM pVM, PCPUMCTXCORE pCtxCore, uint32_t eflags);
774
775/**
776 * Lazily sync in the FPU/XMM state
777 *
778 * This function will change any selector registers with DPL=1 to DPL=0.
779 *
780 * @returns VBox status code.
781 * @param pVM VM handle.
782 */
783CPUMDECL(int) CPUMHandleLazyFPU(PVM pVM);
784
785
786/**
787 * Restore host FPU/XMM state
788 *
789 * @returns VBox status code.
790 * @param pVM VM handle.
791 */
792CPUMDECL(int) CPUMRestoreHostFPUState(PVM pVM);
793
794/** @name Changed flags
795 * These flags are used to keep track of which important register that
796 * have been changed since last they were reset. The only one allowed
797 * to clear them is REM!
798 * @{
799 */
800#define CPUM_CHANGED_FPU_REM RT_BIT(0)
801#define CPUM_CHANGED_CR0 RT_BIT(1)
802#define CPUM_CHANGED_CR4 RT_BIT(2)
803#define CPUM_CHANGED_GLOBAL_TLB_FLUSH RT_BIT(3)
804#define CPUM_CHANGED_CR3 RT_BIT(4)
805#define CPUM_CHANGED_GDTR RT_BIT(5)
806#define CPUM_CHANGED_IDTR RT_BIT(6)
807#define CPUM_CHANGED_LDTR RT_BIT(7)
808#define CPUM_CHANGED_TR RT_BIT(8)
809#define CPUM_CHANGED_SYSENTER_MSR RT_BIT(9)
810#define CPUM_CHANGED_HIDDEN_SEL_REGS RT_BIT(10)
811#define CPUM_CHANGED_CPUID RT_BIT(11)
812/** @} */
813
814/**
815 * Gets and resets the changed flags (CPUM_CHANGED_*).
816 *
817 * @returns The changed flags.
818 * @param pVM VM handle.
819 */
820CPUMDECL(unsigned) CPUMGetAndClearChangedFlagsREM(PVM pVM);
821
822/**
823 * Sets the specified changed flags (CPUM_CHANGED_*).
824 *
825 * @param pVM The VM handle.
826 */
827CPUMDECL(void) CPUMSetChangedFlags(PVM pVM, uint32_t fChangedFlags);
828
829/**
830 * Checks if the CPU supports the FXSAVE and FXRSTOR instruction.
831 * @returns true if supported.
832 * @returns false if not supported.
833 * @param pVM The VM handle.
834 */
835CPUMDECL(bool) CPUMSupportsFXSR(PVM pVM);
836
837/**
838 * Checks if the host OS uses the SYSENTER / SYSEXIT instructions.
839 * @returns true if used.
840 * @returns false if not used.
841 * @param pVM The VM handle.
842 */
843CPUMDECL(bool) CPUMIsHostUsingSysEnter(PVM pVM);
844
845/**
846 * Checks if the host OS uses the SYSCALL / SYSRET instructions.
847 * @returns true if used.
848 * @returns false if not used.
849 * @param pVM The VM handle.
850 */
851CPUMDECL(bool) CPUMIsHostUsingSysCall(PVM pVM);
852
853/**
854 * Checks if we activated the FPU/XMM state of the guest OS
855 * @returns true if we did.
856 * @returns false if not.
857 * @param pVM The VM handle.
858 */
859CPUMDECL(bool) CPUMIsGuestFPUStateActive(PVM pVM);
860
861/**
862 * Deactivate the FPU/XMM state of the guest OS
863 * @param pVM The VM handle.
864 */
865CPUMDECL(void) CPUMDeactivateGuestFPUState(PVM pVM);
866
867
868/**
869 * Checks if the hidden selector registers are valid
870 * @returns true if they are.
871 * @returns false if not.
872 * @param pVM The VM handle.
873 */
874CPUMDECL(bool) CPUMAreHiddenSelRegsValid(PVM pVM);
875
876/**
877 * Checks if the hidden selector registers are valid
878 * @param pVM The VM handle.
879 * @param fValid Valid or not
880 */
881CPUMDECL(void) CPUMSetHiddenSelRegsValid(PVM pVM, bool fValid);
882
883/**
884 * Get the current privilege level of the guest.
885 *
886 * @returns cpl
887 * @param pVM VM Handle.
888 * @param pRegFrame Trap register frame.
889 */
890CPUMDECL(uint32_t) CPUMGetGuestCPL(PVM pVM, PCPUMCTXCORE pCtxCore);
891
892/**
893 * CPU modes.
894 */
895typedef enum CPUMMODE
896{
897 /** The usual invalid zero entry. */
898 CPUMMODE_INVALID = 0,
899 /** Real mode. */
900 CPUMMODE_REAL,
901 /** Protected mode (32-bit). */
902 CPUMMODE_PROTECTED,
903 /** Long mode (64-bit). */
904 CPUMMODE_LONG
905} CPUMMODE;
906
907/**
908 * Gets the current guest CPU mode.
909 *
910 * If paging mode is what you need, check out PGMGetGuestMode().
911 *
912 * @returns The CPU mode.
913 * @param pVM The VM handle.
914 */
915CPUMDECL(CPUMMODE) CPUMGetGuestMode(PVM pVM);
916
917
918#ifdef IN_RING3
919/** @defgroup grp_cpum_r3 The CPU Monitor(/Manager) API
920 * @ingroup grp_cpum
921 * @{
922 */
923
924/**
925 * Initializes the CPUM.
926 *
927 * @returns VBox status code.
928 * @param pVM The VM to operate on.
929 */
930CPUMR3DECL(int) CPUMR3Init(PVM pVM);
931
932/**
933 * Applies relocations to data and code managed by this
934 * component. This function will be called at init and
935 * whenever the VMM need to relocate it self inside the GC.
936 *
937 * The CPUM will update the addresses used by the switcher.
938 *
939 * @param pVM The VM.
940 */
941CPUMR3DECL(void) CPUMR3Relocate(PVM pVM);
942
943/**
944 * Terminates the CPUM.
945 *
946 * Termination means cleaning up and freeing all resources,
947 * the VM it self is at this point powered off or suspended.
948 *
949 * @returns VBox status code.
950 * @param pVM The VM to operate on.
951 */
952CPUMR3DECL(int) CPUMR3Term(PVM pVM);
953
954/**
955 * Resets the CPU.
956 *
957 * @param pVM The VM handle.
958 */
959CPUMR3DECL(void) CPUMR3Reset(PVM pVM);
960
961/**
962 * Queries the pointer to the internal CPUMCTX structure
963 *
964 * @returns VBox status code.
965 * @param pVM Handle to the virtual machine.
966 * @param ppCtx Receives the CPUMCTX GC pointer when successful.
967 */
968CPUMR3DECL(int) CPUMR3QueryGuestCtxGCPtr(PVM pVM, RCPTRTYPE(PCPUMCTX) *ppCtx);
969
970
971#ifdef DEBUG
972/**
973 * Debug helper - Saves guest context on raw mode entry (for fatal dump)
974 *
975 * @internal
976 */
977CPUMR3DECL(void) CPUMR3SaveEntryCtx(PVM pVM);
978#endif
979
980/**
981 * API for controlling a few of the CPU features found in CR4.
982 *
983 * Currently only X86_CR4_TSD is accepted as input.
984 *
985 * @returns VBox status code.
986 *
987 * @param pVM The VM handle.
988 * @param fOr The CR4 OR mask.
989 * @param fAnd The CR4 AND mask.
990 */
991CPUMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd);
992
993/** @} */
994#endif
995
996#ifdef IN_GC
997/** @defgroup grp_cpum_gc The CPU Monitor(/Manager) API
998 * @ingroup grp_cpum
999 * @{
1000 */
1001
1002/**
1003 * Calls a guest trap/interrupt handler directly
1004 * Assumes a trap stack frame has already been setup on the guest's stack!
1005 *
1006 * @param pRegFrame Original trap/interrupt context
1007 * @param selCS Code selector of handler
1008 * @param pHandler GC virtual address of handler
1009 * @param eflags Callee's EFLAGS
1010 * @param selSS Stack selector for handler
1011 * @param pEsp Stack address for handler
1012 *
1013 * This function does not return!
1014 *
1015 */
1016DECLASM(void) CPUMGCCallGuestTrapHandler(PCPUMCTXCORE pRegFrame, uint32_t selCS, RTRCPTR pHandler, uint32_t eflags, uint32_t selSS, RTRCPTR pEsp);
1017
1018/**
1019 * Performs an iret to V86 code
1020 * Assumes a trap stack frame has already been setup on the guest's stack!
1021 *
1022 * @param pRegFrame Original trap/interrupt context
1023 *
1024 * This function does not return!
1025 */
1026CPUMGCDECL(void) CPUMGCCallV86Code(PCPUMCTXCORE pRegFrame);
1027
1028/** @} */
1029#endif
1030
1031#ifdef IN_RING0
1032/** @defgroup grp_cpum_r0 The CPU Monitor(/Manager) API
1033 * @ingroup grp_cpum
1034 * @{
1035 */
1036
1037/**
1038 * Does Ring-0 CPUM initialization.
1039 *
1040 * This is mainly to check that the Host CPU mode is compatible
1041 * with VBox.
1042 *
1043 * @returns VBox status code.
1044 * @param pVM The VM to operate on.
1045 */
1046CPUMR0DECL(int) CPUMR0Init(PVM pVM);
1047
1048/** @} */
1049#endif
1050
1051/** @} */
1052__END_DECLS
1053
1054
1055#endif
1056
1057
1058
1059
1060
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