cpum.h@ 11946

Last change on this file since 11946 was 11946, checked in by vboxsync, 17 years ago
Fetched esp from the wrong place (1.6 compatibility)
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1	/** @file
2	* CPUM - CPU Monitor(/ Manager).
3	*/
4
5	/*
6	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
7	*
8	* This file is part of VirtualBox Open Source Edition (OSE), as
9	* available from http://www.virtualbox.org. This file is free software;
10	* you can redistribute it and/or modify it under the terms of the GNU
11	* General Public License (GPL) as published by the Free Software
12	* Foundation, in version 2 as it comes in the "COPYING" file of the
13	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15	*
16	* The contents of this file may alternatively be used under the terms
17	* of the Common Development and Distribution License Version 1.0
18	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19	* VirtualBox OSE distribution, in which case the provisions of the
20	* CDDL are applicable instead of those of the GPL.
21	*
22	* You may elect to license modified versions of this file under the
23	* terms and conditions of either the GPL or the CDDL or both.
24	*
25	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
26	* Clara, CA 95054 USA or visit http://www.sun.com if you need
27	* additional information or have any questions.
28	*/
29
30	#ifndef ___VBox_cpum_h
31	#define ___VBox_cpum_h
32
33	#include <VBox/cdefs.h>
34	#include <VBox/types.h>
35	#include <VBox/x86.h>
36
37
38	__BEGIN_DECLS
39
40	/** @defgroup grp_cpum The CPU Monitor(/Manager) API
41	* @{
42	*/
43
44	/**
45	* Selector hidden registers.
46	*/
47	typedef struct CPUMSELREGHID
48	{
49	/** Base register.
50	*
51	* Long mode remarks:
52	* - Unused in long mode for CS, DS, ES, SS
53	* - 32 bits for FS & GS; FS(GS)_BASE msr used for the base address
54	* - 64 bits for TR & LDTR
55	*/
56	uint64_t u64Base;
57	/** Limit (expanded). */
58	uint32_t u32Limit;
59	/** Flags.
60	* This is the high 32-bit word of the descriptor entry.
61	* Only the flags, dpl and type are used. */
62	X86DESCATTR Attr;
63	} CPUMSELREGHID;
64
65
66	/**
67	* The sysenter register set.
68	*/
69	typedef struct CPUMSYSENTER
70	{
71	/** Ring 0 cs.
72	* This value + 8 is the Ring 0 ss.
73	* This value + 16 is the Ring 3 cs.
74	* This value + 24 is the Ring 3 ss.
75	*/
76	uint64_t cs;
77	/** Ring 0 eip. */
78	uint64_t eip;
79	/** Ring 0 esp. */
80	uint64_t esp;
81	} CPUMSYSENTER;
82
83
84	/**
85	* CPU context core.
86	*/
87	#pragma pack(1)
88	typedef struct CPUMCTXCORE
89	{
90	union
91	{
92	uint16_t di;
93	uint32_t edi;
94	uint64_t rdi;
95	};
96	union
97	{
98	uint16_t si;
99	uint32_t esi;
100	uint64_t rsi;
101	};
102	union
103	{
104	uint16_t bp;
105	uint32_t ebp;
106	uint64_t rbp;
107	};
108	union
109	{
110	uint16_t ax;
111	uint32_t eax;
112	uint64_t rax;
113	};
114	union
115	{
116	uint16_t bx;
117	uint32_t ebx;
118	uint64_t rbx;
119	};
120	union
121	{
122	uint16_t dx;
123	uint32_t edx;
124	uint64_t rdx;
125	};
126	union
127	{
128	uint16_t cx;
129	uint32_t ecx;
130	uint64_t rcx;
131	};
132	union
133	{
134	uint16_t sp;
135	uint32_t esp;
136	uint64_t rsp;
137	};
138	/* Note: lss esp, [] in the switcher needs some space, so we reserve it here instead of relying on the exact esp & ss layout as before. */
139	uint32_t lss_esp;
140	RTSEL ss;
141	RTSEL ssPadding;
142
143	RTSEL gs;
144	RTSEL gsPadding;
145	RTSEL fs;
146	RTSEL fsPadding;
147	RTSEL es;
148	RTSEL esPadding;
149	RTSEL ds;
150	RTSEL dsPadding;
151	RTSEL cs;
152	RTSEL csPadding[3]; /* 3 words to force 8 byte alignment for the remainder */
153
154	union
155	{
156	X86EFLAGS eflags;
157	X86RFLAGS rflags;
158	};
159	union
160	{
161	uint16_t ip;
162	uint32_t eip;
163	uint64_t rip;
164	};
165
166	uint64_t r8;
167	uint64_t r9;
168	uint64_t r10;
169	uint64_t r11;
170	uint64_t r12;
171	uint64_t r13;
172	uint64_t r14;
173	uint64_t r15;
174
175	/** Hidden selector registers.
176	* @{ */
177	CPUMSELREGHID esHid;
178	CPUMSELREGHID csHid;
179	CPUMSELREGHID ssHid;
180	CPUMSELREGHID dsHid;
181	CPUMSELREGHID fsHid;
182	CPUMSELREGHID gsHid;
183	/** @} */
184
185	} CPUMCTXCORE;
186	#pragma pack()
187
188
189	/**
190	* CPU context.
191	*/
192	#pragma pack(1)
193	typedef struct CPUMCTX
194	{
195	/** FPU state. (16-byte alignment)
196	* @todo This doesn't have to be in X86FXSTATE on CPUs without fxsr - we need a type for the
197	* actual format or convert it (waste of time). */
198	X86FXSTATE fpu;
199
200	/** CPUMCTXCORE Part.
201	* @{ */
202	union
203	{
204	uint16_t di;
205	uint32_t edi;
206	uint64_t rdi;
207	};
208	union
209	{
210	uint16_t si;
211	uint32_t esi;
212	uint64_t rsi;
213	};
214	union
215	{
216	uint16_t bp;
217	uint32_t ebp;
218	uint64_t rbp;
219	};
220	union
221	{
222	uint16_t ax;
223	uint32_t eax;
224	uint64_t rax;
225	};
226	union
227	{
228	uint16_t bx;
229	uint32_t ebx;
230	uint64_t rbx;
231	};
232	union
233	{
234	uint16_t dx;
235	uint32_t edx;
236	uint64_t rdx;
237	};
238	union
239	{
240	uint16_t cx;
241	uint32_t ecx;
242	uint64_t rcx;
243	};
244	union
245	{
246	uint16_t sp;
247	uint32_t esp;
248	uint64_t rsp;
249	};
250	/* Note: lss esp, [] in the switcher needs some space, so we reserve it here instead of relying on the exact esp & ss layout as before (prevented us from using a union with rsp). */
251	uint32_t lss_esp;
252	RTSEL ss;
253	RTSEL ssPadding;
254
255	RTSEL gs;
256	RTSEL gsPadding;
257	RTSEL fs;
258	RTSEL fsPadding;
259	RTSEL es;
260	RTSEL esPadding;
261	RTSEL ds;
262	RTSEL dsPadding;
263	RTSEL cs;
264	RTSEL csPadding[3]; /* 3 words to force 8 byte alignment for the remainder */
265
266	union
267	{
268	X86EFLAGS eflags;
269	X86RFLAGS rflags;
270	};
271	union
272	{
273	uint16_t ip;
274	uint32_t eip;
275	uint64_t rip;
276	};
277
278	uint64_t r8;
279	uint64_t r9;
280	uint64_t r10;
281	uint64_t r11;
282	uint64_t r12;
283	uint64_t r13;
284	uint64_t r14;
285	uint64_t r15;
286
287	/** Hidden selector registers.
288	* @{ */
289	CPUMSELREGHID esHid;
290	CPUMSELREGHID csHid;
291	CPUMSELREGHID ssHid;
292	CPUMSELREGHID dsHid;
293	CPUMSELREGHID fsHid;
294	CPUMSELREGHID gsHid;
295	/** @} */
296
297	/** @} */
298
299	/** Control registers.
300	* @{ */
301	uint64_t cr0;
302	uint64_t cr2;
303	uint64_t cr3;
304	uint64_t cr4;
305	/** @} */
306
307	/** Debug registers.
308	* @{ */
309	uint64_t dr0;
310	uint64_t dr1;
311	uint64_t dr2;
312	uint64_t dr3;
313	uint64_t dr4; /*< @todo remove dr4 and dr5. /
314	uint64_t dr5;
315	uint64_t dr6;
316	uint64_t dr7;
317	/* DR8-15 are currently not supported */
318	/** @} */
319
320	/** Global Descriptor Table register. */
321	VBOXGDTR gdtr;
322	uint16_t gdtrPadding;
323	/** Interrupt Descriptor Table register. */
324	VBOXIDTR idtr;
325	uint16_t idtrPadding;
326	/** The task register.
327	* Only the guest context uses all the members. */
328	RTSEL ldtr;
329	RTSEL ldtrPadding;
330	/** The task register.
331	* Only the guest context uses all the members. */
332	RTSEL tr;
333	RTSEL trPadding;
334
335	/** The sysenter msr registers.
336	* This member is not used by the hypervisor context. */
337	CPUMSYSENTER SysEnter;
338
339	/** System MSRs.
340	* @{ */
341	uint64_t msrEFER;
342	uint64_t msrSTAR; /* legacy syscall eip, cs & ss */
343	uint64_t msrPAT;
344	uint64_t msrLSTAR; /* 64 bits mode syscall rip */
345	uint64_t msrCSTAR; /* compatibility mode syscall rip */
346	uint64_t msrSFMASK; /* syscall flag mask */
347	uint64_t msrKERNELGSBASE;/* swapgs exchange value */
348	/** @} */
349
350	/** Hidden selector registers.
351	* @{ */
352	CPUMSELREGHID ldtrHid;
353	CPUMSELREGHID trHid;
354	/** @} */
355
356	/* padding to get 32byte aligned size */
357	//// uint32_t padding[6];
358	} CPUMCTX;
359	#pragma pack()
360
361	/**
362	* Gets the CPUMCTXCORE part of a CPUMCTX.
363	*/
364	#define CPUMCTX2CORE(pCtx) ((PCPUMCTXCORE)(void *)&(pCtx)->edi)
365
366
367	/**
368	* Selector hidden registers. (version 1.6)
369	*/
370	typedef struct CPUMSELREGHID_VER1_6
371	{
372	/** Base register. */
373	uint32_t u32Base;
374	/** Limit (expanded). */
375	uint32_t u32Limit;
376	/** Flags.
377	* This is the high 32-bit word of the descriptor entry.
378	* Only the flags, dpl and type are used. */
379	X86DESCATTR Attr;
380	} CPUMSELREGHID_VER1_6;
381
382	/**
383	* CPU context. (Version 1.6)
384	*/
385	#pragma pack(1)
386	typedef struct CPUMCTX_VER1_6
387	{
388	/** FPU state. (16-byte alignment)
389	* @todo This doesn't have to be in X86FXSTATE on CPUs without fxsr - we need a type for the
390	* actual format or convert it (waste of time). */
391	X86FXSTATE fpu;
392
393	/** CPUMCTXCORE Part.
394	* @{ */
395	union
396	{
397	uint32_t edi;
398	uint64_t rdi;
399	};
400	union
401	{
402	uint32_t esi;
403	uint64_t rsi;
404	};
405	union
406	{
407	uint32_t ebp;
408	uint64_t rbp;
409	};
410	union
411	{
412	uint32_t eax;
413	uint64_t rax;
414	};
415	union
416	{
417	uint32_t ebx;
418	uint64_t rbx;
419	};
420	union
421	{
422	uint32_t edx;
423	uint64_t rdx;
424	};
425	union
426	{
427	uint32_t ecx;
428	uint64_t rcx;
429	};
430	/* Note: we rely on the exact layout, because we use lss esp, [] in the switcher */
431	uint32_t esp;
432	RTSEL ss;
433	RTSEL ssPadding;
434	/* Note: no overlap with esp here. */
435	uint64_t rsp_notused;
436
437	RTSEL gs;
438	RTSEL gsPadding;
439	RTSEL fs;
440	RTSEL fsPadding;
441	RTSEL es;
442	RTSEL esPadding;
443	RTSEL ds;
444	RTSEL dsPadding;
445	RTSEL cs;
446	RTSEL csPadding[3]; /* 3 words to force 8 byte alignment for the remainder */
447
448	union
449	{
450	X86EFLAGS eflags;
451	X86RFLAGS rflags;
452	};
453	union
454	{
455	uint32_t eip;
456	uint64_t rip;
457	};
458
459	uint64_t r8;
460	uint64_t r9;
461	uint64_t r10;
462	uint64_t r11;
463	uint64_t r12;
464	uint64_t r13;
465	uint64_t r14;
466	uint64_t r15;
467
468	/** Hidden selector registers.
469	* @{ */
470	CPUMSELREGHID_VER1_6 esHid;
471	CPUMSELREGHID_VER1_6 csHid;
472	CPUMSELREGHID_VER1_6 ssHid;
473	CPUMSELREGHID_VER1_6 dsHid;
474	CPUMSELREGHID_VER1_6 fsHid;
475	CPUMSELREGHID_VER1_6 gsHid;
476	/** @} */
477
478	/** @} */
479
480	/** Control registers.
481	* @{ */
482	uint64_t cr0;
483	uint64_t cr2;
484	uint64_t cr3;
485	uint64_t cr4;
486	uint64_t cr8;
487	/** @} */
488
489	/** Debug registers.
490	* @{ */
491	uint64_t dr0;
492	uint64_t dr1;
493	uint64_t dr2;
494	uint64_t dr3;
495	uint64_t dr4; /*< @todo remove dr4 and dr5. /
496	uint64_t dr5;
497	uint64_t dr6;
498	uint64_t dr7;
499	/* DR8-15 are currently not supported */
500	/** @} */
501
502	/** Global Descriptor Table register. */
503	VBOXGDTR_VER1_6 gdtr;
504	uint16_t gdtrPadding;
505	uint32_t gdtrPadding64;/** @todo fix this hack */
506	/** Interrupt Descriptor Table register. */
507	VBOXIDTR_VER1_6 idtr;
508	uint16_t idtrPadding;
509	uint32_t idtrPadding64;/** @todo fix this hack */
510	/** The task register.
511	* Only the guest context uses all the members. */
512	RTSEL ldtr;
513	RTSEL ldtrPadding;
514	/** The task register.
515	* Only the guest context uses all the members. */
516	RTSEL tr;
517	RTSEL trPadding;
518
519	/** The sysenter msr registers.
520	* This member is not used by the hypervisor context. */
521	CPUMSYSENTER SysEnter;
522
523	/** System MSRs.
524	* @{ */
525	uint64_t msrEFER;
526	uint64_t msrSTAR;
527	uint64_t msrPAT;
528	uint64_t msrLSTAR;
529	uint64_t msrCSTAR;
530	uint64_t msrSFMASK;
531	uint64_t msrFSBASE;
532	uint64_t msrGSBASE;
533	uint64_t msrKERNELGSBASE;
534	/** @} */
535
536	/** Hidden selector registers.
537	* @{ */
538	CPUMSELREGHID_VER1_6 ldtrHid;
539	CPUMSELREGHID_VER1_6 trHid;
540	/** @} */
541
542	/* padding to get 32byte aligned size */
543	uint32_t padding[2];
544	} CPUMCTX_VER1_6;
545	#pragma pack()
546
547	/**
548	* The register set returned by a CPUID operation.
549	*/
550	typedef struct CPUMCPUID
551	{
552	uint32_t eax;
553	uint32_t ebx;
554	uint32_t ecx;
555	uint32_t edx;
556	} CPUMCPUID;
557	/** Pointer to a CPUID leaf. */
558	typedef CPUMCPUID *PCPUMCPUID;
559	/** Pointer to a const CPUID leaf. */
560	typedef const CPUMCPUID *PCCPUMCPUID;
561
562	/**
563	* CPUID feature to set or clear.
564	*/
565	typedef enum CPUMCPUIDFEATURE
566	{
567	CPUMCPUIDFEATURE_INVALID = 0,
568	/** The APIC feature bit. (Std+Ext) */
569	CPUMCPUIDFEATURE_APIC,
570	/** The sysenter/sysexit feature bit. (Std) */
571	CPUMCPUIDFEATURE_SEP,
572	/** The SYSCALL/SYSEXIT feature bit (64 bits mode only for Intel CPUs). (Ext) */
573	CPUMCPUIDFEATURE_SYSCALL,
574	/** The PAE feature bit. (Std+Ext) */
575	CPUMCPUIDFEATURE_PAE,
576	/** The NXE feature bit. (Ext) */
577	CPUMCPUIDFEATURE_NXE,
578	/** The LAHF/SAHF feature bit (64 bits mode only). (Ext) */
579	CPUMCPUIDFEATURE_LAHF,
580	/** The LONG MODE feature bit. (Ext) */
581	CPUMCPUIDFEATURE_LONG_MODE,
582	/** The PAT feature bit. (Std+Ext) */
583	CPUMCPUIDFEATURE_PAT,
584	/** 32bit hackishness. */
585	CPUMCPUIDFEATURE_32BIT_HACK = 0x7fffffff
586	} CPUMCPUIDFEATURE;
587
588	/*
589	* CPU Vendor.
590	*/
591	typedef enum CPUMCPUVENDOR
592	{
593	CPUMCPUVENDOR_INVALID = 0,
594	CPUMCPUVENDOR_INTEL,
595	CPUMCPUVENDOR_AMD,
596	CPUMCPUVENDOR_VIA,
597	CPUMCPUVENDOR_UNKNOWN,
598	/** 32bit hackishness. */
599	CPUMCPUVENDOR_32BIT_HACK = 0x7fffffff
600	} CPUMCPUVENDOR;
601
602
603	/** @name Guest Register Getters.
604	* @{ */
605	CPUMDECL(void) CPUMGetGuestGDTR(PVM pVM, PVBOXGDTR pGDTR);
606	CPUMDECL(RTGCPTR) CPUMGetGuestIDTR(PVM pVM, uint16_t *pcbLimit);
607	CPUMDECL(RTSEL) CPUMGetGuestTR(PVM pVM);
608	CPUMDECL(RTSEL) CPUMGetGuestLDTR(PVM pVM);
609	CPUMDECL(uint64_t) CPUMGetGuestCR0(PVM pVM);
610	CPUMDECL(uint64_t) CPUMGetGuestCR2(PVM pVM);
611	CPUMDECL(uint64_t) CPUMGetGuestCR3(PVM pVM);
612	CPUMDECL(uint64_t) CPUMGetGuestCR4(PVM pVM);
613	CPUMDECL(int) CPUMGetGuestCRx(PVM pVM, unsigned iReg, uint64_t *pValue);
614	CPUMDECL(uint32_t) CPUMGetGuestEFlags(PVM pVM);
615	CPUMDECL(uint32_t) CPUMGetGuestEIP(PVM pVM);
616	CPUMDECL(uint64_t) CPUMGetGuestRIP(PVM pVM);
617	CPUMDECL(uint32_t) CPUMGetGuestEAX(PVM pVM);
618	CPUMDECL(uint32_t) CPUMGetGuestEBX(PVM pVM);
619	CPUMDECL(uint32_t) CPUMGetGuestECX(PVM pVM);
620	CPUMDECL(uint32_t) CPUMGetGuestEDX(PVM pVM);
621	CPUMDECL(uint32_t) CPUMGetGuestESI(PVM pVM);
622	CPUMDECL(uint32_t) CPUMGetGuestEDI(PVM pVM);
623	CPUMDECL(uint32_t) CPUMGetGuestESP(PVM pVM);
624	CPUMDECL(uint32_t) CPUMGetGuestEBP(PVM pVM);
625	CPUMDECL(RTSEL) CPUMGetGuestCS(PVM pVM);
626	CPUMDECL(RTSEL) CPUMGetGuestDS(PVM pVM);
627	CPUMDECL(RTSEL) CPUMGetGuestES(PVM pVM);
628	CPUMDECL(RTSEL) CPUMGetGuestFS(PVM pVM);
629	CPUMDECL(RTSEL) CPUMGetGuestGS(PVM pVM);
630	CPUMDECL(RTSEL) CPUMGetGuestSS(PVM pVM);
631	CPUMDECL(uint64_t) CPUMGetGuestDR0(PVM pVM);
632	CPUMDECL(uint64_t) CPUMGetGuestDR1(PVM pVM);
633	CPUMDECL(uint64_t) CPUMGetGuestDR2(PVM pVM);
634	CPUMDECL(uint64_t) CPUMGetGuestDR3(PVM pVM);
635	CPUMDECL(uint64_t) CPUMGetGuestDR6(PVM pVM);
636	CPUMDECL(uint64_t) CPUMGetGuestDR7(PVM pVM);
637	CPUMDECL(int) CPUMGetGuestDRx(PVM pVM, uint32_t iReg, uint64_t *pValue);
638	CPUMDECL(void) CPUMGetGuestCpuId(PVM pVM, uint32_t iLeaf, uint32_t pEax, uint32_t pEbx, uint32_t pEcx, uint32_t pEdx);
639	CPUMDECL(RCPTRTYPE(PCCPUMCPUID)) CPUMGetGuestCpuIdStdGCPtr(PVM pVM);
640	CPUMDECL(RCPTRTYPE(PCCPUMCPUID)) CPUMGetGuestCpuIdExtGCPtr(PVM pVM);
641	CPUMDECL(RCPTRTYPE(PCCPUMCPUID)) CPUMGetGuestCpuIdCentaurGCPtr(PVM pVM);
642	CPUMDECL(RCPTRTYPE(PCCPUMCPUID)) CPUMGetGuestCpuIdDefGCPtr(PVM pVM);
643	CPUMDECL(uint32_t) CPUMGetGuestCpuIdStdMax(PVM pVM);
644	CPUMDECL(uint32_t) CPUMGetGuestCpuIdExtMax(PVM pVM);
645	CPUMDECL(uint32_t) CPUMGetGuestCpuIdCentaurMax(PVM pVM);
646	CPUMDECL(CPUMSELREGHID *) CPUMGetGuestTRHid(PVM pVM);
647	CPUMDECL(uint64_t) CPUMGetGuestEFER(PVM pVM);
648	CPUMDECL(uint64_t) CPUMGetGuestMsr(PVM pVM, unsigned idMsr);
649	/** @} */
650
651	/** @name Guest Register Setters.
652	* @{ */
653	CPUMDECL(int) CPUMSetGuestGDTR(PVM pVM, uint32_t addr, uint16_t limit);
654	CPUMDECL(int) CPUMSetGuestIDTR(PVM pVM, uint32_t addr, uint16_t limit);
655	CPUMDECL(int) CPUMSetGuestTR(PVM pVM, uint16_t tr);
656	CPUMDECL(int) CPUMSetGuestLDTR(PVM pVM, uint16_t ldtr);
657	CPUMDECL(int) CPUMSetGuestCR0(PVM pVM, uint64_t cr0);
658	CPUMDECL(int) CPUMSetGuestCR2(PVM pVM, uint64_t cr2);
659	CPUMDECL(int) CPUMSetGuestCR3(PVM pVM, uint64_t cr3);
660	CPUMDECL(int) CPUMSetGuestCR4(PVM pVM, uint64_t cr4);
661	CPUMDECL(int) CPUMSetGuestDR0(PVM pVM, uint64_t uDr0);
662	CPUMDECL(int) CPUMSetGuestDR1(PVM pVM, uint64_t uDr1);
663	CPUMDECL(int) CPUMSetGuestDR2(PVM pVM, uint64_t uDr2);
664	CPUMDECL(int) CPUMSetGuestDR3(PVM pVM, uint64_t uDr3);
665	CPUMDECL(int) CPUMSetGuestDR6(PVM pVM, uint64_t uDr6);
666	CPUMDECL(int) CPUMSetGuestDR7(PVM pVM, uint64_t uDr7);
667	CPUMDECL(int) CPUMSetGuestDRx(PVM pVM, uint32_t iReg, uint64_t Value);
668	CPUMDECL(int) CPUMSetGuestEFlags(PVM pVM, uint32_t eflags);
669	CPUMDECL(int) CPUMSetGuestEIP(PVM pVM, uint32_t eip);
670	CPUMDECL(int) CPUMSetGuestEAX(PVM pVM, uint32_t eax);
671	CPUMDECL(int) CPUMSetGuestEBX(PVM pVM, uint32_t ebx);
672	CPUMDECL(int) CPUMSetGuestECX(PVM pVM, uint32_t ecx);
673	CPUMDECL(int) CPUMSetGuestEDX(PVM pVM, uint32_t edx);
674	CPUMDECL(int) CPUMSetGuestESI(PVM pVM, uint32_t esi);
675	CPUMDECL(int) CPUMSetGuestEDI(PVM pVM, uint32_t edi);
676	CPUMDECL(int) CPUMSetGuestESP(PVM pVM, uint32_t esp);
677	CPUMDECL(int) CPUMSetGuestEBP(PVM pVM, uint32_t ebp);
678	CPUMDECL(int) CPUMSetGuestCS(PVM pVM, uint16_t cs);
679	CPUMDECL(int) CPUMSetGuestDS(PVM pVM, uint16_t ds);
680	CPUMDECL(int) CPUMSetGuestES(PVM pVM, uint16_t es);
681	CPUMDECL(int) CPUMSetGuestFS(PVM pVM, uint16_t fs);
682	CPUMDECL(int) CPUMSetGuestGS(PVM pVM, uint16_t gs);
683	CPUMDECL(int) CPUMSetGuestSS(PVM pVM, uint16_t ss);
684	CPUMDECL(void) CPUMSetGuestEFER(PVM pVM, uint64_t val);
685	CPUMDECL(void) CPUMSetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature);
686	CPUMDECL(void) CPUMClearGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature);
687	CPUMDECL(bool) CPUMGetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature);
688	CPUMDECL(void) CPUMSetGuestCtx(PVM pVM, const PCPUMCTX pCtx);
689	/** @} */
690
691	/** @name Misc Guest Predicate Functions.
692	* @{ */
693
694	/**
695	* Tests if the guest is running in real mode or not.
696	*
697	* @returns true if in real mode, otherwise false.
698	* @param pVM The VM handle.
699	*/
700	DECLINLINE(bool) CPUMIsGuestInRealMode(PVM pVM)
701	{
702	return !(CPUMGetGuestCR0(pVM) & X86_CR0_PE);
703	}
704
705	/**
706	* Tests if the guest is running in protected or not.
707	*
708	* @returns true if in protected mode, otherwise false.
709	* @param pVM The VM handle.
710	*/
711	DECLINLINE(bool) CPUMIsGuestInProtectedMode(PVM pVM)
712	{
713	return !!(CPUMGetGuestCR0(pVM) & X86_CR0_PE);
714	}
715
716	/**
717	* Tests if the guest is running in paged protected or not.
718	*
719	* @returns true if in paged protected mode, otherwise false.
720	* @param pVM The VM handle.
721	*/
722	DECLINLINE(bool) CPUMIsGuestInPagedProtectedMode(PVM pVM)
723	{
724	return (CPUMGetGuestCR0(pVM) & (X86_CR0_PE \| X86_CR0_PG)) == (X86_CR0_PE \| X86_CR0_PG);
725	}
726
727	/**
728	* Tests if the guest is running in long mode or not.
729	*
730	* @returns true if in long mode, otherwise false.
731	* @param pVM The VM handle.
732	*/
733	DECLINLINE(bool) CPUMIsGuestInLongMode(PVM pVM)
734	{
735	return (CPUMGetGuestEFER(pVM) & MSR_K6_EFER_LMA) == MSR_K6_EFER_LMA;
736	}
737
738	/**
739	* Tests if the guest is running in long mode or not.
740	*
741	* @returns true if in long mode, otherwise false.
742	* @param pCtx Current CPU context
743	*/
744	DECLINLINE(bool) CPUMIsGuestInLongModeEx(PCPUMCTX pCtx)
745	{
746	return (pCtx->msrEFER & MSR_K6_EFER_LMA) == MSR_K6_EFER_LMA;
747	}
748
749	/**
750	* Tests if the guest is running in 16 bits paged protected or not.
751	*
752	* @returns true if in paged protected mode, otherwise false.
753	* @param pVM The VM handle.
754	*/
755	CPUMDECL(bool) CPUMIsGuestIn16BitCode(PVM pVM);
756
757	/**
758	* Tests if the guest is running in 32 bits paged protected or not.
759	*
760	* @returns true if in paged protected mode, otherwise false.
761	* @param pVM The VM handle.
762	*/
763	CPUMDECL(bool) CPUMIsGuestIn32BitCode(PVM pVM);
764
765	/**
766	* Tests if the guest is running in 64 bits mode or not.
767	*
768	* @returns true if in 64 bits protected mode, otherwise false.
769	* @param pVM The VM handle.
770	* @param pCtx Current CPU context
771	*/
772	DECLINLINE(bool) CPUMIsGuestIn64BitCode(PVM pVM, PCCPUMCTXCORE pCtx)
773	{
774	if (!CPUMIsGuestInLongMode(pVM))
775	return false;
776
777	return pCtx->csHid.Attr.n.u1Long;
778	}
779
780	/**
781	* Tests if the guest is running in 64 bits mode or not.
782	*
783	* @returns true if in 64 bits protected mode, otherwise false.
784	* @param pVM The VM handle.
785	* @param pCtx Current CPU context
786	*/
787	DECLINLINE(bool) CPUMIsGuestIn64BitCodeEx(PCCPUMCTX pCtx)
788	{
789	if (!(pCtx->msrEFER & MSR_K6_EFER_LMA))
790	return false;
791
792	return pCtx->csHid.Attr.n.u1Long;
793	}
794
795	/**
796	* Gets the CPU vendor
797	*
798	* @returns CPU vendor
799	* @param pVM The VM handle.
800	*/
801	CPUMDECL(CPUMCPUVENDOR) CPUMGetCPUVendor(PVM pVM);
802
803
804	/** @} */
805
806
807
808	/** @name Hypervisor Register Getters.
809	* @{ */
810	CPUMDECL(RTSEL) CPUMGetHyperCS(PVM pVM);
811	CPUMDECL(RTSEL) CPUMGetHyperDS(PVM pVM);
812	CPUMDECL(RTSEL) CPUMGetHyperES(PVM pVM);
813	CPUMDECL(RTSEL) CPUMGetHyperFS(PVM pVM);
814	CPUMDECL(RTSEL) CPUMGetHyperGS(PVM pVM);
815	CPUMDECL(RTSEL) CPUMGetHyperSS(PVM pVM);
816	#if 0 /* these are not correct. */
817	CPUMDECL(uint32_t) CPUMGetHyperCR0(PVM pVM);
818	CPUMDECL(uint32_t) CPUMGetHyperCR2(PVM pVM);
819	CPUMDECL(uint32_t) CPUMGetHyperCR3(PVM pVM);
820	CPUMDECL(uint32_t) CPUMGetHyperCR4(PVM pVM);
821	#endif
822	/** This register is only saved on fatal traps. */
823	CPUMDECL(uint32_t) CPUMGetHyperEAX(PVM pVM);
824	CPUMDECL(uint32_t) CPUMGetHyperEBX(PVM pVM);
825	/** This register is only saved on fatal traps. */
826	CPUMDECL(uint32_t) CPUMGetHyperECX(PVM pVM);
827	/** This register is only saved on fatal traps. */
828	CPUMDECL(uint32_t) CPUMGetHyperEDX(PVM pVM);
829	CPUMDECL(uint32_t) CPUMGetHyperESI(PVM pVM);
830	CPUMDECL(uint32_t) CPUMGetHyperEDI(PVM pVM);
831	CPUMDECL(uint32_t) CPUMGetHyperEBP(PVM pVM);
832	CPUMDECL(uint32_t) CPUMGetHyperESP(PVM pVM);
833	CPUMDECL(uint32_t) CPUMGetHyperEFlags(PVM pVM);
834	CPUMDECL(uint32_t) CPUMGetHyperEIP(PVM pVM);
835	CPUMDECL(uint64_t) CPUMGetHyperRIP(PVM pVM);
836	CPUMDECL(uint32_t) CPUMGetHyperIDTR(PVM pVM, uint16_t *pcbLimit);
837	CPUMDECL(uint32_t) CPUMGetHyperGDTR(PVM pVM, uint16_t *pcbLimit);
838	CPUMDECL(RTSEL) CPUMGetHyperLDTR(PVM pVM);
839	CPUMDECL(RTGCUINTREG) CPUMGetHyperDR0(PVM pVM);
840	CPUMDECL(RTGCUINTREG) CPUMGetHyperDR1(PVM pVM);
841	CPUMDECL(RTGCUINTREG) CPUMGetHyperDR2(PVM pVM);
842	CPUMDECL(RTGCUINTREG) CPUMGetHyperDR3(PVM pVM);
843	CPUMDECL(RTGCUINTREG) CPUMGetHyperDR6(PVM pVM);
844	CPUMDECL(RTGCUINTREG) CPUMGetHyperDR7(PVM pVM);
845	CPUMDECL(void) CPUMGetHyperCtx(PVM pVM, PCPUMCTX pCtx);
846	/** @} */
847
848	/** @name Hypervisor Register Setters.
849	* @{ */
850	CPUMDECL(void) CPUMSetHyperGDTR(PVM pVM, uint32_t addr, uint16_t limit);
851	CPUMDECL(void) CPUMSetHyperLDTR(PVM pVM, RTSEL SelLDTR);
852	CPUMDECL(void) CPUMSetHyperIDTR(PVM pVM, uint32_t addr, uint16_t limit);
853	CPUMDECL(void) CPUMSetHyperCR3(PVM pVM, uint32_t cr3);
854	CPUMDECL(void) CPUMSetHyperTR(PVM pVM, RTSEL SelTR);
855	CPUMDECL(void) CPUMSetHyperCS(PVM pVM, RTSEL SelCS);
856	CPUMDECL(void) CPUMSetHyperDS(PVM pVM, RTSEL SelDS);
857	CPUMDECL(void) CPUMSetHyperES(PVM pVM, RTSEL SelDS);
858	CPUMDECL(void) CPUMSetHyperFS(PVM pVM, RTSEL SelDS);
859	CPUMDECL(void) CPUMSetHyperGS(PVM pVM, RTSEL SelDS);
860	CPUMDECL(void) CPUMSetHyperSS(PVM pVM, RTSEL SelSS);
861	CPUMDECL(void) CPUMSetHyperESP(PVM pVM, uint32_t u32ESP);
862	CPUMDECL(int) CPUMSetHyperEFlags(PVM pVM, uint32_t Efl);
863	CPUMDECL(void) CPUMSetHyperEIP(PVM pVM, uint32_t u32EIP);
864	CPUMDECL(void) CPUMSetHyperDR0(PVM pVM, RTGCUINTREG uDr0);
865	CPUMDECL(void) CPUMSetHyperDR1(PVM pVM, RTGCUINTREG uDr1);
866	CPUMDECL(void) CPUMSetHyperDR2(PVM pVM, RTGCUINTREG uDr2);
867	CPUMDECL(void) CPUMSetHyperDR3(PVM pVM, RTGCUINTREG uDr3);
868	CPUMDECL(void) CPUMSetHyperDR6(PVM pVM, RTGCUINTREG uDr6);
869	CPUMDECL(void) CPUMSetHyperDR7(PVM pVM, RTGCUINTREG uDr7);
870	CPUMDECL(void) CPUMSetHyperCtx(PVM pVM, const PCPUMCTX pCtx);
871	CPUMDECL(int) CPUMRecalcHyperDRx(PVM pVM);
872	/** @} */
873
874	CPUMDECL(void) CPUMPushHyper(PVM pVM, uint32_t u32);
875
876	/**
877	* Sets or resets an alternative hypervisor context core.
878	*
879	* This is called when we get a hypervisor trap set switch the context
880	* core with the trap frame on the stack. It is called again to reset
881	* back to the default context core when resuming hypervisor execution.
882	*
883	* @param pVM The VM handle.
884	* @param pCtxCore Pointer to the alternative context core or NULL
885	* to go back to the default context core.
886	*/
887	CPUMDECL(void) CPUMHyperSetCtxCore(PVM pVM, PCPUMCTXCORE pCtxCore);
888
889
890	/**
891	* Queries the pointer to the internal CPUMCTX structure
892	*
893	* @returns VBox status code.
894	* @param pVM Handle to the virtual machine.
895	* @param ppCtx Receives the CPUMCTX pointer when successful.
896	*/
897	CPUMDECL(int) CPUMQueryGuestCtxPtr(PVM pVM, PCPUMCTX *ppCtx);
898
899	/**
900	* Queries the pointer to the internal CPUMCTX structure for the hypervisor.
901	*
902	* @returns VBox status code.
903	* @param pVM Handle to the virtual machine.
904	* @param ppCtx Receives the hyper CPUMCTX pointer when successful.
905	*/
906	CPUMDECL(int) CPUMQueryHyperCtxPtr(PVM pVM, PCPUMCTX *ppCtx);
907
908
909	/**
910	* Gets the pointer to the internal CPUMCTXCORE structure.
911	* This is only for reading in order to save a few calls.
912	*
913	* @param pVM Handle to the virtual machine.
914	*/
915	CPUMDECL(PCCPUMCTXCORE) CPUMGetGuestCtxCore(PVM pVM);
916
917	/**
918	* Gets the pointer to the internal CPUMCTXCORE structure for the hypervisor.
919	* This is only for reading in order to save a few calls.
920	*
921	* @param pVM Handle to the virtual machine.
922	*/
923	CPUMDECL(PCCPUMCTXCORE) CPUMGetHyperCtxCore(PVM pVM);
924
925	/**
926	* Sets the guest context core registers.
927	*
928	* @param pVM Handle to the virtual machine.
929	* @param pCtxCore The new context core values.
930	*/
931	CPUMDECL(void) CPUMSetGuestCtxCore(PVM pVM, PCCPUMCTXCORE pCtxCore);
932
933
934	/**
935	* Transforms the guest CPU state to raw-ring mode.
936	*
937	* This function will change the any of the cs and ss register with DPL=0 to DPL=1.
938	*
939	* @returns VBox status. (recompiler failure)
940	* @param pVM VM handle.
941	* @param pCtxCore The context core (for trap usage).
942	* @see @ref pg_raw
943	*/
944	CPUMDECL(int) CPUMRawEnter(PVM pVM, PCPUMCTXCORE pCtxCore);
945
946	/**
947	* Transforms the guest CPU state from raw-ring mode to correct values.
948	*
949	* This function will change any selector registers with DPL=1 to DPL=0.
950	*
951	* @returns Adjusted rc.
952	* @param pVM VM handle.
953	* @param rc Raw mode return code
954	* @param pCtxCore The context core (for trap usage).
955	* @see @ref pg_raw
956	*/
957	CPUMDECL(int) CPUMRawLeave(PVM pVM, PCPUMCTXCORE pCtxCore, int rc);
958
959	/**
960	* Gets the EFLAGS while we're in raw-mode.
961	*
962	* @returns The eflags.
963	* @param pVM The VM handle.
964	* @param pCtxCore The context core.
965	*/
966	CPUMDECL(uint32_t) CPUMRawGetEFlags(PVM pVM, PCPUMCTXCORE pCtxCore);
967
968	/**
969	* Updates the EFLAGS while we're in raw-mode.
970	*
971	* @param pVM The VM handle.
972	* @param pCtxCore The context core.
973	* @param eflags The new EFLAGS value.
974	*/
975	CPUMDECL(void) CPUMRawSetEFlags(PVM pVM, PCPUMCTXCORE pCtxCore, uint32_t eflags);
976
977	/**
978	* Lazily sync in the FPU/XMM state
979	*
980	* This function will change any selector registers with DPL=1 to DPL=0.
981	*
982	* @returns VBox status code.
983	* @param pVM VM handle.
984	*/
985	CPUMDECL(int) CPUMHandleLazyFPU(PVM pVM);
986
987
988	/**
989	* Restore host FPU/XMM state
990	*
991	* @returns VBox status code.
992	* @param pVM VM handle.
993	*/
994	CPUMDECL(int) CPUMRestoreHostFPUState(PVM pVM);
995
996	/** @name Changed flags
997	* These flags are used to keep track of which important register that
998	* have been changed since last they were reset. The only one allowed
999	* to clear them is REM!
1000	* @{
1001	*/
1002	#define CPUM_CHANGED_FPU_REM RT_BIT(0)
1003	#define CPUM_CHANGED_CR0 RT_BIT(1)
1004	#define CPUM_CHANGED_CR4 RT_BIT(2)
1005	#define CPUM_CHANGED_GLOBAL_TLB_FLUSH RT_BIT(3)
1006	#define CPUM_CHANGED_CR3 RT_BIT(4)
1007	#define CPUM_CHANGED_GDTR RT_BIT(5)
1008	#define CPUM_CHANGED_IDTR RT_BIT(6)
1009	#define CPUM_CHANGED_LDTR RT_BIT(7)
1010	#define CPUM_CHANGED_TR RT_BIT(8)
1011	#define CPUM_CHANGED_SYSENTER_MSR RT_BIT(9)
1012	#define CPUM_CHANGED_HIDDEN_SEL_REGS RT_BIT(10)
1013	#define CPUM_CHANGED_CPUID RT_BIT(11)
1014	#define CPUM_CHANGED_ALL (CPUM_CHANGED_FPU_REM\|CPUM_CHANGED_CR0\|CPUM_CHANGED_CR3\|CPUM_CHANGED_CR4\|CPUM_CHANGED_GDTR\|CPUM_CHANGED_IDTR\|CPUM_CHANGED_LDTR\|CPUM_CHANGED_TR\|CPUM_CHANGED_SYSENTER_MSR\|CPUM_CHANGED_HIDDEN_SEL_REGS\|CPUM_CHANGED_CPUID)
1015	/** @} */
1016
1017	/**
1018	* Gets and resets the changed flags (CPUM_CHANGED_*).
1019	*
1020	* @returns The changed flags.
1021	* @param pVM VM handle.
1022	*/
1023	CPUMDECL(unsigned) CPUMGetAndClearChangedFlagsREM(PVM pVM);
1024
1025	/**
1026	* Sets the specified changed flags (CPUM_CHANGED_*).
1027	*
1028	* @param pVM The VM handle.
1029	*/
1030	CPUMDECL(void) CPUMSetChangedFlags(PVM pVM, uint32_t fChangedFlags);
1031
1032	/**
1033	* Checks if the CPU supports the FXSAVE and FXRSTOR instruction.
1034	* @returns true if supported.
1035	* @returns false if not supported.
1036	* @param pVM The VM handle.
1037	*/
1038	CPUMDECL(bool) CPUMSupportsFXSR(PVM pVM);
1039
1040	/**
1041	* Checks if the host OS uses the SYSENTER / SYSEXIT instructions.
1042	* @returns true if used.
1043	* @returns false if not used.
1044	* @param pVM The VM handle.
1045	*/
1046	CPUMDECL(bool) CPUMIsHostUsingSysEnter(PVM pVM);
1047
1048	/**
1049	* Checks if the host OS uses the SYSCALL / SYSRET instructions.
1050	* @returns true if used.
1051	* @returns false if not used.
1052	* @param pVM The VM handle.
1053	*/
1054	CPUMDECL(bool) CPUMIsHostUsingSysCall(PVM pVM);
1055
1056	/**
1057	* Checks if we activated the FPU/XMM state of the guest OS
1058	* @returns true if we did.
1059	* @returns false if not.
1060	* @param pVM The VM handle.
1061	*/
1062	CPUMDECL(bool) CPUMIsGuestFPUStateActive(PVM pVM);
1063
1064	/**
1065	* Deactivate the FPU/XMM state of the guest OS
1066	* @param pVM The VM handle.
1067	*/
1068	CPUMDECL(void) CPUMDeactivateGuestFPUState(PVM pVM);
1069
1070
1071	/**
1072	* Checks if the hidden selector registers are valid
1073	* @returns true if they are.
1074	* @returns false if not.
1075	* @param pVM The VM handle.
1076	*/
1077	CPUMDECL(bool) CPUMAreHiddenSelRegsValid(PVM pVM);
1078
1079	/**
1080	* Checks if the hidden selector registers are valid
1081	* @param pVM The VM handle.
1082	* @param fValid Valid or not
1083	*/
1084	CPUMDECL(void) CPUMSetHiddenSelRegsValid(PVM pVM, bool fValid);
1085
1086	/**
1087	* Get the current privilege level of the guest.
1088	*
1089	* @returns cpl
1090	* @param pVM VM Handle.
1091	* @param pRegFrame Trap register frame.
1092	*/
1093	CPUMDECL(uint32_t) CPUMGetGuestCPL(PVM pVM, PCPUMCTXCORE pCtxCore);
1094
1095	/**
1096	* CPU modes.
1097	*/
1098	typedef enum CPUMMODE
1099	{
1100	/** The usual invalid zero entry. */
1101	CPUMMODE_INVALID = 0,
1102	/** Real mode. */
1103	CPUMMODE_REAL,
1104	/** Protected mode (32-bit). */
1105	CPUMMODE_PROTECTED,
1106	/** Long mode (64-bit). */
1107	CPUMMODE_LONG
1108	} CPUMMODE;
1109
1110	/**
1111	* Gets the current guest CPU mode.
1112	*
1113	* If paging mode is what you need, check out PGMGetGuestMode().
1114	*
1115	* @returns The CPU mode.
1116	* @param pVM The VM handle.
1117	*/
1118	CPUMDECL(CPUMMODE) CPUMGetGuestMode(PVM pVM);
1119
1120
1121	#ifdef IN_RING3
1122	/** @defgroup grp_cpum_r3 The CPU Monitor(/Manager) API
1123	* @ingroup grp_cpum
1124	* @{
1125	*/
1126
1127	/**
1128	* Initializes the CPUM.
1129	*
1130	* @returns VBox status code.
1131	* @param pVM The VM to operate on.
1132	*/
1133	CPUMR3DECL(int) CPUMR3Init(PVM pVM);
1134
1135	/**
1136	* Applies relocations to data and code managed by this
1137	* component. This function will be called at init and
1138	* whenever the VMM need to relocate it self inside the GC.
1139	*
1140	* The CPUM will update the addresses used by the switcher.
1141	*
1142	* @param pVM The VM.
1143	*/
1144	CPUMR3DECL(void) CPUMR3Relocate(PVM pVM);
1145
1146	/**
1147	* Terminates the CPUM.
1148	*
1149	* Termination means cleaning up and freeing all resources,
1150	* the VM it self is at this point powered off or suspended.
1151	*
1152	* @returns VBox status code.
1153	* @param pVM The VM to operate on.
1154	*/
1155	CPUMR3DECL(int) CPUMR3Term(PVM pVM);
1156
1157	/**
1158	* Resets the CPU.
1159	*
1160	* @param pVM The VM handle.
1161	*/
1162	CPUMR3DECL(void) CPUMR3Reset(PVM pVM);
1163
1164	/**
1165	* Queries the pointer to the internal CPUMCTX structure
1166	*
1167	* @returns VBox status code.
1168	* @param pVM Handle to the virtual machine.
1169	* @param ppCtx Receives the CPUMCTX GC pointer when successful.
1170	*/
1171	CPUMR3DECL(int) CPUMR3QueryGuestCtxGCPtr(PVM pVM, RCPTRTYPE(PCPUMCTX) *ppCtx);
1172
1173
1174	#ifdef DEBUG
1175	/**
1176	* Debug helper - Saves guest context on raw mode entry (for fatal dump)
1177	*
1178	* @internal
1179	*/
1180	CPUMR3DECL(void) CPUMR3SaveEntryCtx(PVM pVM);
1181	#endif
1182
1183	/**
1184	* API for controlling a few of the CPU features found in CR4.
1185	*
1186	* Currently only X86_CR4_TSD is accepted as input.
1187	*
1188	* @returns VBox status code.
1189	*
1190	* @param pVM The VM handle.
1191	* @param fOr The CR4 OR mask.
1192	* @param fAnd The CR4 AND mask.
1193	*/
1194	CPUMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd);
1195
1196	/** @} */
1197	#endif
1198
1199	#ifdef IN_GC
1200	/** @defgroup grp_cpum_gc The CPU Monitor(/Manager) API
1201	* @ingroup grp_cpum
1202	* @{
1203	*/
1204
1205	/**
1206	* Calls a guest trap/interrupt handler directly
1207	* Assumes a trap stack frame has already been setup on the guest's stack!
1208	*
1209	* @param pRegFrame Original trap/interrupt context
1210	* @param selCS Code selector of handler
1211	* @param pHandler GC virtual address of handler
1212	* @param eflags Callee's EFLAGS
1213	* @param selSS Stack selector for handler
1214	* @param pEsp Stack address for handler
1215	*
1216	* This function does not return!
1217	*
1218	*/
1219	DECLASM(void) CPUMGCCallGuestTrapHandler(PCPUMCTXCORE pRegFrame, uint32_t selCS, RTRCPTR pHandler, uint32_t eflags, uint32_t selSS, RTRCPTR pEsp);
1220
1221	/**
1222	* Performs an iret to V86 code
1223	* Assumes a trap stack frame has already been setup on the guest's stack!
1224	*
1225	* @param pRegFrame Original trap/interrupt context
1226	*
1227	* This function does not return!
1228	*/
1229	CPUMGCDECL(void) CPUMGCCallV86Code(PCPUMCTXCORE pRegFrame);
1230
1231	/** @} */
1232	#endif
1233
1234	#ifdef IN_RING0
1235	/** @defgroup grp_cpum_r0 The CPU Monitor(/Manager) API
1236	* @ingroup grp_cpum
1237	* @{
1238	*/
1239
1240	/**
1241	* Does Ring-0 CPUM initialization.
1242	*
1243	* This is mainly to check that the Host CPU mode is compatible
1244	* with VBox.
1245	*
1246	* @returns VBox status code.
1247	* @param pVM The VM to operate on.
1248	*/
1249	CPUMR0DECL(int) CPUMR0Init(PVM pVM);
1250
1251	/**
1252	* Lazily sync in the FPU/XMM state
1253	*
1254	* @returns VBox status code.
1255	* @param pVM VM handle.
1256	* @param pCtx CPU context
1257	*/
1258	CPUMR0DECL(int) CPUMR0LoadGuestFPU(PVM pVM, PCPUMCTX pCtx);
1259
1260	/**
1261	* Save guest FPU/XMM state
1262	*
1263	* @returns VBox status code.
1264	* @param pVM VM handle.
1265	* @param pCtx CPU context
1266	*/
1267	CPUMR0DECL(int) CPUMR0SaveGuestFPU(PVM pVM, PCPUMCTX pCtx);
1268
1269	/** @} */
1270	#endif
1271
1272	/** @} */
1273	__END_DECLS
1274
1275
1276	#endif
1277
1278
1279
1280
1281

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source: vbox/trunk/include/VBox/cpum.h@ 11946

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