VirtualBox

source: vbox/trunk/include/VBox/cpum.h@ 34655

Last change on this file since 34655 was 34326, checked in by vboxsync, 14 years ago

VMM: Removed the XXXInitCPU and XXXTermCPU methods since all but the HWACCM ones where stubs and the XXXTermCPU bits was not called in all expected paths. The HWACCMR3InitCPU was hooked up as a VMINITCOMPLETED_RING3 hook, essentially leaving it's position in the order of things unchanged, while the HWACCMR3TermCPU call was made static without changing its position at the end of HWACCMR3Term.
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  • Property svn:keywords set to Author Date Id Revision
File size: 20.0 KB
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1/** @file
2 * CPUM - CPU Monitor(/ Manager). (VMM)
3 */
4
5/*
6 * Copyright (C) 2006-2010 Oracle Corporation
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * The contents of this file may alternatively be used under the terms
17 * of the Common Development and Distribution License Version 1.0
18 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19 * VirtualBox OSE distribution, in which case the provisions of the
20 * CDDL are applicable instead of those of the GPL.
21 *
22 * You may elect to license modified versions of this file under the
23 * terms and conditions of either the GPL or the CDDL or both.
24 */
25
26#ifndef ___VBox_cpum_h
27#define ___VBox_cpum_h
28
29#include <VBox/cdefs.h>
30#include <VBox/types.h>
31#include <VBox/x86.h>
32#include <VBox/cpumctx.h>
33
34RT_C_DECLS_BEGIN
35
36/** @defgroup grp_cpum The CPU Monitor / Manager API
37 * @{
38 */
39
40/**
41 * CPUID feature to set or clear.
42 */
43typedef enum CPUMCPUIDFEATURE
44{
45 CPUMCPUIDFEATURE_INVALID = 0,
46 /** The APIC feature bit. (Std+Ext) */
47 CPUMCPUIDFEATURE_APIC,
48 /** The sysenter/sysexit feature bit. (Std) */
49 CPUMCPUIDFEATURE_SEP,
50 /** The SYSCALL/SYSEXIT feature bit (64 bits mode only for Intel CPUs). (Ext) */
51 CPUMCPUIDFEATURE_SYSCALL,
52 /** The PAE feature bit. (Std+Ext) */
53 CPUMCPUIDFEATURE_PAE,
54 /** The NXE feature bit. (Ext) */
55 CPUMCPUIDFEATURE_NXE,
56 /** The LAHF/SAHF feature bit (64 bits mode only). (Ext) */
57 CPUMCPUIDFEATURE_LAHF,
58 /** The LONG MODE feature bit. (Ext) */
59 CPUMCPUIDFEATURE_LONG_MODE,
60 /** The PAT feature bit. (Std+Ext) */
61 CPUMCPUIDFEATURE_PAT,
62 /** The x2APIC feature bit. (Std) */
63 CPUMCPUIDFEATURE_X2APIC,
64 /** The RDTSCP feature bit. (Ext) */
65 CPUMCPUIDFEATURE_RDTSCP,
66 /** 32bit hackishness. */
67 CPUMCPUIDFEATURE_32BIT_HACK = 0x7fffffff
68} CPUMCPUIDFEATURE;
69
70/**
71 * CPU Vendor.
72 */
73typedef enum CPUMCPUVENDOR
74{
75 CPUMCPUVENDOR_INVALID = 0,
76 CPUMCPUVENDOR_INTEL,
77 CPUMCPUVENDOR_AMD,
78 CPUMCPUVENDOR_VIA,
79 CPUMCPUVENDOR_UNKNOWN,
80 CPUMCPUVENDOR_SYNTHETIC,
81 /** 32bit hackishness. */
82 CPUMCPUVENDOR_32BIT_HACK = 0x7fffffff
83} CPUMCPUVENDOR;
84
85
86/** @name Guest Register Getters.
87 * @{ */
88VMMDECL(void) CPUMGetGuestGDTR(PVMCPU pVCpu, PVBOXGDTR pGDTR);
89VMMDECL(RTGCPTR) CPUMGetGuestIDTR(PVMCPU pVCpu, uint16_t *pcbLimit);
90VMMDECL(RTSEL) CPUMGetGuestTR(PVMCPU pVCpu, PCPUMSELREGHID pHidden);
91VMMDECL(RTSEL) CPUMGetGuestLDTR(PVMCPU pVCpu);
92VMMDECL(uint64_t) CPUMGetGuestCR0(PVMCPU pVCpu);
93VMMDECL(uint64_t) CPUMGetGuestCR2(PVMCPU pVCpu);
94VMMDECL(uint64_t) CPUMGetGuestCR3(PVMCPU pVCpu);
95VMMDECL(uint64_t) CPUMGetGuestCR4(PVMCPU pVCpu);
96VMMDECL(uint64_t) CPUMGetGuestCR8(PVMCPU pVCpu);
97VMMDECL(int) CPUMGetGuestCRx(PVMCPU pVCpu, unsigned iReg, uint64_t *pValue);
98VMMDECL(uint32_t) CPUMGetGuestEFlags(PVMCPU pVCpu);
99VMMDECL(uint32_t) CPUMGetGuestEIP(PVMCPU pVCpu);
100VMMDECL(uint64_t) CPUMGetGuestRIP(PVMCPU pVCpu);
101VMMDECL(uint32_t) CPUMGetGuestEAX(PVMCPU pVCpu);
102VMMDECL(uint32_t) CPUMGetGuestEBX(PVMCPU pVCpu);
103VMMDECL(uint32_t) CPUMGetGuestECX(PVMCPU pVCpu);
104VMMDECL(uint32_t) CPUMGetGuestEDX(PVMCPU pVCpu);
105VMMDECL(uint32_t) CPUMGetGuestESI(PVMCPU pVCpu);
106VMMDECL(uint32_t) CPUMGetGuestEDI(PVMCPU pVCpu);
107VMMDECL(uint32_t) CPUMGetGuestESP(PVMCPU pVCpu);
108VMMDECL(uint32_t) CPUMGetGuestEBP(PVMCPU pVCpu);
109VMMDECL(RTSEL) CPUMGetGuestCS(PVMCPU pVCpu);
110VMMDECL(RTSEL) CPUMGetGuestDS(PVMCPU pVCpu);
111VMMDECL(RTSEL) CPUMGetGuestES(PVMCPU pVCpu);
112VMMDECL(RTSEL) CPUMGetGuestFS(PVMCPU pVCpu);
113VMMDECL(RTSEL) CPUMGetGuestGS(PVMCPU pVCpu);
114VMMDECL(RTSEL) CPUMGetGuestSS(PVMCPU pVCpu);
115VMMDECL(uint64_t) CPUMGetGuestDR0(PVMCPU pVCpu);
116VMMDECL(uint64_t) CPUMGetGuestDR1(PVMCPU pVCpu);
117VMMDECL(uint64_t) CPUMGetGuestDR2(PVMCPU pVCpu);
118VMMDECL(uint64_t) CPUMGetGuestDR3(PVMCPU pVCpu);
119VMMDECL(uint64_t) CPUMGetGuestDR6(PVMCPU pVCpu);
120VMMDECL(uint64_t) CPUMGetGuestDR7(PVMCPU pVCpu);
121VMMDECL(int) CPUMGetGuestDRx(PVMCPU pVCpu, uint32_t iReg, uint64_t *pValue);
122VMMDECL(void) CPUMGetGuestCpuId(PVMCPU pVCpu, uint32_t iLeaf, uint32_t *pEax, uint32_t *pEbx, uint32_t *pEcx, uint32_t *pEdx);
123VMMDECL(uint32_t) CPUMGetGuestCpuIdStdMax(PVM pVM);
124VMMDECL(uint32_t) CPUMGetGuestCpuIdExtMax(PVM pVM);
125VMMDECL(uint32_t) CPUMGetGuestCpuIdCentaurMax(PVM pVM);
126VMMDECL(uint64_t) CPUMGetGuestEFER(PVMCPU pVCpu);
127VMMDECL(int) CPUMQueryGuestMsr(PVMCPU pVCpu, uint32_t idMsr, uint64_t *puValue);
128VMMDECL(int) CPUMSetGuestMsr(PVMCPU pVCpu, uint32_t idMsr, uint64_t uValue);
129VMMDECL(CPUMCPUVENDOR) CPUMGetGuestCpuVendor(PVM pVM);
130VMMDECL(CPUMCPUVENDOR) CPUMGetHostCpuVendor(PVM pVM);
131/** @} */
132
133/** @name Guest Register Setters.
134 * @{ */
135VMMDECL(int) CPUMSetGuestGDTR(PVMCPU pVCpu, uint32_t addr, uint16_t limit);
136VMMDECL(int) CPUMSetGuestIDTR(PVMCPU pVCpu, uint32_t addr, uint16_t limit);
137VMMDECL(int) CPUMSetGuestTR(PVMCPU pVCpu, uint16_t tr);
138VMMDECL(int) CPUMSetGuestLDTR(PVMCPU pVCpu, uint16_t ldtr);
139VMMDECL(int) CPUMSetGuestCR0(PVMCPU pVCpu, uint64_t cr0);
140VMMDECL(int) CPUMSetGuestCR2(PVMCPU pVCpu, uint64_t cr2);
141VMMDECL(int) CPUMSetGuestCR3(PVMCPU pVCpu, uint64_t cr3);
142VMMDECL(int) CPUMSetGuestCR4(PVMCPU pVCpu, uint64_t cr4);
143VMMDECL(int) CPUMSetGuestDR0(PVMCPU pVCpu, uint64_t uDr0);
144VMMDECL(int) CPUMSetGuestDR1(PVMCPU pVCpu, uint64_t uDr1);
145VMMDECL(int) CPUMSetGuestDR2(PVMCPU pVCpu, uint64_t uDr2);
146VMMDECL(int) CPUMSetGuestDR3(PVMCPU pVCpu, uint64_t uDr3);
147VMMDECL(int) CPUMSetGuestDR6(PVMCPU pVCpu, uint64_t uDr6);
148VMMDECL(int) CPUMSetGuestDR7(PVMCPU pVCpu, uint64_t uDr7);
149VMMDECL(int) CPUMSetGuestDRx(PVMCPU pVCpu, uint32_t iReg, uint64_t Value);
150VMMDECL(int) CPUMSetGuestEFlags(PVMCPU pVCpu, uint32_t eflags);
151VMMDECL(int) CPUMSetGuestEIP(PVMCPU pVCpu, uint32_t eip);
152VMMDECL(int) CPUMSetGuestEAX(PVMCPU pVCpu, uint32_t eax);
153VMMDECL(int) CPUMSetGuestEBX(PVMCPU pVCpu, uint32_t ebx);
154VMMDECL(int) CPUMSetGuestECX(PVMCPU pVCpu, uint32_t ecx);
155VMMDECL(int) CPUMSetGuestEDX(PVMCPU pVCpu, uint32_t edx);
156VMMDECL(int) CPUMSetGuestESI(PVMCPU pVCpu, uint32_t esi);
157VMMDECL(int) CPUMSetGuestEDI(PVMCPU pVCpu, uint32_t edi);
158VMMDECL(int) CPUMSetGuestESP(PVMCPU pVCpu, uint32_t esp);
159VMMDECL(int) CPUMSetGuestEBP(PVMCPU pVCpu, uint32_t ebp);
160VMMDECL(int) CPUMSetGuestCS(PVMCPU pVCpu, uint16_t cs);
161VMMDECL(int) CPUMSetGuestDS(PVMCPU pVCpu, uint16_t ds);
162VMMDECL(int) CPUMSetGuestES(PVMCPU pVCpu, uint16_t es);
163VMMDECL(int) CPUMSetGuestFS(PVMCPU pVCpu, uint16_t fs);
164VMMDECL(int) CPUMSetGuestGS(PVMCPU pVCpu, uint16_t gs);
165VMMDECL(int) CPUMSetGuestSS(PVMCPU pVCpu, uint16_t ss);
166VMMDECL(void) CPUMSetGuestEFER(PVMCPU pVCpu, uint64_t val);
167VMMDECL(void) CPUMSetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature);
168VMMDECL(void) CPUMClearGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature);
169VMMDECL(bool) CPUMGetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature);
170VMMDECL(void) CPUMSetGuestCtx(PVMCPU pVCpu, const PCPUMCTX pCtx);
171/** @} */
172
173
174/** @name Misc Guest Predicate Functions.
175 * @{ */
176
177VMMDECL(bool) CPUMIsGuestIn16BitCode(PVMCPU pVCpu);
178VMMDECL(bool) CPUMIsGuestIn32BitCode(PVMCPU pVCpu);
179VMMDECL(bool) CPUMIsGuestNXEnabled(PVMCPU pVCpu);
180VMMDECL(bool) CPUMIsGuestPageSizeExtEnabled(PVMCPU pVCpu);
181VMMDECL(bool) CPUMIsGuestPagingEnabled(PVMCPU pVCpu);
182VMMDECL(bool) CPUMIsGuestR0WriteProtEnabled(PVMCPU pVCpu);
183VMMDECL(bool) CPUMIsGuestInRealMode(PVMCPU pVCpu);
184VMMDECL(bool) CPUMIsGuestInProtectedMode(PVMCPU pVCpu);
185VMMDECL(bool) CPUMIsGuestInPagedProtectedMode(PVMCPU pVCpu);
186VMMDECL(bool) CPUMIsGuestInLongMode(PVMCPU pVCpu);
187VMMDECL(bool) CPUMIsGuestInPAEMode(PVMCPU pVCpu);
188
189#ifndef VBOX_WITHOUT_UNNAMED_UNIONS
190
191/**
192 * Tests if the guest is running in real mode or not.
193 *
194 * @returns true if in real mode, otherwise false.
195 * @param pCtx Current CPU context
196 */
197DECLINLINE(bool) CPUMIsGuestInRealModeEx(PCPUMCTX pCtx)
198{
199 return !(pCtx->cr0 & X86_CR0_PE);
200}
201
202/**
203 * Tests if the guest is running in paged protected or not.
204 *
205 * @returns true if in paged protected mode, otherwise false.
206 * @param pVM The VM handle.
207 */
208DECLINLINE(bool) CPUMIsGuestInPagedProtectedModeEx(PCPUMCTX pCtx)
209{
210 return (pCtx->cr0 & (X86_CR0_PE | X86_CR0_PG)) == (X86_CR0_PE | X86_CR0_PG);
211}
212
213/**
214 * Tests if the guest is running in long mode or not.
215 *
216 * @returns true if in long mode, otherwise false.
217 * @param pCtx Current CPU context
218 */
219DECLINLINE(bool) CPUMIsGuestInLongModeEx(PCPUMCTX pCtx)
220{
221 return (pCtx->msrEFER & MSR_K6_EFER_LMA) == MSR_K6_EFER_LMA;
222}
223
224/**
225 * Tests if the guest is running in 64 bits mode or not.
226 *
227 * @returns true if in 64 bits protected mode, otherwise false.
228 * @param pVM The VM handle.
229 * @param pCtx Current CPU context
230 */
231DECLINLINE(bool) CPUMIsGuestIn64BitCode(PVMCPU pVCpu, PCCPUMCTXCORE pCtx)
232{
233 if (!CPUMIsGuestInLongMode(pVCpu))
234 return false;
235
236 return pCtx->csHid.Attr.n.u1Long;
237}
238
239/**
240 * Tests if the guest is running in 64 bits mode or not.
241 *
242 * @returns true if in 64 bits protected mode, otherwise false.
243 * @param pVM The VM handle.
244 * @param pCtx Current CPU context
245 */
246DECLINLINE(bool) CPUMIsGuestIn64BitCodeEx(PCCPUMCTX pCtx)
247{
248 if (!(pCtx->msrEFER & MSR_K6_EFER_LMA))
249 return false;
250
251 return pCtx->csHid.Attr.n.u1Long;
252}
253
254/**
255 * Tests if the guest is running in PAE mode or not.
256 *
257 * @returns true if in PAE mode, otherwise false.
258 * @param pCtx Current CPU context
259 */
260DECLINLINE(bool) CPUMIsGuestInPAEModeEx(PCPUMCTX pCtx)
261{
262 return ( (pCtx->cr4 & X86_CR4_PAE)
263 && CPUMIsGuestInPagedProtectedModeEx(pCtx)
264 && !CPUMIsGuestInLongModeEx(pCtx));
265}
266
267#endif /* VBOX_WITHOUT_UNNAMED_UNIONS */
268
269/** @} */
270
271
272/** @name Hypervisor Register Getters.
273 * @{ */
274VMMDECL(RTSEL) CPUMGetHyperCS(PVMCPU pVCpu);
275VMMDECL(RTSEL) CPUMGetHyperDS(PVMCPU pVCpu);
276VMMDECL(RTSEL) CPUMGetHyperES(PVMCPU pVCpu);
277VMMDECL(RTSEL) CPUMGetHyperFS(PVMCPU pVCpu);
278VMMDECL(RTSEL) CPUMGetHyperGS(PVMCPU pVCpu);
279VMMDECL(RTSEL) CPUMGetHyperSS(PVMCPU pVCpu);
280#if 0 /* these are not correct. */
281VMMDECL(uint32_t) CPUMGetHyperCR0(PVMCPU pVCpu);
282VMMDECL(uint32_t) CPUMGetHyperCR2(PVMCPU pVCpu);
283VMMDECL(uint32_t) CPUMGetHyperCR3(PVMCPU pVCpu);
284VMMDECL(uint32_t) CPUMGetHyperCR4(PVMCPU pVCpu);
285#endif
286/** This register is only saved on fatal traps. */
287VMMDECL(uint32_t) CPUMGetHyperEAX(PVMCPU pVCpu);
288VMMDECL(uint32_t) CPUMGetHyperEBX(PVMCPU pVCpu);
289/** This register is only saved on fatal traps. */
290VMMDECL(uint32_t) CPUMGetHyperECX(PVMCPU pVCpu);
291/** This register is only saved on fatal traps. */
292VMMDECL(uint32_t) CPUMGetHyperEDX(PVMCPU pVCpu);
293VMMDECL(uint32_t) CPUMGetHyperESI(PVMCPU pVCpu);
294VMMDECL(uint32_t) CPUMGetHyperEDI(PVMCPU pVCpu);
295VMMDECL(uint32_t) CPUMGetHyperEBP(PVMCPU pVCpu);
296VMMDECL(uint32_t) CPUMGetHyperESP(PVMCPU pVCpu);
297VMMDECL(uint32_t) CPUMGetHyperEFlags(PVMCPU pVCpu);
298VMMDECL(uint32_t) CPUMGetHyperEIP(PVMCPU pVCpu);
299VMMDECL(uint64_t) CPUMGetHyperRIP(PVMCPU pVCpu);
300VMMDECL(uint32_t) CPUMGetHyperIDTR(PVMCPU pVCpu, uint16_t *pcbLimit);
301VMMDECL(uint32_t) CPUMGetHyperGDTR(PVMCPU pVCpu, uint16_t *pcbLimit);
302VMMDECL(RTSEL) CPUMGetHyperLDTR(PVMCPU pVCpu);
303VMMDECL(RTGCUINTREG) CPUMGetHyperDR0(PVMCPU pVCpu);
304VMMDECL(RTGCUINTREG) CPUMGetHyperDR1(PVMCPU pVCpu);
305VMMDECL(RTGCUINTREG) CPUMGetHyperDR2(PVMCPU pVCpu);
306VMMDECL(RTGCUINTREG) CPUMGetHyperDR3(PVMCPU pVCpu);
307VMMDECL(RTGCUINTREG) CPUMGetHyperDR6(PVMCPU pVCpu);
308VMMDECL(RTGCUINTREG) CPUMGetHyperDR7(PVMCPU pVCpu);
309VMMDECL(void) CPUMGetHyperCtx(PVMCPU pVCpu, PCPUMCTX pCtx);
310VMMDECL(uint32_t) CPUMGetHyperCR3(PVMCPU pVCpu);
311/** @} */
312
313/** @name Hypervisor Register Setters.
314 * @{ */
315VMMDECL(void) CPUMSetHyperGDTR(PVMCPU pVCpu, uint32_t addr, uint16_t limit);
316VMMDECL(void) CPUMSetHyperLDTR(PVMCPU pVCpu, RTSEL SelLDTR);
317VMMDECL(void) CPUMSetHyperIDTR(PVMCPU pVCpu, uint32_t addr, uint16_t limit);
318VMMDECL(void) CPUMSetHyperCR3(PVMCPU pVCpu, uint32_t cr3);
319VMMDECL(void) CPUMSetHyperTR(PVMCPU pVCpu, RTSEL SelTR);
320VMMDECL(void) CPUMSetHyperCS(PVMCPU pVCpu, RTSEL SelCS);
321VMMDECL(void) CPUMSetHyperDS(PVMCPU pVCpu, RTSEL SelDS);
322VMMDECL(void) CPUMSetHyperES(PVMCPU pVCpu, RTSEL SelDS);
323VMMDECL(void) CPUMSetHyperFS(PVMCPU pVCpu, RTSEL SelDS);
324VMMDECL(void) CPUMSetHyperGS(PVMCPU pVCpu, RTSEL SelDS);
325VMMDECL(void) CPUMSetHyperSS(PVMCPU pVCpu, RTSEL SelSS);
326VMMDECL(void) CPUMSetHyperESP(PVMCPU pVCpu, uint32_t u32ESP);
327VMMDECL(int) CPUMSetHyperEFlags(PVMCPU pVCpu, uint32_t Efl);
328VMMDECL(void) CPUMSetHyperEIP(PVMCPU pVCpu, uint32_t u32EIP);
329VMMDECL(void) CPUMSetHyperDR0(PVMCPU pVCpu, RTGCUINTREG uDr0);
330VMMDECL(void) CPUMSetHyperDR1(PVMCPU pVCpu, RTGCUINTREG uDr1);
331VMMDECL(void) CPUMSetHyperDR2(PVMCPU pVCpu, RTGCUINTREG uDr2);
332VMMDECL(void) CPUMSetHyperDR3(PVMCPU pVCpu, RTGCUINTREG uDr3);
333VMMDECL(void) CPUMSetHyperDR6(PVMCPU pVCpu, RTGCUINTREG uDr6);
334VMMDECL(void) CPUMSetHyperDR7(PVMCPU pVCpu, RTGCUINTREG uDr7);
335VMMDECL(void) CPUMSetHyperCtx(PVMCPU pVCpu, const PCPUMCTX pCtx);
336VMMDECL(int) CPUMRecalcHyperDRx(PVMCPU pVCpu);
337/** @} */
338
339VMMDECL(void) CPUMPushHyper(PVMCPU pVCpu, uint32_t u32);
340VMMDECL(void) CPUMHyperSetCtxCore(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore);
341VMMDECL(int) CPUMQueryHyperCtxPtr(PVMCPU pVCpu, PCPUMCTX *ppCtx);
342VMMDECL(PCCPUMCTXCORE) CPUMGetHyperCtxCore(PVMCPU pVCpu);
343VMMDECL(PCPUMCTX) CPUMQueryGuestCtxPtr(PVMCPU pVCpu);
344VMMDECL(PCCPUMCTXCORE) CPUMGetGuestCtxCore(PVMCPU pVCpu);
345VMMDECL(void) CPUMSetGuestCtxCore(PVMCPU pVCpu, PCCPUMCTXCORE pCtxCore);
346VMMR3DECL(int) CPUMR3RawEnter(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore);
347VMMR3DECL(int) CPUMR3RawLeave(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, int rc);
348VMMDECL(uint32_t) CPUMRawGetEFlags(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore);
349VMMDECL(void) CPUMRawSetEFlags(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, uint32_t eflags);
350VMMDECL(int) CPUMHandleLazyFPU(PVMCPU pVCpu);
351
352/** @name Changed flags
353 * These flags are used to keep track of which important register that
354 * have been changed since last they were reset. The only one allowed
355 * to clear them is REM!
356 * @{
357 */
358#define CPUM_CHANGED_FPU_REM RT_BIT(0)
359#define CPUM_CHANGED_CR0 RT_BIT(1)
360#define CPUM_CHANGED_CR4 RT_BIT(2)
361#define CPUM_CHANGED_GLOBAL_TLB_FLUSH RT_BIT(3)
362#define CPUM_CHANGED_CR3 RT_BIT(4)
363#define CPUM_CHANGED_GDTR RT_BIT(5)
364#define CPUM_CHANGED_IDTR RT_BIT(6)
365#define CPUM_CHANGED_LDTR RT_BIT(7)
366#define CPUM_CHANGED_TR RT_BIT(8)
367#define CPUM_CHANGED_SYSENTER_MSR RT_BIT(9)
368#define CPUM_CHANGED_HIDDEN_SEL_REGS RT_BIT(10)
369#define CPUM_CHANGED_CPUID RT_BIT(11)
370#define CPUM_CHANGED_ALL \
371 ( CPUM_CHANGED_FPU_REM | CPUM_CHANGED_CR0 | CPUM_CHANGED_CR3 | CPUM_CHANGED_CR4 | CPUM_CHANGED_GDTR | CPUM_CHANGED_IDTR \
372 | CPUM_CHANGED_LDTR | CPUM_CHANGED_TR | CPUM_CHANGED_SYSENTER_MSR | CPUM_CHANGED_HIDDEN_SEL_REGS | CPUM_CHANGED_CPUID )
373/** This one is used by raw-mode to indicate that the hidden register
374 * information is not longer reliable and have to be re-determined.
375 *
376 * @remarks This must not be part of CPUM_CHANGED_ALL! */
377#define CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID RT_BIT(12)
378/** @} */
379
380VMMDECL(void) CPUMSetChangedFlags(PVMCPU pVCpu, uint32_t fChangedFlags);
381VMMR3DECL(uint32_t) CPUMR3RemEnter(PVMCPU pVCpu, uint32_t *puCpl);
382VMMR3DECL(void) CPUMR3RemLeave(PVMCPU pVCpu, bool fNoOutOfSyncSels);
383VMMDECL(bool) CPUMSupportsFXSR(PVM pVM);
384VMMDECL(bool) CPUMIsHostUsingSysEnter(PVM pVM);
385VMMDECL(bool) CPUMIsHostUsingSysCall(PVM pVM);
386VMMDECL(bool) CPUMIsGuestFPUStateActive(PVMCPU pVCPU);
387VMMDECL(void) CPUMDeactivateGuestFPUState(PVMCPU pVCpu);
388VMMDECL(bool) CPUMIsGuestDebugStateActive(PVMCPU pVCpu);
389VMMDECL(void) CPUMDeactivateGuestDebugState(PVMCPU pVCpu);
390VMMDECL(bool) CPUMIsHyperDebugStateActive(PVMCPU pVCpu);
391VMMDECL(void) CPUMDeactivateHyperDebugState(PVMCPU pVCpu);
392VMMDECL(uint32_t) CPUMGetGuestCPL(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore);
393VMMDECL(bool) CPUMAreHiddenSelRegsValid(PVMCPU pVCpu);
394VMMDECL(CPUMMODE) CPUMGetGuestMode(PVMCPU pVCpu);
395
396
397#ifdef IN_RING3
398/** @defgroup grp_cpum_r3 The CPU Monitor(/Manager) API
399 * @ingroup grp_cpum
400 * @{
401 */
402
403VMMR3DECL(int) CPUMR3Init(PVM pVM);
404VMMR3DECL(void) CPUMR3Relocate(PVM pVM);
405VMMR3DECL(int) CPUMR3Term(PVM pVM);
406VMMR3DECL(void) CPUMR3Reset(PVM pVM);
407VMMR3DECL(void) CPUMR3ResetCpu(PVMCPU pVCpu);
408VMMDECL(bool) CPUMR3IsStateRestorePending(PVM pVM);
409VMMR3DECL(void) CPUMR3SetHWVirtEx(PVM pVM, bool fHWVirtExEnabled);
410# ifdef DEBUG
411VMMR3DECL(void) CPUMR3SaveEntryCtx(PVM pVM);
412# endif
413VMMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd);
414VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdStdRCPtr(PVM pVM);
415VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdExtRCPtr(PVM pVM);
416VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdCentaurRCPtr(PVM pVM);
417VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdDefRCPtr(PVM pVM);
418
419/** @} */
420#endif /* IN_RING3 */
421
422#ifdef IN_RC
423/** @defgroup grp_cpum_gc The CPU Monitor(/Manager) API
424 * @ingroup grp_cpum
425 * @{
426 */
427
428/**
429 * Calls a guest trap/interrupt handler directly
430 *
431 * Assumes a trap stack frame has already been setup on the guest's stack!
432 * This function does not return!
433 *
434 * @param pRegFrame Original trap/interrupt context
435 * @param selCS Code selector of handler
436 * @param pHandler GC virtual address of handler
437 * @param eflags Callee's EFLAGS
438 * @param selSS Stack selector for handler
439 * @param pEsp Stack address for handler
440 */
441DECLASM(void) CPUMGCCallGuestTrapHandler(PCPUMCTXCORE pRegFrame, uint32_t selCS, RTRCPTR pHandler,
442 uint32_t eflags, uint32_t selSS, RTRCPTR pEsp);
443
444/**
445 * Call guest V86 code directly.
446 *
447 * This function does not return!
448 *
449 * @param pRegFrame Original trap/interrupt context
450 */
451DECLASM(void) CPUMGCCallV86Code(PCPUMCTXCORE pRegFrame);
452
453/** @} */
454#endif /* IN_RC */
455
456#ifdef IN_RING0
457/** @defgroup grp_cpum_r0 The CPU Monitor(/Manager) API
458 * @ingroup grp_cpum
459 * @{
460 */
461VMMR0DECL(int) CPUMR0ModuleInit();
462VMMR0DECL(int) CPUMR0ModuleTerm();
463VMMR0DECL(int) CPUMR0Init(PVM pVM);
464VMMR0DECL(int) CPUMR0LoadGuestFPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
465VMMR0DECL(int) CPUMR0SaveGuestFPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
466VMMR0DECL(int) CPUMR0SaveGuestDebugState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, bool fDR6);
467VMMR0DECL(int) CPUMR0LoadGuestDebugState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, bool fDR6);
468VMMR0DECL(int) CPUMR0LoadHostDebugState(PVM pVM, PVMCPU pVCpu);
469VMMR0DECL(int) CPUMR0SaveHostDebugState(PVM pVM, PVMCPU pVCpu);
470VMMR0DECL(int) CPUMR0LoadHyperDebugState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, bool fDR6);
471#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
472VMMR0DECL(void) CPUMR0SetLApic(PVM pVM, RTCPUID idHostCpu);
473#endif
474
475/** @} */
476#endif /* IN_RING0 */
477
478/** @} */
479RT_C_DECLS_END
480
481
482#endif
483
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