VirtualBox

source: vbox/trunk/include/VBox/cpum.h@ 7581

Last change on this file since 7581 was 7133, checked in by vboxsync, 17 years ago

Eliminate cpum.h dependency (shuts up a bunch of .c warnings). Fixed the header tests.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 26.9 KB
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1/** @file
2 * CPUM - CPU Monitor(/ Manager).
3 */
4
5/*
6 * Copyright (C) 2006-2007 innotek GmbH
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * The contents of this file may alternatively be used under the terms
17 * of the Common Development and Distribution License Version 1.0
18 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19 * VirtualBox OSE distribution, in which case the provisions of the
20 * CDDL are applicable instead of those of the GPL.
21 *
22 * You may elect to license modified versions of this file under the
23 * terms and conditions of either the GPL or the CDDL or both.
24 */
25
26#ifndef ___VBox_cpum_h
27#define ___VBox_cpum_h
28
29#include <VBox/cdefs.h>
30#include <VBox/types.h>
31#include <VBox/x86.h>
32
33
34__BEGIN_DECLS
35
36/** @defgroup grp_cpum The CPU Monitor(/Manager) API
37 * @{
38 */
39
40/**
41 * Selector hidden registers.
42 */
43typedef struct CPUMSELREGHID
44{
45 /** Base register. */
46 uint32_t u32Base;
47 /** Limit (expanded). */
48 uint32_t u32Limit;
49 /** Flags.
50 * This is the high 32-bit word of the descriptor entry.
51 * Only the flags, dpl and type are used. */
52 X86DESCATTR Attr;
53} CPUMSELREGHID;
54
55
56/**
57 * The sysenter register set.
58 */
59typedef struct CPUMSYSENTER
60{
61 /** Ring 0 cs.
62 * This value + 8 is the Ring 0 ss.
63 * This value + 16 is the Ring 3 cs.
64 * This value + 24 is the Ring 3 ss.
65 */
66 uint64_t cs;
67 /** Ring 0 eip. */
68 uint64_t eip;
69 /** Ring 0 esp. */
70 uint64_t esp;
71} CPUMSYSENTER;
72
73
74/**
75 * CPU context core.
76 */
77#pragma pack(1)
78typedef struct CPUMCTXCORE
79{
80 union
81 {
82 uint32_t edi;
83 uint64_t rdi;
84 };
85 union
86 {
87 uint32_t esi;
88 uint64_t rsi;
89 };
90 union
91 {
92 uint32_t ebp;
93 uint64_t rbp;
94 };
95 union
96 {
97 uint32_t eax;
98 uint64_t rax;
99 };
100 union
101 {
102 uint32_t ebx;
103 uint64_t rbx;
104 };
105 union
106 {
107 uint32_t edx;
108 uint64_t rdx;
109 };
110 union
111 {
112 uint32_t ecx;
113 uint64_t rcx;
114 };
115 /* Note: we rely on the exact layout, because we use lss esp, [] in the switcher */
116 uint32_t esp;
117 RTSEL ss;
118 RTSEL ssPadding;
119 /* Note: no overlap with esp here. */
120 uint64_t rsp;
121
122 RTSEL gs;
123 RTSEL gsPadding;
124 RTSEL fs;
125 RTSEL fsPadding;
126 RTSEL es;
127 RTSEL esPadding;
128 RTSEL ds;
129 RTSEL dsPadding;
130 RTSEL cs;
131 RTSEL csPadding[3]; /* 3 words to force 8 byte alignment for the remainder */
132
133 union
134 {
135 X86EFLAGS eflags;
136 X86RFLAGS rflags;
137 };
138 union
139 {
140 uint32_t eip;
141 uint64_t rip;
142 };
143
144 uint64_t r8;
145 uint64_t r9;
146 uint64_t r10;
147 uint64_t r11;
148 uint64_t r12;
149 uint64_t r13;
150 uint64_t r14;
151 uint64_t r15;
152
153 /** Hidden selector registers.
154 * @{ */
155 CPUMSELREGHID esHid;
156 CPUMSELREGHID csHid;
157 CPUMSELREGHID ssHid;
158 CPUMSELREGHID dsHid;
159 CPUMSELREGHID fsHid;
160 CPUMSELREGHID gsHid;
161 /** @} */
162
163} CPUMCTXCORE;
164#pragma pack()
165
166
167/**
168 * CPU context.
169 */
170#pragma pack(1)
171typedef struct CPUMCTX
172{
173 /** FPU state. (16-byte alignment)
174 * @todo This doesn't have to be in X86FXSTATE on CPUs without fxsr - we need a type for the
175 * actual format or convert it (waste of time). */
176 X86FXSTATE fpu;
177
178 /** CPUMCTXCORE Part.
179 * @{ */
180 union
181 {
182 uint32_t edi;
183 uint64_t rdi;
184 };
185 union
186 {
187 uint32_t esi;
188 uint64_t rsi;
189 };
190 union
191 {
192 uint32_t ebp;
193 uint64_t rbp;
194 };
195 union
196 {
197 uint32_t eax;
198 uint64_t rax;
199 };
200 union
201 {
202 uint32_t ebx;
203 uint64_t rbx;
204 };
205 union
206 {
207 uint32_t edx;
208 uint64_t rdx;
209 };
210 union
211 {
212 uint32_t ecx;
213 uint64_t rcx;
214 };
215 /* Note: we rely on the exact layout, because we use lss esp, [] in the switcher */
216 uint32_t esp;
217 RTSEL ss;
218 RTSEL ssPadding;
219 /* Note: no overlap with esp here. */
220 uint64_t rsp;
221
222 RTSEL gs;
223 RTSEL gsPadding;
224 RTSEL fs;
225 RTSEL fsPadding;
226 RTSEL es;
227 RTSEL esPadding;
228 RTSEL ds;
229 RTSEL dsPadding;
230 RTSEL cs;
231 RTSEL csPadding[3]; /* 3 words to force 8 byte alignment for the remainder */
232
233 union
234 {
235 X86EFLAGS eflags;
236 X86RFLAGS rflags;
237 };
238 union
239 {
240 uint32_t eip;
241 uint64_t rip;
242 };
243
244 uint64_t r8;
245 uint64_t r9;
246 uint64_t r10;
247 uint64_t r11;
248 uint64_t r12;
249 uint64_t r13;
250 uint64_t r14;
251 uint64_t r15;
252
253 /** Hidden selector registers.
254 * @{ */
255 CPUMSELREGHID esHid;
256 CPUMSELREGHID csHid;
257 CPUMSELREGHID ssHid;
258 CPUMSELREGHID dsHid;
259 CPUMSELREGHID fsHid;
260 CPUMSELREGHID gsHid;
261 /** @} */
262
263 /** @} */
264
265 /** Control registers.
266 * @{ */
267 uint64_t cr0;
268 uint64_t cr2;
269 uint64_t cr3;
270 uint64_t cr4;
271 uint64_t cr8;
272 /** @} */
273
274 /** Debug registers.
275 * @{ */
276 uint64_t dr0;
277 uint64_t dr1;
278 uint64_t dr2;
279 uint64_t dr3;
280 uint64_t dr4; /**< @todo remove dr4 and dr5. */
281 uint64_t dr5;
282 uint64_t dr6;
283 uint64_t dr7;
284 /* DR8-15 are currently not supported */
285 /** @} */
286
287 /** Global Descriptor Table register. */
288 VBOXGDTR gdtr;
289 uint16_t gdtrPadding;
290 uint32_t gdtrPadding64;/** @todo fix this hack */
291 /** Interrupt Descriptor Table register. */
292 VBOXIDTR idtr;
293 uint16_t idtrPadding;
294 uint32_t idtrPadding64;/** @todo fix this hack */
295 /** The task register.
296 * Only the guest context uses all the members. */
297 RTSEL ldtr;
298 RTSEL ldtrPadding;
299 /** The task register.
300 * Only the guest context uses all the members. */
301 RTSEL tr;
302 RTSEL trPadding;
303
304 /** The sysenter msr registers.
305 * This member is not used by the hypervisor context. */
306 CPUMSYSENTER SysEnter;
307
308 /** Hidden selector registers.
309 * @{ */
310 CPUMSELREGHID ldtrHid;
311 CPUMSELREGHID trHid;
312 /** @} */
313
314 /* padding to get 32byte aligned size */
315 uint32_t padding[4];
316} CPUMCTX;
317#pragma pack()
318
319/**
320 * Gets the CPUMCTXCORE part of a CPUMCTX.
321 */
322#define CPUMCTX2CORE(pCtx) ((PCPUMCTXCORE)(void *)&(pCtx)->edi)
323
324/**
325 * The register set returned by a CPUID operation.
326 */
327typedef struct CPUMCPUID
328{
329 uint32_t eax;
330 uint32_t ebx;
331 uint32_t ecx;
332 uint32_t edx;
333} CPUMCPUID;
334/** Pointer to a CPUID leaf. */
335typedef CPUMCPUID *PCPUMCPUID;
336/** Pointer to a const CPUID leaf. */
337typedef const CPUMCPUID *PCCPUMCPUID;
338
339/**
340 * CPUID feature to set or clear.
341 */
342typedef enum CPUMCPUIDFEATURE
343{
344 CPUMCPUIDFEATURE_INVALID = 0,
345 /** The APIC feature bit. (Std+Ext) */
346 CPUMCPUIDFEATURE_APIC,
347 /** The sysenter/sysexit feature bit. (Std+Ext) */
348 CPUMCPUIDFEATURE_SEP
349} CPUMCPUIDFEATURE;
350
351
352/** @name Guest Register Getters.
353 * @{ */
354CPUMDECL(void) CPUMGetGuestGDTR(PVM pVM, PVBOXGDTR pGDTR);
355CPUMDECL(uint32_t) CPUMGetGuestIDTR(PVM pVM, uint16_t *pcbLimit);
356CPUMDECL(RTSEL) CPUMGetGuestTR(PVM pVM);
357CPUMDECL(RTSEL) CPUMGetGuestLDTR(PVM pVM);
358CPUMDECL(uint32_t) CPUMGetGuestCR0(PVM pVM);
359CPUMDECL(uint32_t) CPUMGetGuestCR2(PVM pVM);
360CPUMDECL(uint32_t) CPUMGetGuestCR3(PVM pVM);
361CPUMDECL(uint32_t) CPUMGetGuestCR4(PVM pVM);
362CPUMDECL(int) CPUMGetGuestCRx(PVM pVM, uint32_t iReg, uint32_t *pValue);
363CPUMDECL(uint32_t) CPUMGetGuestEFlags(PVM pVM);
364CPUMDECL(uint32_t) CPUMGetGuestEIP(PVM pVM);
365CPUMDECL(uint32_t) CPUMGetGuestEAX(PVM pVM);
366CPUMDECL(uint32_t) CPUMGetGuestEBX(PVM pVM);
367CPUMDECL(uint32_t) CPUMGetGuestECX(PVM pVM);
368CPUMDECL(uint32_t) CPUMGetGuestEDX(PVM pVM);
369CPUMDECL(uint32_t) CPUMGetGuestESI(PVM pVM);
370CPUMDECL(uint32_t) CPUMGetGuestEDI(PVM pVM);
371CPUMDECL(uint32_t) CPUMGetGuestESP(PVM pVM);
372CPUMDECL(uint32_t) CPUMGetGuestEBP(PVM pVM);
373CPUMDECL(RTSEL) CPUMGetGuestCS(PVM pVM);
374CPUMDECL(RTSEL) CPUMGetGuestDS(PVM pVM);
375CPUMDECL(RTSEL) CPUMGetGuestES(PVM pVM);
376CPUMDECL(RTSEL) CPUMGetGuestFS(PVM pVM);
377CPUMDECL(RTSEL) CPUMGetGuestGS(PVM pVM);
378CPUMDECL(RTSEL) CPUMGetGuestSS(PVM pVM);
379CPUMDECL(RTUINTREG) CPUMGetGuestDR0(PVM pVM);
380CPUMDECL(RTUINTREG) CPUMGetGuestDR1(PVM pVM);
381CPUMDECL(RTUINTREG) CPUMGetGuestDR2(PVM pVM);
382CPUMDECL(RTUINTREG) CPUMGetGuestDR3(PVM pVM);
383CPUMDECL(RTUINTREG) CPUMGetGuestDR6(PVM pVM);
384CPUMDECL(RTUINTREG) CPUMGetGuestDR7(PVM pVM);
385CPUMDECL(int) CPUMGetGuestDRx(PVM pVM, uint32_t iReg, uint32_t *pValue);
386CPUMDECL(void) CPUMGetGuestCpuId(PVM pVM, uint32_t iLeaf, uint32_t *pEax, uint32_t *pEbx, uint32_t *pEcx, uint32_t *pEdx);
387CPUMDECL(GCPTRTYPE(PCCPUMCPUID)) CPUMGetGuestCpuIdStdGCPtr(PVM pVM);
388CPUMDECL(GCPTRTYPE(PCCPUMCPUID)) CPUMGetGuestCpuIdExtGCPtr(PVM pVM);
389CPUMDECL(GCPTRTYPE(PCCPUMCPUID)) CPUMGetGuestCpuIdCentaurGCPtr(PVM pVM);
390CPUMDECL(GCPTRTYPE(PCCPUMCPUID)) CPUMGetGuestCpuIdDefGCPtr(PVM pVM);
391CPUMDECL(uint32_t) CPUMGetGuestCpuIdStdMax(PVM pVM);
392CPUMDECL(uint32_t) CPUMGetGuestCpuIdExtMax(PVM pVM);
393CPUMDECL(uint32_t) CPUMGetGuestCpuIdCentaurMax(PVM pVM);
394CPUMDECL(CPUMSELREGHID *) CPUMGetGuestTRHid(PVM pVM);
395/** @} */
396
397/** @name Guest Register Setters.
398 * @{ */
399CPUMDECL(int) CPUMSetGuestGDTR(PVM pVM, uint32_t addr, uint16_t limit);
400CPUMDECL(int) CPUMSetGuestIDTR(PVM pVM, uint32_t addr, uint16_t limit);
401CPUMDECL(int) CPUMSetGuestTR(PVM pVM, uint16_t tr);
402CPUMDECL(int) CPUMSetGuestLDTR(PVM pVM, uint16_t ldtr);
403CPUMDECL(int) CPUMSetGuestCR0(PVM pVM, uint32_t cr0);
404CPUMDECL(int) CPUMSetGuestCR2(PVM pVM, uint32_t cr2);
405CPUMDECL(int) CPUMSetGuestCR3(PVM pVM, uint32_t cr3);
406CPUMDECL(int) CPUMSetGuestCR4(PVM pVM, uint32_t cr4);
407CPUMDECL(int) CPUMSetGuestCRx(PVM pVM, uint32_t iReg, uint32_t Value);
408CPUMDECL(int) CPUMSetGuestDR0(PVM pVM, RTGCUINTREG uDr0);
409CPUMDECL(int) CPUMSetGuestDR1(PVM pVM, RTGCUINTREG uDr1);
410CPUMDECL(int) CPUMSetGuestDR2(PVM pVM, RTGCUINTREG uDr2);
411CPUMDECL(int) CPUMSetGuestDR3(PVM pVM, RTGCUINTREG uDr3);
412CPUMDECL(int) CPUMSetGuestDR6(PVM pVM, RTGCUINTREG uDr6);
413CPUMDECL(int) CPUMSetGuestDR7(PVM pVM, RTGCUINTREG uDr7);
414CPUMDECL(int) CPUMSetGuestDRx(PVM pVM, uint32_t iReg, uint32_t Value);
415CPUMDECL(int) CPUMSetGuestEFlags(PVM pVM, uint32_t eflags);
416CPUMDECL(int) CPUMSetGuestEIP(PVM pVM, uint32_t eip);
417CPUMDECL(int) CPUMSetGuestEAX(PVM pVM, uint32_t eax);
418CPUMDECL(int) CPUMSetGuestEBX(PVM pVM, uint32_t ebx);
419CPUMDECL(int) CPUMSetGuestECX(PVM pVM, uint32_t ecx);
420CPUMDECL(int) CPUMSetGuestEDX(PVM pVM, uint32_t edx);
421CPUMDECL(int) CPUMSetGuestESI(PVM pVM, uint32_t esi);
422CPUMDECL(int) CPUMSetGuestEDI(PVM pVM, uint32_t edi);
423CPUMDECL(int) CPUMSetGuestESP(PVM pVM, uint32_t esp);
424CPUMDECL(int) CPUMSetGuestEBP(PVM pVM, uint32_t ebp);
425CPUMDECL(int) CPUMSetGuestCS(PVM pVM, uint16_t cs);
426CPUMDECL(int) CPUMSetGuestDS(PVM pVM, uint16_t ds);
427CPUMDECL(int) CPUMSetGuestES(PVM pVM, uint16_t es);
428CPUMDECL(int) CPUMSetGuestFS(PVM pVM, uint16_t fs);
429CPUMDECL(int) CPUMSetGuestGS(PVM pVM, uint16_t gs);
430CPUMDECL(int) CPUMSetGuestSS(PVM pVM, uint16_t ss);
431CPUMDECL(void) CPUMSetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature);
432CPUMDECL(void) CPUMClearGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature);
433CPUMDECL(void) CPUMSetGuestCtx(PVM pVM, const PCPUMCTX pCtx);
434/** @} */
435
436/** @name Misc Guest Predicate Functions.
437 * @{ */
438
439/**
440 * Tests if the guest is running in real mode or not.
441 *
442 * @returns true if in real mode, otherwise false.
443 * @param pVM The VM handle.
444 */
445DECLINLINE(bool) CPUMIsGuestInRealMode(PVM pVM)
446{
447 return !(CPUMGetGuestCR0(pVM) & X86_CR0_PE);
448}
449
450/**
451 * Tests if the guest is running in protected or not.
452 *
453 * @returns true if in protected mode, otherwise false.
454 * @param pVM The VM handle.
455 */
456DECLINLINE(bool) CPUMIsGuestInProtectedMode(PVM pVM)
457{
458 return !!(CPUMGetGuestCR0(pVM) & X86_CR0_PE);
459}
460
461/**
462 * Tests if the guest is running in paged protected or not.
463 *
464 * @returns true if in paged protected mode, otherwise false.
465 * @param pVM The VM handle.
466 */
467DECLINLINE(bool) CPUMIsGuestInPagedProtectedMode(PVM pVM)
468{
469 return (CPUMGetGuestCR0(pVM) & (X86_CR0_PE | X86_CR0_PG)) == (X86_CR0_PE | X86_CR0_PG);
470}
471
472/**
473 * Tests if the guest is running in paged protected or not.
474 *
475 * @returns true if in paged protected mode, otherwise false.
476 * @param pVM The VM handle.
477 */
478CPUMDECL(bool) CPUMIsGuestIn16BitCode(PVM pVM);
479
480/**
481 * Tests if the guest is running in paged protected or not.
482 *
483 * @returns true if in paged protected mode, otherwise false.
484 * @param pVM The VM handle.
485 */
486CPUMDECL(bool) CPUMIsGuestIn32BitCode(PVM pVM);
487
488/**
489 * Tests if the guest is running in paged protected or not.
490 *
491 * @returns true if in paged protected mode, otherwise false.
492 * @param pVM The VM handle.
493 */
494CPUMDECL(bool) CPUMIsGuestIn64BitCode(PVM pVM);
495
496/** @} */
497
498
499
500/** @name Hypervisor Register Getters.
501 * @{ */
502CPUMDECL(RTSEL) CPUMGetHyperCS(PVM pVM);
503CPUMDECL(RTSEL) CPUMGetHyperDS(PVM pVM);
504CPUMDECL(RTSEL) CPUMGetHyperES(PVM pVM);
505CPUMDECL(RTSEL) CPUMGetHyperFS(PVM pVM);
506CPUMDECL(RTSEL) CPUMGetHyperGS(PVM pVM);
507CPUMDECL(RTSEL) CPUMGetHyperSS(PVM pVM);
508#if 0 /* these are not correct. */
509CPUMDECL(uint32_t) CPUMGetHyperCR0(PVM pVM);
510CPUMDECL(uint32_t) CPUMGetHyperCR2(PVM pVM);
511CPUMDECL(uint32_t) CPUMGetHyperCR3(PVM pVM);
512CPUMDECL(uint32_t) CPUMGetHyperCR4(PVM pVM);
513#endif
514/** This register is only saved on fatal traps. */
515CPUMDECL(uint32_t) CPUMGetHyperEAX(PVM pVM);
516CPUMDECL(uint32_t) CPUMGetHyperEBX(PVM pVM);
517/** This register is only saved on fatal traps. */
518CPUMDECL(uint32_t) CPUMGetHyperECX(PVM pVM);
519/** This register is only saved on fatal traps. */
520CPUMDECL(uint32_t) CPUMGetHyperEDX(PVM pVM);
521CPUMDECL(uint32_t) CPUMGetHyperESI(PVM pVM);
522CPUMDECL(uint32_t) CPUMGetHyperEDI(PVM pVM);
523CPUMDECL(uint32_t) CPUMGetHyperEBP(PVM pVM);
524CPUMDECL(uint32_t) CPUMGetHyperESP(PVM pVM);
525CPUMDECL(uint32_t) CPUMGetHyperEFlags(PVM pVM);
526CPUMDECL(uint32_t) CPUMGetHyperEIP(PVM pVM);
527CPUMDECL(uint32_t) CPUMGetHyperIDTR(PVM pVM, uint16_t *pcbLimit);
528CPUMDECL(uint32_t) CPUMGetHyperGDTR(PVM pVM, uint16_t *pcbLimit);
529CPUMDECL(RTSEL) CPUMGetHyperLDTR(PVM pVM);
530CPUMDECL(RTGCUINTREG) CPUMGetHyperDR0(PVM pVM);
531CPUMDECL(RTGCUINTREG) CPUMGetHyperDR1(PVM pVM);
532CPUMDECL(RTGCUINTREG) CPUMGetHyperDR2(PVM pVM);
533CPUMDECL(RTGCUINTREG) CPUMGetHyperDR3(PVM pVM);
534CPUMDECL(RTGCUINTREG) CPUMGetHyperDR6(PVM pVM);
535CPUMDECL(RTGCUINTREG) CPUMGetHyperDR7(PVM pVM);
536CPUMDECL(void) CPUMGetHyperCtx(PVM pVM, PCPUMCTX pCtx);
537/** @} */
538
539/** @name Hypervisor Register Setters.
540 * @{ */
541CPUMDECL(void) CPUMSetHyperGDTR(PVM pVM, uint32_t addr, uint16_t limit);
542CPUMDECL(void) CPUMSetHyperLDTR(PVM pVM, RTSEL SelLDTR);
543CPUMDECL(void) CPUMSetHyperIDTR(PVM pVM, uint32_t addr, uint16_t limit);
544CPUMDECL(void) CPUMSetHyperCR3(PVM pVM, uint32_t cr3);
545CPUMDECL(void) CPUMSetHyperTR(PVM pVM, RTSEL SelTR);
546CPUMDECL(void) CPUMSetHyperCS(PVM pVM, RTSEL SelCS);
547CPUMDECL(void) CPUMSetHyperDS(PVM pVM, RTSEL SelDS);
548CPUMDECL(void) CPUMSetHyperES(PVM pVM, RTSEL SelDS);
549CPUMDECL(void) CPUMSetHyperFS(PVM pVM, RTSEL SelDS);
550CPUMDECL(void) CPUMSetHyperGS(PVM pVM, RTSEL SelDS);
551CPUMDECL(void) CPUMSetHyperSS(PVM pVM, RTSEL SelSS);
552CPUMDECL(void) CPUMSetHyperESP(PVM pVM, uint32_t u32ESP);
553CPUMDECL(int) CPUMSetHyperEFlags(PVM pVM, uint32_t Efl);
554CPUMDECL(void) CPUMSetHyperEIP(PVM pVM, uint32_t u32EIP);
555CPUMDECL(void) CPUMSetHyperDR0(PVM pVM, RTGCUINTREG uDr0);
556CPUMDECL(void) CPUMSetHyperDR1(PVM pVM, RTGCUINTREG uDr1);
557CPUMDECL(void) CPUMSetHyperDR2(PVM pVM, RTGCUINTREG uDr2);
558CPUMDECL(void) CPUMSetHyperDR3(PVM pVM, RTGCUINTREG uDr3);
559CPUMDECL(void) CPUMSetHyperDR6(PVM pVM, RTGCUINTREG uDr6);
560CPUMDECL(void) CPUMSetHyperDR7(PVM pVM, RTGCUINTREG uDr7);
561CPUMDECL(void) CPUMSetHyperCtx(PVM pVM, const PCPUMCTX pCtx);
562CPUMDECL(int) CPUMRecalcHyperDRx(PVM pVM);
563/** @} */
564
565CPUMDECL(void) CPUMPushHyper(PVM pVM, uint32_t u32);
566
567/**
568 * Sets or resets an alternative hypervisor context core.
569 *
570 * This is called when we get a hypervisor trap set switch the context
571 * core with the trap frame on the stack. It is called again to reset
572 * back to the default context core when resuming hypervisor execution.
573 *
574 * @param pVM The VM handle.
575 * @param pCtxCore Pointer to the alternative context core or NULL
576 * to go back to the default context core.
577 */
578CPUMDECL(void) CPUMHyperSetCtxCore(PVM pVM, PCPUMCTXCORE pCtxCore);
579
580
581/**
582 * Queries the pointer to the internal CPUMCTX structure
583 *
584 * @returns VBox status code.
585 * @param pVM Handle to the virtual machine.
586 * @param ppCtx Receives the CPUMCTX pointer when successful.
587 */
588CPUMDECL(int) CPUMQueryGuestCtxPtr(PVM pVM, PCPUMCTX *ppCtx);
589
590/**
591 * Queries the pointer to the internal CPUMCTX structure for the hypervisor.
592 *
593 * @returns VBox status code.
594 * @param pVM Handle to the virtual machine.
595 * @param ppCtx Receives the hyper CPUMCTX pointer when successful.
596 */
597CPUMDECL(int) CPUMQueryHyperCtxPtr(PVM pVM, PCPUMCTX *ppCtx);
598
599
600/**
601 * Gets the pointer to the internal CPUMCTXCORE structure.
602 * This is only for reading in order to save a few calls.
603 *
604 * @param pVM Handle to the virtual machine.
605 */
606CPUMDECL(PCCPUMCTXCORE) CPUMGetGuestCtxCore(PVM pVM);
607
608/**
609 * Gets the pointer to the internal CPUMCTXCORE structure for the hypervisor.
610 * This is only for reading in order to save a few calls.
611 *
612 * @param pVM Handle to the virtual machine.
613 */
614CPUMDECL(PCCPUMCTXCORE) CPUMGetHyperCtxCore(PVM pVM);
615
616/**
617 * Sets the guest context core registers.
618 *
619 * @param pVM Handle to the virtual machine.
620 * @param pCtxCore The new context core values.
621 */
622CPUMDECL(void) CPUMSetGuestCtxCore(PVM pVM, PCCPUMCTXCORE pCtxCore);
623
624
625/**
626 * Transforms the guest CPU state to raw-ring mode.
627 *
628 * This function will change the any of the cs and ss register with DPL=0 to DPL=1.
629 *
630 * @returns VBox status. (recompiler failure)
631 * @param pVM VM handle.
632 * @param pCtxCore The context core (for trap usage).
633 * @see @ref pg_raw
634 */
635CPUMDECL(int) CPUMRawEnter(PVM pVM, PCPUMCTXCORE pCtxCore);
636
637/**
638 * Transforms the guest CPU state from raw-ring mode to correct values.
639 *
640 * This function will change any selector registers with DPL=1 to DPL=0.
641 *
642 * @returns Adjusted rc.
643 * @param pVM VM handle.
644 * @param rc Raw mode return code
645 * @param pCtxCore The context core (for trap usage).
646 * @see @ref pg_raw
647 */
648CPUMDECL(int) CPUMRawLeave(PVM pVM, PCPUMCTXCORE pCtxCore, int rc);
649
650/**
651 * Gets the EFLAGS while we're in raw-mode.
652 *
653 * @returns The eflags.
654 * @param pVM The VM handle.
655 * @param pCtxCore The context core.
656 */
657CPUMDECL(uint32_t) CPUMRawGetEFlags(PVM pVM, PCPUMCTXCORE pCtxCore);
658
659/**
660 * Updates the EFLAGS while we're in raw-mode.
661 *
662 * @param pVM The VM handle.
663 * @param pCtxCore The context core.
664 * @param eflags The new EFLAGS value.
665 */
666CPUMDECL(void) CPUMRawSetEFlags(PVM pVM, PCPUMCTXCORE pCtxCore, uint32_t eflags);
667
668/**
669 * Lazily sync in the FPU/XMM state
670 *
671 * This function will change any selector registers with DPL=1 to DPL=0.
672 *
673 * @returns VBox status code.
674 * @param pVM VM handle.
675 */
676CPUMDECL(int) CPUMHandleLazyFPU(PVM pVM);
677
678
679/**
680 * Restore host FPU/XMM state
681 *
682 * @returns VBox status code.
683 * @param pVM VM handle.
684 */
685CPUMDECL(int) CPUMRestoreHostFPUState(PVM pVM);
686
687/** @name Changed flags
688 * These flags are used to keep track of which important register that
689 * have been changed since last they were reset. The only one allowed
690 * to clear them is REM!
691 * @{
692 */
693#define CPUM_CHANGED_FPU_REM RT_BIT(0)
694#define CPUM_CHANGED_CR0 RT_BIT(1)
695#define CPUM_CHANGED_CR4 RT_BIT(2)
696#define CPUM_CHANGED_GLOBAL_TLB_FLUSH RT_BIT(3)
697#define CPUM_CHANGED_CR3 RT_BIT(4)
698#define CPUM_CHANGED_GDTR RT_BIT(5)
699#define CPUM_CHANGED_IDTR RT_BIT(6)
700#define CPUM_CHANGED_LDTR RT_BIT(7)
701#define CPUM_CHANGED_TR RT_BIT(8)
702#define CPUM_CHANGED_SYSENTER_MSR RT_BIT(9)
703#define CPUM_CHANGED_HIDDEN_SEL_REGS RT_BIT(10)
704/** @} */
705
706/**
707 * Gets and resets the changed flags (CPUM_CHANGED_*).
708 *
709 * @returns The changed flags.
710 * @param pVM VM handle.
711 */
712CPUMDECL(unsigned) CPUMGetAndClearChangedFlagsREM(PVM pVM);
713
714/**
715 * Sets the specified changed flags (CPUM_CHANGED_*).
716 *
717 * @param pVM The VM handle.
718 */
719CPUMDECL(void) CPUMSetChangedFlags(PVM pVM, uint32_t fChangedFlags);
720
721/**
722 * Checks if the CPU supports the FXSAVE and FXRSTOR instruction.
723 * @returns true if supported.
724 * @returns false if not supported.
725 * @param pVM The VM handle.
726 */
727CPUMDECL(bool) CPUMSupportsFXSR(PVM pVM);
728
729/**
730 * Checks if the host OS uses the SYSENTER / SYSEXIT instructions.
731 * @returns true if used.
732 * @returns false if not used.
733 * @param pVM The VM handle.
734 */
735CPUMDECL(bool) CPUMIsHostUsingSysEnter(PVM pVM);
736
737/**
738 * Checks if the host OS uses the SYSCALL / SYSRET instructions.
739 * @returns true if used.
740 * @returns false if not used.
741 * @param pVM The VM handle.
742 */
743CPUMDECL(bool) CPUMIsHostUsingSysCall(PVM pVM);
744
745/**
746 * Checks if we activated the FPU/XMM state of the guest OS
747 * @returns true if we did.
748 * @returns false if not.
749 * @param pVM The VM handle.
750 */
751CPUMDECL(bool) CPUMIsGuestFPUStateActive(PVM pVM);
752
753/**
754 * Deactivate the FPU/XMM state of the guest OS
755 * @param pVM The VM handle.
756 */
757CPUMDECL(void) CPUMDeactivateGuestFPUState(PVM pVM);
758
759
760/**
761 * Checks if the hidden selector registers are valid
762 * @returns true if they are.
763 * @returns false if not.
764 * @param pVM The VM handle.
765 */
766CPUMDECL(bool) CPUMAreHiddenSelRegsValid(PVM pVM);
767
768/**
769 * Checks if the hidden selector registers are valid
770 * @param pVM The VM handle.
771 * @param fValid Valid or not
772 */
773CPUMDECL(void) CPUMSetHiddenSelRegsValid(PVM pVM, bool fValid);
774
775/**
776 * Get the current privilege level of the guest.
777 *
778 * @returns cpl
779 * @param pVM VM Handle.
780 * @param pRegFrame Trap register frame.
781 */
782CPUMDECL(uint32_t) CPUMGetGuestCPL(PVM pVM, PCPUMCTXCORE pCtxCore);
783
784/**
785 * CPU modes.
786 */
787typedef enum CPUMMODE
788{
789 /** The usual invalid zero entry. */
790 CPUMMODE_INVALID = 0,
791 /** Real mode. */
792 CPUMMODE_REAL,
793 /** Protected mode (32-bit). */
794 CPUMMODE_PROTECTED,
795 /** Long mode (64-bit). */
796 CPUMMODE_LONG
797} CPUMMODE;
798
799/**
800 * Gets the current guest CPU mode.
801 *
802 * If paging mode is what you need, check out PGMGetGuestMode().
803 *
804 * @returns The CPU mode.
805 * @param pVM The VM handle.
806 */
807CPUMDECL(CPUMMODE) CPUMGetGuestMode(PVM pVM);
808
809
810#ifdef IN_RING3
811/** @defgroup grp_cpum_r3 The CPU Monitor(/Manager) API
812 * @ingroup grp_cpum
813 * @{
814 */
815
816/**
817 * Initializes the CPUM.
818 *
819 * @returns VBox status code.
820 * @param pVM The VM to operate on.
821 */
822CPUMR3DECL(int) CPUMR3Init(PVM pVM);
823
824/**
825 * Applies relocations to data and code managed by this
826 * component. This function will be called at init and
827 * whenever the VMM need to relocate it self inside the GC.
828 *
829 * The CPUM will update the addresses used by the switcher.
830 *
831 * @param pVM The VM.
832 */
833CPUMR3DECL(void) CPUMR3Relocate(PVM pVM);
834
835/**
836 * Terminates the CPUM.
837 *
838 * Termination means cleaning up and freeing all resources,
839 * the VM it self is at this point powered off or suspended.
840 *
841 * @returns VBox status code.
842 * @param pVM The VM to operate on.
843 */
844CPUMR3DECL(int) CPUMR3Term(PVM pVM);
845
846/**
847 * Resets the CPU.
848 *
849 * @param pVM The VM handle.
850 */
851CPUMR3DECL(void) CPUMR3Reset(PVM pVM);
852
853/**
854 * Queries the pointer to the internal CPUMCTX structure
855 *
856 * @returns VBox status code.
857 * @param pVM Handle to the virtual machine.
858 * @param ppCtx Receives the CPUMCTX GC pointer when successful.
859 */
860CPUMR3DECL(int) CPUMR3QueryGuestCtxGCPtr(PVM pVM, GCPTRTYPE(PCPUMCTX) *ppCtx);
861
862
863#ifdef DEBUG
864/**
865 * Debug helper - Saves guest context on raw mode entry (for fatal dump)
866 *
867 * @internal
868 */
869CPUMR3DECL(void) CPUMR3SaveEntryCtx(PVM pVM);
870#endif
871
872/**
873 * API for controlling a few of the CPU features found in CR4.
874 *
875 * Currently only X86_CR4_TSD is accepted as input.
876 *
877 * @returns VBox status code.
878 *
879 * @param pVM The VM handle.
880 * @param fOr The CR4 OR mask.
881 * @param fAnd The CR4 AND mask.
882 */
883CPUMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd);
884
885/** @} */
886#endif
887
888#ifdef IN_GC
889/** @defgroup grp_cpum_gc The CPU Monitor(/Manager) API
890 * @ingroup grp_cpum
891 * @{
892 */
893
894/**
895 * Calls a guest trap/interrupt handler directly
896 * Assumes a trap stack frame has already been setup on the guest's stack!
897 *
898 * @param pRegFrame Original trap/interrupt context
899 * @param selCS Code selector of handler
900 * @param pHandler GC virtual address of handler
901 * @param eflags Callee's EFLAGS
902 * @param selSS Stack selector for handler
903 * @param pEsp Stack address for handler
904 *
905 * This function does not return!
906 *
907 */
908CPUMGCDECL(void) CPUMGCCallGuestTrapHandler(PCPUMCTXCORE pRegFrame, uint32_t selCS, RTGCPTR pHandler, uint32_t eflags, uint32_t selSS, RTGCPTR pEsp);
909
910/**
911 * Performs an iret to V86 code
912 * Assumes a trap stack frame has already been setup on the guest's stack!
913 *
914 * @param pRegFrame Original trap/interrupt context
915 *
916 * This function does not return!
917 */
918CPUMGCDECL(void) CPUMGCCallV86Code(PCPUMCTXCORE pRegFrame);
919
920/** @} */
921#endif
922
923#ifdef IN_RING0
924/** @defgroup grp_cpum_r0 The CPU Monitor(/Manager) API
925 * @ingroup grp_cpum
926 * @{
927 */
928
929/**
930 * Does Ring-0 CPUM initialization.
931 *
932 * This is mainly to check that the Host CPU mode is compatible
933 * with VBox.
934 *
935 * @returns VBox status code.
936 * @param pVM The VM to operate on.
937 */
938CPUMR0DECL(int) CPUMR0Init(PVM pVM);
939
940/** @} */
941#endif
942
943/** @} */
944__END_DECLS
945
946
947#endif
948
949
950
951
952
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