VirtualBox

source: vbox/trunk/include/VBox/cpum.h@ 7644

Last change on this file since 7644 was 7644, checked in by vboxsync, 17 years ago

Added CPUMCPUIDFEATURE_PAE
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1/** @file
2 * CPUM - CPU Monitor(/ Manager).
3 */
4
5/*
6 * Copyright (C) 2006-2007 innotek GmbH
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * The contents of this file may alternatively be used under the terms
17 * of the Common Development and Distribution License Version 1.0
18 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19 * VirtualBox OSE distribution, in which case the provisions of the
20 * CDDL are applicable instead of those of the GPL.
21 *
22 * You may elect to license modified versions of this file under the
23 * terms and conditions of either the GPL or the CDDL or both.
24 */
25
26#ifndef ___VBox_cpum_h
27#define ___VBox_cpum_h
28
29#include <VBox/cdefs.h>
30#include <VBox/types.h>
31#include <VBox/x86.h>
32
33
34__BEGIN_DECLS
35
36/** @defgroup grp_cpum The CPU Monitor(/Manager) API
37 * @{
38 */
39
40/**
41 * Selector hidden registers.
42 */
43typedef struct CPUMSELREGHID
44{
45 /** Base register. */
46 uint32_t u32Base;
47 /** Limit (expanded). */
48 uint32_t u32Limit;
49 /** Flags.
50 * This is the high 32-bit word of the descriptor entry.
51 * Only the flags, dpl and type are used. */
52 X86DESCATTR Attr;
53} CPUMSELREGHID;
54
55
56/**
57 * The sysenter register set.
58 */
59typedef struct CPUMSYSENTER
60{
61 /** Ring 0 cs.
62 * This value + 8 is the Ring 0 ss.
63 * This value + 16 is the Ring 3 cs.
64 * This value + 24 is the Ring 3 ss.
65 */
66 uint64_t cs;
67 /** Ring 0 eip. */
68 uint64_t eip;
69 /** Ring 0 esp. */
70 uint64_t esp;
71} CPUMSYSENTER;
72
73
74/**
75 * CPU context core.
76 */
77#pragma pack(1)
78typedef struct CPUMCTXCORE
79{
80 union
81 {
82 uint32_t edi;
83 uint64_t rdi;
84 };
85 union
86 {
87 uint32_t esi;
88 uint64_t rsi;
89 };
90 union
91 {
92 uint32_t ebp;
93 uint64_t rbp;
94 };
95 union
96 {
97 uint32_t eax;
98 uint64_t rax;
99 };
100 union
101 {
102 uint32_t ebx;
103 uint64_t rbx;
104 };
105 union
106 {
107 uint32_t edx;
108 uint64_t rdx;
109 };
110 union
111 {
112 uint32_t ecx;
113 uint64_t rcx;
114 };
115 /* Note: we rely on the exact layout, because we use lss esp, [] in the switcher */
116 uint32_t esp;
117 RTSEL ss;
118 RTSEL ssPadding;
119 /* Note: no overlap with esp here. */
120 uint64_t rsp;
121
122 RTSEL gs;
123 RTSEL gsPadding;
124 RTSEL fs;
125 RTSEL fsPadding;
126 RTSEL es;
127 RTSEL esPadding;
128 RTSEL ds;
129 RTSEL dsPadding;
130 RTSEL cs;
131 RTSEL csPadding[3]; /* 3 words to force 8 byte alignment for the remainder */
132
133 union
134 {
135 X86EFLAGS eflags;
136 X86RFLAGS rflags;
137 };
138 union
139 {
140 uint32_t eip;
141 uint64_t rip;
142 };
143
144 uint64_t r8;
145 uint64_t r9;
146 uint64_t r10;
147 uint64_t r11;
148 uint64_t r12;
149 uint64_t r13;
150 uint64_t r14;
151 uint64_t r15;
152
153 /** Hidden selector registers.
154 * @{ */
155 CPUMSELREGHID esHid;
156 CPUMSELREGHID csHid;
157 CPUMSELREGHID ssHid;
158 CPUMSELREGHID dsHid;
159 CPUMSELREGHID fsHid;
160 CPUMSELREGHID gsHid;
161 /** @} */
162
163} CPUMCTXCORE;
164#pragma pack()
165
166
167/**
168 * CPU context.
169 */
170#pragma pack(1)
171typedef struct CPUMCTX
172{
173 /** FPU state. (16-byte alignment)
174 * @todo This doesn't have to be in X86FXSTATE on CPUs without fxsr - we need a type for the
175 * actual format or convert it (waste of time). */
176 X86FXSTATE fpu;
177
178 /** CPUMCTXCORE Part.
179 * @{ */
180 union
181 {
182 uint32_t edi;
183 uint64_t rdi;
184 };
185 union
186 {
187 uint32_t esi;
188 uint64_t rsi;
189 };
190 union
191 {
192 uint32_t ebp;
193 uint64_t rbp;
194 };
195 union
196 {
197 uint32_t eax;
198 uint64_t rax;
199 };
200 union
201 {
202 uint32_t ebx;
203 uint64_t rbx;
204 };
205 union
206 {
207 uint32_t edx;
208 uint64_t rdx;
209 };
210 union
211 {
212 uint32_t ecx;
213 uint64_t rcx;
214 };
215 /* Note: we rely on the exact layout, because we use lss esp, [] in the switcher */
216 uint32_t esp;
217 RTSEL ss;
218 RTSEL ssPadding;
219 /* Note: no overlap with esp here. */
220 uint64_t rsp;
221
222 RTSEL gs;
223 RTSEL gsPadding;
224 RTSEL fs;
225 RTSEL fsPadding;
226 RTSEL es;
227 RTSEL esPadding;
228 RTSEL ds;
229 RTSEL dsPadding;
230 RTSEL cs;
231 RTSEL csPadding[3]; /* 3 words to force 8 byte alignment for the remainder */
232
233 union
234 {
235 X86EFLAGS eflags;
236 X86RFLAGS rflags;
237 };
238 union
239 {
240 uint32_t eip;
241 uint64_t rip;
242 };
243
244 uint64_t r8;
245 uint64_t r9;
246 uint64_t r10;
247 uint64_t r11;
248 uint64_t r12;
249 uint64_t r13;
250 uint64_t r14;
251 uint64_t r15;
252
253 /** Hidden selector registers.
254 * @{ */
255 CPUMSELREGHID esHid;
256 CPUMSELREGHID csHid;
257 CPUMSELREGHID ssHid;
258 CPUMSELREGHID dsHid;
259 CPUMSELREGHID fsHid;
260 CPUMSELREGHID gsHid;
261 /** @} */
262
263 /** @} */
264
265 /** Control registers.
266 * @{ */
267 uint64_t cr0;
268 uint64_t cr2;
269 uint64_t cr3;
270 uint64_t cr4;
271 uint64_t cr8;
272 /** @} */
273
274 /** Debug registers.
275 * @{ */
276 uint64_t dr0;
277 uint64_t dr1;
278 uint64_t dr2;
279 uint64_t dr3;
280 uint64_t dr4; /**< @todo remove dr4 and dr5. */
281 uint64_t dr5;
282 uint64_t dr6;
283 uint64_t dr7;
284 /* DR8-15 are currently not supported */
285 /** @} */
286
287 /** Global Descriptor Table register. */
288 VBOXGDTR gdtr;
289 uint16_t gdtrPadding;
290 uint32_t gdtrPadding64;/** @todo fix this hack */
291 /** Interrupt Descriptor Table register. */
292 VBOXIDTR idtr;
293 uint16_t idtrPadding;
294 uint32_t idtrPadding64;/** @todo fix this hack */
295 /** The task register.
296 * Only the guest context uses all the members. */
297 RTSEL ldtr;
298 RTSEL ldtrPadding;
299 /** The task register.
300 * Only the guest context uses all the members. */
301 RTSEL tr;
302 RTSEL trPadding;
303
304 /** The sysenter msr registers.
305 * This member is not used by the hypervisor context. */
306 CPUMSYSENTER SysEnter;
307
308 /** Hidden selector registers.
309 * @{ */
310 CPUMSELREGHID ldtrHid;
311 CPUMSELREGHID trHid;
312 /** @} */
313
314 /* padding to get 32byte aligned size */
315 uint32_t padding[4];
316} CPUMCTX;
317#pragma pack()
318
319/**
320 * Gets the CPUMCTXCORE part of a CPUMCTX.
321 */
322#define CPUMCTX2CORE(pCtx) ((PCPUMCTXCORE)(void *)&(pCtx)->edi)
323
324/**
325 * The register set returned by a CPUID operation.
326 */
327typedef struct CPUMCPUID
328{
329 uint32_t eax;
330 uint32_t ebx;
331 uint32_t ecx;
332 uint32_t edx;
333} CPUMCPUID;
334/** Pointer to a CPUID leaf. */
335typedef CPUMCPUID *PCPUMCPUID;
336/** Pointer to a const CPUID leaf. */
337typedef const CPUMCPUID *PCCPUMCPUID;
338
339/**
340 * CPUID feature to set or clear.
341 */
342typedef enum CPUMCPUIDFEATURE
343{
344 CPUMCPUIDFEATURE_INVALID = 0,
345 /** The APIC feature bit. (Std+Ext) */
346 CPUMCPUIDFEATURE_APIC,
347 /** The sysenter/sysexit feature bit. (Std+Ext) */
348 CPUMCPUIDFEATURE_SEP,
349 /** The PAE feature bit. (Std+Ext) */
350 CPUMCPUIDFEATURE_PAE
351} CPUMCPUIDFEATURE;
352
353
354/** @name Guest Register Getters.
355 * @{ */
356CPUMDECL(void) CPUMGetGuestGDTR(PVM pVM, PVBOXGDTR pGDTR);
357CPUMDECL(uint32_t) CPUMGetGuestIDTR(PVM pVM, uint16_t *pcbLimit);
358CPUMDECL(RTSEL) CPUMGetGuestTR(PVM pVM);
359CPUMDECL(RTSEL) CPUMGetGuestLDTR(PVM pVM);
360CPUMDECL(uint32_t) CPUMGetGuestCR0(PVM pVM);
361CPUMDECL(uint32_t) CPUMGetGuestCR2(PVM pVM);
362CPUMDECL(uint32_t) CPUMGetGuestCR3(PVM pVM);
363CPUMDECL(uint32_t) CPUMGetGuestCR4(PVM pVM);
364CPUMDECL(int) CPUMGetGuestCRx(PVM pVM, uint32_t iReg, uint32_t *pValue);
365CPUMDECL(uint32_t) CPUMGetGuestEFlags(PVM pVM);
366CPUMDECL(uint32_t) CPUMGetGuestEIP(PVM pVM);
367CPUMDECL(uint32_t) CPUMGetGuestEAX(PVM pVM);
368CPUMDECL(uint32_t) CPUMGetGuestEBX(PVM pVM);
369CPUMDECL(uint32_t) CPUMGetGuestECX(PVM pVM);
370CPUMDECL(uint32_t) CPUMGetGuestEDX(PVM pVM);
371CPUMDECL(uint32_t) CPUMGetGuestESI(PVM pVM);
372CPUMDECL(uint32_t) CPUMGetGuestEDI(PVM pVM);
373CPUMDECL(uint32_t) CPUMGetGuestESP(PVM pVM);
374CPUMDECL(uint32_t) CPUMGetGuestEBP(PVM pVM);
375CPUMDECL(RTSEL) CPUMGetGuestCS(PVM pVM);
376CPUMDECL(RTSEL) CPUMGetGuestDS(PVM pVM);
377CPUMDECL(RTSEL) CPUMGetGuestES(PVM pVM);
378CPUMDECL(RTSEL) CPUMGetGuestFS(PVM pVM);
379CPUMDECL(RTSEL) CPUMGetGuestGS(PVM pVM);
380CPUMDECL(RTSEL) CPUMGetGuestSS(PVM pVM);
381CPUMDECL(RTUINTREG) CPUMGetGuestDR0(PVM pVM);
382CPUMDECL(RTUINTREG) CPUMGetGuestDR1(PVM pVM);
383CPUMDECL(RTUINTREG) CPUMGetGuestDR2(PVM pVM);
384CPUMDECL(RTUINTREG) CPUMGetGuestDR3(PVM pVM);
385CPUMDECL(RTUINTREG) CPUMGetGuestDR6(PVM pVM);
386CPUMDECL(RTUINTREG) CPUMGetGuestDR7(PVM pVM);
387CPUMDECL(int) CPUMGetGuestDRx(PVM pVM, uint32_t iReg, uint32_t *pValue);
388CPUMDECL(void) CPUMGetGuestCpuId(PVM pVM, uint32_t iLeaf, uint32_t *pEax, uint32_t *pEbx, uint32_t *pEcx, uint32_t *pEdx);
389CPUMDECL(GCPTRTYPE(PCCPUMCPUID)) CPUMGetGuestCpuIdStdGCPtr(PVM pVM);
390CPUMDECL(GCPTRTYPE(PCCPUMCPUID)) CPUMGetGuestCpuIdExtGCPtr(PVM pVM);
391CPUMDECL(GCPTRTYPE(PCCPUMCPUID)) CPUMGetGuestCpuIdCentaurGCPtr(PVM pVM);
392CPUMDECL(GCPTRTYPE(PCCPUMCPUID)) CPUMGetGuestCpuIdDefGCPtr(PVM pVM);
393CPUMDECL(uint32_t) CPUMGetGuestCpuIdStdMax(PVM pVM);
394CPUMDECL(uint32_t) CPUMGetGuestCpuIdExtMax(PVM pVM);
395CPUMDECL(uint32_t) CPUMGetGuestCpuIdCentaurMax(PVM pVM);
396CPUMDECL(CPUMSELREGHID *) CPUMGetGuestTRHid(PVM pVM);
397/** @} */
398
399/** @name Guest Register Setters.
400 * @{ */
401CPUMDECL(int) CPUMSetGuestGDTR(PVM pVM, uint32_t addr, uint16_t limit);
402CPUMDECL(int) CPUMSetGuestIDTR(PVM pVM, uint32_t addr, uint16_t limit);
403CPUMDECL(int) CPUMSetGuestTR(PVM pVM, uint16_t tr);
404CPUMDECL(int) CPUMSetGuestLDTR(PVM pVM, uint16_t ldtr);
405CPUMDECL(int) CPUMSetGuestCR0(PVM pVM, uint32_t cr0);
406CPUMDECL(int) CPUMSetGuestCR2(PVM pVM, uint32_t cr2);
407CPUMDECL(int) CPUMSetGuestCR3(PVM pVM, uint32_t cr3);
408CPUMDECL(int) CPUMSetGuestCR4(PVM pVM, uint32_t cr4);
409CPUMDECL(int) CPUMSetGuestCRx(PVM pVM, uint32_t iReg, uint32_t Value);
410CPUMDECL(int) CPUMSetGuestDR0(PVM pVM, RTGCUINTREG uDr0);
411CPUMDECL(int) CPUMSetGuestDR1(PVM pVM, RTGCUINTREG uDr1);
412CPUMDECL(int) CPUMSetGuestDR2(PVM pVM, RTGCUINTREG uDr2);
413CPUMDECL(int) CPUMSetGuestDR3(PVM pVM, RTGCUINTREG uDr3);
414CPUMDECL(int) CPUMSetGuestDR6(PVM pVM, RTGCUINTREG uDr6);
415CPUMDECL(int) CPUMSetGuestDR7(PVM pVM, RTGCUINTREG uDr7);
416CPUMDECL(int) CPUMSetGuestDRx(PVM pVM, uint32_t iReg, uint32_t Value);
417CPUMDECL(int) CPUMSetGuestEFlags(PVM pVM, uint32_t eflags);
418CPUMDECL(int) CPUMSetGuestEIP(PVM pVM, uint32_t eip);
419CPUMDECL(int) CPUMSetGuestEAX(PVM pVM, uint32_t eax);
420CPUMDECL(int) CPUMSetGuestEBX(PVM pVM, uint32_t ebx);
421CPUMDECL(int) CPUMSetGuestECX(PVM pVM, uint32_t ecx);
422CPUMDECL(int) CPUMSetGuestEDX(PVM pVM, uint32_t edx);
423CPUMDECL(int) CPUMSetGuestESI(PVM pVM, uint32_t esi);
424CPUMDECL(int) CPUMSetGuestEDI(PVM pVM, uint32_t edi);
425CPUMDECL(int) CPUMSetGuestESP(PVM pVM, uint32_t esp);
426CPUMDECL(int) CPUMSetGuestEBP(PVM pVM, uint32_t ebp);
427CPUMDECL(int) CPUMSetGuestCS(PVM pVM, uint16_t cs);
428CPUMDECL(int) CPUMSetGuestDS(PVM pVM, uint16_t ds);
429CPUMDECL(int) CPUMSetGuestES(PVM pVM, uint16_t es);
430CPUMDECL(int) CPUMSetGuestFS(PVM pVM, uint16_t fs);
431CPUMDECL(int) CPUMSetGuestGS(PVM pVM, uint16_t gs);
432CPUMDECL(int) CPUMSetGuestSS(PVM pVM, uint16_t ss);
433CPUMDECL(void) CPUMSetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature);
434CPUMDECL(void) CPUMClearGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature);
435CPUMDECL(void) CPUMSetGuestCtx(PVM pVM, const PCPUMCTX pCtx);
436/** @} */
437
438/** @name Misc Guest Predicate Functions.
439 * @{ */
440
441/**
442 * Tests if the guest is running in real mode or not.
443 *
444 * @returns true if in real mode, otherwise false.
445 * @param pVM The VM handle.
446 */
447DECLINLINE(bool) CPUMIsGuestInRealMode(PVM pVM)
448{
449 return !(CPUMGetGuestCR0(pVM) & X86_CR0_PE);
450}
451
452/**
453 * Tests if the guest is running in protected or not.
454 *
455 * @returns true if in protected mode, otherwise false.
456 * @param pVM The VM handle.
457 */
458DECLINLINE(bool) CPUMIsGuestInProtectedMode(PVM pVM)
459{
460 return !!(CPUMGetGuestCR0(pVM) & X86_CR0_PE);
461}
462
463/**
464 * Tests if the guest is running in paged protected or not.
465 *
466 * @returns true if in paged protected mode, otherwise false.
467 * @param pVM The VM handle.
468 */
469DECLINLINE(bool) CPUMIsGuestInPagedProtectedMode(PVM pVM)
470{
471 return (CPUMGetGuestCR0(pVM) & (X86_CR0_PE | X86_CR0_PG)) == (X86_CR0_PE | X86_CR0_PG);
472}
473
474/**
475 * Tests if the guest is running in paged protected or not.
476 *
477 * @returns true if in paged protected mode, otherwise false.
478 * @param pVM The VM handle.
479 */
480CPUMDECL(bool) CPUMIsGuestIn16BitCode(PVM pVM);
481
482/**
483 * Tests if the guest is running in paged protected or not.
484 *
485 * @returns true if in paged protected mode, otherwise false.
486 * @param pVM The VM handle.
487 */
488CPUMDECL(bool) CPUMIsGuestIn32BitCode(PVM pVM);
489
490/**
491 * Tests if the guest is running in paged protected or not.
492 *
493 * @returns true if in paged protected mode, otherwise false.
494 * @param pVM The VM handle.
495 */
496CPUMDECL(bool) CPUMIsGuestIn64BitCode(PVM pVM);
497
498/** @} */
499
500
501
502/** @name Hypervisor Register Getters.
503 * @{ */
504CPUMDECL(RTSEL) CPUMGetHyperCS(PVM pVM);
505CPUMDECL(RTSEL) CPUMGetHyperDS(PVM pVM);
506CPUMDECL(RTSEL) CPUMGetHyperES(PVM pVM);
507CPUMDECL(RTSEL) CPUMGetHyperFS(PVM pVM);
508CPUMDECL(RTSEL) CPUMGetHyperGS(PVM pVM);
509CPUMDECL(RTSEL) CPUMGetHyperSS(PVM pVM);
510#if 0 /* these are not correct. */
511CPUMDECL(uint32_t) CPUMGetHyperCR0(PVM pVM);
512CPUMDECL(uint32_t) CPUMGetHyperCR2(PVM pVM);
513CPUMDECL(uint32_t) CPUMGetHyperCR3(PVM pVM);
514CPUMDECL(uint32_t) CPUMGetHyperCR4(PVM pVM);
515#endif
516/** This register is only saved on fatal traps. */
517CPUMDECL(uint32_t) CPUMGetHyperEAX(PVM pVM);
518CPUMDECL(uint32_t) CPUMGetHyperEBX(PVM pVM);
519/** This register is only saved on fatal traps. */
520CPUMDECL(uint32_t) CPUMGetHyperECX(PVM pVM);
521/** This register is only saved on fatal traps. */
522CPUMDECL(uint32_t) CPUMGetHyperEDX(PVM pVM);
523CPUMDECL(uint32_t) CPUMGetHyperESI(PVM pVM);
524CPUMDECL(uint32_t) CPUMGetHyperEDI(PVM pVM);
525CPUMDECL(uint32_t) CPUMGetHyperEBP(PVM pVM);
526CPUMDECL(uint32_t) CPUMGetHyperESP(PVM pVM);
527CPUMDECL(uint32_t) CPUMGetHyperEFlags(PVM pVM);
528CPUMDECL(uint32_t) CPUMGetHyperEIP(PVM pVM);
529CPUMDECL(uint32_t) CPUMGetHyperIDTR(PVM pVM, uint16_t *pcbLimit);
530CPUMDECL(uint32_t) CPUMGetHyperGDTR(PVM pVM, uint16_t *pcbLimit);
531CPUMDECL(RTSEL) CPUMGetHyperLDTR(PVM pVM);
532CPUMDECL(RTGCUINTREG) CPUMGetHyperDR0(PVM pVM);
533CPUMDECL(RTGCUINTREG) CPUMGetHyperDR1(PVM pVM);
534CPUMDECL(RTGCUINTREG) CPUMGetHyperDR2(PVM pVM);
535CPUMDECL(RTGCUINTREG) CPUMGetHyperDR3(PVM pVM);
536CPUMDECL(RTGCUINTREG) CPUMGetHyperDR6(PVM pVM);
537CPUMDECL(RTGCUINTREG) CPUMGetHyperDR7(PVM pVM);
538CPUMDECL(void) CPUMGetHyperCtx(PVM pVM, PCPUMCTX pCtx);
539/** @} */
540
541/** @name Hypervisor Register Setters.
542 * @{ */
543CPUMDECL(void) CPUMSetHyperGDTR(PVM pVM, uint32_t addr, uint16_t limit);
544CPUMDECL(void) CPUMSetHyperLDTR(PVM pVM, RTSEL SelLDTR);
545CPUMDECL(void) CPUMSetHyperIDTR(PVM pVM, uint32_t addr, uint16_t limit);
546CPUMDECL(void) CPUMSetHyperCR3(PVM pVM, uint32_t cr3);
547CPUMDECL(void) CPUMSetHyperTR(PVM pVM, RTSEL SelTR);
548CPUMDECL(void) CPUMSetHyperCS(PVM pVM, RTSEL SelCS);
549CPUMDECL(void) CPUMSetHyperDS(PVM pVM, RTSEL SelDS);
550CPUMDECL(void) CPUMSetHyperES(PVM pVM, RTSEL SelDS);
551CPUMDECL(void) CPUMSetHyperFS(PVM pVM, RTSEL SelDS);
552CPUMDECL(void) CPUMSetHyperGS(PVM pVM, RTSEL SelDS);
553CPUMDECL(void) CPUMSetHyperSS(PVM pVM, RTSEL SelSS);
554CPUMDECL(void) CPUMSetHyperESP(PVM pVM, uint32_t u32ESP);
555CPUMDECL(int) CPUMSetHyperEFlags(PVM pVM, uint32_t Efl);
556CPUMDECL(void) CPUMSetHyperEIP(PVM pVM, uint32_t u32EIP);
557CPUMDECL(void) CPUMSetHyperDR0(PVM pVM, RTGCUINTREG uDr0);
558CPUMDECL(void) CPUMSetHyperDR1(PVM pVM, RTGCUINTREG uDr1);
559CPUMDECL(void) CPUMSetHyperDR2(PVM pVM, RTGCUINTREG uDr2);
560CPUMDECL(void) CPUMSetHyperDR3(PVM pVM, RTGCUINTREG uDr3);
561CPUMDECL(void) CPUMSetHyperDR6(PVM pVM, RTGCUINTREG uDr6);
562CPUMDECL(void) CPUMSetHyperDR7(PVM pVM, RTGCUINTREG uDr7);
563CPUMDECL(void) CPUMSetHyperCtx(PVM pVM, const PCPUMCTX pCtx);
564CPUMDECL(int) CPUMRecalcHyperDRx(PVM pVM);
565/** @} */
566
567CPUMDECL(void) CPUMPushHyper(PVM pVM, uint32_t u32);
568
569/**
570 * Sets or resets an alternative hypervisor context core.
571 *
572 * This is called when we get a hypervisor trap set switch the context
573 * core with the trap frame on the stack. It is called again to reset
574 * back to the default context core when resuming hypervisor execution.
575 *
576 * @param pVM The VM handle.
577 * @param pCtxCore Pointer to the alternative context core or NULL
578 * to go back to the default context core.
579 */
580CPUMDECL(void) CPUMHyperSetCtxCore(PVM pVM, PCPUMCTXCORE pCtxCore);
581
582
583/**
584 * Queries the pointer to the internal CPUMCTX structure
585 *
586 * @returns VBox status code.
587 * @param pVM Handle to the virtual machine.
588 * @param ppCtx Receives the CPUMCTX pointer when successful.
589 */
590CPUMDECL(int) CPUMQueryGuestCtxPtr(PVM pVM, PCPUMCTX *ppCtx);
591
592/**
593 * Queries the pointer to the internal CPUMCTX structure for the hypervisor.
594 *
595 * @returns VBox status code.
596 * @param pVM Handle to the virtual machine.
597 * @param ppCtx Receives the hyper CPUMCTX pointer when successful.
598 */
599CPUMDECL(int) CPUMQueryHyperCtxPtr(PVM pVM, PCPUMCTX *ppCtx);
600
601
602/**
603 * Gets the pointer to the internal CPUMCTXCORE structure.
604 * This is only for reading in order to save a few calls.
605 *
606 * @param pVM Handle to the virtual machine.
607 */
608CPUMDECL(PCCPUMCTXCORE) CPUMGetGuestCtxCore(PVM pVM);
609
610/**
611 * Gets the pointer to the internal CPUMCTXCORE structure for the hypervisor.
612 * This is only for reading in order to save a few calls.
613 *
614 * @param pVM Handle to the virtual machine.
615 */
616CPUMDECL(PCCPUMCTXCORE) CPUMGetHyperCtxCore(PVM pVM);
617
618/**
619 * Sets the guest context core registers.
620 *
621 * @param pVM Handle to the virtual machine.
622 * @param pCtxCore The new context core values.
623 */
624CPUMDECL(void) CPUMSetGuestCtxCore(PVM pVM, PCCPUMCTXCORE pCtxCore);
625
626
627/**
628 * Transforms the guest CPU state to raw-ring mode.
629 *
630 * This function will change the any of the cs and ss register with DPL=0 to DPL=1.
631 *
632 * @returns VBox status. (recompiler failure)
633 * @param pVM VM handle.
634 * @param pCtxCore The context core (for trap usage).
635 * @see @ref pg_raw
636 */
637CPUMDECL(int) CPUMRawEnter(PVM pVM, PCPUMCTXCORE pCtxCore);
638
639/**
640 * Transforms the guest CPU state from raw-ring mode to correct values.
641 *
642 * This function will change any selector registers with DPL=1 to DPL=0.
643 *
644 * @returns Adjusted rc.
645 * @param pVM VM handle.
646 * @param rc Raw mode return code
647 * @param pCtxCore The context core (for trap usage).
648 * @see @ref pg_raw
649 */
650CPUMDECL(int) CPUMRawLeave(PVM pVM, PCPUMCTXCORE pCtxCore, int rc);
651
652/**
653 * Gets the EFLAGS while we're in raw-mode.
654 *
655 * @returns The eflags.
656 * @param pVM The VM handle.
657 * @param pCtxCore The context core.
658 */
659CPUMDECL(uint32_t) CPUMRawGetEFlags(PVM pVM, PCPUMCTXCORE pCtxCore);
660
661/**
662 * Updates the EFLAGS while we're in raw-mode.
663 *
664 * @param pVM The VM handle.
665 * @param pCtxCore The context core.
666 * @param eflags The new EFLAGS value.
667 */
668CPUMDECL(void) CPUMRawSetEFlags(PVM pVM, PCPUMCTXCORE pCtxCore, uint32_t eflags);
669
670/**
671 * Lazily sync in the FPU/XMM state
672 *
673 * This function will change any selector registers with DPL=1 to DPL=0.
674 *
675 * @returns VBox status code.
676 * @param pVM VM handle.
677 */
678CPUMDECL(int) CPUMHandleLazyFPU(PVM pVM);
679
680
681/**
682 * Restore host FPU/XMM state
683 *
684 * @returns VBox status code.
685 * @param pVM VM handle.
686 */
687CPUMDECL(int) CPUMRestoreHostFPUState(PVM pVM);
688
689/** @name Changed flags
690 * These flags are used to keep track of which important register that
691 * have been changed since last they were reset. The only one allowed
692 * to clear them is REM!
693 * @{
694 */
695#define CPUM_CHANGED_FPU_REM RT_BIT(0)
696#define CPUM_CHANGED_CR0 RT_BIT(1)
697#define CPUM_CHANGED_CR4 RT_BIT(2)
698#define CPUM_CHANGED_GLOBAL_TLB_FLUSH RT_BIT(3)
699#define CPUM_CHANGED_CR3 RT_BIT(4)
700#define CPUM_CHANGED_GDTR RT_BIT(5)
701#define CPUM_CHANGED_IDTR RT_BIT(6)
702#define CPUM_CHANGED_LDTR RT_BIT(7)
703#define CPUM_CHANGED_TR RT_BIT(8)
704#define CPUM_CHANGED_SYSENTER_MSR RT_BIT(9)
705#define CPUM_CHANGED_HIDDEN_SEL_REGS RT_BIT(10)
706/** @} */
707
708/**
709 * Gets and resets the changed flags (CPUM_CHANGED_*).
710 *
711 * @returns The changed flags.
712 * @param pVM VM handle.
713 */
714CPUMDECL(unsigned) CPUMGetAndClearChangedFlagsREM(PVM pVM);
715
716/**
717 * Sets the specified changed flags (CPUM_CHANGED_*).
718 *
719 * @param pVM The VM handle.
720 */
721CPUMDECL(void) CPUMSetChangedFlags(PVM pVM, uint32_t fChangedFlags);
722
723/**
724 * Checks if the CPU supports the FXSAVE and FXRSTOR instruction.
725 * @returns true if supported.
726 * @returns false if not supported.
727 * @param pVM The VM handle.
728 */
729CPUMDECL(bool) CPUMSupportsFXSR(PVM pVM);
730
731/**
732 * Checks if the host OS uses the SYSENTER / SYSEXIT instructions.
733 * @returns true if used.
734 * @returns false if not used.
735 * @param pVM The VM handle.
736 */
737CPUMDECL(bool) CPUMIsHostUsingSysEnter(PVM pVM);
738
739/**
740 * Checks if the host OS uses the SYSCALL / SYSRET instructions.
741 * @returns true if used.
742 * @returns false if not used.
743 * @param pVM The VM handle.
744 */
745CPUMDECL(bool) CPUMIsHostUsingSysCall(PVM pVM);
746
747/**
748 * Checks if we activated the FPU/XMM state of the guest OS
749 * @returns true if we did.
750 * @returns false if not.
751 * @param pVM The VM handle.
752 */
753CPUMDECL(bool) CPUMIsGuestFPUStateActive(PVM pVM);
754
755/**
756 * Deactivate the FPU/XMM state of the guest OS
757 * @param pVM The VM handle.
758 */
759CPUMDECL(void) CPUMDeactivateGuestFPUState(PVM pVM);
760
761
762/**
763 * Checks if the hidden selector registers are valid
764 * @returns true if they are.
765 * @returns false if not.
766 * @param pVM The VM handle.
767 */
768CPUMDECL(bool) CPUMAreHiddenSelRegsValid(PVM pVM);
769
770/**
771 * Checks if the hidden selector registers are valid
772 * @param pVM The VM handle.
773 * @param fValid Valid or not
774 */
775CPUMDECL(void) CPUMSetHiddenSelRegsValid(PVM pVM, bool fValid);
776
777/**
778 * Get the current privilege level of the guest.
779 *
780 * @returns cpl
781 * @param pVM VM Handle.
782 * @param pRegFrame Trap register frame.
783 */
784CPUMDECL(uint32_t) CPUMGetGuestCPL(PVM pVM, PCPUMCTXCORE pCtxCore);
785
786/**
787 * CPU modes.
788 */
789typedef enum CPUMMODE
790{
791 /** The usual invalid zero entry. */
792 CPUMMODE_INVALID = 0,
793 /** Real mode. */
794 CPUMMODE_REAL,
795 /** Protected mode (32-bit). */
796 CPUMMODE_PROTECTED,
797 /** Long mode (64-bit). */
798 CPUMMODE_LONG
799} CPUMMODE;
800
801/**
802 * Gets the current guest CPU mode.
803 *
804 * If paging mode is what you need, check out PGMGetGuestMode().
805 *
806 * @returns The CPU mode.
807 * @param pVM The VM handle.
808 */
809CPUMDECL(CPUMMODE) CPUMGetGuestMode(PVM pVM);
810
811
812#ifdef IN_RING3
813/** @defgroup grp_cpum_r3 The CPU Monitor(/Manager) API
814 * @ingroup grp_cpum
815 * @{
816 */
817
818/**
819 * Initializes the CPUM.
820 *
821 * @returns VBox status code.
822 * @param pVM The VM to operate on.
823 */
824CPUMR3DECL(int) CPUMR3Init(PVM pVM);
825
826/**
827 * Applies relocations to data and code managed by this
828 * component. This function will be called at init and
829 * whenever the VMM need to relocate it self inside the GC.
830 *
831 * The CPUM will update the addresses used by the switcher.
832 *
833 * @param pVM The VM.
834 */
835CPUMR3DECL(void) CPUMR3Relocate(PVM pVM);
836
837/**
838 * Terminates the CPUM.
839 *
840 * Termination means cleaning up and freeing all resources,
841 * the VM it self is at this point powered off or suspended.
842 *
843 * @returns VBox status code.
844 * @param pVM The VM to operate on.
845 */
846CPUMR3DECL(int) CPUMR3Term(PVM pVM);
847
848/**
849 * Resets the CPU.
850 *
851 * @param pVM The VM handle.
852 */
853CPUMR3DECL(void) CPUMR3Reset(PVM pVM);
854
855/**
856 * Queries the pointer to the internal CPUMCTX structure
857 *
858 * @returns VBox status code.
859 * @param pVM Handle to the virtual machine.
860 * @param ppCtx Receives the CPUMCTX GC pointer when successful.
861 */
862CPUMR3DECL(int) CPUMR3QueryGuestCtxGCPtr(PVM pVM, GCPTRTYPE(PCPUMCTX) *ppCtx);
863
864
865#ifdef DEBUG
866/**
867 * Debug helper - Saves guest context on raw mode entry (for fatal dump)
868 *
869 * @internal
870 */
871CPUMR3DECL(void) CPUMR3SaveEntryCtx(PVM pVM);
872#endif
873
874/**
875 * API for controlling a few of the CPU features found in CR4.
876 *
877 * Currently only X86_CR4_TSD is accepted as input.
878 *
879 * @returns VBox status code.
880 *
881 * @param pVM The VM handle.
882 * @param fOr The CR4 OR mask.
883 * @param fAnd The CR4 AND mask.
884 */
885CPUMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd);
886
887/** @} */
888#endif
889
890#ifdef IN_GC
891/** @defgroup grp_cpum_gc The CPU Monitor(/Manager) API
892 * @ingroup grp_cpum
893 * @{
894 */
895
896/**
897 * Calls a guest trap/interrupt handler directly
898 * Assumes a trap stack frame has already been setup on the guest's stack!
899 *
900 * @param pRegFrame Original trap/interrupt context
901 * @param selCS Code selector of handler
902 * @param pHandler GC virtual address of handler
903 * @param eflags Callee's EFLAGS
904 * @param selSS Stack selector for handler
905 * @param pEsp Stack address for handler
906 *
907 * This function does not return!
908 *
909 */
910CPUMGCDECL(void) CPUMGCCallGuestTrapHandler(PCPUMCTXCORE pRegFrame, uint32_t selCS, RTGCPTR pHandler, uint32_t eflags, uint32_t selSS, RTGCPTR pEsp);
911
912/**
913 * Performs an iret to V86 code
914 * Assumes a trap stack frame has already been setup on the guest's stack!
915 *
916 * @param pRegFrame Original trap/interrupt context
917 *
918 * This function does not return!
919 */
920CPUMGCDECL(void) CPUMGCCallV86Code(PCPUMCTXCORE pRegFrame);
921
922/** @} */
923#endif
924
925#ifdef IN_RING0
926/** @defgroup grp_cpum_r0 The CPU Monitor(/Manager) API
927 * @ingroup grp_cpum
928 * @{
929 */
930
931/**
932 * Does Ring-0 CPUM initialization.
933 *
934 * This is mainly to check that the Host CPU mode is compatible
935 * with VBox.
936 *
937 * @returns VBox status code.
938 * @param pVM The VM to operate on.
939 */
940CPUMR0DECL(int) CPUMR0Init(PVM pVM);
941
942/** @} */
943#endif
944
945/** @} */
946__END_DECLS
947
948
949#endif
950
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