VirtualBox

source: vbox/trunk/include/VBox/cpum.h@ 7689

Last change on this file since 7689 was 7645, checked in by vboxsync, 17 years ago

CPUMCPUIDFEATURE_LONG_MODE added
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File size: 27.1 KB
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1/** @file
2 * CPUM - CPU Monitor(/ Manager).
3 */
4
5/*
6 * Copyright (C) 2006-2007 innotek GmbH
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * The contents of this file may alternatively be used under the terms
17 * of the Common Development and Distribution License Version 1.0
18 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19 * VirtualBox OSE distribution, in which case the provisions of the
20 * CDDL are applicable instead of those of the GPL.
21 *
22 * You may elect to license modified versions of this file under the
23 * terms and conditions of either the GPL or the CDDL or both.
24 */
25
26#ifndef ___VBox_cpum_h
27#define ___VBox_cpum_h
28
29#include <VBox/cdefs.h>
30#include <VBox/types.h>
31#include <VBox/x86.h>
32
33
34__BEGIN_DECLS
35
36/** @defgroup grp_cpum The CPU Monitor(/Manager) API
37 * @{
38 */
39
40/**
41 * Selector hidden registers.
42 */
43typedef struct CPUMSELREGHID
44{
45 /** Base register. */
46 uint32_t u32Base;
47 /** Limit (expanded). */
48 uint32_t u32Limit;
49 /** Flags.
50 * This is the high 32-bit word of the descriptor entry.
51 * Only the flags, dpl and type are used. */
52 X86DESCATTR Attr;
53} CPUMSELREGHID;
54
55
56/**
57 * The sysenter register set.
58 */
59typedef struct CPUMSYSENTER
60{
61 /** Ring 0 cs.
62 * This value + 8 is the Ring 0 ss.
63 * This value + 16 is the Ring 3 cs.
64 * This value + 24 is the Ring 3 ss.
65 */
66 uint64_t cs;
67 /** Ring 0 eip. */
68 uint64_t eip;
69 /** Ring 0 esp. */
70 uint64_t esp;
71} CPUMSYSENTER;
72
73
74/**
75 * CPU context core.
76 */
77#pragma pack(1)
78typedef struct CPUMCTXCORE
79{
80 union
81 {
82 uint32_t edi;
83 uint64_t rdi;
84 };
85 union
86 {
87 uint32_t esi;
88 uint64_t rsi;
89 };
90 union
91 {
92 uint32_t ebp;
93 uint64_t rbp;
94 };
95 union
96 {
97 uint32_t eax;
98 uint64_t rax;
99 };
100 union
101 {
102 uint32_t ebx;
103 uint64_t rbx;
104 };
105 union
106 {
107 uint32_t edx;
108 uint64_t rdx;
109 };
110 union
111 {
112 uint32_t ecx;
113 uint64_t rcx;
114 };
115 /* Note: we rely on the exact layout, because we use lss esp, [] in the switcher */
116 uint32_t esp;
117 RTSEL ss;
118 RTSEL ssPadding;
119 /* Note: no overlap with esp here. */
120 uint64_t rsp;
121
122 RTSEL gs;
123 RTSEL gsPadding;
124 RTSEL fs;
125 RTSEL fsPadding;
126 RTSEL es;
127 RTSEL esPadding;
128 RTSEL ds;
129 RTSEL dsPadding;
130 RTSEL cs;
131 RTSEL csPadding[3]; /* 3 words to force 8 byte alignment for the remainder */
132
133 union
134 {
135 X86EFLAGS eflags;
136 X86RFLAGS rflags;
137 };
138 union
139 {
140 uint32_t eip;
141 uint64_t rip;
142 };
143
144 uint64_t r8;
145 uint64_t r9;
146 uint64_t r10;
147 uint64_t r11;
148 uint64_t r12;
149 uint64_t r13;
150 uint64_t r14;
151 uint64_t r15;
152
153 /** Hidden selector registers.
154 * @{ */
155 CPUMSELREGHID esHid;
156 CPUMSELREGHID csHid;
157 CPUMSELREGHID ssHid;
158 CPUMSELREGHID dsHid;
159 CPUMSELREGHID fsHid;
160 CPUMSELREGHID gsHid;
161 /** @} */
162
163} CPUMCTXCORE;
164#pragma pack()
165
166
167/**
168 * CPU context.
169 */
170#pragma pack(1)
171typedef struct CPUMCTX
172{
173 /** FPU state. (16-byte alignment)
174 * @todo This doesn't have to be in X86FXSTATE on CPUs without fxsr - we need a type for the
175 * actual format or convert it (waste of time). */
176 X86FXSTATE fpu;
177
178 /** CPUMCTXCORE Part.
179 * @{ */
180 union
181 {
182 uint32_t edi;
183 uint64_t rdi;
184 };
185 union
186 {
187 uint32_t esi;
188 uint64_t rsi;
189 };
190 union
191 {
192 uint32_t ebp;
193 uint64_t rbp;
194 };
195 union
196 {
197 uint32_t eax;
198 uint64_t rax;
199 };
200 union
201 {
202 uint32_t ebx;
203 uint64_t rbx;
204 };
205 union
206 {
207 uint32_t edx;
208 uint64_t rdx;
209 };
210 union
211 {
212 uint32_t ecx;
213 uint64_t rcx;
214 };
215 /* Note: we rely on the exact layout, because we use lss esp, [] in the switcher */
216 uint32_t esp;
217 RTSEL ss;
218 RTSEL ssPadding;
219 /* Note: no overlap with esp here. */
220 uint64_t rsp;
221
222 RTSEL gs;
223 RTSEL gsPadding;
224 RTSEL fs;
225 RTSEL fsPadding;
226 RTSEL es;
227 RTSEL esPadding;
228 RTSEL ds;
229 RTSEL dsPadding;
230 RTSEL cs;
231 RTSEL csPadding[3]; /* 3 words to force 8 byte alignment for the remainder */
232
233 union
234 {
235 X86EFLAGS eflags;
236 X86RFLAGS rflags;
237 };
238 union
239 {
240 uint32_t eip;
241 uint64_t rip;
242 };
243
244 uint64_t r8;
245 uint64_t r9;
246 uint64_t r10;
247 uint64_t r11;
248 uint64_t r12;
249 uint64_t r13;
250 uint64_t r14;
251 uint64_t r15;
252
253 /** Hidden selector registers.
254 * @{ */
255 CPUMSELREGHID esHid;
256 CPUMSELREGHID csHid;
257 CPUMSELREGHID ssHid;
258 CPUMSELREGHID dsHid;
259 CPUMSELREGHID fsHid;
260 CPUMSELREGHID gsHid;
261 /** @} */
262
263 /** @} */
264
265 /** Control registers.
266 * @{ */
267 uint64_t cr0;
268 uint64_t cr2;
269 uint64_t cr3;
270 uint64_t cr4;
271 uint64_t cr8;
272 /** @} */
273
274 /** Debug registers.
275 * @{ */
276 uint64_t dr0;
277 uint64_t dr1;
278 uint64_t dr2;
279 uint64_t dr3;
280 uint64_t dr4; /**< @todo remove dr4 and dr5. */
281 uint64_t dr5;
282 uint64_t dr6;
283 uint64_t dr7;
284 /* DR8-15 are currently not supported */
285 /** @} */
286
287 /** Global Descriptor Table register. */
288 VBOXGDTR gdtr;
289 uint16_t gdtrPadding;
290 uint32_t gdtrPadding64;/** @todo fix this hack */
291 /** Interrupt Descriptor Table register. */
292 VBOXIDTR idtr;
293 uint16_t idtrPadding;
294 uint32_t idtrPadding64;/** @todo fix this hack */
295 /** The task register.
296 * Only the guest context uses all the members. */
297 RTSEL ldtr;
298 RTSEL ldtrPadding;
299 /** The task register.
300 * Only the guest context uses all the members. */
301 RTSEL tr;
302 RTSEL trPadding;
303
304 /** The sysenter msr registers.
305 * This member is not used by the hypervisor context. */
306 CPUMSYSENTER SysEnter;
307
308 /** Hidden selector registers.
309 * @{ */
310 CPUMSELREGHID ldtrHid;
311 CPUMSELREGHID trHid;
312 /** @} */
313
314 /* padding to get 32byte aligned size */
315 uint32_t padding[4];
316} CPUMCTX;
317#pragma pack()
318
319/**
320 * Gets the CPUMCTXCORE part of a CPUMCTX.
321 */
322#define CPUMCTX2CORE(pCtx) ((PCPUMCTXCORE)(void *)&(pCtx)->edi)
323
324/**
325 * The register set returned by a CPUID operation.
326 */
327typedef struct CPUMCPUID
328{
329 uint32_t eax;
330 uint32_t ebx;
331 uint32_t ecx;
332 uint32_t edx;
333} CPUMCPUID;
334/** Pointer to a CPUID leaf. */
335typedef CPUMCPUID *PCPUMCPUID;
336/** Pointer to a const CPUID leaf. */
337typedef const CPUMCPUID *PCCPUMCPUID;
338
339/**
340 * CPUID feature to set or clear.
341 */
342typedef enum CPUMCPUIDFEATURE
343{
344 CPUMCPUIDFEATURE_INVALID = 0,
345 /** The APIC feature bit. (Std+Ext) */
346 CPUMCPUIDFEATURE_APIC,
347 /** The sysenter/sysexit feature bit. (Std+Ext) */
348 CPUMCPUIDFEATURE_SEP,
349 /** The PAE feature bit. (Std+Ext) */
350 CPUMCPUIDFEATURE_PAE,
351 /** The LONG MODE feature bit. (Ext) */
352 CPUMCPUIDFEATURE_LONG_MODE
353} CPUMCPUIDFEATURE;
354
355
356/** @name Guest Register Getters.
357 * @{ */
358CPUMDECL(void) CPUMGetGuestGDTR(PVM pVM, PVBOXGDTR pGDTR);
359CPUMDECL(uint32_t) CPUMGetGuestIDTR(PVM pVM, uint16_t *pcbLimit);
360CPUMDECL(RTSEL) CPUMGetGuestTR(PVM pVM);
361CPUMDECL(RTSEL) CPUMGetGuestLDTR(PVM pVM);
362CPUMDECL(uint32_t) CPUMGetGuestCR0(PVM pVM);
363CPUMDECL(uint32_t) CPUMGetGuestCR2(PVM pVM);
364CPUMDECL(uint32_t) CPUMGetGuestCR3(PVM pVM);
365CPUMDECL(uint32_t) CPUMGetGuestCR4(PVM pVM);
366CPUMDECL(int) CPUMGetGuestCRx(PVM pVM, uint32_t iReg, uint32_t *pValue);
367CPUMDECL(uint32_t) CPUMGetGuestEFlags(PVM pVM);
368CPUMDECL(uint32_t) CPUMGetGuestEIP(PVM pVM);
369CPUMDECL(uint32_t) CPUMGetGuestEAX(PVM pVM);
370CPUMDECL(uint32_t) CPUMGetGuestEBX(PVM pVM);
371CPUMDECL(uint32_t) CPUMGetGuestECX(PVM pVM);
372CPUMDECL(uint32_t) CPUMGetGuestEDX(PVM pVM);
373CPUMDECL(uint32_t) CPUMGetGuestESI(PVM pVM);
374CPUMDECL(uint32_t) CPUMGetGuestEDI(PVM pVM);
375CPUMDECL(uint32_t) CPUMGetGuestESP(PVM pVM);
376CPUMDECL(uint32_t) CPUMGetGuestEBP(PVM pVM);
377CPUMDECL(RTSEL) CPUMGetGuestCS(PVM pVM);
378CPUMDECL(RTSEL) CPUMGetGuestDS(PVM pVM);
379CPUMDECL(RTSEL) CPUMGetGuestES(PVM pVM);
380CPUMDECL(RTSEL) CPUMGetGuestFS(PVM pVM);
381CPUMDECL(RTSEL) CPUMGetGuestGS(PVM pVM);
382CPUMDECL(RTSEL) CPUMGetGuestSS(PVM pVM);
383CPUMDECL(RTUINTREG) CPUMGetGuestDR0(PVM pVM);
384CPUMDECL(RTUINTREG) CPUMGetGuestDR1(PVM pVM);
385CPUMDECL(RTUINTREG) CPUMGetGuestDR2(PVM pVM);
386CPUMDECL(RTUINTREG) CPUMGetGuestDR3(PVM pVM);
387CPUMDECL(RTUINTREG) CPUMGetGuestDR6(PVM pVM);
388CPUMDECL(RTUINTREG) CPUMGetGuestDR7(PVM pVM);
389CPUMDECL(int) CPUMGetGuestDRx(PVM pVM, uint32_t iReg, uint32_t *pValue);
390CPUMDECL(void) CPUMGetGuestCpuId(PVM pVM, uint32_t iLeaf, uint32_t *pEax, uint32_t *pEbx, uint32_t *pEcx, uint32_t *pEdx);
391CPUMDECL(GCPTRTYPE(PCCPUMCPUID)) CPUMGetGuestCpuIdStdGCPtr(PVM pVM);
392CPUMDECL(GCPTRTYPE(PCCPUMCPUID)) CPUMGetGuestCpuIdExtGCPtr(PVM pVM);
393CPUMDECL(GCPTRTYPE(PCCPUMCPUID)) CPUMGetGuestCpuIdCentaurGCPtr(PVM pVM);
394CPUMDECL(GCPTRTYPE(PCCPUMCPUID)) CPUMGetGuestCpuIdDefGCPtr(PVM pVM);
395CPUMDECL(uint32_t) CPUMGetGuestCpuIdStdMax(PVM pVM);
396CPUMDECL(uint32_t) CPUMGetGuestCpuIdExtMax(PVM pVM);
397CPUMDECL(uint32_t) CPUMGetGuestCpuIdCentaurMax(PVM pVM);
398CPUMDECL(CPUMSELREGHID *) CPUMGetGuestTRHid(PVM pVM);
399/** @} */
400
401/** @name Guest Register Setters.
402 * @{ */
403CPUMDECL(int) CPUMSetGuestGDTR(PVM pVM, uint32_t addr, uint16_t limit);
404CPUMDECL(int) CPUMSetGuestIDTR(PVM pVM, uint32_t addr, uint16_t limit);
405CPUMDECL(int) CPUMSetGuestTR(PVM pVM, uint16_t tr);
406CPUMDECL(int) CPUMSetGuestLDTR(PVM pVM, uint16_t ldtr);
407CPUMDECL(int) CPUMSetGuestCR0(PVM pVM, uint32_t cr0);
408CPUMDECL(int) CPUMSetGuestCR2(PVM pVM, uint32_t cr2);
409CPUMDECL(int) CPUMSetGuestCR3(PVM pVM, uint32_t cr3);
410CPUMDECL(int) CPUMSetGuestCR4(PVM pVM, uint32_t cr4);
411CPUMDECL(int) CPUMSetGuestCRx(PVM pVM, uint32_t iReg, uint32_t Value);
412CPUMDECL(int) CPUMSetGuestDR0(PVM pVM, RTGCUINTREG uDr0);
413CPUMDECL(int) CPUMSetGuestDR1(PVM pVM, RTGCUINTREG uDr1);
414CPUMDECL(int) CPUMSetGuestDR2(PVM pVM, RTGCUINTREG uDr2);
415CPUMDECL(int) CPUMSetGuestDR3(PVM pVM, RTGCUINTREG uDr3);
416CPUMDECL(int) CPUMSetGuestDR6(PVM pVM, RTGCUINTREG uDr6);
417CPUMDECL(int) CPUMSetGuestDR7(PVM pVM, RTGCUINTREG uDr7);
418CPUMDECL(int) CPUMSetGuestDRx(PVM pVM, uint32_t iReg, uint32_t Value);
419CPUMDECL(int) CPUMSetGuestEFlags(PVM pVM, uint32_t eflags);
420CPUMDECL(int) CPUMSetGuestEIP(PVM pVM, uint32_t eip);
421CPUMDECL(int) CPUMSetGuestEAX(PVM pVM, uint32_t eax);
422CPUMDECL(int) CPUMSetGuestEBX(PVM pVM, uint32_t ebx);
423CPUMDECL(int) CPUMSetGuestECX(PVM pVM, uint32_t ecx);
424CPUMDECL(int) CPUMSetGuestEDX(PVM pVM, uint32_t edx);
425CPUMDECL(int) CPUMSetGuestESI(PVM pVM, uint32_t esi);
426CPUMDECL(int) CPUMSetGuestEDI(PVM pVM, uint32_t edi);
427CPUMDECL(int) CPUMSetGuestESP(PVM pVM, uint32_t esp);
428CPUMDECL(int) CPUMSetGuestEBP(PVM pVM, uint32_t ebp);
429CPUMDECL(int) CPUMSetGuestCS(PVM pVM, uint16_t cs);
430CPUMDECL(int) CPUMSetGuestDS(PVM pVM, uint16_t ds);
431CPUMDECL(int) CPUMSetGuestES(PVM pVM, uint16_t es);
432CPUMDECL(int) CPUMSetGuestFS(PVM pVM, uint16_t fs);
433CPUMDECL(int) CPUMSetGuestGS(PVM pVM, uint16_t gs);
434CPUMDECL(int) CPUMSetGuestSS(PVM pVM, uint16_t ss);
435CPUMDECL(void) CPUMSetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature);
436CPUMDECL(void) CPUMClearGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature);
437CPUMDECL(void) CPUMSetGuestCtx(PVM pVM, const PCPUMCTX pCtx);
438/** @} */
439
440/** @name Misc Guest Predicate Functions.
441 * @{ */
442
443/**
444 * Tests if the guest is running in real mode or not.
445 *
446 * @returns true if in real mode, otherwise false.
447 * @param pVM The VM handle.
448 */
449DECLINLINE(bool) CPUMIsGuestInRealMode(PVM pVM)
450{
451 return !(CPUMGetGuestCR0(pVM) & X86_CR0_PE);
452}
453
454/**
455 * Tests if the guest is running in protected or not.
456 *
457 * @returns true if in protected mode, otherwise false.
458 * @param pVM The VM handle.
459 */
460DECLINLINE(bool) CPUMIsGuestInProtectedMode(PVM pVM)
461{
462 return !!(CPUMGetGuestCR0(pVM) & X86_CR0_PE);
463}
464
465/**
466 * Tests if the guest is running in paged protected or not.
467 *
468 * @returns true if in paged protected mode, otherwise false.
469 * @param pVM The VM handle.
470 */
471DECLINLINE(bool) CPUMIsGuestInPagedProtectedMode(PVM pVM)
472{
473 return (CPUMGetGuestCR0(pVM) & (X86_CR0_PE | X86_CR0_PG)) == (X86_CR0_PE | X86_CR0_PG);
474}
475
476/**
477 * Tests if the guest is running in paged protected or not.
478 *
479 * @returns true if in paged protected mode, otherwise false.
480 * @param pVM The VM handle.
481 */
482CPUMDECL(bool) CPUMIsGuestIn16BitCode(PVM pVM);
483
484/**
485 * Tests if the guest is running in paged protected or not.
486 *
487 * @returns true if in paged protected mode, otherwise false.
488 * @param pVM The VM handle.
489 */
490CPUMDECL(bool) CPUMIsGuestIn32BitCode(PVM pVM);
491
492/**
493 * Tests if the guest is running in paged protected or not.
494 *
495 * @returns true if in paged protected mode, otherwise false.
496 * @param pVM The VM handle.
497 */
498CPUMDECL(bool) CPUMIsGuestIn64BitCode(PVM pVM);
499
500/** @} */
501
502
503
504/** @name Hypervisor Register Getters.
505 * @{ */
506CPUMDECL(RTSEL) CPUMGetHyperCS(PVM pVM);
507CPUMDECL(RTSEL) CPUMGetHyperDS(PVM pVM);
508CPUMDECL(RTSEL) CPUMGetHyperES(PVM pVM);
509CPUMDECL(RTSEL) CPUMGetHyperFS(PVM pVM);
510CPUMDECL(RTSEL) CPUMGetHyperGS(PVM pVM);
511CPUMDECL(RTSEL) CPUMGetHyperSS(PVM pVM);
512#if 0 /* these are not correct. */
513CPUMDECL(uint32_t) CPUMGetHyperCR0(PVM pVM);
514CPUMDECL(uint32_t) CPUMGetHyperCR2(PVM pVM);
515CPUMDECL(uint32_t) CPUMGetHyperCR3(PVM pVM);
516CPUMDECL(uint32_t) CPUMGetHyperCR4(PVM pVM);
517#endif
518/** This register is only saved on fatal traps. */
519CPUMDECL(uint32_t) CPUMGetHyperEAX(PVM pVM);
520CPUMDECL(uint32_t) CPUMGetHyperEBX(PVM pVM);
521/** This register is only saved on fatal traps. */
522CPUMDECL(uint32_t) CPUMGetHyperECX(PVM pVM);
523/** This register is only saved on fatal traps. */
524CPUMDECL(uint32_t) CPUMGetHyperEDX(PVM pVM);
525CPUMDECL(uint32_t) CPUMGetHyperESI(PVM pVM);
526CPUMDECL(uint32_t) CPUMGetHyperEDI(PVM pVM);
527CPUMDECL(uint32_t) CPUMGetHyperEBP(PVM pVM);
528CPUMDECL(uint32_t) CPUMGetHyperESP(PVM pVM);
529CPUMDECL(uint32_t) CPUMGetHyperEFlags(PVM pVM);
530CPUMDECL(uint32_t) CPUMGetHyperEIP(PVM pVM);
531CPUMDECL(uint32_t) CPUMGetHyperIDTR(PVM pVM, uint16_t *pcbLimit);
532CPUMDECL(uint32_t) CPUMGetHyperGDTR(PVM pVM, uint16_t *pcbLimit);
533CPUMDECL(RTSEL) CPUMGetHyperLDTR(PVM pVM);
534CPUMDECL(RTGCUINTREG) CPUMGetHyperDR0(PVM pVM);
535CPUMDECL(RTGCUINTREG) CPUMGetHyperDR1(PVM pVM);
536CPUMDECL(RTGCUINTREG) CPUMGetHyperDR2(PVM pVM);
537CPUMDECL(RTGCUINTREG) CPUMGetHyperDR3(PVM pVM);
538CPUMDECL(RTGCUINTREG) CPUMGetHyperDR6(PVM pVM);
539CPUMDECL(RTGCUINTREG) CPUMGetHyperDR7(PVM pVM);
540CPUMDECL(void) CPUMGetHyperCtx(PVM pVM, PCPUMCTX pCtx);
541/** @} */
542
543/** @name Hypervisor Register Setters.
544 * @{ */
545CPUMDECL(void) CPUMSetHyperGDTR(PVM pVM, uint32_t addr, uint16_t limit);
546CPUMDECL(void) CPUMSetHyperLDTR(PVM pVM, RTSEL SelLDTR);
547CPUMDECL(void) CPUMSetHyperIDTR(PVM pVM, uint32_t addr, uint16_t limit);
548CPUMDECL(void) CPUMSetHyperCR3(PVM pVM, uint32_t cr3);
549CPUMDECL(void) CPUMSetHyperTR(PVM pVM, RTSEL SelTR);
550CPUMDECL(void) CPUMSetHyperCS(PVM pVM, RTSEL SelCS);
551CPUMDECL(void) CPUMSetHyperDS(PVM pVM, RTSEL SelDS);
552CPUMDECL(void) CPUMSetHyperES(PVM pVM, RTSEL SelDS);
553CPUMDECL(void) CPUMSetHyperFS(PVM pVM, RTSEL SelDS);
554CPUMDECL(void) CPUMSetHyperGS(PVM pVM, RTSEL SelDS);
555CPUMDECL(void) CPUMSetHyperSS(PVM pVM, RTSEL SelSS);
556CPUMDECL(void) CPUMSetHyperESP(PVM pVM, uint32_t u32ESP);
557CPUMDECL(int) CPUMSetHyperEFlags(PVM pVM, uint32_t Efl);
558CPUMDECL(void) CPUMSetHyperEIP(PVM pVM, uint32_t u32EIP);
559CPUMDECL(void) CPUMSetHyperDR0(PVM pVM, RTGCUINTREG uDr0);
560CPUMDECL(void) CPUMSetHyperDR1(PVM pVM, RTGCUINTREG uDr1);
561CPUMDECL(void) CPUMSetHyperDR2(PVM pVM, RTGCUINTREG uDr2);
562CPUMDECL(void) CPUMSetHyperDR3(PVM pVM, RTGCUINTREG uDr3);
563CPUMDECL(void) CPUMSetHyperDR6(PVM pVM, RTGCUINTREG uDr6);
564CPUMDECL(void) CPUMSetHyperDR7(PVM pVM, RTGCUINTREG uDr7);
565CPUMDECL(void) CPUMSetHyperCtx(PVM pVM, const PCPUMCTX pCtx);
566CPUMDECL(int) CPUMRecalcHyperDRx(PVM pVM);
567/** @} */
568
569CPUMDECL(void) CPUMPushHyper(PVM pVM, uint32_t u32);
570
571/**
572 * Sets or resets an alternative hypervisor context core.
573 *
574 * This is called when we get a hypervisor trap set switch the context
575 * core with the trap frame on the stack. It is called again to reset
576 * back to the default context core when resuming hypervisor execution.
577 *
578 * @param pVM The VM handle.
579 * @param pCtxCore Pointer to the alternative context core or NULL
580 * to go back to the default context core.
581 */
582CPUMDECL(void) CPUMHyperSetCtxCore(PVM pVM, PCPUMCTXCORE pCtxCore);
583
584
585/**
586 * Queries the pointer to the internal CPUMCTX structure
587 *
588 * @returns VBox status code.
589 * @param pVM Handle to the virtual machine.
590 * @param ppCtx Receives the CPUMCTX pointer when successful.
591 */
592CPUMDECL(int) CPUMQueryGuestCtxPtr(PVM pVM, PCPUMCTX *ppCtx);
593
594/**
595 * Queries the pointer to the internal CPUMCTX structure for the hypervisor.
596 *
597 * @returns VBox status code.
598 * @param pVM Handle to the virtual machine.
599 * @param ppCtx Receives the hyper CPUMCTX pointer when successful.
600 */
601CPUMDECL(int) CPUMQueryHyperCtxPtr(PVM pVM, PCPUMCTX *ppCtx);
602
603
604/**
605 * Gets the pointer to the internal CPUMCTXCORE structure.
606 * This is only for reading in order to save a few calls.
607 *
608 * @param pVM Handle to the virtual machine.
609 */
610CPUMDECL(PCCPUMCTXCORE) CPUMGetGuestCtxCore(PVM pVM);
611
612/**
613 * Gets the pointer to the internal CPUMCTXCORE structure for the hypervisor.
614 * This is only for reading in order to save a few calls.
615 *
616 * @param pVM Handle to the virtual machine.
617 */
618CPUMDECL(PCCPUMCTXCORE) CPUMGetHyperCtxCore(PVM pVM);
619
620/**
621 * Sets the guest context core registers.
622 *
623 * @param pVM Handle to the virtual machine.
624 * @param pCtxCore The new context core values.
625 */
626CPUMDECL(void) CPUMSetGuestCtxCore(PVM pVM, PCCPUMCTXCORE pCtxCore);
627
628
629/**
630 * Transforms the guest CPU state to raw-ring mode.
631 *
632 * This function will change the any of the cs and ss register with DPL=0 to DPL=1.
633 *
634 * @returns VBox status. (recompiler failure)
635 * @param pVM VM handle.
636 * @param pCtxCore The context core (for trap usage).
637 * @see @ref pg_raw
638 */
639CPUMDECL(int) CPUMRawEnter(PVM pVM, PCPUMCTXCORE pCtxCore);
640
641/**
642 * Transforms the guest CPU state from raw-ring mode to correct values.
643 *
644 * This function will change any selector registers with DPL=1 to DPL=0.
645 *
646 * @returns Adjusted rc.
647 * @param pVM VM handle.
648 * @param rc Raw mode return code
649 * @param pCtxCore The context core (for trap usage).
650 * @see @ref pg_raw
651 */
652CPUMDECL(int) CPUMRawLeave(PVM pVM, PCPUMCTXCORE pCtxCore, int rc);
653
654/**
655 * Gets the EFLAGS while we're in raw-mode.
656 *
657 * @returns The eflags.
658 * @param pVM The VM handle.
659 * @param pCtxCore The context core.
660 */
661CPUMDECL(uint32_t) CPUMRawGetEFlags(PVM pVM, PCPUMCTXCORE pCtxCore);
662
663/**
664 * Updates the EFLAGS while we're in raw-mode.
665 *
666 * @param pVM The VM handle.
667 * @param pCtxCore The context core.
668 * @param eflags The new EFLAGS value.
669 */
670CPUMDECL(void) CPUMRawSetEFlags(PVM pVM, PCPUMCTXCORE pCtxCore, uint32_t eflags);
671
672/**
673 * Lazily sync in the FPU/XMM state
674 *
675 * This function will change any selector registers with DPL=1 to DPL=0.
676 *
677 * @returns VBox status code.
678 * @param pVM VM handle.
679 */
680CPUMDECL(int) CPUMHandleLazyFPU(PVM pVM);
681
682
683/**
684 * Restore host FPU/XMM state
685 *
686 * @returns VBox status code.
687 * @param pVM VM handle.
688 */
689CPUMDECL(int) CPUMRestoreHostFPUState(PVM pVM);
690
691/** @name Changed flags
692 * These flags are used to keep track of which important register that
693 * have been changed since last they were reset. The only one allowed
694 * to clear them is REM!
695 * @{
696 */
697#define CPUM_CHANGED_FPU_REM RT_BIT(0)
698#define CPUM_CHANGED_CR0 RT_BIT(1)
699#define CPUM_CHANGED_CR4 RT_BIT(2)
700#define CPUM_CHANGED_GLOBAL_TLB_FLUSH RT_BIT(3)
701#define CPUM_CHANGED_CR3 RT_BIT(4)
702#define CPUM_CHANGED_GDTR RT_BIT(5)
703#define CPUM_CHANGED_IDTR RT_BIT(6)
704#define CPUM_CHANGED_LDTR RT_BIT(7)
705#define CPUM_CHANGED_TR RT_BIT(8)
706#define CPUM_CHANGED_SYSENTER_MSR RT_BIT(9)
707#define CPUM_CHANGED_HIDDEN_SEL_REGS RT_BIT(10)
708/** @} */
709
710/**
711 * Gets and resets the changed flags (CPUM_CHANGED_*).
712 *
713 * @returns The changed flags.
714 * @param pVM VM handle.
715 */
716CPUMDECL(unsigned) CPUMGetAndClearChangedFlagsREM(PVM pVM);
717
718/**
719 * Sets the specified changed flags (CPUM_CHANGED_*).
720 *
721 * @param pVM The VM handle.
722 */
723CPUMDECL(void) CPUMSetChangedFlags(PVM pVM, uint32_t fChangedFlags);
724
725/**
726 * Checks if the CPU supports the FXSAVE and FXRSTOR instruction.
727 * @returns true if supported.
728 * @returns false if not supported.
729 * @param pVM The VM handle.
730 */
731CPUMDECL(bool) CPUMSupportsFXSR(PVM pVM);
732
733/**
734 * Checks if the host OS uses the SYSENTER / SYSEXIT instructions.
735 * @returns true if used.
736 * @returns false if not used.
737 * @param pVM The VM handle.
738 */
739CPUMDECL(bool) CPUMIsHostUsingSysEnter(PVM pVM);
740
741/**
742 * Checks if the host OS uses the SYSCALL / SYSRET instructions.
743 * @returns true if used.
744 * @returns false if not used.
745 * @param pVM The VM handle.
746 */
747CPUMDECL(bool) CPUMIsHostUsingSysCall(PVM pVM);
748
749/**
750 * Checks if we activated the FPU/XMM state of the guest OS
751 * @returns true if we did.
752 * @returns false if not.
753 * @param pVM The VM handle.
754 */
755CPUMDECL(bool) CPUMIsGuestFPUStateActive(PVM pVM);
756
757/**
758 * Deactivate the FPU/XMM state of the guest OS
759 * @param pVM The VM handle.
760 */
761CPUMDECL(void) CPUMDeactivateGuestFPUState(PVM pVM);
762
763
764/**
765 * Checks if the hidden selector registers are valid
766 * @returns true if they are.
767 * @returns false if not.
768 * @param pVM The VM handle.
769 */
770CPUMDECL(bool) CPUMAreHiddenSelRegsValid(PVM pVM);
771
772/**
773 * Checks if the hidden selector registers are valid
774 * @param pVM The VM handle.
775 * @param fValid Valid or not
776 */
777CPUMDECL(void) CPUMSetHiddenSelRegsValid(PVM pVM, bool fValid);
778
779/**
780 * Get the current privilege level of the guest.
781 *
782 * @returns cpl
783 * @param pVM VM Handle.
784 * @param pRegFrame Trap register frame.
785 */
786CPUMDECL(uint32_t) CPUMGetGuestCPL(PVM pVM, PCPUMCTXCORE pCtxCore);
787
788/**
789 * CPU modes.
790 */
791typedef enum CPUMMODE
792{
793 /** The usual invalid zero entry. */
794 CPUMMODE_INVALID = 0,
795 /** Real mode. */
796 CPUMMODE_REAL,
797 /** Protected mode (32-bit). */
798 CPUMMODE_PROTECTED,
799 /** Long mode (64-bit). */
800 CPUMMODE_LONG
801} CPUMMODE;
802
803/**
804 * Gets the current guest CPU mode.
805 *
806 * If paging mode is what you need, check out PGMGetGuestMode().
807 *
808 * @returns The CPU mode.
809 * @param pVM The VM handle.
810 */
811CPUMDECL(CPUMMODE) CPUMGetGuestMode(PVM pVM);
812
813
814#ifdef IN_RING3
815/** @defgroup grp_cpum_r3 The CPU Monitor(/Manager) API
816 * @ingroup grp_cpum
817 * @{
818 */
819
820/**
821 * Initializes the CPUM.
822 *
823 * @returns VBox status code.
824 * @param pVM The VM to operate on.
825 */
826CPUMR3DECL(int) CPUMR3Init(PVM pVM);
827
828/**
829 * Applies relocations to data and code managed by this
830 * component. This function will be called at init and
831 * whenever the VMM need to relocate it self inside the GC.
832 *
833 * The CPUM will update the addresses used by the switcher.
834 *
835 * @param pVM The VM.
836 */
837CPUMR3DECL(void) CPUMR3Relocate(PVM pVM);
838
839/**
840 * Terminates the CPUM.
841 *
842 * Termination means cleaning up and freeing all resources,
843 * the VM it self is at this point powered off or suspended.
844 *
845 * @returns VBox status code.
846 * @param pVM The VM to operate on.
847 */
848CPUMR3DECL(int) CPUMR3Term(PVM pVM);
849
850/**
851 * Resets the CPU.
852 *
853 * @param pVM The VM handle.
854 */
855CPUMR3DECL(void) CPUMR3Reset(PVM pVM);
856
857/**
858 * Queries the pointer to the internal CPUMCTX structure
859 *
860 * @returns VBox status code.
861 * @param pVM Handle to the virtual machine.
862 * @param ppCtx Receives the CPUMCTX GC pointer when successful.
863 */
864CPUMR3DECL(int) CPUMR3QueryGuestCtxGCPtr(PVM pVM, GCPTRTYPE(PCPUMCTX) *ppCtx);
865
866
867#ifdef DEBUG
868/**
869 * Debug helper - Saves guest context on raw mode entry (for fatal dump)
870 *
871 * @internal
872 */
873CPUMR3DECL(void) CPUMR3SaveEntryCtx(PVM pVM);
874#endif
875
876/**
877 * API for controlling a few of the CPU features found in CR4.
878 *
879 * Currently only X86_CR4_TSD is accepted as input.
880 *
881 * @returns VBox status code.
882 *
883 * @param pVM The VM handle.
884 * @param fOr The CR4 OR mask.
885 * @param fAnd The CR4 AND mask.
886 */
887CPUMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd);
888
889/** @} */
890#endif
891
892#ifdef IN_GC
893/** @defgroup grp_cpum_gc The CPU Monitor(/Manager) API
894 * @ingroup grp_cpum
895 * @{
896 */
897
898/**
899 * Calls a guest trap/interrupt handler directly
900 * Assumes a trap stack frame has already been setup on the guest's stack!
901 *
902 * @param pRegFrame Original trap/interrupt context
903 * @param selCS Code selector of handler
904 * @param pHandler GC virtual address of handler
905 * @param eflags Callee's EFLAGS
906 * @param selSS Stack selector for handler
907 * @param pEsp Stack address for handler
908 *
909 * This function does not return!
910 *
911 */
912CPUMGCDECL(void) CPUMGCCallGuestTrapHandler(PCPUMCTXCORE pRegFrame, uint32_t selCS, RTGCPTR pHandler, uint32_t eflags, uint32_t selSS, RTGCPTR pEsp);
913
914/**
915 * Performs an iret to V86 code
916 * Assumes a trap stack frame has already been setup on the guest's stack!
917 *
918 * @param pRegFrame Original trap/interrupt context
919 *
920 * This function does not return!
921 */
922CPUMGCDECL(void) CPUMGCCallV86Code(PCPUMCTXCORE pRegFrame);
923
924/** @} */
925#endif
926
927#ifdef IN_RING0
928/** @defgroup grp_cpum_r0 The CPU Monitor(/Manager) API
929 * @ingroup grp_cpum
930 * @{
931 */
932
933/**
934 * Does Ring-0 CPUM initialization.
935 *
936 * This is mainly to check that the Host CPU mode is compatible
937 * with VBox.
938 *
939 * @returns VBox status code.
940 * @param pVM The VM to operate on.
941 */
942CPUMR0DECL(int) CPUMR0Init(PVM pVM);
943
944/** @} */
945#endif
946
947/** @} */
948__END_DECLS
949
950
951#endif
952
953
954
955
956
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