VirtualBox

source: vbox/trunk/include/VBox/cpum.h@ 9721

Last change on this file since 9721 was 9675, checked in by vboxsync, 17 years ago

General cleanup of SELMToFlat.
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File size: 29.5 KB
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1/** @file
2 * CPUM - CPU Monitor(/ Manager).
3 */
4
5/*
6 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * The contents of this file may alternatively be used under the terms
17 * of the Common Development and Distribution License Version 1.0
18 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19 * VirtualBox OSE distribution, in which case the provisions of the
20 * CDDL are applicable instead of those of the GPL.
21 *
22 * You may elect to license modified versions of this file under the
23 * terms and conditions of either the GPL or the CDDL or both.
24 *
25 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
26 * Clara, CA 95054 USA or visit http://www.sun.com if you need
27 * additional information or have any questions.
28 */
29
30#ifndef ___VBox_cpum_h
31#define ___VBox_cpum_h
32
33#include <VBox/cdefs.h>
34#include <VBox/types.h>
35#include <VBox/x86.h>
36
37
38__BEGIN_DECLS
39
40/** @defgroup grp_cpum The CPU Monitor(/Manager) API
41 * @{
42 */
43
44/**
45 * Selector hidden registers.
46 */
47typedef struct CPUMSELREGHID
48{
49 /** Base register.
50 *
51 * Long mode remarks:
52 * - Unused in long mode for CS, DS, ES, SS
53 * - 32 bits for FS & GS; FS(GS)_BASE msr used for the base address
54 * - 64 bits for TR & LDTR
55 */
56 uint64_t u64Base;
57 /** Limit (expanded). */
58 uint32_t u32Limit;
59 /** Flags.
60 * This is the high 32-bit word of the descriptor entry.
61 * Only the flags, dpl and type are used. */
62 X86DESCATTR Attr;
63} CPUMSELREGHID;
64
65
66/**
67 * The sysenter register set.
68 */
69typedef struct CPUMSYSENTER
70{
71 /** Ring 0 cs.
72 * This value + 8 is the Ring 0 ss.
73 * This value + 16 is the Ring 3 cs.
74 * This value + 24 is the Ring 3 ss.
75 */
76 uint64_t cs;
77 /** Ring 0 eip. */
78 uint64_t eip;
79 /** Ring 0 esp. */
80 uint64_t esp;
81} CPUMSYSENTER;
82
83
84/**
85 * CPU context core.
86 */
87#pragma pack(1)
88typedef struct CPUMCTXCORE
89{
90 union
91 {
92 uint32_t edi;
93 uint64_t rdi;
94 };
95 union
96 {
97 uint32_t esi;
98 uint64_t rsi;
99 };
100 union
101 {
102 uint32_t ebp;
103 uint64_t rbp;
104 };
105 union
106 {
107 uint32_t eax;
108 uint64_t rax;
109 };
110 union
111 {
112 uint32_t ebx;
113 uint64_t rbx;
114 };
115 union
116 {
117 uint32_t edx;
118 uint64_t rdx;
119 };
120 union
121 {
122 uint32_t ecx;
123 uint64_t rcx;
124 };
125 union
126 {
127 uint32_t esp;
128 uint64_t rsp;
129 };
130 /* Note: lss esp, [] in the switcher needs some space, so we reserve it here instead of relying on the exact esp & ss layout as before. */
131 uint32_t lss_esp;
132 RTSEL ss;
133 RTSEL ssPadding;
134
135 RTSEL gs;
136 RTSEL gsPadding;
137 RTSEL fs;
138 RTSEL fsPadding;
139 RTSEL es;
140 RTSEL esPadding;
141 RTSEL ds;
142 RTSEL dsPadding;
143 RTSEL cs;
144 RTSEL csPadding[3]; /* 3 words to force 8 byte alignment for the remainder */
145
146 union
147 {
148 X86EFLAGS eflags;
149 X86RFLAGS rflags;
150 };
151 union
152 {
153 uint32_t eip;
154 uint64_t rip;
155 };
156
157 uint64_t r8;
158 uint64_t r9;
159 uint64_t r10;
160 uint64_t r11;
161 uint64_t r12;
162 uint64_t r13;
163 uint64_t r14;
164 uint64_t r15;
165
166 /** Hidden selector registers.
167 * @{ */
168 CPUMSELREGHID esHid;
169 CPUMSELREGHID csHid;
170 CPUMSELREGHID ssHid;
171 CPUMSELREGHID dsHid;
172 CPUMSELREGHID fsHid;
173 CPUMSELREGHID gsHid;
174 /** @} */
175
176} CPUMCTXCORE;
177#pragma pack()
178
179
180/**
181 * CPU context.
182 */
183#pragma pack(1)
184typedef struct CPUMCTX
185{
186 /** FPU state. (16-byte alignment)
187 * @todo This doesn't have to be in X86FXSTATE on CPUs without fxsr - we need a type for the
188 * actual format or convert it (waste of time). */
189 X86FXSTATE fpu;
190
191 /** CPUMCTXCORE Part.
192 * @{ */
193 union
194 {
195 uint32_t edi;
196 uint64_t rdi;
197 };
198 union
199 {
200 uint32_t esi;
201 uint64_t rsi;
202 };
203 union
204 {
205 uint32_t ebp;
206 uint64_t rbp;
207 };
208 union
209 {
210 uint32_t eax;
211 uint64_t rax;
212 };
213 union
214 {
215 uint32_t ebx;
216 uint64_t rbx;
217 };
218 union
219 {
220 uint32_t edx;
221 uint64_t rdx;
222 };
223 union
224 {
225 uint32_t ecx;
226 uint64_t rcx;
227 };
228 union
229 {
230 uint32_t esp;
231 uint64_t rsp;
232 };
233 /* Note: lss esp, [] in the switcher needs some space, so we reserve it here instead of relying on the exact esp & ss layout as before (prevented us from using a union with rsp). */
234 uint32_t lss_esp;
235 RTSEL ss;
236 RTSEL ssPadding;
237
238 RTSEL gs;
239 RTSEL gsPadding;
240 RTSEL fs;
241 RTSEL fsPadding;
242 RTSEL es;
243 RTSEL esPadding;
244 RTSEL ds;
245 RTSEL dsPadding;
246 RTSEL cs;
247 RTSEL csPadding[3]; /* 3 words to force 8 byte alignment for the remainder */
248
249 union
250 {
251 X86EFLAGS eflags;
252 X86RFLAGS rflags;
253 };
254 union
255 {
256 uint32_t eip;
257 uint64_t rip;
258 };
259
260 uint64_t r8;
261 uint64_t r9;
262 uint64_t r10;
263 uint64_t r11;
264 uint64_t r12;
265 uint64_t r13;
266 uint64_t r14;
267 uint64_t r15;
268
269 /** Hidden selector registers.
270 * @{ */
271 CPUMSELREGHID esHid;
272 CPUMSELREGHID csHid;
273 CPUMSELREGHID ssHid;
274 CPUMSELREGHID dsHid;
275 CPUMSELREGHID fsHid;
276 CPUMSELREGHID gsHid;
277 /** @} */
278
279 /** @} */
280
281 /** Control registers.
282 * @{ */
283 uint64_t cr0;
284 uint64_t cr2;
285 uint64_t cr3;
286 uint64_t cr4;
287 uint64_t cr8;
288 /** @} */
289
290 /** Debug registers.
291 * @{ */
292 uint64_t dr0;
293 uint64_t dr1;
294 uint64_t dr2;
295 uint64_t dr3;
296 uint64_t dr4; /**< @todo remove dr4 and dr5. */
297 uint64_t dr5;
298 uint64_t dr6;
299 uint64_t dr7;
300 /* DR8-15 are currently not supported */
301 /** @} */
302
303 /** Global Descriptor Table register. */
304 VBOXGDTR gdtr;
305 uint16_t gdtrPadding;
306 /** Interrupt Descriptor Table register. */
307 VBOXIDTR idtr;
308 uint16_t idtrPadding;
309 /** The task register.
310 * Only the guest context uses all the members. */
311 RTSEL ldtr;
312 RTSEL ldtrPadding;
313 /** The task register.
314 * Only the guest context uses all the members. */
315 RTSEL tr;
316 RTSEL trPadding;
317
318 /** The sysenter msr registers.
319 * This member is not used by the hypervisor context. */
320 CPUMSYSENTER SysEnter;
321
322 /** System MSRs.
323 * @{ */
324 uint64_t msrEFER;
325 uint64_t msrSTAR; /* legacy syscall eip, cs & ss */
326 uint64_t msrPAT;
327 uint64_t msrLSTAR; /* 64 bits mode syscall rip */
328 uint64_t msrCSTAR; /* compatibility mode syscall rip */
329 uint64_t msrSFMASK; /* syscall flag mask */
330 uint64_t msrFSBASE;
331 uint64_t msrGSBASE;
332 uint64_t msrKERNELGSBASE;/* swapgs exchange value */
333 /** @} */
334
335 /** Hidden selector registers.
336 * @{ */
337 CPUMSELREGHID ldtrHid;
338 CPUMSELREGHID trHid;
339 /** @} */
340
341 /* padding to get 32byte aligned size */
342 uint32_t padding[2];
343} CPUMCTX;
344#pragma pack()
345
346/**
347 * Gets the CPUMCTXCORE part of a CPUMCTX.
348 */
349#define CPUMCTX2CORE(pCtx) ((PCPUMCTXCORE)(void *)&(pCtx)->edi)
350
351/**
352 * The register set returned by a CPUID operation.
353 */
354typedef struct CPUMCPUID
355{
356 uint32_t eax;
357 uint32_t ebx;
358 uint32_t ecx;
359 uint32_t edx;
360} CPUMCPUID;
361/** Pointer to a CPUID leaf. */
362typedef CPUMCPUID *PCPUMCPUID;
363/** Pointer to a const CPUID leaf. */
364typedef const CPUMCPUID *PCCPUMCPUID;
365
366/**
367 * CPUID feature to set or clear.
368 */
369typedef enum CPUMCPUIDFEATURE
370{
371 CPUMCPUIDFEATURE_INVALID = 0,
372 /** The APIC feature bit. (Std+Ext) */
373 CPUMCPUIDFEATURE_APIC,
374 /** The sysenter/sysexit feature bit. (Std) */
375 CPUMCPUIDFEATURE_SEP,
376 /** The SYSCALL/SYSEXIT feature bit (64 bits mode only for Intel CPUs). (Ext) */
377 CPUMCPUIDFEATURE_SYSCALL,
378 /** The PAE feature bit. (Std+Ext) */
379 CPUMCPUIDFEATURE_PAE,
380 /** The NXE feature bit. (Ext) */
381 CPUMCPUIDFEATURE_NXE,
382 /** The LAHF/SAHF feature bit (64 bits mode only). (Ext) */
383 CPUMCPUIDFEATURE_LAHF,
384 /** The LONG MODE feature bit. (Ext) */
385 CPUMCPUIDFEATURE_LONG_MODE
386} CPUMCPUIDFEATURE;
387
388/*
389 * CPU Vendor.
390 */
391typedef enum CPUMCPUVENDOR
392{
393 CPUMCPUVENDOR_INVALID = 0,
394 CPUMCPUVENDOR_INTEL,
395 CPUMCPUVENDOR_AMD,
396 CPUMCPUVENDOR_VIA,
397 CPUMCPUVENDOR_UNKNOWN,
398 /** 32bit hackishness. */
399 CPUMCPUVENDOR_32BIT_HACK = 0x7fffffff
400} CPUMCPUVENDOR;
401
402
403/** @name Guest Register Getters.
404 * @{ */
405CPUMDECL(void) CPUMGetGuestGDTR(PVM pVM, PVBOXGDTR pGDTR);
406CPUMDECL(uint32_t) CPUMGetGuestIDTR(PVM pVM, uint16_t *pcbLimit);
407CPUMDECL(RTSEL) CPUMGetGuestTR(PVM pVM);
408CPUMDECL(RTSEL) CPUMGetGuestLDTR(PVM pVM);
409CPUMDECL(uint64_t) CPUMGetGuestCR0(PVM pVM);
410CPUMDECL(uint64_t) CPUMGetGuestCR2(PVM pVM);
411CPUMDECL(uint64_t) CPUMGetGuestCR3(PVM pVM);
412CPUMDECL(uint64_t) CPUMGetGuestCR4(PVM pVM);
413CPUMDECL(int) CPUMGetGuestCRx(PVM pVM, unsigned iReg, uint64_t *pValue);
414CPUMDECL(uint32_t) CPUMGetGuestEFlags(PVM pVM);
415CPUMDECL(uint32_t) CPUMGetGuestEIP(PVM pVM);
416CPUMDECL(uint32_t) CPUMGetGuestEAX(PVM pVM);
417CPUMDECL(uint32_t) CPUMGetGuestEBX(PVM pVM);
418CPUMDECL(uint32_t) CPUMGetGuestECX(PVM pVM);
419CPUMDECL(uint32_t) CPUMGetGuestEDX(PVM pVM);
420CPUMDECL(uint32_t) CPUMGetGuestESI(PVM pVM);
421CPUMDECL(uint32_t) CPUMGetGuestEDI(PVM pVM);
422CPUMDECL(uint32_t) CPUMGetGuestESP(PVM pVM);
423CPUMDECL(uint32_t) CPUMGetGuestEBP(PVM pVM);
424CPUMDECL(RTSEL) CPUMGetGuestCS(PVM pVM);
425CPUMDECL(RTSEL) CPUMGetGuestDS(PVM pVM);
426CPUMDECL(RTSEL) CPUMGetGuestES(PVM pVM);
427CPUMDECL(RTSEL) CPUMGetGuestFS(PVM pVM);
428CPUMDECL(RTSEL) CPUMGetGuestGS(PVM pVM);
429CPUMDECL(RTSEL) CPUMGetGuestSS(PVM pVM);
430CPUMDECL(uint64_t) CPUMGetGuestDR0(PVM pVM);
431CPUMDECL(uint64_t) CPUMGetGuestDR1(PVM pVM);
432CPUMDECL(uint64_t) CPUMGetGuestDR2(PVM pVM);
433CPUMDECL(uint64_t) CPUMGetGuestDR3(PVM pVM);
434CPUMDECL(uint64_t) CPUMGetGuestDR6(PVM pVM);
435CPUMDECL(uint64_t) CPUMGetGuestDR7(PVM pVM);
436CPUMDECL(int) CPUMGetGuestDRx(PVM pVM, uint32_t iReg, uint64_t *pValue);
437CPUMDECL(void) CPUMGetGuestCpuId(PVM pVM, uint32_t iLeaf, uint32_t *pEax, uint32_t *pEbx, uint32_t *pEcx, uint32_t *pEdx);
438CPUMDECL(RCPTRTYPE(PCCPUMCPUID)) CPUMGetGuestCpuIdStdGCPtr(PVM pVM);
439CPUMDECL(RCPTRTYPE(PCCPUMCPUID)) CPUMGetGuestCpuIdExtGCPtr(PVM pVM);
440CPUMDECL(RCPTRTYPE(PCCPUMCPUID)) CPUMGetGuestCpuIdCentaurGCPtr(PVM pVM);
441CPUMDECL(RCPTRTYPE(PCCPUMCPUID)) CPUMGetGuestCpuIdDefGCPtr(PVM pVM);
442CPUMDECL(uint32_t) CPUMGetGuestCpuIdStdMax(PVM pVM);
443CPUMDECL(uint32_t) CPUMGetGuestCpuIdExtMax(PVM pVM);
444CPUMDECL(uint32_t) CPUMGetGuestCpuIdCentaurMax(PVM pVM);
445CPUMDECL(CPUMSELREGHID *) CPUMGetGuestTRHid(PVM pVM);
446CPUMDECL(uint64_t) CPUMGetGuestEFER(PVM pVM);
447CPUMDECL(uint64_t) CPUMGetGuestFSBASE(PVM pVM);
448CPUMDECL(uint64_t) CPUMGetGuestGSBASE(PVM pVM);
449/** @} */
450
451/** @name Guest Register Setters.
452 * @{ */
453CPUMDECL(int) CPUMSetGuestGDTR(PVM pVM, uint32_t addr, uint16_t limit);
454CPUMDECL(int) CPUMSetGuestIDTR(PVM pVM, uint32_t addr, uint16_t limit);
455CPUMDECL(int) CPUMSetGuestTR(PVM pVM, uint16_t tr);
456CPUMDECL(int) CPUMSetGuestLDTR(PVM pVM, uint16_t ldtr);
457CPUMDECL(int) CPUMSetGuestCR0(PVM pVM, uint64_t cr0);
458CPUMDECL(int) CPUMSetGuestCR2(PVM pVM, uint64_t cr2);
459CPUMDECL(int) CPUMSetGuestCR3(PVM pVM, uint64_t cr3);
460CPUMDECL(int) CPUMSetGuestCR4(PVM pVM, uint64_t cr4);
461CPUMDECL(int) CPUMSetGuestDR0(PVM pVM, uint64_t uDr0);
462CPUMDECL(int) CPUMSetGuestDR1(PVM pVM, uint64_t uDr1);
463CPUMDECL(int) CPUMSetGuestDR2(PVM pVM, uint64_t uDr2);
464CPUMDECL(int) CPUMSetGuestDR3(PVM pVM, uint64_t uDr3);
465CPUMDECL(int) CPUMSetGuestDR6(PVM pVM, uint64_t uDr6);
466CPUMDECL(int) CPUMSetGuestDR7(PVM pVM, uint64_t uDr7);
467CPUMDECL(int) CPUMSetGuestDRx(PVM pVM, uint32_t iReg, uint64_t Value);
468CPUMDECL(int) CPUMSetGuestEFlags(PVM pVM, uint32_t eflags);
469CPUMDECL(int) CPUMSetGuestEIP(PVM pVM, uint32_t eip);
470CPUMDECL(int) CPUMSetGuestEAX(PVM pVM, uint32_t eax);
471CPUMDECL(int) CPUMSetGuestEBX(PVM pVM, uint32_t ebx);
472CPUMDECL(int) CPUMSetGuestECX(PVM pVM, uint32_t ecx);
473CPUMDECL(int) CPUMSetGuestEDX(PVM pVM, uint32_t edx);
474CPUMDECL(int) CPUMSetGuestESI(PVM pVM, uint32_t esi);
475CPUMDECL(int) CPUMSetGuestEDI(PVM pVM, uint32_t edi);
476CPUMDECL(int) CPUMSetGuestESP(PVM pVM, uint32_t esp);
477CPUMDECL(int) CPUMSetGuestEBP(PVM pVM, uint32_t ebp);
478CPUMDECL(int) CPUMSetGuestCS(PVM pVM, uint16_t cs);
479CPUMDECL(int) CPUMSetGuestDS(PVM pVM, uint16_t ds);
480CPUMDECL(int) CPUMSetGuestES(PVM pVM, uint16_t es);
481CPUMDECL(int) CPUMSetGuestFS(PVM pVM, uint16_t fs);
482CPUMDECL(int) CPUMSetGuestGS(PVM pVM, uint16_t gs);
483CPUMDECL(int) CPUMSetGuestSS(PVM pVM, uint16_t ss);
484CPUMDECL(void) CPUMSetGuestEFER(PVM pVM, uint64_t val);
485CPUMDECL(void) CPUMSetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature);
486CPUMDECL(void) CPUMClearGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature);
487CPUMDECL(bool) CPUMGetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature);
488CPUMDECL(void) CPUMSetGuestCtx(PVM pVM, const PCPUMCTX pCtx);
489/** @} */
490
491/** @name Misc Guest Predicate Functions.
492 * @{ */
493
494/**
495 * Tests if the guest is running in real mode or not.
496 *
497 * @returns true if in real mode, otherwise false.
498 * @param pVM The VM handle.
499 */
500DECLINLINE(bool) CPUMIsGuestInRealMode(PVM pVM)
501{
502 return !(CPUMGetGuestCR0(pVM) & X86_CR0_PE);
503}
504
505/**
506 * Tests if the guest is running in protected or not.
507 *
508 * @returns true if in protected mode, otherwise false.
509 * @param pVM The VM handle.
510 */
511DECLINLINE(bool) CPUMIsGuestInProtectedMode(PVM pVM)
512{
513 return !!(CPUMGetGuestCR0(pVM) & X86_CR0_PE);
514}
515
516/**
517 * Tests if the guest is running in paged protected or not.
518 *
519 * @returns true if in paged protected mode, otherwise false.
520 * @param pVM The VM handle.
521 */
522DECLINLINE(bool) CPUMIsGuestInPagedProtectedMode(PVM pVM)
523{
524 return (CPUMGetGuestCR0(pVM) & (X86_CR0_PE | X86_CR0_PG)) == (X86_CR0_PE | X86_CR0_PG);
525}
526
527/**
528 * Tests if the guest is running in long mode or not.
529 *
530 * @returns true if in long mode, otherwise false.
531 * @param pVM The VM handle.
532 */
533DECLINLINE(bool) CPUMIsGuestInLongMode(PVM pVM)
534{
535 return (CPUMGetGuestEFER(pVM) & MSR_K6_EFER_LMA) == MSR_K6_EFER_LMA;
536}
537
538/**
539 * Tests if the guest is running in 16 bits paged protected or not.
540 *
541 * @returns true if in paged protected mode, otherwise false.
542 * @param pVM The VM handle.
543 */
544CPUMDECL(bool) CPUMIsGuestIn16BitCode(PVM pVM);
545
546/**
547 * Tests if the guest is running in 32 bits paged protected or not.
548 *
549 * @returns true if in paged protected mode, otherwise false.
550 * @param pVM The VM handle.
551 */
552CPUMDECL(bool) CPUMIsGuestIn32BitCode(PVM pVM);
553
554/**
555 * Tests if the guest is running in 64 bits mode or not.
556 *
557 * @returns true if in 64 bits protected mode, otherwise false.
558 * @param pVM The VM handle.
559 * @param pCtx Current CPU context
560 */
561DECLINLINE(bool) CPUMIsGuestIn64BitCode(PVM pVM, PCCPUMCTXCORE pCtx)
562{
563 if (!CPUMIsGuestInLongMode(pVM))
564 return false;
565
566 return pCtx->csHid.Attr.n.u1Long;
567}
568
569/**
570 * Gets the CPU vendor
571 *
572 * @returns CPU vendor
573 * @param pVM The VM handle.
574 */
575CPUMDECL(CPUMCPUVENDOR) CPUMGetCPUVendor(PVM pVM);
576
577
578/** @} */
579
580
581
582/** @name Hypervisor Register Getters.
583 * @{ */
584CPUMDECL(RTSEL) CPUMGetHyperCS(PVM pVM);
585CPUMDECL(RTSEL) CPUMGetHyperDS(PVM pVM);
586CPUMDECL(RTSEL) CPUMGetHyperES(PVM pVM);
587CPUMDECL(RTSEL) CPUMGetHyperFS(PVM pVM);
588CPUMDECL(RTSEL) CPUMGetHyperGS(PVM pVM);
589CPUMDECL(RTSEL) CPUMGetHyperSS(PVM pVM);
590#if 0 /* these are not correct. */
591CPUMDECL(uint32_t) CPUMGetHyperCR0(PVM pVM);
592CPUMDECL(uint32_t) CPUMGetHyperCR2(PVM pVM);
593CPUMDECL(uint32_t) CPUMGetHyperCR3(PVM pVM);
594CPUMDECL(uint32_t) CPUMGetHyperCR4(PVM pVM);
595#endif
596/** This register is only saved on fatal traps. */
597CPUMDECL(uint32_t) CPUMGetHyperEAX(PVM pVM);
598CPUMDECL(uint32_t) CPUMGetHyperEBX(PVM pVM);
599/** This register is only saved on fatal traps. */
600CPUMDECL(uint32_t) CPUMGetHyperECX(PVM pVM);
601/** This register is only saved on fatal traps. */
602CPUMDECL(uint32_t) CPUMGetHyperEDX(PVM pVM);
603CPUMDECL(uint32_t) CPUMGetHyperESI(PVM pVM);
604CPUMDECL(uint32_t) CPUMGetHyperEDI(PVM pVM);
605CPUMDECL(uint32_t) CPUMGetHyperEBP(PVM pVM);
606CPUMDECL(uint32_t) CPUMGetHyperESP(PVM pVM);
607CPUMDECL(uint32_t) CPUMGetHyperEFlags(PVM pVM);
608CPUMDECL(uint32_t) CPUMGetHyperEIP(PVM pVM);
609CPUMDECL(uint32_t) CPUMGetHyperIDTR(PVM pVM, uint16_t *pcbLimit);
610CPUMDECL(uint32_t) CPUMGetHyperGDTR(PVM pVM, uint16_t *pcbLimit);
611CPUMDECL(RTSEL) CPUMGetHyperLDTR(PVM pVM);
612CPUMDECL(RTGCUINTREG) CPUMGetHyperDR0(PVM pVM);
613CPUMDECL(RTGCUINTREG) CPUMGetHyperDR1(PVM pVM);
614CPUMDECL(RTGCUINTREG) CPUMGetHyperDR2(PVM pVM);
615CPUMDECL(RTGCUINTREG) CPUMGetHyperDR3(PVM pVM);
616CPUMDECL(RTGCUINTREG) CPUMGetHyperDR6(PVM pVM);
617CPUMDECL(RTGCUINTREG) CPUMGetHyperDR7(PVM pVM);
618CPUMDECL(void) CPUMGetHyperCtx(PVM pVM, PCPUMCTX pCtx);
619/** @} */
620
621/** @name Hypervisor Register Setters.
622 * @{ */
623CPUMDECL(void) CPUMSetHyperGDTR(PVM pVM, uint32_t addr, uint16_t limit);
624CPUMDECL(void) CPUMSetHyperLDTR(PVM pVM, RTSEL SelLDTR);
625CPUMDECL(void) CPUMSetHyperIDTR(PVM pVM, uint32_t addr, uint16_t limit);
626CPUMDECL(void) CPUMSetHyperCR3(PVM pVM, uint32_t cr3);
627CPUMDECL(void) CPUMSetHyperTR(PVM pVM, RTSEL SelTR);
628CPUMDECL(void) CPUMSetHyperCS(PVM pVM, RTSEL SelCS);
629CPUMDECL(void) CPUMSetHyperDS(PVM pVM, RTSEL SelDS);
630CPUMDECL(void) CPUMSetHyperES(PVM pVM, RTSEL SelDS);
631CPUMDECL(void) CPUMSetHyperFS(PVM pVM, RTSEL SelDS);
632CPUMDECL(void) CPUMSetHyperGS(PVM pVM, RTSEL SelDS);
633CPUMDECL(void) CPUMSetHyperSS(PVM pVM, RTSEL SelSS);
634CPUMDECL(void) CPUMSetHyperESP(PVM pVM, uint32_t u32ESP);
635CPUMDECL(int) CPUMSetHyperEFlags(PVM pVM, uint32_t Efl);
636CPUMDECL(void) CPUMSetHyperEIP(PVM pVM, uint32_t u32EIP);
637CPUMDECL(void) CPUMSetHyperDR0(PVM pVM, RTGCUINTREG uDr0);
638CPUMDECL(void) CPUMSetHyperDR1(PVM pVM, RTGCUINTREG uDr1);
639CPUMDECL(void) CPUMSetHyperDR2(PVM pVM, RTGCUINTREG uDr2);
640CPUMDECL(void) CPUMSetHyperDR3(PVM pVM, RTGCUINTREG uDr3);
641CPUMDECL(void) CPUMSetHyperDR6(PVM pVM, RTGCUINTREG uDr6);
642CPUMDECL(void) CPUMSetHyperDR7(PVM pVM, RTGCUINTREG uDr7);
643CPUMDECL(void) CPUMSetHyperCtx(PVM pVM, const PCPUMCTX pCtx);
644CPUMDECL(int) CPUMRecalcHyperDRx(PVM pVM);
645/** @} */
646
647CPUMDECL(void) CPUMPushHyper(PVM pVM, uint32_t u32);
648
649/**
650 * Sets or resets an alternative hypervisor context core.
651 *
652 * This is called when we get a hypervisor trap set switch the context
653 * core with the trap frame on the stack. It is called again to reset
654 * back to the default context core when resuming hypervisor execution.
655 *
656 * @param pVM The VM handle.
657 * @param pCtxCore Pointer to the alternative context core or NULL
658 * to go back to the default context core.
659 */
660CPUMDECL(void) CPUMHyperSetCtxCore(PVM pVM, PCPUMCTXCORE pCtxCore);
661
662
663/**
664 * Queries the pointer to the internal CPUMCTX structure
665 *
666 * @returns VBox status code.
667 * @param pVM Handle to the virtual machine.
668 * @param ppCtx Receives the CPUMCTX pointer when successful.
669 */
670CPUMDECL(int) CPUMQueryGuestCtxPtr(PVM pVM, PCPUMCTX *ppCtx);
671
672/**
673 * Queries the pointer to the internal CPUMCTX structure for the hypervisor.
674 *
675 * @returns VBox status code.
676 * @param pVM Handle to the virtual machine.
677 * @param ppCtx Receives the hyper CPUMCTX pointer when successful.
678 */
679CPUMDECL(int) CPUMQueryHyperCtxPtr(PVM pVM, PCPUMCTX *ppCtx);
680
681
682/**
683 * Gets the pointer to the internal CPUMCTXCORE structure.
684 * This is only for reading in order to save a few calls.
685 *
686 * @param pVM Handle to the virtual machine.
687 */
688CPUMDECL(PCCPUMCTXCORE) CPUMGetGuestCtxCore(PVM pVM);
689
690/**
691 * Gets the pointer to the internal CPUMCTXCORE structure for the hypervisor.
692 * This is only for reading in order to save a few calls.
693 *
694 * @param pVM Handle to the virtual machine.
695 */
696CPUMDECL(PCCPUMCTXCORE) CPUMGetHyperCtxCore(PVM pVM);
697
698/**
699 * Sets the guest context core registers.
700 *
701 * @param pVM Handle to the virtual machine.
702 * @param pCtxCore The new context core values.
703 */
704CPUMDECL(void) CPUMSetGuestCtxCore(PVM pVM, PCCPUMCTXCORE pCtxCore);
705
706
707/**
708 * Transforms the guest CPU state to raw-ring mode.
709 *
710 * This function will change the any of the cs and ss register with DPL=0 to DPL=1.
711 *
712 * @returns VBox status. (recompiler failure)
713 * @param pVM VM handle.
714 * @param pCtxCore The context core (for trap usage).
715 * @see @ref pg_raw
716 */
717CPUMDECL(int) CPUMRawEnter(PVM pVM, PCPUMCTXCORE pCtxCore);
718
719/**
720 * Transforms the guest CPU state from raw-ring mode to correct values.
721 *
722 * This function will change any selector registers with DPL=1 to DPL=0.
723 *
724 * @returns Adjusted rc.
725 * @param pVM VM handle.
726 * @param rc Raw mode return code
727 * @param pCtxCore The context core (for trap usage).
728 * @see @ref pg_raw
729 */
730CPUMDECL(int) CPUMRawLeave(PVM pVM, PCPUMCTXCORE pCtxCore, int rc);
731
732/**
733 * Gets the EFLAGS while we're in raw-mode.
734 *
735 * @returns The eflags.
736 * @param pVM The VM handle.
737 * @param pCtxCore The context core.
738 */
739CPUMDECL(uint32_t) CPUMRawGetEFlags(PVM pVM, PCPUMCTXCORE pCtxCore);
740
741/**
742 * Updates the EFLAGS while we're in raw-mode.
743 *
744 * @param pVM The VM handle.
745 * @param pCtxCore The context core.
746 * @param eflags The new EFLAGS value.
747 */
748CPUMDECL(void) CPUMRawSetEFlags(PVM pVM, PCPUMCTXCORE pCtxCore, uint32_t eflags);
749
750/**
751 * Lazily sync in the FPU/XMM state
752 *
753 * This function will change any selector registers with DPL=1 to DPL=0.
754 *
755 * @returns VBox status code.
756 * @param pVM VM handle.
757 */
758CPUMDECL(int) CPUMHandleLazyFPU(PVM pVM);
759
760
761/**
762 * Restore host FPU/XMM state
763 *
764 * @returns VBox status code.
765 * @param pVM VM handle.
766 */
767CPUMDECL(int) CPUMRestoreHostFPUState(PVM pVM);
768
769/** @name Changed flags
770 * These flags are used to keep track of which important register that
771 * have been changed since last they were reset. The only one allowed
772 * to clear them is REM!
773 * @{
774 */
775#define CPUM_CHANGED_FPU_REM RT_BIT(0)
776#define CPUM_CHANGED_CR0 RT_BIT(1)
777#define CPUM_CHANGED_CR4 RT_BIT(2)
778#define CPUM_CHANGED_GLOBAL_TLB_FLUSH RT_BIT(3)
779#define CPUM_CHANGED_CR3 RT_BIT(4)
780#define CPUM_CHANGED_GDTR RT_BIT(5)
781#define CPUM_CHANGED_IDTR RT_BIT(6)
782#define CPUM_CHANGED_LDTR RT_BIT(7)
783#define CPUM_CHANGED_TR RT_BIT(8)
784#define CPUM_CHANGED_SYSENTER_MSR RT_BIT(9)
785#define CPUM_CHANGED_HIDDEN_SEL_REGS RT_BIT(10)
786#define CPUM_CHANGED_CPUID RT_BIT(11)
787/** @} */
788
789/**
790 * Gets and resets the changed flags (CPUM_CHANGED_*).
791 *
792 * @returns The changed flags.
793 * @param pVM VM handle.
794 */
795CPUMDECL(unsigned) CPUMGetAndClearChangedFlagsREM(PVM pVM);
796
797/**
798 * Sets the specified changed flags (CPUM_CHANGED_*).
799 *
800 * @param pVM The VM handle.
801 */
802CPUMDECL(void) CPUMSetChangedFlags(PVM pVM, uint32_t fChangedFlags);
803
804/**
805 * Checks if the CPU supports the FXSAVE and FXRSTOR instruction.
806 * @returns true if supported.
807 * @returns false if not supported.
808 * @param pVM The VM handle.
809 */
810CPUMDECL(bool) CPUMSupportsFXSR(PVM pVM);
811
812/**
813 * Checks if the host OS uses the SYSENTER / SYSEXIT instructions.
814 * @returns true if used.
815 * @returns false if not used.
816 * @param pVM The VM handle.
817 */
818CPUMDECL(bool) CPUMIsHostUsingSysEnter(PVM pVM);
819
820/**
821 * Checks if the host OS uses the SYSCALL / SYSRET instructions.
822 * @returns true if used.
823 * @returns false if not used.
824 * @param pVM The VM handle.
825 */
826CPUMDECL(bool) CPUMIsHostUsingSysCall(PVM pVM);
827
828/**
829 * Checks if we activated the FPU/XMM state of the guest OS
830 * @returns true if we did.
831 * @returns false if not.
832 * @param pVM The VM handle.
833 */
834CPUMDECL(bool) CPUMIsGuestFPUStateActive(PVM pVM);
835
836/**
837 * Deactivate the FPU/XMM state of the guest OS
838 * @param pVM The VM handle.
839 */
840CPUMDECL(void) CPUMDeactivateGuestFPUState(PVM pVM);
841
842
843/**
844 * Checks if the hidden selector registers are valid
845 * @returns true if they are.
846 * @returns false if not.
847 * @param pVM The VM handle.
848 */
849CPUMDECL(bool) CPUMAreHiddenSelRegsValid(PVM pVM);
850
851/**
852 * Checks if the hidden selector registers are valid
853 * @param pVM The VM handle.
854 * @param fValid Valid or not
855 */
856CPUMDECL(void) CPUMSetHiddenSelRegsValid(PVM pVM, bool fValid);
857
858/**
859 * Get the current privilege level of the guest.
860 *
861 * @returns cpl
862 * @param pVM VM Handle.
863 * @param pRegFrame Trap register frame.
864 */
865CPUMDECL(uint32_t) CPUMGetGuestCPL(PVM pVM, PCPUMCTXCORE pCtxCore);
866
867/**
868 * CPU modes.
869 */
870typedef enum CPUMMODE
871{
872 /** The usual invalid zero entry. */
873 CPUMMODE_INVALID = 0,
874 /** Real mode. */
875 CPUMMODE_REAL,
876 /** Protected mode (32-bit). */
877 CPUMMODE_PROTECTED,
878 /** Long mode (64-bit). */
879 CPUMMODE_LONG
880} CPUMMODE;
881
882/**
883 * Gets the current guest CPU mode.
884 *
885 * If paging mode is what you need, check out PGMGetGuestMode().
886 *
887 * @returns The CPU mode.
888 * @param pVM The VM handle.
889 */
890CPUMDECL(CPUMMODE) CPUMGetGuestMode(PVM pVM);
891
892
893#ifdef IN_RING3
894/** @defgroup grp_cpum_r3 The CPU Monitor(/Manager) API
895 * @ingroup grp_cpum
896 * @{
897 */
898
899/**
900 * Initializes the CPUM.
901 *
902 * @returns VBox status code.
903 * @param pVM The VM to operate on.
904 */
905CPUMR3DECL(int) CPUMR3Init(PVM pVM);
906
907/**
908 * Applies relocations to data and code managed by this
909 * component. This function will be called at init and
910 * whenever the VMM need to relocate it self inside the GC.
911 *
912 * The CPUM will update the addresses used by the switcher.
913 *
914 * @param pVM The VM.
915 */
916CPUMR3DECL(void) CPUMR3Relocate(PVM pVM);
917
918/**
919 * Terminates the CPUM.
920 *
921 * Termination means cleaning up and freeing all resources,
922 * the VM it self is at this point powered off or suspended.
923 *
924 * @returns VBox status code.
925 * @param pVM The VM to operate on.
926 */
927CPUMR3DECL(int) CPUMR3Term(PVM pVM);
928
929/**
930 * Resets the CPU.
931 *
932 * @param pVM The VM handle.
933 */
934CPUMR3DECL(void) CPUMR3Reset(PVM pVM);
935
936/**
937 * Queries the pointer to the internal CPUMCTX structure
938 *
939 * @returns VBox status code.
940 * @param pVM Handle to the virtual machine.
941 * @param ppCtx Receives the CPUMCTX GC pointer when successful.
942 */
943CPUMR3DECL(int) CPUMR3QueryGuestCtxGCPtr(PVM pVM, RCPTRTYPE(PCPUMCTX) *ppCtx);
944
945
946#ifdef DEBUG
947/**
948 * Debug helper - Saves guest context on raw mode entry (for fatal dump)
949 *
950 * @internal
951 */
952CPUMR3DECL(void) CPUMR3SaveEntryCtx(PVM pVM);
953#endif
954
955/**
956 * API for controlling a few of the CPU features found in CR4.
957 *
958 * Currently only X86_CR4_TSD is accepted as input.
959 *
960 * @returns VBox status code.
961 *
962 * @param pVM The VM handle.
963 * @param fOr The CR4 OR mask.
964 * @param fAnd The CR4 AND mask.
965 */
966CPUMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd);
967
968/** @} */
969#endif
970
971#ifdef IN_GC
972/** @defgroup grp_cpum_gc The CPU Monitor(/Manager) API
973 * @ingroup grp_cpum
974 * @{
975 */
976
977/**
978 * Calls a guest trap/interrupt handler directly
979 * Assumes a trap stack frame has already been setup on the guest's stack!
980 *
981 * @param pRegFrame Original trap/interrupt context
982 * @param selCS Code selector of handler
983 * @param pHandler GC virtual address of handler
984 * @param eflags Callee's EFLAGS
985 * @param selSS Stack selector for handler
986 * @param pEsp Stack address for handler
987 *
988 * This function does not return!
989 *
990 */
991DECLASM(void) CPUMGCCallGuestTrapHandler(PCPUMCTXCORE pRegFrame, uint32_t selCS, RTRCPTR pHandler, uint32_t eflags, uint32_t selSS, RTRCPTR pEsp);
992
993/**
994 * Performs an iret to V86 code
995 * Assumes a trap stack frame has already been setup on the guest's stack!
996 *
997 * @param pRegFrame Original trap/interrupt context
998 *
999 * This function does not return!
1000 */
1001CPUMGCDECL(void) CPUMGCCallV86Code(PCPUMCTXCORE pRegFrame);
1002
1003/** @} */
1004#endif
1005
1006#ifdef IN_RING0
1007/** @defgroup grp_cpum_r0 The CPU Monitor(/Manager) API
1008 * @ingroup grp_cpum
1009 * @{
1010 */
1011
1012/**
1013 * Does Ring-0 CPUM initialization.
1014 *
1015 * This is mainly to check that the Host CPU mode is compatible
1016 * with VBox.
1017 *
1018 * @returns VBox status code.
1019 * @param pVM The VM to operate on.
1020 */
1021CPUMR0DECL(int) CPUMR0Init(PVM pVM);
1022
1023/** @} */
1024#endif
1025
1026/** @} */
1027__END_DECLS
1028
1029
1030#endif
1031
1032
1033
1034
1035
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