VirtualBox

source: vbox/trunk/include/VBox/cpum.h@ 9841

Last change on this file since 9841 was 9841, checked in by vboxsync, 16 years ago

Added CPUMGetGuest/HyperRIP.
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File size: 29.8 KB
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1/** @file
2 * CPUM - CPU Monitor(/ Manager).
3 */
4
5/*
6 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * The contents of this file may alternatively be used under the terms
17 * of the Common Development and Distribution License Version 1.0
18 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19 * VirtualBox OSE distribution, in which case the provisions of the
20 * CDDL are applicable instead of those of the GPL.
21 *
22 * You may elect to license modified versions of this file under the
23 * terms and conditions of either the GPL or the CDDL or both.
24 *
25 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
26 * Clara, CA 95054 USA or visit http://www.sun.com if you need
27 * additional information or have any questions.
28 */
29
30#ifndef ___VBox_cpum_h
31#define ___VBox_cpum_h
32
33#include <VBox/cdefs.h>
34#include <VBox/types.h>
35#include <VBox/x86.h>
36
37
38__BEGIN_DECLS
39
40/** @defgroup grp_cpum The CPU Monitor(/Manager) API
41 * @{
42 */
43
44/**
45 * Selector hidden registers.
46 */
47typedef struct CPUMSELREGHID
48{
49 /** Base register.
50 *
51 * Long mode remarks:
52 * - Unused in long mode for CS, DS, ES, SS
53 * - 32 bits for FS & GS; FS(GS)_BASE msr used for the base address
54 * - 64 bits for TR & LDTR
55 */
56 uint64_t u64Base;
57 /** Limit (expanded). */
58 uint32_t u32Limit;
59 /** Flags.
60 * This is the high 32-bit word of the descriptor entry.
61 * Only the flags, dpl and type are used. */
62 X86DESCATTR Attr;
63} CPUMSELREGHID;
64
65
66/**
67 * The sysenter register set.
68 */
69typedef struct CPUMSYSENTER
70{
71 /** Ring 0 cs.
72 * This value + 8 is the Ring 0 ss.
73 * This value + 16 is the Ring 3 cs.
74 * This value + 24 is the Ring 3 ss.
75 */
76 uint64_t cs;
77 /** Ring 0 eip. */
78 uint64_t eip;
79 /** Ring 0 esp. */
80 uint64_t esp;
81} CPUMSYSENTER;
82
83
84/**
85 * CPU context core.
86 */
87#pragma pack(1)
88typedef struct CPUMCTXCORE
89{
90 union
91 {
92 uint32_t edi;
93 uint64_t rdi;
94 };
95 union
96 {
97 uint32_t esi;
98 uint64_t rsi;
99 };
100 union
101 {
102 uint32_t ebp;
103 uint64_t rbp;
104 };
105 union
106 {
107 uint32_t eax;
108 uint64_t rax;
109 };
110 union
111 {
112 uint32_t ebx;
113 uint64_t rbx;
114 };
115 union
116 {
117 uint32_t edx;
118 uint64_t rdx;
119 };
120 union
121 {
122 uint32_t ecx;
123 uint64_t rcx;
124 };
125 union
126 {
127 uint32_t esp;
128 uint64_t rsp;
129 };
130 /* Note: lss esp, [] in the switcher needs some space, so we reserve it here instead of relying on the exact esp & ss layout as before. */
131 uint32_t lss_esp;
132 RTSEL ss;
133 RTSEL ssPadding;
134
135 RTSEL gs;
136 RTSEL gsPadding;
137 RTSEL fs;
138 RTSEL fsPadding;
139 RTSEL es;
140 RTSEL esPadding;
141 RTSEL ds;
142 RTSEL dsPadding;
143 RTSEL cs;
144 RTSEL csPadding[3]; /* 3 words to force 8 byte alignment for the remainder */
145
146 union
147 {
148 X86EFLAGS eflags;
149 X86RFLAGS rflags;
150 };
151 union
152 {
153 uint32_t eip;
154 uint64_t rip;
155 };
156
157 uint64_t r8;
158 uint64_t r9;
159 uint64_t r10;
160 uint64_t r11;
161 uint64_t r12;
162 uint64_t r13;
163 uint64_t r14;
164 uint64_t r15;
165
166 /** Hidden selector registers.
167 * @{ */
168 CPUMSELREGHID esHid;
169 CPUMSELREGHID csHid;
170 CPUMSELREGHID ssHid;
171 CPUMSELREGHID dsHid;
172 CPUMSELREGHID fsHid;
173 CPUMSELREGHID gsHid;
174 /** @} */
175
176} CPUMCTXCORE;
177#pragma pack()
178
179
180/**
181 * CPU context.
182 */
183#pragma pack(1)
184typedef struct CPUMCTX
185{
186 /** FPU state. (16-byte alignment)
187 * @todo This doesn't have to be in X86FXSTATE on CPUs without fxsr - we need a type for the
188 * actual format or convert it (waste of time). */
189 X86FXSTATE fpu;
190
191 /** CPUMCTXCORE Part.
192 * @{ */
193 union
194 {
195 uint32_t edi;
196 uint64_t rdi;
197 };
198 union
199 {
200 uint32_t esi;
201 uint64_t rsi;
202 };
203 union
204 {
205 uint32_t ebp;
206 uint64_t rbp;
207 };
208 union
209 {
210 uint32_t eax;
211 uint64_t rax;
212 };
213 union
214 {
215 uint32_t ebx;
216 uint64_t rbx;
217 };
218 union
219 {
220 uint32_t edx;
221 uint64_t rdx;
222 };
223 union
224 {
225 uint32_t ecx;
226 uint64_t rcx;
227 };
228 union
229 {
230 uint32_t esp;
231 uint64_t rsp;
232 };
233 /* Note: lss esp, [] in the switcher needs some space, so we reserve it here instead of relying on the exact esp & ss layout as before (prevented us from using a union with rsp). */
234 uint32_t lss_esp;
235 RTSEL ss;
236 RTSEL ssPadding;
237
238 RTSEL gs;
239 RTSEL gsPadding;
240 RTSEL fs;
241 RTSEL fsPadding;
242 RTSEL es;
243 RTSEL esPadding;
244 RTSEL ds;
245 RTSEL dsPadding;
246 RTSEL cs;
247 RTSEL csPadding[3]; /* 3 words to force 8 byte alignment for the remainder */
248
249 union
250 {
251 X86EFLAGS eflags;
252 X86RFLAGS rflags;
253 };
254 union
255 {
256 uint32_t eip;
257 uint64_t rip;
258 };
259
260 uint64_t r8;
261 uint64_t r9;
262 uint64_t r10;
263 uint64_t r11;
264 uint64_t r12;
265 uint64_t r13;
266 uint64_t r14;
267 uint64_t r15;
268
269 /** Hidden selector registers.
270 * @{ */
271 CPUMSELREGHID esHid;
272 CPUMSELREGHID csHid;
273 CPUMSELREGHID ssHid;
274 CPUMSELREGHID dsHid;
275 CPUMSELREGHID fsHid;
276 CPUMSELREGHID gsHid;
277 /** @} */
278
279 /** @} */
280
281 /** Control registers.
282 * @{ */
283 uint64_t cr0;
284 uint64_t cr2;
285 uint64_t cr3;
286 uint64_t cr4;
287 uint64_t cr8;
288 /** @} */
289
290 /** Debug registers.
291 * @{ */
292 uint64_t dr0;
293 uint64_t dr1;
294 uint64_t dr2;
295 uint64_t dr3;
296 uint64_t dr4; /**< @todo remove dr4 and dr5. */
297 uint64_t dr5;
298 uint64_t dr6;
299 uint64_t dr7;
300 /* DR8-15 are currently not supported */
301 /** @} */
302
303 /** Global Descriptor Table register. */
304 VBOXGDTR gdtr;
305 uint16_t gdtrPadding;
306 /** Interrupt Descriptor Table register. */
307 VBOXIDTR idtr;
308 uint16_t idtrPadding;
309 /** The task register.
310 * Only the guest context uses all the members. */
311 RTSEL ldtr;
312 RTSEL ldtrPadding;
313 /** The task register.
314 * Only the guest context uses all the members. */
315 RTSEL tr;
316 RTSEL trPadding;
317
318 /** The sysenter msr registers.
319 * This member is not used by the hypervisor context. */
320 CPUMSYSENTER SysEnter;
321
322 /** System MSRs.
323 * @{ */
324 uint64_t msrEFER;
325 uint64_t msrSTAR; /* legacy syscall eip, cs & ss */
326 uint64_t msrPAT;
327 uint64_t msrLSTAR; /* 64 bits mode syscall rip */
328 uint64_t msrCSTAR; /* compatibility mode syscall rip */
329 uint64_t msrSFMASK; /* syscall flag mask */
330 uint64_t msrKERNELGSBASE;/* swapgs exchange value */
331 /** @} */
332
333 /** Hidden selector registers.
334 * @{ */
335 CPUMSELREGHID ldtrHid;
336 CPUMSELREGHID trHid;
337 /** @} */
338
339 /* padding to get 32byte aligned size */
340 uint32_t padding[6];
341} CPUMCTX;
342#pragma pack()
343
344/**
345 * Gets the CPUMCTXCORE part of a CPUMCTX.
346 */
347#define CPUMCTX2CORE(pCtx) ((PCPUMCTXCORE)(void *)&(pCtx)->edi)
348
349/**
350 * The register set returned by a CPUID operation.
351 */
352typedef struct CPUMCPUID
353{
354 uint32_t eax;
355 uint32_t ebx;
356 uint32_t ecx;
357 uint32_t edx;
358} CPUMCPUID;
359/** Pointer to a CPUID leaf. */
360typedef CPUMCPUID *PCPUMCPUID;
361/** Pointer to a const CPUID leaf. */
362typedef const CPUMCPUID *PCCPUMCPUID;
363
364/**
365 * CPUID feature to set or clear.
366 */
367typedef enum CPUMCPUIDFEATURE
368{
369 CPUMCPUIDFEATURE_INVALID = 0,
370 /** The APIC feature bit. (Std+Ext) */
371 CPUMCPUIDFEATURE_APIC,
372 /** The sysenter/sysexit feature bit. (Std) */
373 CPUMCPUIDFEATURE_SEP,
374 /** The SYSCALL/SYSEXIT feature bit (64 bits mode only for Intel CPUs). (Ext) */
375 CPUMCPUIDFEATURE_SYSCALL,
376 /** The PAE feature bit. (Std+Ext) */
377 CPUMCPUIDFEATURE_PAE,
378 /** The NXE feature bit. (Ext) */
379 CPUMCPUIDFEATURE_NXE,
380 /** The LAHF/SAHF feature bit (64 bits mode only). (Ext) */
381 CPUMCPUIDFEATURE_LAHF,
382 /** The LONG MODE feature bit. (Ext) */
383 CPUMCPUIDFEATURE_LONG_MODE
384} CPUMCPUIDFEATURE;
385
386/*
387 * CPU Vendor.
388 */
389typedef enum CPUMCPUVENDOR
390{
391 CPUMCPUVENDOR_INVALID = 0,
392 CPUMCPUVENDOR_INTEL,
393 CPUMCPUVENDOR_AMD,
394 CPUMCPUVENDOR_VIA,
395 CPUMCPUVENDOR_UNKNOWN,
396 /** 32bit hackishness. */
397 CPUMCPUVENDOR_32BIT_HACK = 0x7fffffff
398} CPUMCPUVENDOR;
399
400
401/** @name Guest Register Getters.
402 * @{ */
403CPUMDECL(void) CPUMGetGuestGDTR(PVM pVM, PVBOXGDTR pGDTR);
404CPUMDECL(uint32_t) CPUMGetGuestIDTR(PVM pVM, uint16_t *pcbLimit);
405CPUMDECL(RTSEL) CPUMGetGuestTR(PVM pVM);
406CPUMDECL(RTSEL) CPUMGetGuestLDTR(PVM pVM);
407CPUMDECL(uint64_t) CPUMGetGuestCR0(PVM pVM);
408CPUMDECL(uint64_t) CPUMGetGuestCR2(PVM pVM);
409CPUMDECL(uint64_t) CPUMGetGuestCR3(PVM pVM);
410CPUMDECL(uint64_t) CPUMGetGuestCR4(PVM pVM);
411CPUMDECL(int) CPUMGetGuestCRx(PVM pVM, unsigned iReg, uint64_t *pValue);
412CPUMDECL(uint32_t) CPUMGetGuestEFlags(PVM pVM);
413CPUMDECL(uint32_t) CPUMGetGuestEIP(PVM pVM);
414CPUMDECL(uint64_t) CPUMGetGuestRIP(PVM pVM);
415CPUMDECL(uint32_t) CPUMGetGuestEAX(PVM pVM);
416CPUMDECL(uint32_t) CPUMGetGuestEBX(PVM pVM);
417CPUMDECL(uint32_t) CPUMGetGuestECX(PVM pVM);
418CPUMDECL(uint32_t) CPUMGetGuestEDX(PVM pVM);
419CPUMDECL(uint32_t) CPUMGetGuestESI(PVM pVM);
420CPUMDECL(uint32_t) CPUMGetGuestEDI(PVM pVM);
421CPUMDECL(uint32_t) CPUMGetGuestESP(PVM pVM);
422CPUMDECL(uint32_t) CPUMGetGuestEBP(PVM pVM);
423CPUMDECL(RTSEL) CPUMGetGuestCS(PVM pVM);
424CPUMDECL(RTSEL) CPUMGetGuestDS(PVM pVM);
425CPUMDECL(RTSEL) CPUMGetGuestES(PVM pVM);
426CPUMDECL(RTSEL) CPUMGetGuestFS(PVM pVM);
427CPUMDECL(RTSEL) CPUMGetGuestGS(PVM pVM);
428CPUMDECL(RTSEL) CPUMGetGuestSS(PVM pVM);
429CPUMDECL(uint64_t) CPUMGetGuestDR0(PVM pVM);
430CPUMDECL(uint64_t) CPUMGetGuestDR1(PVM pVM);
431CPUMDECL(uint64_t) CPUMGetGuestDR2(PVM pVM);
432CPUMDECL(uint64_t) CPUMGetGuestDR3(PVM pVM);
433CPUMDECL(uint64_t) CPUMGetGuestDR6(PVM pVM);
434CPUMDECL(uint64_t) CPUMGetGuestDR7(PVM pVM);
435CPUMDECL(int) CPUMGetGuestDRx(PVM pVM, uint32_t iReg, uint64_t *pValue);
436CPUMDECL(void) CPUMGetGuestCpuId(PVM pVM, uint32_t iLeaf, uint32_t *pEax, uint32_t *pEbx, uint32_t *pEcx, uint32_t *pEdx);
437CPUMDECL(RCPTRTYPE(PCCPUMCPUID)) CPUMGetGuestCpuIdStdGCPtr(PVM pVM);
438CPUMDECL(RCPTRTYPE(PCCPUMCPUID)) CPUMGetGuestCpuIdExtGCPtr(PVM pVM);
439CPUMDECL(RCPTRTYPE(PCCPUMCPUID)) CPUMGetGuestCpuIdCentaurGCPtr(PVM pVM);
440CPUMDECL(RCPTRTYPE(PCCPUMCPUID)) CPUMGetGuestCpuIdDefGCPtr(PVM pVM);
441CPUMDECL(uint32_t) CPUMGetGuestCpuIdStdMax(PVM pVM);
442CPUMDECL(uint32_t) CPUMGetGuestCpuIdExtMax(PVM pVM);
443CPUMDECL(uint32_t) CPUMGetGuestCpuIdCentaurMax(PVM pVM);
444CPUMDECL(CPUMSELREGHID *) CPUMGetGuestTRHid(PVM pVM);
445CPUMDECL(uint64_t) CPUMGetGuestEFER(PVM pVM);
446/** @} */
447
448/** @name Guest Register Setters.
449 * @{ */
450CPUMDECL(int) CPUMSetGuestGDTR(PVM pVM, uint32_t addr, uint16_t limit);
451CPUMDECL(int) CPUMSetGuestIDTR(PVM pVM, uint32_t addr, uint16_t limit);
452CPUMDECL(int) CPUMSetGuestTR(PVM pVM, uint16_t tr);
453CPUMDECL(int) CPUMSetGuestLDTR(PVM pVM, uint16_t ldtr);
454CPUMDECL(int) CPUMSetGuestCR0(PVM pVM, uint64_t cr0);
455CPUMDECL(int) CPUMSetGuestCR2(PVM pVM, uint64_t cr2);
456CPUMDECL(int) CPUMSetGuestCR3(PVM pVM, uint64_t cr3);
457CPUMDECL(int) CPUMSetGuestCR4(PVM pVM, uint64_t cr4);
458CPUMDECL(int) CPUMSetGuestDR0(PVM pVM, uint64_t uDr0);
459CPUMDECL(int) CPUMSetGuestDR1(PVM pVM, uint64_t uDr1);
460CPUMDECL(int) CPUMSetGuestDR2(PVM pVM, uint64_t uDr2);
461CPUMDECL(int) CPUMSetGuestDR3(PVM pVM, uint64_t uDr3);
462CPUMDECL(int) CPUMSetGuestDR6(PVM pVM, uint64_t uDr6);
463CPUMDECL(int) CPUMSetGuestDR7(PVM pVM, uint64_t uDr7);
464CPUMDECL(int) CPUMSetGuestDRx(PVM pVM, uint32_t iReg, uint64_t Value);
465CPUMDECL(int) CPUMSetGuestEFlags(PVM pVM, uint32_t eflags);
466CPUMDECL(int) CPUMSetGuestEIP(PVM pVM, uint32_t eip);
467CPUMDECL(int) CPUMSetGuestEAX(PVM pVM, uint32_t eax);
468CPUMDECL(int) CPUMSetGuestEBX(PVM pVM, uint32_t ebx);
469CPUMDECL(int) CPUMSetGuestECX(PVM pVM, uint32_t ecx);
470CPUMDECL(int) CPUMSetGuestEDX(PVM pVM, uint32_t edx);
471CPUMDECL(int) CPUMSetGuestESI(PVM pVM, uint32_t esi);
472CPUMDECL(int) CPUMSetGuestEDI(PVM pVM, uint32_t edi);
473CPUMDECL(int) CPUMSetGuestESP(PVM pVM, uint32_t esp);
474CPUMDECL(int) CPUMSetGuestEBP(PVM pVM, uint32_t ebp);
475CPUMDECL(int) CPUMSetGuestCS(PVM pVM, uint16_t cs);
476CPUMDECL(int) CPUMSetGuestDS(PVM pVM, uint16_t ds);
477CPUMDECL(int) CPUMSetGuestES(PVM pVM, uint16_t es);
478CPUMDECL(int) CPUMSetGuestFS(PVM pVM, uint16_t fs);
479CPUMDECL(int) CPUMSetGuestGS(PVM pVM, uint16_t gs);
480CPUMDECL(int) CPUMSetGuestSS(PVM pVM, uint16_t ss);
481CPUMDECL(void) CPUMSetGuestEFER(PVM pVM, uint64_t val);
482CPUMDECL(void) CPUMSetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature);
483CPUMDECL(void) CPUMClearGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature);
484CPUMDECL(bool) CPUMGetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature);
485CPUMDECL(void) CPUMSetGuestCtx(PVM pVM, const PCPUMCTX pCtx);
486/** @} */
487
488/** @name Misc Guest Predicate Functions.
489 * @{ */
490
491/**
492 * Tests if the guest is running in real mode or not.
493 *
494 * @returns true if in real mode, otherwise false.
495 * @param pVM The VM handle.
496 */
497DECLINLINE(bool) CPUMIsGuestInRealMode(PVM pVM)
498{
499 return !(CPUMGetGuestCR0(pVM) & X86_CR0_PE);
500}
501
502/**
503 * Tests if the guest is running in protected or not.
504 *
505 * @returns true if in protected mode, otherwise false.
506 * @param pVM The VM handle.
507 */
508DECLINLINE(bool) CPUMIsGuestInProtectedMode(PVM pVM)
509{
510 return !!(CPUMGetGuestCR0(pVM) & X86_CR0_PE);
511}
512
513/**
514 * Tests if the guest is running in paged protected or not.
515 *
516 * @returns true if in paged protected mode, otherwise false.
517 * @param pVM The VM handle.
518 */
519DECLINLINE(bool) CPUMIsGuestInPagedProtectedMode(PVM pVM)
520{
521 return (CPUMGetGuestCR0(pVM) & (X86_CR0_PE | X86_CR0_PG)) == (X86_CR0_PE | X86_CR0_PG);
522}
523
524/**
525 * Tests if the guest is running in long mode or not.
526 *
527 * @returns true if in long mode, otherwise false.
528 * @param pVM The VM handle.
529 */
530DECLINLINE(bool) CPUMIsGuestInLongMode(PVM pVM)
531{
532 return (CPUMGetGuestEFER(pVM) & MSR_K6_EFER_LMA) == MSR_K6_EFER_LMA;
533}
534
535/**
536 * Tests if the guest is running in 16 bits paged protected or not.
537 *
538 * @returns true if in paged protected mode, otherwise false.
539 * @param pVM The VM handle.
540 */
541CPUMDECL(bool) CPUMIsGuestIn16BitCode(PVM pVM);
542
543/**
544 * Tests if the guest is running in 32 bits paged protected or not.
545 *
546 * @returns true if in paged protected mode, otherwise false.
547 * @param pVM The VM handle.
548 */
549CPUMDECL(bool) CPUMIsGuestIn32BitCode(PVM pVM);
550
551/**
552 * Tests if the guest is running in 64 bits mode or not.
553 *
554 * @returns true if in 64 bits protected mode, otherwise false.
555 * @param pVM The VM handle.
556 * @param pCtx Current CPU context
557 */
558DECLINLINE(bool) CPUMIsGuestIn64BitCode(PVM pVM, PCCPUMCTXCORE pCtx)
559{
560 if (!CPUMIsGuestInLongMode(pVM))
561 return false;
562
563 return pCtx->csHid.Attr.n.u1Long;
564}
565
566/**
567 * Tests if the guest is running in 64 bits mode or not.
568 *
569 * @returns true if in 64 bits protected mode, otherwise false.
570 * @param pVM The VM handle.
571 * @param pCtx Current CPU context
572 */
573DECLINLINE(bool) CPUMIsGuestIn64BitCodeEx(PCCPUMCTX pCtx)
574{
575 if (!(pCtx->msrEFER & MSR_K6_EFER_LMA))
576 return false;
577
578 return pCtx->csHid.Attr.n.u1Long;
579}
580
581/**
582 * Gets the CPU vendor
583 *
584 * @returns CPU vendor
585 * @param pVM The VM handle.
586 */
587CPUMDECL(CPUMCPUVENDOR) CPUMGetCPUVendor(PVM pVM);
588
589
590/** @} */
591
592
593
594/** @name Hypervisor Register Getters.
595 * @{ */
596CPUMDECL(RTSEL) CPUMGetHyperCS(PVM pVM);
597CPUMDECL(RTSEL) CPUMGetHyperDS(PVM pVM);
598CPUMDECL(RTSEL) CPUMGetHyperES(PVM pVM);
599CPUMDECL(RTSEL) CPUMGetHyperFS(PVM pVM);
600CPUMDECL(RTSEL) CPUMGetHyperGS(PVM pVM);
601CPUMDECL(RTSEL) CPUMGetHyperSS(PVM pVM);
602#if 0 /* these are not correct. */
603CPUMDECL(uint32_t) CPUMGetHyperCR0(PVM pVM);
604CPUMDECL(uint32_t) CPUMGetHyperCR2(PVM pVM);
605CPUMDECL(uint32_t) CPUMGetHyperCR3(PVM pVM);
606CPUMDECL(uint32_t) CPUMGetHyperCR4(PVM pVM);
607#endif
608/** This register is only saved on fatal traps. */
609CPUMDECL(uint32_t) CPUMGetHyperEAX(PVM pVM);
610CPUMDECL(uint32_t) CPUMGetHyperEBX(PVM pVM);
611/** This register is only saved on fatal traps. */
612CPUMDECL(uint32_t) CPUMGetHyperECX(PVM pVM);
613/** This register is only saved on fatal traps. */
614CPUMDECL(uint32_t) CPUMGetHyperEDX(PVM pVM);
615CPUMDECL(uint32_t) CPUMGetHyperESI(PVM pVM);
616CPUMDECL(uint32_t) CPUMGetHyperEDI(PVM pVM);
617CPUMDECL(uint32_t) CPUMGetHyperEBP(PVM pVM);
618CPUMDECL(uint32_t) CPUMGetHyperESP(PVM pVM);
619CPUMDECL(uint32_t) CPUMGetHyperEFlags(PVM pVM);
620CPUMDECL(uint32_t) CPUMGetHyperEIP(PVM pVM);
621CPUMDECL(uint64_t) CPUMGetHyperRIP(PVM pVM);
622CPUMDECL(uint32_t) CPUMGetHyperIDTR(PVM pVM, uint16_t *pcbLimit);
623CPUMDECL(uint32_t) CPUMGetHyperGDTR(PVM pVM, uint16_t *pcbLimit);
624CPUMDECL(RTSEL) CPUMGetHyperLDTR(PVM pVM);
625CPUMDECL(RTGCUINTREG) CPUMGetHyperDR0(PVM pVM);
626CPUMDECL(RTGCUINTREG) CPUMGetHyperDR1(PVM pVM);
627CPUMDECL(RTGCUINTREG) CPUMGetHyperDR2(PVM pVM);
628CPUMDECL(RTGCUINTREG) CPUMGetHyperDR3(PVM pVM);
629CPUMDECL(RTGCUINTREG) CPUMGetHyperDR6(PVM pVM);
630CPUMDECL(RTGCUINTREG) CPUMGetHyperDR7(PVM pVM);
631CPUMDECL(void) CPUMGetHyperCtx(PVM pVM, PCPUMCTX pCtx);
632/** @} */
633
634/** @name Hypervisor Register Setters.
635 * @{ */
636CPUMDECL(void) CPUMSetHyperGDTR(PVM pVM, uint32_t addr, uint16_t limit);
637CPUMDECL(void) CPUMSetHyperLDTR(PVM pVM, RTSEL SelLDTR);
638CPUMDECL(void) CPUMSetHyperIDTR(PVM pVM, uint32_t addr, uint16_t limit);
639CPUMDECL(void) CPUMSetHyperCR3(PVM pVM, uint32_t cr3);
640CPUMDECL(void) CPUMSetHyperTR(PVM pVM, RTSEL SelTR);
641CPUMDECL(void) CPUMSetHyperCS(PVM pVM, RTSEL SelCS);
642CPUMDECL(void) CPUMSetHyperDS(PVM pVM, RTSEL SelDS);
643CPUMDECL(void) CPUMSetHyperES(PVM pVM, RTSEL SelDS);
644CPUMDECL(void) CPUMSetHyperFS(PVM pVM, RTSEL SelDS);
645CPUMDECL(void) CPUMSetHyperGS(PVM pVM, RTSEL SelDS);
646CPUMDECL(void) CPUMSetHyperSS(PVM pVM, RTSEL SelSS);
647CPUMDECL(void) CPUMSetHyperESP(PVM pVM, uint32_t u32ESP);
648CPUMDECL(int) CPUMSetHyperEFlags(PVM pVM, uint32_t Efl);
649CPUMDECL(void) CPUMSetHyperEIP(PVM pVM, uint32_t u32EIP);
650CPUMDECL(void) CPUMSetHyperDR0(PVM pVM, RTGCUINTREG uDr0);
651CPUMDECL(void) CPUMSetHyperDR1(PVM pVM, RTGCUINTREG uDr1);
652CPUMDECL(void) CPUMSetHyperDR2(PVM pVM, RTGCUINTREG uDr2);
653CPUMDECL(void) CPUMSetHyperDR3(PVM pVM, RTGCUINTREG uDr3);
654CPUMDECL(void) CPUMSetHyperDR6(PVM pVM, RTGCUINTREG uDr6);
655CPUMDECL(void) CPUMSetHyperDR7(PVM pVM, RTGCUINTREG uDr7);
656CPUMDECL(void) CPUMSetHyperCtx(PVM pVM, const PCPUMCTX pCtx);
657CPUMDECL(int) CPUMRecalcHyperDRx(PVM pVM);
658/** @} */
659
660CPUMDECL(void) CPUMPushHyper(PVM pVM, uint32_t u32);
661
662/**
663 * Sets or resets an alternative hypervisor context core.
664 *
665 * This is called when we get a hypervisor trap set switch the context
666 * core with the trap frame on the stack. It is called again to reset
667 * back to the default context core when resuming hypervisor execution.
668 *
669 * @param pVM The VM handle.
670 * @param pCtxCore Pointer to the alternative context core or NULL
671 * to go back to the default context core.
672 */
673CPUMDECL(void) CPUMHyperSetCtxCore(PVM pVM, PCPUMCTXCORE pCtxCore);
674
675
676/**
677 * Queries the pointer to the internal CPUMCTX structure
678 *
679 * @returns VBox status code.
680 * @param pVM Handle to the virtual machine.
681 * @param ppCtx Receives the CPUMCTX pointer when successful.
682 */
683CPUMDECL(int) CPUMQueryGuestCtxPtr(PVM pVM, PCPUMCTX *ppCtx);
684
685/**
686 * Queries the pointer to the internal CPUMCTX structure for the hypervisor.
687 *
688 * @returns VBox status code.
689 * @param pVM Handle to the virtual machine.
690 * @param ppCtx Receives the hyper CPUMCTX pointer when successful.
691 */
692CPUMDECL(int) CPUMQueryHyperCtxPtr(PVM pVM, PCPUMCTX *ppCtx);
693
694
695/**
696 * Gets the pointer to the internal CPUMCTXCORE structure.
697 * This is only for reading in order to save a few calls.
698 *
699 * @param pVM Handle to the virtual machine.
700 */
701CPUMDECL(PCCPUMCTXCORE) CPUMGetGuestCtxCore(PVM pVM);
702
703/**
704 * Gets the pointer to the internal CPUMCTXCORE structure for the hypervisor.
705 * This is only for reading in order to save a few calls.
706 *
707 * @param pVM Handle to the virtual machine.
708 */
709CPUMDECL(PCCPUMCTXCORE) CPUMGetHyperCtxCore(PVM pVM);
710
711/**
712 * Sets the guest context core registers.
713 *
714 * @param pVM Handle to the virtual machine.
715 * @param pCtxCore The new context core values.
716 */
717CPUMDECL(void) CPUMSetGuestCtxCore(PVM pVM, PCCPUMCTXCORE pCtxCore);
718
719
720/**
721 * Transforms the guest CPU state to raw-ring mode.
722 *
723 * This function will change the any of the cs and ss register with DPL=0 to DPL=1.
724 *
725 * @returns VBox status. (recompiler failure)
726 * @param pVM VM handle.
727 * @param pCtxCore The context core (for trap usage).
728 * @see @ref pg_raw
729 */
730CPUMDECL(int) CPUMRawEnter(PVM pVM, PCPUMCTXCORE pCtxCore);
731
732/**
733 * Transforms the guest CPU state from raw-ring mode to correct values.
734 *
735 * This function will change any selector registers with DPL=1 to DPL=0.
736 *
737 * @returns Adjusted rc.
738 * @param pVM VM handle.
739 * @param rc Raw mode return code
740 * @param pCtxCore The context core (for trap usage).
741 * @see @ref pg_raw
742 */
743CPUMDECL(int) CPUMRawLeave(PVM pVM, PCPUMCTXCORE pCtxCore, int rc);
744
745/**
746 * Gets the EFLAGS while we're in raw-mode.
747 *
748 * @returns The eflags.
749 * @param pVM The VM handle.
750 * @param pCtxCore The context core.
751 */
752CPUMDECL(uint32_t) CPUMRawGetEFlags(PVM pVM, PCPUMCTXCORE pCtxCore);
753
754/**
755 * Updates the EFLAGS while we're in raw-mode.
756 *
757 * @param pVM The VM handle.
758 * @param pCtxCore The context core.
759 * @param eflags The new EFLAGS value.
760 */
761CPUMDECL(void) CPUMRawSetEFlags(PVM pVM, PCPUMCTXCORE pCtxCore, uint32_t eflags);
762
763/**
764 * Lazily sync in the FPU/XMM state
765 *
766 * This function will change any selector registers with DPL=1 to DPL=0.
767 *
768 * @returns VBox status code.
769 * @param pVM VM handle.
770 */
771CPUMDECL(int) CPUMHandleLazyFPU(PVM pVM);
772
773
774/**
775 * Restore host FPU/XMM state
776 *
777 * @returns VBox status code.
778 * @param pVM VM handle.
779 */
780CPUMDECL(int) CPUMRestoreHostFPUState(PVM pVM);
781
782/** @name Changed flags
783 * These flags are used to keep track of which important register that
784 * have been changed since last they were reset. The only one allowed
785 * to clear them is REM!
786 * @{
787 */
788#define CPUM_CHANGED_FPU_REM RT_BIT(0)
789#define CPUM_CHANGED_CR0 RT_BIT(1)
790#define CPUM_CHANGED_CR4 RT_BIT(2)
791#define CPUM_CHANGED_GLOBAL_TLB_FLUSH RT_BIT(3)
792#define CPUM_CHANGED_CR3 RT_BIT(4)
793#define CPUM_CHANGED_GDTR RT_BIT(5)
794#define CPUM_CHANGED_IDTR RT_BIT(6)
795#define CPUM_CHANGED_LDTR RT_BIT(7)
796#define CPUM_CHANGED_TR RT_BIT(8)
797#define CPUM_CHANGED_SYSENTER_MSR RT_BIT(9)
798#define CPUM_CHANGED_HIDDEN_SEL_REGS RT_BIT(10)
799#define CPUM_CHANGED_CPUID RT_BIT(11)
800/** @} */
801
802/**
803 * Gets and resets the changed flags (CPUM_CHANGED_*).
804 *
805 * @returns The changed flags.
806 * @param pVM VM handle.
807 */
808CPUMDECL(unsigned) CPUMGetAndClearChangedFlagsREM(PVM pVM);
809
810/**
811 * Sets the specified changed flags (CPUM_CHANGED_*).
812 *
813 * @param pVM The VM handle.
814 */
815CPUMDECL(void) CPUMSetChangedFlags(PVM pVM, uint32_t fChangedFlags);
816
817/**
818 * Checks if the CPU supports the FXSAVE and FXRSTOR instruction.
819 * @returns true if supported.
820 * @returns false if not supported.
821 * @param pVM The VM handle.
822 */
823CPUMDECL(bool) CPUMSupportsFXSR(PVM pVM);
824
825/**
826 * Checks if the host OS uses the SYSENTER / SYSEXIT instructions.
827 * @returns true if used.
828 * @returns false if not used.
829 * @param pVM The VM handle.
830 */
831CPUMDECL(bool) CPUMIsHostUsingSysEnter(PVM pVM);
832
833/**
834 * Checks if the host OS uses the SYSCALL / SYSRET instructions.
835 * @returns true if used.
836 * @returns false if not used.
837 * @param pVM The VM handle.
838 */
839CPUMDECL(bool) CPUMIsHostUsingSysCall(PVM pVM);
840
841/**
842 * Checks if we activated the FPU/XMM state of the guest OS
843 * @returns true if we did.
844 * @returns false if not.
845 * @param pVM The VM handle.
846 */
847CPUMDECL(bool) CPUMIsGuestFPUStateActive(PVM pVM);
848
849/**
850 * Deactivate the FPU/XMM state of the guest OS
851 * @param pVM The VM handle.
852 */
853CPUMDECL(void) CPUMDeactivateGuestFPUState(PVM pVM);
854
855
856/**
857 * Checks if the hidden selector registers are valid
858 * @returns true if they are.
859 * @returns false if not.
860 * @param pVM The VM handle.
861 */
862CPUMDECL(bool) CPUMAreHiddenSelRegsValid(PVM pVM);
863
864/**
865 * Checks if the hidden selector registers are valid
866 * @param pVM The VM handle.
867 * @param fValid Valid or not
868 */
869CPUMDECL(void) CPUMSetHiddenSelRegsValid(PVM pVM, bool fValid);
870
871/**
872 * Get the current privilege level of the guest.
873 *
874 * @returns cpl
875 * @param pVM VM Handle.
876 * @param pRegFrame Trap register frame.
877 */
878CPUMDECL(uint32_t) CPUMGetGuestCPL(PVM pVM, PCPUMCTXCORE pCtxCore);
879
880/**
881 * CPU modes.
882 */
883typedef enum CPUMMODE
884{
885 /** The usual invalid zero entry. */
886 CPUMMODE_INVALID = 0,
887 /** Real mode. */
888 CPUMMODE_REAL,
889 /** Protected mode (32-bit). */
890 CPUMMODE_PROTECTED,
891 /** Long mode (64-bit). */
892 CPUMMODE_LONG
893} CPUMMODE;
894
895/**
896 * Gets the current guest CPU mode.
897 *
898 * If paging mode is what you need, check out PGMGetGuestMode().
899 *
900 * @returns The CPU mode.
901 * @param pVM The VM handle.
902 */
903CPUMDECL(CPUMMODE) CPUMGetGuestMode(PVM pVM);
904
905
906#ifdef IN_RING3
907/** @defgroup grp_cpum_r3 The CPU Monitor(/Manager) API
908 * @ingroup grp_cpum
909 * @{
910 */
911
912/**
913 * Initializes the CPUM.
914 *
915 * @returns VBox status code.
916 * @param pVM The VM to operate on.
917 */
918CPUMR3DECL(int) CPUMR3Init(PVM pVM);
919
920/**
921 * Applies relocations to data and code managed by this
922 * component. This function will be called at init and
923 * whenever the VMM need to relocate it self inside the GC.
924 *
925 * The CPUM will update the addresses used by the switcher.
926 *
927 * @param pVM The VM.
928 */
929CPUMR3DECL(void) CPUMR3Relocate(PVM pVM);
930
931/**
932 * Terminates the CPUM.
933 *
934 * Termination means cleaning up and freeing all resources,
935 * the VM it self is at this point powered off or suspended.
936 *
937 * @returns VBox status code.
938 * @param pVM The VM to operate on.
939 */
940CPUMR3DECL(int) CPUMR3Term(PVM pVM);
941
942/**
943 * Resets the CPU.
944 *
945 * @param pVM The VM handle.
946 */
947CPUMR3DECL(void) CPUMR3Reset(PVM pVM);
948
949/**
950 * Queries the pointer to the internal CPUMCTX structure
951 *
952 * @returns VBox status code.
953 * @param pVM Handle to the virtual machine.
954 * @param ppCtx Receives the CPUMCTX GC pointer when successful.
955 */
956CPUMR3DECL(int) CPUMR3QueryGuestCtxGCPtr(PVM pVM, RCPTRTYPE(PCPUMCTX) *ppCtx);
957
958
959#ifdef DEBUG
960/**
961 * Debug helper - Saves guest context on raw mode entry (for fatal dump)
962 *
963 * @internal
964 */
965CPUMR3DECL(void) CPUMR3SaveEntryCtx(PVM pVM);
966#endif
967
968/**
969 * API for controlling a few of the CPU features found in CR4.
970 *
971 * Currently only X86_CR4_TSD is accepted as input.
972 *
973 * @returns VBox status code.
974 *
975 * @param pVM The VM handle.
976 * @param fOr The CR4 OR mask.
977 * @param fAnd The CR4 AND mask.
978 */
979CPUMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd);
980
981/** @} */
982#endif
983
984#ifdef IN_GC
985/** @defgroup grp_cpum_gc The CPU Monitor(/Manager) API
986 * @ingroup grp_cpum
987 * @{
988 */
989
990/**
991 * Calls a guest trap/interrupt handler directly
992 * Assumes a trap stack frame has already been setup on the guest's stack!
993 *
994 * @param pRegFrame Original trap/interrupt context
995 * @param selCS Code selector of handler
996 * @param pHandler GC virtual address of handler
997 * @param eflags Callee's EFLAGS
998 * @param selSS Stack selector for handler
999 * @param pEsp Stack address for handler
1000 *
1001 * This function does not return!
1002 *
1003 */
1004DECLASM(void) CPUMGCCallGuestTrapHandler(PCPUMCTXCORE pRegFrame, uint32_t selCS, RTRCPTR pHandler, uint32_t eflags, uint32_t selSS, RTRCPTR pEsp);
1005
1006/**
1007 * Performs an iret to V86 code
1008 * Assumes a trap stack frame has already been setup on the guest's stack!
1009 *
1010 * @param pRegFrame Original trap/interrupt context
1011 *
1012 * This function does not return!
1013 */
1014CPUMGCDECL(void) CPUMGCCallV86Code(PCPUMCTXCORE pRegFrame);
1015
1016/** @} */
1017#endif
1018
1019#ifdef IN_RING0
1020/** @defgroup grp_cpum_r0 The CPU Monitor(/Manager) API
1021 * @ingroup grp_cpum
1022 * @{
1023 */
1024
1025/**
1026 * Does Ring-0 CPUM initialization.
1027 *
1028 * This is mainly to check that the Host CPU mode is compatible
1029 * with VBox.
1030 *
1031 * @returns VBox status code.
1032 * @param pVM The VM to operate on.
1033 */
1034CPUMR0DECL(int) CPUMR0Init(PVM pVM);
1035
1036/** @} */
1037#endif
1038
1039/** @} */
1040__END_DECLS
1041
1042
1043#endif
1044
1045
1046
1047
1048
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