VirtualBox

source: vbox/trunk/include/VBox/cpumctx.h@ 34801

Last change on this file since 34801 was 33540, checked in by vboxsync, 14 years ago

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1/** @file
2 * CPUM - CPU Monitor(/ Manager), Context Structures. (VMM)
3 */
4
5/*
6 * Copyright (C) 2006-2010 Oracle Corporation
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * The contents of this file may alternatively be used under the terms
17 * of the Common Development and Distribution License Version 1.0
18 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19 * VirtualBox OSE distribution, in which case the provisions of the
20 * CDDL are applicable instead of those of the GPL.
21 *
22 * You may elect to license modified versions of this file under the
23 * terms and conditions of either the GPL or the CDDL or both.
24 */
25
26#ifndef ___VBox_cpumctx_h
27#define ___VBox_cpumctx_h
28
29#include <VBox/cdefs.h>
30#include <VBox/types.h>
31#include <VBox/x86.h>
32
33
34RT_C_DECLS_BEGIN
35
36/** @addgroup grp_cpum_ctx The CPUM Context Structures
37 * @ingroup grp_cpum
38 * @{
39 */
40
41/**
42 * Selector hidden registers.
43 */
44typedef struct CPUMSELREGHID
45{
46 /** Base register.
47 *
48 * Long mode remarks:
49 * - Unused in long mode for CS, DS, ES, SS
50 * - 32 bits for FS & GS; FS(GS)_BASE msr used for the base address
51 * - 64 bits for TR & LDTR
52 */
53 uint64_t u64Base;
54 /** Limit (expanded). */
55 uint32_t u32Limit;
56 /** Flags.
57 * This is the high 32-bit word of the descriptor entry.
58 * Only the flags, dpl and type are used. */
59 X86DESCATTR Attr;
60} CPUMSELREGHID;
61
62
63/**
64 * The sysenter register set.
65 */
66typedef struct CPUMSYSENTER
67{
68 /** Ring 0 cs.
69 * This value + 8 is the Ring 0 ss.
70 * This value + 16 is the Ring 3 cs.
71 * This value + 24 is the Ring 3 ss.
72 */
73 uint64_t cs;
74 /** Ring 0 eip. */
75 uint64_t eip;
76 /** Ring 0 esp. */
77 uint64_t esp;
78} CPUMSYSENTER;
79
80
81/**
82 * CPU context core.
83 */
84#ifndef VBOX_WITHOUT_UNNAMED_UNIONS
85#pragma pack(1)
86typedef struct CPUMCTXCORE
87{
88 union
89 {
90 uint16_t di;
91 uint32_t edi;
92 uint64_t rdi;
93 };
94 union
95 {
96 uint16_t si;
97 uint32_t esi;
98 uint64_t rsi;
99 };
100 union
101 {
102 uint16_t bp;
103 uint32_t ebp;
104 uint64_t rbp;
105 };
106 union
107 {
108 uint16_t ax;
109 uint32_t eax;
110 uint64_t rax;
111 };
112 union
113 {
114 uint16_t bx;
115 uint32_t ebx;
116 uint64_t rbx;
117 };
118 union
119 {
120 uint16_t dx;
121 uint32_t edx;
122 uint64_t rdx;
123 };
124 union
125 {
126 uint16_t cx;
127 uint32_t ecx;
128 uint64_t rcx;
129 };
130 union
131 {
132 uint16_t sp;
133 uint32_t esp;
134 uint64_t rsp;
135 };
136 /* Note: lss esp, [] in the switcher needs some space, so we reserve it here instead of relying on the exact esp & ss layout as before. */
137 uint32_t lss_esp;
138 RTSEL ss;
139 RTSEL ssPadding;
140
141 RTSEL gs;
142 RTSEL gsPadding;
143 RTSEL fs;
144 RTSEL fsPadding;
145 RTSEL es;
146 RTSEL esPadding;
147 RTSEL ds;
148 RTSEL dsPadding;
149 RTSEL cs;
150 RTSEL csPadding[3]; /* 3 words to force 8 byte alignment for the remainder */
151
152 union
153 {
154 X86EFLAGS eflags;
155 X86RFLAGS rflags;
156 };
157 union
158 {
159 uint16_t ip;
160 uint32_t eip;
161 uint64_t rip;
162 };
163
164 uint64_t r8;
165 uint64_t r9;
166 uint64_t r10;
167 uint64_t r11;
168 uint64_t r12;
169 uint64_t r13;
170 uint64_t r14;
171 uint64_t r15;
172
173 /** Hidden selector registers.
174 * @{ */
175 CPUMSELREGHID esHid;
176 CPUMSELREGHID csHid;
177 CPUMSELREGHID ssHid;
178 CPUMSELREGHID dsHid;
179 CPUMSELREGHID fsHid;
180 CPUMSELREGHID gsHid;
181 /** @} */
182
183} CPUMCTXCORE;
184#pragma pack()
185#else /* VBOX_WITHOUT_UNNAMED_UNIONS */
186typedef struct CPUMCTXCORE CPUMCTXCORE;
187#endif /* VBOX_WITHOUT_UNNAMED_UNIONS */
188
189
190/**
191 * CPU context.
192 */
193#ifndef VBOX_WITHOUT_UNNAMED_UNIONS
194# pragma pack(1)
195typedef struct CPUMCTX
196{
197 /** FPU state. (16-byte alignment)
198 * @todo This doesn't have to be in X86FXSTATE on CPUs without fxsr - we need a type for the
199 * actual format or convert it (waste of time). */
200 X86FXSTATE fpu;
201
202 /** CPUMCTXCORE Part.
203 * @{ */
204 union
205 {
206 uint16_t di;
207 uint32_t edi;
208 uint64_t rdi;
209 };
210 union
211 {
212 uint16_t si;
213 uint32_t esi;
214 uint64_t rsi;
215 };
216 union
217 {
218 uint16_t bp;
219 uint32_t ebp;
220 uint64_t rbp;
221 };
222 union
223 {
224 uint16_t ax;
225 uint32_t eax;
226 uint64_t rax;
227 };
228 union
229 {
230 uint16_t bx;
231 uint32_t ebx;
232 uint64_t rbx;
233 };
234 union
235 {
236 uint16_t dx;
237 uint32_t edx;
238 uint64_t rdx;
239 };
240 union
241 {
242 uint16_t cx;
243 uint32_t ecx;
244 uint64_t rcx;
245 };
246 union
247 {
248 uint16_t sp;
249 uint32_t esp;
250 uint64_t rsp;
251 };
252 /** @note lss esp, [] in the switcher needs some space, so we reserve it here
253 * instead of relying on the exact esp & ss layout as before (prevented
254 * us from using a union with rsp). */
255 uint32_t lss_esp;
256 RTSEL ss;
257 RTSEL ssPadding;
258
259 RTSEL gs;
260 RTSEL gsPadding;
261 RTSEL fs;
262 RTSEL fsPadding;
263 RTSEL es;
264 RTSEL esPadding;
265 RTSEL ds;
266 RTSEL dsPadding;
267 RTSEL cs;
268 RTSEL csPadding[3]; /* 3 words to force 8 byte alignment for the remainder */
269
270 union
271 {
272 X86EFLAGS eflags;
273 X86RFLAGS rflags;
274 };
275 union
276 {
277 uint16_t ip;
278 uint32_t eip;
279 uint64_t rip;
280 };
281
282 uint64_t r8;
283 uint64_t r9;
284 uint64_t r10;
285 uint64_t r11;
286 uint64_t r12;
287 uint64_t r13;
288 uint64_t r14;
289 uint64_t r15;
290
291 /** Hidden selector registers.
292 * @{ */
293 CPUMSELREGHID esHid;
294 CPUMSELREGHID csHid;
295 CPUMSELREGHID ssHid;
296 CPUMSELREGHID dsHid;
297 CPUMSELREGHID fsHid;
298 CPUMSELREGHID gsHid;
299 /** @} */
300
301 /** @} */
302
303 /** Control registers.
304 * @{ */
305 uint64_t cr0;
306 uint64_t cr2;
307 uint64_t cr3;
308 uint64_t cr4;
309 /** @} */
310
311 /** Debug registers.
312 * @remarks DR4 and DR5 should not be used since they are aliases for
313 * DR6 and DR7 respectively on both AMD and Intel CPUs.
314 * @remarks DR8-15 are currently not supported by AMD or Intel, so
315 * neither do we.
316 * @{ */
317 uint64_t dr[8];
318 /** @} */
319
320 /** Global Descriptor Table register. */
321 VBOXGDTR gdtr;
322 uint16_t gdtrPadding;
323 /** Interrupt Descriptor Table register. */
324 VBOXIDTR idtr;
325 uint16_t idtrPadding;
326 /** The task register.
327 * Only the guest context uses all the members. */
328 RTSEL ldtr;
329 RTSEL ldtrPadding;
330 /** The task register.
331 * Only the guest context uses all the members. */
332 RTSEL tr;
333 RTSEL trPadding;
334
335 /** The sysenter msr registers.
336 * This member is not used by the hypervisor context. */
337 CPUMSYSENTER SysEnter;
338
339 /** System MSRs.
340 * @{ */
341 uint64_t msrEFER;
342 uint64_t msrSTAR; /**< Legacy syscall eip, cs & ss. */
343 uint64_t msrPAT;
344 uint64_t msrLSTAR; /**< 64 bits mode syscall rip. */
345 uint64_t msrCSTAR; /**< Compatibility mode syscall rip. */
346 uint64_t msrSFMASK; /**< syscall flag mask. */
347 uint64_t msrKERNELGSBASE; /**< swapgs exchange value. */
348 /** @} */
349
350 /** Hidden selector registers.
351 * @{ */
352 CPUMSELREGHID ldtrHid;
353 CPUMSELREGHID trHid;
354 /** @} */
355
356# if 0
357 /** Padding to align the size on a 64 byte boundary. */
358 uint32_t padding[6];
359# endif
360} CPUMCTX;
361# pragma pack()
362#else /* VBOX_WITHOUT_UNNAMED_UNIONS */
363typedef struct CPUMCTX CPUMCTX;
364#endif /* VBOX_WITHOUT_UNNAMED_UNIONS */
365
366/**
367 * Gets the CPUMCTXCORE part of a CPUMCTX.
368 */
369#define CPUMCTX2CORE(pCtx) ((PCPUMCTXCORE)(void *)&(pCtx)->edi)
370
371/**
372 * Selector hidden registers, for version 1.6 saved state.
373 */
374typedef struct CPUMSELREGHID_VER1_6
375{
376 /** Base register. */
377 uint32_t u32Base;
378 /** Limit (expanded). */
379 uint32_t u32Limit;
380 /** Flags.
381 * This is the high 32-bit word of the descriptor entry.
382 * Only the flags, dpl and type are used. */
383 X86DESCATTR Attr;
384} CPUMSELREGHID_VER1_6;
385
386/**
387 * CPU context, for version 1.6 saved state.
388 * @remarks PATM uses this, which is why it has to be here.
389 */
390#ifndef VBOX_WITHOUT_UNNAMED_UNIONS
391# pragma pack(1)
392typedef struct CPUMCTX_VER1_6
393{
394 /** FPU state. (16-byte alignment)
395 * @todo This doesn't have to be in X86FXSTATE on CPUs without fxsr - we need a type for the
396 * actual format or convert it (waste of time). */
397 X86FXSTATE fpu;
398
399 /** CPUMCTXCORE Part.
400 * @{ */
401 union
402 {
403 uint32_t edi;
404 uint64_t rdi;
405 };
406 union
407 {
408 uint32_t esi;
409 uint64_t rsi;
410 };
411 union
412 {
413 uint32_t ebp;
414 uint64_t rbp;
415 };
416 union
417 {
418 uint32_t eax;
419 uint64_t rax;
420 };
421 union
422 {
423 uint32_t ebx;
424 uint64_t rbx;
425 };
426 union
427 {
428 uint32_t edx;
429 uint64_t rdx;
430 };
431 union
432 {
433 uint32_t ecx;
434 uint64_t rcx;
435 };
436 /** @note We rely on the exact layout, because we use lss esp, [] in the
437 * switcher. */
438 uint32_t esp;
439 RTSEL ss;
440 RTSEL ssPadding;
441 /* Note: no overlap with esp here. */
442 uint64_t rsp_notused;
443
444 RTSEL gs;
445 RTSEL gsPadding;
446 RTSEL fs;
447 RTSEL fsPadding;
448 RTSEL es;
449 RTSEL esPadding;
450 RTSEL ds;
451 RTSEL dsPadding;
452 RTSEL cs;
453 RTSEL csPadding[3]; /**< 3 words to force 8 byte alignment for the remainder. */
454
455 union
456 {
457 X86EFLAGS eflags;
458 X86RFLAGS rflags;
459 };
460 union
461 {
462 uint32_t eip;
463 uint64_t rip;
464 };
465
466 uint64_t r8;
467 uint64_t r9;
468 uint64_t r10;
469 uint64_t r11;
470 uint64_t r12;
471 uint64_t r13;
472 uint64_t r14;
473 uint64_t r15;
474
475 /** Hidden selector registers.
476 * @{ */
477 CPUMSELREGHID_VER1_6 esHid;
478 CPUMSELREGHID_VER1_6 csHid;
479 CPUMSELREGHID_VER1_6 ssHid;
480 CPUMSELREGHID_VER1_6 dsHid;
481 CPUMSELREGHID_VER1_6 fsHid;
482 CPUMSELREGHID_VER1_6 gsHid;
483 /** @} */
484
485 /** @} */
486
487 /** Control registers.
488 * @{ */
489 uint64_t cr0;
490 uint64_t cr2;
491 uint64_t cr3;
492 uint64_t cr4;
493 uint64_t cr8;
494 /** @} */
495
496 /** Debug registers.
497 * @{ */
498 uint64_t dr0;
499 uint64_t dr1;
500 uint64_t dr2;
501 uint64_t dr3;
502 uint64_t dr4; /**< @todo remove dr4 and dr5. */
503 uint64_t dr5;
504 uint64_t dr6;
505 uint64_t dr7;
506 /* DR8-15 are currently not supported */
507 /** @} */
508
509 /** Global Descriptor Table register. */
510 VBOXGDTR_VER1_6 gdtr;
511 uint16_t gdtrPadding;
512 uint32_t gdtrPadding64;/** @todo fix this hack */
513 /** Interrupt Descriptor Table register. */
514 VBOXIDTR_VER1_6 idtr;
515 uint16_t idtrPadding;
516 uint32_t idtrPadding64;/** @todo fix this hack */
517 /** The task register.
518 * Only the guest context uses all the members. */
519 RTSEL ldtr;
520 RTSEL ldtrPadding;
521 /** The task register.
522 * Only the guest context uses all the members. */
523 RTSEL tr;
524 RTSEL trPadding;
525
526 /** The sysenter msr registers.
527 * This member is not used by the hypervisor context. */
528 CPUMSYSENTER SysEnter;
529
530 /** System MSRs.
531 * @{ */
532 uint64_t msrEFER;
533 uint64_t msrSTAR;
534 uint64_t msrPAT;
535 uint64_t msrLSTAR;
536 uint64_t msrCSTAR;
537 uint64_t msrSFMASK;
538 uint64_t msrFSBASE;
539 uint64_t msrGSBASE;
540 uint64_t msrKERNELGSBASE;
541 /** @} */
542
543 /** Hidden selector registers.
544 * @{ */
545 CPUMSELREGHID_VER1_6 ldtrHid;
546 CPUMSELREGHID_VER1_6 trHid;
547 /** @} */
548
549 /** padding to get 32byte aligned size. */
550 uint32_t padding[2];
551} CPUMCTX_VER1_6;
552#pragma pack()
553#else /* VBOX_WITHOUT_UNNAMED_UNIONS */
554typedef struct CPUMCTX_VER1_6 CPUMCTX_VER1_6;
555#endif /* VBOX_WITHOUT_UNNAMED_UNIONS */
556
557/**
558 * Guest MSR state.
559 *
560 * @note Never change the order here because of saved stated!
561 */
562typedef union CPUMCTXMSR
563{
564 struct
565 {
566 uint64_t tscAux; /**< MSR_K8_TSC_AUX */
567 uint64_t miscEnable; /**< MSR_IA32_MISC_ENABLE */
568 } msr;
569 uint64_t au64[64];
570} CPUMCTXMSR;
571/** Pointer to the guest MSR state. */
572typedef CPUMCTXMSR *PCPUMCTXMSR;
573/** Pointer to the const guest MSR state. */
574typedef const CPUMCTXMSR *PCCPUMCTXMSR;
575
576/**
577 * The register set returned by a CPUID operation.
578 */
579typedef struct CPUMCPUID
580{
581 uint32_t eax;
582 uint32_t ebx;
583 uint32_t ecx;
584 uint32_t edx;
585} CPUMCPUID;
586/** Pointer to a CPUID leaf. */
587typedef CPUMCPUID *PCPUMCPUID;
588/** Pointer to a const CPUID leaf. */
589typedef const CPUMCPUID *PCCPUMCPUID;
590
591/** @} */
592
593RT_C_DECLS_END
594
595#endif
596
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