VirtualBox

source: vbox/trunk/include/VBox/dis.h@ 41739

Last change on this file since 41739 was 41739, checked in by vboxsync, 13 years ago

DISCPUSTATE: s/param/Param/
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1/** @file
2 * DIS - The VirtualBox Disassembler.
3 */
4
5/*
6 * Copyright (C) 2006-2012 Oracle Corporation
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * The contents of this file may alternatively be used under the terms
17 * of the Common Development and Distribution License Version 1.0
18 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19 * VirtualBox OSE distribution, in which case the provisions of the
20 * CDDL are applicable instead of those of the GPL.
21 *
22 * You may elect to license modified versions of this file under the
23 * terms and conditions of either the GPL or the CDDL or both.
24 */
25
26#ifndef ___VBox_dis_h
27#define ___VBox_dis_h
28
29#include <VBox/types.h>
30#include <VBox/disopcode.h>
31#include <iprt/assert.h>
32
33
34RT_C_DECLS_BEGIN
35
36
37/**
38 * CPU mode flags (DISCPUSTATE::mode).
39 */
40typedef enum DISCPUMODE
41{
42 DISCPUMODE_INVALID = 0,
43 DISCPUMODE_16BIT,
44 DISCPUMODE_32BIT,
45 DISCPUMODE_64BIT,
46 /** hack forcing the size of the enum to 32-bits. */
47 DISCPUMODE_MAKE_32BIT_HACK = 0x7fffffff
48} DISCPUMODE;
49
50/** @name Prefix byte flags (DISCPUSTATE::fPrefix).
51 * @{
52 */
53#define DISPREFIX_NONE UINT8_C(0x00)
54/** non-default address size. */
55#define DISPREFIX_ADDRSIZE UINT8_C(0x01)
56/** non-default operand size. */
57#define DISPREFIX_OPSIZE UINT8_C(0x02)
58/** lock prefix. */
59#define DISPREFIX_LOCK UINT8_C(0x04)
60/** segment prefix. */
61#define DISPREFIX_SEG UINT8_C(0x08)
62/** rep(e) prefix (not a prefix, but we'll treat is as one). */
63#define DISPREFIX_REP UINT8_C(0x10)
64/** rep(e) prefix (not a prefix, but we'll treat is as one). */
65#define DISPREFIX_REPNE UINT8_C(0x20)
66/** REX prefix (64 bits) */
67#define DISPREFIX_REX UINT8_C(0x40)
68/** @} */
69
70/** @name 64 bits prefix byte flags (DISCPUSTATE::fRexPrefix).
71 * Requires VBox/disopcode.h.
72 * @{
73 */
74#define DISPREFIX_REX_OP_2_FLAGS(a) (a - OP_PARM_REX_START)
75#define DISPREFIX_REX_FLAGS DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX)
76#define DISPREFIX_REX_FLAGS_B DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_B)
77#define DISPREFIX_REX_FLAGS_X DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_X)
78#define DISPREFIX_REX_FLAGS_XB DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_XB)
79#define DISPREFIX_REX_FLAGS_R DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_R)
80#define DISPREFIX_REX_FLAGS_RB DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_RB)
81#define DISPREFIX_REX_FLAGS_RX DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_RX)
82#define DISPREFIX_REX_FLAGS_RXB DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_RXB)
83#define DISPREFIX_REX_FLAGS_W DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_W)
84#define DISPREFIX_REX_FLAGS_WB DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_WB)
85#define DISPREFIX_REX_FLAGS_WX DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_WX)
86#define DISPREFIX_REX_FLAGS_WXB DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_WXB)
87#define DISPREFIX_REX_FLAGS_WR DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_WR)
88#define DISPREFIX_REX_FLAGS_WRB DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_WRB)
89#define DISPREFIX_REX_FLAGS_WRX DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_WRX)
90#define DISPREFIX_REX_FLAGS_WRXB DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_WRXB)
91/** @} */
92
93/** @name Operand type (DISOPCODE::fOpType).
94 * @{
95 */
96#define DISOPTYPE_INVALID RT_BIT_32(0)
97#define DISOPTYPE_HARMLESS RT_BIT_32(1)
98#define DISOPTYPE_CONTROLFLOW RT_BIT_32(2)
99#define DISOPTYPE_POTENTIALLY_DANGEROUS RT_BIT_32(3)
100#define DISOPTYPE_DANGEROUS RT_BIT_32(4)
101#define DISOPTYPE_PORTIO RT_BIT_32(5)
102#define DISOPTYPE_PRIVILEGED RT_BIT_32(6)
103#define DISOPTYPE_PRIVILEGED_NOTRAP RT_BIT_32(7)
104#define DISOPTYPE_UNCOND_CONTROLFLOW RT_BIT_32(8)
105#define DISOPTYPE_RELATIVE_CONTROLFLOW RT_BIT_32(9)
106#define DISOPTYPE_COND_CONTROLFLOW RT_BIT_32(10)
107#define DISOPTYPE_INTERRUPT RT_BIT_32(11)
108#define DISOPTYPE_ILLEGAL RT_BIT_32(12)
109#define DISOPTYPE_RRM_DANGEROUS RT_BIT_32(14) /**< Some additional dangerous ones when recompiling raw r0. */
110#define DISOPTYPE_RRM_DANGEROUS_16 RT_BIT_32(15) /**< Some additional dangerous ones when recompiling 16-bit raw r0. */
111#define DISOPTYPE_RRM_MASK (DISOPTYPE_RRM_DANGEROUS | DISOPTYPE_RRM_DANGEROUS_16)
112#define DISOPTYPE_INHIBIT_IRQS RT_BIT_32(16) /**< Will or can inhibit irqs (sti, pop ss, mov ss) */
113#define DISOPTYPE_PORTIO_READ RT_BIT_32(17)
114#define DISOPTYPE_PORTIO_WRITE RT_BIT_32(18)
115#define DISOPTYPE_INVALID_64 RT_BIT_32(19) /**< Invalid in 64 bits mode */
116#define DISOPTYPE_ONLY_64 RT_BIT_32(20) /**< Only valid in 64 bits mode */
117#define DISOPTYPE_DEFAULT_64_OP_SIZE RT_BIT_32(21) /**< Default 64 bits operand size */
118#define DISOPTYPE_FORCED_64_OP_SIZE RT_BIT_32(22) /**< Forced 64 bits operand size; regardless of prefix bytes */
119#define DISOPTYPE_REXB_EXTENDS_OPREG RT_BIT_32(23) /**< REX.B extends the register field in the opcode byte */
120#define DISOPTYPE_MOD_FIXED_11 RT_BIT_32(24) /**< modrm.mod is always 11b */
121#define DISOPTYPE_FORCED_32_OP_SIZE_X86 RT_BIT_32(25) /**< Forced 32 bits operand size; regardless of prefix bytes (only in 16 & 32 bits mode!) */
122#define DISOPTYPE_ALL UINT32_C(0xffffffff)
123/** @} */
124
125/** @name Parameter usage flags.
126 * @{
127 */
128#define DISUSE_BASE RT_BIT_64(0)
129#define DISUSE_INDEX RT_BIT_64(1)
130#define DISUSE_SCALE RT_BIT_64(2)
131#define DISUSE_REG_GEN8 RT_BIT_64(3)
132#define DISUSE_REG_GEN16 RT_BIT_64(4)
133#define DISUSE_REG_GEN32 RT_BIT_64(5)
134#define DISUSE_REG_GEN64 RT_BIT_64(6)
135#define DISUSE_REG_FP RT_BIT_64(7)
136#define DISUSE_REG_MMX RT_BIT_64(8)
137#define DISUSE_REG_XMM RT_BIT_64(9)
138#define DISUSE_REG_CR RT_BIT_64(10)
139#define DISUSE_REG_DBG RT_BIT_64(11)
140#define DISUSE_REG_SEG RT_BIT_64(12)
141#define DISUSE_REG_TEST RT_BIT_64(13)
142#define DISUSE_DISPLACEMENT8 RT_BIT_64(14)
143#define DISUSE_DISPLACEMENT16 RT_BIT_64(15)
144#define DISUSE_DISPLACEMENT32 RT_BIT_64(16)
145#define DISUSE_DISPLACEMENT64 RT_BIT_64(17)
146#define DISUSE_RIPDISPLACEMENT32 RT_BIT_64(18)
147#define DISUSE_IMMEDIATE8 RT_BIT_64(19)
148#define DISUSE_IMMEDIATE8_REL RT_BIT_64(20)
149#define DISUSE_IMMEDIATE16 RT_BIT_64(21)
150#define DISUSE_IMMEDIATE16_REL RT_BIT_64(22)
151#define DISUSE_IMMEDIATE32 RT_BIT_64(23)
152#define DISUSE_IMMEDIATE32_REL RT_BIT_64(24)
153#define DISUSE_IMMEDIATE64 RT_BIT_64(25)
154#define DISUSE_IMMEDIATE64_REL RT_BIT_64(26)
155#define DISUSE_IMMEDIATE_ADDR_0_32 RT_BIT_64(27)
156#define DISUSE_IMMEDIATE_ADDR_16_32 RT_BIT_64(28)
157#define DISUSE_IMMEDIATE_ADDR_0_16 RT_BIT_64(29)
158#define DISUSE_IMMEDIATE_ADDR_16_16 RT_BIT_64(30)
159/** DS:ESI */
160#define DISUSE_POINTER_DS_BASED RT_BIT_64(31)
161/** ES:EDI */
162#define DISUSE_POINTER_ES_BASED RT_BIT_64(32)
163#define DISUSE_IMMEDIATE16_SX8 RT_BIT_64(33)
164#define DISUSE_IMMEDIATE32_SX8 RT_BIT_64(34)
165#define DISUSE_IMMEDIATE64_SX8 RT_BIT_64(36)
166
167/** Mask of immediate use flags. */
168#define DISUSE_IMMEDIATE ( DISUSE_IMMEDIATE8 \
169 | DISUSE_IMMEDIATE16 \
170 | DISUSE_IMMEDIATE32 \
171 | DISUSE_IMMEDIATE64 \
172 | DISUSE_IMMEDIATE8_REL \
173 | DISUSE_IMMEDIATE16_REL \
174 | DISUSE_IMMEDIATE32_REL \
175 | DISUSE_IMMEDIATE64_REL \
176 | DISUSE_IMMEDIATE_ADDR_0_32 \
177 | DISUSE_IMMEDIATE_ADDR_16_32 \
178 | DISUSE_IMMEDIATE_ADDR_0_16 \
179 | DISUSE_IMMEDIATE_ADDR_16_16 \
180 | DISUSE_IMMEDIATE16_SX8 \
181 | DISUSE_IMMEDIATE32_SX8 \
182 | DISUSE_IMMEDIATE64_SX8)
183/** Check if the use flags indicates an effective address. */
184#define DISUSE_IS_EFFECTIVE_ADDR(a_fUseFlags) (!!( (a_fUseFlags) \
185 & ( DISUSE_BASE \
186 | DISUSE_INDEX \
187 | DISUSE_DISPLACEMENT32 \
188 | DISUSE_DISPLACEMENT64 \
189 | DISUSE_DISPLACEMENT16 \
190 | DISUSE_DISPLACEMENT8 \
191 | DISUSE_RIPDISPLACEMENT32) ))
192/** @} */
193
194/** @name 64-bit general register indexes.
195 * This matches the AMD64 register encoding. It is found used in
196 * DISOPPARAM::base.reg_gen and DISOPPARAM::index.reg_gen.
197 * @note Safe to assume same values as the 16-bit and 32-bit general registers.
198 * @{
199 */
200#define DISGREG_RAX UINT8_C(0)
201#define DISGREG_RCX UINT8_C(1)
202#define DISGREG_RDX UINT8_C(2)
203#define DISGREG_RBX UINT8_C(3)
204#define DISGREG_RSP UINT8_C(4)
205#define DISGREG_RBP UINT8_C(5)
206#define DISGREG_RSI UINT8_C(6)
207#define DISGREG_RDI UINT8_C(7)
208#define DISGREG_R8 UINT8_C(8)
209#define DISGREG_R9 UINT8_C(9)
210#define DISGREG_R10 UINT8_C(10)
211#define DISGREG_R11 UINT8_C(11)
212#define DISGREG_R12 UINT8_C(12)
213#define DISGREG_R13 UINT8_C(13)
214#define DISGREG_R14 UINT8_C(14)
215#define DISGREG_R15 UINT8_C(15)
216/** @} */
217
218/** @name 32-bit general register indexes.
219 * This matches the AMD64 register encoding. It is found used in
220 * DISOPPARAM::base.reg_gen and DISOPPARAM::index.reg_gen.
221 * @note Safe to assume same values as the 16-bit and 64-bit general registers.
222 * @{
223 */
224#define DISGREG_EAX UINT8_C(0)
225#define DISGREG_ECX UINT8_C(1)
226#define DISGREG_EDX UINT8_C(2)
227#define DISGREG_EBX UINT8_C(3)
228#define DISGREG_ESP UINT8_C(4)
229#define DISGREG_EBP UINT8_C(5)
230#define DISGREG_ESI UINT8_C(6)
231#define DISGREG_EDI UINT8_C(7)
232#define DISGREG_R8D UINT8_C(8)
233#define DISGREG_R9D UINT8_C(9)
234#define DISGREG_R10D UINT8_C(10)
235#define DISGREG_R11D UINT8_C(11)
236#define DISGREG_R12D UINT8_C(12)
237#define DISGREG_R13D UINT8_C(13)
238#define DISGREG_R14D UINT8_C(14)
239#define DISGREG_R15D UINT8_C(15)
240/** @} */
241
242/** @name 16-bit general register indexes.
243 * This matches the AMD64 register encoding. It is found used in
244 * DISOPPARAM::base.reg_gen and DISOPPARAM::index.reg_gen.
245 * @note Safe to assume same values as the 32-bit and 64-bit general registers.
246 * @{
247 */
248#define DISGREG_AX UINT8_C(0)
249#define DISGREG_CX UINT8_C(1)
250#define DISGREG_DX UINT8_C(2)
251#define DISGREG_BX UINT8_C(3)
252#define DISGREG_SP UINT8_C(4)
253#define DISGREG_BP UINT8_C(5)
254#define DISGREG_SI UINT8_C(6)
255#define DISGREG_DI UINT8_C(7)
256#define DISGREG_R8W UINT8_C(8)
257#define DISGREG_R9W UINT8_C(9)
258#define DISGREG_R10W UINT8_C(10)
259#define DISGREG_R11W UINT8_C(11)
260#define DISGREG_R12W UINT8_C(12)
261#define DISGREG_R13W UINT8_C(13)
262#define DISGREG_R14W UINT8_C(14)
263#define DISGREG_R15W UINT8_C(15)
264/** @} */
265
266/** @name 8-bit general register indexes.
267 * This mostly (?) matches the AMD64 register encoding. It is found used in
268 * DISOPPARAM::base.reg_gen and DISOPPARAM::index.reg_gen.
269 * @{
270 */
271#define DISGREG_AL UINT8_C(0)
272#define DISGREG_CL UINT8_C(1)
273#define DISGREG_DL UINT8_C(2)
274#define DISGREG_BL UINT8_C(3)
275#define DISGREG_AH UINT8_C(4)
276#define DISGREG_CH UINT8_C(5)
277#define DISGREG_DH UINT8_C(6)
278#define DISGREG_BH UINT8_C(7)
279#define DISGREG_R8B UINT8_C(8)
280#define DISGREG_R9B UINT8_C(9)
281#define DISGREG_R10B UINT8_C(10)
282#define DISGREG_R11B UINT8_C(11)
283#define DISGREG_R12B UINT8_C(12)
284#define DISGREG_R13B UINT8_C(13)
285#define DISGREG_R14B UINT8_C(14)
286#define DISGREG_R15B UINT8_C(15)
287#define DISGREG_SPL UINT8_C(16)
288#define DISGREG_BPL UINT8_C(17)
289#define DISGREG_SIL UINT8_C(18)
290#define DISGREG_DIL UINT8_C(19)
291/** @} */
292
293/** @name Segment registerindexes.
294 * This matches the AMD64 register encoding. It is found used in
295 * DISOPPARAM::base.reg_seg.
296 * @{
297 */
298typedef enum
299{
300 DISSELREG_ES = 0,
301 DISSELREG_CS = 1,
302 DISSELREG_SS = 2,
303 DISSELREG_DS = 3,
304 DISSELREG_FS = 4,
305 DISSELREG_GS = 5,
306 /** The usual 32-bit paranoia. */
307 DIS_SEGREG_32BIT_HACK = 0x7fffffff
308} DISSELREG;
309/** @} */
310
311/** @name FPU register indexes.
312 * This matches the AMD64 register encoding. It is found used in
313 * DISOPPARAM::base.reg_fp.
314 * @{
315 */
316#define DISFPREG_ST0 UINT8_C(0)
317#define DISFPREG_ST1 UINT8_C(1)
318#define DISFPREG_ST2 UINT8_C(2)
319#define DISFPREG_ST3 UINT8_C(3)
320#define DISFPREG_ST4 UINT8_C(4)
321#define DISFPREG_ST5 UINT8_C(5)
322#define DISFPREG_ST6 UINT8_C(6)
323#define DISFPREG_ST7 UINT8_C(7)
324/** @} */
325
326/** @name Control register indexes.
327 * This matches the AMD64 register encoding. It is found used in
328 * DISOPPARAM::base.reg_ctrl.
329 * @{
330 */
331#define DISCREG_CR0 UINT8_C(0)
332#define DISCREG_CR1 UINT8_C(1)
333#define DISCREG_CR2 UINT8_C(2)
334#define DISCREG_CR3 UINT8_C(3)
335#define DISCREG_CR4 UINT8_C(4)
336#define DISCREG_CR8 UINT8_C(8)
337/** @} */
338
339/** @name Debug register indexes.
340 * This matches the AMD64 register encoding. It is found used in
341 * DISOPPARAM::base.reg_dbg.
342 * @{
343 */
344#define DISDREG_DR0 UINT8_C(0)
345#define DISDREG_DR1 UINT8_C(1)
346#define DISDREG_DR2 UINT8_C(2)
347#define DISDREG_DR3 UINT8_C(3)
348#define DISDREG_DR4 UINT8_C(4)
349#define DISDREG_DR5 UINT8_C(5)
350#define DISDREG_DR6 UINT8_C(6)
351#define DISDREG_DR7 UINT8_C(7)
352/** @} */
353
354/** @name MMX register indexes.
355 * This matches the AMD64 register encoding. It is found used in
356 * DISOPPARAM::base.reg_mmx.
357 * @{
358 */
359#define DISMREG_MMX0 UINT8_C(0)
360#define DISMREG_MMX1 UINT8_C(1)
361#define DISMREG_MMX2 UINT8_C(2)
362#define DISMREG_MMX3 UINT8_C(3)
363#define DISMREG_MMX4 UINT8_C(4)
364#define DISMREG_MMX5 UINT8_C(5)
365#define DISMREG_MMX6 UINT8_C(6)
366#define DISMREG_MMX7 UINT8_C(7)
367/** @} */
368
369/** @name SSE register indexes.
370 * This matches the AMD64 register encoding. It is found used in
371 * DISOPPARAM::base.reg_xmm.
372 * @{
373 */
374#define DISXREG_XMM0 UINT8_C(0)
375#define DISXREG_XMM1 UINT8_C(1)
376#define DISXREG_XMM2 UINT8_C(2)
377#define DISXREG_XMM3 UINT8_C(3)
378#define DISXREG_XMM4 UINT8_C(4)
379#define DISXREG_XMM5 UINT8_C(5)
380#define DISXREG_XMM6 UINT8_C(6)
381#define DISXREG_XMM7 UINT8_C(7)
382/** @} */
383
384
385/**
386 * Operand Parameter.
387 */
388typedef struct DISOPPARAM
389{
390 uint64_t parval;
391 /** A combination of DISUSE_XXX. */
392 uint64_t fUse;
393 union
394 {
395 int64_t i64;
396 int32_t i32;
397 int32_t i16;
398 int32_t i8;
399 uint64_t u64;
400 uint32_t u32;
401 uint32_t u16;
402 uint32_t u8;
403 } uDisp;
404 int32_t param;
405
406 union
407 {
408 /** DISGREG_XXX. */
409 uint8_t reg_gen;
410 /** DISFPREG_XXX */
411 uint8_t reg_fp;
412 /** DISMREG_XXX. */
413 uint8_t reg_mmx;
414 /** DISXREG_XXX. */
415 uint8_t reg_xmm;
416 /** DISSELREG_XXX. */
417 uint8_t reg_seg;
418 /** TR0-TR7 (no defines for these). */
419 uint8_t reg_test;
420 /** DISCREG_XXX */
421 uint8_t reg_ctrl;
422 /** DISDREG_XXX */
423 uint8_t reg_dbg;
424 } base;
425 union
426 {
427 /** DISGREG_XXX. */
428 uint8_t reg_gen;
429 } index;
430
431 /** 2, 4 or 8. */
432 uint8_t scale;
433 /** Parameter size. */
434 uint8_t cb;
435} DISOPPARAM;
436AssertCompileSize(DISOPPARAM, 32);
437/** Pointer to opcode parameter. */
438typedef DISOPPARAM *PDISOPPARAM;
439/** Pointer to opcode parameter. */
440typedef const DISOPPARAM *PCDISOPPARAM;
441
442
443/**
444 * Opcode descriptor.
445 */
446typedef struct DISOPCODE
447{
448#ifndef DIS_CORE_ONLY
449 const char *pszOpcode;
450#endif
451 /** Parameter \#1 parser index. */
452 uint8_t idxParse1;
453 /** Parameter \#2 parser index. */
454 uint8_t idxParse2;
455 /** Parameter \#3 parser index. */
456 uint8_t idxParse3;
457 /** Unused padding. */
458 uint8_t uUnused;
459 /** The opcode identifier. This DIS specific, @see grp_dis_opcodes and
460 * VBox/disopcode.h. */
461 uint16_t uOpcode;
462 /** Parameter \#1 info, @see grp_dis_opparam. */
463 uint16_t fParam1;
464 /** Parameter \#2 info, @see grp_dis_opparam. */
465 uint16_t fParam2;
466 /** Parameter \#3 info, @see grp_dis_opparam. */
467 uint16_t fParam3;
468 /** Operand type flags, DISOPTYPE_XXX. */
469 uint32_t fOpType;
470} DISOPCODE;
471/** Pointer to const opcode. */
472typedef const struct DISOPCODE *PCDISOPCODE;
473
474
475/**
476 * Callback for reading opcode bytes.
477 *
478 * @param pDisState Pointer to the CPU state. The primary user argument
479 * can be retrived from DISCPUSTATE::pvUser. If
480 * more is required these can be passed in the
481 * subsequent slots.
482 * @param pbDst Pointer to output buffer.
483 * @param uSrcAddr The address to start reading at.
484 * @param cbToRead The number of bytes to read.
485 */
486typedef DECLCALLBACK(int) FNDISREADBYTES(PDISCPUSTATE pDisState, uint8_t *pbDst, RTUINTPTR uSrcAddr, uint32_t cbToRead);
487/** Pointer to a opcode byte reader. */
488typedef FNDISREADBYTES *PFNDISREADBYTES;
489
490/** Parser callback.
491 * @remark no DECLCALLBACK() here because it's considered to be internal (really, I'm too lazy to update all the functions). */
492typedef unsigned FNDISPARSE(RTUINTPTR pu8CodeBlock, PCDISOPCODE pOp, PDISOPPARAM pParam, PDISCPUSTATE pCpu);
493/** Pointer to a disassembler parser function. */
494typedef FNDISPARSE *PFNDISPARSE;
495/** Pointer to a const disassembler parser function pointer. */
496typedef PFNDISPARSE const *PCPFNDISPARSE;
497
498/**
499 * The diassembler state and result.
500 */
501typedef struct DISCPUSTATE
502{
503 /* Because of pvUser2, put the less frequently used bits at the top for
504 now. (Might be better off in the middle?) */
505 DISOPPARAM Param3;
506 DISOPPARAM Param2;
507 DISOPPARAM Param1;
508
509 /* off: 0x060 (96) */
510 /** ModRM fields. */
511 union
512 {
513 /** Bitfield view */
514 struct
515 {
516 unsigned Rm : 4;
517 unsigned Reg : 4;
518 unsigned Mod : 2;
519 } Bits;
520 /** unsigned view */
521 unsigned u;
522 } ModRM;
523 /** SIB fields. */
524 union
525 {
526 /** Bitfield view */
527 struct
528 {
529 unsigned Base : 4;
530 unsigned Index : 4;
531 unsigned Scale : 2;
532 } Bits;
533 /** unsigned view */
534 unsigned u;
535 } SIB;
536 int32_t i32SibDisp;
537
538 /* off: 0x06c (108) */
539 /** The CPU mode (DISCPUMODE). */
540 uint8_t uCpuMode;
541 /** The addressing mode (DISCPUMODE). */
542 uint8_t uAddrMode;
543 /** The operand mode (DISCPUMODE). */
544 uint8_t uOpMode;
545 /** Per instruction prefix settings. */
546 uint8_t fPrefix;
547 /* off: 0x070 (112) */
548 /** REX prefix value (64 bits only). */
549 uint8_t fRexPrefix;
550 /** Segment prefix value (DISSELREG). */
551 uint8_t idxSegPrefix;
552 /** Last prefix byte (for SSE2 extension tables). */
553 uint8_t bLastPrefix;
554 /** First opcode byte of instruction. */
555 uint8_t bOpCode;
556 /* off: 0x074 (116) */
557 /** The size of the prefix bytes. */
558 uint8_t cbPrefix;
559 /** The instruction size. */
560 uint8_t cbInstr;
561 uint8_t abUnused[2];
562 /* off: 0x078 (120) */
563 /** Return code set by a worker function like the opcode bytes readers. */
564 int32_t rc;
565 /** Internal: instruction filter */
566 uint32_t fFilter;
567 /* off: 0x080 (128) */
568 /** Internal: pointer to disassembly function table */
569 PCPFNDISPARSE pfnDisasmFnTable;
570#if ARCH_BITS == 32
571 uint32_t uPtrPadding1;
572#endif
573 /** Pointer to the current instruction. */
574 PCDISOPCODE pCurInstr;
575#if ARCH_BITS == 32
576 uint32_t uPtrPadding2;
577#endif
578 /* off: 0x090 (144) */
579 /** The address of the instruction. */
580 RTUINTPTR uInstrAddr;
581 /* off: 0x098 (152) */
582 /** Optional read function */
583 PFNDISREADBYTES pfnReadBytes;
584#if ARCH_BITS == 32
585 uint32_t uPadding3;
586#endif
587 /* off: 0x0a0 (160) */
588 /** The instruction bytes. */
589 uint8_t abInstr[16];
590 /* off: 0x0b0 (176) */
591 /** User data supplied as an argument to the APIs. */
592 void *pvUser;
593#if ARCH_BITS == 32
594 uint32_t uPadding4;
595#endif
596 /** User data that can be set prior to calling the API.
597 * @deprecated Please don't use this any more. */
598 void *pvUser2;
599#if ARCH_BITS == 32
600 uint32_t uPadding5;
601#endif
602} DISCPUSTATE;
603
604
605
606DISDECL(int) DISInstrToStr(void const *pvInstr, DISCPUMODE enmCpuMode,
607 PDISCPUSTATE pCpu, uint32_t *pcbInstr, char *pszOutput, size_t cbOutput);
608DISDECL(int) DISInstrToStrWithReader(RTUINTPTR uInstrAddr, DISCPUMODE enmCpuMode, PFNDISREADBYTES pfnReadBytes, void *pvUser,
609 PDISCPUSTATE pCpu, uint32_t *pcbInstr, char *pszOutput, size_t cbOutput);
610DISDECL(int) DISInstrToStrEx(RTUINTPTR uInstrAddr, DISCPUMODE enmCpuMode,
611 PFNDISREADBYTES pfnReadBytes, void *pvUser, uint32_t uFilter,
612 PDISCPUSTATE pCpu, uint32_t *pcbInstr, char *pszOutput, size_t cbOutput);
613
614DISDECL(int) DISInstr(void const *pvInstr, DISCPUMODE enmCpuMode, PDISCPUSTATE pCpu, uint32_t *pcbInstr);
615DISDECL(int) DISInstrWithReader(RTUINTPTR uInstrAddr, DISCPUMODE enmCpuMode, PFNDISREADBYTES pfnReadBytes, void *pvUser,
616 PDISCPUSTATE pCpu, uint32_t *pcbInstr);
617DISDECL(int) DISInstEx(RTUINTPTR uInstrAddr, DISCPUMODE enmCpuMode, uint32_t uFilter,
618 PFNDISREADBYTES pfnReadBytes, void *pvUser,
619 PDISCPUSTATE pCpu, uint32_t *pcbInstr);
620
621DISDECL(int) DISGetParamSize(PDISCPUSTATE pCpu, PDISOPPARAM pParam);
622DISDECL(DISSELREG) DISDetectSegReg(PDISCPUSTATE pCpu, PDISOPPARAM pParam);
623DISDECL(uint8_t) DISQuerySegPrefixByte(PDISCPUSTATE pCpu);
624
625
626
627/** @name Flags returned by DISQueryParamVal (DISQPVPARAMVAL::flags).
628 * @{
629 */
630#define DISQPV_FLAG_8 UINT8_C(0x01)
631#define DISQPV_FLAG_16 UINT8_C(0x02)
632#define DISQPV_FLAG_32 UINT8_C(0x04)
633#define DISQPV_FLAG_64 UINT8_C(0x08)
634#define DISQPV_FLAG_FARPTR16 UINT8_C(0x10)
635#define DISQPV_FLAG_FARPTR32 UINT8_C(0x20)
636/** @} */
637
638/** @name Types returned by DISQueryParamVal (DISQPVPARAMVAL::flags).
639 * @{ */
640#define DISQPV_TYPE_REGISTER UINT8_C(1)
641#define DISQPV_TYPE_ADDRESS UINT8_C(2)
642#define DISQPV_TYPE_IMMEDIATE UINT8_C(3)
643/** @} */
644
645typedef struct
646{
647 union
648 {
649 uint8_t val8;
650 uint16_t val16;
651 uint32_t val32;
652 uint64_t val64;
653
654 struct
655 {
656 uint16_t sel;
657 uint32_t offset;
658 } farptr;
659 } val;
660
661 uint8_t type;
662 uint8_t size;
663 uint8_t flags;
664} DISQPVPARAMVAL;
665/** Pointer to opcode parameter value. */
666typedef DISQPVPARAMVAL *PDISQPVPARAMVAL;
667
668/** Indicates which parameter DISQueryParamVal should operate on. */
669typedef enum DISQPVWHICH
670{
671 DISQPVWHICH_DST = 1,
672 DISQPVWHICH_SRC,
673 DISQPVWHAT_32_BIT_HACK = 0x7fffffff
674} DISQPVWHICH;
675DISDECL(int) DISQueryParamVal(PCPUMCTXCORE pCtx, PDISCPUSTATE pCpu, PDISOPPARAM pParam, PDISQPVPARAMVAL pParamVal, DISQPVWHICH parmtype);
676
677DISDECL(int) DISQueryParamRegPtr(PCPUMCTXCORE pCtx, PDISCPUSTATE pCpu, PDISOPPARAM pParam, void **ppReg, size_t *pcbSize);
678DISDECL(int) DISFetchReg8(PCCPUMCTXCORE pCtx, unsigned reg8, uint8_t *pVal);
679DISDECL(int) DISFetchReg16(PCCPUMCTXCORE pCtx, unsigned reg16, uint16_t *pVal);
680DISDECL(int) DISFetchReg32(PCCPUMCTXCORE pCtx, unsigned reg32, uint32_t *pVal);
681DISDECL(int) DISFetchReg64(PCCPUMCTXCORE pCtx, unsigned reg64, uint64_t *pVal);
682DISDECL(int) DISFetchRegSeg(PCCPUMCTXCORE pCtx, DISSELREG sel, RTSEL *pVal);
683DISDECL(int) DISFetchRegSegEx(PCCPUMCTXCORE pCtx, DISSELREG sel, RTSEL *pVal, PCPUMSELREGHID *ppSelHidReg);
684DISDECL(int) DISWriteReg8(PCPUMCTXCORE pRegFrame, unsigned reg8, uint8_t val8);
685DISDECL(int) DISWriteReg16(PCPUMCTXCORE pRegFrame, unsigned reg32, uint16_t val16);
686DISDECL(int) DISWriteReg32(PCPUMCTXCORE pRegFrame, unsigned reg32, uint32_t val32);
687DISDECL(int) DISWriteReg64(PCPUMCTXCORE pRegFrame, unsigned reg64, uint64_t val64);
688DISDECL(int) DISWriteRegSeg(PCPUMCTXCORE pCtx, DISSELREG sel, RTSEL val);
689DISDECL(int) DISPtrReg8(PCPUMCTXCORE pCtx, unsigned reg8, uint8_t **ppReg);
690DISDECL(int) DISPtrReg16(PCPUMCTXCORE pCtx, unsigned reg16, uint16_t **ppReg);
691DISDECL(int) DISPtrReg32(PCPUMCTXCORE pCtx, unsigned reg32, uint32_t **ppReg);
692DISDECL(int) DISPtrReg64(PCPUMCTXCORE pCtx, unsigned reg64, uint64_t **ppReg);
693
694
695/**
696 * Try resolve an address into a symbol name.
697 *
698 * For use with DISFormatYasmEx(), DISFormatMasmEx() and DISFormatGasEx().
699 *
700 * @returns VBox status code.
701 * @retval VINF_SUCCESS on success, pszBuf contains the full symbol name.
702 * @retval VINF_BUFFER_OVERFLOW if pszBuf is too small the symbol name. The
703 * content of pszBuf is truncated and zero terminated.
704 * @retval VERR_SYMBOL_NOT_FOUND if no matching symbol was found for the address.
705 *
706 * @param pCpu Pointer to the disassembler CPU state.
707 * @param u32Sel The selector value. Use DIS_FMT_SEL_IS_REG, DIS_FMT_SEL_GET_VALUE,
708 * DIS_FMT_SEL_GET_REG to access this.
709 * @param uAddress The segment address.
710 * @param pszBuf Where to store the symbol name
711 * @param cchBuf The size of the buffer.
712 * @param poff If not a perfect match, then this is where the offset from the return
713 * symbol to the specified address is returned.
714 * @param pvUser The user argument.
715 */
716typedef DECLCALLBACK(int) FNDISGETSYMBOL(PCDISCPUSTATE pCpu, uint32_t u32Sel, RTUINTPTR uAddress, char *pszBuf, size_t cchBuf, RTINTPTR *poff, void *pvUser);
717/** Pointer to a FNDISGETSYMBOL(). */
718typedef FNDISGETSYMBOL *PFNDISGETSYMBOL;
719
720/**
721 * Checks if the FNDISGETSYMBOL argument u32Sel is a register or not.
722 */
723#define DIS_FMT_SEL_IS_REG(u32Sel) ( !!((u32Sel) & RT_BIT(31)) )
724
725/**
726 * Extracts the selector value from the FNDISGETSYMBOL argument u32Sel.
727 * @returns Selector value.
728 */
729#define DIS_FMT_SEL_GET_VALUE(u32Sel) ( (RTSEL)(u32Sel) )
730
731/**
732 * Extracts the register number from the FNDISGETSYMBOL argument u32Sel.
733 * @returns USE_REG_CS, USE_REG_SS, USE_REG_DS, USE_REG_ES, USE_REG_FS or USE_REG_FS.
734 */
735#define DIS_FMT_SEL_GET_REG(u32Sel) ( ((u32Sel) >> 16) & 0xf )
736
737/** @internal */
738#define DIS_FMT_SEL_FROM_REG(uReg) ( ((uReg) << 16) | RT_BIT(31) | 0xffff )
739/** @internal */
740#define DIS_FMT_SEL_FROM_VALUE(Sel) ( (Sel) & 0xffff )
741
742
743/** @name Flags for use with DISFormatYasmEx(), DISFormatMasmEx() and DISFormatGasEx().
744 * @{
745 */
746/** Put the address to the right. */
747#define DIS_FMT_FLAGS_ADDR_RIGHT RT_BIT_32(0)
748/** Put the address to the left. */
749#define DIS_FMT_FLAGS_ADDR_LEFT RT_BIT_32(1)
750/** Put the address in comments.
751 * For some assemblers this implies placing it to the right. */
752#define DIS_FMT_FLAGS_ADDR_COMMENT RT_BIT_32(2)
753/** Put the instruction bytes to the right of the disassembly. */
754#define DIS_FMT_FLAGS_BYTES_RIGHT RT_BIT_32(3)
755/** Put the instruction bytes to the left of the disassembly. */
756#define DIS_FMT_FLAGS_BYTES_LEFT RT_BIT_32(4)
757/** Put the instruction bytes in comments.
758 * For some assemblers this implies placing the bytes to the right. */
759#define DIS_FMT_FLAGS_BYTES_COMMENT RT_BIT_32(5)
760/** Put the bytes in square brackets. */
761#define DIS_FMT_FLAGS_BYTES_BRACKETS RT_BIT_32(6)
762/** Put spaces between the bytes. */
763#define DIS_FMT_FLAGS_BYTES_SPACED RT_BIT_32(7)
764/** Display the relative +/- offset of branch instructions that uses relative addresses,
765 * and put the target address in parenthesis. */
766#define DIS_FMT_FLAGS_RELATIVE_BRANCH RT_BIT_32(8)
767/** Strict assembly. The assembly should, when ever possible, make the
768 * assembler reproduce the exact same binary. (Refers to the yasm
769 * strict keyword.) */
770#define DIS_FMT_FLAGS_STRICT RT_BIT_32(9)
771/** Checks if the given flags are a valid combination. */
772#define DIS_FMT_FLAGS_IS_VALID(fFlags) \
773 ( !((fFlags) & ~UINT32_C(0x000003ff)) \
774 && ((fFlags) & (DIS_FMT_FLAGS_ADDR_RIGHT | DIS_FMT_FLAGS_ADDR_LEFT)) != (DIS_FMT_FLAGS_ADDR_RIGHT | DIS_FMT_FLAGS_ADDR_LEFT) \
775 && ( !((fFlags) & DIS_FMT_FLAGS_ADDR_COMMENT) \
776 || (fFlags & (DIS_FMT_FLAGS_ADDR_RIGHT | DIS_FMT_FLAGS_ADDR_LEFT)) ) \
777 && ((fFlags) & (DIS_FMT_FLAGS_BYTES_RIGHT | DIS_FMT_FLAGS_BYTES_LEFT)) != (DIS_FMT_FLAGS_BYTES_RIGHT | DIS_FMT_FLAGS_BYTES_LEFT) \
778 && ( !((fFlags) & (DIS_FMT_FLAGS_BYTES_COMMENT | DIS_FMT_FLAGS_BYTES_BRACKETS)) \
779 || (fFlags & (DIS_FMT_FLAGS_BYTES_RIGHT | DIS_FMT_FLAGS_BYTES_LEFT)) ) \
780 )
781/** @} */
782
783DISDECL(size_t) DISFormatYasm( PCDISCPUSTATE pCpu, char *pszBuf, size_t cchBuf);
784DISDECL(size_t) DISFormatYasmEx(PCDISCPUSTATE pCpu, char *pszBuf, size_t cchBuf, uint32_t fFlags, PFNDISGETSYMBOL pfnGetSymbol, void *pvUser);
785DISDECL(size_t) DISFormatMasm( PCDISCPUSTATE pCpu, char *pszBuf, size_t cchBuf);
786DISDECL(size_t) DISFormatMasmEx(PCDISCPUSTATE pCpu, char *pszBuf, size_t cchBuf, uint32_t fFlags, PFNDISGETSYMBOL pfnGetSymbol, void *pvUser);
787DISDECL(size_t) DISFormatGas( PCDISCPUSTATE pCpu, char *pszBuf, size_t cchBuf);
788DISDECL(size_t) DISFormatGasEx( PCDISCPUSTATE pCpu, char *pszBuf, size_t cchBuf, uint32_t fFlags, PFNDISGETSYMBOL pfnGetSymbol, void *pvUser);
789
790/** @todo DISAnnotate(PCDISCPUSTATE pCpu, char *pszBuf, size_t cchBuf, register reader, memory reader); */
791
792DISDECL(bool) DISFormatYasmIsOddEncoding(PDISCPUSTATE pCpu);
793
794
795RT_C_DECLS_END
796
797#endif
798
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