VirtualBox

source: vbox/trunk/include/VBox/dis.h@ 9569

Last change on this file since 9569 was 9272, checked in by vboxsync, 17 years ago

Fixed symbol lookup - pCpu was missing.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 27.6 KB
Line 
1/** @file
2 * DIS - The VirtualBox Disassembler.
3 */
4
5/*
6 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * The contents of this file may alternatively be used under the terms
17 * of the Common Development and Distribution License Version 1.0
18 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19 * VirtualBox OSE distribution, in which case the provisions of the
20 * CDDL are applicable instead of those of the GPL.
21 *
22 * You may elect to license modified versions of this file under the
23 * terms and conditions of either the GPL or the CDDL or both.
24 *
25 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
26 * Clara, CA 95054 USA or visit http://www.sun.com if you need
27 * additional information or have any questions.
28 */
29
30#ifndef ___VBox_disasm_h
31#define ___VBox_disasm_h
32
33#include <VBox/cdefs.h>
34#include <VBox/types.h>
35#include <VBox/disopcode.h>
36
37#if defined(__L4ENV__)
38#include <setjmp.h>
39#endif
40
41__BEGIN_DECLS
42
43
44/** CPU mode flags (DISCPUSTATE::mode).
45 * @{
46 */
47typedef enum
48{
49 CPUMODE_16BIT = 1,
50 CPUMODE_32BIT = 2,
51 CPUMODE_64BIT = 3,
52 /** hack forcing the size of the enum to 32-bits. */
53 CPUMODE_MAKE_32BIT_HACK = 0x7fffffff
54} DISCPUMODE;
55/** @} */
56
57/** Prefix byte flags
58 * @{
59 */
60#define PREFIX_NONE 0
61/** non-default address size. */
62#define PREFIX_ADDRSIZE RT_BIT(0)
63/** non-default operand size. */
64#define PREFIX_OPSIZE RT_BIT(1)
65/** lock prefix. */
66#define PREFIX_LOCK RT_BIT(2)
67/** segment prefix. */
68#define PREFIX_SEG RT_BIT(3)
69/** rep(e) prefix (not a prefix, but we'll treat is as one). */
70#define PREFIX_REP RT_BIT(4)
71/** rep(e) prefix (not a prefix, but we'll treat is as one). */
72#define PREFIX_REPNE RT_BIT(5)
73/** REX prefix (64 bits) */
74#define PREFIX_REX RT_BIT(6)
75/** @} */
76
77/** 64 bits prefix byte flags
78 * @{
79 */
80#define PREFIX_REX_OP_2_FLAGS(a) (a - OP_PARM_REX_START)
81#define PREFIX_REX_FLAGS PREFIX_REX_OP_2_FLAGS(OP_PARM_REX)
82#define PREFIX_REX_FLAGS_B PREFIX_REX_OP_2_FLAGS(OP_PARM_REX_B)
83#define PREFIX_REX_FLAGS_X PREFIX_REX_OP_2_FLAGS(OP_PARM_REX_X)
84#define PREFIX_REX_FLAGS_XB PREFIX_REX_OP_2_FLAGS(OP_PARM_REX_XB)
85#define PREFIX_REX_FLAGS_R PREFIX_REX_OP_2_FLAGS(OP_PARM_REX_R)
86#define PREFIX_REX_FLAGS_RB PREFIX_REX_OP_2_FLAGS(OP_PARM_REX_RB)
87#define PREFIX_REX_FLAGS_RX PREFIX_REX_OP_2_FLAGS(OP_PARM_REX_RX)
88#define PREFIX_REX_FLAGS_RXB PREFIX_REX_OP_2_FLAGS(OP_PARM_REX_RXB)
89#define PREFIX_REX_FLAGS_W PREFIX_REX_OP_2_FLAGS(OP_PARM_REX_W)
90#define PREFIX_REX_FLAGS_WB PREFIX_REX_OP_2_FLAGS(OP_PARM_REX_WB)
91#define PREFIX_REX_FLAGS_WX PREFIX_REX_OP_2_FLAGS(OP_PARM_REX_WX)
92#define PREFIX_REX_FLAGS_WXB PREFIX_REX_OP_2_FLAGS(OP_PARM_REX_WXB)
93#define PREFIX_REX_FLAGS_WR PREFIX_REX_OP_2_FLAGS(OP_PARM_REX_WR)
94#define PREFIX_REX_FLAGS_WRB PREFIX_REX_OP_2_FLAGS(OP_PARM_REX_WRB)
95#define PREFIX_REX_FLAGS_WRX PREFIX_REX_OP_2_FLAGS(OP_PARM_REX_WRX)
96#define PREFIX_REX_FLAGS_WRXB PREFIX_REX_OP_2_FLAGS(OP_PARM_REX_WRXB)
97/** @} */
98
99/**
100 * Operand type.
101 */
102#define OPTYPE_INVALID RT_BIT(0)
103#define OPTYPE_HARMLESS RT_BIT(1)
104#define OPTYPE_CONTROLFLOW RT_BIT(2)
105#define OPTYPE_POTENTIALLY_DANGEROUS RT_BIT(3)
106#define OPTYPE_DANGEROUS RT_BIT(4)
107#define OPTYPE_PORTIO RT_BIT(5)
108#define OPTYPE_PRIVILEGED RT_BIT(6)
109#define OPTYPE_PRIVILEGED_NOTRAP RT_BIT(7)
110#define OPTYPE_UNCOND_CONTROLFLOW RT_BIT(8)
111#define OPTYPE_RELATIVE_CONTROLFLOW RT_BIT(9)
112#define OPTYPE_COND_CONTROLFLOW RT_BIT(10)
113#define OPTYPE_INTERRUPT RT_BIT(11)
114#define OPTYPE_ILLEGAL RT_BIT(12)
115#define OPTYPE_RRM_DANGEROUS RT_BIT(14) /**< Some additional dangerouse ones when recompiling raw r0. */
116#define OPTYPE_RRM_DANGEROUS_16 RT_BIT(15) /**< Some additional dangerouse ones when recompiling 16-bit raw r0. */
117#define OPTYPE_RRM_MASK (OPTYPE_RRM_DANGEROUS | OPTYPE_RRM_DANGEROUS_16)
118#define OPTYPE_INHIBIT_IRQS RT_BIT(16) /**< Will or can inhibit irqs (sti, pop ss, mov ss) */
119#define OPTYPE_PORTIO_READ RT_BIT(17)
120#define OPTYPE_PORTIO_WRITE RT_BIT(18)
121#define OPTYPE_INVALID_64 RT_BIT(19) /**< Invalid in 64 bits mode */
122#define OPTYPE_ONLY_64 RT_BIT(20) /**< Only valid in 64 bits mode */
123#define OPTYPE_DEFAULT_64_OP_SIZE RT_BIT(21) /**< Default 64 bits operand size */
124#define OPTYPE_FORCED_64_OP_SIZE RT_BIT(22) /**< Forced 64 bits operand size; regardless of prefix bytes */
125#define OPTYPE_REXB_EXTENDS_OPREG RT_BIT(23) /**< REX.B extends the register field in the opcode byte */
126#define OPTYPE_ALL (0xffffffff)
127
128/** Parameter usage flags.
129 * @{
130 */
131#define USE_BASE RT_BIT_64(0)
132#define USE_INDEX RT_BIT_64(1)
133#define USE_SCALE RT_BIT_64(2)
134#define USE_REG_GEN8 RT_BIT_64(3)
135#define USE_REG_GEN16 RT_BIT_64(4)
136#define USE_REG_GEN32 RT_BIT_64(5)
137#define USE_REG_GEN64 RT_BIT_64(6)
138#define USE_REG_FP RT_BIT_64(7)
139#define USE_REG_MMX RT_BIT_64(8)
140#define USE_REG_XMM RT_BIT_64(9)
141#define USE_REG_CR RT_BIT_64(10)
142#define USE_REG_DBG RT_BIT_64(11)
143#define USE_REG_SEG RT_BIT_64(12)
144#define USE_REG_TEST RT_BIT_64(13)
145#define USE_DISPLACEMENT8 RT_BIT_64(14)
146#define USE_DISPLACEMENT16 RT_BIT_64(15)
147#define USE_DISPLACEMENT32 RT_BIT_64(16)
148#define USE_DISPLACEMENT64 RT_BIT_64(17)
149#define USE_RIPDISPLACEMENT32 RT_BIT_64(18)
150#define USE_IMMEDIATE8 RT_BIT_64(19)
151#define USE_IMMEDIATE8_REL RT_BIT_64(20)
152#define USE_IMMEDIATE16 RT_BIT_64(21)
153#define USE_IMMEDIATE16_REL RT_BIT_64(22)
154#define USE_IMMEDIATE32 RT_BIT_64(23)
155#define USE_IMMEDIATE32_REL RT_BIT_64(24)
156#define USE_IMMEDIATE64 RT_BIT_64(25)
157#define USE_IMMEDIATE64_REL RT_BIT_64(26)
158#define USE_IMMEDIATE_ADDR_0_32 RT_BIT_64(27)
159#define USE_IMMEDIATE_ADDR_16_32 RT_BIT_64(28)
160#define USE_IMMEDIATE_ADDR_0_16 RT_BIT_64(29)
161#define USE_IMMEDIATE_ADDR_16_16 RT_BIT_64(30)
162/** DS:ESI */
163#define USE_POINTER_DS_BASED RT_BIT_64(31)
164/** ES:EDI */
165#define USE_POINTER_ES_BASED RT_BIT_64(32)
166#define USE_IMMEDIATE16_SX8 RT_BIT_64(33)
167#define USE_IMMEDIATE32_SX8 RT_BIT_64(34)
168
169#define USE_IMMEDIATE (USE_IMMEDIATE8|USE_IMMEDIATE16|USE_IMMEDIATE32|USE_IMMEDIATE64|USE_IMMEDIATE8_REL|USE_IMMEDIATE16_REL|USE_IMMEDIATE32_REL|USE_IMMEDIATE64_REL|USE_IMMEDIATE_ADDR_0_32|USE_IMMEDIATE_ADDR_16_32|USE_IMMEDIATE_ADDR_0_16|USE_IMMEDIATE_ADDR_16_16|USE_IMMEDIATE16_SX8|USE_IMMEDIATE32_SX8)
170
171#define DIS_IS_EFFECTIVE_ADDR(flags) !!((flags) & (USE_BASE|USE_INDEX|USE_DISPLACEMENT32|USE_DISPLACEMENT16|USE_DISPLACEMENT8|USE_RIPDISPLACEMENT32))
172/** @} */
173
174/** index in {"RAX", "RCX", "RDX", "RBX", "RSP", "RBP", "RSI", "RDI", "R8", "R9", "R10", "R11", "R12", "R13", "R14", "R15"}
175 * @{
176 */
177#define USE_REG_RAX 0
178#define USE_REG_RCX 1
179#define USE_REG_RDX 2
180#define USE_REG_RBX 3
181#define USE_REG_RSP 4
182#define USE_REG_RBP 5
183#define USE_REG_RSI 6
184#define USE_REG_RDI 7
185#define USE_REG_R8 8
186#define USE_REG_R9 9
187#define USE_REG_R10 10
188#define USE_REG_R11 11
189#define USE_REG_R12 12
190#define USE_REG_R13 13
191#define USE_REG_R14 14
192#define USE_REG_R15 15
193/** @} */
194
195/** index in {"EAX", "ECX", "EDX", "EBX", "ESP", "EBP", "ESI", "EDI"}
196 * @{
197 */
198#define USE_REG_EAX 0
199#define USE_REG_ECX 1
200#define USE_REG_EDX 2
201#define USE_REG_EBX 3
202#define USE_REG_ESP 4
203#define USE_REG_EBP 5
204#define USE_REG_ESI 6
205#define USE_REG_EDI 7
206/** @} */
207/** index in {"AX", "CX", "DX", "BX", "SP", "BP", "SI", "DI"}
208 * @{
209 */
210#define USE_REG_AX 0
211#define USE_REG_CX 1
212#define USE_REG_DX 2
213#define USE_REG_BX 3
214#define USE_REG_SP 4
215#define USE_REG_BP 5
216#define USE_REG_SI 6
217#define USE_REG_DI 7
218/** @} */
219
220/** index in {"AL", "CL", "DL", "BL", "AH", "CH", "DH", "BH"}
221 * @{
222 */
223#define USE_REG_AL 0
224#define USE_REG_CL 1
225#define USE_REG_DL 2
226#define USE_REG_BL 3
227#define USE_REG_AH 4
228#define USE_REG_CH 5
229#define USE_REG_DH 6
230#define USE_REG_BH 7
231/** @} */
232
233/** index in {ES, CS, SS, DS, FS, GS}
234 * @{
235 */
236#define USE_REG_ES 0
237#define USE_REG_CS 1
238#define USE_REG_SS 2
239#define USE_REG_DS 3
240#define USE_REG_FS 4
241#define USE_REG_GS 5
242/** @} */
243
244#define USE_REG_FP0 0
245#define USE_REG_FP1 1
246#define USE_REG_FP2 2
247#define USE_REG_FP3 3
248#define USE_REG_FP4 4
249#define USE_REG_FP5 5
250#define USE_REG_FP6 6
251#define USE_REG_FP7 7
252
253#define USE_REG_CR0 0
254#define USE_REG_CR1 1
255#define USE_REG_CR2 2
256#define USE_REG_CR3 3
257#define USE_REG_CR4 4
258
259#define USE_REG_DR0 0
260#define USE_REG_DR1 1
261#define USE_REG_DR2 2
262#define USE_REG_DR3 3
263#define USE_REG_DR4 4
264#define USE_REG_DR5 5
265#define USE_REG_DR6 6
266#define USE_REG_DR7 7
267
268#define USE_REG_MMX0 0
269#define USE_REG_MMX1 1
270#define USE_REG_MMX2 2
271#define USE_REG_MMX3 3
272#define USE_REG_MMX4 4
273#define USE_REG_MMX5 5
274#define USE_REG_MMX6 6
275#define USE_REG_MMX7 7
276
277#define USE_REG_XMM0 0
278#define USE_REG_XMM1 1
279#define USE_REG_XMM2 2
280#define USE_REG_XMM3 3
281#define USE_REG_XMM4 4
282#define USE_REG_XMM5 5
283#define USE_REG_XMM6 6
284#define USE_REG_XMM7 7
285
286/** Used by DISQueryParamVal & EMIQueryParamVal
287 * @{
288 */
289#define PARAM_VAL8 RT_BIT(0)
290#define PARAM_VAL16 RT_BIT(1)
291#define PARAM_VAL32 RT_BIT(2)
292#define PARAM_VAL64 RT_BIT(3)
293#define PARAM_VALFARPTR16 RT_BIT(4)
294#define PARAM_VALFARPTR32 RT_BIT(5)
295
296#define PARMTYPE_REGISTER 1
297#define PARMTYPE_ADDRESS 2
298#define PARMTYPE_IMMEDIATE 3
299
300typedef struct
301{
302 uint32_t type;
303 uint32_t size;
304 uint64_t flags;
305
306 union
307 {
308 uint8_t val8;
309 uint16_t val16;
310 uint32_t val32;
311 uint64_t val64;
312
313 struct
314 {
315 uint16_t sel;
316 uint32_t offset;
317 } farptr;
318 } val;
319
320} OP_PARAMVAL;
321/** Pointer to opcode parameter value. */
322typedef OP_PARAMVAL *POP_PARAMVAL;
323
324typedef enum
325{
326 PARAM_DEST,
327 PARAM_SOURCE
328} PARAM_TYPE;
329
330/** @} */
331
332/**
333 * Operand Parameter.
334 */
335typedef struct _OP_PARAMETER
336{
337 /** @todo switch param and parval and move disp64 and flags up here with the other 64-bit vars to get more natural alignment and save space. */
338 int param;
339 uint64_t parval;
340#ifndef DIS_SEPARATE_FORMATTER
341 char szParam[32];
342#endif
343
344 int32_t disp8, disp16, disp32;
345 uint32_t size;
346
347 int64_t disp64;
348 uint64_t flags;
349
350 union
351 {
352 uint32_t reg_gen;
353 /** ST(0) - ST(7) */
354 uint32_t reg_fp;
355 /** MMX0 - MMX7 */
356 uint32_t reg_mmx;
357 /** XMM0 - XMM7 */
358 uint32_t reg_xmm;
359 /** {ES, CS, SS, DS, FS, GS} */
360 uint32_t reg_seg;
361 /** TR0-TR7 (?) */
362 uint32_t reg_test;
363 /** CR0-CR4 */
364 uint32_t reg_ctrl;
365 /** DR0-DR7 */
366 uint32_t reg_dbg;
367 } base;
368 union
369 {
370 uint32_t reg_gen;
371 } index;
372
373 /** 2, 4 or 8. */
374 uint32_t scale;
375
376} OP_PARAMETER;
377/** Pointer to opcode parameter. */
378typedef OP_PARAMETER *POP_PARAMETER;
379/** Pointer to opcode parameter. */
380typedef const OP_PARAMETER *PCOP_PARAMETER;
381
382
383struct _OPCODE;
384/** Pointer to opcode. */
385typedef struct _OPCODE *POPCODE;
386/** Pointer to const opcode. */
387typedef const struct _OPCODE *PCOPCODE;
388
389typedef DECLCALLBACK(int) FN_DIS_READBYTES(RTUINTPTR pSrc, uint8_t *pDest, unsigned size, void *pvUserdata);
390typedef FN_DIS_READBYTES *PFN_DIS_READBYTES;
391
392/* forward decl */
393struct _DISCPUSTATE;
394/** Pointer to the disassembler CPU state. */
395typedef struct _DISCPUSTATE *PDISCPUSTATE;
396
397/** Parser callback.
398 * @remark no DECLCALLBACK() here because it's considered to be internal (really, I'm too lazy to update all the functions). */
399typedef unsigned FNDISPARSE(RTUINTPTR pu8CodeBlock, PCOPCODE pOp, POP_PARAMETER pParam, PDISCPUSTATE pCpu);
400typedef FNDISPARSE *PFNDISPARSE;
401
402typedef struct _DISCPUSTATE
403{
404 /* Global setting */
405 DISCPUMODE mode;
406
407 /* Per instruction prefix settings */
408 uint32_t prefix;
409 /** segment prefix value. */
410 uint32_t prefix_seg;
411 /** rex prefix value (64 bits only */
412 uint32_t prefix_rex;
413 /** addressing mode (16 or 32 bits). (CPUMODE_*) */
414 DISCPUMODE addrmode;
415 /** operand mode (16 or 32 bits). (CPUMODE_*) */
416 DISCPUMODE opmode;
417
418 OP_PARAMETER param1;
419 OP_PARAMETER param2;
420 OP_PARAMETER param3;
421
422 /** ModRM fields. */
423 union
424 {
425 /* Bitfield view */
426 struct
427 {
428 unsigned Rm : 4;
429 unsigned Reg : 4;
430 unsigned Mod : 2;
431 } Bits;
432 /* unsigned view */
433 unsigned u;
434 } ModRM;
435
436 /** SIB fields. */
437 union
438 {
439 /* Bitfield view */
440 struct
441 {
442 unsigned Base : 4;
443 unsigned Index : 4;
444 unsigned Scale : 2;
445 } Bits;
446 /* unsigned view */
447 unsigned u;
448 } SIB;
449
450 int32_t disp;
451
452 /** First opcode byte of instruction. */
453 uint8_t opcode;
454 /** Last prefix byte (for SSE2 extension tables) */
455 uint8_t lastprefix;
456 RTUINTPTR opaddr;
457 uint32_t opsize;
458#ifndef DIS_CORE_ONLY
459 /** Opcode format string for current instruction. */
460 const char *pszOpcode;
461#endif
462
463 /** Internal: pointer to disassembly function table */
464 PFNDISPARSE *pfnDisasmFnTable;
465 /** Internal: instruction filter */
466 uint32_t uFilter;
467
468 /** Pointer to the current instruction. */
469 PCOPCODE pCurInstr;
470
471 void *apvUserData[3];
472
473 /** Optional read function */
474 PFN_DIS_READBYTES pfnReadBytes;
475#ifdef __L4ENV__
476 jmp_buf *pJumpBuffer;
477#endif /* __L4ENV__ */
478} DISCPUSTATE;
479
480/** Pointer to a const disassembler CPU state. */
481typedef DISCPUSTATE const *PCDISCPUSTATE;
482
483/** Opcode. */
484#pragma pack(4)
485typedef struct _OPCODE
486{
487#ifndef DIS_CORE_ONLY
488 const char *pszOpcode;
489#endif
490 uint8_t idxParse1;
491 uint8_t idxParse2;
492 uint8_t idxParse3;
493 uint16_t opcode;
494 uint16_t param1;
495 uint16_t param2;
496 uint16_t param3;
497
498 unsigned optype;
499} OPCODE;
500#pragma pack()
501
502
503/**
504 * Disassembles a code block.
505 *
506 * @returns VBox error code
507 * @param pCpu Pointer to cpu structure which have DISCPUSTATE::mode
508 * set correctly.
509 * @param pvCodeBlock Pointer to the strunction to disassemble.
510 * @param cbMax Maximum number of bytes to disassemble.
511 * @param pcbSize Where to store the size of the instruction.
512 * NULL is allowed.
513 *
514 *
515 * @todo Define output callback.
516 * @todo Using signed integers as sizes is a bit odd. There are still
517 * some GCC warnings about mixing signed and unsigend integers.
518 * @todo Need to extend this interface to include a code address so we
519 * can dissassemble GC code. Perhaps a new function is better...
520 * @remark cbMax isn't respected as a boundry. DISInstr() will read beyond cbMax.
521 * This means *pcbSize >= cbMax sometimes.
522 */
523DISDECL(int) DISBlock(PDISCPUSTATE pCpu, RTUINTPTR pvCodeBlock, unsigned cbMax, unsigned *pSize);
524
525/**
526 * Disassembles one instruction
527 *
528 * @returns VBox error code
529 * @param pCpu Pointer to cpu structure which have DISCPUSTATE::mode
530 * set correctly.
531 * @param pu8Instruction Pointer to the instrunction to disassemble.
532 * @param u32EipOffset Offset to add to instruction address to get the real virtual address
533 * @param pcbSize Where to store the size of the instruction.
534 * NULL is allowed.
535 * @param pszOutput Storage for disassembled instruction
536 *
537 * @todo Define output callback.
538 */
539DISDECL(int) DISInstr(PDISCPUSTATE pCpu, RTUINTPTR pu8Instruction, unsigned u32EipOffset, unsigned *pcbSize, char *pszOutput);
540
541/**
542 * Disassembles one instruction
543 *
544 * @returns VBox error code
545 * @param pCpu Pointer to cpu structure which have DISCPUSTATE::mode
546 * set correctly.
547 * @param pu8Instruction Pointer to the strunction to disassemble.
548 * @param u32EipOffset Offset to add to instruction address to get the real virtual address
549 * @param pcbSize Where to store the size of the instruction.
550 * NULL is allowed.
551 * @param pszOutput Storage for disassembled instruction
552 * @param uFilter Instruction type filter
553 *
554 * @todo Define output callback.
555 */
556DISDECL(int) DISInstrEx(PDISCPUSTATE pCpu, RTUINTPTR pu8Instruction, uint32_t u32EipOffset, uint32_t *pcbSize,
557 char *pszOutput, unsigned uFilter);
558
559/**
560 * Parses one instruction.
561 * The result is found in pCpu.
562 *
563 * @returns VBox error code
564 * @param pCpu Pointer to cpu structure which has DISCPUSTATE::mode set correctly.
565 * @param InstructionAddr Pointer to the instruction to parse.
566 * @param pcbInstruction Where to store the size of the instruction.
567 * NULL is allowed.
568 */
569DISDECL(int) DISCoreOne(PDISCPUSTATE pCpu, RTUINTPTR InstructionAddr, unsigned *pcbInstruction);
570
571/**
572 * Parses one guest instruction.
573 * The result is found in pCpu and pcbInstruction.
574 *
575 * @returns VBox status code.
576 * @param InstructionAddr Address of the instruction to decode. What this means
577 * is left to the pfnReadBytes function.
578 * @param enmCpuMode The CPU mode. CPUMODE_32BIT, CPUMODE_16BIT, or CPUMODE_64BIT.
579 * @param pfnReadBytes Callback for reading instruction bytes.
580 * @param pvUser User argument for the instruction reader. (Ends up in apvUserData[0].)
581 * @param pCpu Pointer to cpu structure. Will be initialized.
582 * @param pcbInstruction Where to store the size of the instruction.
583 * NULL is allowed.
584 */
585DISDECL(int) DISCoreOneEx(RTUINTPTR InstructionAddr, DISCPUMODE enmCpuMode, PFN_DIS_READBYTES pfnReadBytes, void *pvUser,
586 PDISCPUSTATE pCpu, unsigned *pcbInstruction);
587
588DISDECL(int) DISGetParamSize(PDISCPUSTATE pCpu, POP_PARAMETER pParam);
589DISDECL(int) DISDetectSegReg(PDISCPUSTATE pCpu, POP_PARAMETER pParam);
590DISDECL(uint8_t) DISQuerySegPrefixByte(PDISCPUSTATE pCpu);
591
592/**
593 * Returns the value of the parameter in pParam
594 *
595 * @returns VBox error code
596 * @param pCtx Exception structure pointer
597 * @param pCpu Pointer to cpu structure which have DISCPUSTATE::mode
598 * set correctly.
599 * @param pParam Pointer to the parameter to parse
600 * @param pParamVal Pointer to parameter value (OUT)
601 * @param parmtype Parameter type
602 *
603 * @note Currently doesn't handle FPU/XMM/MMX/3DNow! parameters correctly!!
604 *
605 */
606DISDECL(int) DISQueryParamVal(PCPUMCTXCORE pCtx, PDISCPUSTATE pCpu, POP_PARAMETER pParam, POP_PARAMVAL pParamVal, PARAM_TYPE parmtype);
607DISDECL(int) DISQueryParamRegPtr(PCPUMCTXCORE pCtx, PDISCPUSTATE pCpu, POP_PARAMETER pParam, void **ppReg, size_t *pcbSize);
608
609DISDECL(int) DISFetchReg8(PCPUMCTXCORE pCtx, unsigned reg8, uint8_t *pVal);
610DISDECL(int) DISFetchReg16(PCPUMCTXCORE pCtx, unsigned reg16, uint16_t *pVal);
611DISDECL(int) DISFetchReg32(PCPUMCTXCORE pCtx, unsigned reg32, uint32_t *pVal);
612DISDECL(int) DISFetchReg64(PCPUMCTXCORE pCtx, unsigned reg64, uint64_t *pVal);
613DISDECL(int) DISFetchRegSeg(PCPUMCTXCORE pCtx, unsigned sel, RTSEL *pVal);
614DISDECL(int) DISFetchRegSegEx(PCPUMCTXCORE pCtx, unsigned sel, RTSEL *pVal, PCPUMSELREGHID *ppSelHidReg);
615DISDECL(int) DISWriteReg8(PCPUMCTXCORE pRegFrame, unsigned reg8, uint8_t val8);
616DISDECL(int) DISWriteReg16(PCPUMCTXCORE pRegFrame, unsigned reg32, uint16_t val16);
617DISDECL(int) DISWriteReg32(PCPUMCTXCORE pRegFrame, unsigned reg32, uint32_t val32);
618DISDECL(int) DISWriteReg64(PCPUMCTXCORE pRegFrame, unsigned reg64, uint64_t val64);
619DISDECL(int) DISWriteRegSeg(PCPUMCTXCORE pCtx, unsigned sel, RTSEL val);
620DISDECL(int) DISPtrReg8(PCPUMCTXCORE pCtx, unsigned reg8, uint8_t **ppReg);
621DISDECL(int) DISPtrReg16(PCPUMCTXCORE pCtx, unsigned reg16, uint16_t **ppReg);
622DISDECL(int) DISPtrReg32(PCPUMCTXCORE pCtx, unsigned reg32, uint32_t **ppReg);
623DISDECL(int) DISPtrReg64(PCPUMCTXCORE pCtx, unsigned reg64, uint64_t **ppReg);
624
625
626/**
627 * Try resolve an address into a symbol name.
628 *
629 * For use with DISFormatYasmEx(), DISFormatMasmEx() and DISFormatGasEx().
630 *
631 * @returns VBox status code.
632 * @retval VINF_SUCCESS on success, pszBuf contains the full symbol name.
633 * @retval VINF_BUFFER_OVERFLOW if pszBuf is too small the symbol name. The
634 * content of pszBuf is truncated and zero terminated.
635 * @retval VERR_SYMBOL_NOT_FOUND if no matching symbol was found for the address.
636 *
637 * @param pCpu Pointer to the disassembler CPU state.
638 * @param u32Sel The selector value. Use DIS_FMT_SEL_IS_REG, DIS_FMT_SEL_GET_VALUE,
639 * DIS_FMT_SEL_GET_REG to access this.
640 * @param uAddress The segment address.
641 * @param pszBuf Where to store the symbol name
642 * @param cchBuf The size of the buffer.
643 * @param poff If not a perfect match, then this is where the offset from the return
644 * symbol to the specified address is returned.
645 * @param pvUser The user argument.
646 */
647typedef DECLCALLBACK(int) FNDISGETSYMBOL(PCDISCPUSTATE pCpu, uint32_t u32Sel, RTUINTPTR uAddress, char *pszBuf, size_t cchBuf, RTINTPTR *poff, void *pvUser);
648/** Pointer to a FNDISGETSYMBOL(). */
649typedef FNDISGETSYMBOL *PFNDISGETSYMBOL;
650
651/**
652 * Checks if the FNDISGETSYMBOL argument u32Sel is a register or not.
653 */
654#define DIS_FMT_SEL_IS_REG(u32Sel) ( !!((u32Sel) & RT_BIT(31)) )
655
656/**
657 * Extracts the selector value from the FNDISGETSYMBOL argument u32Sel.
658 * @returns Selector value.
659 */
660#define DIS_FMT_SEL_GET_VALUE(u32Sel) ( (RTSEL)(u32Sel) )
661
662/**
663 * Extracts the register number from the FNDISGETSYMBOL argument u32Sel.
664 * @returns USE_REG_CS, USE_REG_SS, USE_REG_DS, USE_REG_ES, USE_REG_FS or USE_REG_FS.
665 */
666#define DIS_FMT_SEL_GET_REG(u32Sel) ( ((u32Sel) >> 16) & 0xf )
667
668/** @internal */
669#define DIS_FMT_SEL_FROM_REG(uReg) ( ((uReg) << 16) | RT_BIT(31) | 0xffff )
670/** @internal */
671#define DIS_FMT_SEL_FROM_VALUE(Sel) ( (Sel) & 0xffff )
672
673
674/** @name Flags for use with DISFormatYasmEx(), DISFormatMasmEx() and DISFormatGasEx().
675 * @{
676 */
677/** Put the address to the right. */
678#define DIS_FMT_FLAGS_ADDR_RIGHT RT_BIT_32(0)
679/** Put the address to the left. */
680#define DIS_FMT_FLAGS_ADDR_LEFT RT_BIT_32(1)
681/** Put the address in comments.
682 * For some assemblers this implies placing it to the right. */
683#define DIS_FMT_FLAGS_ADDR_COMMENT RT_BIT_32(2)
684/** Put the instruction bytes to the right of the disassembly. */
685#define DIS_FMT_FLAGS_BYTES_RIGHT RT_BIT_32(3)
686/** Put the instruction bytes to the left of the disassembly. */
687#define DIS_FMT_FLAGS_BYTES_LEFT RT_BIT_32(4)
688/** Put the instruction bytes in comments.
689 * For some assemblers this implies placing the bytes to the right. */
690#define DIS_FMT_FLAGS_BYTES_COMMENT RT_BIT_32(5)
691/** Put the bytes in square brackets. */
692#define DIS_FMT_FLAGS_BYTES_BRACKETS RT_BIT_32(6)
693/** Put spaces between the bytes. */
694#define DIS_FMT_FLAGS_BYTES_SPACED RT_BIT_32(7)
695/** Display the relative +/- offset of branch instructions that uses relative addresses,
696 * and put the target address in parenthesis. */
697#define DIS_FMT_FLAGS_RELATIVE_BRANCH RT_BIT_32(8)
698/** Strict assembly. The assembly should, when ever possible, make the
699 * assembler reproduce the exact same binary. (Refers to the yasm
700 * strict keyword.) */
701#define DIS_FMT_FLAGS_STRICT RT_BIT_32(9)
702/** Checks if the given flags are a valid combination. */
703#define DIS_FMT_FLAGS_IS_VALID(fFlags) \
704 ( !((fFlags) & ~UINT32_C(0x000003ff)) \
705 && ((fFlags) & (DIS_FMT_FLAGS_ADDR_RIGHT | DIS_FMT_FLAGS_ADDR_LEFT)) != (DIS_FMT_FLAGS_ADDR_RIGHT | DIS_FMT_FLAGS_ADDR_LEFT) \
706 && ( !((fFlags) & DIS_FMT_FLAGS_ADDR_COMMENT) \
707 || (fFlags & (DIS_FMT_FLAGS_ADDR_RIGHT | DIS_FMT_FLAGS_ADDR_LEFT)) ) \
708 && ((fFlags) & (DIS_FMT_FLAGS_BYTES_RIGHT | DIS_FMT_FLAGS_BYTES_LEFT)) != (DIS_FMT_FLAGS_BYTES_RIGHT | DIS_FMT_FLAGS_BYTES_LEFT) \
709 && ( !((fFlags) & (DIS_FMT_FLAGS_BYTES_COMMENT | DIS_FMT_FLAGS_BYTES_BRACKETS)) \
710 || (fFlags & (DIS_FMT_FLAGS_BYTES_RIGHT | DIS_FMT_FLAGS_BYTES_LEFT)) ) \
711 )
712/** @} */
713
714DISDECL(size_t) DISFormatYasm( PCDISCPUSTATE pCpu, char *pszBuf, size_t cchBuf);
715DISDECL(size_t) DISFormatYasmEx(PCDISCPUSTATE pCpu, char *pszBuf, size_t cchBuf, uint32_t fFlags, PFNDISGETSYMBOL pfnGetSymbol, void *pvUser);
716DISDECL(size_t) DISFormatMasm( PCDISCPUSTATE pCpu, char *pszBuf, size_t cchBuf);
717DISDECL(size_t) DISFormatMasmEx(PCDISCPUSTATE pCpu, char *pszBuf, size_t cchBuf, uint32_t fFlags, PFNDISGETSYMBOL pfnGetSymbol, void *pvUser);
718DISDECL(size_t) DISFormatGas( PCDISCPUSTATE pCpu, char *pszBuf, size_t cchBuf);
719DISDECL(size_t) DISFormatGasEx( PCDISCPUSTATE pCpu, char *pszBuf, size_t cchBuf, uint32_t fFlags, PFNDISGETSYMBOL pfnGetSymbol, void *pvUser);
720
721/** @todo DISAnnotate(PCDISCPUSTATE pCpu, char *pszBuf, size_t cchBuf, register reader, memory reader); */
722
723
724__END_DECLS
725
726#endif
727
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