VirtualBox

source: vbox/trunk/include/VBox/dis.h@ 9721

Last change on this file since 9721 was 9675, checked in by vboxsync, 17 years ago

General cleanup of SELMToFlat.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 27.6 KB
Line 
1/** @file
2 * DIS - The VirtualBox Disassembler.
3 */
4
5/*
6 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * The contents of this file may alternatively be used under the terms
17 * of the Common Development and Distribution License Version 1.0
18 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19 * VirtualBox OSE distribution, in which case the provisions of the
20 * CDDL are applicable instead of those of the GPL.
21 *
22 * You may elect to license modified versions of this file under the
23 * terms and conditions of either the GPL or the CDDL or both.
24 *
25 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
26 * Clara, CA 95054 USA or visit http://www.sun.com if you need
27 * additional information or have any questions.
28 */
29
30#ifndef ___VBox_disasm_h
31#define ___VBox_disasm_h
32
33#include <VBox/cdefs.h>
34#include <VBox/types.h>
35#include <VBox/disopcode.h>
36
37#if defined(__L4ENV__)
38#include <setjmp.h>
39#endif
40
41__BEGIN_DECLS
42
43
44/** CPU mode flags (DISCPUSTATE::mode).
45 * @{
46 */
47typedef enum
48{
49 CPUMODE_16BIT = 1,
50 CPUMODE_32BIT = 2,
51 CPUMODE_64BIT = 3,
52 /** hack forcing the size of the enum to 32-bits. */
53 CPUMODE_MAKE_32BIT_HACK = 0x7fffffff
54} DISCPUMODE;
55/** @} */
56
57/** Prefix byte flags
58 * @{
59 */
60#define PREFIX_NONE 0
61/** non-default address size. */
62#define PREFIX_ADDRSIZE RT_BIT(0)
63/** non-default operand size. */
64#define PREFIX_OPSIZE RT_BIT(1)
65/** lock prefix. */
66#define PREFIX_LOCK RT_BIT(2)
67/** segment prefix. */
68#define PREFIX_SEG RT_BIT(3)
69/** rep(e) prefix (not a prefix, but we'll treat is as one). */
70#define PREFIX_REP RT_BIT(4)
71/** rep(e) prefix (not a prefix, but we'll treat is as one). */
72#define PREFIX_REPNE RT_BIT(5)
73/** REX prefix (64 bits) */
74#define PREFIX_REX RT_BIT(6)
75/** @} */
76
77/** 64 bits prefix byte flags
78 * @{
79 */
80#define PREFIX_REX_OP_2_FLAGS(a) (a - OP_PARM_REX_START)
81#define PREFIX_REX_FLAGS PREFIX_REX_OP_2_FLAGS(OP_PARM_REX)
82#define PREFIX_REX_FLAGS_B PREFIX_REX_OP_2_FLAGS(OP_PARM_REX_B)
83#define PREFIX_REX_FLAGS_X PREFIX_REX_OP_2_FLAGS(OP_PARM_REX_X)
84#define PREFIX_REX_FLAGS_XB PREFIX_REX_OP_2_FLAGS(OP_PARM_REX_XB)
85#define PREFIX_REX_FLAGS_R PREFIX_REX_OP_2_FLAGS(OP_PARM_REX_R)
86#define PREFIX_REX_FLAGS_RB PREFIX_REX_OP_2_FLAGS(OP_PARM_REX_RB)
87#define PREFIX_REX_FLAGS_RX PREFIX_REX_OP_2_FLAGS(OP_PARM_REX_RX)
88#define PREFIX_REX_FLAGS_RXB PREFIX_REX_OP_2_FLAGS(OP_PARM_REX_RXB)
89#define PREFIX_REX_FLAGS_W PREFIX_REX_OP_2_FLAGS(OP_PARM_REX_W)
90#define PREFIX_REX_FLAGS_WB PREFIX_REX_OP_2_FLAGS(OP_PARM_REX_WB)
91#define PREFIX_REX_FLAGS_WX PREFIX_REX_OP_2_FLAGS(OP_PARM_REX_WX)
92#define PREFIX_REX_FLAGS_WXB PREFIX_REX_OP_2_FLAGS(OP_PARM_REX_WXB)
93#define PREFIX_REX_FLAGS_WR PREFIX_REX_OP_2_FLAGS(OP_PARM_REX_WR)
94#define PREFIX_REX_FLAGS_WRB PREFIX_REX_OP_2_FLAGS(OP_PARM_REX_WRB)
95#define PREFIX_REX_FLAGS_WRX PREFIX_REX_OP_2_FLAGS(OP_PARM_REX_WRX)
96#define PREFIX_REX_FLAGS_WRXB PREFIX_REX_OP_2_FLAGS(OP_PARM_REX_WRXB)
97/** @} */
98
99/**
100 * Operand type.
101 */
102#define OPTYPE_INVALID RT_BIT(0)
103#define OPTYPE_HARMLESS RT_BIT(1)
104#define OPTYPE_CONTROLFLOW RT_BIT(2)
105#define OPTYPE_POTENTIALLY_DANGEROUS RT_BIT(3)
106#define OPTYPE_DANGEROUS RT_BIT(4)
107#define OPTYPE_PORTIO RT_BIT(5)
108#define OPTYPE_PRIVILEGED RT_BIT(6)
109#define OPTYPE_PRIVILEGED_NOTRAP RT_BIT(7)
110#define OPTYPE_UNCOND_CONTROLFLOW RT_BIT(8)
111#define OPTYPE_RELATIVE_CONTROLFLOW RT_BIT(9)
112#define OPTYPE_COND_CONTROLFLOW RT_BIT(10)
113#define OPTYPE_INTERRUPT RT_BIT(11)
114#define OPTYPE_ILLEGAL RT_BIT(12)
115#define OPTYPE_RRM_DANGEROUS RT_BIT(14) /**< Some additional dangerouse ones when recompiling raw r0. */
116#define OPTYPE_RRM_DANGEROUS_16 RT_BIT(15) /**< Some additional dangerouse ones when recompiling 16-bit raw r0. */
117#define OPTYPE_RRM_MASK (OPTYPE_RRM_DANGEROUS | OPTYPE_RRM_DANGEROUS_16)
118#define OPTYPE_INHIBIT_IRQS RT_BIT(16) /**< Will or can inhibit irqs (sti, pop ss, mov ss) */
119#define OPTYPE_PORTIO_READ RT_BIT(17)
120#define OPTYPE_PORTIO_WRITE RT_BIT(18)
121#define OPTYPE_INVALID_64 RT_BIT(19) /**< Invalid in 64 bits mode */
122#define OPTYPE_ONLY_64 RT_BIT(20) /**< Only valid in 64 bits mode */
123#define OPTYPE_DEFAULT_64_OP_SIZE RT_BIT(21) /**< Default 64 bits operand size */
124#define OPTYPE_FORCED_64_OP_SIZE RT_BIT(22) /**< Forced 64 bits operand size; regardless of prefix bytes */
125#define OPTYPE_REXB_EXTENDS_OPREG RT_BIT(23) /**< REX.B extends the register field in the opcode byte */
126#define OPTYPE_ALL (0xffffffff)
127
128/** Parameter usage flags.
129 * @{
130 */
131#define USE_BASE RT_BIT_64(0)
132#define USE_INDEX RT_BIT_64(1)
133#define USE_SCALE RT_BIT_64(2)
134#define USE_REG_GEN8 RT_BIT_64(3)
135#define USE_REG_GEN16 RT_BIT_64(4)
136#define USE_REG_GEN32 RT_BIT_64(5)
137#define USE_REG_GEN64 RT_BIT_64(6)
138#define USE_REG_FP RT_BIT_64(7)
139#define USE_REG_MMX RT_BIT_64(8)
140#define USE_REG_XMM RT_BIT_64(9)
141#define USE_REG_CR RT_BIT_64(10)
142#define USE_REG_DBG RT_BIT_64(11)
143#define USE_REG_SEG RT_BIT_64(12)
144#define USE_REG_TEST RT_BIT_64(13)
145#define USE_DISPLACEMENT8 RT_BIT_64(14)
146#define USE_DISPLACEMENT16 RT_BIT_64(15)
147#define USE_DISPLACEMENT32 RT_BIT_64(16)
148#define USE_DISPLACEMENT64 RT_BIT_64(17)
149#define USE_RIPDISPLACEMENT32 RT_BIT_64(18)
150#define USE_IMMEDIATE8 RT_BIT_64(19)
151#define USE_IMMEDIATE8_REL RT_BIT_64(20)
152#define USE_IMMEDIATE16 RT_BIT_64(21)
153#define USE_IMMEDIATE16_REL RT_BIT_64(22)
154#define USE_IMMEDIATE32 RT_BIT_64(23)
155#define USE_IMMEDIATE32_REL RT_BIT_64(24)
156#define USE_IMMEDIATE64 RT_BIT_64(25)
157#define USE_IMMEDIATE64_REL RT_BIT_64(26)
158#define USE_IMMEDIATE_ADDR_0_32 RT_BIT_64(27)
159#define USE_IMMEDIATE_ADDR_16_32 RT_BIT_64(28)
160#define USE_IMMEDIATE_ADDR_0_16 RT_BIT_64(29)
161#define USE_IMMEDIATE_ADDR_16_16 RT_BIT_64(30)
162/** DS:ESI */
163#define USE_POINTER_DS_BASED RT_BIT_64(31)
164/** ES:EDI */
165#define USE_POINTER_ES_BASED RT_BIT_64(32)
166#define USE_IMMEDIATE16_SX8 RT_BIT_64(33)
167#define USE_IMMEDIATE32_SX8 RT_BIT_64(34)
168
169#define USE_IMMEDIATE (USE_IMMEDIATE8|USE_IMMEDIATE16|USE_IMMEDIATE32|USE_IMMEDIATE64|USE_IMMEDIATE8_REL|USE_IMMEDIATE16_REL|USE_IMMEDIATE32_REL|USE_IMMEDIATE64_REL|USE_IMMEDIATE_ADDR_0_32|USE_IMMEDIATE_ADDR_16_32|USE_IMMEDIATE_ADDR_0_16|USE_IMMEDIATE_ADDR_16_16|USE_IMMEDIATE16_SX8|USE_IMMEDIATE32_SX8)
170
171#define DIS_IS_EFFECTIVE_ADDR(flags) !!((flags) & (USE_BASE|USE_INDEX|USE_DISPLACEMENT32|USE_DISPLACEMENT16|USE_DISPLACEMENT8|USE_RIPDISPLACEMENT32))
172/** @} */
173
174/** index in {"RAX", "RCX", "RDX", "RBX", "RSP", "RBP", "RSI", "RDI", "R8", "R9", "R10", "R11", "R12", "R13", "R14", "R15"}
175 * @{
176 */
177#define USE_REG_RAX 0
178#define USE_REG_RCX 1
179#define USE_REG_RDX 2
180#define USE_REG_RBX 3
181#define USE_REG_RSP 4
182#define USE_REG_RBP 5
183#define USE_REG_RSI 6
184#define USE_REG_RDI 7
185#define USE_REG_R8 8
186#define USE_REG_R9 9
187#define USE_REG_R10 10
188#define USE_REG_R11 11
189#define USE_REG_R12 12
190#define USE_REG_R13 13
191#define USE_REG_R14 14
192#define USE_REG_R15 15
193/** @} */
194
195/** index in {"EAX", "ECX", "EDX", "EBX", "ESP", "EBP", "ESI", "EDI"}
196 * @{
197 */
198#define USE_REG_EAX 0
199#define USE_REG_ECX 1
200#define USE_REG_EDX 2
201#define USE_REG_EBX 3
202#define USE_REG_ESP 4
203#define USE_REG_EBP 5
204#define USE_REG_ESI 6
205#define USE_REG_EDI 7
206/** @} */
207/** index in {"AX", "CX", "DX", "BX", "SP", "BP", "SI", "DI"}
208 * @{
209 */
210#define USE_REG_AX 0
211#define USE_REG_CX 1
212#define USE_REG_DX 2
213#define USE_REG_BX 3
214#define USE_REG_SP 4
215#define USE_REG_BP 5
216#define USE_REG_SI 6
217#define USE_REG_DI 7
218/** @} */
219
220/** index in {"AL", "CL", "DL", "BL", "AH", "CH", "DH", "BH"}
221 * @{
222 */
223#define USE_REG_AL 0
224#define USE_REG_CL 1
225#define USE_REG_DL 2
226#define USE_REG_BL 3
227#define USE_REG_AH 4
228#define USE_REG_CH 5
229#define USE_REG_DH 6
230#define USE_REG_BH 7
231/** @} */
232
233/** index in {ES, CS, SS, DS, FS, GS}
234 * @{
235 */
236typedef enum
237{
238 DIS_SELREG_ES = 0,
239 DIS_SELREG_CS = 1,
240 DIS_SELREG_SS = 2,
241 DIS_SELREG_DS = 3,
242 DIS_SELREG_FS = 4,
243 DIS_SELREG_GS = 5,
244 /** The usual 32-bit paranoia. */
245 DIS_SEGREG_32BIT_HACK = 0x7fffffff
246} DIS_SELREG;
247/** @} */
248
249#define USE_REG_FP0 0
250#define USE_REG_FP1 1
251#define USE_REG_FP2 2
252#define USE_REG_FP3 3
253#define USE_REG_FP4 4
254#define USE_REG_FP5 5
255#define USE_REG_FP6 6
256#define USE_REG_FP7 7
257
258#define USE_REG_CR0 0
259#define USE_REG_CR1 1
260#define USE_REG_CR2 2
261#define USE_REG_CR3 3
262#define USE_REG_CR4 4
263
264#define USE_REG_DR0 0
265#define USE_REG_DR1 1
266#define USE_REG_DR2 2
267#define USE_REG_DR3 3
268#define USE_REG_DR4 4
269#define USE_REG_DR5 5
270#define USE_REG_DR6 6
271#define USE_REG_DR7 7
272
273#define USE_REG_MMX0 0
274#define USE_REG_MMX1 1
275#define USE_REG_MMX2 2
276#define USE_REG_MMX3 3
277#define USE_REG_MMX4 4
278#define USE_REG_MMX5 5
279#define USE_REG_MMX6 6
280#define USE_REG_MMX7 7
281
282#define USE_REG_XMM0 0
283#define USE_REG_XMM1 1
284#define USE_REG_XMM2 2
285#define USE_REG_XMM3 3
286#define USE_REG_XMM4 4
287#define USE_REG_XMM5 5
288#define USE_REG_XMM6 6
289#define USE_REG_XMM7 7
290
291/** Used by DISQueryParamVal & EMIQueryParamVal
292 * @{
293 */
294#define PARAM_VAL8 RT_BIT(0)
295#define PARAM_VAL16 RT_BIT(1)
296#define PARAM_VAL32 RT_BIT(2)
297#define PARAM_VAL64 RT_BIT(3)
298#define PARAM_VALFARPTR16 RT_BIT(4)
299#define PARAM_VALFARPTR32 RT_BIT(5)
300
301#define PARMTYPE_REGISTER 1
302#define PARMTYPE_ADDRESS 2
303#define PARMTYPE_IMMEDIATE 3
304
305typedef struct
306{
307 uint32_t type;
308 uint32_t size;
309 uint64_t flags;
310
311 union
312 {
313 uint8_t val8;
314 uint16_t val16;
315 uint32_t val32;
316 uint64_t val64;
317
318 struct
319 {
320 uint16_t sel;
321 uint32_t offset;
322 } farptr;
323 } val;
324
325} OP_PARAMVAL;
326/** Pointer to opcode parameter value. */
327typedef OP_PARAMVAL *POP_PARAMVAL;
328
329typedef enum
330{
331 PARAM_DEST,
332 PARAM_SOURCE
333} PARAM_TYPE;
334
335/** @} */
336
337/**
338 * Operand Parameter.
339 */
340typedef struct _OP_PARAMETER
341{
342 /** @todo switch param and parval and move disp64 and flags up here with the other 64-bit vars to get more natural alignment and save space. */
343 int param;
344 uint64_t parval;
345#ifndef DIS_SEPARATE_FORMATTER
346 char szParam[32];
347#endif
348
349 int32_t disp8, disp16, disp32;
350 uint32_t size;
351
352 int64_t disp64;
353 uint64_t flags;
354
355 union
356 {
357 uint32_t reg_gen;
358 /** ST(0) - ST(7) */
359 uint32_t reg_fp;
360 /** MMX0 - MMX7 */
361 uint32_t reg_mmx;
362 /** XMM0 - XMM7 */
363 uint32_t reg_xmm;
364 /** {ES, CS, SS, DS, FS, GS} */
365 DIS_SELREG reg_seg;
366 /** TR0-TR7 (?) */
367 uint32_t reg_test;
368 /** CR0-CR4 */
369 uint32_t reg_ctrl;
370 /** DR0-DR7 */
371 uint32_t reg_dbg;
372 } base;
373 union
374 {
375 uint32_t reg_gen;
376 } index;
377
378 /** 2, 4 or 8. */
379 uint32_t scale;
380
381} OP_PARAMETER;
382/** Pointer to opcode parameter. */
383typedef OP_PARAMETER *POP_PARAMETER;
384/** Pointer to opcode parameter. */
385typedef const OP_PARAMETER *PCOP_PARAMETER;
386
387
388struct _OPCODE;
389/** Pointer to opcode. */
390typedef struct _OPCODE *POPCODE;
391/** Pointer to const opcode. */
392typedef const struct _OPCODE *PCOPCODE;
393
394typedef DECLCALLBACK(int) FN_DIS_READBYTES(RTUINTPTR pSrc, uint8_t *pDest, unsigned size, void *pvUserdata);
395typedef FN_DIS_READBYTES *PFN_DIS_READBYTES;
396
397/* forward decl */
398struct _DISCPUSTATE;
399/** Pointer to the disassembler CPU state. */
400typedef struct _DISCPUSTATE *PDISCPUSTATE;
401
402/** Parser callback.
403 * @remark no DECLCALLBACK() here because it's considered to be internal (really, I'm too lazy to update all the functions). */
404typedef unsigned FNDISPARSE(RTUINTPTR pu8CodeBlock, PCOPCODE pOp, POP_PARAMETER pParam, PDISCPUSTATE pCpu);
405typedef FNDISPARSE *PFNDISPARSE;
406
407typedef struct _DISCPUSTATE
408{
409 /* Global setting */
410 DISCPUMODE mode;
411
412 /* Per instruction prefix settings */
413 uint32_t prefix;
414 /** segment prefix value. */
415 DIS_SELREG enmPrefixSeg;
416 /** rex prefix value (64 bits only */
417 uint32_t prefix_rex;
418 /** addressing mode (16 or 32 bits). (CPUMODE_*) */
419 DISCPUMODE addrmode;
420 /** operand mode (16 or 32 bits). (CPUMODE_*) */
421 DISCPUMODE opmode;
422
423 OP_PARAMETER param1;
424 OP_PARAMETER param2;
425 OP_PARAMETER param3;
426
427 /** ModRM fields. */
428 union
429 {
430 /* Bitfield view */
431 struct
432 {
433 unsigned Rm : 4;
434 unsigned Reg : 4;
435 unsigned Mod : 2;
436 } Bits;
437 /* unsigned view */
438 unsigned u;
439 } ModRM;
440
441 /** SIB fields. */
442 union
443 {
444 /* Bitfield view */
445 struct
446 {
447 unsigned Base : 4;
448 unsigned Index : 4;
449 unsigned Scale : 2;
450 } Bits;
451 /* unsigned view */
452 unsigned u;
453 } SIB;
454
455 int32_t disp;
456
457 /** First opcode byte of instruction. */
458 uint8_t opcode;
459 /** Last prefix byte (for SSE2 extension tables) */
460 uint8_t lastprefix;
461 RTUINTPTR opaddr;
462 uint32_t opsize;
463#ifndef DIS_CORE_ONLY
464 /** Opcode format string for current instruction. */
465 const char *pszOpcode;
466#endif
467
468 /** Internal: pointer to disassembly function table */
469 PFNDISPARSE *pfnDisasmFnTable;
470 /** Internal: instruction filter */
471 uint32_t uFilter;
472
473 /** Pointer to the current instruction. */
474 PCOPCODE pCurInstr;
475
476 void *apvUserData[3];
477
478 /** Optional read function */
479 PFN_DIS_READBYTES pfnReadBytes;
480#ifdef __L4ENV__
481 jmp_buf *pJumpBuffer;
482#endif /* __L4ENV__ */
483} DISCPUSTATE;
484
485/** Pointer to a const disassembler CPU state. */
486typedef DISCPUSTATE const *PCDISCPUSTATE;
487
488/** Opcode. */
489#pragma pack(4)
490typedef struct _OPCODE
491{
492#ifndef DIS_CORE_ONLY
493 const char *pszOpcode;
494#endif
495 uint8_t idxParse1;
496 uint8_t idxParse2;
497 uint8_t idxParse3;
498 uint16_t opcode;
499 uint16_t param1;
500 uint16_t param2;
501 uint16_t param3;
502
503 unsigned optype;
504} OPCODE;
505#pragma pack()
506
507
508/**
509 * Disassembles a code block.
510 *
511 * @returns VBox error code
512 * @param pCpu Pointer to cpu structure which have DISCPUSTATE::mode
513 * set correctly.
514 * @param pvCodeBlock Pointer to the strunction to disassemble.
515 * @param cbMax Maximum number of bytes to disassemble.
516 * @param pcbSize Where to store the size of the instruction.
517 * NULL is allowed.
518 *
519 *
520 * @todo Define output callback.
521 * @todo Using signed integers as sizes is a bit odd. There are still
522 * some GCC warnings about mixing signed and unsigend integers.
523 * @todo Need to extend this interface to include a code address so we
524 * can dissassemble GC code. Perhaps a new function is better...
525 * @remark cbMax isn't respected as a boundry. DISInstr() will read beyond cbMax.
526 * This means *pcbSize >= cbMax sometimes.
527 */
528DISDECL(int) DISBlock(PDISCPUSTATE pCpu, RTUINTPTR pvCodeBlock, unsigned cbMax, unsigned *pSize);
529
530/**
531 * Disassembles one instruction
532 *
533 * @returns VBox error code
534 * @param pCpu Pointer to cpu structure which have DISCPUSTATE::mode
535 * set correctly.
536 * @param pu8Instruction Pointer to the instrunction to disassemble.
537 * @param u32EipOffset Offset to add to instruction address to get the real virtual address
538 * @param pcbSize Where to store the size of the instruction.
539 * NULL is allowed.
540 * @param pszOutput Storage for disassembled instruction
541 *
542 * @todo Define output callback.
543 */
544DISDECL(int) DISInstr(PDISCPUSTATE pCpu, RTUINTPTR pu8Instruction, unsigned u32EipOffset, unsigned *pcbSize, char *pszOutput);
545
546/**
547 * Disassembles one instruction
548 *
549 * @returns VBox error code
550 * @param pCpu Pointer to cpu structure which have DISCPUSTATE::mode
551 * set correctly.
552 * @param pu8Instruction Pointer to the strunction to disassemble.
553 * @param u32EipOffset Offset to add to instruction address to get the real virtual address
554 * @param pcbSize Where to store the size of the instruction.
555 * NULL is allowed.
556 * @param pszOutput Storage for disassembled instruction
557 * @param uFilter Instruction type filter
558 *
559 * @todo Define output callback.
560 */
561DISDECL(int) DISInstrEx(PDISCPUSTATE pCpu, RTUINTPTR pu8Instruction, uint32_t u32EipOffset, uint32_t *pcbSize,
562 char *pszOutput, unsigned uFilter);
563
564/**
565 * Parses one instruction.
566 * The result is found in pCpu.
567 *
568 * @returns VBox error code
569 * @param pCpu Pointer to cpu structure which has DISCPUSTATE::mode set correctly.
570 * @param InstructionAddr Pointer to the instruction to parse.
571 * @param pcbInstruction Where to store the size of the instruction.
572 * NULL is allowed.
573 */
574DISDECL(int) DISCoreOne(PDISCPUSTATE pCpu, RTUINTPTR InstructionAddr, unsigned *pcbInstruction);
575
576/**
577 * Parses one guest instruction.
578 * The result is found in pCpu and pcbInstruction.
579 *
580 * @returns VBox status code.
581 * @param InstructionAddr Address of the instruction to decode. What this means
582 * is left to the pfnReadBytes function.
583 * @param enmCpuMode The CPU mode. CPUMODE_32BIT, CPUMODE_16BIT, or CPUMODE_64BIT.
584 * @param pfnReadBytes Callback for reading instruction bytes.
585 * @param pvUser User argument for the instruction reader. (Ends up in apvUserData[0].)
586 * @param pCpu Pointer to cpu structure. Will be initialized.
587 * @param pcbInstruction Where to store the size of the instruction.
588 * NULL is allowed.
589 */
590DISDECL(int) DISCoreOneEx(RTUINTPTR InstructionAddr, DISCPUMODE enmCpuMode, PFN_DIS_READBYTES pfnReadBytes, void *pvUser,
591 PDISCPUSTATE pCpu, unsigned *pcbInstruction);
592
593DISDECL(int) DISGetParamSize(PDISCPUSTATE pCpu, POP_PARAMETER pParam);
594DISDECL(DIS_SELREG) DISDetectSegReg(PDISCPUSTATE pCpu, POP_PARAMETER pParam);
595DISDECL(uint8_t) DISQuerySegPrefixByte(PDISCPUSTATE pCpu);
596
597/**
598 * Returns the value of the parameter in pParam
599 *
600 * @returns VBox error code
601 * @param pCtx Exception structure pointer
602 * @param pCpu Pointer to cpu structure which have DISCPUSTATE::mode
603 * set correctly.
604 * @param pParam Pointer to the parameter to parse
605 * @param pParamVal Pointer to parameter value (OUT)
606 * @param parmtype Parameter type
607 *
608 * @note Currently doesn't handle FPU/XMM/MMX/3DNow! parameters correctly!!
609 *
610 */
611DISDECL(int) DISQueryParamVal(PCPUMCTXCORE pCtx, PDISCPUSTATE pCpu, POP_PARAMETER pParam, POP_PARAMVAL pParamVal, PARAM_TYPE parmtype);
612DISDECL(int) DISQueryParamRegPtr(PCPUMCTXCORE pCtx, PDISCPUSTATE pCpu, POP_PARAMETER pParam, void **ppReg, size_t *pcbSize);
613
614DISDECL(int) DISFetchReg8(PCPUMCTXCORE pCtx, unsigned reg8, uint8_t *pVal);
615DISDECL(int) DISFetchReg16(PCPUMCTXCORE pCtx, unsigned reg16, uint16_t *pVal);
616DISDECL(int) DISFetchReg32(PCPUMCTXCORE pCtx, unsigned reg32, uint32_t *pVal);
617DISDECL(int) DISFetchReg64(PCPUMCTXCORE pCtx, unsigned reg64, uint64_t *pVal);
618DISDECL(int) DISFetchRegSeg(PCPUMCTXCORE pCtx, DIS_SELREG sel, RTSEL *pVal);
619DISDECL(int) DISFetchRegSegEx(PCPUMCTXCORE pCtx, DIS_SELREG sel, RTSEL *pVal, PCPUMSELREGHID *ppSelHidReg);
620DISDECL(int) DISWriteReg8(PCPUMCTXCORE pRegFrame, unsigned reg8, uint8_t val8);
621DISDECL(int) DISWriteReg16(PCPUMCTXCORE pRegFrame, unsigned reg32, uint16_t val16);
622DISDECL(int) DISWriteReg32(PCPUMCTXCORE pRegFrame, unsigned reg32, uint32_t val32);
623DISDECL(int) DISWriteReg64(PCPUMCTXCORE pRegFrame, unsigned reg64, uint64_t val64);
624DISDECL(int) DISWriteRegSeg(PCPUMCTXCORE pCtx, DIS_SELREG sel, RTSEL val);
625DISDECL(int) DISPtrReg8(PCPUMCTXCORE pCtx, unsigned reg8, uint8_t **ppReg);
626DISDECL(int) DISPtrReg16(PCPUMCTXCORE pCtx, unsigned reg16, uint16_t **ppReg);
627DISDECL(int) DISPtrReg32(PCPUMCTXCORE pCtx, unsigned reg32, uint32_t **ppReg);
628DISDECL(int) DISPtrReg64(PCPUMCTXCORE pCtx, unsigned reg64, uint64_t **ppReg);
629
630
631/**
632 * Try resolve an address into a symbol name.
633 *
634 * For use with DISFormatYasmEx(), DISFormatMasmEx() and DISFormatGasEx().
635 *
636 * @returns VBox status code.
637 * @retval VINF_SUCCESS on success, pszBuf contains the full symbol name.
638 * @retval VINF_BUFFER_OVERFLOW if pszBuf is too small the symbol name. The
639 * content of pszBuf is truncated and zero terminated.
640 * @retval VERR_SYMBOL_NOT_FOUND if no matching symbol was found for the address.
641 *
642 * @param pCpu Pointer to the disassembler CPU state.
643 * @param u32Sel The selector value. Use DIS_FMT_SEL_IS_REG, DIS_FMT_SEL_GET_VALUE,
644 * DIS_FMT_SEL_GET_REG to access this.
645 * @param uAddress The segment address.
646 * @param pszBuf Where to store the symbol name
647 * @param cchBuf The size of the buffer.
648 * @param poff If not a perfect match, then this is where the offset from the return
649 * symbol to the specified address is returned.
650 * @param pvUser The user argument.
651 */
652typedef DECLCALLBACK(int) FNDISGETSYMBOL(PCDISCPUSTATE pCpu, uint32_t u32Sel, RTUINTPTR uAddress, char *pszBuf, size_t cchBuf, RTINTPTR *poff, void *pvUser);
653/** Pointer to a FNDISGETSYMBOL(). */
654typedef FNDISGETSYMBOL *PFNDISGETSYMBOL;
655
656/**
657 * Checks if the FNDISGETSYMBOL argument u32Sel is a register or not.
658 */
659#define DIS_FMT_SEL_IS_REG(u32Sel) ( !!((u32Sel) & RT_BIT(31)) )
660
661/**
662 * Extracts the selector value from the FNDISGETSYMBOL argument u32Sel.
663 * @returns Selector value.
664 */
665#define DIS_FMT_SEL_GET_VALUE(u32Sel) ( (RTSEL)(u32Sel) )
666
667/**
668 * Extracts the register number from the FNDISGETSYMBOL argument u32Sel.
669 * @returns USE_REG_CS, USE_REG_SS, USE_REG_DS, USE_REG_ES, USE_REG_FS or USE_REG_FS.
670 */
671#define DIS_FMT_SEL_GET_REG(u32Sel) ( ((u32Sel) >> 16) & 0xf )
672
673/** @internal */
674#define DIS_FMT_SEL_FROM_REG(uReg) ( ((uReg) << 16) | RT_BIT(31) | 0xffff )
675/** @internal */
676#define DIS_FMT_SEL_FROM_VALUE(Sel) ( (Sel) & 0xffff )
677
678
679/** @name Flags for use with DISFormatYasmEx(), DISFormatMasmEx() and DISFormatGasEx().
680 * @{
681 */
682/** Put the address to the right. */
683#define DIS_FMT_FLAGS_ADDR_RIGHT RT_BIT_32(0)
684/** Put the address to the left. */
685#define DIS_FMT_FLAGS_ADDR_LEFT RT_BIT_32(1)
686/** Put the address in comments.
687 * For some assemblers this implies placing it to the right. */
688#define DIS_FMT_FLAGS_ADDR_COMMENT RT_BIT_32(2)
689/** Put the instruction bytes to the right of the disassembly. */
690#define DIS_FMT_FLAGS_BYTES_RIGHT RT_BIT_32(3)
691/** Put the instruction bytes to the left of the disassembly. */
692#define DIS_FMT_FLAGS_BYTES_LEFT RT_BIT_32(4)
693/** Put the instruction bytes in comments.
694 * For some assemblers this implies placing the bytes to the right. */
695#define DIS_FMT_FLAGS_BYTES_COMMENT RT_BIT_32(5)
696/** Put the bytes in square brackets. */
697#define DIS_FMT_FLAGS_BYTES_BRACKETS RT_BIT_32(6)
698/** Put spaces between the bytes. */
699#define DIS_FMT_FLAGS_BYTES_SPACED RT_BIT_32(7)
700/** Display the relative +/- offset of branch instructions that uses relative addresses,
701 * and put the target address in parenthesis. */
702#define DIS_FMT_FLAGS_RELATIVE_BRANCH RT_BIT_32(8)
703/** Strict assembly. The assembly should, when ever possible, make the
704 * assembler reproduce the exact same binary. (Refers to the yasm
705 * strict keyword.) */
706#define DIS_FMT_FLAGS_STRICT RT_BIT_32(9)
707/** Checks if the given flags are a valid combination. */
708#define DIS_FMT_FLAGS_IS_VALID(fFlags) \
709 ( !((fFlags) & ~UINT32_C(0x000003ff)) \
710 && ((fFlags) & (DIS_FMT_FLAGS_ADDR_RIGHT | DIS_FMT_FLAGS_ADDR_LEFT)) != (DIS_FMT_FLAGS_ADDR_RIGHT | DIS_FMT_FLAGS_ADDR_LEFT) \
711 && ( !((fFlags) & DIS_FMT_FLAGS_ADDR_COMMENT) \
712 || (fFlags & (DIS_FMT_FLAGS_ADDR_RIGHT | DIS_FMT_FLAGS_ADDR_LEFT)) ) \
713 && ((fFlags) & (DIS_FMT_FLAGS_BYTES_RIGHT | DIS_FMT_FLAGS_BYTES_LEFT)) != (DIS_FMT_FLAGS_BYTES_RIGHT | DIS_FMT_FLAGS_BYTES_LEFT) \
714 && ( !((fFlags) & (DIS_FMT_FLAGS_BYTES_COMMENT | DIS_FMT_FLAGS_BYTES_BRACKETS)) \
715 || (fFlags & (DIS_FMT_FLAGS_BYTES_RIGHT | DIS_FMT_FLAGS_BYTES_LEFT)) ) \
716 )
717/** @} */
718
719DISDECL(size_t) DISFormatYasm( PCDISCPUSTATE pCpu, char *pszBuf, size_t cchBuf);
720DISDECL(size_t) DISFormatYasmEx(PCDISCPUSTATE pCpu, char *pszBuf, size_t cchBuf, uint32_t fFlags, PFNDISGETSYMBOL pfnGetSymbol, void *pvUser);
721DISDECL(size_t) DISFormatMasm( PCDISCPUSTATE pCpu, char *pszBuf, size_t cchBuf);
722DISDECL(size_t) DISFormatMasmEx(PCDISCPUSTATE pCpu, char *pszBuf, size_t cchBuf, uint32_t fFlags, PFNDISGETSYMBOL pfnGetSymbol, void *pvUser);
723DISDECL(size_t) DISFormatGas( PCDISCPUSTATE pCpu, char *pszBuf, size_t cchBuf);
724DISDECL(size_t) DISFormatGasEx( PCDISCPUSTATE pCpu, char *pszBuf, size_t cchBuf, uint32_t fFlags, PFNDISGETSYMBOL pfnGetSymbol, void *pvUser);
725
726/** @todo DISAnnotate(PCDISCPUSTATE pCpu, char *pszBuf, size_t cchBuf, register reader, memory reader); */
727
728
729__END_DECLS
730
731#endif
732
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