VirtualBox

source: vbox/trunk/include/VBox/dis.h@ 41668

Last change on this file since 41668 was 41668, checked in by vboxsync, 13 years ago

DIS,DIS-users: Drop the operand/parameter formatting during instruction parsing. The desired formatter can do this afterwards if desired. Should save time + size. (DISCPUSTATE is now 256 bytes here on 64-bit linux, was ~406 yesterday.)
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File size: 27.1 KB
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1/** @file
2 * DIS - The VirtualBox Disassembler.
3 */
4
5/*
6 * Copyright (C) 2006-2012 Oracle Corporation
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * The contents of this file may alternatively be used under the terms
17 * of the Common Development and Distribution License Version 1.0
18 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19 * VirtualBox OSE distribution, in which case the provisions of the
20 * CDDL are applicable instead of those of the GPL.
21 *
22 * You may elect to license modified versions of this file under the
23 * terms and conditions of either the GPL or the CDDL or both.
24 */
25
26#ifndef ___VBox_disasm_h
27#define ___VBox_disasm_h
28
29#include <VBox/cdefs.h>
30#include <VBox/types.h>
31#include <VBox/disopcode.h>
32
33
34RT_C_DECLS_BEGIN
35
36
37/** CPU mode flags (DISCPUSTATE::mode).
38 * @{
39 */
40typedef enum
41{
42 CPUMODE_16BIT = 1,
43 CPUMODE_32BIT = 2,
44 CPUMODE_64BIT = 3,
45 /** hack forcing the size of the enum to 32-bits. */
46 CPUMODE_MAKE_32BIT_HACK = 0x7fffffff
47} DISCPUMODE;
48/** @} */
49
50/** Prefix byte flags
51 * @{
52 */
53#define PREFIX_NONE 0
54/** non-default address size. */
55#define PREFIX_ADDRSIZE RT_BIT(0)
56/** non-default operand size. */
57#define PREFIX_OPSIZE RT_BIT(1)
58/** lock prefix. */
59#define PREFIX_LOCK RT_BIT(2)
60/** segment prefix. */
61#define PREFIX_SEG RT_BIT(3)
62/** rep(e) prefix (not a prefix, but we'll treat is as one). */
63#define PREFIX_REP RT_BIT(4)
64/** rep(e) prefix (not a prefix, but we'll treat is as one). */
65#define PREFIX_REPNE RT_BIT(5)
66/** REX prefix (64 bits) */
67#define PREFIX_REX RT_BIT(6)
68/** @} */
69
70/** 64 bits prefix byte flags
71 * @{
72 */
73#define PREFIX_REX_OP_2_FLAGS(a) (a - OP_PARM_REX_START)
74#define PREFIX_REX_FLAGS PREFIX_REX_OP_2_FLAGS(OP_PARM_REX)
75#define PREFIX_REX_FLAGS_B PREFIX_REX_OP_2_FLAGS(OP_PARM_REX_B)
76#define PREFIX_REX_FLAGS_X PREFIX_REX_OP_2_FLAGS(OP_PARM_REX_X)
77#define PREFIX_REX_FLAGS_XB PREFIX_REX_OP_2_FLAGS(OP_PARM_REX_XB)
78#define PREFIX_REX_FLAGS_R PREFIX_REX_OP_2_FLAGS(OP_PARM_REX_R)
79#define PREFIX_REX_FLAGS_RB PREFIX_REX_OP_2_FLAGS(OP_PARM_REX_RB)
80#define PREFIX_REX_FLAGS_RX PREFIX_REX_OP_2_FLAGS(OP_PARM_REX_RX)
81#define PREFIX_REX_FLAGS_RXB PREFIX_REX_OP_2_FLAGS(OP_PARM_REX_RXB)
82#define PREFIX_REX_FLAGS_W PREFIX_REX_OP_2_FLAGS(OP_PARM_REX_W)
83#define PREFIX_REX_FLAGS_WB PREFIX_REX_OP_2_FLAGS(OP_PARM_REX_WB)
84#define PREFIX_REX_FLAGS_WX PREFIX_REX_OP_2_FLAGS(OP_PARM_REX_WX)
85#define PREFIX_REX_FLAGS_WXB PREFIX_REX_OP_2_FLAGS(OP_PARM_REX_WXB)
86#define PREFIX_REX_FLAGS_WR PREFIX_REX_OP_2_FLAGS(OP_PARM_REX_WR)
87#define PREFIX_REX_FLAGS_WRB PREFIX_REX_OP_2_FLAGS(OP_PARM_REX_WRB)
88#define PREFIX_REX_FLAGS_WRX PREFIX_REX_OP_2_FLAGS(OP_PARM_REX_WRX)
89#define PREFIX_REX_FLAGS_WRXB PREFIX_REX_OP_2_FLAGS(OP_PARM_REX_WRXB)
90/** @} */
91
92/**
93 * Operand type.
94 */
95#define OPTYPE_INVALID RT_BIT(0)
96#define OPTYPE_HARMLESS RT_BIT(1)
97#define OPTYPE_CONTROLFLOW RT_BIT(2)
98#define OPTYPE_POTENTIALLY_DANGEROUS RT_BIT(3)
99#define OPTYPE_DANGEROUS RT_BIT(4)
100#define OPTYPE_PORTIO RT_BIT(5)
101#define OPTYPE_PRIVILEGED RT_BIT(6)
102#define OPTYPE_PRIVILEGED_NOTRAP RT_BIT(7)
103#define OPTYPE_UNCOND_CONTROLFLOW RT_BIT(8)
104#define OPTYPE_RELATIVE_CONTROLFLOW RT_BIT(9)
105#define OPTYPE_COND_CONTROLFLOW RT_BIT(10)
106#define OPTYPE_INTERRUPT RT_BIT(11)
107#define OPTYPE_ILLEGAL RT_BIT(12)
108#define OPTYPE_RRM_DANGEROUS RT_BIT(14) /**< Some additional dangerous ones when recompiling raw r0. */
109#define OPTYPE_RRM_DANGEROUS_16 RT_BIT(15) /**< Some additional dangerous ones when recompiling 16-bit raw r0. */
110#define OPTYPE_RRM_MASK (OPTYPE_RRM_DANGEROUS | OPTYPE_RRM_DANGEROUS_16)
111#define OPTYPE_INHIBIT_IRQS RT_BIT(16) /**< Will or can inhibit irqs (sti, pop ss, mov ss) */
112#define OPTYPE_PORTIO_READ RT_BIT(17)
113#define OPTYPE_PORTIO_WRITE RT_BIT(18)
114#define OPTYPE_INVALID_64 RT_BIT(19) /**< Invalid in 64 bits mode */
115#define OPTYPE_ONLY_64 RT_BIT(20) /**< Only valid in 64 bits mode */
116#define OPTYPE_DEFAULT_64_OP_SIZE RT_BIT(21) /**< Default 64 bits operand size */
117#define OPTYPE_FORCED_64_OP_SIZE RT_BIT(22) /**< Forced 64 bits operand size; regardless of prefix bytes */
118#define OPTYPE_REXB_EXTENDS_OPREG RT_BIT(23) /**< REX.B extends the register field in the opcode byte */
119#define OPTYPE_MOD_FIXED_11 RT_BIT(24) /**< modrm.mod is always 11b */
120#define OPTYPE_FORCED_32_OP_SIZE_X86 RT_BIT(25) /**< Forced 32 bits operand size; regardless of prefix bytes (only in 16 & 32 bits mode!) */
121#define OPTYPE_ALL (0xffffffff)
122
123/** Parameter usage flags.
124 * @{
125 */
126#define USE_BASE RT_BIT_64(0)
127#define USE_INDEX RT_BIT_64(1)
128#define USE_SCALE RT_BIT_64(2)
129#define USE_REG_GEN8 RT_BIT_64(3)
130#define USE_REG_GEN16 RT_BIT_64(4)
131#define USE_REG_GEN32 RT_BIT_64(5)
132#define USE_REG_GEN64 RT_BIT_64(6)
133#define USE_REG_FP RT_BIT_64(7)
134#define USE_REG_MMX RT_BIT_64(8)
135#define USE_REG_XMM RT_BIT_64(9)
136#define USE_REG_CR RT_BIT_64(10)
137#define USE_REG_DBG RT_BIT_64(11)
138#define USE_REG_SEG RT_BIT_64(12)
139#define USE_REG_TEST RT_BIT_64(13)
140#define USE_DISPLACEMENT8 RT_BIT_64(14)
141#define USE_DISPLACEMENT16 RT_BIT_64(15)
142#define USE_DISPLACEMENT32 RT_BIT_64(16)
143#define USE_DISPLACEMENT64 RT_BIT_64(17)
144#define USE_RIPDISPLACEMENT32 RT_BIT_64(18)
145#define USE_IMMEDIATE8 RT_BIT_64(19)
146#define USE_IMMEDIATE8_REL RT_BIT_64(20)
147#define USE_IMMEDIATE16 RT_BIT_64(21)
148#define USE_IMMEDIATE16_REL RT_BIT_64(22)
149#define USE_IMMEDIATE32 RT_BIT_64(23)
150#define USE_IMMEDIATE32_REL RT_BIT_64(24)
151#define USE_IMMEDIATE64 RT_BIT_64(25)
152#define USE_IMMEDIATE64_REL RT_BIT_64(26)
153#define USE_IMMEDIATE_ADDR_0_32 RT_BIT_64(27)
154#define USE_IMMEDIATE_ADDR_16_32 RT_BIT_64(28)
155#define USE_IMMEDIATE_ADDR_0_16 RT_BIT_64(29)
156#define USE_IMMEDIATE_ADDR_16_16 RT_BIT_64(30)
157/** DS:ESI */
158#define USE_POINTER_DS_BASED RT_BIT_64(31)
159/** ES:EDI */
160#define USE_POINTER_ES_BASED RT_BIT_64(32)
161#define USE_IMMEDIATE16_SX8 RT_BIT_64(33)
162#define USE_IMMEDIATE32_SX8 RT_BIT_64(34)
163#define USE_IMMEDIATE64_SX8 RT_BIT_64(36)
164
165#define USE_IMMEDIATE (USE_IMMEDIATE8|USE_IMMEDIATE16|USE_IMMEDIATE32|USE_IMMEDIATE64|USE_IMMEDIATE8_REL|USE_IMMEDIATE16_REL|USE_IMMEDIATE32_REL|USE_IMMEDIATE64_REL|USE_IMMEDIATE_ADDR_0_32|USE_IMMEDIATE_ADDR_16_32|USE_IMMEDIATE_ADDR_0_16|USE_IMMEDIATE_ADDR_16_16|USE_IMMEDIATE16_SX8|USE_IMMEDIATE32_SX8|USE_IMMEDIATE64_SX8)
166
167#define DIS_IS_EFFECTIVE_ADDR(flags) !!((flags) & (USE_BASE|USE_INDEX|USE_DISPLACEMENT32|USE_DISPLACEMENT64|USE_DISPLACEMENT16|USE_DISPLACEMENT8|USE_RIPDISPLACEMENT32))
168/** @} */
169
170/** index in {"RAX", "RCX", "RDX", "RBX", "RSP", "RBP", "RSI", "RDI", "R8", "R9", "R10", "R11", "R12", "R13", "R14", "R15"}
171 * @{
172 */
173#define USE_REG_RAX 0
174#define USE_REG_RCX 1
175#define USE_REG_RDX 2
176#define USE_REG_RBX 3
177#define USE_REG_RSP 4
178#define USE_REG_RBP 5
179#define USE_REG_RSI 6
180#define USE_REG_RDI 7
181#define USE_REG_R8 8
182#define USE_REG_R9 9
183#define USE_REG_R10 10
184#define USE_REG_R11 11
185#define USE_REG_R12 12
186#define USE_REG_R13 13
187#define USE_REG_R14 14
188#define USE_REG_R15 15
189/** @} */
190
191/** index in {"EAX", "ECX", "EDX", "EBX", "ESP", "EBP", "ESI", "EDI", "R8D", "R9D", "R10D", "R11D", "R12D", "R13D", "R14D", "R15D"}
192 * @{
193 */
194#define USE_REG_EAX 0
195#define USE_REG_ECX 1
196#define USE_REG_EDX 2
197#define USE_REG_EBX 3
198#define USE_REG_ESP 4
199#define USE_REG_EBP 5
200#define USE_REG_ESI 6
201#define USE_REG_EDI 7
202#define USE_REG_R8D 8
203#define USE_REG_R9D 9
204#define USE_REG_R10D 10
205#define USE_REG_R11D 11
206#define USE_REG_R12D 12
207#define USE_REG_R13D 13
208#define USE_REG_R14D 14
209#define USE_REG_R15D 15
210
211/** @} */
212/** index in {"AX", "CX", "DX", "BX", "SP", "BP", "SI", "DI", "R8W", "R9W", "R10W", "R11W", "R12W", "R13W", "R14W", "R15W"}
213 * @{
214 */
215#define USE_REG_AX 0
216#define USE_REG_CX 1
217#define USE_REG_DX 2
218#define USE_REG_BX 3
219#define USE_REG_SP 4
220#define USE_REG_BP 5
221#define USE_REG_SI 6
222#define USE_REG_DI 7
223#define USE_REG_R8W 8
224#define USE_REG_R9W 9
225#define USE_REG_R10W 10
226#define USE_REG_R11W 11
227#define USE_REG_R12W 12
228#define USE_REG_R13W 13
229#define USE_REG_R14W 14
230#define USE_REG_R15W 15
231/** @} */
232
233/** index in {"AL", "CL", "DL", "BL", "AH", "CH", "DH", "BH", "R8B", "R9B", "R10B", "R11B", "R12B", "R13B", "R14B", "R15B", "SPL", "BPL", "SIL", "DIL"}
234 * @{
235 */
236#define USE_REG_AL 0
237#define USE_REG_CL 1
238#define USE_REG_DL 2
239#define USE_REG_BL 3
240#define USE_REG_AH 4
241#define USE_REG_CH 5
242#define USE_REG_DH 6
243#define USE_REG_BH 7
244#define USE_REG_R8B 8
245#define USE_REG_R9B 9
246#define USE_REG_R10B 10
247#define USE_REG_R11B 11
248#define USE_REG_R12B 12
249#define USE_REG_R13B 13
250#define USE_REG_R14B 14
251#define USE_REG_R15B 15
252#define USE_REG_SPL 16
253#define USE_REG_BPL 17
254#define USE_REG_SIL 18
255#define USE_REG_DIL 19
256
257/** @} */
258
259/** index in {ES, CS, SS, DS, FS, GS}
260 * @{
261 */
262typedef enum
263{
264 DIS_SELREG_ES = 0,
265 DIS_SELREG_CS = 1,
266 DIS_SELREG_SS = 2,
267 DIS_SELREG_DS = 3,
268 DIS_SELREG_FS = 4,
269 DIS_SELREG_GS = 5,
270 /** The usual 32-bit paranoia. */
271 DIS_SEGREG_32BIT_HACK = 0x7fffffff
272} DIS_SELREG;
273/** @} */
274
275#define USE_REG_FP0 0
276#define USE_REG_FP1 1
277#define USE_REG_FP2 2
278#define USE_REG_FP3 3
279#define USE_REG_FP4 4
280#define USE_REG_FP5 5
281#define USE_REG_FP6 6
282#define USE_REG_FP7 7
283
284#define USE_REG_CR0 0
285#define USE_REG_CR1 1
286#define USE_REG_CR2 2
287#define USE_REG_CR3 3
288#define USE_REG_CR4 4
289#define USE_REG_CR8 8
290
291#define USE_REG_DR0 0
292#define USE_REG_DR1 1
293#define USE_REG_DR2 2
294#define USE_REG_DR3 3
295#define USE_REG_DR4 4
296#define USE_REG_DR5 5
297#define USE_REG_DR6 6
298#define USE_REG_DR7 7
299
300#define USE_REG_MMX0 0
301#define USE_REG_MMX1 1
302#define USE_REG_MMX2 2
303#define USE_REG_MMX3 3
304#define USE_REG_MMX4 4
305#define USE_REG_MMX5 5
306#define USE_REG_MMX6 6
307#define USE_REG_MMX7 7
308
309#define USE_REG_XMM0 0
310#define USE_REG_XMM1 1
311#define USE_REG_XMM2 2
312#define USE_REG_XMM3 3
313#define USE_REG_XMM4 4
314#define USE_REG_XMM5 5
315#define USE_REG_XMM6 6
316#define USE_REG_XMM7 7
317
318/** Used by DISQueryParamVal & EMIQueryParamVal
319 * @{
320 */
321#define PARAM_VAL8 RT_BIT(0)
322#define PARAM_VAL16 RT_BIT(1)
323#define PARAM_VAL32 RT_BIT(2)
324#define PARAM_VAL64 RT_BIT(3)
325#define PARAM_VALFARPTR16 RT_BIT(4)
326#define PARAM_VALFARPTR32 RT_BIT(5)
327
328#define PARMTYPE_REGISTER 1
329#define PARMTYPE_ADDRESS 2
330#define PARMTYPE_IMMEDIATE 3
331
332typedef struct
333{
334 uint32_t type;
335 uint32_t size;
336 uint64_t flags;
337
338 union
339 {
340 uint8_t val8;
341 uint16_t val16;
342 uint32_t val32;
343 uint64_t val64;
344
345 struct
346 {
347 uint16_t sel;
348 uint32_t offset;
349 } farptr;
350 } val;
351
352} OP_PARAMVAL;
353/** Pointer to opcode parameter value. */
354typedef OP_PARAMVAL *POP_PARAMVAL;
355
356typedef enum
357{
358 PARAM_DEST,
359 PARAM_SOURCE
360} PARAM_TYPE;
361
362/** @} */
363
364/**
365 * Operand Parameter.
366 */
367typedef struct OP_PARAMETER
368{
369 uint64_t parval;
370 uint64_t flags;
371 union
372 {
373 int64_t i64;
374 int32_t i32;
375 int32_t i16;
376 int32_t i8;
377 uint64_t u64;
378 uint32_t u32;
379 uint32_t u16;
380 uint32_t u8;
381 } uDisp;
382 int32_t param;
383
384 union
385 {
386 uint32_t reg_gen;
387 /** ST(0) - ST(7) */
388 uint32_t reg_fp;
389 /** MMX0 - MMX7 */
390 uint32_t reg_mmx;
391 /** XMM0 - XMM7 */
392 uint32_t reg_xmm;
393 /** {ES, CS, SS, DS, FS, GS} */
394 DIS_SELREG reg_seg;
395 /** TR0-TR7 (?) */
396 uint32_t reg_test;
397 /** CR0-CR4 */
398 uint32_t reg_ctrl;
399 /** DR0-DR7 */
400 uint32_t reg_dbg;
401 } base;
402 union
403 {
404 uint32_t reg_gen;
405 } index;
406
407 /** 2, 4 or 8. */
408 uint8_t scale;
409 /** Parameter size. */
410 uint8_t cb;
411} OP_PARAMETER;
412/** Pointer to opcode parameter. */
413typedef OP_PARAMETER *POP_PARAMETER;
414/** Pointer to opcode parameter. */
415typedef const OP_PARAMETER *PCOP_PARAMETER;
416
417
418/** Pointer to opcode. */
419typedef struct OPCODE *POPCODE;
420/** Pointer to const opcode. */
421typedef const struct OPCODE *PCOPCODE;
422
423/**
424 * Callback for reading opcode bytes.
425 *
426 * @param pDisState Pointer to the CPU state. The primary user argument
427 * can be retrived from DISCPUSTATE::apvUserData[0]. If
428 * more is required these can be passed in the
429 * subsequent slots.
430 * @param pbDst Pointer to output buffer.
431 * @param uSrcAddr The address to start reading at.
432 * @param cbToRead The number of bytes to read.
433 */
434typedef DECLCALLBACK(int) FNDISREADBYTES(PDISCPUSTATE pDisState, uint8_t *pbDst, RTUINTPTR uSrcAddr, uint32_t cbToRead);
435/** Pointer to a opcode byte reader. */
436typedef FNDISREADBYTES *PFNDISREADBYTES;
437
438/** Parser callback.
439 * @remark no DECLCALLBACK() here because it's considered to be internal (really, I'm too lazy to update all the functions). */
440typedef unsigned FNDISPARSE(RTUINTPTR pu8CodeBlock, PCOPCODE pOp, POP_PARAMETER pParam, PDISCPUSTATE pCpu);
441typedef FNDISPARSE *PFNDISPARSE;
442
443typedef struct DISCPUSTATE
444{
445 /** Global setting. */
446 DISCPUMODE mode;
447
448 /** Per instruction prefix settings. */
449 uint32_t prefix; /**< @todo change to uint8_t */
450 /** segment prefix value. */
451 DIS_SELREG enmPrefixSeg;
452 /** rex prefix value (64 bits only */
453 uint32_t prefix_rex; /**< @todo change to uint8_t */
454 /** addressing mode (16 or 32 bits). (CPUMODE_*) */
455 DISCPUMODE addrmode;
456 /** operand mode (16 or 32 bits). (CPUMODE_*) */
457 DISCPUMODE opmode;
458
459 OP_PARAMETER param1;
460 OP_PARAMETER param2;
461 OP_PARAMETER param3;
462
463 /** ModRM fields. */
464 union
465 {
466 /** Bitfield view */
467 struct
468 {
469 unsigned Rm : 4;
470 unsigned Reg : 4;
471 unsigned Mod : 2;
472 } Bits;
473 /** unsigned view */
474 unsigned u;
475 } ModRM;
476
477 /** SIB fields. */
478 union
479 {
480 /** Bitfield view */
481 struct
482 {
483 unsigned Base : 4;
484 unsigned Index : 4;
485 unsigned Scale : 2;
486 } Bits;
487 /** unsigned view */
488 unsigned u;
489 } SIB;
490 int32_t i32SibDisp;
491
492 /** The instruction size. */
493 uint32_t opsize;
494 /** The address of the instruction. */
495 RTUINTPTR uInstrAddr;
496 /** The size of the prefix bytes. */
497 uint8_t cbPrefix;
498
499 /** First opcode byte of instruction. */
500 uint8_t opcode;
501 /** Last prefix byte (for SSE2 extension tables). */
502 uint8_t lastprefix;
503 /** The instruction bytes. */
504 uint8_t abInstr[16];
505
506 /** Internal: pointer to disassembly function table */
507 PFNDISPARSE *pfnDisasmFnTable;
508 /** Internal: instruction filter */
509 uint32_t uFilter;
510 /** Return code set by a worker function like the opcode bytes readers. */
511 int32_t rc;
512
513 /** Pointer to the current instruction. */
514 PCOPCODE pCurInstr;
515#ifndef DIS_CORE_ONLY
516 /** Opcode format string for current instruction. */
517 const char *pszOpcode;
518#endif
519
520 /** Optional read function */
521 PFNDISREADBYTES pfnReadBytes;
522 /** User data slots for the read callback. The first entry is used for the
523 * pvUser argument, the rest are up for grabs.
524 * @remarks This must come last so that we can memset everything before this. */
525 void *apvUserData[3];
526} DISCPUSTATE;
527
528/** The storage padding sufficient to hold the largest DISCPUSTATE in all
529 * contexts (R3, R0 and RC). Used various places in the VMM internals. */
530#define DISCPUSTATE_PADDING_SIZE (HC_ARCH_BITS == 64 ? 0x1a0 : 0x180)
531
532/** Opcode. */
533#pragma pack(4)
534typedef struct OPCODE
535{
536#ifndef DIS_CORE_ONLY
537 const char *pszOpcode;
538#endif
539 uint8_t idxParse1;
540 uint8_t idxParse2;
541 uint8_t idxParse3;
542 uint16_t opcode;
543 uint16_t param1;
544 uint16_t param2;
545 uint16_t param3;
546
547 unsigned optype;
548} OPCODE;
549#pragma pack()
550
551
552DISDECL(int) DISInstr(RTUINTPTR uInstrAddr, DISCPUMODE enmCpuMode, PDISCPUSTATE pCpu, uint32_t *pcbInstr, char *pszOutput);
553DISDECL(int) DISInstrWithOff(PDISCPUSTATE pCpu, RTUINTPTR uInstrAddr, RTUINTPTR offRealAddr, uint32_t *pcbInstr, char *pszOutput);
554DISDECL(int) DISInstrWithReader(RTUINTPTR uInstrAddr, DISCPUMODE enmCpuMode, PFNDISREADBYTES pfnReadBytes, void *pvUser,
555 PDISCPUSTATE pCpu, uint32_t *pcbInstr, char *pszOutput);
556DISDECL(int) DISInstrEx(RTUINTPTR uInstrAddr, RTUINTPTR offRealAddr, DISCPUMODE enmCpuMode,
557 PFNDISREADBYTES pfnReadBytes, void *pvUser, uint32_t uFilter,
558 PDISCPUSTATE pCpu, uint32_t *pcbInstr, char *pszOutput);
559
560DISDECL(int) DISCoreOne(RTUINTPTR uInstrAddr, DISCPUMODE enmCpuMode, PDISCPUSTATE pCpu, uint32_t *pcbInstr);
561DISDECL(int) DISCoreOneWithReader(RTUINTPTR uInstrAddr, DISCPUMODE enmCpuMode, PFNDISREADBYTES pfnReadBytes, void *pvUser,
562 PDISCPUSTATE pCpu, uint32_t *pcbInstr);
563DISDECL(int) DISCoreOneExEx(RTUINTPTR uInstrAddr, DISCPUMODE enmCpuMode, uint32_t uFilter,
564 PFNDISREADBYTES pfnReadBytes, void *pvUser,
565 PDISCPUSTATE pCpu, uint32_t *pcbInstr);
566
567DISDECL(int) DISGetParamSize(PDISCPUSTATE pCpu, POP_PARAMETER pParam);
568DISDECL(DIS_SELREG) DISDetectSegReg(PDISCPUSTATE pCpu, POP_PARAMETER pParam);
569DISDECL(uint8_t) DISQuerySegPrefixByte(PDISCPUSTATE pCpu);
570
571DISDECL(int) DISQueryParamVal(PCPUMCTXCORE pCtx, PDISCPUSTATE pCpu, POP_PARAMETER pParam, POP_PARAMVAL pParamVal, PARAM_TYPE parmtype);
572DISDECL(int) DISQueryParamRegPtr(PCPUMCTXCORE pCtx, PDISCPUSTATE pCpu, POP_PARAMETER pParam, void **ppReg, size_t *pcbSize);
573
574DISDECL(int) DISFetchReg8(PCCPUMCTXCORE pCtx, unsigned reg8, uint8_t *pVal);
575DISDECL(int) DISFetchReg16(PCCPUMCTXCORE pCtx, unsigned reg16, uint16_t *pVal);
576DISDECL(int) DISFetchReg32(PCCPUMCTXCORE pCtx, unsigned reg32, uint32_t *pVal);
577DISDECL(int) DISFetchReg64(PCCPUMCTXCORE pCtx, unsigned reg64, uint64_t *pVal);
578DISDECL(int) DISFetchRegSeg(PCCPUMCTXCORE pCtx, DIS_SELREG sel, RTSEL *pVal);
579DISDECL(int) DISFetchRegSegEx(PCCPUMCTXCORE pCtx, DIS_SELREG sel, RTSEL *pVal, PCPUMSELREGHID *ppSelHidReg);
580DISDECL(int) DISWriteReg8(PCPUMCTXCORE pRegFrame, unsigned reg8, uint8_t val8);
581DISDECL(int) DISWriteReg16(PCPUMCTXCORE pRegFrame, unsigned reg32, uint16_t val16);
582DISDECL(int) DISWriteReg32(PCPUMCTXCORE pRegFrame, unsigned reg32, uint32_t val32);
583DISDECL(int) DISWriteReg64(PCPUMCTXCORE pRegFrame, unsigned reg64, uint64_t val64);
584DISDECL(int) DISWriteRegSeg(PCPUMCTXCORE pCtx, DIS_SELREG sel, RTSEL val);
585DISDECL(int) DISPtrReg8(PCPUMCTXCORE pCtx, unsigned reg8, uint8_t **ppReg);
586DISDECL(int) DISPtrReg16(PCPUMCTXCORE pCtx, unsigned reg16, uint16_t **ppReg);
587DISDECL(int) DISPtrReg32(PCPUMCTXCORE pCtx, unsigned reg32, uint32_t **ppReg);
588DISDECL(int) DISPtrReg64(PCPUMCTXCORE pCtx, unsigned reg64, uint64_t **ppReg);
589
590
591/**
592 * Try resolve an address into a symbol name.
593 *
594 * For use with DISFormatYasmEx(), DISFormatMasmEx() and DISFormatGasEx().
595 *
596 * @returns VBox status code.
597 * @retval VINF_SUCCESS on success, pszBuf contains the full symbol name.
598 * @retval VINF_BUFFER_OVERFLOW if pszBuf is too small the symbol name. The
599 * content of pszBuf is truncated and zero terminated.
600 * @retval VERR_SYMBOL_NOT_FOUND if no matching symbol was found for the address.
601 *
602 * @param pCpu Pointer to the disassembler CPU state.
603 * @param u32Sel The selector value. Use DIS_FMT_SEL_IS_REG, DIS_FMT_SEL_GET_VALUE,
604 * DIS_FMT_SEL_GET_REG to access this.
605 * @param uAddress The segment address.
606 * @param pszBuf Where to store the symbol name
607 * @param cchBuf The size of the buffer.
608 * @param poff If not a perfect match, then this is where the offset from the return
609 * symbol to the specified address is returned.
610 * @param pvUser The user argument.
611 */
612typedef DECLCALLBACK(int) FNDISGETSYMBOL(PCDISCPUSTATE pCpu, uint32_t u32Sel, RTUINTPTR uAddress, char *pszBuf, size_t cchBuf, RTINTPTR *poff, void *pvUser);
613/** Pointer to a FNDISGETSYMBOL(). */
614typedef FNDISGETSYMBOL *PFNDISGETSYMBOL;
615
616/**
617 * Checks if the FNDISGETSYMBOL argument u32Sel is a register or not.
618 */
619#define DIS_FMT_SEL_IS_REG(u32Sel) ( !!((u32Sel) & RT_BIT(31)) )
620
621/**
622 * Extracts the selector value from the FNDISGETSYMBOL argument u32Sel.
623 * @returns Selector value.
624 */
625#define DIS_FMT_SEL_GET_VALUE(u32Sel) ( (RTSEL)(u32Sel) )
626
627/**
628 * Extracts the register number from the FNDISGETSYMBOL argument u32Sel.
629 * @returns USE_REG_CS, USE_REG_SS, USE_REG_DS, USE_REG_ES, USE_REG_FS or USE_REG_FS.
630 */
631#define DIS_FMT_SEL_GET_REG(u32Sel) ( ((u32Sel) >> 16) & 0xf )
632
633/** @internal */
634#define DIS_FMT_SEL_FROM_REG(uReg) ( ((uReg) << 16) | RT_BIT(31) | 0xffff )
635/** @internal */
636#define DIS_FMT_SEL_FROM_VALUE(Sel) ( (Sel) & 0xffff )
637
638
639/** @name Flags for use with DISFormatYasmEx(), DISFormatMasmEx() and DISFormatGasEx().
640 * @{
641 */
642/** Put the address to the right. */
643#define DIS_FMT_FLAGS_ADDR_RIGHT RT_BIT_32(0)
644/** Put the address to the left. */
645#define DIS_FMT_FLAGS_ADDR_LEFT RT_BIT_32(1)
646/** Put the address in comments.
647 * For some assemblers this implies placing it to the right. */
648#define DIS_FMT_FLAGS_ADDR_COMMENT RT_BIT_32(2)
649/** Put the instruction bytes to the right of the disassembly. */
650#define DIS_FMT_FLAGS_BYTES_RIGHT RT_BIT_32(3)
651/** Put the instruction bytes to the left of the disassembly. */
652#define DIS_FMT_FLAGS_BYTES_LEFT RT_BIT_32(4)
653/** Put the instruction bytes in comments.
654 * For some assemblers this implies placing the bytes to the right. */
655#define DIS_FMT_FLAGS_BYTES_COMMENT RT_BIT_32(5)
656/** Put the bytes in square brackets. */
657#define DIS_FMT_FLAGS_BYTES_BRACKETS RT_BIT_32(6)
658/** Put spaces between the bytes. */
659#define DIS_FMT_FLAGS_BYTES_SPACED RT_BIT_32(7)
660/** Display the relative +/- offset of branch instructions that uses relative addresses,
661 * and put the target address in parenthesis. */
662#define DIS_FMT_FLAGS_RELATIVE_BRANCH RT_BIT_32(8)
663/** Strict assembly. The assembly should, when ever possible, make the
664 * assembler reproduce the exact same binary. (Refers to the yasm
665 * strict keyword.) */
666#define DIS_FMT_FLAGS_STRICT RT_BIT_32(9)
667/** Checks if the given flags are a valid combination. */
668#define DIS_FMT_FLAGS_IS_VALID(fFlags) \
669 ( !((fFlags) & ~UINT32_C(0x000003ff)) \
670 && ((fFlags) & (DIS_FMT_FLAGS_ADDR_RIGHT | DIS_FMT_FLAGS_ADDR_LEFT)) != (DIS_FMT_FLAGS_ADDR_RIGHT | DIS_FMT_FLAGS_ADDR_LEFT) \
671 && ( !((fFlags) & DIS_FMT_FLAGS_ADDR_COMMENT) \
672 || (fFlags & (DIS_FMT_FLAGS_ADDR_RIGHT | DIS_FMT_FLAGS_ADDR_LEFT)) ) \
673 && ((fFlags) & (DIS_FMT_FLAGS_BYTES_RIGHT | DIS_FMT_FLAGS_BYTES_LEFT)) != (DIS_FMT_FLAGS_BYTES_RIGHT | DIS_FMT_FLAGS_BYTES_LEFT) \
674 && ( !((fFlags) & (DIS_FMT_FLAGS_BYTES_COMMENT | DIS_FMT_FLAGS_BYTES_BRACKETS)) \
675 || (fFlags & (DIS_FMT_FLAGS_BYTES_RIGHT | DIS_FMT_FLAGS_BYTES_LEFT)) ) \
676 )
677/** @} */
678
679DISDECL(size_t) DISFormatYasm( PCDISCPUSTATE pCpu, char *pszBuf, size_t cchBuf);
680DISDECL(size_t) DISFormatYasmEx(PCDISCPUSTATE pCpu, char *pszBuf, size_t cchBuf, uint32_t fFlags, PFNDISGETSYMBOL pfnGetSymbol, void *pvUser);
681DISDECL(size_t) DISFormatMasm( PCDISCPUSTATE pCpu, char *pszBuf, size_t cchBuf);
682DISDECL(size_t) DISFormatMasmEx(PCDISCPUSTATE pCpu, char *pszBuf, size_t cchBuf, uint32_t fFlags, PFNDISGETSYMBOL pfnGetSymbol, void *pvUser);
683DISDECL(size_t) DISFormatGas( PCDISCPUSTATE pCpu, char *pszBuf, size_t cchBuf);
684DISDECL(size_t) DISFormatGasEx( PCDISCPUSTATE pCpu, char *pszBuf, size_t cchBuf, uint32_t fFlags, PFNDISGETSYMBOL pfnGetSymbol, void *pvUser);
685
686/** @todo DISAnnotate(PCDISCPUSTATE pCpu, char *pszBuf, size_t cchBuf, register reader, memory reader); */
687
688DISDECL(bool) DISFormatYasmIsOddEncoding(PDISCPUSTATE pCpu);
689
690
691RT_C_DECLS_END
692
693#endif
694
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