VirtualBox

source: vbox/trunk/include/VBox/dis.h@ 41727

Last change on this file since 41727 was 41727, checked in by vboxsync, 13 years ago

DIS: register macro name adjustments.
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1/** @file
2 * DIS - The VirtualBox Disassembler.
3 */
4
5/*
6 * Copyright (C) 2006-2012 Oracle Corporation
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * The contents of this file may alternatively be used under the terms
17 * of the Common Development and Distribution License Version 1.0
18 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19 * VirtualBox OSE distribution, in which case the provisions of the
20 * CDDL are applicable instead of those of the GPL.
21 *
22 * You may elect to license modified versions of this file under the
23 * terms and conditions of either the GPL or the CDDL or both.
24 */
25
26#ifndef ___VBox_dis_h
27#define ___VBox_dis_h
28
29#include <VBox/types.h>
30#include <VBox/disopcode.h>
31#include <iprt/assert.h>
32
33
34RT_C_DECLS_BEGIN
35
36
37/**
38 * CPU mode flags (DISCPUSTATE::mode).
39 */
40typedef enum DISCPUMODE
41{
42 DISCPUMODE_INVALID = 0,
43 DISCPUMODE_16BIT,
44 DISCPUMODE_32BIT,
45 DISCPUMODE_64BIT,
46 /** hack forcing the size of the enum to 32-bits. */
47 DISCPUMODE_MAKE_32BIT_HACK = 0x7fffffff
48} DISCPUMODE;
49
50/** @name Prefix byte flags (DISCPUSTATE::prefix_rex).
51 * @{
52 */
53#define DISPREFIX_NONE UINT8_C(0x00)
54/** non-default address size. */
55#define DISPREFIX_ADDRSIZE UINT8_C(0x01)
56/** non-default operand size. */
57#define DISPREFIX_OPSIZE UINT8_C(0x02)
58/** lock prefix. */
59#define DISPREFIX_LOCK UINT8_C(0x04)
60/** segment prefix. */
61#define DISPREFIX_SEG UINT8_C(0x08)
62/** rep(e) prefix (not a prefix, but we'll treat is as one). */
63#define DISPREFIX_REP UINT8_C(0x10)
64/** rep(e) prefix (not a prefix, but we'll treat is as one). */
65#define DISPREFIX_REPNE UINT8_C(0x20)
66/** REX prefix (64 bits) */
67#define DISPREFIX_REX UINT8_C(0x40)
68/** @} */
69
70/** @name 64 bits prefix byte flags (DISCPUSTATE::prefix_rex).
71 * Requires VBox/disopcode.h.
72 * @{
73 */
74#define DISPREFIX_REX_OP_2_FLAGS(a) (a - OP_PARM_REX_START)
75#define DISPREFIX_REX_FLAGS DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX)
76#define DISPREFIX_REX_FLAGS_B DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_B)
77#define DISPREFIX_REX_FLAGS_X DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_X)
78#define DISPREFIX_REX_FLAGS_XB DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_XB)
79#define DISPREFIX_REX_FLAGS_R DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_R)
80#define DISPREFIX_REX_FLAGS_RB DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_RB)
81#define DISPREFIX_REX_FLAGS_RX DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_RX)
82#define DISPREFIX_REX_FLAGS_RXB DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_RXB)
83#define DISPREFIX_REX_FLAGS_W DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_W)
84#define DISPREFIX_REX_FLAGS_WB DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_WB)
85#define DISPREFIX_REX_FLAGS_WX DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_WX)
86#define DISPREFIX_REX_FLAGS_WXB DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_WXB)
87#define DISPREFIX_REX_FLAGS_WR DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_WR)
88#define DISPREFIX_REX_FLAGS_WRB DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_WRB)
89#define DISPREFIX_REX_FLAGS_WRX DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_WRX)
90#define DISPREFIX_REX_FLAGS_WRXB DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_WRXB)
91/** @} */
92
93/** @name Operand type.
94 * @{
95 */
96#define DISOPTYPE_INVALID RT_BIT_32(0)
97#define DISOPTYPE_HARMLESS RT_BIT_32(1)
98#define DISOPTYPE_CONTROLFLOW RT_BIT_32(2)
99#define DISOPTYPE_POTENTIALLY_DANGEROUS RT_BIT_32(3)
100#define DISOPTYPE_DANGEROUS RT_BIT_32(4)
101#define DISOPTYPE_PORTIO RT_BIT_32(5)
102#define DISOPTYPE_PRIVILEGED RT_BIT_32(6)
103#define DISOPTYPE_PRIVILEGED_NOTRAP RT_BIT_32(7)
104#define DISOPTYPE_UNCOND_CONTROLFLOW RT_BIT_32(8)
105#define DISOPTYPE_RELATIVE_CONTROLFLOW RT_BIT_32(9)
106#define DISOPTYPE_COND_CONTROLFLOW RT_BIT_32(10)
107#define DISOPTYPE_INTERRUPT RT_BIT_32(11)
108#define DISOPTYPE_ILLEGAL RT_BIT_32(12)
109#define DISOPTYPE_RRM_DANGEROUS RT_BIT_32(14) /**< Some additional dangerous ones when recompiling raw r0. */
110#define DISOPTYPE_RRM_DANGEROUS_16 RT_BIT_32(15) /**< Some additional dangerous ones when recompiling 16-bit raw r0. */
111#define DISOPTYPE_RRM_MASK (DISOPTYPE_RRM_DANGEROUS | DISOPTYPE_RRM_DANGEROUS_16)
112#define DISOPTYPE_INHIBIT_IRQS RT_BIT_32(16) /**< Will or can inhibit irqs (sti, pop ss, mov ss) */
113#define DISOPTYPE_PORTIO_READ RT_BIT_32(17)
114#define DISOPTYPE_PORTIO_WRITE RT_BIT_32(18)
115#define DISOPTYPE_INVALID_64 RT_BIT_32(19) /**< Invalid in 64 bits mode */
116#define DISOPTYPE_ONLY_64 RT_BIT_32(20) /**< Only valid in 64 bits mode */
117#define DISOPTYPE_DEFAULT_64_OP_SIZE RT_BIT_32(21) /**< Default 64 bits operand size */
118#define DISOPTYPE_FORCED_64_OP_SIZE RT_BIT_32(22) /**< Forced 64 bits operand size; regardless of prefix bytes */
119#define DISOPTYPE_REXB_EXTENDS_OPREG RT_BIT_32(23) /**< REX.B extends the register field in the opcode byte */
120#define DISOPTYPE_MOD_FIXED_11 RT_BIT_32(24) /**< modrm.mod is always 11b */
121#define DISOPTYPE_FORCED_32_OP_SIZE_X86 RT_BIT_32(25) /**< Forced 32 bits operand size; regardless of prefix bytes (only in 16 & 32 bits mode!) */
122#define DISOPTYPE_ALL UINT32_C(0xffffffff)
123/** @} */
124
125/** @name Parameter usage flags.
126 * @{
127 */
128#define DISUSE_BASE RT_BIT_64(0)
129#define DISUSE_INDEX RT_BIT_64(1)
130#define DISUSE_SCALE RT_BIT_64(2)
131#define DISUSE_REG_GEN8 RT_BIT_64(3)
132#define DISUSE_REG_GEN16 RT_BIT_64(4)
133#define DISUSE_REG_GEN32 RT_BIT_64(5)
134#define DISUSE_REG_GEN64 RT_BIT_64(6)
135#define DISUSE_REG_FP RT_BIT_64(7)
136#define DISUSE_REG_MMX RT_BIT_64(8)
137#define DISUSE_REG_XMM RT_BIT_64(9)
138#define DISUSE_REG_CR RT_BIT_64(10)
139#define DISUSE_REG_DBG RT_BIT_64(11)
140#define DISUSE_REG_SEG RT_BIT_64(12)
141#define DISUSE_REG_TEST RT_BIT_64(13)
142#define DISUSE_DISPLACEMENT8 RT_BIT_64(14)
143#define DISUSE_DISPLACEMENT16 RT_BIT_64(15)
144#define DISUSE_DISPLACEMENT32 RT_BIT_64(16)
145#define DISUSE_DISPLACEMENT64 RT_BIT_64(17)
146#define DISUSE_RIPDISPLACEMENT32 RT_BIT_64(18)
147#define DISUSE_IMMEDIATE8 RT_BIT_64(19)
148#define DISUSE_IMMEDIATE8_REL RT_BIT_64(20)
149#define DISUSE_IMMEDIATE16 RT_BIT_64(21)
150#define DISUSE_IMMEDIATE16_REL RT_BIT_64(22)
151#define DISUSE_IMMEDIATE32 RT_BIT_64(23)
152#define DISUSE_IMMEDIATE32_REL RT_BIT_64(24)
153#define DISUSE_IMMEDIATE64 RT_BIT_64(25)
154#define DISUSE_IMMEDIATE64_REL RT_BIT_64(26)
155#define DISUSE_IMMEDIATE_ADDR_0_32 RT_BIT_64(27)
156#define DISUSE_IMMEDIATE_ADDR_16_32 RT_BIT_64(28)
157#define DISUSE_IMMEDIATE_ADDR_0_16 RT_BIT_64(29)
158#define DISUSE_IMMEDIATE_ADDR_16_16 RT_BIT_64(30)
159/** DS:ESI */
160#define DISUSE_POINTER_DS_BASED RT_BIT_64(31)
161/** ES:EDI */
162#define DISUSE_POINTER_ES_BASED RT_BIT_64(32)
163#define DISUSE_IMMEDIATE16_SX8 RT_BIT_64(33)
164#define DISUSE_IMMEDIATE32_SX8 RT_BIT_64(34)
165#define DISUSE_IMMEDIATE64_SX8 RT_BIT_64(36)
166
167/** Mask of immediate use flags. */
168#define DISUSE_IMMEDIATE ( DISUSE_IMMEDIATE8 \
169 | DISUSE_IMMEDIATE16 \
170 | DISUSE_IMMEDIATE32 \
171 | DISUSE_IMMEDIATE64 \
172 | DISUSE_IMMEDIATE8_REL \
173 | DISUSE_IMMEDIATE16_REL \
174 | DISUSE_IMMEDIATE32_REL \
175 | DISUSE_IMMEDIATE64_REL \
176 | DISUSE_IMMEDIATE_ADDR_0_32 \
177 | DISUSE_IMMEDIATE_ADDR_16_32 \
178 | DISUSE_IMMEDIATE_ADDR_0_16 \
179 | DISUSE_IMMEDIATE_ADDR_16_16 \
180 | DISUSE_IMMEDIATE16_SX8 \
181 | DISUSE_IMMEDIATE32_SX8 \
182 | DISUSE_IMMEDIATE64_SX8)
183/** Check if the use flags indicates an effective address. */
184#define DISUSE_IS_EFFECTIVE_ADDR(a_fUseFlags) (!!( (a_fUseFlags) \
185 & ( DISUSE_BASE \
186 | DISUSE_INDEX \
187 | DISUSE_DISPLACEMENT32 \
188 | DISUSE_DISPLACEMENT64 \
189 | DISUSE_DISPLACEMENT16 \
190 | DISUSE_DISPLACEMENT8 \
191 | DISUSE_RIPDISPLACEMENT32) ))
192/** @} */
193
194/** @name 64-bit general register indexes.
195 * This matches the AMD64 register encoding. It is found used in
196 * DISOPPARAM::base.reg_gen and DISOPPARAM::index.reg_gen.
197 * @note Safe to assume same values as the 16-bit and 32-bit general registers.
198 * @{
199 */
200#define DISGREG_RAX UINT8_C(0)
201#define DISGREG_RCX UINT8_C(1)
202#define DISGREG_RDX UINT8_C(2)
203#define DISGREG_RBX UINT8_C(3)
204#define DISGREG_RSP UINT8_C(4)
205#define DISGREG_RBP UINT8_C(5)
206#define DISGREG_RSI UINT8_C(6)
207#define DISGREG_RDI UINT8_C(7)
208#define DISGREG_R8 UINT8_C(8)
209#define DISGREG_R9 UINT8_C(9)
210#define DISGREG_R10 UINT8_C(10)
211#define DISGREG_R11 UINT8_C(11)
212#define DISGREG_R12 UINT8_C(12)
213#define DISGREG_R13 UINT8_C(13)
214#define DISGREG_R14 UINT8_C(14)
215#define DISGREG_R15 UINT8_C(15)
216/** @} */
217
218/** @name 32-bit general register indexes.
219 * This matches the AMD64 register encoding. It is found used in
220 * DISOPPARAM::base.reg_gen and DISOPPARAM::index.reg_gen.
221 * @note Safe to assume same values as the 16-bit and 64-bit general registers.
222 * @{
223 */
224#define DISGREG_EAX UINT8_C(0)
225#define DISGREG_ECX UINT8_C(1)
226#define DISGREG_EDX UINT8_C(2)
227#define DISGREG_EBX UINT8_C(3)
228#define DISGREG_ESP UINT8_C(4)
229#define DISGREG_EBP UINT8_C(5)
230#define DISGREG_ESI UINT8_C(6)
231#define DISGREG_EDI UINT8_C(7)
232#define DISGREG_R8D UINT8_C(8)
233#define DISGREG_R9D UINT8_C(9)
234#define DISGREG_R10D UINT8_C(10)
235#define DISGREG_R11D UINT8_C(11)
236#define DISGREG_R12D UINT8_C(12)
237#define DISGREG_R13D UINT8_C(13)
238#define DISGREG_R14D UINT8_C(14)
239#define DISGREG_R15D UINT8_C(15)
240/** @} */
241
242/** @name 16-bit general register indexes.
243 * This matches the AMD64 register encoding. It is found used in
244 * DISOPPARAM::base.reg_gen and DISOPPARAM::index.reg_gen.
245 * @note Safe to assume same values as the 32-bit and 64-bit general registers.
246 * @{
247 */
248#define DISGREG_AX UINT8_C(0)
249#define DISGREG_CX UINT8_C(1)
250#define DISGREG_DX UINT8_C(2)
251#define DISGREG_BX UINT8_C(3)
252#define DISGREG_SP UINT8_C(4)
253#define DISGREG_BP UINT8_C(5)
254#define DISGREG_SI UINT8_C(6)
255#define DISGREG_DI UINT8_C(7)
256#define DISGREG_R8W UINT8_C(8)
257#define DISGREG_R9W UINT8_C(9)
258#define DISGREG_R10W UINT8_C(10)
259#define DISGREG_R11W UINT8_C(11)
260#define DISGREG_R12W UINT8_C(12)
261#define DISGREG_R13W UINT8_C(13)
262#define DISGREG_R14W UINT8_C(14)
263#define DISGREG_R15W UINT8_C(15)
264/** @} */
265
266/** @name 8-bit general register indexes.
267 * This mostly (?) matches the AMD64 register encoding. It is found used in
268 * DISOPPARAM::base.reg_gen and DISOPPARAM::index.reg_gen.
269 * @{
270 */
271#define DISGREG_AL UINT8_C(0)
272#define DISGREG_CL UINT8_C(1)
273#define DISGREG_DL UINT8_C(2)
274#define DISGREG_BL UINT8_C(3)
275#define DISGREG_AH UINT8_C(4)
276#define DISGREG_CH UINT8_C(5)
277#define DISGREG_DH UINT8_C(6)
278#define DISGREG_BH UINT8_C(7)
279#define DISGREG_R8B UINT8_C(8)
280#define DISGREG_R9B UINT8_C(9)
281#define DISGREG_R10B UINT8_C(10)
282#define DISGREG_R11B UINT8_C(11)
283#define DISGREG_R12B UINT8_C(12)
284#define DISGREG_R13B UINT8_C(13)
285#define DISGREG_R14B UINT8_C(14)
286#define DISGREG_R15B UINT8_C(15)
287#define DISGREG_SPL UINT8_C(16)
288#define DISGREG_BPL UINT8_C(17)
289#define DISGREG_SIL UINT8_C(18)
290#define DISGREG_DIL UINT8_C(19)
291/** @} */
292
293/** @name Segment registerindexes.
294 * This matches the AMD64 register encoding. It is found used in
295 * DISOPPARAM::base.reg_seg.
296 * @{
297 */
298typedef enum
299{
300 DISSELREG_ES = 0,
301 DISSELREG_CS = 1,
302 DISSELREG_SS = 2,
303 DISSELREG_DS = 3,
304 DISSELREG_FS = 4,
305 DISSELREG_GS = 5,
306 /** The usual 32-bit paranoia. */
307 DIS_SEGREG_32BIT_HACK = 0x7fffffff
308} DISSELREG;
309/** @} */
310
311#define USE_REG_FP0 0
312#define USE_REG_FP1 1
313#define USE_REG_FP2 2
314#define USE_REG_FP3 3
315#define USE_REG_FP4 4
316#define USE_REG_FP5 5
317#define USE_REG_FP6 6
318#define USE_REG_FP7 7
319
320#define USE_REG_CR0 0
321#define USE_REG_CR1 1
322#define USE_REG_CR2 2
323#define USE_REG_CR3 3
324#define USE_REG_CR4 4
325#define USE_REG_CR8 8
326
327#define USE_REG_DR0 0
328#define USE_REG_DR1 1
329#define USE_REG_DR2 2
330#define USE_REG_DR3 3
331#define USE_REG_DR4 4
332#define USE_REG_DR5 5
333#define USE_REG_DR6 6
334#define USE_REG_DR7 7
335
336#define USE_REG_MMX0 0
337#define USE_REG_MMX1 1
338#define USE_REG_MMX2 2
339#define USE_REG_MMX3 3
340#define USE_REG_MMX4 4
341#define USE_REG_MMX5 5
342#define USE_REG_MMX6 6
343#define USE_REG_MMX7 7
344
345#define USE_REG_XMM0 0
346#define USE_REG_XMM1 1
347#define USE_REG_XMM2 2
348#define USE_REG_XMM3 3
349#define USE_REG_XMM4 4
350#define USE_REG_XMM5 5
351#define USE_REG_XMM6 6
352#define USE_REG_XMM7 7
353/** @todo missing XMM8-XMM15 */
354
355/** Used by DISQueryParamVal & EMIQueryParamVal
356 * @{
357 */
358#define PARAM_VAL8 RT_BIT(0)
359#define PARAM_VAL16 RT_BIT(1)
360#define PARAM_VAL32 RT_BIT(2)
361#define PARAM_VAL64 RT_BIT(3)
362#define PARAM_VALFARPTR16 RT_BIT(4)
363#define PARAM_VALFARPTR32 RT_BIT(5)
364
365#define PARMTYPE_REGISTER 1
366#define PARMTYPE_ADDRESS 2
367#define PARMTYPE_IMMEDIATE 3
368
369typedef struct
370{
371 uint32_t type;
372 uint32_t size;
373 uint64_t flags;
374
375 union
376 {
377 uint8_t val8;
378 uint16_t val16;
379 uint32_t val32;
380 uint64_t val64;
381
382 struct
383 {
384 uint16_t sel;
385 uint32_t offset;
386 } farptr;
387 } val;
388
389} OP_PARAMVAL;
390/** Pointer to opcode parameter value. */
391typedef OP_PARAMVAL *POP_PARAMVAL;
392
393typedef enum
394{
395 PARAM_DEST,
396 PARAM_SOURCE
397} PARAM_TYPE;
398
399/** @} */
400
401/**
402 * Operand Parameter.
403 */
404typedef struct DISOPPARAM
405{
406 uint64_t parval;
407 /** A combination of DISUSE_XXX. */
408 uint64_t fUse;
409 union
410 {
411 int64_t i64;
412 int32_t i32;
413 int32_t i16;
414 int32_t i8;
415 uint64_t u64;
416 uint32_t u32;
417 uint32_t u16;
418 uint32_t u8;
419 } uDisp;
420 int32_t param;
421
422 union
423 {
424 /** DISGREG_XXX. */
425 uint8_t reg_gen;
426 /** ST(0) - ST(7) */
427 uint8_t reg_fp;
428 /** MMX0 - MMX7 */
429 uint8_t reg_mmx;
430 /** XMM0 - XMM7 */
431 uint8_t reg_xmm;
432 /** {ES, CS, SS, DS, FS, GS} (DISSELREG). */
433 uint8_t reg_seg;
434 /** TR0-TR7 (?) */
435 uint8_t reg_test;
436 /** CR0-CR4 */
437 uint8_t reg_ctrl;
438 /** DR0-DR7 */
439 uint8_t reg_dbg;
440 } base;
441 union
442 {
443 /** DISGREG_XXX. */
444 uint8_t reg_gen;
445 } index;
446
447 /** 2, 4 or 8. */
448 uint8_t scale;
449 /** Parameter size. */
450 uint8_t cb;
451} DISOPPARAM;
452AssertCompileSize(DISOPPARAM, 32);
453/** Pointer to opcode parameter. */
454typedef DISOPPARAM *PDISOPPARAM;
455/** Pointer to opcode parameter. */
456typedef const DISOPPARAM *PCOP_PARAMETER;
457
458
459/** Pointer to const opcode. */
460typedef const struct DISOPCODE *PCDISOPCODE;
461
462/**
463 * Callback for reading opcode bytes.
464 *
465 * @param pDisState Pointer to the CPU state. The primary user argument
466 * can be retrived from DISCPUSTATE::apvUserData[0]. If
467 * more is required these can be passed in the
468 * subsequent slots.
469 * @param pbDst Pointer to output buffer.
470 * @param uSrcAddr The address to start reading at.
471 * @param cbToRead The number of bytes to read.
472 */
473typedef DECLCALLBACK(int) FNDISREADBYTES(PDISCPUSTATE pDisState, uint8_t *pbDst, RTUINTPTR uSrcAddr, uint32_t cbToRead);
474/** Pointer to a opcode byte reader. */
475typedef FNDISREADBYTES *PFNDISREADBYTES;
476
477/** Parser callback.
478 * @remark no DECLCALLBACK() here because it's considered to be internal (really, I'm too lazy to update all the functions). */
479typedef unsigned FNDISPARSE(RTUINTPTR pu8CodeBlock, PCDISOPCODE pOp, PDISOPPARAM pParam, PDISCPUSTATE pCpu);
480typedef FNDISPARSE *PFNDISPARSE;
481typedef PFNDISPARSE const *PCPFNDISPARSE;
482
483typedef struct DISCPUSTATE
484{
485 /* Because of apvUserData[1] and apvUserData[2], put the less frequently
486 used bits at the top for now. (Might be better off in the middle?) */
487 DISOPPARAM param3;
488 DISOPPARAM param2;
489 DISOPPARAM param1;
490
491 /* off: 0x060 (96) */
492 /** ModRM fields. */
493 union
494 {
495 /** Bitfield view */
496 struct
497 {
498 unsigned Rm : 4;
499 unsigned Reg : 4;
500 unsigned Mod : 2;
501 } Bits;
502 /** unsigned view */
503 unsigned u;
504 } ModRM;
505 /** SIB fields. */
506 union
507 {
508 /** Bitfield view */
509 struct
510 {
511 unsigned Base : 4;
512 unsigned Index : 4;
513 unsigned Scale : 2;
514 } Bits;
515 /** unsigned view */
516 unsigned u;
517 } SIB;
518 int32_t i32SibDisp;
519
520 /* off: 0x06c (108) */
521 /** The CPU mode (DISCPUMODE). */
522 uint8_t mode;
523 /** The addressing mode (DISCPUMODE). */
524 uint8_t addrmode;
525 /** The operand mode (DISCPUMODE). */
526 uint8_t opmode;
527 /** Per instruction prefix settings. */
528 uint8_t prefix;
529 /* off: 0x070 (112) */
530 /** REX prefix value (64 bits only). */
531 uint8_t prefix_rex;
532 /** Segment prefix value (DISSELREG). */
533 uint8_t idxSegPrefix;
534 /** Last prefix byte (for SSE2 extension tables). */
535 uint8_t lastprefix;
536 /** First opcode byte of instruction. */
537 uint8_t opcode;
538 /* off: 0x074 (116) */
539 /** The size of the prefix bytes. */
540 uint8_t cbPrefix;
541 /** The instruction size. */
542 uint8_t opsize;
543 uint8_t abUnused[2];
544 /* off: 0x078 (120) */
545 /** Return code set by a worker function like the opcode bytes readers. */
546 int32_t rc;
547 /** Internal: instruction filter */
548 uint32_t fFilter;
549 /* off: 0x080 (128) */
550 /** Internal: pointer to disassembly function table */
551 PCPFNDISPARSE pfnDisasmFnTable;
552#if ARCH_BITS == 32
553 uint32_t uPtrPadding1;
554#endif
555 /** Pointer to the current instruction. */
556 PCDISOPCODE pCurInstr;
557#if ARCH_BITS == 32
558 uint32_t uPtrPadding2;
559#endif
560 /* off: 0x090 (144) */
561 /** The address of the instruction. */
562 RTUINTPTR uInstrAddr;
563 /* off: 0x098 (152) */
564 /** Optional read function */
565 PFNDISREADBYTES pfnReadBytes;
566#if ARCH_BITS == 32
567 uint32_t uPadding3;
568#endif
569 /* off: 0x0a0 (160) */
570 /** The instruction bytes. */
571 uint8_t abInstr[16];
572 /* off: 0x0b0 (176) */
573 /** User data slots for the read callback. The first entry is used for the
574 * pvUser argument, the rest are up for grabs.
575 * @remarks This must come last so that we can memset everything before this. */
576 void *apvUserData[3];
577#if ARCH_BITS == 32
578 uint32_t auPadding4[3];
579#endif
580} DISCPUSTATE;
581
582
583/**
584 * Opcode descriptor.
585 */
586typedef struct DISOPCODE
587{
588#ifndef DIS_CORE_ONLY
589 const char *pszOpcode;
590#endif
591 uint8_t idxParse1;
592 uint8_t idxParse2;
593 uint8_t idxParse3;
594 uint8_t uUnused;
595 uint16_t opcode;
596 uint16_t param1;
597 uint16_t param2;
598 uint16_t param3;
599 uint32_t optype;
600} DISOPCODE;
601
602
603DISDECL(int) DISInstrToStr(void const *pvInstr, DISCPUMODE enmCpuMode,
604 PDISCPUSTATE pCpu, uint32_t *pcbInstr, char *pszOutput, size_t cbOutput);
605DISDECL(int) DISInstrToStrWithReader(RTUINTPTR uInstrAddr, DISCPUMODE enmCpuMode, PFNDISREADBYTES pfnReadBytes, void *pvUser,
606 PDISCPUSTATE pCpu, uint32_t *pcbInstr, char *pszOutput, size_t cbOutput);
607DISDECL(int) DISInstrToStrEx(RTUINTPTR uInstrAddr, DISCPUMODE enmCpuMode,
608 PFNDISREADBYTES pfnReadBytes, void *pvUser, uint32_t uFilter,
609 PDISCPUSTATE pCpu, uint32_t *pcbInstr, char *pszOutput, size_t cbOutput);
610
611DISDECL(int) DISInstr(void const *pvInstr, DISCPUMODE enmCpuMode, PDISCPUSTATE pCpu, uint32_t *pcbInstr);
612DISDECL(int) DISInstrWithReader(RTUINTPTR uInstrAddr, DISCPUMODE enmCpuMode, PFNDISREADBYTES pfnReadBytes, void *pvUser,
613 PDISCPUSTATE pCpu, uint32_t *pcbInstr);
614DISDECL(int) DISInstEx(RTUINTPTR uInstrAddr, DISCPUMODE enmCpuMode, uint32_t uFilter,
615 PFNDISREADBYTES pfnReadBytes, void *pvUser,
616 PDISCPUSTATE pCpu, uint32_t *pcbInstr);
617
618DISDECL(int) DISGetParamSize(PDISCPUSTATE pCpu, PDISOPPARAM pParam);
619DISDECL(DISSELREG) DISDetectSegReg(PDISCPUSTATE pCpu, PDISOPPARAM pParam);
620DISDECL(uint8_t) DISQuerySegPrefixByte(PDISCPUSTATE pCpu);
621
622DISDECL(int) DISQueryParamVal(PCPUMCTXCORE pCtx, PDISCPUSTATE pCpu, PDISOPPARAM pParam, POP_PARAMVAL pParamVal, PARAM_TYPE parmtype);
623DISDECL(int) DISQueryParamRegPtr(PCPUMCTXCORE pCtx, PDISCPUSTATE pCpu, PDISOPPARAM pParam, void **ppReg, size_t *pcbSize);
624
625DISDECL(int) DISFetchReg8(PCCPUMCTXCORE pCtx, unsigned reg8, uint8_t *pVal);
626DISDECL(int) DISFetchReg16(PCCPUMCTXCORE pCtx, unsigned reg16, uint16_t *pVal);
627DISDECL(int) DISFetchReg32(PCCPUMCTXCORE pCtx, unsigned reg32, uint32_t *pVal);
628DISDECL(int) DISFetchReg64(PCCPUMCTXCORE pCtx, unsigned reg64, uint64_t *pVal);
629DISDECL(int) DISFetchRegSeg(PCCPUMCTXCORE pCtx, DISSELREG sel, RTSEL *pVal);
630DISDECL(int) DISFetchRegSegEx(PCCPUMCTXCORE pCtx, DISSELREG sel, RTSEL *pVal, PCPUMSELREGHID *ppSelHidReg);
631DISDECL(int) DISWriteReg8(PCPUMCTXCORE pRegFrame, unsigned reg8, uint8_t val8);
632DISDECL(int) DISWriteReg16(PCPUMCTXCORE pRegFrame, unsigned reg32, uint16_t val16);
633DISDECL(int) DISWriteReg32(PCPUMCTXCORE pRegFrame, unsigned reg32, uint32_t val32);
634DISDECL(int) DISWriteReg64(PCPUMCTXCORE pRegFrame, unsigned reg64, uint64_t val64);
635DISDECL(int) DISWriteRegSeg(PCPUMCTXCORE pCtx, DISSELREG sel, RTSEL val);
636DISDECL(int) DISPtrReg8(PCPUMCTXCORE pCtx, unsigned reg8, uint8_t **ppReg);
637DISDECL(int) DISPtrReg16(PCPUMCTXCORE pCtx, unsigned reg16, uint16_t **ppReg);
638DISDECL(int) DISPtrReg32(PCPUMCTXCORE pCtx, unsigned reg32, uint32_t **ppReg);
639DISDECL(int) DISPtrReg64(PCPUMCTXCORE pCtx, unsigned reg64, uint64_t **ppReg);
640
641
642/**
643 * Try resolve an address into a symbol name.
644 *
645 * For use with DISFormatYasmEx(), DISFormatMasmEx() and DISFormatGasEx().
646 *
647 * @returns VBox status code.
648 * @retval VINF_SUCCESS on success, pszBuf contains the full symbol name.
649 * @retval VINF_BUFFER_OVERFLOW if pszBuf is too small the symbol name. The
650 * content of pszBuf is truncated and zero terminated.
651 * @retval VERR_SYMBOL_NOT_FOUND if no matching symbol was found for the address.
652 *
653 * @param pCpu Pointer to the disassembler CPU state.
654 * @param u32Sel The selector value. Use DIS_FMT_SEL_IS_REG, DIS_FMT_SEL_GET_VALUE,
655 * DIS_FMT_SEL_GET_REG to access this.
656 * @param uAddress The segment address.
657 * @param pszBuf Where to store the symbol name
658 * @param cchBuf The size of the buffer.
659 * @param poff If not a perfect match, then this is where the offset from the return
660 * symbol to the specified address is returned.
661 * @param pvUser The user argument.
662 */
663typedef DECLCALLBACK(int) FNDISGETSYMBOL(PCDISCPUSTATE pCpu, uint32_t u32Sel, RTUINTPTR uAddress, char *pszBuf, size_t cchBuf, RTINTPTR *poff, void *pvUser);
664/** Pointer to a FNDISGETSYMBOL(). */
665typedef FNDISGETSYMBOL *PFNDISGETSYMBOL;
666
667/**
668 * Checks if the FNDISGETSYMBOL argument u32Sel is a register or not.
669 */
670#define DIS_FMT_SEL_IS_REG(u32Sel) ( !!((u32Sel) & RT_BIT(31)) )
671
672/**
673 * Extracts the selector value from the FNDISGETSYMBOL argument u32Sel.
674 * @returns Selector value.
675 */
676#define DIS_FMT_SEL_GET_VALUE(u32Sel) ( (RTSEL)(u32Sel) )
677
678/**
679 * Extracts the register number from the FNDISGETSYMBOL argument u32Sel.
680 * @returns USE_REG_CS, USE_REG_SS, USE_REG_DS, USE_REG_ES, USE_REG_FS or USE_REG_FS.
681 */
682#define DIS_FMT_SEL_GET_REG(u32Sel) ( ((u32Sel) >> 16) & 0xf )
683
684/** @internal */
685#define DIS_FMT_SEL_FROM_REG(uReg) ( ((uReg) << 16) | RT_BIT(31) | 0xffff )
686/** @internal */
687#define DIS_FMT_SEL_FROM_VALUE(Sel) ( (Sel) & 0xffff )
688
689
690/** @name Flags for use with DISFormatYasmEx(), DISFormatMasmEx() and DISFormatGasEx().
691 * @{
692 */
693/** Put the address to the right. */
694#define DIS_FMT_FLAGS_ADDR_RIGHT RT_BIT_32(0)
695/** Put the address to the left. */
696#define DIS_FMT_FLAGS_ADDR_LEFT RT_BIT_32(1)
697/** Put the address in comments.
698 * For some assemblers this implies placing it to the right. */
699#define DIS_FMT_FLAGS_ADDR_COMMENT RT_BIT_32(2)
700/** Put the instruction bytes to the right of the disassembly. */
701#define DIS_FMT_FLAGS_BYTES_RIGHT RT_BIT_32(3)
702/** Put the instruction bytes to the left of the disassembly. */
703#define DIS_FMT_FLAGS_BYTES_LEFT RT_BIT_32(4)
704/** Put the instruction bytes in comments.
705 * For some assemblers this implies placing the bytes to the right. */
706#define DIS_FMT_FLAGS_BYTES_COMMENT RT_BIT_32(5)
707/** Put the bytes in square brackets. */
708#define DIS_FMT_FLAGS_BYTES_BRACKETS RT_BIT_32(6)
709/** Put spaces between the bytes. */
710#define DIS_FMT_FLAGS_BYTES_SPACED RT_BIT_32(7)
711/** Display the relative +/- offset of branch instructions that uses relative addresses,
712 * and put the target address in parenthesis. */
713#define DIS_FMT_FLAGS_RELATIVE_BRANCH RT_BIT_32(8)
714/** Strict assembly. The assembly should, when ever possible, make the
715 * assembler reproduce the exact same binary. (Refers to the yasm
716 * strict keyword.) */
717#define DIS_FMT_FLAGS_STRICT RT_BIT_32(9)
718/** Checks if the given flags are a valid combination. */
719#define DIS_FMT_FLAGS_IS_VALID(fFlags) \
720 ( !((fFlags) & ~UINT32_C(0x000003ff)) \
721 && ((fFlags) & (DIS_FMT_FLAGS_ADDR_RIGHT | DIS_FMT_FLAGS_ADDR_LEFT)) != (DIS_FMT_FLAGS_ADDR_RIGHT | DIS_FMT_FLAGS_ADDR_LEFT) \
722 && ( !((fFlags) & DIS_FMT_FLAGS_ADDR_COMMENT) \
723 || (fFlags & (DIS_FMT_FLAGS_ADDR_RIGHT | DIS_FMT_FLAGS_ADDR_LEFT)) ) \
724 && ((fFlags) & (DIS_FMT_FLAGS_BYTES_RIGHT | DIS_FMT_FLAGS_BYTES_LEFT)) != (DIS_FMT_FLAGS_BYTES_RIGHT | DIS_FMT_FLAGS_BYTES_LEFT) \
725 && ( !((fFlags) & (DIS_FMT_FLAGS_BYTES_COMMENT | DIS_FMT_FLAGS_BYTES_BRACKETS)) \
726 || (fFlags & (DIS_FMT_FLAGS_BYTES_RIGHT | DIS_FMT_FLAGS_BYTES_LEFT)) ) \
727 )
728/** @} */
729
730DISDECL(size_t) DISFormatYasm( PCDISCPUSTATE pCpu, char *pszBuf, size_t cchBuf);
731DISDECL(size_t) DISFormatYasmEx(PCDISCPUSTATE pCpu, char *pszBuf, size_t cchBuf, uint32_t fFlags, PFNDISGETSYMBOL pfnGetSymbol, void *pvUser);
732DISDECL(size_t) DISFormatMasm( PCDISCPUSTATE pCpu, char *pszBuf, size_t cchBuf);
733DISDECL(size_t) DISFormatMasmEx(PCDISCPUSTATE pCpu, char *pszBuf, size_t cchBuf, uint32_t fFlags, PFNDISGETSYMBOL pfnGetSymbol, void *pvUser);
734DISDECL(size_t) DISFormatGas( PCDISCPUSTATE pCpu, char *pszBuf, size_t cchBuf);
735DISDECL(size_t) DISFormatGasEx( PCDISCPUSTATE pCpu, char *pszBuf, size_t cchBuf, uint32_t fFlags, PFNDISGETSYMBOL pfnGetSymbol, void *pvUser);
736
737/** @todo DISAnnotate(PCDISCPUSTATE pCpu, char *pszBuf, size_t cchBuf, register reader, memory reader); */
738
739DISDECL(bool) DISFormatYasmIsOddEncoding(PDISCPUSTATE pCpu);
740
741
742RT_C_DECLS_END
743
744#endif
745
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