dis.h@ 46783

Last change on this file since 46783 was 42186, checked in by vboxsync, 12 years ago
SELM,DIS,CPUM,EM: Hidden selector register cleanups.
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1	/** @file
2	* DIS - The VirtualBox Disassembler.
3	*/
4
5	/*
6	* Copyright (C) 2006-2012 Oracle Corporation
7	*
8	* This file is part of VirtualBox Open Source Edition (OSE), as
9	* available from http://www.virtualbox.org. This file is free software;
10	* you can redistribute it and/or modify it under the terms of the GNU
11	* General Public License (GPL) as published by the Free Software
12	* Foundation, in version 2 as it comes in the "COPYING" file of the
13	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15	*
16	* The contents of this file may alternatively be used under the terms
17	* of the Common Development and Distribution License Version 1.0
18	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19	* VirtualBox OSE distribution, in which case the provisions of the
20	* CDDL are applicable instead of those of the GPL.
21	*
22	* You may elect to license modified versions of this file under the
23	* terms and conditions of either the GPL or the CDDL or both.
24	*/
25
26	#ifndef ___VBox_dis_h
27	#define ___VBox_dis_h
28
29	#include <VBox/types.h>
30	#include <VBox/disopcode.h>
31	#include <iprt/assert.h>
32
33
34	RT_C_DECLS_BEGIN
35
36
37	/** @name Prefix byte flags (DISSTATE::fPrefix).
38	* @{
39	*/
40	#define DISPREFIX_NONE UINT8_C(0x00)
41	/** non-default address size. */
42	#define DISPREFIX_ADDRSIZE UINT8_C(0x01)
43	/** non-default operand size. */
44	#define DISPREFIX_OPSIZE UINT8_C(0x02)
45	/** lock prefix. */
46	#define DISPREFIX_LOCK UINT8_C(0x04)
47	/** segment prefix. */
48	#define DISPREFIX_SEG UINT8_C(0x08)
49	/** rep(e) prefix (not a prefix, but we'll treat is as one). */
50	#define DISPREFIX_REP UINT8_C(0x10)
51	/** rep(e) prefix (not a prefix, but we'll treat is as one). */
52	#define DISPREFIX_REPNE UINT8_C(0x20)
53	/** REX prefix (64 bits) */
54	#define DISPREFIX_REX UINT8_C(0x40)
55	/** @} */
56
57	/** @name 64 bits prefix byte flags (DISSTATE::fRexPrefix).
58	* Requires VBox/disopcode.h.
59	* @{
60	*/
61	#define DISPREFIX_REX_OP_2_FLAGS(a) (a - OP_PARM_REX_START)
62	#define DISPREFIX_REX_FLAGS DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX)
63	#define DISPREFIX_REX_FLAGS_B DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_B)
64	#define DISPREFIX_REX_FLAGS_X DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_X)
65	#define DISPREFIX_REX_FLAGS_XB DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_XB)
66	#define DISPREFIX_REX_FLAGS_R DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_R)
67	#define DISPREFIX_REX_FLAGS_RB DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_RB)
68	#define DISPREFIX_REX_FLAGS_RX DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_RX)
69	#define DISPREFIX_REX_FLAGS_RXB DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_RXB)
70	#define DISPREFIX_REX_FLAGS_W DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_W)
71	#define DISPREFIX_REX_FLAGS_WB DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_WB)
72	#define DISPREFIX_REX_FLAGS_WX DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_WX)
73	#define DISPREFIX_REX_FLAGS_WXB DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_WXB)
74	#define DISPREFIX_REX_FLAGS_WR DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_WR)
75	#define DISPREFIX_REX_FLAGS_WRB DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_WRB)
76	#define DISPREFIX_REX_FLAGS_WRX DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_WRX)
77	#define DISPREFIX_REX_FLAGS_WRXB DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_WRXB)
78	/** @} */
79
80	/** @name Operand type (DISOPCODE::fOpType).
81	* @{
82	*/
83	#define DISOPTYPE_INVALID RT_BIT_32(0)
84	#define DISOPTYPE_HARMLESS RT_BIT_32(1)
85	#define DISOPTYPE_CONTROLFLOW RT_BIT_32(2)
86	#define DISOPTYPE_POTENTIALLY_DANGEROUS RT_BIT_32(3)
87	#define DISOPTYPE_DANGEROUS RT_BIT_32(4)
88	#define DISOPTYPE_PORTIO RT_BIT_32(5)
89	#define DISOPTYPE_PRIVILEGED RT_BIT_32(6)
90	#define DISOPTYPE_PRIVILEGED_NOTRAP RT_BIT_32(7)
91	#define DISOPTYPE_UNCOND_CONTROLFLOW RT_BIT_32(8)
92	#define DISOPTYPE_RELATIVE_CONTROLFLOW RT_BIT_32(9)
93	#define DISOPTYPE_COND_CONTROLFLOW RT_BIT_32(10)
94	#define DISOPTYPE_INTERRUPT RT_BIT_32(11)
95	#define DISOPTYPE_ILLEGAL RT_BIT_32(12)
96	#define DISOPTYPE_RRM_DANGEROUS RT_BIT_32(14) /*< Some additional dangerous ones when recompiling raw r0. /
97	#define DISOPTYPE_RRM_DANGEROUS_16 RT_BIT_32(15) /*< Some additional dangerous ones when recompiling 16-bit raw r0. /
98	#define DISOPTYPE_RRM_MASK (DISOPTYPE_RRM_DANGEROUS \| DISOPTYPE_RRM_DANGEROUS_16)
99	#define DISOPTYPE_INHIBIT_IRQS RT_BIT_32(16) /*< Will or can inhibit irqs (sti, pop ss, mov ss) /
100	#define DISOPTYPE_PORTIO_READ RT_BIT_32(17)
101	#define DISOPTYPE_PORTIO_WRITE RT_BIT_32(18)
102	#define DISOPTYPE_INVALID_64 RT_BIT_32(19) /*< Invalid in 64 bits mode /
103	#define DISOPTYPE_ONLY_64 RT_BIT_32(20) /*< Only valid in 64 bits mode /
104	#define DISOPTYPE_DEFAULT_64_OP_SIZE RT_BIT_32(21) /*< Default 64 bits operand size /
105	#define DISOPTYPE_FORCED_64_OP_SIZE RT_BIT_32(22) /*< Forced 64 bits operand size; regardless of prefix bytes /
106	#define DISOPTYPE_REXB_EXTENDS_OPREG RT_BIT_32(23) /*< REX.B extends the register field in the opcode byte /
107	#define DISOPTYPE_MOD_FIXED_11 RT_BIT_32(24) /*< modrm.mod is always 11b /
108	#define DISOPTYPE_FORCED_32_OP_SIZE_X86 RT_BIT_32(25) /*< Forced 32 bits operand size; regardless of prefix bytes (only in 16 & 32 bits mode!) /
109	#define DISOPTYPE_ALL UINT32_C(0xffffffff)
110	/** @} */
111
112	/** @name Parameter usage flags.
113	* @{
114	*/
115	#define DISUSE_BASE RT_BIT_64(0)
116	#define DISUSE_INDEX RT_BIT_64(1)
117	#define DISUSE_SCALE RT_BIT_64(2)
118	#define DISUSE_REG_GEN8 RT_BIT_64(3)
119	#define DISUSE_REG_GEN16 RT_BIT_64(4)
120	#define DISUSE_REG_GEN32 RT_BIT_64(5)
121	#define DISUSE_REG_GEN64 RT_BIT_64(6)
122	#define DISUSE_REG_FP RT_BIT_64(7)
123	#define DISUSE_REG_MMX RT_BIT_64(8)
124	#define DISUSE_REG_XMM RT_BIT_64(9)
125	#define DISUSE_REG_CR RT_BIT_64(10)
126	#define DISUSE_REG_DBG RT_BIT_64(11)
127	#define DISUSE_REG_SEG RT_BIT_64(12)
128	#define DISUSE_REG_TEST RT_BIT_64(13)
129	#define DISUSE_DISPLACEMENT8 RT_BIT_64(14)
130	#define DISUSE_DISPLACEMENT16 RT_BIT_64(15)
131	#define DISUSE_DISPLACEMENT32 RT_BIT_64(16)
132	#define DISUSE_DISPLACEMENT64 RT_BIT_64(17)
133	#define DISUSE_RIPDISPLACEMENT32 RT_BIT_64(18)
134	#define DISUSE_IMMEDIATE8 RT_BIT_64(19)
135	#define DISUSE_IMMEDIATE8_REL RT_BIT_64(20)
136	#define DISUSE_IMMEDIATE16 RT_BIT_64(21)
137	#define DISUSE_IMMEDIATE16_REL RT_BIT_64(22)
138	#define DISUSE_IMMEDIATE32 RT_BIT_64(23)
139	#define DISUSE_IMMEDIATE32_REL RT_BIT_64(24)
140	#define DISUSE_IMMEDIATE64 RT_BIT_64(25)
141	#define DISUSE_IMMEDIATE64_REL RT_BIT_64(26)
142	#define DISUSE_IMMEDIATE_ADDR_0_32 RT_BIT_64(27)
143	#define DISUSE_IMMEDIATE_ADDR_16_32 RT_BIT_64(28)
144	#define DISUSE_IMMEDIATE_ADDR_0_16 RT_BIT_64(29)
145	#define DISUSE_IMMEDIATE_ADDR_16_16 RT_BIT_64(30)
146	/** DS:ESI */
147	#define DISUSE_POINTER_DS_BASED RT_BIT_64(31)
148	/** ES:EDI */
149	#define DISUSE_POINTER_ES_BASED RT_BIT_64(32)
150	#define DISUSE_IMMEDIATE16_SX8 RT_BIT_64(33)
151	#define DISUSE_IMMEDIATE32_SX8 RT_BIT_64(34)
152	#define DISUSE_IMMEDIATE64_SX8 RT_BIT_64(36)
153
154	/** Mask of immediate use flags. */
155	#define DISUSE_IMMEDIATE ( DISUSE_IMMEDIATE8 \
156	\| DISUSE_IMMEDIATE16 \
157	\| DISUSE_IMMEDIATE32 \
158	\| DISUSE_IMMEDIATE64 \
159	\| DISUSE_IMMEDIATE8_REL \
160	\| DISUSE_IMMEDIATE16_REL \
161	\| DISUSE_IMMEDIATE32_REL \
162	\| DISUSE_IMMEDIATE64_REL \
163	\| DISUSE_IMMEDIATE_ADDR_0_32 \
164	\| DISUSE_IMMEDIATE_ADDR_16_32 \
165	\| DISUSE_IMMEDIATE_ADDR_0_16 \
166	\| DISUSE_IMMEDIATE_ADDR_16_16 \
167	\| DISUSE_IMMEDIATE16_SX8 \
168	\| DISUSE_IMMEDIATE32_SX8 \
169	\| DISUSE_IMMEDIATE64_SX8)
170	/** Check if the use flags indicates an effective address. */
171	#define DISUSE_IS_EFFECTIVE_ADDR(a_fUseFlags) (!!( (a_fUseFlags) \
172	& ( DISUSE_BASE \
173	\| DISUSE_INDEX \
174	\| DISUSE_DISPLACEMENT32 \
175	\| DISUSE_DISPLACEMENT64 \
176	\| DISUSE_DISPLACEMENT16 \
177	\| DISUSE_DISPLACEMENT8 \
178	\| DISUSE_RIPDISPLACEMENT32) ))
179	/** @} */
180
181	/** @name 64-bit general register indexes.
182	* This matches the AMD64 register encoding. It is found used in
183	* DISOPPARAM::Base.idxGenReg and DISOPPARAM::Index.idxGenReg.
184	* @note Safe to assume same values as the 16-bit and 32-bit general registers.
185	* @{
186	*/
187	#define DISGREG_RAX UINT8_C(0)
188	#define DISGREG_RCX UINT8_C(1)
189	#define DISGREG_RDX UINT8_C(2)
190	#define DISGREG_RBX UINT8_C(3)
191	#define DISGREG_RSP UINT8_C(4)
192	#define DISGREG_RBP UINT8_C(5)
193	#define DISGREG_RSI UINT8_C(6)
194	#define DISGREG_RDI UINT8_C(7)
195	#define DISGREG_R8 UINT8_C(8)
196	#define DISGREG_R9 UINT8_C(9)
197	#define DISGREG_R10 UINT8_C(10)
198	#define DISGREG_R11 UINT8_C(11)
199	#define DISGREG_R12 UINT8_C(12)
200	#define DISGREG_R13 UINT8_C(13)
201	#define DISGREG_R14 UINT8_C(14)
202	#define DISGREG_R15 UINT8_C(15)
203	/** @} */
204
205	/** @name 32-bit general register indexes.
206	* This matches the AMD64 register encoding. It is found used in
207	* DISOPPARAM::Base.idxGenReg and DISOPPARAM::Index.idxGenReg.
208	* @note Safe to assume same values as the 16-bit and 64-bit general registers.
209	* @{
210	*/
211	#define DISGREG_EAX UINT8_C(0)
212	#define DISGREG_ECX UINT8_C(1)
213	#define DISGREG_EDX UINT8_C(2)
214	#define DISGREG_EBX UINT8_C(3)
215	#define DISGREG_ESP UINT8_C(4)
216	#define DISGREG_EBP UINT8_C(5)
217	#define DISGREG_ESI UINT8_C(6)
218	#define DISGREG_EDI UINT8_C(7)
219	#define DISGREG_R8D UINT8_C(8)
220	#define DISGREG_R9D UINT8_C(9)
221	#define DISGREG_R10D UINT8_C(10)
222	#define DISGREG_R11D UINT8_C(11)
223	#define DISGREG_R12D UINT8_C(12)
224	#define DISGREG_R13D UINT8_C(13)
225	#define DISGREG_R14D UINT8_C(14)
226	#define DISGREG_R15D UINT8_C(15)
227	/** @} */
228
229	/** @name 16-bit general register indexes.
230	* This matches the AMD64 register encoding. It is found used in
231	* DISOPPARAM::Base.idxGenReg and DISOPPARAM::Index.idxGenReg.
232	* @note Safe to assume same values as the 32-bit and 64-bit general registers.
233	* @{
234	*/
235	#define DISGREG_AX UINT8_C(0)
236	#define DISGREG_CX UINT8_C(1)
237	#define DISGREG_DX UINT8_C(2)
238	#define DISGREG_BX UINT8_C(3)
239	#define DISGREG_SP UINT8_C(4)
240	#define DISGREG_BP UINT8_C(5)
241	#define DISGREG_SI UINT8_C(6)
242	#define DISGREG_DI UINT8_C(7)
243	#define DISGREG_R8W UINT8_C(8)
244	#define DISGREG_R9W UINT8_C(9)
245	#define DISGREG_R10W UINT8_C(10)
246	#define DISGREG_R11W UINT8_C(11)
247	#define DISGREG_R12W UINT8_C(12)
248	#define DISGREG_R13W UINT8_C(13)
249	#define DISGREG_R14W UINT8_C(14)
250	#define DISGREG_R15W UINT8_C(15)
251	/** @} */
252
253	/** @name 8-bit general register indexes.
254	* This mostly (?) matches the AMD64 register encoding. It is found used in
255	* DISOPPARAM::Base.idxGenReg and DISOPPARAM::Index.idxGenReg.
256	* @{
257	*/
258	#define DISGREG_AL UINT8_C(0)
259	#define DISGREG_CL UINT8_C(1)
260	#define DISGREG_DL UINT8_C(2)
261	#define DISGREG_BL UINT8_C(3)
262	#define DISGREG_AH UINT8_C(4)
263	#define DISGREG_CH UINT8_C(5)
264	#define DISGREG_DH UINT8_C(6)
265	#define DISGREG_BH UINT8_C(7)
266	#define DISGREG_R8B UINT8_C(8)
267	#define DISGREG_R9B UINT8_C(9)
268	#define DISGREG_R10B UINT8_C(10)
269	#define DISGREG_R11B UINT8_C(11)
270	#define DISGREG_R12B UINT8_C(12)
271	#define DISGREG_R13B UINT8_C(13)
272	#define DISGREG_R14B UINT8_C(14)
273	#define DISGREG_R15B UINT8_C(15)
274	#define DISGREG_SPL UINT8_C(16)
275	#define DISGREG_BPL UINT8_C(17)
276	#define DISGREG_SIL UINT8_C(18)
277	#define DISGREG_DIL UINT8_C(19)
278	/** @} */
279
280	/** @name Segment registerindexes.
281	* This matches the AMD64 register encoding. It is found used in
282	* DISOPPARAM::Base.idxSegReg.
283	* @{
284	*/
285	typedef enum
286	{
287	DISSELREG_ES = 0,
288	DISSELREG_CS = 1,
289	DISSELREG_SS = 2,
290	DISSELREG_DS = 3,
291	DISSELREG_FS = 4,
292	DISSELREG_GS = 5,
293	/** End of the valid register index values. */
294	DISSELREG_END,
295	/** The usual 32-bit paranoia. */
296	DIS_SEGREG_32BIT_HACK = 0x7fffffff
297	} DISSELREG;
298	/** @} */
299
300	/** @name FPU register indexes.
301	* This matches the AMD64 register encoding. It is found used in
302	* DISOPPARAM::Base.idxFpuReg.
303	* @{
304	*/
305	#define DISFPREG_ST0 UINT8_C(0)
306	#define DISFPREG_ST1 UINT8_C(1)
307	#define DISFPREG_ST2 UINT8_C(2)
308	#define DISFPREG_ST3 UINT8_C(3)
309	#define DISFPREG_ST4 UINT8_C(4)
310	#define DISFPREG_ST5 UINT8_C(5)
311	#define DISFPREG_ST6 UINT8_C(6)
312	#define DISFPREG_ST7 UINT8_C(7)
313	/** @} */
314
315	/** @name Control register indexes.
316	* This matches the AMD64 register encoding. It is found used in
317	* DISOPPARAM::Base.idxCtrlReg.
318	* @{
319	*/
320	#define DISCREG_CR0 UINT8_C(0)
321	#define DISCREG_CR1 UINT8_C(1)
322	#define DISCREG_CR2 UINT8_C(2)
323	#define DISCREG_CR3 UINT8_C(3)
324	#define DISCREG_CR4 UINT8_C(4)
325	#define DISCREG_CR8 UINT8_C(8)
326	/** @} */
327
328	/** @name Debug register indexes.
329	* This matches the AMD64 register encoding. It is found used in
330	* DISOPPARAM::Base.idxDbgReg.
331	* @{
332	*/
333	#define DISDREG_DR0 UINT8_C(0)
334	#define DISDREG_DR1 UINT8_C(1)
335	#define DISDREG_DR2 UINT8_C(2)
336	#define DISDREG_DR3 UINT8_C(3)
337	#define DISDREG_DR4 UINT8_C(4)
338	#define DISDREG_DR5 UINT8_C(5)
339	#define DISDREG_DR6 UINT8_C(6)
340	#define DISDREG_DR7 UINT8_C(7)
341	/** @} */
342
343	/** @name MMX register indexes.
344	* This matches the AMD64 register encoding. It is found used in
345	* DISOPPARAM::Base.idxMmxReg.
346	* @{
347	*/
348	#define DISMREG_MMX0 UINT8_C(0)
349	#define DISMREG_MMX1 UINT8_C(1)
350	#define DISMREG_MMX2 UINT8_C(2)
351	#define DISMREG_MMX3 UINT8_C(3)
352	#define DISMREG_MMX4 UINT8_C(4)
353	#define DISMREG_MMX5 UINT8_C(5)
354	#define DISMREG_MMX6 UINT8_C(6)
355	#define DISMREG_MMX7 UINT8_C(7)
356	/** @} */
357
358	/** @name SSE register indexes.
359	* This matches the AMD64 register encoding. It is found used in
360	* DISOPPARAM::Base.idxXmmReg.
361	* @{
362	*/
363	#define DISXREG_XMM0 UINT8_C(0)
364	#define DISXREG_XMM1 UINT8_C(1)
365	#define DISXREG_XMM2 UINT8_C(2)
366	#define DISXREG_XMM3 UINT8_C(3)
367	#define DISXREG_XMM4 UINT8_C(4)
368	#define DISXREG_XMM5 UINT8_C(5)
369	#define DISXREG_XMM6 UINT8_C(6)
370	#define DISXREG_XMM7 UINT8_C(7)
371	/** @} */
372
373
374	/**
375	* Opcode parameter (operand) details.
376	*/
377	typedef struct DISOPPARAM
378	{
379	/** A combination of DISUSE_XXX. */
380	uint64_t fUse;
381	/** Immediate value or address, applicable if any of the flags included in
382	* DISUSE_IMMEDIATE are set in fUse. */
383	uint64_t uValue;
384	/** Disposition. */
385	union
386	{
387	/** 64-bit displacement, applicable if DISUSE_DISPLACEMENT64 is set in fUse. */
388	int64_t i64;
389	uint64_t u64;
390	/** 32-bit displacement, applicable if DISUSE_DISPLACEMENT32 or
391	* DISUSE_RIPDISPLACEMENT32 is set in fUse. */
392	int32_t i32;
393	uint32_t u32;
394	/** 16-bit displacement, applicable if DISUSE_DISPLACEMENT16 is set in fUse. */
395	int32_t i16;
396	uint32_t u16;
397	/** 8-bit displacement, applicable if DISUSE_DISPLACEMENT8 is set in fUse. */
398	int32_t i8;
399	uint32_t u8;
400	} uDisp;
401	/** The base register from ModR/M or SIB, applicable if DISUSE_BASE is
402	* set in fUse. */
403	union
404	{
405	/** General register index (DISGREG_XXX), applicable if DISUSE_REG_GEN8,
406	* DISUSE_REG_GEN16, DISUSE_REG_GEN32 or DISUSE_REG_GEN64 is set in fUse. */
407	uint8_t idxGenReg;
408	/** FPU stack register index (DISFPREG_XXX), applicable if DISUSE_REG_FP is
409	* set in fUse. 1:1 indexes. */
410	uint8_t idxFpuReg;
411	/** MMX register index (DISMREG_XXX), applicable if DISUSE_REG_MMX is
412	* set in fUse. 1:1 indexes. */
413	uint8_t idxMmxReg;
414	/** SSE register index (DISXREG_XXX), applicable if DISUSE_REG_XMM is
415	* set in fUse. 1:1 indexes. */
416	uint8_t idxXmmReg;
417	/** Segment register index (DISSELREG_XXX), applicable if DISUSE_REG_SEG is
418	* set in fUse. */
419	uint8_t idxSegReg;
420	/** Test register, TR0-TR7, present on early IA32 CPUs, applicable if
421	* DISUSE_REG_TEST is set in fUse. No index defines for these. */
422	uint8_t idxTestReg;
423	/** Control register index (DISCREG_XXX), applicable if DISUSE_REG_CR is
424	* set in fUse. 1:1 indexes. */
425	uint8_t idxCtrlReg;
426	/** Debug register index (DISDREG_XXX), applicable if DISUSE_REG_DBG is
427	* set in fUse. 1:1 indexes. */
428	uint8_t idxDbgReg;
429	} Base;
430	/** The SIB index register meaning, applicable if DISUSE_INDEX is
431	* set in fUse. */
432	union
433	{
434	/** General register index (DISGREG_XXX), applicable if DISUSE_REG_GEN8,
435	* DISUSE_REG_GEN16, DISUSE_REG_GEN32 or DISUSE_REG_GEN64 is set in fUse. */
436	uint8_t idxGenReg;
437	} Index;
438	/** 2, 4 or 8, if DISUSE_SCALE is set in fUse. */
439	uint8_t uScale;
440	/** Parameter size. */
441	uint8_t cb;
442	/** Copy of the corresponding DISOPCODE::fParam1 / DISOPCODE::fParam2 /
443	* DISOPCODE::fParam3. */
444	uint32_t fParam;
445	} DISOPPARAM;
446	AssertCompileSize(DISOPPARAM, 32);
447	/** Pointer to opcode parameter. */
448	typedef DISOPPARAM *PDISOPPARAM;
449	/** Pointer to opcode parameter. */
450	typedef const DISOPPARAM *PCDISOPPARAM;
451
452
453	/**
454	* Opcode descriptor.
455	*/
456	typedef struct DISOPCODE
457	{
458	#ifndef DIS_CORE_ONLY
459	const char *pszOpcode;
460	#endif
461	/** Parameter \#1 parser index. */
462	uint8_t idxParse1;
463	/** Parameter \#2 parser index. */
464	uint8_t idxParse2;
465	/** Parameter \#3 parser index. */
466	uint8_t idxParse3;
467	/** Unused padding. */
468	uint8_t uUnused;
469	/** The opcode identifier. This DIS specific, @see grp_dis_opcodes and
470	* VBox/disopcode.h. */
471	uint16_t uOpcode;
472	/** Parameter \#1 info, @see grp_dis_opparam. */
473	uint16_t fParam1;
474	/** Parameter \#2 info, @see grp_dis_opparam. */
475	uint16_t fParam2;
476	/** Parameter \#3 info, @see grp_dis_opparam. */
477	uint16_t fParam3;
478	/** Operand type flags, DISOPTYPE_XXX. */
479	uint32_t fOpType;
480	} DISOPCODE;
481	/** Pointer to const opcode. */
482	typedef const struct DISOPCODE *PCDISOPCODE;
483
484
485	/**
486	* Callback for reading instruction bytes.
487	*
488	* @returns VBox status code, bytes in DISSTATE::abInstr and byte count in
489	* DISSTATE::cbCachedInstr.
490	* @param pDis Pointer to the disassembler state. The user
491	* argument can be found in DISSTATE::pvUser if needed.
492	* @param offInstr The offset relative to the start of the instruction.
493	*
494	* To get the source address, add this to
495	* DISSTATE::uInstrAddr.
496	*
497	* To calculate the destination buffer address, use it
498	* as an index into DISSTATE::abInstr.
499	*
500	* @param cbMinRead The minimum number of bytes to read.
501	* @param cbMaxRead The maximum number of bytes that may be read.
502	*/
503	typedef DECLCALLBACK(int) FNDISREADBYTES(PDISSTATE pDis, uint8_t offInstr, uint8_t cbMinRead, uint8_t cbMaxRead);
504	/** Pointer to a opcode byte reader. */
505	typedef FNDISREADBYTES *PFNDISREADBYTES;
506
507	/** Parser callback.
508	* @remark no DECLCALLBACK() here because it's considered to be internal and
509	* there is no point in enforcing CDECL. */
510	typedef size_t FNDISPARSE(size_t offInstr, PCDISOPCODE pOp, PDISSTATE pDis, PDISOPPARAM pParam);
511	/** Pointer to a disassembler parser function. */
512	typedef FNDISPARSE *PFNDISPARSE;
513	/** Pointer to a const disassembler parser function pointer. */
514	typedef PFNDISPARSE const *PCPFNDISPARSE;
515
516	/**
517	* The diassembler state and result.
518	*/
519	typedef struct DISSTATE
520	{
521	/** The number of valid bytes in abInstr. */
522	uint8_t cbCachedInstr;
523	/** SIB fields. */
524	union
525	{
526	/** Bitfield view */
527	struct
528	{
529	uint8_t Base;
530	uint8_t Index;
531	uint8_t Scale;
532	} Bits;
533	} SIB;
534	/** ModRM fields. */
535	union
536	{
537	/** Bitfield view */
538	struct
539	{
540	uint8_t Rm;
541	uint8_t Reg;
542	uint8_t Mod;
543	} Bits;
544	} ModRM;
545	/** The CPU mode (DISCPUMODE). */
546	uint8_t uCpuMode;
547	/** The addressing mode (DISCPUMODE). */
548	uint8_t uAddrMode;
549	/** The operand mode (DISCPUMODE). */
550	uint8_t uOpMode;
551	/** Per instruction prefix settings. */
552	uint8_t fPrefix;
553	/** REX prefix value (64 bits only). */
554	uint8_t fRexPrefix;
555	/** Segment prefix value (DISSELREG). */
556	uint8_t idxSegPrefix;
557	/** Last prefix byte (for SSE2 extension tables). */
558	uint8_t bLastPrefix;
559	/** Last significan opcode byte of instruction. */
560	uint8_t bOpCode;
561	/** The size of the prefix bytes. */
562	uint8_t cbPrefix;
563	/** The instruction size. */
564	uint8_t cbInstr;
565	/** Unused bytes. */
566	uint8_t abUnused[3];
567	/** Internal: instruction filter */
568	uint32_t fFilter;
569	/** Internal: pointer to disassembly function table */
570	PCPFNDISPARSE pfnDisasmFnTable;
571	#if ARCH_BITS == 32
572	uint32_t uPtrPadding1;
573	#endif
574	/** Pointer to the current instruction. */
575	PCDISOPCODE pCurInstr;
576	#if ARCH_BITS == 32
577	uint32_t uPtrPadding2;
578	#endif
579	/** The instruction bytes. */
580	uint8_t abInstr[16];
581	/** SIB displacment. */
582	int32_t i32SibDisp;
583
584	/** Return code set by a worker function like the opcode bytes readers. */
585	int32_t rc;
586	/** The address of the instruction. */
587	RTUINTPTR uInstrAddr;
588	/** Optional read function */
589	PFNDISREADBYTES pfnReadBytes;
590	#if ARCH_BITS == 32
591	uint32_t uPadding3;
592	#endif
593	/** User data supplied as an argument to the APIs. */
594	void *pvUser;
595	#if ARCH_BITS == 32
596	uint32_t uPadding4;
597	#endif
598	/** Parameters. */
599	DISOPPARAM Param1;
600	DISOPPARAM Param2;
601	DISOPPARAM Param3;
602	} DISSTATE;
603	AssertCompileSize(DISSTATE, 0xb8);
604
605	/** @deprecated Use DISSTATE and change Cpu and DisState to Dis. */
606	typedef DISSTATE DISCPUSTATE;
607
608
609
610	DISDECL(int) DISInstrToStr(void const *pvInstr, DISCPUMODE enmCpuMode,
611	PDISSTATE pDis, uint32_t pcbInstr, char pszOutput, size_t cbOutput);
612	DISDECL(int) DISInstrToStrWithReader(RTUINTPTR uInstrAddr, DISCPUMODE enmCpuMode, PFNDISREADBYTES pfnReadBytes, void *pvUser,
613	PDISSTATE pDis, uint32_t pcbInstr, char pszOutput, size_t cbOutput);
614	DISDECL(int) DISInstrToStrEx(RTUINTPTR uInstrAddr, DISCPUMODE enmCpuMode,
615	PFNDISREADBYTES pfnReadBytes, void *pvUser, uint32_t uFilter,
616	PDISSTATE pDis, uint32_t pcbInstr, char pszOutput, size_t cbOutput);
617
618	DISDECL(int) DISInstr(void const pvInstr, DISCPUMODE enmCpuMode, PDISSTATE pDis, uint32_t pcbInstr);
619	DISDECL(int) DISInstrWithReader(RTUINTPTR uInstrAddr, DISCPUMODE enmCpuMode, PFNDISREADBYTES pfnReadBytes, void *pvUser,
620	PDISSTATE pDis, uint32_t *pcbInstr);
621	DISDECL(int) DISInstrEx(RTUINTPTR uInstrAddr, DISCPUMODE enmCpuMode, uint32_t uFilter,
622	PFNDISREADBYTES pfnReadBytes, void *pvUser,
623	PDISSTATE pDis, uint32_t *pcbInstr);
624	DISDECL(int) DISInstrWithPrefetchedBytes(RTUINTPTR uInstrAddr, DISCPUMODE enmCpuMode, uint32_t fFilter,
625	void const *pvPrefetched, size_t cbPretched,
626	PFNDISREADBYTES pfnReadBytes, void *pvUser,
627	PDISSTATE pDis, uint32_t *pcbInstr);
628
629	DISDECL(int) DISGetParamSize(PCDISSTATE pDis, PCDISOPPARAM pParam);
630	DISDECL(DISSELREG) DISDetectSegReg(PCDISSTATE pDis, PCDISOPPARAM pParam);
631	DISDECL(uint8_t) DISQuerySegPrefixByte(PCDISSTATE pDis);
632
633
634
635	/** @name Flags returned by DISQueryParamVal (DISQPVPARAMVAL::flags).
636	* @{
637	*/
638	#define DISQPV_FLAG_8 UINT8_C(0x01)
639	#define DISQPV_FLAG_16 UINT8_C(0x02)
640	#define DISQPV_FLAG_32 UINT8_C(0x04)
641	#define DISQPV_FLAG_64 UINT8_C(0x08)
642	#define DISQPV_FLAG_FARPTR16 UINT8_C(0x10)
643	#define DISQPV_FLAG_FARPTR32 UINT8_C(0x20)
644	/** @} */
645
646	/** @name Types returned by DISQueryParamVal (DISQPVPARAMVAL::flags).
647	* @{ */
648	#define DISQPV_TYPE_REGISTER UINT8_C(1)
649	#define DISQPV_TYPE_ADDRESS UINT8_C(2)
650	#define DISQPV_TYPE_IMMEDIATE UINT8_C(3)
651	/** @} */
652
653	typedef struct
654	{
655	union
656	{
657	uint8_t val8;
658	uint16_t val16;
659	uint32_t val32;
660	uint64_t val64;
661
662	struct
663	{
664	uint16_t sel;
665	uint32_t offset;
666	} farptr;
667	} val;
668
669	uint8_t type;
670	uint8_t size;
671	uint8_t flags;
672	} DISQPVPARAMVAL;
673	/** Pointer to opcode parameter value. */
674	typedef DISQPVPARAMVAL *PDISQPVPARAMVAL;
675
676	/** Indicates which parameter DISQueryParamVal should operate on. */
677	typedef enum DISQPVWHICH
678	{
679	DISQPVWHICH_DST = 1,
680	DISQPVWHICH_SRC,
681	DISQPVWHAT_32_BIT_HACK = 0x7fffffff
682	} DISQPVWHICH;
683	DISDECL(int) DISQueryParamVal(PCPUMCTXCORE pCtx, PCDISSTATE pDis, PCDISOPPARAM pParam, PDISQPVPARAMVAL pParamVal, DISQPVWHICH parmtype);
684	DISDECL(int) DISQueryParamRegPtr(PCPUMCTXCORE pCtx, PCDISSTATE pDis, PCDISOPPARAM pParam, void *ppReg, size_t pcbSize);
685
686	DISDECL(int) DISFetchReg8(PCCPUMCTXCORE pCtx, unsigned reg8, uint8_t *pVal);
687	DISDECL(int) DISFetchReg16(PCCPUMCTXCORE pCtx, unsigned reg16, uint16_t *pVal);
688	DISDECL(int) DISFetchReg32(PCCPUMCTXCORE pCtx, unsigned reg32, uint32_t *pVal);
689	DISDECL(int) DISFetchReg64(PCCPUMCTXCORE pCtx, unsigned reg64, uint64_t *pVal);
690	DISDECL(int) DISFetchRegSeg(PCCPUMCTXCORE pCtx, DISSELREG sel, RTSEL *pVal);
691	DISDECL(int) DISFetchRegSegEx(PCPUMCTXCORE pCtx, DISSELREG sel, PCPUMSELREG *ppSelReg);
692	DISDECL(int) DISWriteReg8(PCPUMCTXCORE pRegFrame, unsigned reg8, uint8_t val8);
693	DISDECL(int) DISWriteReg16(PCPUMCTXCORE pRegFrame, unsigned reg32, uint16_t val16);
694	DISDECL(int) DISWriteReg32(PCPUMCTXCORE pRegFrame, unsigned reg32, uint32_t val32);
695	DISDECL(int) DISWriteReg64(PCPUMCTXCORE pRegFrame, unsigned reg64, uint64_t val64);
696	DISDECL(int) DISWriteRegSeg(PCPUMCTXCORE pCtx, DISSELREG sel, RTSEL val);
697	DISDECL(int) DISPtrReg8(PCPUMCTXCORE pCtx, unsigned reg8, uint8_t **ppReg);
698	DISDECL(int) DISPtrReg16(PCPUMCTXCORE pCtx, unsigned reg16, uint16_t **ppReg);
699	DISDECL(int) DISPtrReg32(PCPUMCTXCORE pCtx, unsigned reg32, uint32_t **ppReg);
700	DISDECL(int) DISPtrReg64(PCPUMCTXCORE pCtx, unsigned reg64, uint64_t **ppReg);
701
702
703	/**
704	* Try resolve an address into a symbol name.
705	*
706	* For use with DISFormatYasmEx(), DISFormatMasmEx() and DISFormatGasEx().
707	*
708	* @returns VBox status code.
709	* @retval VINF_SUCCESS on success, pszBuf contains the full symbol name.
710	* @retval VINF_BUFFER_OVERFLOW if pszBuf is too small the symbol name. The
711	* content of pszBuf is truncated and zero terminated.
712	* @retval VERR_SYMBOL_NOT_FOUND if no matching symbol was found for the address.
713	*
714	* @param pDis Pointer to the disassembler CPU state.
715	* @param u32Sel The selector value. Use DIS_FMT_SEL_IS_REG, DIS_FMT_SEL_GET_VALUE,
716	* DIS_FMT_SEL_GET_REG to access this.
717	* @param uAddress The segment address.
718	* @param pszBuf Where to store the symbol name
719	* @param cchBuf The size of the buffer.
720	* @param poff If not a perfect match, then this is where the offset from the return
721	* symbol to the specified address is returned.
722	* @param pvUser The user argument.
723	*/
724	typedef DECLCALLBACK(int) FNDISGETSYMBOL(PCDISSTATE pDis, uint32_t u32Sel, RTUINTPTR uAddress, char pszBuf, size_t cchBuf, RTINTPTR poff, void *pvUser);
725	/** Pointer to a FNDISGETSYMBOL(). */
726	typedef FNDISGETSYMBOL *PFNDISGETSYMBOL;
727
728	/**
729	* Checks if the FNDISGETSYMBOL argument u32Sel is a register or not.
730	*/
731	#define DIS_FMT_SEL_IS_REG(u32Sel) ( !!((u32Sel) & RT_BIT(31)) )
732
733	/**
734	* Extracts the selector value from the FNDISGETSYMBOL argument u32Sel.
735	* @returns Selector value.
736	*/
737	#define DIS_FMT_SEL_GET_VALUE(u32Sel) ( (RTSEL)(u32Sel) )
738
739	/**
740	* Extracts the register number from the FNDISGETSYMBOL argument u32Sel.
741	* @returns USE_REG_CS, USE_REG_SS, USE_REG_DS, USE_REG_ES, USE_REG_FS or USE_REG_FS.
742	*/
743	#define DIS_FMT_SEL_GET_REG(u32Sel) ( ((u32Sel) >> 16) & 0xf )
744
745	/** @internal */
746	#define DIS_FMT_SEL_FROM_REG(uReg) ( ((uReg) << 16) \| RT_BIT(31) \| 0xffff )
747	/** @internal */
748	#define DIS_FMT_SEL_FROM_VALUE(Sel) ( (Sel) & 0xffff )
749
750
751	/** @name Flags for use with DISFormatYasmEx(), DISFormatMasmEx() and DISFormatGasEx().
752	* @{
753	*/
754	/** Put the address to the right. */
755	#define DIS_FMT_FLAGS_ADDR_RIGHT RT_BIT_32(0)
756	/** Put the address to the left. */
757	#define DIS_FMT_FLAGS_ADDR_LEFT RT_BIT_32(1)
758	/** Put the address in comments.
759	* For some assemblers this implies placing it to the right. */
760	#define DIS_FMT_FLAGS_ADDR_COMMENT RT_BIT_32(2)
761	/** Put the instruction bytes to the right of the disassembly. */
762	#define DIS_FMT_FLAGS_BYTES_RIGHT RT_BIT_32(3)
763	/** Put the instruction bytes to the left of the disassembly. */
764	#define DIS_FMT_FLAGS_BYTES_LEFT RT_BIT_32(4)
765	/** Put the instruction bytes in comments.
766	* For some assemblers this implies placing the bytes to the right. */
767	#define DIS_FMT_FLAGS_BYTES_COMMENT RT_BIT_32(5)
768	/** Put the bytes in square brackets. */
769	#define DIS_FMT_FLAGS_BYTES_BRACKETS RT_BIT_32(6)
770	/** Put spaces between the bytes. */
771	#define DIS_FMT_FLAGS_BYTES_SPACED RT_BIT_32(7)
772	/** Display the relative +/- offset of branch instructions that uses relative addresses,
773	* and put the target address in parenthesis. */
774	#define DIS_FMT_FLAGS_RELATIVE_BRANCH RT_BIT_32(8)
775	/** Strict assembly. The assembly should, when ever possible, make the
776	* assembler reproduce the exact same binary. (Refers to the yasm
777	* strict keyword.) */
778	#define DIS_FMT_FLAGS_STRICT RT_BIT_32(9)
779	/** Checks if the given flags are a valid combination. */
780	#define DIS_FMT_FLAGS_IS_VALID(fFlags) \
781	( !((fFlags) & ~UINT32_C(0x000003ff)) \
782	&& ((fFlags) & (DIS_FMT_FLAGS_ADDR_RIGHT \| DIS_FMT_FLAGS_ADDR_LEFT)) != (DIS_FMT_FLAGS_ADDR_RIGHT \| DIS_FMT_FLAGS_ADDR_LEFT) \
783	&& ( !((fFlags) & DIS_FMT_FLAGS_ADDR_COMMENT) \
784	\|\| (fFlags & (DIS_FMT_FLAGS_ADDR_RIGHT \| DIS_FMT_FLAGS_ADDR_LEFT)) ) \
785	&& ((fFlags) & (DIS_FMT_FLAGS_BYTES_RIGHT \| DIS_FMT_FLAGS_BYTES_LEFT)) != (DIS_FMT_FLAGS_BYTES_RIGHT \| DIS_FMT_FLAGS_BYTES_LEFT) \
786	&& ( !((fFlags) & (DIS_FMT_FLAGS_BYTES_COMMENT \| DIS_FMT_FLAGS_BYTES_BRACKETS)) \
787	\|\| (fFlags & (DIS_FMT_FLAGS_BYTES_RIGHT \| DIS_FMT_FLAGS_BYTES_LEFT)) ) \
788	)
789	/** @} */
790
791	DISDECL(size_t) DISFormatYasm( PCDISSTATE pDis, char *pszBuf, size_t cchBuf);
792	DISDECL(size_t) DISFormatYasmEx(PCDISSTATE pDis, char pszBuf, size_t cchBuf, uint32_t fFlags, PFNDISGETSYMBOL pfnGetSymbol, void pvUser);
793	DISDECL(size_t) DISFormatMasm( PCDISSTATE pDis, char *pszBuf, size_t cchBuf);
794	DISDECL(size_t) DISFormatMasmEx(PCDISSTATE pDis, char pszBuf, size_t cchBuf, uint32_t fFlags, PFNDISGETSYMBOL pfnGetSymbol, void pvUser);
795	DISDECL(size_t) DISFormatGas( PCDISSTATE pDis, char *pszBuf, size_t cchBuf);
796	DISDECL(size_t) DISFormatGasEx( PCDISSTATE pDis, char pszBuf, size_t cchBuf, uint32_t fFlags, PFNDISGETSYMBOL pfnGetSymbol, void pvUser);
797
798	/** @todo DISAnnotate(PCDISSTATE pDis, char *pszBuf, size_t cchBuf, register
799	* reader, memory reader); */
800
801	DISDECL(bool) DISFormatYasmIsOddEncoding(PDISSTATE pDis);
802
803
804	RT_C_DECLS_END
805
806	#endif
807

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source: vbox/trunk/include/VBox/dis.h@ 46783

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