VirtualBox

source: vbox/trunk/include/VBox/dis.h@ 6561

Last change on this file since 6561 was 5999, checked in by vboxsync, 17 years ago

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1/** @file
2 * DIS - The VirtualBox Disassembler.
3 */
4
5/*
6 * Copyright (C) 2006-2007 innotek GmbH
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * The contents of this file may alternatively be used under the terms
17 * of the Common Development and Distribution License Version 1.0
18 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19 * VirtualBox OSE distribution, in which case the provisions of the
20 * CDDL are applicable instead of those of the GPL.
21 *
22 * You may elect to license modified versions of this file under the
23 * terms and conditions of either the GPL or the CDDL or both.
24 */
25
26#ifndef ___VBox_disasm_h
27#define ___VBox_disasm_h
28
29#include <VBox/cdefs.h>
30#include <VBox/types.h>
31#include <VBox/cpum.h>
32#include <VBox/disopcode.h>
33
34#if defined(__L4ENV__)
35#include <setjmp.h>
36#endif
37
38__BEGIN_DECLS
39
40
41/** CPU mode flags (DISCPUSTATE::mode).
42 * @{
43 */
44typedef enum
45{
46 CPUMODE_16BIT = 1,
47 CPUMODE_32BIT = 2,
48 CPUMODE_64BIT = 3
49} DISCPUMODE;
50/** @} */
51
52/** Prefix byte flags
53 * @{
54 */
55#define PREFIX_NONE 0
56/** non-default address size. */
57#define PREFIX_ADDRSIZE 1
58/** non-default operand size. */
59#define PREFIX_OPSIZE 2
60/** lock prefix. */
61#define PREFIX_LOCK 4
62/** segment prefix. */
63#define PREFIX_SEG 8
64/** rep(e) prefix (not a prefix, but we'll treat is as one). */
65#define PREFIX_REP 16
66/** rep(e) prefix (not a prefix, but we'll treat is as one). */
67#define PREFIX_REPNE 32
68/** @} */
69
70/**
71 * Operand type.
72 */
73#define OPTYPE_INVALID RT_BIT(0)
74#define OPTYPE_HARMLESS RT_BIT(1)
75#define OPTYPE_CONTROLFLOW RT_BIT(2)
76#define OPTYPE_POTENTIALLY_DANGEROUS RT_BIT(3)
77#define OPTYPE_DANGEROUS RT_BIT(4)
78#define OPTYPE_PORTIO RT_BIT(5)
79#define OPTYPE_PRIVILEGED RT_BIT(6)
80#define OPTYPE_PRIVILEGED_NOTRAP RT_BIT(7)
81#define OPTYPE_UNCOND_CONTROLFLOW RT_BIT(8)
82#define OPTYPE_RELATIVE_CONTROLFLOW RT_BIT(9)
83#define OPTYPE_COND_CONTROLFLOW RT_BIT(10)
84#define OPTYPE_INTERRUPT RT_BIT(11)
85#define OPTYPE_ILLEGAL RT_BIT(12)
86#define OPTYPE_RRM_DANGEROUS RT_BIT(14) /**< Some additional dangerouse ones when recompiling raw r0. */
87#define OPTYPE_RRM_DANGEROUS_16 RT_BIT(15) /**< Some additional dangerouse ones when recompiling 16-bit raw r0. */
88#define OPTYPE_RRM_MASK (OPTYPE_RRM_DANGEROUS | OPTYPE_RRM_DANGEROUS_16)
89#define OPTYPE_INHIBIT_IRQS RT_BIT(16) /**< Will or can inhibit irqs (sti, pop ss, mov ss) */
90#define OPTYPE_PORTIO_READ RT_BIT(17)
91#define OPTYPE_PORTIO_WRITE RT_BIT(18)
92#define OPTYPE_ALL (0xffffffff)
93
94/** Parameter usage flags.
95 * @{
96 */
97#define USE_BASE RT_BIT(0)
98#define USE_INDEX RT_BIT(1)
99#define USE_SCALE RT_BIT(2)
100#define USE_REG_GEN8 RT_BIT(3)
101#define USE_REG_GEN16 RT_BIT(4)
102#define USE_REG_GEN32 RT_BIT(5)
103#define USE_REG_FP RT_BIT(6)
104#define USE_REG_MMX RT_BIT(7)
105#define USE_REG_XMM RT_BIT(8)
106#define USE_REG_CR RT_BIT(9)
107#define USE_REG_DBG RT_BIT(10)
108#define USE_REG_SEG RT_BIT(11)
109#define USE_REG_TEST RT_BIT(12)
110#define USE_DISPLACEMENT8 RT_BIT(13)
111#define USE_DISPLACEMENT16 RT_BIT(14)
112#define USE_DISPLACEMENT32 RT_BIT(15)
113#define USE_IMMEDIATE8 RT_BIT(16)
114#define USE_IMMEDIATE8_REL RT_BIT(17)
115#define USE_IMMEDIATE16 RT_BIT(18)
116#define USE_IMMEDIATE16_REL RT_BIT(19)
117#define USE_IMMEDIATE32 RT_BIT(20)
118#define USE_IMMEDIATE32_REL RT_BIT(21)
119#define USE_IMMEDIATE64 RT_BIT(22)
120#define USE_IMMEDIATE_ADDR_0_32 RT_BIT(23)
121#define USE_IMMEDIATE_ADDR_16_32 RT_BIT(24)
122#define USE_IMMEDIATE_ADDR_0_16 RT_BIT(25)
123#define USE_IMMEDIATE_ADDR_16_16 RT_BIT(26)
124/** DS:ESI */
125#define USE_POINTER_DS_BASED RT_BIT(27)
126/** ES:EDI */
127#define USE_POINTER_ES_BASED RT_BIT(28)
128#define USE_IMMEDIATE16_SX8 RT_BIT(29)
129#define USE_IMMEDIATE32_SX8 RT_BIT(30)
130
131#define USE_IMMEDIATE (USE_IMMEDIATE8|USE_IMMEDIATE16|USE_IMMEDIATE32|USE_IMMEDIATE64|USE_IMMEDIATE8_REL|USE_IMMEDIATE16_REL|USE_IMMEDIATE32_REL|USE_IMMEDIATE_ADDR_0_32|USE_IMMEDIATE_ADDR_16_32|USE_IMMEDIATE_ADDR_0_16|USE_IMMEDIATE_ADDR_16_16|USE_IMMEDIATE16_SX8|USE_IMMEDIATE32_SX8)
132
133/** @} */
134
135/** index in {"EAX", "ECX", "EDX", "EBX", "ESP", "EBP", "ESI", "EDI"}
136 * @{
137 */
138#define USE_REG_EAX 0
139#define USE_REG_ECX 1
140#define USE_REG_EDX 2
141#define USE_REG_EBX 3
142#define USE_REG_ESP 4
143#define USE_REG_EBP 5
144#define USE_REG_ESI 6
145#define USE_REG_EDI 7
146/** @} */
147/** index in {"AX", "CX", "DX", "BX", "SP", "BP", "SI", "DI"}
148 * @{
149 */
150#define USE_REG_AX 0
151#define USE_REG_CX 1
152#define USE_REG_DX 2
153#define USE_REG_BX 3
154#define USE_REG_SP 4
155#define USE_REG_BP 5
156#define USE_REG_SI 6
157#define USE_REG_DI 7
158/** @} */
159
160/** index in {"AL", "CL", "DL", "BL", "AH", "CH", "DH", "BH"}
161 * @{
162 */
163#define USE_REG_AL 0
164#define USE_REG_CL 1
165#define USE_REG_DL 2
166#define USE_REG_BL 3
167#define USE_REG_AH 4
168#define USE_REG_CH 5
169#define USE_REG_DH 6
170#define USE_REG_BH 7
171/** @} */
172
173/** index in {ES, CS, SS, DS, FS, GS}
174 * @{
175 */
176#define USE_REG_ES 0
177#define USE_REG_CS 1
178#define USE_REG_SS 2
179#define USE_REG_DS 3
180#define USE_REG_FS 4
181#define USE_REG_GS 5
182/** @} */
183
184#define USE_REG_FP0 0
185#define USE_REG_FP1 1
186#define USE_REG_FP2 2
187#define USE_REG_FP3 3
188#define USE_REG_FP4 4
189#define USE_REG_FP5 5
190#define USE_REG_FP6 6
191#define USE_REG_FP7 7
192
193#define USE_REG_CR0 0
194#define USE_REG_CR1 1
195#define USE_REG_CR2 2
196#define USE_REG_CR3 3
197#define USE_REG_CR4 4
198
199#define USE_REG_DR0 0
200#define USE_REG_DR1 1
201#define USE_REG_DR2 2
202#define USE_REG_DR3 3
203#define USE_REG_DR4 4
204#define USE_REG_DR5 5
205#define USE_REG_DR6 6
206#define USE_REG_DR7 7
207
208#define USE_REG_MMX0 0
209#define USE_REG_MMX1 1
210#define USE_REG_MMX2 2
211#define USE_REG_MMX3 3
212#define USE_REG_MMX4 4
213#define USE_REG_MMX5 5
214#define USE_REG_MMX6 6
215#define USE_REG_MMX7 7
216
217#define USE_REG_XMM0 0
218#define USE_REG_XMM1 1
219#define USE_REG_XMM2 2
220#define USE_REG_XMM3 3
221#define USE_REG_XMM4 4
222#define USE_REG_XMM5 5
223#define USE_REG_XMM6 6
224#define USE_REG_XMM7 7
225
226/** Used by DISQueryParamVal & EMIQueryParamVal
227 * @{
228 */
229#define PARAM_VAL8 RT_BIT(0)
230#define PARAM_VAL16 RT_BIT(1)
231#define PARAM_VAL32 RT_BIT(2)
232#define PARAM_VAL64 RT_BIT(3)
233#define PARAM_VALFARPTR16 RT_BIT(4)
234#define PARAM_VALFARPTR32 RT_BIT(5)
235
236#define PARMTYPE_REGISTER 1
237#define PARMTYPE_ADDRESS 2
238#define PARMTYPE_IMMEDIATE 3
239
240typedef struct
241{
242 uint32_t type;
243 uint32_t flags;
244 uint32_t size;
245
246 union
247 {
248 uint8_t val8;
249 uint16_t val16;
250 uint32_t val32;
251 uint64_t val64;
252
253 struct
254 {
255 uint16_t sel;
256 uint32_t offset;
257 } farptr;
258 } val;
259
260} OP_PARAMVAL;
261/** Pointer to opcode parameter value. */
262typedef OP_PARAMVAL *POP_PARAMVAL;
263
264typedef enum
265{
266 PARAM_DEST,
267 PARAM_SOURCE
268} PARAM_TYPE;
269
270/** @} */
271
272/**
273 * Operand Parameter.
274 */
275typedef struct _OP_PARAMETER
276{
277 int param;
278 uint64_t parval;
279 char szParam[32];
280
281 int32_t disp8, disp16, disp32;
282
283 uint32_t flags;
284
285 uint32_t size;
286
287 union
288 {
289 uint32_t reg_gen8;
290 uint32_t reg_gen16;
291 uint32_t reg_gen32;
292 /** ST(0) - ST(7) */
293 uint32_t reg_fp;
294 /** MMX0 - MMX7 */
295 uint32_t reg_mmx;
296 /** XMM0 - XMM7 */
297 uint32_t reg_xmm;
298 /** {ES, CS, SS, DS, FS, GS} */
299 uint32_t reg_seg;
300 /** TR0-TR7 (?) */
301 uint32_t reg_test;
302 /** CR0-CR4 */
303 uint32_t reg_ctrl;
304 /** DR0-DR7 */
305 uint32_t reg_dbg;
306 } base;
307 union
308 {
309 uint32_t reg_gen;
310 } index;
311
312 /** 2, 4 or 8. */
313 uint32_t scale;
314
315} OP_PARAMETER;
316/** Pointer to opcode parameter. */
317typedef OP_PARAMETER *POP_PARAMETER;
318/** Pointer to opcode parameter. */
319typedef const OP_PARAMETER *PCOP_PARAMETER;
320
321
322struct _OPCODE;
323/** Pointer to opcode. */
324typedef struct _OPCODE *POPCODE;
325/** Pointer to const opcode. */
326typedef const struct _OPCODE *PCOPCODE;
327
328typedef DECLCALLBACK(int) FN_DIS_READBYTES(RTUINTPTR pSrc, uint8_t *pDest, uint32_t size, void *pvUserdata);
329typedef FN_DIS_READBYTES *PFN_DIS_READBYTES;
330
331/* forward decl */
332struct _DISCPUSTATE;
333/** Pointer to the disassembler CPU state. */
334typedef struct _DISCPUSTATE *PDISCPUSTATE;
335
336/** Parser callback.
337 * @remark no DECLCALLBACK() here because it's considered to be internal (really, I'm too lazy to update all the functions). */
338typedef unsigned FNDISPARSE(RTUINTPTR pu8CodeBlock, PCOPCODE pOp, POP_PARAMETER pParam, PDISCPUSTATE pCpu);
339typedef FNDISPARSE *PFNDISPARSE;
340
341typedef struct _DISCPUSTATE
342{
343 /* Global setting */
344 uint32_t mode;
345
346 /* Per instruction prefix settings */
347 uint32_t prefix;
348 /** segment prefix value. */
349 uint32_t prefix_seg;
350 /** addressing mode (16 or 32 bits). (CPUMODE_*) */
351 uint32_t addrmode;
352 /** operand mode (16 or 32 bits). (CPUMODE_*) */
353 uint32_t opmode;
354
355 OP_PARAMETER param1;
356 OP_PARAMETER param2;
357 OP_PARAMETER param3;
358
359 /** ModRM byte. */
360 uint32_t ModRM;
361 /** scalar, index, base byte. */
362 uint32_t SIB;
363
364 int32_t disp;
365
366 /** First opcode byte of instruction. */
367 uint8_t opcode;
368 /** Last prefix byte (for SSE2 extension tables) */
369 uint8_t lastprefix;
370 RTUINTPTR opaddr;
371 uint32_t opsize;
372#ifndef DIS_CORE_ONLY
373 /** Opcode format string for current instruction. */
374 const char *pszOpcode;
375#endif
376
377 /** Internal: pointer to disassembly function table */
378 PFNDISPARSE *pfnDisasmFnTable;
379 /** Internal: instruction filter */
380 uint32_t uFilter;
381
382 /** Pointer to the current instruction. */
383 PCOPCODE pCurInstr;
384
385 void *apvUserData[3];
386
387 /** Optional read function */
388 PFN_DIS_READBYTES pfnReadBytes;
389#ifdef __L4ENV__
390 jmp_buf *pJumpBuffer;
391#endif /* __L4ENV__ */
392} DISCPUSTATE;
393
394/** Opcode. */
395#pragma pack(4)
396typedef struct _OPCODE
397{
398#ifndef DIS_CORE_ONLY
399 const char *pszOpcode;
400#endif
401 uint8_t idxParse1;
402 uint8_t idxParse2;
403 uint8_t idxParse3;
404 uint16_t opcode;
405 uint16_t param1;
406 uint16_t param2;
407 uint16_t param3;
408
409 uint32_t optype;
410} OPCODE;
411#pragma pack()
412
413
414/**
415 * Disassembles a code block.
416 *
417 * @returns VBox error code
418 * @param pCpu Pointer to cpu structure which have DISCPUSTATE::mode
419 * set correctly.
420 * @param pvCodeBlock Pointer to the strunction to disassemble.
421 * @param cbMax Maximum number of bytes to disassemble.
422 * @param pcbSize Where to store the size of the instruction.
423 * NULL is allowed.
424 *
425 *
426 * @todo Define output callback.
427 * @todo Using signed integers as sizes is a bit odd. There are still
428 * some GCC warnings about mixing signed and unsigend integers.
429 * @todo Need to extend this interface to include a code address so we
430 * can dissassemble GC code. Perhaps a new function is better...
431 * @remark cbMax isn't respected as a boundry. DISInstr() will read beyond cbMax.
432 * This means *pcbSize >= cbMax sometimes.
433 */
434DISDECL(int) DISBlock(PDISCPUSTATE pCpu, RTUINTPTR pvCodeBlock, unsigned cbMax, unsigned *pSize);
435
436/**
437 * Disassembles one instruction
438 *
439 * @returns VBox error code
440 * @param pCpu Pointer to cpu structure which have DISCPUSTATE::mode
441 * set correctly.
442 * @param pu8Instruction Pointer to the instrunction to disassemble.
443 * @param u32EipOffset Offset to add to instruction address to get the real virtual address
444 * @param pcbSize Where to store the size of the instruction.
445 * NULL is allowed.
446 * @param pszOutput Storage for disassembled instruction
447 *
448 * @todo Define output callback.
449 */
450DISDECL(int) DISInstr(PDISCPUSTATE pCpu, RTUINTPTR pu8Instruction, unsigned u32EipOffset, unsigned *pcbSize, char *pszOutput);
451
452/**
453 * Disassembles one instruction
454 *
455 * @returns VBox error code
456 * @param pCpu Pointer to cpu structure which have DISCPUSTATE::mode
457 * set correctly.
458 * @param pu8Instruction Pointer to the strunction to disassemble.
459 * @param u32EipOffset Offset to add to instruction address to get the real virtual address
460 * @param pcbSize Where to store the size of the instruction.
461 * NULL is allowed.
462 * @param pszOutput Storage for disassembled instruction
463 * @param uFilter Instruction type filter
464 *
465 * @todo Define output callback.
466 */
467DISDECL(int) DISInstrEx(PDISCPUSTATE pCpu, RTUINTPTR pu8Instruction, uint32_t u32EipOffset, uint32_t *pcbSize,
468 char *pszOutput, unsigned uFilter);
469
470/**
471 * Parses one instruction.
472 * The result is found in pCpu.
473 *
474 * @returns VBox error code
475 * @param pCpu Pointer to cpu structure which has DISCPUSTATE::mode set correctly.
476 * @param InstructionAddr Pointer to the instruction to parse.
477 * @param pcbInstruction Where to store the size of the instruction.
478 * NULL is allowed.
479 */
480DISDECL(int) DISCoreOne(PDISCPUSTATE pCpu, RTUINTPTR InstructionAddr, unsigned *pcbInstruction);
481
482/**
483 * Parses one guest instruction.
484 * * The result is found in pCpu and pcbInstruction.
485 *
486 * @returns VBox status code.
487 * @param InstructionAddr Address of the instruction to decode. What this means
488 * is left to the pfnReadBytes function.
489 * @param CpuMode The CPU mode. CPUMODE_32BIT, CPUMODE_16BIT, or CPUMODE_64BIT.
490 * @param pfnReadBytes Callback for reading instruction bytes.
491 * @param pvUser User argument for the instruction reader. (Ends up in dwUserData[0].)
492 * @param pCpu Pointer to cpu structure. Will be initialized.
493 * @param pcbInstruction Where to store the size of the instruction.
494 * NULL is allowed.
495 */
496DISDECL(int) DISCoreOneEx(RTUINTPTR InstructionAddr, unsigned CpuMode, PFN_DIS_READBYTES pfnReadBytes, void *pvUser,
497 PDISCPUSTATE pCpu, unsigned *pcbInstruction);
498
499DISDECL(int) DISGetParamSize(PDISCPUSTATE pCpu, POP_PARAMETER pParam);
500DISDECL(int) DISDetectSegReg(PDISCPUSTATE pCpu, POP_PARAMETER pParam);
501DISDECL(uint8_t) DISQuerySegPrefixByte(PDISCPUSTATE pCpu);
502
503/**
504 * Returns the value of the parameter in pParam
505 *
506 * @returns VBox error code
507 * @param pCtx Exception structure pointer
508 * @param pCpu Pointer to cpu structure which have DISCPUSTATE::mode
509 * set correctly.
510 * @param pParam Pointer to the parameter to parse
511 * @param pParamVal Pointer to parameter value (OUT)
512 * @param parmtype Parameter type
513 *
514 * @note Currently doesn't handle FPU/XMM/MMX/3DNow! parameters correctly!!
515 *
516 */
517DISDECL(int) DISQueryParamVal(PCPUMCTXCORE pCtx, PDISCPUSTATE pCpu, POP_PARAMETER pParam, POP_PARAMVAL pParamVal, PARAM_TYPE parmtype);
518
519DISDECL(int) DISFetchReg8(PCPUMCTXCORE pCtx, uint32_t reg8, uint8_t *pVal);
520DISDECL(int) DISFetchReg16(PCPUMCTXCORE pCtx, uint32_t reg16, uint16_t *pVal);
521DISDECL(int) DISFetchReg32(PCPUMCTXCORE pCtx, uint32_t reg32, uint32_t *pVal);
522DISDECL(int) DISFetchRegSeg(PCPUMCTXCORE pCtx, uint32_t sel, RTSEL *pVal);
523DISDECL(int) DISFetchRegSegEx(PCPUMCTXCORE pCtx, uint32_t sel, RTSEL *pVal, CPUMSELREGHID **ppSelHidReg);
524DISDECL(int) DISWriteReg8(PCPUMCTXCORE pRegFrame, uint32_t reg8, uint8_t val8);
525DISDECL(int) DISWriteReg16(PCPUMCTXCORE pRegFrame, uint32_t reg32, uint16_t val16);
526DISDECL(int) DISWriteReg32(PCPUMCTXCORE pRegFrame, uint32_t reg32, uint32_t val32);
527DISDECL(int) DISWriteRegSeg(PCPUMCTXCORE pCtx, uint32_t sel, RTSEL val);
528
529__END_DECLS
530
531#endif
532
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