disopcode-armv8.h@ 106626

Last change on this file since 106626 was 106626, checked in by vboxsync, 5 weeks ago
Disassembler: Re-arrange the ARMv8 tables to allow for multiple decoders for a single instruction class in case instructions in the same class require different decoding, implement decoding of 2-source instructions, bugref:10394
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1	/** @file
2	* Disassembler - Opcodes
3	*/
4
5	/*
6	* Copyright (C) 2023-2024 Oracle and/or its affiliates.
7	*
8	* This file is part of VirtualBox base platform packages, as
9	* available from https://www.virtualbox.org.
10	*
11	* This program is free software; you can redistribute it and/or
12	* modify it under the terms of the GNU General Public License
13	* as published by the Free Software Foundation, in version 3 of the
14	* License.
15	*
16	* This program is distributed in the hope that it will be useful, but
17	* WITHOUT ANY WARRANTY; without even the implied warranty of
18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19	* General Public License for more details.
20	*
21	* You should have received a copy of the GNU General Public License
22	* along with this program; if not, see <https://www.gnu.org/licenses>.
23	*
24	* The contents of this file may alternatively be used under the terms
25	* of the Common Development and Distribution License Version 1.0
26	* (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
27	* in the VirtualBox distribution, in which case the provisions of the
28	* CDDL are applicable instead of those of the GPL.
29	*
30	* You may elect to license modified versions of this file under the
31	* terms and conditions of either the GPL or the CDDL or both.
32	*
33	* SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
34	*/
35
36	#ifndef VBOX_INCLUDED_disopcode_armv8_h
37	#define VBOX_INCLUDED_disopcode_armv8_h
38	#ifndef RT_WITHOUT_PRAGMA_ONCE
39	# pragma once
40	#endif
41
42	#include <iprt/assert.h>
43
44	/** @defgroup grp_dis_opcodes_armv8 Opcodes (DISOPCODE::uOpCode)
45	* @ingroup grp_dis
46	* @{
47	*/
48	enum OPCODESARMV8
49	{
50	/** @name Full ARMv8 AArch64 opcode list.
51	* @{ */
52	OP_ARMV8_INVALID = 0,
53	OP_ARMV8_A64_ADC,
54	OP_ARMV8_A64_ADCS,
55	OP_ARMV8_A64_ADD,
56	OP_ARMV8_A64_ADDG,
57	OP_ARMV8_A64_ADDS,
58	OP_ARMV8_A64_ADR,
59	OP_ARMV8_A64_ADRP,
60	OP_ARMV8_A64_AND,
61	OP_ARMV8_A64_ANDS,
62	OP_ARMV8_A64_ASR,
63	OP_ARMV8_A64_ASRV,
64	OP_ARMV8_A64_AT,
65	OP_ARMV8_A64_AUTDA,
66	OP_ARMV8_A64_AUTDZA,
67	OP_ARMV8_A64_AUTDB,
68	OP_ARMV8_A64_AUTDZB,
69	OP_ARMV8_A64_AUTIA,
70	OP_ARMV8_A64_AUTIA1716,
71	OP_ARMV8_A64_AUTIASP,
72	OP_ARMV8_A64_AUTIAZ,
73	OP_ARMV8_A64_AUTIZA,
74	OP_ARMV8_A64_AUTIB,
75	OP_ARMV8_A64_AUTIB1716,
76	OP_ARMV8_A64_AUTIBSP,
77	OP_ARMV8_A64_AUTIBZ,
78	OP_ARMV8_A64_AUTIZB,
79	OP_ARMV8_A64_AXFLAG,
80	OP_ARMV8_A64_B,
81	OP_ARMV8_A64_BC,
82	OP_ARMV8_A64_BFC,
83	OP_ARMV8_A64_BFI,
84	OP_ARMV8_A64_BFM,
85	OP_ARMV8_A64_BFXIL,
86	OP_ARMV8_A64_BIC,
87	OP_ARMV8_A64_BICS,
88	OP_ARMV8_A64_BL,
89	OP_ARMV8_A64_BLR,
90	OP_ARMV8_A64_BLRAA,
91	OP_ARMV8_A64_BLRAAZ,
92	OP_ARMV8_A64_BLRAB,
93	OP_ARMV8_A64_BLRABZ,
94	OP_ARMV8_A64_BR,
95	OP_ARMV8_A64_BRAA,
96	OP_ARMV8_A64_BRAAZ,
97	OP_ARMV8_A64_BRAB,
98	OP_ARMV8_A64_BRABZ,
99	OP_ARMV8_A64_BRB,
100	OP_ARMV8_A64_BRK,
101	OP_ARMV8_A64_BTI,
102	OP_ARMV8_A64_CASB,
103	OP_ARMV8_A64_CASAB,
104	OP_ARMV8_A64_CASALB,
105	OP_ARMV8_A64_CASLB,
106	OP_ARMV8_A64_CASH,
107	OP_ARMV8_A64_CASAH,
108	OP_ARMV8_A64_CASALH,
109	OP_ARMV8_A64_CASLH,
110	OP_ARMV8_A64_CASP,
111	OP_ARMV8_A64_CASPA,
112	OP_ARMV8_A64_CASPAL,
113	OP_ARMV8_A64_CASPL,
114	OP_ARMV8_A64_CAS,
115	OP_ARMV8_A64_CASA,
116	OP_ARMV8_A64_CASAL,
117	OP_ARMV8_A64_CASL,
118	OP_ARMV8_A64_CBNZ,
119	OP_ARMV8_A64_CBZ,
120	OP_ARMV8_A64_CCMN,
121	OP_ARMV8_A64_CCMP,
122	OP_ARMV8_A64_CFINV,
123	OP_ARMV8_A64_CFP,
124	OP_ARMV8_A64_CINC,
125	OP_ARMV8_A64_CINV,
126	OP_ARMV8_A64_CLREX,
127	OP_ARMV8_A64_CLS,
128	OP_ARMV8_A64_CLZ,
129	OP_ARMV8_A64_CMN,
130	OP_ARMV8_A64_CMP,
131	OP_ARMV8_A64_CMPP,
132	OP_ARMV8_A64_CNEG,
133	OP_ARMV8_A64_CPP,
134	/** @todo FEAT_MOPS instructions (CPYFP and friends). */
135	OP_ARMV8_A64_CRC32B,
136	OP_ARMV8_A64_CRC32H,
137	OP_ARMV8_A64_CRC32W,
138	OP_ARMV8_A64_CRC32X,
139	OP_ARMV8_A64_CRC32CB,
140	OP_ARMV8_A64_CRC32CH,
141	OP_ARMV8_A64_CRC32CW,
142	OP_ARMV8_A64_CRC32CX,
143	OP_ARMV8_A64_CSDB,
144	OP_ARMV8_A64_CSEL,
145	OP_ARMV8_A64_CSET,
146	OP_ARMV8_A64_CSETM,
147	OP_ARMV8_A64_CSINC,
148	OP_ARMV8_A64_CSNEG,
149	OP_ARMV8_A64_DC,
150	OP_ARMV8_A64_DCPS1,
151	OP_ARMV8_A64_DCPS2,
152	OP_ARMV8_A64_DCPS3,
153	OP_ARMV8_A64_DGH,
154	OP_ARMV8_A64_DMB,
155	OP_ARMV8_A64_DRPS,
156	OP_ARMV8_A64_DSB,
157	OP_ARMV8_A64_DVP,
158	OP_ARMV8_A64_EON,
159	OP_ARMV8_A64_EOR,
160	OP_ARMV8_A64_ERET,
161	OP_ARMV8_A64_ERETAA,
162	OP_ARMV8_A64_ERETAB,
163	OP_ARMV8_A64_ESB,
164	OP_ARMV8_A64_EXTR,
165	OP_ARMV8_A64_FABS,
166	OP_ARMV8_A64_FADD,
167	OP_ARMV8_A64_FCCMP,
168	OP_ARMV8_A64_FCCMPE,
169	OP_ARMV8_A64_FCMP,
170	OP_ARMV8_A64_FCMPE,
171	OP_ARMV8_A64_FCSEL,
172	OP_ARMV8_A64_FCVT,
173	OP_ARMV8_A64_FCVTZS,
174	OP_ARMV8_A64_FCVTZU,
175	OP_ARMV8_A64_FDIV,
176	OP_ARMV8_A64_FMADD,
177	OP_ARMV8_A64_FMAX,
178	OP_ARMV8_A64_FMAXNM,
179	OP_ARMV8_A64_FMIN,
180	OP_ARMV8_A64_FMINNM,
181	OP_ARMV8_A64_FMOV,
182	OP_ARMV8_A64_FMSUB,
183	OP_ARMV8_A64_FMUL,
184	OP_ARMV8_A64_FNEG,
185	OP_ARMV8_A64_FNMADD,
186	OP_ARMV8_A64_FNMSUB,
187	OP_ARMV8_A64_FNMUL,
188	OP_ARMV8_A64_FRINT32X,
189	OP_ARMV8_A64_FRINT32Z,
190	OP_ARMV8_A64_FRINT64X,
191	OP_ARMV8_A64_FRINT64Z,
192	OP_ARMV8_A64_FRINTA,
193	OP_ARMV8_A64_FRINTI,
194	OP_ARMV8_A64_FRINTM,
195	OP_ARMV8_A64_FRINTN,
196	OP_ARMV8_A64_FRINTP,
197	OP_ARMV8_A64_FRINTX,
198	OP_ARMV8_A64_FRINTZ,
199	OP_ARMV8_A64_FSQRT,
200	OP_ARMV8_A64_FSUB,
201	OP_ARMV8_A64_GMI,
202	OP_ARMV8_A64_HINT,
203	OP_ARMV8_A64_HLT,
204	OP_ARMV8_A64_HVC,
205	OP_ARMV8_A64_IC,
206	OP_ARMV8_A64_IRG,
207	OP_ARMV8_A64_ISB,
208	OP_ARMV8_A64_LD64B,
209	OP_ARMV8_A64_LDADDB,
210	OP_ARMV8_A64_LDADDAB,
211	OP_ARMV8_A64_LDADDALB,
212	OP_ARMV8_A64_LDADDLB,
213	OP_ARMV8_A64_LDADDH,
214	OP_ARMV8_A64_LDADDAH,
215	OP_ARMV8_A64_LDADDALH,
216	OP_ARMV8_A64_LDADDLH,
217	OP_ARMV8_A64_LDADD,
218	OP_ARMV8_A64_LDADDA,
219	OP_ARMV8_A64_LDADDAL,
220	OP_ARMV8_A64_LDADDL,
221	OP_ARMV8_A64_LDAPR,
222	OP_ARMV8_A64_LDAPRB,
223	OP_ARMV8_A64_LDAPRH,
224	OP_ARMV8_A64_LDAPUR,
225	OP_ARMV8_A64_LDAPURB,
226	OP_ARMV8_A64_LDAPURH,
227	OP_ARMV8_A64_LDAPURSB,
228	OP_ARMV8_A64_LDAPURSH,
229	OP_ARMV8_A64_LDAPURSW,
230	OP_ARMV8_A64_LDAR,
231	OP_ARMV8_A64_LDARB,
232	OP_ARMV8_A64_LDARH,
233	OP_ARMV8_A64_LDAXP,
234	OP_ARMV8_A64_LDAXRB,
235	OP_ARMV8_A64_LDAXRH,
236	OP_ARMV8_A64_LDCLRB,
237	OP_ARMV8_A64_LDCLRAB,
238	OP_ARMV8_A64_LDCLRALB,
239	OP_ARMV8_A64_LDCLRLB,
240	OP_ARMV8_A64_LDCLRH,
241	OP_ARMV8_A64_LDCLRAH,
242	OP_ARMV8_A64_LDCLRALH,
243	OP_ARMV8_A64_LDCLRLH,
244	OP_ARMV8_A64_LDCLR,
245	OP_ARMV8_A64_LDCLRA,
246	OP_ARMV8_A64_LDCLRAL,
247	OP_ARMV8_A64_LDCLRL,
248	OP_ARMV8_A64_LDEORB,
249	OP_ARMV8_A64_LDEORAB,
250	OP_ARMV8_A64_LDEORALB,
251	OP_ARMV8_A64_LDEORLB,
252	OP_ARMV8_A64_LDEORH,
253	OP_ARMV8_A64_LDEORAH,
254	OP_ARMV8_A64_LDEORALH,
255	OP_ARMV8_A64_LDEORLH,
256	OP_ARMV8_A64_LDEOR,
257	OP_ARMV8_A64_LDEORA,
258	OP_ARMV8_A64_LDEORAL,
259	OP_ARMV8_A64_LDEORL,
260	OP_ARMV8_A64_LDG,
261	OP_ARMV8_A64_LDGM,
262	OP_ARMV8_A64_LDLARB,
263	OP_ARMV8_A64_LDLARH,
264	OP_ARMV8_A64_LDLAR,
265	OP_ARMV8_A64_LDNP,
266	OP_ARMV8_A64_LDP,
267	OP_ARMV8_A64_LDPSW,
268	OP_ARMV8_A64_LDR,
269	OP_ARMV8_A64_LDRAA,
270	OP_ARMV8_A64_LDRAB,
271	OP_ARMV8_A64_LDRB,
272	OP_ARMV8_A64_LDRH,
273	OP_ARMV8_A64_LDRSB,
274	OP_ARMV8_A64_LDRSH,
275	OP_ARMV8_A64_LDRSW,
276	OP_ARMV8_A64_LDSETB,
277	OP_ARMV8_A64_LDSETAB,
278	OP_ARMV8_A64_LDSETALB,
279	OP_ARMV8_A64_LDSETLB,
280	OP_ARMV8_A64_LDSETH,
281	OP_ARMV8_A64_LDSETAH,
282	OP_ARMV8_A64_LDSETALH,
283	OP_ARMV8_A64_LDSETLH,
284	OP_ARMV8_A64_LDSET,
285	OP_ARMV8_A64_LDSETA,
286	OP_ARMV8_A64_LDSETAL,
287	OP_ARMV8_A64_LDSETL,
288	OP_ARMV8_A64_LDSMAB,
289	OP_ARMV8_A64_LDSMAXAB,
290	OP_ARMV8_A64_LDSMAXALB,
291	OP_ARMV8_A64_LDSMAXLB,
292	OP_ARMV8_A64_LDSMAXH,
293	OP_ARMV8_A64_LDSMAXAH,
294	OP_ARMV8_A64_LDSMAXALH,
295	OP_ARMV8_A64_LDSMAXLH,
296	OP_ARMV8_A64_LDSMAX,
297	OP_ARMV8_A64_LDSMAXA,
298	OP_ARMV8_A64_LDSMAXAL,
299	OP_ARMV8_A64_LDSMAXL,
300	OP_ARMV8_A64_LDSMINB,
301	OP_ARMV8_A64_LDSMINAB,
302	OP_ARMV8_A64_LDSMINALB,
303	OP_ARMV8_A64_LDSMINLB,
304	OP_ARMV8_A64_LDSMINH,
305	OP_ARMV8_A64_LDSMINAH,
306	OP_ARMV8_A64_LDSMINALH,
307	OP_ARMV8_A64_LDSMINLH,
308	OP_ARMV8_A64_LDSMIN,
309	OP_ARMV8_A64_LDSMINA,
310	OP_ARMV8_A64_LDSMINAL,
311	OP_ARMV8_A64_LDSMINL,
312	OP_ARMV8_A64_LDTR,
313	OP_ARMV8_A64_LDTRB,
314	OP_ARMV8_A64_LDTRH,
315	OP_ARMV8_A64_LDTRSB,
316	OP_ARMV8_A64_LDTRSH,
317	OP_ARMV8_A64_LDTRSW,
318	OP_ARMV8_A64_LDUMAXB,
319	OP_ARMV8_A64_LDUMAXAB,
320	OP_ARMV8_A64_LDUMAXALB,
321	OP_ARMV8_A64_LDUMAXLB,
322	OP_ARMV8_A64_LDUMAXH,
323	OP_ARMV8_A64_LDUMAXAH,
324	OP_ARMV8_A64_LDUMAXALH,
325	OP_ARMV8_A64_LDUMAXLH,
326	OP_ARMV8_A64_LDUMAX,
327	OP_ARMV8_A64_LDUMAXA,
328	OP_ARMV8_A64_LDUMAXAL,
329	OP_ARMV8_A64_LDUMAXL,
330	OP_ARMV8_A64_LDUMINB,
331	OP_ARMV8_A64_LDUMINAB,
332	OP_ARMV8_A64_LDUMINALB,
333	OP_ARMV8_A64_LDUMINLB,
334	OP_ARMV8_A64_LDUMINH,
335	OP_ARMV8_A64_LDUMINAH,
336	OP_ARMV8_A64_LDUMINALH,
337	OP_ARMV8_A64_LDUMINLH,
338	OP_ARMV8_A64_LDUMIN,
339	OP_ARMV8_A64_LDUMINA,
340	OP_ARMV8_A64_LDUMINAL,
341	OP_ARMV8_A64_LDUMINL,
342	OP_ARMV8_A64_LDUR,
343	OP_ARMV8_A64_LDURB,
344	OP_ARMV8_A64_LDURH,
345	OP_ARMV8_A64_LDURSB,
346	OP_ARMV8_A64_LDURSH,
347	OP_ARMV8_A64_LDURSW,
348	OP_ARMV8_A64_LDXP,
349	OP_ARMV8_A64_LDXR,
350	OP_ARMV8_A64_LDXRB,
351	OP_ARMV8_A64_LDXRH,
352	OP_ARMV8_A64_LSL,
353	OP_ARMV8_A64_LSLV,
354	OP_ARMV8_A64_LSR,
355	OP_ARMV8_A64_LSRV,
356	OP_ARMV8_A64_MADD,
357	OP_ARMV8_A64_MNEG,
358	OP_ARMV8_A64_MOV,
359	OP_ARMV8_A64_MOVK,
360	OP_ARMV8_A64_MOVN,
361	OP_ARMV8_A64_MOVZ,
362	OP_ARMV8_A64_MRS,
363	OP_ARMV8_A64_MSR,
364	OP_ARMV8_A64_MSUB,
365	OP_ARMV8_A64_MUL,
366	OP_ARMV8_A64_MVN,
367	OP_ARMV8_A64_NEG,
368	OP_ARMV8_A64_NEGS,
369	OP_ARMV8_A64_NGC,
370	OP_ARMV8_A64_NGCS,
371	OP_ARMV8_A64_NOP,
372	OP_ARMV8_A64_ORR,
373	OP_ARMV8_A64_ORN,
374	OP_ARMV8_A64_PACDA,
375	OP_ARMV8_A64_PACDZA,
376	OP_ARMV8_A64_PACDB,
377	OP_ARMV8_A64_PACDZB,
378	OP_ARMV8_A64_PACGA,
379	OP_ARMV8_A64_PACIA,
380	OP_ARMV8_A64_PACIA1716,
381	OP_ARMV8_A64_PACIASP,
382	OP_ARMV8_A64_PACIAZ,
383	OP_ARMV8_A64_PACIZA,
384	OP_ARMV8_A64_PACIB,
385	OP_ARMV8_A64_PACIB1716,
386	OP_ARMV8_A64_PACIBSP,
387	OP_ARMV8_A64_PACIBZ,
388	OP_ARMV8_A64_PACIBZB,
389	OP_ARMV8_A64_PRFM,
390	OP_ARMV8_A64_PRFUM,
391	OP_ARMV8_A64_PSBSYNC,
392	OP_ARMV8_A64_PSSBB,
393	OP_ARMV8_A64_RBIT,
394	OP_ARMV8_A64_RET,
395	OP_ARMV8_A64_RETAA,
396	OP_ARMV8_A64_RETAB,
397	OP_ARMV8_A64_REV,
398	OP_ARMV8_A64_REV16,
399	OP_ARMV8_A64_REV32,
400	OP_ARMV8_A64_RMIF,
401	OP_ARMV8_A64_ROR,
402	OP_ARMV8_A64_RORV,
403	OP_ARMV8_A64_SB,
404	OP_ARMV8_A64_SBC,
405	OP_ARMV8_A64_SBCS,
406	OP_ARMV8_A64_SBFIZ,
407	OP_ARMV8_A64_SBFM,
408	OP_ARMV8_A64_SBFX,
409	OP_ARMV8_A64_SCVTF,
410	OP_ARMV8_A64_SDIV,
411	OP_ARMV8_A64_SETF8,
412	OP_ARMV8_A64_SETF16,
413	OP_ARMV8_A64_SETGP,
414	OP_ARMV8_A64_SETGM,
415	OP_ARMV8_A64_SETGE,
416	OP_ARMV8_A64_SETGPN,
417	OP_ARMV8_A64_SETGMN,
418	OP_ARMV8_A64_SETGEN,
419	OP_ARMV8_A64_SETGPT,
420	OP_ARMV8_A64_SETGMT,
421	OP_ARMV8_A64_SETGET,
422	OP_ARMV8_A64_SETGPTN,
423	OP_ARMV8_A64_SETGMTN,
424	OP_ARMV8_A64_SETGETN,
425	OP_ARMV8_A64_SETP,
426	OP_ARMV8_A64_SETM,
427	OP_ARMV8_A64_SETE,
428	OP_ARMV8_A64_SETPN,
429	OP_ARMV8_A64_SETMNM,
430	OP_ARMV8_A64_SETEN,
431	OP_ARMV8_A64_SETPT,
432	OP_ARMV8_A64_SETMT,
433	OP_ARMV8_A64_SETET,
434	OP_ARMV8_A64_SETPTN,
435	OP_ARMV8_A64_SETMTN,
436	OP_ARMV8_A64_SETETN,
437	OP_ARMV8_A64_SEV,
438	OP_ARMV8_A64_SEVL,
439	OP_ARMV8_A64_SHL,
440	OP_ARMV8_A64_SMADDL,
441	OP_ARMV8_A64_SMAX,
442	OP_ARMV8_A64_SMC,
443	OP_ARMV8_A64_SMIN,
444	OP_ARMV8_A64_SMNEGL,
445	OP_ARMV8_A64_SMSTART,
446	OP_ARMV8_A64_SMSTOP,
447	OP_ARMV8_A64_SMSUBL,
448	OP_ARMV8_A64_SMULH,
449	OP_ARMV8_A64_SMULL,
450	OP_ARMV8_A64_SQRSHRN,
451	OP_ARMV8_A64_SQSHL,
452	OP_ARMV8_A64_SQSHRN,
453	OP_ARMV8_A64_SRSHR,
454	OP_ARMV8_A64_SRSRA,
455	OP_ARMV8_A64_SSBB,
456	OP_ARMV8_A64_SSHR,
457	OP_ARMV8_A64_SSRA,
458	OP_ARMV8_A64_ST2G,
459	OP_ARMV8_A64_ST64B,
460	OP_ARMV8_A64_ST64BV0,
461	OP_ARMV8_A64_STADDB,
462	OP_ARMV8_A64_STADDLB,
463	OP_ARMV8_A64_STADDH,
464	OP_ARMV8_A64_STADDLH,
465	OP_ARMV8_A64_STADD,
466	OP_ARMV8_A64_STADDL,
467	OP_ARMV8_A64_STCLRB,
468	OP_ARMV8_A64_STCLRLB,
469	OP_ARMV8_A64_STCLRH,
470	OP_ARMV8_A64_STCLRLH,
471	OP_ARMV8_A64_STCLR,
472	OP_ARMV8_A64_STCLRL,
473	OP_ARMV8_A64_STEORB,
474	OP_ARMV8_A64_STEROLB,
475	OP_ARMV8_A64_STEORH,
476	OP_ARMV8_A64_STEORLH,
477	OP_ARMV8_A64_STEOR,
478	OP_ARMV8_A64_STEORL,
479	OP_ARMV8_A64_STG,
480	OP_ARMV8_A64_STGM,
481	OP_ARMV8_A64_STGP,
482	OP_ARMV8_A64_STLLRB,
483	OP_ARMV8_A64_STLLRH,
484	OP_ARMV8_A64_STLLR,
485	OP_ARMV8_A64_STLR,
486	OP_ARMV8_A64_STLRB,
487	OP_ARMV8_A64_STLRH,
488	OP_ARMV8_A64_STLUR,
489	OP_ARMV8_A64_STLURB,
490	OP_ARMV8_A64_STLURH,
491	OP_ARMV8_A64_STLXP,
492	OP_ARMV8_A64_STLXR,
493	OP_ARMV8_A64_STLXRB,
494	OP_ARMV8_A64_STLXRH,
495	OP_ARMV8_A64_STNP,
496	OP_ARMV8_A64_STP,
497	OP_ARMV8_A64_STR,
498	OP_ARMV8_A64_STRB,
499	OP_ARMV8_A64_STRH,
500	OP_ARMV8_A64_STTR,
501	OP_ARMV8_A64_STTRB,
502	OP_ARMV8_A64_STTRH,
503	OP_ARMV8_A64_STUR,
504	OP_ARMV8_A64_STURB,
505	OP_ARMV8_A64_STURH,
506	OP_ARMV8_A64_STXP,
507	OP_ARMV8_A64_STXR,
508	OP_ARMV8_A64_STXRB,
509	OP_ARMV8_A64_STXRH,
510	OP_ARMV8_A64_STZ2G,
511	OP_ARMV8_A64_STZG,
512	OP_ARMV8_A64_STZGM,
513	OP_ARMV8_A64_SUB,
514	OP_ARMV8_A64_SUBG,
515	OP_ARMV8_A64_SUBPS,
516	OP_ARMV8_A64_SUBS,
517	OP_ARMV8_A64_SVC,
518	OP_ARMV8_A64_SWPB,
519	OP_ARMV8_A64_SWPAB,
520	OP_ARMV8_A64_SWPALB,
521	OP_ARMV8_A64_SWPLB,
522	OP_ARMV8_A64_SWPH,
523	OP_ARMV8_A64_SWPAH,
524	OP_ARMV8_A64_SWPALH,
525	OP_ARMV8_A64_SWPLH,
526	OP_ARMV8_A64_SWP,
527	OP_ARMV8_A64_SWPA,
528	OP_ARMV8_A64_SWPAL,
529	OP_ARMV8_A64_SWPL,
530	OP_ARMV8_A64_SXTB,
531	OP_ARMV8_A64_SXTH,
532	OP_ARMV8_A64_SXTW,
533	OP_ARMV8_A64_SYS,
534	OP_ARMV8_A64_SYSL,
535	OP_ARMV8_A64_TBNZ,
536	OP_ARMV8_A64_TBZ,
537	OP_ARMV8_A64_TCANCEL,
538	OP_ARMV8_A64_TCOMMIT,
539	OP_ARMV8_A64_TLBI,
540	OP_ARMV8_A64_TSTART,
541	OP_ARMV8_A64_TTEST,
542	OP_ARMV8_A64_TSBCSYNC,
543	OP_ARMV8_A64_TST,
544	OP_ARMV8_A64_UBFIZ,
545	OP_ARMV8_A64_UBFM,
546	OP_ARMV8_A64_UBFX,
547	OP_ARMV8_A64_UCVTF,
548	OP_ARMV8_A64_UDF,
549	OP_ARMV8_A64_UDIV,
550	OP_ARMV8_A64_UMADDL,
551	OP_ARMV8_A64_UMAX,
552	OP_ARMV8_A64_UMIN,
553	OP_ARMV8_A64_UMNEGL,
554	OP_ARMV8_A64_UMSUBL,
555	OP_ARMV8_A64_UMULH,
556	OP_ARMV8_A64_UMULL,
557	OP_ARMV8_A64_UXTB,
558	OP_ARMV8_A64_UXTH,
559	OP_ARMV8_A64_WFE,
560	OP_ARMV8_A64_WFET,
561	OP_ARMV8_A64_WFI,
562	OP_ARMV8_A64_WFIT,
563	OP_ARMV8_A64_XAFLAG,
564	OP_ARMV8_A64_XPACD,
565	OP_ARMV8_A64_XPACI,
566	OP_ARMV8_A64_XPACLRI,
567	OP_ARMV8_A64_YIELD,
568	/** @} */
569
570	OP_ARMV8_END_OF_OPCODES
571	};
572
573
574	/** Armv8 Condition codes. */
575	typedef enum DISARMV8INSTRCOND
576	{
577	kDisArmv8InstrCond_Eq = 0, /*< 0 - Equal - Zero set. /
578	kDisArmv8InstrCond_Ne, /*< 1 - Not equal - Zero clear. /
579
580	kDisArmv8InstrCond_Cs, /*< 2 - Carry set (also known as 'HS'). /
581	kDisArmv8InstrCond_Hs = kDisArmv8InstrCond_Cs, /*< 2 - Unsigned higher or same. /
582	kDisArmv8InstrCond_Cc, /*< 3 - Carry clear (also known as 'LO'). /
583	kDisArmv8InstrCond_Lo = kDisArmv8InstrCond_Cc, /*< 3 - Unsigned lower. /
584
585	kDisArmv8InstrCond_Mi, /*< 4 - Negative result (minus). /
586	kDisArmv8InstrCond_Pl, /*< 5 - Positive or zero result (plus). /
587
588	kDisArmv8InstrCond_Vs, /*< 6 - Overflow set. /
589	kDisArmv8InstrCond_Vc, /*< 7 - Overflow clear. /
590
591	kDisArmv8InstrCond_Hi, /*< 8 - Unsigned higher. /
592	kDisArmv8InstrCond_Ls, /*< 9 - Unsigned lower or same. /
593
594	kDisArmv8InstrCond_Ge, /*< a - Signed greater or equal. /
595	kDisArmv8InstrCond_Lt, /*< b - Signed less than. /
596
597	kDisArmv8InstrCond_Gt, /*< c - Signed greater than. /
598	kDisArmv8InstrCond_Le, /*< d - Signed less or equal. /
599
600	kDisArmv8InstrCond_Al, /*< e - Condition is always true. /
601	kDisArmv8InstrCond_Al1 /*< f - Condition is always true. /
602	} DISARMV8INSTRCOND;
603
604
605	/** Armv8 PState fields. */
606	typedef enum DISARMV8INSTRPSTATE
607	{
608	kDisArmv8InstrPState_SPSel = 0,
609	kDisArmv8InstrPState_DAIFSet,
610	kDisArmv8InstrPState_DAIFClr,
611	kDisArmv8InstrPState_UAO,
612	kDisArmv8InstrPState_PAN,
613	kDisArmv8InstrPState_ALLINT,
614	kDisArmv8InstrPState_PM,
615	kDisArmv8InstrPState_SSBS,
616	kDisArmv8InstrPState_DIT,
617	kDisArmv8InstrPState_SVCRSM,
618	kDisArmv8InstrPState_SVCRZA,
619	kDisArmv8InstrPState_SVCRSMZA,
620	kDisArmv8InstrPState_TCO
621	} DISARMV8INSTRPSTATE;
622
623
624	/**
625	* Floating point types.
626	*/
627	typedef enum DISARMV8INSTRFPTYPE
628	{
629	kDisArmv8InstrFpType_Invalid = 0,
630	kDisArmv8InstrFpType_Single,
631	kDisArmv8InstrFpType_Double,
632	kDisArmv8InstrFpType_Half
633	} DISARMV8INSTRFPTYPE;
634
635
636	/** @defgroup grp_dis_opparam_armv8 Opcode parameters (DISOPCODE::fParam1,
637	* DISOPCODE::fParam2, DISOPCODE::fParam3)
638	* @ingroup grp_dis
639	* @{
640	*/
641
642	/**
643	* Basic parameter type.
644	*/
645	typedef enum DISARMV8OPPARM
646	{
647	/** Parameter is not used. */
648	kDisArmv8OpParmNone = 0,
649	/** Immediate value. */
650	kDisArmv8OpParmImm,
651	/** Relative address immediate. */
652	kDisArmv8OpParmImmRel,
653	/** Register. */
654	kDisArmv8OpParmReg,
655	/** System register. */
656	kDisArmv8OpParmSysReg,
657	/** Accessing memory from address in base register + potential offset. */
658	kDisArmv8OpParmAddrInGpr,
659	/** Conditional as parameter (CCMN/CCMP). */
660	kDisArmv8OpParmCond,
661	/** PSTATE field (specific to MSR). */
662	kDisArmv8OpParmPState
663	} DISARMV8OPPARM;
664
665
666	/**
667	* Extend types.
668	*/
669	typedef enum DISARMV8OPPARMEXTEND
670	{
671	/** No shift applied. */
672	kDisArmv8OpParmExtendNone = 0,
673	/** Left shift applied. */
674	kDisArmv8OpParmExtendLsl,
675	/** Right shift applied. */
676	kDisArmv8OpParmExtendLsr,
677	/** Arithmetic right shift applied. */
678	kDisArmv8OpParmExtendAsr,
679	/** Rotation applied. */
680	kDisArmv8OpParmExtendRor,
681	/** @todo Document. */
682	kDisArmv8OpParmExtendUxtB,
683	kDisArmv8OpParmExtendUxtH,
684	kDisArmv8OpParmExtendUxtW,
685	kDisArmv8OpParmExtendUxtX,
686	kDisArmv8OpParmExtendSxtB,
687	kDisArmv8OpParmExtendSxtH,
688	kDisArmv8OpParmExtendSxtW,
689	kDisArmv8OpParmExtendSxtX
690	} DISARMV8OPPARMEXTEND;
691	/** @} */
692
693	/** @} */
694
695	#endif /* !VBOX_INCLUDED_disopcode_armv8_h */
696

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source: vbox/trunk/include/VBox/disopcode-armv8.h@ 106626

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