disopcode.h@ 95440

Last change on this file since 95440 was 95440, checked in by vboxsync, 2 years ago
DIS: VANDPS, VANDPD, VPAND, VANDNPS, VANDNPD, VPANDN, VORPS, VORPD, AND VPOR opcode enum values. bugref:9898 bugref:6251
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 28.9 KB

Line
1	/** @file
2	* Disassembler - Opcodes
3	*/
4
5	/*
6	* Copyright (C) 2006-2022 Oracle Corporation
7	*
8	* This file is part of VirtualBox Open Source Edition (OSE), as
9	* available from http://www.virtualbox.org. This file is free software;
10	* you can redistribute it and/or modify it under the terms of the GNU
11	* General Public License (GPL) as published by the Free Software
12	* Foundation, in version 2 as it comes in the "COPYING" file of the
13	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15	*
16	* The contents of this file may alternatively be used under the terms
17	* of the Common Development and Distribution License Version 1.0
18	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19	* VirtualBox OSE distribution, in which case the provisions of the
20	* CDDL are applicable instead of those of the GPL.
21	*
22	* You may elect to license modified versions of this file under the
23	* terms and conditions of either the GPL or the CDDL or both.
24	*/
25
26	#ifndef VBOX_INCLUDED_disopcode_h
27	#define VBOX_INCLUDED_disopcode_h
28	#ifndef RT_WITHOUT_PRAGMA_ONCE
29	# pragma once
30	#endif
31
32	#include <iprt/assert.h>
33
34	#define MODRM_MOD(a) (a>>6)
35	#define MODRM_REG(a) ((a>>3)&0x7)
36	#define MODRM_RM(a) (a&0x7)
37	#define MAKE_MODRM(mod, reg, rm) (((mod&3) << 6) \| ((reg&7) << 3) \| (rm&7))
38
39	#define SIB_SCALE(a) (a>>6)
40	#define SIB_INDEX(a) ((a>>3)&0x7)
41	#define SIB_BASE(a) (a&0x7)
42
43
44	/** @defgroup grp_dis_opcodes Opcodes (DISOPCODE::uOpCode)
45	* @ingroup grp_dis
46	* @{
47	*/
48	enum OPCODES
49	{
50	/** @name Full Intel X86 opcode list
51	* @{ */
52	OP_INVALID = 0,
53	OP_OPSIZE,
54	OP_ADDRSIZE,
55	OP_SEG,
56	OP_REPNE,
57	OP_REPE,
58	OP_REX,
59	OP_LOCK,
60	#ifndef IN_SLICKEDIT
61	OP_LAST_PREFIX = OP_LOCK, /*< Last prefix for disassembler. /
62	#else
63	OP_LAST_PREFIX = 7, /*< Last prefix for disassembler. /
64	#endif
65	OP_AND,
66	OP_OR,
67	OP_DAA,
68	OP_SUB,
69	OP_DAS,
70	OP_XOR,
71	OP_AAA,
72	OP_CMP,
73	OP_IMM_GRP1,
74	OP_AAS,
75	OP_INC,
76	OP_DEC,
77	OP_PUSHA,
78	OP_POPA,
79	OP_BOUND,
80	OP_ARPL,
81	OP_PUSH,
82	OP_POP,
83	OP_IMUL,
84	OP_INSB,
85	OP_INSWD,
86	OP_OUTSB,
87	OP_OUTSWD,
88	OP_JO,
89	OP_JNO,
90	OP_JC,
91	OP_JNC,
92	OP_JE,
93	OP_JNE,
94	OP_JBE,
95	OP_JNBE,
96	OP_JS,
97	OP_JNS,
98	OP_JP,
99	OP_JNP,
100	OP_JL,
101	OP_JNL,
102	OP_JLE,
103	OP_JNLE,
104	OP_ADD,
105	OP_TEST,
106	OP_XCHG,
107	OP_MOV,
108	OP_LEA,
109	OP_NOP,
110	OP_CBW,
111	OP_CWD,
112	OP_CALL,
113	OP_WAIT,
114	OP_PUSHF,
115	OP_POPF,
116	OP_SAHF,
117	OP_LAHF,
118	OP_MOVSB,
119	OP_MOVSWD,
120	OP_CMPSB,
121	OP_CMPWD,
122	OP_STOSB,
123	OP_STOSWD,
124	OP_LODSB,
125	OP_LODSWD,
126	OP_SCASB,
127	OP_SCASWD,
128	OP_SHIFT_GRP2,
129	OP_RETN,
130	OP_LES,
131	OP_LDS,
132	OP_ENTER,
133	OP_LEAVE,
134	OP_RETF,
135	OP_INT1,
136	OP_INT3,
137	OP_INT,
138	OP_INTO,
139	OP_IRET,
140	OP_AAM,
141	OP_AAD,
142	OP_XLAT,
143	OP_ESCF0,
144	OP_ESCF1,
145	OP_ESCF2,
146	OP_ESCF3,
147	OP_ESCF4,
148	OP_ESCF5,
149	OP_ESCF6,
150	OP_ESCF7,
151	OP_LOOPNE,
152	OP_LOOPE,
153	OP_LOOP,
154	OP_JECXZ,
155	OP_IN,
156	OP_OUT,
157	OP_JMP,
158	OP_2B_ESC,
159	OP_ADC,
160	OP_SBB,
161	OP_HLT,
162	OP_CMC,
163	OP_UNARY_GRP3,
164	OP_CLC,
165	OP_STC,
166	OP_CLI,
167	OP_STI,
168	OP_CLD,
169	OP_STD,
170	OP_INC_GRP4,
171	OP_IND_GRP5,
172	OP_GRP6,
173	OP_GRP7,
174	OP_LAR,
175	OP_LSL,
176	OP_SYSCALL,
177	OP_CLTS,
178	OP_SYSRET,
179	OP_INVD,
180	OP_WBINVD,
181	OP_ILLUD2,
182	OP_FEMMS,
183	OP_3DNOW,
184	OP_MOVUPS,
185	OP_MOVLPS,
186	OP_MOVHLPS = OP_MOVLPS, /*< @todo OP_MOVHLPS /
187	OP_UNPCKLPS,
188	OP_MOVHPS,
189	OP_MOVLHPS = OP_MOVHPS, /*< @todo OP_MOVLHPS /
190	OP_UNPCKHPS,
191	OP_PREFETCH_GRP16,
192	OP_MOV_CR,
193	OP_MOVAPS,
194	OP_CVTPI2PS,
195	OP_MOVNTPS,
196	OP_CVTTPS2PI,
197	OP_CVTPS2PI,
198	OP_UCOMISS,
199	OP_COMISS,
200	OP_WRMSR,
201	OP_RDTSC,
202	OP_RDMSR,
203	OP_RDPMC,
204	OP_SYSENTER,
205	OP_SYSEXIT,
206	OP_GETSEC,
207	OP_PAUSE,
208	OP_CMOVO,
209	OP_CMOVNO,
210	OP_CMOVC,
211	OP_CMOVNC,
212	OP_CMOVZ,
213	OP_CMOVNZ,
214	OP_CMOVBE,
215	OP_CMOVNBE,
216	OP_CMOVS,
217	OP_CMOVNS,
218	OP_CMOVP,
219	OP_CMOVNP,
220	OP_CMOVL,
221	OP_CMOVNL,
222	OP_CMOVLE,
223	OP_CMOVNLE,
224	OP_MOVMSKPS,
225	OP_SQRTPS,
226	OP_RSQRTPS,
227	OP_RCPPS,
228	OP_ANDPS,
229	OP_ANDNPS,
230	OP_ORPS,
231	OP_XORPS,
232	OP_ADDPS,
233	OP_MULPS,
234	OP_CVTPS2PD,
235	OP_CVTDQ2PS,
236	OP_SUBPS,
237	OP_MINPS,
238	OP_DIVPS,
239	OP_MAXPS,
240	OP_PUNPCKLBW,
241	OP_PUNPCKLWD,
242	OP_PUNPCKLDQ,
243	OP_PACKSSWB,
244	OP_PCMPGTB,
245	OP_PCMPGTW,
246	OP_PCMPGTD,
247	OP_PCMPGTQ,
248	OP_PACKUSWB,
249	OP_PUNPCKHBW,
250	OP_PUNPCKHWD,
251	OP_PUNPCKHDQ,
252	OP_PACKSSDW,
253	OP_MOVD,
254	OP_MOVQ,
255	OP_PSHUFW,
256	OP_3B_ESC4,
257	OP_3B_ESC5,
258	OP_PCMPEQB,
259	OP_PCMPEQW,
260	OP_PCMPEQD,
261	OP_PCMPEQQ,
262	OP_SETO,
263	OP_SETNO,
264	OP_SETC,
265	OP_SETNC,
266	OP_SETE,
267	OP_SETNE,
268	OP_SETBE,
269	OP_SETNBE,
270	OP_SETS,
271	OP_SETNS,
272	OP_SETP,
273	OP_SETNP,
274	OP_SETL,
275	OP_SETNL,
276	OP_SETLE,
277	OP_SETNLE,
278	OP_CPUID,
279	OP_BT,
280	OP_SHLD,
281	OP_RSM,
282	OP_BTS,
283	OP_SHRD,
284	OP_GRP15,
285	OP_CMPXCHG,
286	OP_LSS,
287	OP_BTR,
288	OP_LFS,
289	OP_LGS,
290	OP_MOVZX,
291	OP_GRP10_INV,
292	OP_GRP8,
293	OP_BTC,
294	OP_BSF,
295	OP_BSR,
296	OP_MOVSX,
297	OP_XADD,
298	OP_CMPPS,
299	OP_MOVNTI,
300	OP_PINSRW,
301	OP_PEXTRW,
302	OP_SHUFPS,
303	OP_GRP9,
304	OP_BSWAP,
305	OP_ADDSUBPS,
306	OP_ADDSUBPD,
307	OP_PSRLW,
308	OP_PSRLD,
309	OP_PSRLQ,
310	OP_PADDQ,
311	OP_PMULLW,
312	OP_PMOVMSKB,
313	OP_PSUBUSB,
314	OP_PSUBUSW,
315	OP_PMINUB,
316	OP_PAND,
317	OP_PADDUSB,
318	OP_PADDUSW,
319	OP_PMAXUB,
320	OP_PANDN,
321	OP_PAVGB,
322	OP_PSRAW,
323	OP_PSRAD,
324	OP_PAVGW,
325	OP_PMULHUW,
326	OP_PMULHW,
327	OP_MOVNTQ,
328	OP_PSUBSB,
329	OP_PSUBSW,
330	OP_PMINSW,
331	OP_POR,
332	OP_PADDSB,
333	OP_PADDSW,
334	OP_PMAXSW,
335	OP_PXOR,
336	OP_LDDQU,
337	OP_PSLLW,
338	OP_PSLLD,
339	OP_PSSQ,
340	OP_PMULUDQ,
341	OP_PMADDWD,
342	OP_PSADBW,
343	OP_MASKMOVQ,
344	OP_PSUBB,
345	OP_PSUBW,
346	OP_PSUBD,
347	OP_PSUBQ,
348	OP_PADDB,
349	OP_PADDW,
350	OP_PADDD,
351	OP_MOVUPD,
352	OP_MOVLPD,
353	OP_UNPCKLPD,
354	OP_UNPCKHPD,
355	OP_MOVHPD,
356	OP_MOVAPD,
357	OP_CVTPI2PD,
358	OP_MOVNTPD,
359	OP_CVTTPD2PI,
360	OP_CVTPD2PI,
361	OP_UCOMISD,
362	OP_COMISD,
363	OP_MOVMSKPD,
364	OP_SQRTPD,
365	OP_ANDPD,
366	OP_ANDNPD,
367	OP_ORPD,
368	OP_XORPD,
369	OP_ADDPD,
370	OP_MULPD,
371	OP_CVTPD2PS,
372	OP_CVTPS2DQ,
373	OP_SUBPD,
374	OP_MINPD,
375	OP_DIVPD,
376	OP_MAXPD,
377	OP_GRP12,
378	OP_GRP13,
379	OP_GRP14,
380	OP_GRP17,
381	OP_EMMS,
382	OP_MMX_UD78,
383	OP_MMX_UD79,
384	OP_MMX_UD7A,
385	OP_MMX_UD7B,
386	OP_MMX_UD7C,
387	OP_MMX_UD7D,
388	OP_PUNPCKLQDQ,
389	OP_PUNPCKHQDQ,
390	OP_MOVDQA,
391	OP_PSHUFD,
392	OP_CMPPD,
393	OP_SHUFPD,
394	OP_CVTTPD2DQ,
395	OP_MOVNTDQ,
396	OP_MOVNTDQA,
397	OP_PACKUSDW,
398	OP_PSHUFB,
399	OP_PHADDW,
400	OP_PHADDD,
401	OP_PHADDSW,
402	OP_HADDPS,
403	OP_HADDPD,
404	OP_PMADDUBSW,
405	OP_PHSUBW,
406	OP_PHSUBD,
407	OP_PHSUBSW,
408	OP_HSUBPS,
409	OP_HSUBPD,
410	OP_PSIGNB,
411	OP_PSIGNW,
412	OP_PSIGND,
413	OP_PMULHRSW,
414	OP_PERMILPS,
415	OP_PERMILPD,
416	OP_TESTPS,
417	OP_TESTPD,
418	OP_PBLENDVB,
419	OP_CVTPH2PS,
420	OP_BLENDVPS,
421	OP_BLENDVPD,
422	OP_PERMPS,
423	OP_PERMD,
424	OP_PTEST,
425	OP_BROADCASTSS,
426	OP_BROADCASTSD,
427	OP_BROADCASTF128,
428	OP_PABSB,
429	OP_PABSW,
430	OP_PABSD,
431	OP_PMOVSX,
432	OP_PMOVZX,
433	OP_PMULDQ,
434	OP_PMINSB,
435	OP_PMINSD,
436	OP_PMINUW,
437	OP_PMINUD,
438	OP_PMAXSB,
439	OP_PMAXSD,
440	OP_PMAXUW,
441	OP_PMAXUD,
442	OP_PMULLD,
443	OP_PHMINPOSUW,
444	OP_PSRLVD,
445	OP_PSRAVD,
446	OP_PSLLVD,
447	OP_PBROADCASTD,
448	OP_PBROADCASTQ,
449	OP_PBROADCASTI128,
450	OP_PBROADCASTB,
451	OP_PBROADCASTW,
452	OP_PMASKMOVD,
453	OP_GATHER,
454	OP_FMADDSUB132PS,
455	OP_FMSUBADD132PS,
456	OP_FMADD132PS,
457	OP_FMADD132SS,
458	OP_FMSUB132PS,
459	OP_FMSUB132SS,
460	OP_FNMADD132PS,
461	OP_FNMADD132SS,
462	OP_FNMSUB132PS,
463	OP_FNMSUB132SS,
464	OP_FMADDSUB213PS,
465	OP_FMSUBADD213PS,
466	OP_FMADD213PS,
467	OP_FMADD213SS,
468	OP_FMSUB213PS,
469	OP_FMSUB213SS,
470	OP_FNMADD213PS,
471	OP_FNMADD213SS,
472	OP_FNMSUB213PS,
473	OP_FNMSUB213SS,
474	OP_FMADDSUB231PS,
475	OP_FMSUBADD231PS,
476	OP_FMADD231PS,
477	OP_FMADD231SS,
478	OP_FMSUB231PS,
479	OP_FMSUB231SS,
480	OP_FNMADD231PS,
481	OP_FNMADD231SS,
482	OP_FNMSUB231PS,
483	OP_FNMSUB231SS,
484	OP_AESIMC,
485	OP_AESENC,
486	OP_AESENCLAST,
487	OP_AESDEC,
488	OP_AESDECLAST,
489	OP_MOVBEGM,
490	OP_MOVBEMG,
491	OP_CRC32GDEB,
492	OP_CRC32GDEY,
493	OP_POPCNT,
494	OP_TZCNT,
495	OP_LZCNT,
496	OP_ADCX,
497	OP_ADOX,
498	OP_ANDN,
499	OP_BZHI,
500	OP_BEXTR,
501	OP_BLSR,
502	OP_BLSMSK,
503	OP_BLSI,
504	OP_PEXT,
505	OP_PDEP,
506	OP_SHLX,
507	OP_SHRX,
508	OP_SARX,
509	OP_MULX,
510	OP_MASKMOVDQU,
511	OP_MASKMOVPS,
512	OP_MASKMOVPD,
513	OP_MOVSD,
514	OP_CVTSI2SD,
515	OP_CVTTSD2SI,
516	OP_CVTSD2SI,
517	OP_SQRTSD,
518	OP_ADDSD,
519	OP_MULSD,
520	OP_CVTSD2SS,
521	OP_SUBSD,
522	OP_MINSD,
523	OP_DIVSD,
524	OP_MAXSD,
525	OP_PSHUFLW,
526	OP_CMPSD,
527	OP_MOVDQ2Q,
528	OP_CVTPD2DQ,
529	OP_MOVSS,
530	OP_MOVSLDUP,
531	OP_MOVDDUP,
532	OP_MOVSHDUP,
533	OP_CVTSI2SS,
534	OP_CVTTSS2SI,
535	OP_CVTSS2SI,
536	OP_CVTSS2SD,
537	OP_SQRTSS,
538	OP_RSQRTSS,
539	OP_RCPSS,
540	OP_ADDSS,
541	OP_MULSS,
542	OP_CVTTPS2DQ,
543	OP_SUBSS,
544	OP_MINSS,
545	OP_DIVSS,
546	OP_MAXSS,
547	OP_MOVDQU,
548	OP_PSHUFHW,
549	OP_CMPSS,
550	OP_MOVQ2DQ,
551	OP_CVTDQ2PD,
552	OP_PERMQ,
553	OP_PERMPD,
554	OP_PBLENDD,
555	OP_PERM2F128,
556	OP_ROUNDPS,
557	OP_ROUNDPD,
558	OP_ROUNDSS,
559	OP_ROUNDSD,
560	OP_BLENDPS,
561	OP_BLENDPD,
562	OP_PBLENDW,
563	OP_PALIGNR,
564	OP_PEXTRB,
565	OP_PEXTRD,
566	OP_EXTRACTPS,
567	OP_INSERTF128,
568	OP_EXTRACTF128,
569	OP_CVTPS2PH,
570	OP_PINSRB,
571	OP_PINSRD,
572	OP_INSERTPS,
573	OP_INSERTI128,
574	OP_EXTRACTI128,
575	OP_DPPS,
576	OP_DPPD,
577	OP_MPSADBW,
578	OP_PCLMULQDQ,
579	OP_PERM2I128,
580	OP_PCMPESTRM,
581	OP_PCMPESTRI,
582	OP_PCMPISTRM,
583	OP_PCMPISTRI,
584	OP_AESKEYGEN,
585	OP_RORX,
586	OP_VEX3B,
587	OP_VEX2B,
588	/** @} */
589
590	/** @name Floating point ops
591	* @{ */
592	OP_FADD,
593	OP_FMUL,
594	OP_FCOM,
595	OP_FCOMP,
596	OP_FSUB,
597	OP_FSUBR,
598	OP_FDIV,
599	OP_FDIVR,
600	OP_FLD,
601	OP_FST,
602	OP_FSTP,
603	OP_FLDENV,
604	OP_FSTENV,
605	OP_FSTCW,
606	OP_FXCH,
607	OP_FNOP,
608	OP_FCHS,
609	OP_FABS,
610	OP_FLD1,
611	OP_FLDL2T,
612	OP_FLDL2E,
613	OP_FLDPI,
614	OP_FLDLG2,
615	OP_FLDLN2,
616	OP_FLDZ,
617	OP_F2XM1,
618	OP_FYL2X,
619	OP_FPTAN,
620	OP_FPATAN,
621	OP_FXTRACT,
622	OP_FREM1,
623	OP_FDECSTP,
624	OP_FINCSTP,
625	OP_FPREM,
626	OP_FYL2XP1,
627	OP_FSQRT,
628	OP_FSINCOS,
629	OP_FRNDINT,
630	OP_FSCALE,
631	OP_FSIN,
632	OP_FCOS,
633	OP_FIADD,
634	OP_FIMUL,
635	OP_FISUB,
636	OP_FISUBR,
637	OP_FIDIV,
638	OP_FIDIVR,
639	OP_FCMOVB,
640	OP_FCMOVE,
641	OP_FCMOVBE,
642	OP_FCMOVU,
643	OP_FUCOMPP,
644	OP_FILD,
645	OP_FIST,
646	OP_FISTP,
647	OP_FCMOVNB,
648	OP_FCMOVNE,
649	OP_FCMOVNBE,
650	OP_FCMOVNU,
651	OP_FCLEX,
652	OP_FINIT,
653	OP_FUCOMI,
654	OP_FCOMI,
655	OP_FRSTOR,
656	OP_FSAVE,
657	OP_FNSTSW,
658	OP_FFREE,
659	OP_FUCOM,
660	OP_FUCOMP,
661	OP_FICOM,
662	OP_FICOMP,
663	OP_FADDP,
664	OP_FMULP,
665	OP_FCOMPP,
666	OP_FSUBRP,
667	OP_FSUBP,
668	OP_FDIVRP,
669	OP_FDIVP,
670	OP_FBLD,
671	OP_FBSTP,
672	OP_FCOMIP,
673	OP_FUCOMIP,
674	/** @} */
675
676	/** @name 3DNow!
677	* @{ */
678	OP_PI2FW,
679	OP_PI2FD,
680	OP_PF2IW,
681	OP_PF2ID,
682	OP_PFPNACC,
683	OP_PFCMPGE,
684	OP_PFMIN,
685	OP_PFRCP,
686	OP_PFRSQRT,
687	OP_PFSUB,
688	OP_PFADD,
689	OP_PFCMPGT,
690	OP_PFMAX,
691	OP_PFRCPIT1,
692	OP_PFRSQRTIT1,
693	OP_PFSUBR,
694	OP_PFACC,
695	OP_PFCMPEQ,
696	OP_PFMUL,
697	OP_PFRCPIT2,
698	OP_PFMULHRW,
699	OP_PFSWAPD,
700	OP_PAVGUSB,
701	OP_PFNACC,
702	/** @} */
703	OP_ROL,
704	OP_ROR,
705	OP_RCL,
706	OP_RCR,
707	OP_SHL,
708	OP_SHR,
709	OP_SAR,
710	OP_NOT,
711	OP_NEG,
712	OP_MUL,
713	OP_DIV,
714	OP_IDIV,
715	OP_SLDT,
716	OP_STR,
717	OP_LLDT,
718	OP_LTR,
719	OP_VERR,
720	OP_VERW,
721	OP_SGDT,
722	OP_LGDT,
723	OP_SIDT,
724	OP_LIDT,
725	OP_SMSW,
726	OP_LMSW,
727	OP_INVLPG,
728	OP_CMPXCHG8B,
729	OP_PSLLQ,
730	OP_PSRLDQ,
731	OP_PSLLDQ,
732	OP_FXSAVE,
733	OP_FXRSTOR,
734	OP_LDMXCSR,
735	OP_STMXCSR,
736	OP_XSAVE,
737	OP_XSAVEOPT,
738	OP_XRSTOR,
739	OP_XGETBV,
740	OP_XSETBV,
741	OP_RDFSBASE,
742	OP_RDGSBASE,
743	OP_WRFSBASE,
744	OP_WRGSBASE,
745	OP_LFENCE,
746	OP_MFENCE,
747	OP_SFENCE,
748	OP_PREFETCH,
749	OP_MONITOR,
750	OP_MWAIT,
751	OP_CLFLUSH,
752	OP_CLFLUSHOPT,
753	OP_MOV_DR,
754	OP_MOV_TR,
755	OP_SWAPGS,
756	OP_UD1,
757	OP_UD2,
758	/** @name VT-x instructions
759	* @{ */
760	OP_VMREAD,
761	OP_VMWRITE,
762	OP_VMCALL,
763	OP_VMXON,
764	OP_VMXOFF,
765	OP_VMCLEAR,
766	OP_VMLAUNCH,
767	OP_VMRESUME,
768	OP_VMPTRLD,
769	OP_VMPTRST,
770	OP_INVEPT,
771	OP_INVVPID,
772	OP_INVPCID,
773	OP_VMFUNC,
774	/** @} */
775	/** @name AMD-V instructions
776	* @{ */
777	OP_VMMCALL,
778	OP_VMRUN,
779	OP_VMLOAD,
780	OP_VMSAVE,
781	OP_CLGI,
782	OP_STGI,
783	OP_INVLPGA,
784	OP_SKINIT,
785	/** @} */
786	/** @name 64 bits instruction
787	* @{ */
788	OP_MOVSXD,
789	/** @} */
790	/** @name AVX instructions
791	* @{ */
792	OP_VLDMXCSR,
793	OP_VSTMXCSR,
794	OP_VMOVUPS,
795	OP_VMOVUPD,
796	OP_VMOVSS,
797	OP_VMOVSD,
798	OP_VMOVHLPS,
799	OP_VMOVLPS,
800	OP_VMOVLPD,
801	OP_VMOVSLDUP,
802	OP_VMOVDDUP,
803	OP_VMOVAPS,
804	OP_VMOVAPD,
805	OP_VMOVNTPS,
806	OP_VMOVNTPD,
807	OP_VMOVD,
808	OP_VMOVQ,
809	OP_VMOVDQA,
810	OP_VMOVDQU,
811	OP_VMOVNTDQ,
812	OP_VMOVNTDQA,
813	OP_VPAND,
814	OP_VANDPS,
815	OP_VANDPD,
816	OP_VPANDN,
817	OP_VANDNPS,
818	OP_VANDNPD,
819	OP_VPOR,
820	OP_VORPS,
821	OP_VORPD,
822	OP_VPXOR,
823	OP_VXORPS,
824	OP_VXORPD,
825	/** @} */
826	OP_END_OF_OPCODES
827	};
828	AssertCompile(OP_LOCK == 7);
829	AssertCompile(OP_END_OF_OPCODES < 1024 /* see 15 byte DISOPCODE variant */);
830	/** @} */
831
832
833	/** @defgroup grp_dis_opparam Opcode parameters (DISOPCODE::fParam1,
834	* DISOPCODE::fParam2, DISOPCODE::fParam3)
835	* @ingroup grp_dis
836	* @{
837	*/
838
839	/**
840	* @remarks Register order is important for translations!!
841	*/
842	enum OP_PARM
843	{
844	OP_PARM_NONE,
845
846	OP_PARM_REG_EAX,
847	OP_PARM_REG_GEN32_START = OP_PARM_REG_EAX,
848	OP_PARM_REG_ECX,
849	OP_PARM_REG_EDX,
850	OP_PARM_REG_EBX,
851	OP_PARM_REG_ESP,
852	OP_PARM_REG_EBP,
853	OP_PARM_REG_ESI,
854	OP_PARM_REG_EDI,
855	OP_PARM_REG_GEN32_END = OP_PARM_REG_EDI,
856
857	OP_PARM_REG_ES,
858	OP_PARM_REG_SEG_START = OP_PARM_REG_ES,
859	OP_PARM_REG_CS,
860	OP_PARM_REG_SS,
861	OP_PARM_REG_DS,
862	OP_PARM_REG_FS,
863	OP_PARM_REG_GS,
864	OP_PARM_REG_SEG_END = OP_PARM_REG_GS,
865
866	OP_PARM_REG_AX,
867	OP_PARM_REG_GEN16_START = OP_PARM_REG_AX,
868	OP_PARM_REG_CX,
869	OP_PARM_REG_DX,
870	OP_PARM_REG_BX,
871	OP_PARM_REG_SP,
872	OP_PARM_REG_BP,
873	OP_PARM_REG_SI,
874	OP_PARM_REG_DI,
875	OP_PARM_REG_GEN16_END = OP_PARM_REG_DI,
876
877	OP_PARM_REG_AL,
878	OP_PARM_REG_GEN8_START = OP_PARM_REG_AL,
879	OP_PARM_REG_CL,
880	OP_PARM_REG_DL,
881	OP_PARM_REG_BL,
882	OP_PARM_REG_AH,
883	OP_PARM_REG_CH,
884	OP_PARM_REG_DH,
885	OP_PARM_REG_BH,
886	OP_PARM_REG_GEN8_END = OP_PARM_REG_BH,
887
888	OP_PARM_REGFP_0,
889	OP_PARM_REG_FP_START = OP_PARM_REGFP_0,
890	OP_PARM_REGFP_1,
891	OP_PARM_REGFP_2,
892	OP_PARM_REGFP_3,
893	OP_PARM_REGFP_4,
894	OP_PARM_REGFP_5,
895	OP_PARM_REGFP_6,
896	OP_PARM_REGFP_7,
897	OP_PARM_REG_FP_END = OP_PARM_REGFP_7,
898
899	OP_PARM_NTA,
900	OP_PARM_T0,
901	OP_PARM_T1,
902	OP_PARM_T2,
903	OP_PARM_1,
904
905	OP_PARM_REX,
906	OP_PARM_REX_START = OP_PARM_REX,
907	OP_PARM_REX_B,
908	OP_PARM_REX_X,
909	OP_PARM_REX_XB,
910	OP_PARM_REX_R,
911	OP_PARM_REX_RB,
912	OP_PARM_REX_RX,
913	OP_PARM_REX_RXB,
914	OP_PARM_REX_W,
915	OP_PARM_REX_WB,
916	OP_PARM_REX_WX,
917	OP_PARM_REX_WXB,
918	OP_PARM_REX_WR,
919	OP_PARM_REX_WRB,
920	OP_PARM_REX_WRX,
921	OP_PARM_REX_WRXB,
922
923	OP_PARM_REG_RAX,
924	OP_PARM_REG_GEN64_START = OP_PARM_REG_RAX,
925	OP_PARM_REG_RCX,
926	OP_PARM_REG_RDX,
927	OP_PARM_REG_RBX,
928	OP_PARM_REG_RSP,
929	OP_PARM_REG_RBP,
930	OP_PARM_REG_RSI,
931	OP_PARM_REG_RDI,
932	OP_PARM_REG_R8,
933	OP_PARM_REG_R9,
934	OP_PARM_REG_R10,
935	OP_PARM_REG_R11,
936	OP_PARM_REG_R12,
937	OP_PARM_REG_R13,
938	OP_PARM_REG_R14,
939	OP_PARM_REG_R15,
940	OP_PARM_REG_GEN64_END = OP_PARM_REG_R15
941	};
942
943
944	/* 8-bit GRP aliases (for IEM). */
945	#define OP_PARM_AL OP_PARM_REG_AL
946
947	/* GPR aliases for op-size specified register sizes (for IEM). */
948	#define OP_PARM_rAX OP_PARM_REG_EAX
949	#define OP_PARM_rCX OP_PARM_REG_ECX
950	#define OP_PARM_rDX OP_PARM_REG_EDX
951	#define OP_PARM_rBX OP_PARM_REG_EBX
952	#define OP_PARM_rSP OP_PARM_REG_ESP
953	#define OP_PARM_rBP OP_PARM_REG_EBP
954	#define OP_PARM_rSI OP_PARM_REG_ESI
955	#define OP_PARM_rDI OP_PARM_REG_EDI
956
957	/* SREG aliases (for IEM). */
958	#define OP_PARM_ES OP_PARM_REG_ES
959	#define OP_PARM_CS OP_PARM_REG_CS
960	#define OP_PARM_SS OP_PARM_REG_SS
961	#define OP_PARM_DS OP_PARM_REG_DS
962	#define OP_PARM_FS OP_PARM_REG_FS
963	#define OP_PARM_GS OP_PARM_REG_GS
964
965	/*
966	* Note! We don't document anything here if we can help it, because it we love
967	* wasting other peoples time figuring out crypting crap. The new VEX
968	* stuff of course uphelds this vexing tradition. Aaaaaaaaaaaaaaaaaaarg!
969	*/
970
971	#define OP_PARM_VTYPE(a) ((unsigned)a & 0xFE0)
972	#define OP_PARM_VSUBTYPE(a) ((unsigned)a & 0x01F)
973
974	#define OP_PARM_A 0x100
975	#define OP_PARM_VARIABLE OP_PARM_A
976	#define OP_PARM_E 0x120
977	#define OP_PARM_F 0x140
978	#define OP_PARM_G 0x160
979	#define OP_PARM_I 0x180
980	#define OP_PARM_J 0x1A0
981	#define OP_PARM_M 0x1C0
982	#define OP_PARM_O 0x1E0
983	#define OP_PARM_R 0x200
984	#define OP_PARM_X 0x220
985	#define OP_PARM_Y 0x240
986
987	/* Grouped rare parameters for optimization purposes */
988	#define IS_OP_PARM_RARE(a) ((a & 0xF00) >= 0x300)
989	#define OP_PARM_C 0x300 /* control register */
990	#define OP_PARM_D 0x320 /* debug register */
991	#define OP_PARM_S 0x340 /* segment register */
992	#define OP_PARM_T 0x360 /* test register */
993	#define OP_PARM_Q 0x380
994	#define OP_PARM_P 0x3A0 /* mmx register */
995	#define OP_PARM_W 0x3C0 /* xmm register */
996	#define OP_PARM_V 0x3E0
997	#define OP_PARM_U 0x400 /* The R/M field of the ModR/M byte selects XMM/YMM register. */
998	#define OP_PARM_B 0x420 /* VEX.vvvv field select general purpose register. */
999	#define OP_PARM_H 0x440
1000	#define OP_PARM_L 0x460
1001
1002	#define OP_PARM_NONE 0
1003	#define OP_PARM_a 0x1 /*< Operand to bound instruction. /
1004	#define OP_PARM_b 0x2 /*< Byte (always). /
1005	#define OP_PARM_d 0x3 /*< Double word (always). /
1006	#define OP_PARM_dq 0x4 /*< Double quad word (always). /
1007	#define OP_PARM_p 0x5 /*< Far pointer (subject to opsize). /
1008	#define OP_PARM_pd 0x6 /*< 128-bit or 256-bit double precision floating point data. /
1009	#define OP_PARM_pi 0x7 /*< Quad word MMX register. /
1010	#define OP_PARM_ps 0x8 /*< 128-bit or 256-bit single precision floating point data. /
1011	#define OP_PARM_q 0xA /*< Quad word (always). /
1012	#define OP_PARM_s 0xB /*< Descriptor table size (SIDT/LIDT/SGDT/LGDT). /
1013	#define OP_PARM_sd 0xC /*< Scalar element of 128-bit double precision floating point data. /
1014	#define OP_PARM_ss 0xD /*< Scalar element of 128-bit single precision floating point data. /
1015	#define OP_PARM_v 0xE /*< Word, double word, or quad word depending on opsize. /
1016	#define OP_PARM_w 0xF /*< Word (always). /
1017	#define OP_PARM_x 0x10 /*< Double quad word (dq) or quad quad word (qq) depending on opsize. /
1018	#define OP_PARM_y 0x11 /*< Double word or quad word depending on opsize. /
1019	#define OP_PARM_z 0x12 /*< Word (16-bit opsize) or double word (32-bit/64-bit opsize). /
1020	#define OP_PARM_qq 0x13 /*< Quad quad word. /
1021
1022
1023	#define OP_PARM_Ap (OP_PARM_A+OP_PARM_p)
1024	#define OP_PARM_By (OP_PARM_B+OP_PARM_y)
1025	#define OP_PARM_Cd (OP_PARM_C+OP_PARM_d)
1026	#define OP_PARM_Dd (OP_PARM_D+OP_PARM_d)
1027	#define OP_PARM_Eb (OP_PARM_E+OP_PARM_b)
1028	#define OP_PARM_Ed (OP_PARM_E+OP_PARM_d)
1029	#define OP_PARM_Ep (OP_PARM_E+OP_PARM_p)
1030	#define OP_PARM_Ev (OP_PARM_E+OP_PARM_v)
1031	#define OP_PARM_Ew (OP_PARM_E+OP_PARM_w)
1032	#define OP_PARM_Ey (OP_PARM_E+OP_PARM_y)
1033	#define OP_PARM_Fv (OP_PARM_F+OP_PARM_v)
1034	#define OP_PARM_Gb (OP_PARM_G+OP_PARM_b)
1035	#define OP_PARM_Gd (OP_PARM_G+OP_PARM_d)
1036	#define OP_PARM_Gv (OP_PARM_G+OP_PARM_v)
1037	#define OP_PARM_Gw (OP_PARM_G+OP_PARM_w)
1038	#define OP_PARM_Gy (OP_PARM_G+OP_PARM_y)
1039	#define OP_PARM_Hq (OP_PARM_H+OP_PARM_q)
1040	#define OP_PARM_Hps (OP_PARM_H+OP_PARM_ps)
1041	#define OP_PARM_Hpd (OP_PARM_H+OP_PARM_pd)
1042	#define OP_PARM_Hdq (OP_PARM_H+OP_PARM_dq)
1043	#define OP_PARM_Hqq (OP_PARM_H+OP_PARM_qq)
1044	#define OP_PARM_Hsd (OP_PARM_H+OP_PARM_sd)
1045	#define OP_PARM_Hss (OP_PARM_H+OP_PARM_ss)
1046	#define OP_PARM_Hx (OP_PARM_H+OP_PARM_x)
1047	#define OP_PARM_Ib (OP_PARM_I+OP_PARM_b)
1048	#define OP_PARM_Id (OP_PARM_I+OP_PARM_d)
1049	#define OP_PARM_Iq (OP_PARM_I+OP_PARM_q)
1050	#define OP_PARM_Iw (OP_PARM_I+OP_PARM_w)
1051	#define OP_PARM_Iv (OP_PARM_I+OP_PARM_v)
1052	#define OP_PARM_Iz (OP_PARM_I+OP_PARM_z)
1053	#define OP_PARM_Jb (OP_PARM_J+OP_PARM_b)
1054	#define OP_PARM_Jv (OP_PARM_J+OP_PARM_v)
1055	#define OP_PARM_Ma (OP_PARM_M+OP_PARM_a)
1056	#define OP_PARM_Mb (OP_PARM_M+OP_PARM_b)
1057	#define OP_PARM_Mw (OP_PARM_M+OP_PARM_w)
1058	#define OP_PARM_Md (OP_PARM_M+OP_PARM_d)
1059	#define OP_PARM_Mp (OP_PARM_M+OP_PARM_p)
1060	#define OP_PARM_Mq (OP_PARM_M+OP_PARM_q)
1061	#define OP_PARM_Mdq (OP_PARM_M+OP_PARM_dq)
1062	#define OP_PARM_Ms (OP_PARM_M+OP_PARM_s)
1063	#define OP_PARM_Mx (OP_PARM_M+OP_PARM_x)
1064	#define OP_PARM_My (OP_PARM_M+OP_PARM_y)
1065	#define OP_PARM_Mps (OP_PARM_M+OP_PARM_ps)
1066	#define OP_PARM_Mpd (OP_PARM_M+OP_PARM_pd)
1067	#define OP_PARM_Ob (OP_PARM_O+OP_PARM_b)
1068	#define OP_PARM_Ov (OP_PARM_O+OP_PARM_v)
1069	#define OP_PARM_Pq (OP_PARM_P+OP_PARM_q)
1070	#define OP_PARM_Pd (OP_PARM_P+OP_PARM_d)
1071	#define OP_PARM_Qd (OP_PARM_Q+OP_PARM_d)
1072	#define OP_PARM_Qq (OP_PARM_Q+OP_PARM_q)
1073	#define OP_PARM_Rd (OP_PARM_R+OP_PARM_d)
1074	#define OP_PARM_Rw (OP_PARM_R+OP_PARM_w)
1075	#define OP_PARM_Ry (OP_PARM_R+OP_PARM_y)
1076	#define OP_PARM_Sw (OP_PARM_S+OP_PARM_w)
1077	#define OP_PARM_Td (OP_PARM_T+OP_PARM_d)
1078	#define OP_PARM_Ux (OP_PARM_U+OP_PARM_x)
1079	#define OP_PARM_Vq (OP_PARM_V+OP_PARM_q)
1080	#define OP_PARM_Vx (OP_PARM_V+OP_PARM_x)
1081	#define OP_PARM_Vy (OP_PARM_V+OP_PARM_y)
1082	#define OP_PARM_Wq (OP_PARM_W+OP_PARM_q)
1083	/#define OP_PARM_Ws (OP_PARM_W+OP_PARM_s) - wtf? Same as lgdt (OP_PARM_Ms)?/
1084	#define OP_PARM_Wx (OP_PARM_W+OP_PARM_x)
1085	#define OP_PARM_Xb (OP_PARM_X+OP_PARM_b)
1086	#define OP_PARM_Xv (OP_PARM_X+OP_PARM_v)
1087	#define OP_PARM_Yb (OP_PARM_Y+OP_PARM_b)
1088	#define OP_PARM_Yv (OP_PARM_Y+OP_PARM_v)
1089
1090	#define OP_PARM_Vps (OP_PARM_V+OP_PARM_ps)
1091	#define OP_PARM_Vss (OP_PARM_V+OP_PARM_ss)
1092	#define OP_PARM_Vpd (OP_PARM_V+OP_PARM_pd)
1093	#define OP_PARM_Vdq (OP_PARM_V+OP_PARM_dq)
1094	#define OP_PARM_Wps (OP_PARM_W+OP_PARM_ps)
1095	#define OP_PARM_Wpd (OP_PARM_W+OP_PARM_pd)
1096	#define OP_PARM_Wss (OP_PARM_W+OP_PARM_ss)
1097	#define OP_PARM_Ww (OP_PARM_W+OP_PARM_w)
1098	#define OP_PARM_Wd (OP_PARM_W+OP_PARM_d)
1099	#define OP_PARM_Wq (OP_PARM_W+OP_PARM_q)
1100	#define OP_PARM_Wdq (OP_PARM_W+OP_PARM_dq)
1101	#define OP_PARM_Wqq (OP_PARM_W+OP_PARM_qq)
1102	#define OP_PARM_Ppi (OP_PARM_P+OP_PARM_pi)
1103	#define OP_PARM_Qpi (OP_PARM_Q+OP_PARM_pi)
1104	#define OP_PARM_Qdq (OP_PARM_Q+OP_PARM_dq)
1105	#define OP_PARM_Vsd (OP_PARM_V+OP_PARM_sd)
1106	#define OP_PARM_Wsd (OP_PARM_W+OP_PARM_sd)
1107	#define OP_PARM_Vqq (OP_PARM_V+OP_PARM_qq)
1108	#define OP_PARM_Pdq (OP_PARM_P+OP_PARM_dq)
1109	#define OP_PARM_Ups (OP_PARM_U+OP_PARM_ps)
1110	#define OP_PARM_Upd (OP_PARM_U+OP_PARM_pd)
1111	#define OP_PARM_Udq (OP_PARM_U+OP_PARM_dq)
1112	#define OP_PARM_Lx (OP_PARM_L+OP_PARM_x)
1113
1114	/* For making IEM / bs3-cpu-generated-1 happy: */
1115	#define OP_PARM_Ed_WO OP_PARM_Ed /*< Annotates write only operand. /
1116	#define OP_PARM_Eq (OP_PARM_E+OP_PARM_q)
1117	#define OP_PARM_Eq_WO OP_PARM_Eq /*< Annotates write only operand. /
1118	#define OP_PARM_Gv_RO OP_PARM_Gv /*< Annotates read only first operand (default is readwrite). /
1119	#define OP_PARM_HssHi OP_PARM_Hx /*< Register referenced by VEX.vvvv, bits [127:32]. /
1120	#define OP_PARM_HsdHi OP_PARM_Hx /*< Register referenced by VEX.vvvv, bits [127:64]. /
1121	#define OP_PARM_HqHi OP_PARM_Hx /*< Register referenced by VEX.vvvv, bits [127:64]. /
1122	#define OP_PARM_M_RO OP_PARM_M /*< Annotates read only memory of variable operand size (xrstor). /
1123	#define OP_PARM_M_RW OP_PARM_M /*< Annotates read-write memory of variable operand size (xsave). /
1124	#define OP_PARM_Mb_RO OP_PARM_Mb /*< Annotates read only memory byte operand. /
1125	#define OP_PARM_Md_RO OP_PARM_Md /*< Annotates read only memory operand. /
1126	#define OP_PARM_Md_WO OP_PARM_Md /*< Annotates write only memory operand. /
1127	#define OP_PARM_Mdq_WO OP_PARM_Mdq /*< Annotates write only memory operand. /
1128	#define OP_PARM_Mq_WO OP_PARM_Mq /*< Annotates write only memory quad word operand. /
1129	#define OP_PARM_Mps_WO OP_PARM_Mps /*< Annotates write only memory operand. /
1130	#define OP_PARM_Mpd_WO OP_PARM_Mpd /*< Annotates write only memory operand. /
1131	#define OP_PARM_Mx_WO OP_PARM_Mx /*< Annotates write only memory operand. /
1132	#define OP_PARM_PdZx_WO OP_PARM_Pd /*< Annotates write only operand and zero extends to 64-bit. /
1133	#define OP_PARM_Pq_WO OP_PARM_Pq /*< Annotates write only operand. /
1134	#define OP_PARM_Qq_WO OP_PARM_Qq /*< Annotates write only operand. /
1135	#define OP_PARM_Nq OP_PARM_Qq /*< Missing 'N' class (MMX reg selected by modrm.mem) in disasm. /
1136	#define OP_PARM_Uq (OP_PARM_U+OP_PARM_q)
1137	#define OP_PARM_UqHi (OP_PARM_U+OP_PARM_dq)
1138	#define OP_PARM_Uss (OP_PARM_U+OP_PARM_ss)
1139	#define OP_PARM_Uss_WO OP_PARM_Uss /*< Annotates write only operand. /
1140	#define OP_PARM_Usd (OP_PARM_U+OP_PARM_sd)
1141	#define OP_PARM_Usd_WO OP_PARM_Usd /*< Annotates write only operand. /
1142	#define OP_PARM_Vd (OP_PARM_V+OP_PARM_d)
1143	#define OP_PARM_Vd_WO OP_PARM_Vd /*< Annotates write only operand. /
1144	#define OP_PARM_VdZx_WO OP_PARM_Vd /*< Annotates that the registers get their upper bits cleared /
1145	#define OP_PARM_Vdq_WO OP_PARM_Vdq /*< Annotates that only YMM/XMM[127:64] are accessed. /
1146	#define OP_PARM_Vpd_WO OP_PARM_Vpd /*< Annotates write only operand. /
1147	#define OP_PARM_Vps_WO OP_PARM_Vps /*< Annotates write only operand. /
1148	#define OP_PARM_Vq_WO OP_PARM_Vq /*< Annotates write only operand. /
1149	#define OP_PARM_VqHi OP_PARM_Vdq /*< Annotates that only YMM/XMM[127:64] are accessed. /
1150	#define OP_PARM_VqHi_WO OP_PARM_Vdq /*< Annotates that only YMM/XMM[127:64] are written. /
1151	#define OP_PARM_VqZx_WO OP_PARM_Vq /*< Annotates that the registers get their upper bits cleared /
1152	#define OP_PARM_VsdZx_WO OP_PARM_Vsd /*< Annotates that the registers get their upper bits cleared. /
1153	#define OP_PARM_VssZx_WO OP_PARM_Vss /*< Annotates that the registers get their upper bits cleared. /
1154	#define OP_PARM_Vss_WO OP_PARM_Vss /*< Annotates write only operand. /
1155	#define OP_PARM_Vsd_WO OP_PARM_Vsd /*< Annotates write only operand. /
1156	#define OP_PARM_Vx_WO OP_PARM_Vx /*< Annotates write only operand. /
1157	#define OP_PARM_Wpd_WO OP_PARM_Wpd /*< Annotates write only operand. /
1158	#define OP_PARM_Wps_WO OP_PARM_Wps /*< Annotates write only operand. /
1159	#define OP_PARM_Wq_WO OP_PARM_Wq /*< Annotates write only operand. /
1160	#define OP_PARM_WqZxReg_WO OP_PARM_Wq /*< Annotates that register targets get their upper bits cleared. /
1161	#define OP_PARM_Wss_WO OP_PARM_Wss /*< Annotates write only operand. /
1162	#define OP_PARM_Wsd_WO OP_PARM_Wsd /*< Annotates write only operand. /
1163	#define OP_PARM_Wx_WO OP_PARM_Wx /*< Annotates write only operand. /
1164
1165	/** @} */
1166
1167	#endif /* !VBOX_INCLUDED_disopcode_h */
1168

Note: See TracBrowser for help on using the repository browser.

source: vbox/trunk/include/VBox/disopcode.h@ 95440

Download in other formats: