disopcode.h@ 96134

Last change on this file since 96134 was 96114, checked in by vboxsync, 3 years ago
Disassembler: Add individual opcode enums for the various [v]pmov{s,z}x* instruction variants as these are separate instructions (needed for the IEM emulation), bugref:9898
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1	/** @file
2	* Disassembler - Opcodes
3	*/
4
5	/*
6	* Copyright (C) 2006-2022 Oracle Corporation
7	*
8	* This file is part of VirtualBox Open Source Edition (OSE), as
9	* available from http://www.virtualbox.org. This file is free software;
10	* you can redistribute it and/or modify it under the terms of the GNU
11	* General Public License (GPL) as published by the Free Software
12	* Foundation, in version 2 as it comes in the "COPYING" file of the
13	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15	*
16	* The contents of this file may alternatively be used under the terms
17	* of the Common Development and Distribution License Version 1.0
18	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19	* VirtualBox OSE distribution, in which case the provisions of the
20	* CDDL are applicable instead of those of the GPL.
21	*
22	* You may elect to license modified versions of this file under the
23	* terms and conditions of either the GPL or the CDDL or both.
24	*/
25
26	#ifndef VBOX_INCLUDED_disopcode_h
27	#define VBOX_INCLUDED_disopcode_h
28	#ifndef RT_WITHOUT_PRAGMA_ONCE
29	# pragma once
30	#endif
31
32	#include <iprt/assert.h>
33
34	#define MODRM_MOD(a) (a>>6)
35	#define MODRM_REG(a) ((a>>3)&0x7)
36	#define MODRM_RM(a) (a&0x7)
37	#define MAKE_MODRM(mod, reg, rm) (((mod&3) << 6) \| ((reg&7) << 3) \| (rm&7))
38
39	#define SIB_SCALE(a) (a>>6)
40	#define SIB_INDEX(a) ((a>>3)&0x7)
41	#define SIB_BASE(a) (a&0x7)
42
43
44	/** @defgroup grp_dis_opcodes Opcodes (DISOPCODE::uOpCode)
45	* @ingroup grp_dis
46	* @{
47	*/
48	enum OPCODES
49	{
50	/** @name Full Intel X86 opcode list
51	* @{ */
52	OP_INVALID = 0,
53	OP_OPSIZE,
54	OP_ADDRSIZE,
55	OP_SEG,
56	OP_REPNE,
57	OP_REPE,
58	OP_REX,
59	OP_LOCK,
60	#ifndef IN_SLICKEDIT
61	OP_LAST_PREFIX = OP_LOCK, /*< Last prefix for disassembler. /
62	#else
63	OP_LAST_PREFIX = 7, /*< Last prefix for disassembler. /
64	#endif
65	OP_AND,
66	OP_OR,
67	OP_DAA,
68	OP_SUB,
69	OP_DAS,
70	OP_XOR,
71	OP_AAA,
72	OP_CMP,
73	OP_IMM_GRP1,
74	OP_AAS,
75	OP_INC,
76	OP_DEC,
77	OP_PUSHA,
78	OP_POPA,
79	OP_BOUND,
80	OP_ARPL,
81	OP_PUSH,
82	OP_POP,
83	OP_IMUL,
84	OP_INSB,
85	OP_INSWD,
86	OP_OUTSB,
87	OP_OUTSWD,
88	OP_JO,
89	OP_JNO,
90	OP_JC,
91	OP_JNC,
92	OP_JE,
93	OP_JNE,
94	OP_JBE,
95	OP_JNBE,
96	OP_JS,
97	OP_JNS,
98	OP_JP,
99	OP_JNP,
100	OP_JL,
101	OP_JNL,
102	OP_JLE,
103	OP_JNLE,
104	OP_ADD,
105	OP_TEST,
106	OP_XCHG,
107	OP_MOV,
108	OP_LEA,
109	OP_NOP,
110	OP_CBW,
111	OP_CWD,
112	OP_CALL,
113	OP_WAIT,
114	OP_PUSHF,
115	OP_POPF,
116	OP_SAHF,
117	OP_LAHF,
118	OP_MOVSB,
119	OP_MOVSWD,
120	OP_CMPSB,
121	OP_CMPWD,
122	OP_STOSB,
123	OP_STOSWD,
124	OP_LODSB,
125	OP_LODSWD,
126	OP_SCASB,
127	OP_SCASWD,
128	OP_SHIFT_GRP2,
129	OP_RETN,
130	OP_LES,
131	OP_LDS,
132	OP_ENTER,
133	OP_LEAVE,
134	OP_RETF,
135	OP_INT1,
136	OP_INT3,
137	OP_INT,
138	OP_INTO,
139	OP_IRET,
140	OP_AAM,
141	OP_AAD,
142	OP_XLAT,
143	OP_ESCF0,
144	OP_ESCF1,
145	OP_ESCF2,
146	OP_ESCF3,
147	OP_ESCF4,
148	OP_ESCF5,
149	OP_ESCF6,
150	OP_ESCF7,
151	OP_LOOPNE,
152	OP_LOOPE,
153	OP_LOOP,
154	OP_JECXZ,
155	OP_IN,
156	OP_OUT,
157	OP_JMP,
158	OP_2B_ESC,
159	OP_ADC,
160	OP_SBB,
161	OP_HLT,
162	OP_CMC,
163	OP_UNARY_GRP3,
164	OP_CLC,
165	OP_STC,
166	OP_CLI,
167	OP_STI,
168	OP_CLD,
169	OP_STD,
170	OP_INC_GRP4,
171	OP_IND_GRP5,
172	OP_GRP6,
173	OP_GRP7,
174	OP_LAR,
175	OP_LSL,
176	OP_SYSCALL,
177	OP_CLTS,
178	OP_SYSRET,
179	OP_INVD,
180	OP_WBINVD,
181	OP_ILLUD2,
182	OP_FEMMS,
183	OP_3DNOW,
184	OP_MOVUPS,
185	OP_MOVLPS,
186	OP_MOVHLPS = OP_MOVLPS, /*< @todo OP_MOVHLPS /
187	OP_UNPCKLPS,
188	OP_MOVHPS,
189	OP_MOVLHPS = OP_MOVHPS, /*< @todo OP_MOVLHPS /
190	OP_UNPCKHPS,
191	OP_PREFETCH_GRP16,
192	OP_MOV_CR,
193	OP_MOVAPS,
194	OP_CVTPI2PS,
195	OP_MOVNTPS,
196	OP_CVTTPS2PI,
197	OP_CVTPS2PI,
198	OP_UCOMISS,
199	OP_COMISS,
200	OP_WRMSR,
201	OP_RDTSC,
202	OP_RDMSR,
203	OP_RDPMC,
204	OP_SYSENTER,
205	OP_SYSEXIT,
206	OP_GETSEC,
207	OP_PAUSE,
208	OP_CMOVO,
209	OP_CMOVNO,
210	OP_CMOVC,
211	OP_CMOVNC,
212	OP_CMOVZ,
213	OP_CMOVNZ,
214	OP_CMOVBE,
215	OP_CMOVNBE,
216	OP_CMOVS,
217	OP_CMOVNS,
218	OP_CMOVP,
219	OP_CMOVNP,
220	OP_CMOVL,
221	OP_CMOVNL,
222	OP_CMOVLE,
223	OP_CMOVNLE,
224	OP_MOVMSKPS,
225	OP_SQRTPS,
226	OP_RSQRTPS,
227	OP_RCPPS,
228	OP_ANDPS,
229	OP_ANDNPS,
230	OP_ORPS,
231	OP_XORPS,
232	OP_ADDPS,
233	OP_MULPS,
234	OP_CVTPS2PD,
235	OP_CVTDQ2PS,
236	OP_SUBPS,
237	OP_MINPS,
238	OP_DIVPS,
239	OP_MAXPS,
240	OP_PUNPCKLBW,
241	OP_PUNPCKLWD,
242	OP_PUNPCKLDQ,
243	OP_PACKSSWB,
244	OP_PCMPGTB,
245	OP_PCMPGTW,
246	OP_PCMPGTD,
247	OP_PCMPGTQ,
248	OP_PACKUSWB,
249	OP_PUNPCKHBW,
250	OP_PUNPCKHWD,
251	OP_PUNPCKHDQ,
252	OP_PACKSSDW,
253	OP_MOVD,
254	OP_MOVQ,
255	OP_PSHUFW,
256	OP_3B_ESC4,
257	OP_3B_ESC5,
258	OP_PCMPEQB,
259	OP_PCMPEQW,
260	OP_PCMPEQD,
261	OP_PCMPEQQ,
262	OP_SETO,
263	OP_SETNO,
264	OP_SETC,
265	OP_SETNC,
266	OP_SETE,
267	OP_SETNE,
268	OP_SETBE,
269	OP_SETNBE,
270	OP_SETS,
271	OP_SETNS,
272	OP_SETP,
273	OP_SETNP,
274	OP_SETL,
275	OP_SETNL,
276	OP_SETLE,
277	OP_SETNLE,
278	OP_CPUID,
279	OP_BT,
280	OP_SHLD,
281	OP_RSM,
282	OP_BTS,
283	OP_SHRD,
284	OP_GRP15,
285	OP_CMPXCHG,
286	OP_LSS,
287	OP_BTR,
288	OP_LFS,
289	OP_LGS,
290	OP_MOVZX,
291	OP_GRP10_INV,
292	OP_GRP8,
293	OP_BTC,
294	OP_BSF,
295	OP_BSR,
296	OP_MOVSX,
297	OP_XADD,
298	OP_CMPPS,
299	OP_MOVNTI,
300	OP_PINSRW,
301	OP_PEXTRW,
302	OP_SHUFPS,
303	OP_GRP9,
304	OP_BSWAP,
305	OP_ADDSUBPS,
306	OP_ADDSUBPD,
307	OP_PSRLW,
308	OP_PSRLD,
309	OP_PSRLQ,
310	OP_PADDQ,
311	OP_PMULLW,
312	OP_PMOVMSKB,
313	OP_PSUBUSB,
314	OP_PSUBUSW,
315	OP_PMINUB,
316	OP_PAND,
317	OP_PADDUSB,
318	OP_PADDUSW,
319	OP_PMAXUB,
320	OP_PANDN,
321	OP_PAVGB,
322	OP_PSRAW,
323	OP_PSRAD,
324	OP_PAVGW,
325	OP_PMULHUW,
326	OP_PMULHW,
327	OP_MOVNTQ,
328	OP_PSUBSB,
329	OP_PSUBSW,
330	OP_PMINSW,
331	OP_POR,
332	OP_PADDSB,
333	OP_PADDSW,
334	OP_PMAXSW,
335	OP_PXOR,
336	OP_LDDQU,
337	OP_PSLLW,
338	OP_PSLLD,
339	OP_PSSQ,
340	OP_PMULUDQ,
341	OP_PMADDWD,
342	OP_PSADBW,
343	OP_MASKMOVQ,
344	OP_PSUBB,
345	OP_PSUBW,
346	OP_PSUBD,
347	OP_PSUBQ,
348	OP_PADDB,
349	OP_PADDW,
350	OP_PADDD,
351	OP_MOVUPD,
352	OP_MOVLPD,
353	OP_UNPCKLPD,
354	OP_UNPCKHPD,
355	OP_MOVHPD,
356	OP_MOVAPD,
357	OP_CVTPI2PD,
358	OP_MOVNTPD,
359	OP_CVTTPD2PI,
360	OP_CVTPD2PI,
361	OP_UCOMISD,
362	OP_COMISD,
363	OP_MOVMSKPD,
364	OP_SQRTPD,
365	OP_ANDPD,
366	OP_ANDNPD,
367	OP_ORPD,
368	OP_XORPD,
369	OP_ADDPD,
370	OP_MULPD,
371	OP_CVTPD2PS,
372	OP_CVTPS2DQ,
373	OP_SUBPD,
374	OP_MINPD,
375	OP_DIVPD,
376	OP_MAXPD,
377	OP_GRP12,
378	OP_GRP13,
379	OP_GRP14,
380	OP_GRP17,
381	OP_EMMS,
382	OP_MMX_UD78,
383	OP_MMX_UD79,
384	OP_MMX_UD7A,
385	OP_MMX_UD7B,
386	OP_MMX_UD7C,
387	OP_MMX_UD7D,
388	OP_PUNPCKLQDQ,
389	OP_PUNPCKHQDQ,
390	OP_MOVDQA,
391	OP_PSHUFD,
392	OP_CMPPD,
393	OP_SHUFPD,
394	OP_CVTTPD2DQ,
395	OP_MOVNTDQ,
396	OP_MOVNTDQA,
397	OP_PACKUSDW,
398	OP_PSHUFB,
399	OP_PHADDW,
400	OP_PHADDD,
401	OP_PHADDSW,
402	OP_HADDPS,
403	OP_HADDPD,
404	OP_PMADDUBSW,
405	OP_PHSUBW,
406	OP_PHSUBD,
407	OP_PHSUBSW,
408	OP_HSUBPS,
409	OP_HSUBPD,
410	OP_PSIGNB,
411	OP_PSIGNW,
412	OP_PSIGND,
413	OP_PMULHRSW,
414	OP_PERMILPS,
415	OP_PERMILPD,
416	OP_TESTPS,
417	OP_TESTPD,
418	OP_PBLENDVB,
419	OP_CVTPH2PS,
420	OP_BLENDVPS,
421	OP_BLENDVPD,
422	OP_PERMPS,
423	OP_PERMD,
424	OP_PTEST,
425	OP_BROADCASTSS,
426	OP_BROADCASTSD,
427	OP_BROADCASTF128,
428	OP_PABSB,
429	OP_PABSW,
430	OP_PABSD,
431	OP_PMOVSXBW,
432	OP_PMOVSXBD,
433	OP_PMOVSXBQ,
434	OP_PMOVSXWD,
435	OP_PMOVSXWQ,
436	OP_PMOVSXDQ,
437	OP_PMOVZXBW,
438	OP_PMOVZXBD,
439	OP_PMOVZXBQ,
440	OP_PMOVZXWD,
441	OP_PMOVZXWQ,
442	OP_PMOVZXDQ,
443	OP_PMULDQ,
444	OP_PMINSB,
445	OP_PMINSD,
446	OP_PMINUW,
447	OP_PMINUD,
448	OP_PMAXSB,
449	OP_PMAXSD,
450	OP_PMAXUW,
451	OP_PMAXUD,
452	OP_PMULLD,
453	OP_PHMINPOSUW,
454	OP_PSRLVD,
455	OP_PSRAVD,
456	OP_PSLLVD,
457	OP_PBROADCASTD,
458	OP_PBROADCASTQ,
459	OP_PBROADCASTI128,
460	OP_PBROADCASTB,
461	OP_PBROADCASTW,
462	OP_PMASKMOVD,
463	OP_GATHER,
464	OP_FMADDSUB132PS,
465	OP_FMSUBADD132PS,
466	OP_FMADD132PS,
467	OP_FMADD132SS,
468	OP_FMSUB132PS,
469	OP_FMSUB132SS,
470	OP_FNMADD132PS,
471	OP_FNMADD132SS,
472	OP_FNMSUB132PS,
473	OP_FNMSUB132SS,
474	OP_FMADDSUB213PS,
475	OP_FMSUBADD213PS,
476	OP_FMADD213PS,
477	OP_FMADD213SS,
478	OP_FMSUB213PS,
479	OP_FMSUB213SS,
480	OP_FNMADD213PS,
481	OP_FNMADD213SS,
482	OP_FNMSUB213PS,
483	OP_FNMSUB213SS,
484	OP_FMADDSUB231PS,
485	OP_FMSUBADD231PS,
486	OP_FMADD231PS,
487	OP_FMADD231SS,
488	OP_FMSUB231PS,
489	OP_FMSUB231SS,
490	OP_FNMADD231PS,
491	OP_FNMADD231SS,
492	OP_FNMSUB231PS,
493	OP_FNMSUB231SS,
494	OP_AESIMC,
495	OP_AESENC,
496	OP_AESENCLAST,
497	OP_AESDEC,
498	OP_AESDECLAST,
499	OP_MOVBEGM,
500	OP_MOVBEMG,
501	OP_CRC32,
502	OP_POPCNT,
503	OP_TZCNT,
504	OP_LZCNT,
505	OP_ADCX,
506	OP_ADOX,
507	OP_ANDN,
508	OP_BZHI,
509	OP_BEXTR,
510	OP_BLSR,
511	OP_BLSMSK,
512	OP_BLSI,
513	OP_PEXT,
514	OP_PDEP,
515	OP_SHLX,
516	OP_SHRX,
517	OP_SARX,
518	OP_MULX,
519	OP_MASKMOVDQU,
520	OP_MASKMOVPS,
521	OP_MASKMOVPD,
522	OP_MOVSD,
523	OP_CVTSI2SD,
524	OP_CVTTSD2SI,
525	OP_CVTSD2SI,
526	OP_SQRTSD,
527	OP_ADDSD,
528	OP_MULSD,
529	OP_CVTSD2SS,
530	OP_SUBSD,
531	OP_MINSD,
532	OP_DIVSD,
533	OP_MAXSD,
534	OP_PSHUFLW,
535	OP_CMPSD,
536	OP_MOVDQ2Q,
537	OP_CVTPD2DQ,
538	OP_MOVSS,
539	OP_MOVSLDUP,
540	OP_MOVDDUP,
541	OP_MOVSHDUP,
542	OP_CVTSI2SS,
543	OP_CVTTSS2SI,
544	OP_CVTSS2SI,
545	OP_CVTSS2SD,
546	OP_SQRTSS,
547	OP_RSQRTSS,
548	OP_RCPSS,
549	OP_ADDSS,
550	OP_MULSS,
551	OP_CVTTPS2DQ,
552	OP_SUBSS,
553	OP_MINSS,
554	OP_DIVSS,
555	OP_MAXSS,
556	OP_MOVDQU,
557	OP_PSHUFHW,
558	OP_CMPSS,
559	OP_MOVQ2DQ,
560	OP_CVTDQ2PD,
561	OP_PERMQ,
562	OP_PERMPD,
563	OP_PBLENDD,
564	OP_PERM2F128,
565	OP_ROUNDPS,
566	OP_ROUNDPD,
567	OP_ROUNDSS,
568	OP_ROUNDSD,
569	OP_BLENDPS,
570	OP_BLENDPD,
571	OP_PBLENDW,
572	OP_PALIGNR,
573	OP_PEXTRB,
574	OP_PEXTRD,
575	OP_EXTRACTPS,
576	OP_INSERTF128,
577	OP_EXTRACTF128,
578	OP_CVTPS2PH,
579	OP_PINSRB,
580	OP_PINSRD,
581	OP_INSERTPS,
582	OP_INSERTI128,
583	OP_EXTRACTI128,
584	OP_DPPS,
585	OP_DPPD,
586	OP_MPSADBW,
587	OP_PCLMULQDQ,
588	OP_PERM2I128,
589	OP_PCMPESTRM,
590	OP_PCMPESTRI,
591	OP_PCMPISTRM,
592	OP_PCMPISTRI,
593	OP_AESKEYGEN,
594	OP_RORX,
595	OP_VEX3B,
596	OP_VEX2B,
597	/** @} */
598
599	/** @name Floating point ops
600	* @{ */
601	OP_FADD,
602	OP_FMUL,
603	OP_FCOM,
604	OP_FCOMP,
605	OP_FSUB,
606	OP_FSUBR,
607	OP_FDIV,
608	OP_FDIVR,
609	OP_FLD,
610	OP_FST,
611	OP_FSTP,
612	OP_FLDENV,
613	OP_FSTENV,
614	OP_FSTCW,
615	OP_FXCH,
616	OP_FNOP,
617	OP_FCHS,
618	OP_FABS,
619	OP_FLD1,
620	OP_FLDL2T,
621	OP_FLDL2E,
622	OP_FLDPI,
623	OP_FLDLG2,
624	OP_FLDLN2,
625	OP_FLDZ,
626	OP_F2XM1,
627	OP_FYL2X,
628	OP_FPTAN,
629	OP_FPATAN,
630	OP_FXTRACT,
631	OP_FREM1,
632	OP_FDECSTP,
633	OP_FINCSTP,
634	OP_FPREM,
635	OP_FYL2XP1,
636	OP_FSQRT,
637	OP_FSINCOS,
638	OP_FRNDINT,
639	OP_FSCALE,
640	OP_FSIN,
641	OP_FCOS,
642	OP_FIADD,
643	OP_FIMUL,
644	OP_FISUB,
645	OP_FISUBR,
646	OP_FIDIV,
647	OP_FIDIVR,
648	OP_FCMOVB,
649	OP_FCMOVE,
650	OP_FCMOVBE,
651	OP_FCMOVU,
652	OP_FUCOMPP,
653	OP_FILD,
654	OP_FIST,
655	OP_FISTP,
656	OP_FCMOVNB,
657	OP_FCMOVNE,
658	OP_FCMOVNBE,
659	OP_FCMOVNU,
660	OP_FCLEX,
661	OP_FINIT,
662	OP_FUCOMI,
663	OP_FCOMI,
664	OP_FRSTOR,
665	OP_FSAVE,
666	OP_FNSTSW,
667	OP_FFREE,
668	OP_FUCOM,
669	OP_FUCOMP,
670	OP_FICOM,
671	OP_FICOMP,
672	OP_FADDP,
673	OP_FMULP,
674	OP_FCOMPP,
675	OP_FSUBRP,
676	OP_FSUBP,
677	OP_FDIVRP,
678	OP_FDIVP,
679	OP_FBLD,
680	OP_FBSTP,
681	OP_FCOMIP,
682	OP_FUCOMIP,
683	/** @} */
684
685	/** @name 3DNow!
686	* @{ */
687	OP_PI2FW,
688	OP_PI2FD,
689	OP_PF2IW,
690	OP_PF2ID,
691	OP_PFPNACC,
692	OP_PFCMPGE,
693	OP_PFMIN,
694	OP_PFRCP,
695	OP_PFRSQRT,
696	OP_PFSUB,
697	OP_PFADD,
698	OP_PFCMPGT,
699	OP_PFMAX,
700	OP_PFRCPIT1,
701	OP_PFRSQRTIT1,
702	OP_PFSUBR,
703	OP_PFACC,
704	OP_PFCMPEQ,
705	OP_PFMUL,
706	OP_PFRCPIT2,
707	OP_PFMULHRW,
708	OP_PFSWAPD,
709	OP_PAVGUSB,
710	OP_PFNACC,
711	/** @} */
712	OP_ROL,
713	OP_ROR,
714	OP_RCL,
715	OP_RCR,
716	OP_SHL,
717	OP_SHR,
718	OP_SAR,
719	OP_NOT,
720	OP_NEG,
721	OP_MUL,
722	OP_DIV,
723	OP_IDIV,
724	OP_SLDT,
725	OP_STR,
726	OP_LLDT,
727	OP_LTR,
728	OP_VERR,
729	OP_VERW,
730	OP_SGDT,
731	OP_LGDT,
732	OP_SIDT,
733	OP_LIDT,
734	OP_SMSW,
735	OP_LMSW,
736	OP_INVLPG,
737	OP_CMPXCHG8B,
738	OP_PSLLQ,
739	OP_PSRLDQ,
740	OP_PSLLDQ,
741	OP_FXSAVE,
742	OP_FXRSTOR,
743	OP_LDMXCSR,
744	OP_STMXCSR,
745	OP_XSAVE,
746	OP_XSAVEOPT,
747	OP_XRSTOR,
748	OP_XGETBV,
749	OP_XSETBV,
750	OP_RDFSBASE,
751	OP_RDGSBASE,
752	OP_WRFSBASE,
753	OP_WRGSBASE,
754	OP_LFENCE,
755	OP_MFENCE,
756	OP_SFENCE,
757	OP_PREFETCH,
758	OP_MONITOR,
759	OP_MWAIT,
760	OP_CLFLUSH,
761	OP_CLFLUSHOPT,
762	OP_MOV_DR,
763	OP_MOV_TR,
764	OP_SWAPGS,
765	OP_UD1,
766	OP_UD2,
767	/** @name VT-x instructions
768	* @{ */
769	OP_VMREAD,
770	OP_VMWRITE,
771	OP_VMCALL,
772	OP_VMXON,
773	OP_VMXOFF,
774	OP_VMCLEAR,
775	OP_VMLAUNCH,
776	OP_VMRESUME,
777	OP_VMPTRLD,
778	OP_VMPTRST,
779	OP_INVEPT,
780	OP_INVVPID,
781	OP_INVPCID,
782	OP_VMFUNC,
783	/** @} */
784	/** @name AMD-V instructions
785	* @{ */
786	OP_VMMCALL,
787	OP_VMRUN,
788	OP_VMLOAD,
789	OP_VMSAVE,
790	OP_CLGI,
791	OP_STGI,
792	OP_INVLPGA,
793	OP_SKINIT,
794	/** @} */
795	/** @name 64 bits instruction
796	* @{ */
797	OP_MOVSXD,
798	/** @} */
799	/** @name AVX instructions
800	* @{ */
801	/* Manual */
802	OP_VSTMXCSR,
803	OP_VLDMXCSR,
804	OP_VPACKUSDW,
805
806	/* Generated from tables: */
807	OP_VADDPD,
808	OP_VADDPS,
809	OP_VADDSD,
810	OP_VADDSS,
811	OP_VADDSUBPD,
812	OP_VADDSUBPS,
813	OP_VAESDEC,
814	OP_VAESDECLAST,
815	OP_VAESENC,
816	OP_VAESENCLAST,
817	OP_VAESIMC,
818	OP_VAESKEYGEN,
819	OP_VANDNPD,
820	OP_VANDNPS,
821	OP_VANDPD,
822	OP_VANDPS,
823	OP_VBLENDPD,
824	OP_VBLENDPS,
825	OP_VBLENDVPD,
826	OP_VBLENDVPS,
827	OP_VBROADCASTF128,
828	OP_VBROADCASTSD,
829	OP_VBROADCASTSS,
830	OP_VCMPSD,
831	OP_VCMPSS,
832	OP_VCOMISD,
833	OP_VCOMISS,
834	OP_VCVTDQ2PD,
835	OP_VCVTDQ2PS,
836	OP_VCVTPD2DQ,
837	OP_VCVTPD2PS,
838	OP_VCVTPH2PS,
839	OP_VCVTPS2DQ,
840	OP_VCVTPS2PD,
841	OP_VCVTPS2PH,
842	OP_VCVTSD2SS,
843	OP_VCVTSI2SS,
844	OP_VCVTSS2SD,
845	OP_VCVTSS2SI,
846	OP_VCVTTPD2DQ,
847	OP_VCVTTPS2DQ,
848	OP_VCVTTSS2SI,
849	OP_VDIVPD,
850	OP_VDIVPS,
851	OP_VDIVSD,
852	OP_VDIVSS,
853	OP_VDPPD,
854	OP_VDPPS,
855	OP_VEXTRACTF128,
856	OP_VEXTRACTI128,
857	OP_VEXTRACTPS,
858	OP_VFMADD132PS,
859	OP_VFMADD132SS,
860	OP_VFMADD213PS,
861	OP_VFMADD213SS,
862	OP_VFMADD231PS,
863	OP_VFMADD231SS,
864	OP_VFMADDSUB132PS,
865	OP_VFMADDSUB213PS,
866	OP_VFMADDSUB231PS,
867	OP_VFMSUB132PS,
868	OP_VFMSUB132SS,
869	OP_VFMSUB213PS,
870	OP_VFMSUB213SS,
871	OP_VFMSUB231PS,
872	OP_VFMSUB231SS,
873	OP_VFMSUBADD132PS,
874	OP_VFMSUBADD213PS,
875	OP_VFMSUBADD231PS,
876	OP_VFNMADD132PS,
877	OP_VFNMADD132SS,
878	OP_VFNMADD213PS,
879	OP_VFNMADD213SS,
880	OP_VFNMADD231PS,
881	OP_VFNMADD231SS,
882	OP_VFNMSUB132PS,
883	OP_VFNMSUB132SS,
884	OP_VFNMSUB213PS,
885	OP_VFNMSUB213SS,
886	OP_VFNMSUB231PS,
887	OP_VFNMSUB231SS,
888	OP_VGATHER,
889	OP_VHADDPD,
890	OP_VHADDPS,
891	OP_VHSUBPD,
892	OP_VHSUBPS,
893	OP_VINSERTF128,
894	OP_VINSERTI128,
895	OP_VINSERTPS,
896	OP_VLDDQU,
897	OP_VMASKMOVDQU,
898	OP_VMASKMOVPD,
899	OP_VMASKMOVPS,
900	OP_VMAXPD,
901	OP_VMAXPS,
902	OP_VMAXSD,
903	OP_VMAXSS,
904	OP_VMINPD,
905	OP_VMINPS,
906	OP_VMINSD,
907	OP_VMINSS,
908	OP_VMOVAPD,
909	OP_VMOVAPS,
910	OP_VMOVD,
911	OP_VMOVDDUP,
912	OP_VMOVDQA,
913	OP_VMOVDQU,
914	OP_VMOVHPD,
915	OP_VMOVHPS,
916	OP_VMOVLHPS = OP_VMOVHPS, /*< @todo OP_VMOVHPS /
917	OP_VMOVLPD,
918	OP_VMOVLPS,
919	OP_VMOVHLPS = OP_VMOVLPS, /*< @todo OP_VMOVLPS /
920	OP_VMOVMSKPD,
921	OP_VMOVMSKPS,
922	OP_VMOVNTDQ,
923	OP_VMOVNTDQA,
924	OP_VMOVNTPD,
925	OP_VMOVNTPS,
926	OP_VMOVQ,
927	OP_VMOVSD,
928	OP_VMOVSHDUP,
929	OP_VMOVSLDUP,
930	OP_VMOVSS,
931	OP_VMOVUPD,
932	OP_VMOVUPS,
933	OP_VMPSADBW,
934	OP_VMULPD,
935	OP_VMULPS,
936	OP_VMULSD,
937	OP_VMULSS,
938	OP_VORPD,
939	OP_VORPS,
940	OP_VPABSB,
941	OP_VPABSD,
942	OP_VPABSW,
943	OP_VPACKSSDW,
944	OP_VPACKSSWB,
945	OP_VPACKUSWB,
946	OP_VPADDB,
947	OP_VPADDD,
948	OP_VPADDQ,
949	OP_VPADDSB,
950	OP_VPADDSW,
951	OP_VPADDUSB,
952	OP_VPADDUSW,
953	OP_VPADDW,
954	OP_VPALIGNR,
955	OP_VPAND,
956	OP_VPANDN,
957	OP_VPAVGB,
958	OP_VPAVGW,
959	OP_VPBLENDD,
960	OP_VPBLENDVB,
961	OP_VPBLENDW,
962	OP_VPBROADCASTB,
963	OP_VPBROADCASTD,
964	OP_VPBROADCASTI128,
965	OP_VPBROADCASTQ,
966	OP_VPBROADCASTW,
967	OP_VPCLMULQDQ,
968	OP_VPCMPEQB,
969	OP_VPCMPEQD,
970	OP_VPCMPEQQ,
971	OP_VPCMPEQW,
972	OP_VPCMPESTRI,
973	OP_VPCMPESTRM,
974	OP_VPCMPGTB,
975	OP_VPCMPGTD,
976	OP_VPCMPGTQ,
977	OP_VPCMPGTW,
978	OP_VPCMPISTRI,
979	OP_VPCMPISTRM,
980	OP_VPERM2F128,
981	OP_VPERM2I128,
982	OP_VPERMD,
983	OP_VPERMILPD,
984	OP_VPERMILPS,
985	OP_VPERMPD,
986	OP_VPERMPS,
987	OP_VPERMQ,
988	OP_VPEXTRB,
989	OP_VPEXTRD,
990	OP_VPEXTRW,
991	OP_VPHADDD,
992	OP_VPHADDSW,
993	OP_VPHADDW,
994	OP_VPHMINPOSUW,
995	OP_VPHSUBD,
996	OP_VPHSUBSW,
997	OP_VPHSUBW,
998	OP_VPINSRB,
999	OP_VPINSRD,
1000	OP_VPINSRW,
1001	OP_VPMADDUBSW,
1002	OP_VPMADDWD,
1003	OP_VPMASKMOVD,
1004	OP_VPMAXSB,
1005	OP_VPMAXSD,
1006	OP_VPMAXSW,
1007	OP_VPMAXUB,
1008	OP_VPMAXUD,
1009	OP_VPMAXUW,
1010	OP_VPMINSB,
1011	OP_VPMINSD,
1012	OP_VPMINSW,
1013	OP_VPMINUB,
1014	OP_VPMINUD,
1015	OP_VPMINUW,
1016	OP_VPMOVMSKB,
1017	OP_VPMOVSXBW,
1018	OP_VPMOVSXBD,
1019	OP_VPMOVSXBQ,
1020	OP_VPMOVSXWD,
1021	OP_VPMOVSXWQ,
1022	OP_VPMOVSXDQ,
1023	OP_VPMOVZXBW,
1024	OP_VPMOVZXBD,
1025	OP_VPMOVZXBQ,
1026	OP_VPMOVZXWD,
1027	OP_VPMOVZXWQ,
1028	OP_VPMOVZXDQ,
1029	OP_VPMULDQ,
1030	OP_VPMULHRSW,
1031	OP_VPMULHUW,
1032	OP_VPMULHW,
1033	OP_VPMULLD,
1034	OP_VPMULLW,
1035	OP_VPMULUDQ,
1036	OP_VPOR,
1037	OP_VPSADBW,
1038	OP_VPSHUFB,
1039	OP_VPSHUFD,
1040	OP_VPSHUFHW,
1041	OP_VPSHUFLW,
1042	OP_VPSIGNB,
1043	OP_VPSIGND,
1044	OP_VPSIGNW,
1045	OP_VPSLLD,
1046	OP_VPSLLQ,
1047	OP_VPSLLVD,
1048	OP_VPSLLW,
1049	OP_VPSRAD,
1050	OP_VPSRAVD,
1051	OP_VPSRAW,
1052	OP_VPSRLD,
1053	OP_VPSRLQ,
1054	OP_VPSRLVD,
1055	OP_VPSRLW,
1056	OP_VPSUBB,
1057	OP_VPSUBD,
1058	OP_VPSUBQ,
1059	OP_VPSUBSB,
1060	OP_VPSUBSW,
1061	OP_VPSUBUSB,
1062	OP_VPSUBUSW,
1063	OP_VPSUBW,
1064	OP_VPTEST,
1065	OP_VPUNPCKHBW,
1066	OP_VPUNPCKHDQ,
1067	OP_VPUNPCKHQDQ,
1068	OP_VPUNPCKHWD,
1069	OP_VPUNPCKLBW,
1070	OP_VPUNPCKLDQ,
1071	OP_VPUNPCKLQDQ,
1072	OP_VPUNPCKLWD,
1073	OP_VPXOR,
1074	OP_VRCPPS,
1075	OP_VRCPSS,
1076	OP_VROUNDPD,
1077	OP_VROUNDPS,
1078	OP_VROUNDSD,
1079	OP_VROUNDSS,
1080	OP_VRSQRTPS,
1081	OP_VRSQRTSS,
1082	OP_VSHUFPD,
1083	OP_VSHUFPS,
1084	OP_VSQRTPD,
1085	OP_VSQRTPS,
1086	OP_VSQRTSD,
1087	OP_VSQRTSS,
1088	OP_VSUBPD,
1089	OP_VSUBPS,
1090	OP_VSUBSD,
1091	OP_VSUBSS,
1092	OP_VTESTPD,
1093	OP_VTESTPS,
1094	OP_VUCOMISD,
1095	OP_VUCOMISS,
1096	OP_VUNPCKHPD,
1097	OP_VUNPCKHPS,
1098	OP_VUNPCKLPD,
1099	OP_VUNPCKLPS,
1100	OP_VVPACKUSDW,
1101	OP_VXORPD,
1102	OP_VXORPS,
1103	OP_VZEROALL,
1104
1105	/** @} */
1106	OP_END_OF_OPCODES
1107	};
1108	AssertCompile(OP_LOCK == 7);
1109	AssertCompile(OP_END_OF_OPCODES < 1024 /* see 15 byte DISOPCODE variant */);
1110	/** @} */
1111
1112
1113	/** @defgroup grp_dis_opparam Opcode parameters (DISOPCODE::fParam1,
1114	* DISOPCODE::fParam2, DISOPCODE::fParam3)
1115	* @ingroup grp_dis
1116	* @{
1117	*/
1118
1119	/**
1120	* @remarks Register order is important for translations!!
1121	*/
1122	enum OP_PARM
1123	{
1124	OP_PARM_NONE,
1125
1126	OP_PARM_REG_EAX,
1127	OP_PARM_REG_GEN32_START = OP_PARM_REG_EAX,
1128	OP_PARM_REG_ECX,
1129	OP_PARM_REG_EDX,
1130	OP_PARM_REG_EBX,
1131	OP_PARM_REG_ESP,
1132	OP_PARM_REG_EBP,
1133	OP_PARM_REG_ESI,
1134	OP_PARM_REG_EDI,
1135	OP_PARM_REG_GEN32_END = OP_PARM_REG_EDI,
1136
1137	OP_PARM_REG_ES,
1138	OP_PARM_REG_SEG_START = OP_PARM_REG_ES,
1139	OP_PARM_REG_CS,
1140	OP_PARM_REG_SS,
1141	OP_PARM_REG_DS,
1142	OP_PARM_REG_FS,
1143	OP_PARM_REG_GS,
1144	OP_PARM_REG_SEG_END = OP_PARM_REG_GS,
1145
1146	OP_PARM_REG_AX,
1147	OP_PARM_REG_GEN16_START = OP_PARM_REG_AX,
1148	OP_PARM_REG_CX,
1149	OP_PARM_REG_DX,
1150	OP_PARM_REG_BX,
1151	OP_PARM_REG_SP,
1152	OP_PARM_REG_BP,
1153	OP_PARM_REG_SI,
1154	OP_PARM_REG_DI,
1155	OP_PARM_REG_GEN16_END = OP_PARM_REG_DI,
1156
1157	OP_PARM_REG_AL,
1158	OP_PARM_REG_GEN8_START = OP_PARM_REG_AL,
1159	OP_PARM_REG_CL,
1160	OP_PARM_REG_DL,
1161	OP_PARM_REG_BL,
1162	OP_PARM_REG_AH,
1163	OP_PARM_REG_CH,
1164	OP_PARM_REG_DH,
1165	OP_PARM_REG_BH,
1166	OP_PARM_REG_GEN8_END = OP_PARM_REG_BH,
1167
1168	OP_PARM_REGFP_0,
1169	OP_PARM_REG_FP_START = OP_PARM_REGFP_0,
1170	OP_PARM_REGFP_1,
1171	OP_PARM_REGFP_2,
1172	OP_PARM_REGFP_3,
1173	OP_PARM_REGFP_4,
1174	OP_PARM_REGFP_5,
1175	OP_PARM_REGFP_6,
1176	OP_PARM_REGFP_7,
1177	OP_PARM_REG_FP_END = OP_PARM_REGFP_7,
1178
1179	OP_PARM_NTA,
1180	OP_PARM_T0,
1181	OP_PARM_T1,
1182	OP_PARM_T2,
1183	OP_PARM_1,
1184
1185	OP_PARM_REX,
1186	OP_PARM_REX_START = OP_PARM_REX,
1187	OP_PARM_REX_B,
1188	OP_PARM_REX_X,
1189	OP_PARM_REX_XB,
1190	OP_PARM_REX_R,
1191	OP_PARM_REX_RB,
1192	OP_PARM_REX_RX,
1193	OP_PARM_REX_RXB,
1194	OP_PARM_REX_W,
1195	OP_PARM_REX_WB,
1196	OP_PARM_REX_WX,
1197	OP_PARM_REX_WXB,
1198	OP_PARM_REX_WR,
1199	OP_PARM_REX_WRB,
1200	OP_PARM_REX_WRX,
1201	OP_PARM_REX_WRXB,
1202
1203	OP_PARM_REG_RAX,
1204	OP_PARM_REG_GEN64_START = OP_PARM_REG_RAX,
1205	OP_PARM_REG_RCX,
1206	OP_PARM_REG_RDX,
1207	OP_PARM_REG_RBX,
1208	OP_PARM_REG_RSP,
1209	OP_PARM_REG_RBP,
1210	OP_PARM_REG_RSI,
1211	OP_PARM_REG_RDI,
1212	OP_PARM_REG_R8,
1213	OP_PARM_REG_R9,
1214	OP_PARM_REG_R10,
1215	OP_PARM_REG_R11,
1216	OP_PARM_REG_R12,
1217	OP_PARM_REG_R13,
1218	OP_PARM_REG_R14,
1219	OP_PARM_REG_R15,
1220	OP_PARM_REG_GEN64_END = OP_PARM_REG_R15
1221	};
1222
1223
1224	/* 8-bit GRP aliases (for IEM). */
1225	#define OP_PARM_AL OP_PARM_REG_AL
1226
1227	/* GPR aliases for op-size specified register sizes (for IEM). */
1228	#define OP_PARM_rAX OP_PARM_REG_EAX
1229	#define OP_PARM_rCX OP_PARM_REG_ECX
1230	#define OP_PARM_rDX OP_PARM_REG_EDX
1231	#define OP_PARM_rBX OP_PARM_REG_EBX
1232	#define OP_PARM_rSP OP_PARM_REG_ESP
1233	#define OP_PARM_rBP OP_PARM_REG_EBP
1234	#define OP_PARM_rSI OP_PARM_REG_ESI
1235	#define OP_PARM_rDI OP_PARM_REG_EDI
1236
1237	/* SREG aliases (for IEM). */
1238	#define OP_PARM_ES OP_PARM_REG_ES
1239	#define OP_PARM_CS OP_PARM_REG_CS
1240	#define OP_PARM_SS OP_PARM_REG_SS
1241	#define OP_PARM_DS OP_PARM_REG_DS
1242	#define OP_PARM_FS OP_PARM_REG_FS
1243	#define OP_PARM_GS OP_PARM_REG_GS
1244
1245	/*
1246	* Note! We don't document anything here if we can help it, because it we love
1247	* wasting other peoples time figuring out crypting crap. The new VEX
1248	* stuff of course uphelds this vexing tradition. Aaaaaaaaaaaaaaaaaaarg!
1249	*/
1250
1251	#define OP_PARM_VTYPE(a) ((unsigned)a & 0xFE0)
1252	#define OP_PARM_VSUBTYPE(a) ((unsigned)a & 0x01F)
1253
1254	#define OP_PARM_A 0x100
1255	#define OP_PARM_VARIABLE OP_PARM_A
1256	#define OP_PARM_E 0x120
1257	#define OP_PARM_F 0x140
1258	#define OP_PARM_G 0x160
1259	#define OP_PARM_I 0x180
1260	#define OP_PARM_J 0x1A0
1261	#define OP_PARM_M 0x1C0
1262	#define OP_PARM_O 0x1E0
1263	#define OP_PARM_R 0x200
1264	#define OP_PARM_X 0x220
1265	#define OP_PARM_Y 0x240
1266
1267	/* Grouped rare parameters for optimization purposes */
1268	#define IS_OP_PARM_RARE(a) ((a & 0xF00) >= 0x300)
1269	#define OP_PARM_C 0x300 /* control register */
1270	#define OP_PARM_D 0x320 /* debug register */
1271	#define OP_PARM_S 0x340 /* segment register */
1272	#define OP_PARM_T 0x360 /* test register */
1273	#define OP_PARM_Q 0x380
1274	#define OP_PARM_P 0x3A0 /* mmx register */
1275	#define OP_PARM_W 0x3C0 /* xmm register */
1276	#define OP_PARM_V 0x3E0
1277	#define OP_PARM_U 0x400 /* The R/M field of the ModR/M byte selects XMM/YMM register. */
1278	#define OP_PARM_B 0x420 /* VEX.vvvv field select general purpose register. */
1279	#define OP_PARM_H 0x440
1280	#define OP_PARM_L 0x460
1281
1282	#define OP_PARM_NONE 0
1283	#define OP_PARM_a 0x1 /*< Operand to bound instruction. /
1284	#define OP_PARM_b 0x2 /*< Byte (always). /
1285	#define OP_PARM_d 0x3 /*< Double word (always). /
1286	#define OP_PARM_dq 0x4 /*< Double quad word (always). /
1287	#define OP_PARM_p 0x5 /*< Far pointer (subject to opsize). /
1288	#define OP_PARM_pd 0x6 /*< 128-bit or 256-bit double precision floating point data. /
1289	#define OP_PARM_pi 0x7 /*< Quad word MMX register. /
1290	#define OP_PARM_ps 0x8 /*< 128-bit or 256-bit single precision floating point data. /
1291	#define OP_PARM_q 0xA /*< Quad word (always). /
1292	#define OP_PARM_s 0xB /*< Descriptor table size (SIDT/LIDT/SGDT/LGDT). /
1293	#define OP_PARM_sd 0xC /*< Scalar element of 128-bit double precision floating point data. /
1294	#define OP_PARM_ss 0xD /*< Scalar element of 128-bit single precision floating point data. /
1295	#define OP_PARM_v 0xE /*< Word, double word, or quad word depending on opsize. /
1296	#define OP_PARM_w 0xF /*< Word (always). /
1297	#define OP_PARM_x 0x10 /*< Double quad word (dq) or quad quad word (qq) depending on opsize. /
1298	#define OP_PARM_y 0x11 /*< Double word or quad word depending on opsize. /
1299	#define OP_PARM_z 0x12 /*< Word (16-bit opsize) or double word (32-bit/64-bit opsize). /
1300	#define OP_PARM_qq 0x13 /*< Quad quad word. /
1301
1302
1303	#define OP_PARM_Ap (OP_PARM_A+OP_PARM_p)
1304	#define OP_PARM_By (OP_PARM_B+OP_PARM_y)
1305	#define OP_PARM_Cd (OP_PARM_C+OP_PARM_d)
1306	#define OP_PARM_Dd (OP_PARM_D+OP_PARM_d)
1307	#define OP_PARM_Eb (OP_PARM_E+OP_PARM_b)
1308	#define OP_PARM_Ed (OP_PARM_E+OP_PARM_d)
1309	#define OP_PARM_Ep (OP_PARM_E+OP_PARM_p)
1310	#define OP_PARM_Ev (OP_PARM_E+OP_PARM_v)
1311	#define OP_PARM_Ew (OP_PARM_E+OP_PARM_w)
1312	#define OP_PARM_Ey (OP_PARM_E+OP_PARM_y)
1313	#define OP_PARM_Fv (OP_PARM_F+OP_PARM_v)
1314	#define OP_PARM_Gb (OP_PARM_G+OP_PARM_b)
1315	#define OP_PARM_Gd (OP_PARM_G+OP_PARM_d)
1316	#define OP_PARM_Gv (OP_PARM_G+OP_PARM_v)
1317	#define OP_PARM_Gw (OP_PARM_G+OP_PARM_w)
1318	#define OP_PARM_Gy (OP_PARM_G+OP_PARM_y)
1319	#define OP_PARM_Hq (OP_PARM_H+OP_PARM_q)
1320	#define OP_PARM_Hps (OP_PARM_H+OP_PARM_ps)
1321	#define OP_PARM_Hpd (OP_PARM_H+OP_PARM_pd)
1322	#define OP_PARM_Hdq (OP_PARM_H+OP_PARM_dq)
1323	#define OP_PARM_Hqq (OP_PARM_H+OP_PARM_qq)
1324	#define OP_PARM_Hsd (OP_PARM_H+OP_PARM_sd)
1325	#define OP_PARM_Hss (OP_PARM_H+OP_PARM_ss)
1326	#define OP_PARM_Hx (OP_PARM_H+OP_PARM_x)
1327	#define OP_PARM_Ib (OP_PARM_I+OP_PARM_b)
1328	#define OP_PARM_Id (OP_PARM_I+OP_PARM_d)
1329	#define OP_PARM_Iq (OP_PARM_I+OP_PARM_q)
1330	#define OP_PARM_Iw (OP_PARM_I+OP_PARM_w)
1331	#define OP_PARM_Iv (OP_PARM_I+OP_PARM_v)
1332	#define OP_PARM_Iz (OP_PARM_I+OP_PARM_z)
1333	#define OP_PARM_Jb (OP_PARM_J+OP_PARM_b)
1334	#define OP_PARM_Jv (OP_PARM_J+OP_PARM_v)
1335	#define OP_PARM_Ma (OP_PARM_M+OP_PARM_a)
1336	#define OP_PARM_Mb (OP_PARM_M+OP_PARM_b)
1337	#define OP_PARM_Mw (OP_PARM_M+OP_PARM_w)
1338	#define OP_PARM_Md (OP_PARM_M+OP_PARM_d)
1339	#define OP_PARM_Mp (OP_PARM_M+OP_PARM_p)
1340	#define OP_PARM_Mq (OP_PARM_M+OP_PARM_q)
1341	#define OP_PARM_Mdq (OP_PARM_M+OP_PARM_dq)
1342	#define OP_PARM_Ms (OP_PARM_M+OP_PARM_s)
1343	#define OP_PARM_Mx (OP_PARM_M+OP_PARM_x)
1344	#define OP_PARM_My (OP_PARM_M+OP_PARM_y)
1345	#define OP_PARM_Mps (OP_PARM_M+OP_PARM_ps)
1346	#define OP_PARM_Mpd (OP_PARM_M+OP_PARM_pd)
1347	#define OP_PARM_Ob (OP_PARM_O+OP_PARM_b)
1348	#define OP_PARM_Ov (OP_PARM_O+OP_PARM_v)
1349	#define OP_PARM_Pq (OP_PARM_P+OP_PARM_q)
1350	#define OP_PARM_Pd (OP_PARM_P+OP_PARM_d)
1351	#define OP_PARM_Qd (OP_PARM_Q+OP_PARM_d)
1352	#define OP_PARM_Qq (OP_PARM_Q+OP_PARM_q)
1353	#define OP_PARM_Rd (OP_PARM_R+OP_PARM_d)
1354	#define OP_PARM_Rw (OP_PARM_R+OP_PARM_w)
1355	#define OP_PARM_Ry (OP_PARM_R+OP_PARM_y)
1356	#define OP_PARM_Sw (OP_PARM_S+OP_PARM_w)
1357	#define OP_PARM_Td (OP_PARM_T+OP_PARM_d)
1358	#define OP_PARM_Ux (OP_PARM_U+OP_PARM_x)
1359	#define OP_PARM_Vq (OP_PARM_V+OP_PARM_q)
1360	#define OP_PARM_Vx (OP_PARM_V+OP_PARM_x)
1361	#define OP_PARM_Vy (OP_PARM_V+OP_PARM_y)
1362	#define OP_PARM_Wq (OP_PARM_W+OP_PARM_q)
1363	/#define OP_PARM_Ws (OP_PARM_W+OP_PARM_s) - wtf? Same as lgdt (OP_PARM_Ms)?/
1364	#define OP_PARM_Wx (OP_PARM_W+OP_PARM_x)
1365	#define OP_PARM_Xb (OP_PARM_X+OP_PARM_b)
1366	#define OP_PARM_Xv (OP_PARM_X+OP_PARM_v)
1367	#define OP_PARM_Yb (OP_PARM_Y+OP_PARM_b)
1368	#define OP_PARM_Yv (OP_PARM_Y+OP_PARM_v)
1369
1370	#define OP_PARM_Vps (OP_PARM_V+OP_PARM_ps)
1371	#define OP_PARM_Vss (OP_PARM_V+OP_PARM_ss)
1372	#define OP_PARM_Vpd (OP_PARM_V+OP_PARM_pd)
1373	#define OP_PARM_Vdq (OP_PARM_V+OP_PARM_dq)
1374	#define OP_PARM_Wps (OP_PARM_W+OP_PARM_ps)
1375	#define OP_PARM_Wpd (OP_PARM_W+OP_PARM_pd)
1376	#define OP_PARM_Wss (OP_PARM_W+OP_PARM_ss)
1377	#define OP_PARM_Ww (OP_PARM_W+OP_PARM_w)
1378	#define OP_PARM_Wd (OP_PARM_W+OP_PARM_d)
1379	#define OP_PARM_Wq (OP_PARM_W+OP_PARM_q)
1380	#define OP_PARM_Wdq (OP_PARM_W+OP_PARM_dq)
1381	#define OP_PARM_Wqq (OP_PARM_W+OP_PARM_qq)
1382	#define OP_PARM_Ppi (OP_PARM_P+OP_PARM_pi)
1383	#define OP_PARM_Qpi (OP_PARM_Q+OP_PARM_pi)
1384	#define OP_PARM_Qdq (OP_PARM_Q+OP_PARM_dq)
1385	#define OP_PARM_Vsd (OP_PARM_V+OP_PARM_sd)
1386	#define OP_PARM_Wsd (OP_PARM_W+OP_PARM_sd)
1387	#define OP_PARM_Vqq (OP_PARM_V+OP_PARM_qq)
1388	#define OP_PARM_Pdq (OP_PARM_P+OP_PARM_dq)
1389	#define OP_PARM_Ups (OP_PARM_U+OP_PARM_ps)
1390	#define OP_PARM_Upd (OP_PARM_U+OP_PARM_pd)
1391	#define OP_PARM_Udq (OP_PARM_U+OP_PARM_dq)
1392	#define OP_PARM_Lx (OP_PARM_L+OP_PARM_x)
1393
1394	/* For making IEM / bs3-cpu-generated-1 happy: */
1395	#define OP_PARM_Ed_WO OP_PARM_Ed /*< Annotates write only operand. /
1396	#define OP_PARM_Eq (OP_PARM_E+OP_PARM_q)
1397	#define OP_PARM_Eq_WO OP_PARM_Eq /*< Annotates write only operand. /
1398	#define OP_PARM_Gv_RO OP_PARM_Gv /*< Annotates read only first operand (default is readwrite). /
1399	#define OP_PARM_HssHi OP_PARM_Hx /*< Register referenced by VEX.vvvv, bits [127:32]. /
1400	#define OP_PARM_HsdHi OP_PARM_Hx /*< Register referenced by VEX.vvvv, bits [127:64]. /
1401	#define OP_PARM_HqHi OP_PARM_Hx /*< Register referenced by VEX.vvvv, bits [127:64]. /
1402	#define OP_PARM_M_RO OP_PARM_M /*< Annotates read only memory of variable operand size (xrstor). /
1403	#define OP_PARM_M_RW OP_PARM_M /*< Annotates read-write memory of variable operand size (xsave). /
1404	#define OP_PARM_Mb_RO OP_PARM_Mb /*< Annotates read only memory byte operand. /
1405	#define OP_PARM_Md_RO OP_PARM_Md /*< Annotates read only memory operand. /
1406	#define OP_PARM_Md_WO OP_PARM_Md /*< Annotates write only memory operand. /
1407	#define OP_PARM_Mdq_WO OP_PARM_Mdq /*< Annotates write only memory operand. /
1408	#define OP_PARM_Mq_WO OP_PARM_Mq /*< Annotates write only memory quad word operand. /
1409	#define OP_PARM_Mps_WO OP_PARM_Mps /*< Annotates write only memory operand. /
1410	#define OP_PARM_Mpd_WO OP_PARM_Mpd /*< Annotates write only memory operand. /
1411	#define OP_PARM_Mx_WO OP_PARM_Mx /*< Annotates write only memory operand. /
1412	#define OP_PARM_PdZx_WO OP_PARM_Pd /*< Annotates write only operand and zero extends to 64-bit. /
1413	#define OP_PARM_Pq_WO OP_PARM_Pq /*< Annotates write only operand. /
1414	#define OP_PARM_Qq_WO OP_PARM_Qq /*< Annotates write only operand. /
1415	#define OP_PARM_Nq OP_PARM_Qq /*< Missing 'N' class (MMX reg selected by modrm.mem) in disasm. /
1416	#define OP_PARM_Uq (OP_PARM_U+OP_PARM_q)
1417	#define OP_PARM_UqHi (OP_PARM_U+OP_PARM_dq)
1418	#define OP_PARM_Uss (OP_PARM_U+OP_PARM_ss)
1419	#define OP_PARM_Uss_WO OP_PARM_Uss /*< Annotates write only operand. /
1420	#define OP_PARM_Usd (OP_PARM_U+OP_PARM_sd)
1421	#define OP_PARM_Usd_WO OP_PARM_Usd /*< Annotates write only operand. /
1422	#define OP_PARM_Vd (OP_PARM_V+OP_PARM_d)
1423	#define OP_PARM_Vd_WO OP_PARM_Vd /*< Annotates write only operand. /
1424	#define OP_PARM_VdZx_WO OP_PARM_Vd /*< Annotates that the registers get their upper bits cleared /
1425	#define OP_PARM_Vdq_WO OP_PARM_Vdq /*< Annotates that only YMM/XMM[127:64] are accessed. /
1426	#define OP_PARM_Vpd_WO OP_PARM_Vpd /*< Annotates write only operand. /
1427	#define OP_PARM_Vps_WO OP_PARM_Vps /*< Annotates write only operand. /
1428	#define OP_PARM_Vq_WO OP_PARM_Vq /*< Annotates write only operand. /
1429	#define OP_PARM_VqHi OP_PARM_Vdq /*< Annotates that only YMM/XMM[127:64] are accessed. /
1430	#define OP_PARM_VqHi_WO OP_PARM_Vdq /*< Annotates that only YMM/XMM[127:64] are written. /
1431	#define OP_PARM_VqZx_WO OP_PARM_Vq /*< Annotates that the registers get their upper bits cleared /
1432	#define OP_PARM_VsdZx_WO OP_PARM_Vsd /*< Annotates that the registers get their upper bits cleared. /
1433	#define OP_PARM_VssZx_WO OP_PARM_Vss /*< Annotates that the registers get their upper bits cleared. /
1434	#define OP_PARM_Vss_WO OP_PARM_Vss /*< Annotates write only operand. /
1435	#define OP_PARM_Vsd_WO OP_PARM_Vsd /*< Annotates write only operand. /
1436	#define OP_PARM_Vx_WO OP_PARM_Vx /*< Annotates write only operand. /
1437	#define OP_PARM_Wpd_WO OP_PARM_Wpd /*< Annotates write only operand. /
1438	#define OP_PARM_Wps_WO OP_PARM_Wps /*< Annotates write only operand. /
1439	#define OP_PARM_Wq_WO OP_PARM_Wq /*< Annotates write only operand. /
1440	#define OP_PARM_WqZxReg_WO OP_PARM_Wq /*< Annotates that register targets get their upper bits cleared. /
1441	#define OP_PARM_Wss_WO OP_PARM_Wss /*< Annotates write only operand. /
1442	#define OP_PARM_Wsd_WO OP_PARM_Wsd /*< Annotates write only operand. /
1443	#define OP_PARM_Wx_WO OP_PARM_Wx /*< Annotates write only operand. /
1444
1445	/** @} */
1446
1447	#endif /* !VBOX_INCLUDED_disopcode_h */
1448

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source: vbox/trunk/include/VBox/disopcode.h@ 96134

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