VirtualBox

source: vbox/trunk/include/VBox/em.h@ 29567

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1/** @file
2 * EM - Execution Monitor. (VMM)
3 */
4
5/*
6 * Copyright (C) 2006-2007 Oracle Corporation
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * The contents of this file may alternatively be used under the terms
17 * of the Common Development and Distribution License Version 1.0
18 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19 * VirtualBox OSE distribution, in which case the provisions of the
20 * CDDL are applicable instead of those of the GPL.
21 *
22 * You may elect to license modified versions of this file under the
23 * terms and conditions of either the GPL or the CDDL or both.
24 */
25
26#ifndef ___VBox_em_h
27#define ___VBox_em_h
28
29#include <VBox/cdefs.h>
30#include <VBox/types.h>
31#include <VBox/trpm.h>
32#include <VBox/dis.h>
33
34RT_C_DECLS_BEGIN
35
36/** @defgroup grp_em The Execution Monitor / Manager API
37 * @{
38 */
39
40/** Enable to allow V86 code to run in raw mode. */
41#define VBOX_RAW_V86
42
43/**
44 * The Execution Manager State.
45 */
46typedef enum EMSTATE
47{
48 /** Not yet started. */
49 EMSTATE_NONE = 1,
50 /** Raw-mode execution. */
51 EMSTATE_RAW,
52 /** Hardware accelerated raw-mode execution. */
53 EMSTATE_HWACC,
54 /** PARAV function. */
55 EMSTATE_PARAV,
56 /** Recompiled mode execution. */
57 EMSTATE_REM,
58 /** Execution is halted. (waiting for interrupt) */
59 EMSTATE_HALTED,
60 /** Application processor execution is halted. (waiting for startup IPI (SIPI)) */
61 EMSTATE_WAIT_SIPI,
62 /** Execution is suspended. */
63 EMSTATE_SUSPENDED,
64 /** The VM is terminating. */
65 EMSTATE_TERMINATING,
66 /** Guest debug event from raw-mode is being processed. */
67 EMSTATE_DEBUG_GUEST_RAW,
68 /** Guest debug event from hardware accelerated mode is being processed. */
69 EMSTATE_DEBUG_GUEST_HWACC,
70 /** Guest debug event from recompiled-mode is being processed. */
71 EMSTATE_DEBUG_GUEST_REM,
72 /** Hypervisor debug event being processed. */
73 EMSTATE_DEBUG_HYPER,
74 /** The VM has encountered a fatal error. (And everyone is panicing....) */
75 EMSTATE_GURU_MEDITATION,
76 /** Just a hack to ensure that we get a 32-bit integer. */
77 EMSTATE_MAKE_32BIT_HACK = 0x7fffffff
78} EMSTATE;
79
80
81/**
82 * EMInterpretInstructionCPUEx execution modes.
83 */
84typedef enum
85{
86 /** Only supervisor code (CPL=0). */
87 EMCODETYPE_SUPERVISOR,
88 /** User-level code only. */
89 EMCODETYPE_USER,
90 /** Supervisor and user-level code (use with great care!). */
91 EMCODETYPE_ALL,
92 /** Just a hack to ensure that we get a 32-bit integer. */
93 EMCODETYPE_32BIT_HACK = 0x7fffffff
94} EMCODETYPE;
95
96VMMDECL(EMSTATE) EMGetState(PVMCPU pVCpu);
97VMMDECL(void) EMSetState(PVMCPU pVCpu, EMSTATE enmNewState);
98
99/** @name Callback handlers for instruction emulation functions.
100 * These are placed here because IOM wants to use them as well.
101 * @{
102 */
103typedef DECLCALLBACK(uint32_t) FNEMULATEPARAM2UINT32(void *pvParam1, uint64_t val2);
104typedef FNEMULATEPARAM2UINT32 *PFNEMULATEPARAM2UINT32;
105typedef DECLCALLBACK(uint32_t) FNEMULATEPARAM2(void *pvParam1, size_t val2);
106typedef FNEMULATEPARAM2 *PFNEMULATEPARAM2;
107typedef DECLCALLBACK(uint32_t) FNEMULATEPARAM3(void *pvParam1, uint64_t val2, size_t val3);
108typedef FNEMULATEPARAM3 *PFNEMULATEPARAM3;
109typedef DECLCALLBACK(int) FNEMULATELOCKPARAM2(void *pvParam1, uint64_t val2, RTGCUINTREG32 *pf);
110typedef FNEMULATELOCKPARAM2 *PFNEMULATELOCKPARAM2;
111typedef DECLCALLBACK(int) FNEMULATELOCKPARAM3(void *pvParam1, uint64_t val2, size_t cb, RTGCUINTREG32 *pf);
112typedef FNEMULATELOCKPARAM3 *PFNEMULATELOCKPARAM3;
113/** @} */
114
115
116/**
117 * Checks if raw ring-3 execute mode is enabled.
118 *
119 * @returns true if enabled.
120 * @returns false if disabled.
121 * @param pVM The VM to operate on.
122 */
123#define EMIsRawRing3Enabled(pVM) ((pVM)->fRawR3Enabled)
124
125/**
126 * Checks if raw ring-0 execute mode is enabled.
127 *
128 * @returns true if enabled.
129 * @returns false if disabled.
130 * @param pVM The VM to operate on.
131 */
132#define EMIsRawRing0Enabled(pVM) ((pVM)->fRawR0Enabled)
133
134VMMDECL(void) EMSetInhibitInterruptsPC(PVMCPU pVCpu, RTGCUINTPTR PC);
135VMMDECL(RTGCUINTPTR) EMGetInhibitInterruptsPC(PVMCPU pVCpu);
136VMMDECL(int) EMInterpretDisasOne(PVM pVM, PVMCPU pVCpu, PCCPUMCTXCORE pCtxCore, PDISCPUSTATE pCpu, unsigned *pcbInstr);
137VMMDECL(int) EMInterpretDisasOneEx(PVM pVM, PVMCPU pVCpu, RTGCUINTPTR GCPtrInstr, PCCPUMCTXCORE pCtxCore,
138 PDISCPUSTATE pDISState, unsigned *pcbInstr);
139VMMDECL(int) EMInterpretInstruction(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize);
140VMMDECL(int) EMInterpretInstructionCPUEx(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDISState, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize, EMCODETYPE enmCodeType);
141VMMDECL(int) EMInterpretCpuId(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame);
142VMMDECL(int) EMInterpretRdtsc(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame);
143VMMDECL(int) EMInterpretRdpmc(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame);
144VMMDECL(int) EMInterpretRdtscp(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
145VMMDECL(int) EMInterpretInvlpg(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pAddrGC);
146VMMDECL(int) EMInterpretIret(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame);
147VMMDECL(int) EMInterpretMWait(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame);
148VMMDECL(int) EMInterpretMonitor(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame);
149VMMDECL(int) EMInterpretDRxWrite(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegDrx, uint32_t SrcRegGen);
150VMMDECL(int) EMInterpretDRxRead(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegGen, uint32_t SrcRegDrx);
151VMMDECL(int) EMInterpretCRxWrite(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegCrx, uint32_t SrcRegGen);
152VMMDECL(int) EMInterpretCRxRead(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegGen, uint32_t SrcRegCrx);
153VMMDECL(int) EMInterpretLMSW(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint16_t u16Data);
154VMMDECL(int) EMInterpretCLTS(PVM pVM, PVMCPU pVCpu);
155VMMDECL(VBOXSTRICTRC) EMInterpretPortIO(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, PDISCPUSTATE pCpu, uint32_t cbOp);
156VMMDECL(int) EMInterpretRdmsr(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame);
157VMMDECL(int) EMInterpretWrmsr(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame);
158VMMDECL(bool) EMShouldContinueAfterHalt(PVMCPU pVCpu, PCPUMCTX pCtx);
159
160/* Wrap EMInterpretInstructionCPUEx for supervisor code only interpretation.
161 */
162inline int EMInterpretInstructionCPU(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDISState, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
163{
164 return EMInterpretInstructionCPUEx(pVM, pVCpu, pDISState, pRegFrame, pvFault, pcbSize, EMCODETYPE_SUPERVISOR);
165}
166
167/** @name Assembly routines
168 * @{ */
169VMMDECL(uint32_t) EMEmulateCmp(uint32_t u32Param1, uint64_t u64Param2, size_t cb);
170VMMDECL(uint32_t) EMEmulateAnd(void *pvParam1, uint64_t u64Param2, size_t cb);
171VMMDECL(uint32_t) EMEmulateInc(void *pvParam1, size_t cb);
172VMMDECL(uint32_t) EMEmulateDec(void *pvParam1, size_t cb);
173VMMDECL(uint32_t) EMEmulateOr(void *pvParam1, uint64_t u64Param2, size_t cb);
174VMMDECL(int) EMEmulateLockOr(void *pvParam1, uint64_t u64Param2, size_t cbSize, RTGCUINTREG32 *pf);
175VMMDECL(uint32_t) EMEmulateXor(void *pvParam1, uint64_t u64Param2, size_t cb);
176VMMDECL(int) EMEmulateLockXor(void *pvParam1, uint64_t u64Param2, size_t cbSize, RTGCUINTREG32 *pf);
177VMMDECL(uint32_t) EMEmulateAdd(void *pvParam1, uint64_t u64Param2, size_t cb);
178VMMDECL(int) EMEmulateLockAnd(void *pvParam1, uint64_t u64Param2, size_t cbSize, RTGCUINTREG32 *pf);
179VMMDECL(uint32_t) EMEmulateSub(void *pvParam1, uint64_t u64Param2, size_t cb);
180VMMDECL(uint32_t) EMEmulateAdcWithCarrySet(void *pvParam1, uint64_t u64Param2, size_t cb);
181VMMDECL(uint32_t) EMEmulateBtr(void *pvParam1, uint64_t u64Param2);
182VMMDECL(int) EMEmulateLockBtr(void *pvParam1, uint64_t u64Param2, RTGCUINTREG32 *pf);
183VMMDECL(uint32_t) EMEmulateBts(void *pvParam1, uint64_t u64Param2);
184VMMDECL(uint32_t) EMEmulateBtc(void *pvParam1, uint64_t u64Param2);
185VMMDECL(uint32_t) EMEmulateCmpXchg(void *pvParam1, uint64_t *pu32Param2, uint64_t u32Param3, size_t cbSize);
186VMMDECL(uint32_t) EMEmulateLockCmpXchg(void *pvParam1, uint64_t *pu64Param2, uint64_t u64Param3, size_t cbSize);
187VMMDECL(uint32_t) EMEmulateCmpXchg8b(void *pu32Param1, uint32_t *pEAX, uint32_t *pEDX, uint32_t uEBX, uint32_t uECX);
188VMMDECL(uint32_t) EMEmulateLockCmpXchg8b(void *pu32Param1, uint32_t *pEAX, uint32_t *pEDX, uint32_t uEBX, uint32_t uECX);
189/** @} */
190
191/** @name REM locking routines
192 * @{ */
193VMMDECL(void) EMRemUnlock(PVM pVM);
194VMMDECL(void) EMRemLock(PVM pVM);
195VMMDECL(bool) EMRemIsLockOwner(PVM pVM);
196VMMDECL(int) EMTryEnterRemLock(PVM pVM);
197/** @} */
198
199#ifdef IN_RING3
200/** @defgroup grp_em_r3 The EM Host Context Ring-3 API
201 * @ingroup grp_em
202 * @{
203 */
204VMMR3DECL(int) EMR3Init(PVM pVM);
205VMMR3DECL(int) EMR3InitCPU(PVM pVM);
206VMMR3DECL(void) EMR3Relocate(PVM pVM);
207VMMR3DECL(void) EMR3ResetCpu(PVMCPU pVCpu);
208VMMR3DECL(void) EMR3Reset(PVM pVM);
209VMMR3DECL(int) EMR3Term(PVM pVM);
210VMMR3DECL(int) EMR3TermCPU(PVM pVM);
211VMMR3DECL(DECLNORETURN(void)) EMR3FatalError(PVMCPU pVCpu, int rc);
212VMMR3DECL(int) EMR3ExecuteVM(PVM pVM, PVMCPU pVCpu);
213VMMR3DECL(int) EMR3CheckRawForcedActions(PVM pVM, PVMCPU pVCpu);
214VMMR3DECL(int) EMR3Interpret(PVM pVM);
215
216VMMR3DECL(void) EMR3ReleaseOwnedLocks(PVM pVM);
217
218/**
219 * Command argument for EMR3RawSetMode().
220 *
221 * It's possible to extend this interface to change several
222 * execution modes at once should the need arise.
223 */
224typedef enum EMRAWMODE
225{
226 /** No raw execution. */
227 EMRAW_NONE = 0,
228 /** Enable Only ring-3 raw execution. */
229 EMRAW_RING3_ENABLE,
230 /** Only ring-3 raw execution. */
231 EMRAW_RING3_DISABLE,
232 /** Enable raw ring-0 execution. */
233 EMRAW_RING0_ENABLE,
234 /** Disable raw ring-0 execution. */
235 EMRAW_RING0_DISABLE,
236 EMRAW_END
237} EMRAWMODE;
238
239VMMR3DECL(int) EMR3RawSetMode(PVM pVM, EMRAWMODE enmMode);
240/** @} */
241#endif /* IN_RING3 */
242
243
244#ifdef IN_RC
245/** @defgroup grp_em_gc The EM Guest Context API
246 * @ingroup grp_em
247 * @{
248 */
249VMMRCDECL(int) EMGCTrap(PVM pVM, unsigned uTrap, PCPUMCTXCORE pRegFrame);
250VMMRCDECL(uint32_t) EMGCEmulateLockCmpXchg(RTRCPTR pu32Param1, uint32_t *pu32Param2, uint32_t u32Param3, size_t cbSize, uint32_t *pEflags);
251VMMRCDECL(uint32_t) EMGCEmulateCmpXchg(RTRCPTR pu32Param1, uint32_t *pu32Param2, uint32_t u32Param3, size_t cbSize, uint32_t *pEflags);
252VMMRCDECL(uint32_t) EMGCEmulateLockCmpXchg8b(RTRCPTR pu32Param1, uint32_t *pEAX, uint32_t *pEDX, uint32_t uEBX, uint32_t uECX, uint32_t *pEflags);
253VMMRCDECL(uint32_t) EMGCEmulateCmpXchg8b(RTRCPTR pu32Param1, uint32_t *pEAX, uint32_t *pEDX, uint32_t uEBX, uint32_t uECX, uint32_t *pEflags);
254VMMRCDECL(uint32_t) EMGCEmulateLockXAdd(RTRCPTR pu32Param1, uint32_t *pu32Param2, size_t cbSize, uint32_t *pEflags);
255VMMRCDECL(uint32_t) EMGCEmulateXAdd(RTRCPTR pu32Param1, uint32_t *pu32Param2, size_t cbSize, uint32_t *pEflags);
256/** @} */
257#endif /* IN_RC */
258
259/** @} */
260
261RT_C_DECLS_END
262
263#endif
264
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