| 1 | /** @file
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| 2 | * ARMv8 GIC Interrupt Translation Service (ITS) definitions.
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| 3 | */
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| 4 |
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| 5 | /*
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| 6 | * Copyright (C) 2025 Oracle and/or its affiliates.
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| 7 | *
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| 8 | * This file is part of VirtualBox base platform packages, as
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| 9 | * available from https://www.virtualbox.org.
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| 10 | *
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| 11 | * This program is free software; you can redistribute it and/or
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| 12 | * modify it under the terms of the GNU General Public License
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| 13 | * as published by the Free Software Foundation, in version 3 of the
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| 14 | * License.
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| 15 | *
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| 16 | * This program is distributed in the hope that it will be useful, but
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| 17 | * WITHOUT ANY WARRANTY; without even the implied warranty of
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| 18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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| 19 | * General Public License for more details.
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| 20 | *
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| 21 | * You should have received a copy of the GNU General Public License
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| 22 | * along with this program; if not, see <https://www.gnu.org/licenses>.
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| 23 | *
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| 24 | * The contents of this file may alternatively be used under the terms
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| 25 | * of the Common Development and Distribution License Version 1.0
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| 26 | * (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
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| 27 | * in the VirtualBox distribution, in which case the provisions of the
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| 28 | * CDDL are applicable instead of those of the GPL.
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| 29 | *
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| 30 | * You may elect to license modified versions of this file under the
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| 31 | * terms and conditions of either the GPL or the CDDL or both.
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| 32 | *
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| 33 | * SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
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| 34 | */
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| 35 |
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| 36 | #ifndef VBOX_INCLUDED_gic_its_h
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| 37 | #define VBOX_INCLUDED_gic_its_h
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| 38 | #ifndef RT_WITHOUT_PRAGMA_ONCE
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| 39 | # pragma once
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| 40 | #endif
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| 41 |
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| 42 | #include <iprt/types.h>
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| 43 | #include <iprt/assertcompile.h>
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| 44 |
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| 45 | /** Size of the ITS register frame. */
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| 46 | #define GITS_REG_FRAME_SIZE _64K
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| 47 |
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| 48 | /** The GITS command queue page size. */
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| 49 | #define GITS_CMD_QUEUE_PAGE_SIZE 0x1000
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| 50 | /** The GITS command queue page offset mask. */
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| 51 | #define GITS_CMD_QUEUE_PAGE_OFFSET_MASK 0xfff
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| 52 | /** The guest page shift (x86). */
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| 53 | #define GITS_CMD_QUEUE_PAGE_SHIFT 12
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| 54 |
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| 55 | /** The GITS command size in bytes. */
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| 56 | #define GITS_CMD_SIZE 32
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| 57 |
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| 58 | /** GITS_CTLR: Control register - RW. */
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| 59 | #define GITS_CTRL_REG_CTLR_OFF 0x0000
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| 60 | /** GITS_CTLR: Enabled. */
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| 61 | #define GITS_BF_CTRL_REG_CTLR_ENABLED_SHIFT 0
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| 62 | #define GITS_BF_CTRL_REG_CTLR_ENABLED_MASK UINT32_C(0x00000001)
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| 63 | /** GITS_CTLR: ImDe - Implementation Defined. */
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| 64 | #define GITS_BF_CTRL_REG_CTLR_IM_DE_SHIFT 1
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| 65 | #define GITS_BF_CTRL_REG_CTLR_IM_DE_MASK UINT32_C(0x00000002)
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| 66 | /** GITS_CTLR: Reserved (bits 3:2). */
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| 67 | #define GITS_BF_CTRL_REG_CTLR_RSVD_3_2_SHIFT 2
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| 68 | #define GITS_BF_CTRL_REG_CTLR_RSVD_3_2_MASK UINT32_C(0x0000000c)
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| 69 | /** GITS_CTLR: ITS_Number (0 for GICv3). */
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| 70 | #define GITS_BF_CTRL_REG_CTLR_ITS_NUMBER_SHIFT 4
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| 71 | #define GITS_BF_CTRL_REG_CTLR_ITS_NUMBER_MASK UINT32_C(0x000000f0)
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| 72 | /** GITS_CTLR: UMSIirq - Unmapped MSI reporting interrupt enable. */
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| 73 | #define GITS_BF_CTRL_REG_CTLR_UMSI_IRQ_SHIFT 8
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| 74 | #define GITS_BF_CTRL_REG_CTLR_UMSI_IRQ_MASK UINT32_C(0x00000100)
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| 75 | /** GITS_CTLR: Reserved (bits 30:9). */
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| 76 | #define GITS_BF_CTRL_REG_CTLR_RSVD_30_9_SHIFT 9
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| 77 | #define GITS_BF_CTRL_REG_CTLR_RSVD_30_9_MASK UINT32_C(0x7ffffe00)
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| 78 | /** GITS_CTLR: Quiescent. */
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| 79 | #define GITS_BF_CTRL_REG_CTLR_QUIESCENT_SHIFT 31
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| 80 | #define GITS_BF_CTRL_REG_CTLR_QUIESCENT_MASK UINT32_C(0x80000000)
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| 81 | RT_BF_ASSERT_COMPILE_CHECKS(GITS_BF_CTRL_REG_CTLR_, UINT32_C(0), UINT32_MAX,
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| 82 | (ENABLED, IM_DE, RSVD_3_2, ITS_NUMBER, UMSI_IRQ, RSVD_30_9, QUIESCENT));
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| 83 | /** GITS_CTLR: Mask of valid read-write bits. */
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| 84 | #define GITS_BF_CTRL_REG_CTLR_RW_MASK (UINT32_MAX & ~( GITS_BF_CTRL_REG_CTLR_IM_DE_MASK \
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| 85 | | GITS_BF_CTRL_REG_CTLR_RSVD_3_2_MASK \
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| 86 | | GITS_BF_CTRL_REG_CTLR_ITS_NUMBER_MASK \
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| 87 | | GITS_BF_CTRL_REG_CTLR_RSVD_30_9_MASK \
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| 88 | | GITS_BF_CTRL_REG_CTLR_QUIESCENT_MASK))
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| 89 |
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| 90 | /** GITS_IIDR: Implementer and revision register - RO. */
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| 91 | #define GITS_CTRL_REG_IIDR_OFF 0x0004
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| 92 | /** GITS_IIDR: Implementer - JEP106 identification code. */
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| 93 | #define GITS_BF_CTRL_REG_IIDR_IMPL_ID_CODE_SHIFT 0
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| 94 | #define GITS_BF_CTRL_REG_IIDR_IMPL_ID_CODE_MASK UINT32_C(0x0000007f)
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| 95 | /** GITS_IIDR: Implementer - Reserved (bit 7). */
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| 96 | #define GITS_BF_CTRL_REG_IIDR_IMPL_ZERO_7_SHIFT 7
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| 97 | #define GITS_BF_CTRL_REG_IIDR_IMPL_ZERO_7_MASK UINT32_C(0x00000080)
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| 98 | /** GITS_IIDR: Implementer - JEP106 continuation code. */
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| 99 | #define GITS_BF_CTRL_REG_IIDR_IMPL_CONT_CODE_SHIFT 8
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| 100 | #define GITS_BF_CTRL_REG_IIDR_IMPL_CONT_CODE_MASK UINT32_C(0x00000f00)
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| 101 | /** GITS_IIDR: Revision. */
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| 102 | #define GITS_BF_CTRL_REG_IIDR_REVISION_SHIFT 12
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| 103 | #define GITS_BF_CTRL_REG_IIDR_REVISION_MASK UINT32_C(0x0000f000)
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| 104 | /** GITS_IIDR: Variant. */
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| 105 | #define GITS_BF_CTRL_REG_IIDR_VARIANT_SHIFT 16
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| 106 | #define GITS_BF_CTRL_REG_IIDR_VARIANT_MASK UINT32_C(0x000f0000)
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| 107 | /** GITS_IIDR: Reserved (bits 23:20). */
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| 108 | #define GITS_BF_CTRL_REG_IIDR_RSVD_23_20_SHIFT 20
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| 109 | #define GITS_BF_CTRL_REG_IIDR_RSVD_23_20_MASK UINT32_C(0x00f00000)
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| 110 | /** GITS_IIDR: Product ID. */
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| 111 | #define GITS_BF_CTRL_REG_IIDR_PRODUCT_ID_SHIFT 24
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| 112 | #define GITS_BF_CTRL_REG_IIDR_PRODUCT_ID_MASK UINT32_C(0xff000000)
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| 113 | RT_BF_ASSERT_COMPILE_CHECKS(GITS_BF_CTRL_REG_IIDR_, UINT32_C(0), UINT32_MAX,
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| 114 | (IMPL_ID_CODE, IMPL_ZERO_7, IMPL_CONT_CODE, REVISION, VARIANT, RSVD_23_20, PRODUCT_ID));
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| 115 |
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| 116 | /** GITS_TYPER: Feature register - RO. */
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| 117 | #define GITS_CTRL_REG_TYPER_OFF 0x0008
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| 118 | /** GITS_TYPER: Physical - Physical LPI support. */
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| 119 | #define GITS_BF_CTRL_REG_TYPER_PHYSICAL_SHIFT 0
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| 120 | #define GITS_BF_CTRL_REG_TYPER_PHYSICAL_MASK UINT64_C(0x0000000000000001)
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| 121 | /** GITS_TYPER: Virtual - Virtual LPI support. */
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| 122 | #define GITS_BF_CTRL_REG_TYPER_VIRTUAL_SHIFT 1
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| 123 | #define GITS_BF_CTRL_REG_TYPER_VIRTUAL_MASK UINT64_C(0x0000000000000002)
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| 124 | /** GITS_TYPER: CCT - Cumulative Collections Table. */
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| 125 | #define GITS_BF_CTRL_REG_TYPER_CCT_SHIFT 2
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| 126 | #define GITS_BF_CTRL_REG_TYPER_CCT_MASK UINT64_C(0x0000000000000004)
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| 127 | /** GITS_TYPER: Implementation Defined. */
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| 128 | #define GITS_BF_CTRL_REG_TYPER_IM_DE_SHIFT 3
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| 129 | #define GITS_BF_CTRL_REG_TYPER_IM_DE_MASK UINT64_C(0x0000000000000008)
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| 130 | /** GITS_TYPER: ITT_entry_size - Size of translation table entry. */
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| 131 | #define GITS_BF_CTRL_REG_TYPER_ITT_ENTRY_SIZE_SHIFT 4
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| 132 | #define GITS_BF_CTRL_REG_TYPER_ITT_ENTRY_SIZE_MASK UINT64_C(0x00000000000000f0)
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| 133 | /** GITS_TYPER: ID_bits - Number of event ID bits implemented (minus one). */
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| 134 | #define GITS_BF_CTRL_REG_TYPER_ID_BITS_SHIFT 8
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| 135 | #define GITS_BF_CTRL_REG_TYPER_ID_BITS_MASK UINT64_C(0x0000000000001f00)
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| 136 | /** GITS_TYPER: Devbits - Number of device ID bits implemented (minus one). */
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| 137 | #define GITS_BF_CTRL_REG_TYPER_DEV_BITS_SHIFT 13
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| 138 | #define GITS_BF_CTRL_REG_TYPER_DEV_BITS_MASK UINT64_C(0x000000000003e000)
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| 139 | /** GITS_TYPER: SEIS - SEI support for virtual CPUs. */
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| 140 | #define GITS_BF_CTRL_REG_TYPER_SEIS_SHIFT 18
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| 141 | #define GITS_BF_CTRL_REG_TYPER_SEIS_MASK UINT64_C(0x0000000000040000)
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| 142 | /** GITS_TYPER: PTA - Physical target address format. */
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| 143 | #define GITS_BF_CTRL_REG_TYPER_PTA_SHIFT 19
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| 144 | #define GITS_BF_CTRL_REG_TYPER_PTA_MASK UINT64_C(0x0000000000080000)
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| 145 | /** GITS_TYPER: Reserved (bits 23:20). */
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| 146 | #define GITS_BF_CTRL_REG_TYPER_RSVD_23_20_SHIFT 20
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| 147 | #define GITS_BF_CTRL_REG_TYPER_RSVD_23_20_MASK UINT64_C(0x0000000000f00000)
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| 148 | /** GITS_TYPER: HCC - Hardware collection count. */
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| 149 | #define GITS_BF_CTRL_REG_TYPER_HCC_SHIFT 24
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| 150 | #define GITS_BF_CTRL_REG_TYPER_HCC_MASK UINT64_C(0x00000000ff000000)
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| 151 | /** GITS_TYPER: CIDbits - Number of collection ID bits (minus one). */
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| 152 | #define GITS_BF_CTRL_REG_TYPER_CID_BITS_SHIFT 32
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| 153 | #define GITS_BF_CTRL_REG_TYPER_CID_BITS_MASK UINT64_C(0x0000000f00000000)
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| 154 | /** GITS_TYPER: CIL - Collection ID limit. */
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| 155 | #define GITS_BF_CTRL_REG_TYPER_CIL_SHIFT 36
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| 156 | #define GITS_BF_CTRL_REG_TYPER_CIL_MASK UINT64_C(0x0000001000000000)
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| 157 | /** GITS_TYPER: VMOVP - Form of VMOVP command. */
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| 158 | #define GITS_BF_CTRL_REG_TYPER_VMOVP_SHIFT 37
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| 159 | #define GITS_BF_CTRL_REG_TYPER_VMOVP_MASK UINT64_C(0x0000002000000000)
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| 160 | /** GITS_TYPER: MPAM - Memory partitioning and monitoring support. */
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| 161 | #define GITS_BF_CTRL_REG_TYPER_MPAM_SHIFT 38
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| 162 | #define GITS_BF_CTRL_REG_TYPER_MPAM_MASK UINT64_C(0x0000004000000000)
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| 163 | /** GITS_TYPER: VSGI - Direct injection of virtual SGI support. */
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| 164 | #define GITS_BF_CTRL_REG_TYPER_VSGI_SHIFT 39
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| 165 | #define GITS_BF_CTRL_REG_TYPER_VSGI_MASK UINT64_C(0x0000008000000000)
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| 166 | /** GITS_TYPER: VMAPP - VMAPP command support. */
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| 167 | #define GITS_BF_CTRL_REG_TYPER_VMAPP_SHIFT 40
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| 168 | #define GITS_BF_CTRL_REG_TYPER_VMAPP_MASK UINT64_C(0x0000010000000000)
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| 169 | /** GITS_TYPER: SVPET - Shared VPE table configuration. */
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| 170 | #define GITS_BF_CTRL_REG_TYPER_SVPET_SHIFT 41
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| 171 | #define GITS_BF_CTRL_REG_TYPER_SVPET_MASK UINT64_C(0x0000060000000000)
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| 172 | /** GITS_TYPER: nID - Individual doorbell interrupt support. */
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| 173 | #define GITS_BF_CTRL_REG_TYPER_NID_SHIFT 43
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| 174 | #define GITS_BF_CTRL_REG_TYPER_NID_MASK UINT64_C(0x0000080000000000)
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| 175 | /** GITS_TYPER: UMSI - Support for reporting receipts of unmapped MSI. */
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| 176 | #define GITS_BF_CTRL_REG_TYPER_UMSI_SHIFT 44
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| 177 | #define GITS_BF_CTRL_REG_TYPER_UMSI_MASK UINT64_C(0x0000100000000000)
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| 178 | /** GITS_TYPER: UMSIirq - Support for generating interrupt on receiving unmapped MSI. */
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| 179 | #define GITS_BF_CTRL_REG_TYPER_UMSI_IRQ_SHIFT 45
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| 180 | #define GITS_BF_CTRL_REG_TYPER_UMSI_IRQ_MASK UINT64_C(0x0000200000000000)
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| 181 | /** GITS_TYPER: INV - Invalidate ITS cache on disable. */
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| 182 | #define GITS_BF_CTRL_REG_TYPER_INV_SHIFT 46
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| 183 | #define GITS_BF_CTRL_REG_TYPER_INV_MASK UINT64_C(0x0000400000000000)
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| 184 | /** GITS_TYPER: Reserved (bits 63:47). */
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| 185 | #define GITS_BF_CTRL_REG_TYPER_RSVD_63_47_SHIFT 47
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| 186 | #define GITS_BF_CTRL_REG_TYPER_RSVD_63_47_MASK UINT64_C(0xffff800000000000)
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| 187 | RT_BF_ASSERT_COMPILE_CHECKS(GITS_BF_CTRL_REG_TYPER_, UINT64_C(0), UINT64_MAX,
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| 188 | (PHYSICAL, VIRTUAL, CCT, IM_DE, ITT_ENTRY_SIZE, ID_BITS, DEV_BITS, SEIS, PTA, RSVD_23_20, HCC,
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| 189 | CID_BITS, CIL, VMOVP, MPAM, VSGI, VMAPP, SVPET, NID, UMSI, UMSI_IRQ, INV, RSVD_63_47));
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| 190 |
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| 191 | /** GITS_MPAMIDR: Memory partitioning ID sizes. */
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| 192 | #define GITS_CTRL_REG_MPAMIDR_OFF 0x0010
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| 193 | /** GITS_MPAMIDR: PARTIDmax - Maximum PARTID value supported. */
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| 194 | #define GITS_BF_CTRL_REG_MPAMIDR_PARTID_MAX_SHIFT 0
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| 195 | #define GITS_BF_CTRL_REG_MPAMIDR_PARTID_MAX_MASK UINT32_C(0x0000ffff)
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| 196 | /** GITS_MPAMIDR: PMGmax - Maximum PMG value supported. */
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| 197 | #define GITS_BF_CTRL_REG_MPAMIDR_PMG_MAX_SHIFT 16
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| 198 | #define GITS_BF_CTRL_REG_MPAMIDR_PMG_MAX_MASK UINT32_C(0x00ff0000)
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| 199 | /** GITS_MPAMIDR: Reserved (bits 24:31). */
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| 200 | #define GITS_BF_CTRL_REG_MPAMIDR_RSVD_31_24_SHIFT 24
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| 201 | #define GITS_BF_CTRL_REG_MPAMIDR_RSVD_31_24_MASK UINT32_C(0xff000000)
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| 202 | RT_BF_ASSERT_COMPILE_CHECKS(GITS_BF_CTRL_REG_MPAMIDR_, UINT32_C(0), UINT32_MAX, (PARTID_MAX, PMG_MAX, RSVD_31_24));
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| 203 |
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| 204 | /** GITS_PARTID: PARTID and PMG values register. */
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| 205 | #define GITS_CTRL_REG_PARTIDR_OFF 0x0014
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| 206 | /** GITS_PARTID: PARTID - PARTID when ITS accesses memory. */
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| 207 | #define GITS_BF_CTRL_REG_PARTIDR_PARTID_SHIFT 0
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| 208 | #define GITS_BF_CTRL_REG_PARTIDR_PARTID_MASK UINT32_C(0x0000ffff)
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| 209 | /** GITS_PARTID: PMG - PMG value when ITS accesses memory. */
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| 210 | #define GITS_BF_CTRL_REG_PARTIDR_PMG_SHIFT 16
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| 211 | #define GITS_BF_CTRL_REG_PARTIDR_PMG_MASK UINT32_C(0x00ff0000)
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| 212 | /** GITS_PARTID: Reserved (bits 24:31). */
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| 213 | #define GITS_BF_CTRL_REG_PARTIDR_RSVD_31_24_SHIFT 24
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| 214 | #define GITS_BF_CTRL_REG_PARTIDR_RSVD_31_24_MASK UINT32_C(0xff000000)
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| 215 | RT_BF_ASSERT_COMPILE_CHECKS(GITS_BF_CTRL_REG_PARTIDR_, UINT32_C(0), UINT32_MAX, (PARTID, PMG, RSVD_31_24));
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| 216 |
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| 217 | #define GITS_CTRL_REG_MPIDR_OFF 0x0018
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| 218 | #define GITS_CTRL_REG_STATUSR_OFF 0x0040
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| 219 | #define GITS_CTRL_REG_UMSIR_OFF 0x0048
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| 220 |
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| 221 | /** GITS_CBASER: ITS command queue base register - RW. */
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| 222 | #define GITS_CTRL_REG_CBASER_OFF 0x0080
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| 223 | #define GITS_BF_CTRL_REG_CBASER_SIZE_SHIFT 0
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| 224 | #define GITS_BF_CTRL_REG_CBASER_SIZE_MASK UINT64_C(0x00000000000000ff)
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| 225 | #define GITS_BF_CTRL_REG_CBASER_RSVD_9_8_SHIFT 8
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| 226 | #define GITS_BF_CTRL_REG_CBASER_RSVD_9_8_MASK UINT64_C(0x0000000000000300)
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| 227 | #define GITS_BF_CTRL_REG_CBASER_SHAREABILITY_SHIFT 10
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| 228 | #define GITS_BF_CTRL_REG_CBASER_SHAREABILITY_MASK UINT64_C(0x0000000000000c00)
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| 229 | #define GITS_BF_CTRL_REG_CBASER_PHYS_ADDR_SHIFT 12
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| 230 | #define GITS_BF_CTRL_REG_CBASER_PHYS_ADDR_MASK UINT64_C(0x000ffffffffff000)
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| 231 | #define GITS_BF_CTRL_REG_CBASER_RSVD_52_SHIFT 52
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| 232 | #define GITS_BF_CTRL_REG_CBASER_RSVD_52_MASK UINT64_C(0x0010000000000000)
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| 233 | #define GITS_BF_CTRL_REG_CBASER_OUTER_CACHE_SHIFT 53
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| 234 | #define GITS_BF_CTRL_REG_CBASER_OUTER_CACHE_MASK UINT64_C(0x00e0000000000000)
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| 235 | #define GITS_BF_CTRL_REG_CBASER_RSVD_58_56_SHIFT 56
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| 236 | #define GITS_BF_CTRL_REG_CBASER_RSVD_58_56_MASK UINT64_C(0x0700000000000000)
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| 237 | #define GITS_BF_CTRL_REG_CBASER_INNER_CACHE_SHIFT 59
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| 238 | #define GITS_BF_CTRL_REG_CBASER_INNER_CACHE_MASK UINT64_C(0x3800000000000000)
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| 239 | #define GITS_BF_CTRL_REG_CBASER_RSVD_62_SHIFT 62
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| 240 | #define GITS_BF_CTRL_REG_CBASER_RSVD_62_MASK UINT64_C(0x4000000000000000)
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| 241 | #define GITS_BF_CTRL_REG_CBASER_VALID_SHIFT 63
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| 242 | #define GITS_BF_CTRL_REG_CBASER_VALID_MASK UINT64_C(0x8000000000000000)
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| 243 | RT_BF_ASSERT_COMPILE_CHECKS(GITS_BF_CTRL_REG_CBASER_, UINT64_C(0), UINT64_MAX,
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| 244 | (SIZE, RSVD_9_8, SHAREABILITY, PHYS_ADDR, RSVD_52, OUTER_CACHE, RSVD_58_56, INNER_CACHE, RSVD_62,
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| 245 | VALID));
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| 246 | /** GITS_CBASER: Physical address bits [15:12] are reserved MBZ. */
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| 247 | #define GITS_CTRL_REG_CBASER_PHYS_ADDR_RSVD_15_12_MASK UINT64_C(0x000000000000f000)
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| 248 | /** GITS_CBASER: Mask of valid read-write bits. */
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| 249 | #define GITS_CTRL_REG_CBASER_RW_MASK (UINT64_MAX & ~(GITS_BF_CTRL_REG_CBASER_RSVD_9_8_MASK | \
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| 250 | GITS_BF_CTRL_REG_CBASER_RSVD_52_MASK | \
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| 251 | GITS_BF_CTRL_REG_CBASER_RSVD_58_56_MASK | \
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| 252 | GITS_BF_CTRL_REG_CBASER_RSVD_62_MASK | \
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| 253 | GITS_CTRL_REG_CBASER_PHYS_ADDR_RSVD_15_12_MASK))
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| 254 |
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| 255 | /** GITS_CWRITER: ITS command queue write register - RW. */
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| 256 | #define GITS_CTRL_REG_CWRITER_OFF 0x0088
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| 257 | #define GITS_BF_CTRL_REG_CWRITER_RETRY_SHIFT 0
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| 258 | #define GITS_BF_CTRL_REG_CWRITER_RETRY_MASK UINT64_C(0x0000000000000001)
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| 259 | #define GITS_BF_CTRL_REG_CWRITER_RSVD_4_1_SHIFT 1
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| 260 | #define GITS_BF_CTRL_REG_CWRITER_RSVD_4_1_MASK UINT64_C(0x000000000000001e)
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| 261 | #define GITS_BF_CTRL_REG_CWRITER_OFFSET_SHIFT 5
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| 262 | #define GITS_BF_CTRL_REG_CWRITER_OFFSET_MASK UINT64_C(0x00000000000fffe0)
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| 263 | #define GITS_BF_CTRL_REG_CWRITER_RSVD_63_20_SHIFT 20
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| 264 | #define GITS_BF_CTRL_REG_CWRITER_RSVD_63_20_MASK UINT64_C(0xfffffffffff00000)
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| 265 | RT_BF_ASSERT_COMPILE_CHECKS(GITS_BF_CTRL_REG_CWRITER_, UINT64_C(0), UINT64_MAX,
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| 266 | (RETRY, RSVD_4_1, OFFSET, RSVD_63_20));
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| 267 | #define GITS_CTRL_REG_CWRITER_RW_MASK (UINT64_MAX & ~(GITS_BF_CTRL_REG_CWRITER_RSVD_4_1_MASK | \
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| 268 | GITS_BF_CTRL_REG_CWRITER_RSVD_63_20_MASK))
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| 269 |
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| 270 | /** GITS_CREADR: Command read register - RO. */
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| 271 | #define GITS_CTRL_REG_CREADR_OFF 0x0090
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| 272 | #define GITS_BF_CTRL_REG_CREADR_STALLED_SHIFT 0
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| 273 | #define GITS_BF_CTRL_REG_CREADR_STALLED_MASK UINT64_C(0x0000000000000001)
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| 274 | #define GITS_BF_CTRL_REG_CREADR_RSVD_4_1_SHIFT 1
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| 275 | #define GITS_BF_CTRL_REG_CREADR_RSVD_4_1_MASK UINT64_C(0x000000000000001e)
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| 276 | #define GITS_BF_CTRL_REG_CREADR_OFFSET_SHIFT 5
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| 277 | #define GITS_BF_CTRL_REG_CREADR_OFFSET_MASK UINT64_C(0x00000000000fffe0)
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| 278 | #define GITS_BF_CTRL_REG_CREADR_RSVD_63_20_SHIFT 20
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| 279 | #define GITS_BF_CTRL_REG_CREADR_RSVD_63_20_MASK UINT64_C(0xfffffffffff00000)
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| 280 | RT_BF_ASSERT_COMPILE_CHECKS(GITS_BF_CTRL_REG_CREADR_, UINT64_C(0), UINT64_MAX,
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| 281 | (STALLED, RSVD_4_1, OFFSET, RSVD_63_20));
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| 282 |
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| 283 | /** GITS_BASER: ITS Table Descriptors - RW. */
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| 284 | #define GITS_CTRL_REG_BASER_OFF_FIRST 0x0100
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| 285 | #define GITS_CTRL_REG_BASER_OFF_LAST 0x0138
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| 286 | #define GITS_CTRL_REG_BASER_RANGE_SIZE (GITS_CTRL_REG_BASER_OFF_LAST + sizeof(uint64_t) - GITS_CTRL_REG_BASER_OFF_FIRST)
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| 287 | /** GITS_BASER: Size - Number of pages allocated to the table minus one. */
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| 288 | #define GITS_BF_CTRL_REG_BASER_SIZE_SHIFT 0
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| 289 | #define GITS_BF_CTRL_REG_BASER_SIZE_MASK UINT64_C(0x00000000000000ff)
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| 290 | /** GITS_BASER: Page_Size - Size of the page that the table uses. */
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| 291 | #define GITS_BF_CTRL_REG_BASER_PAGESIZE_SHIFT 8
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| 292 | #define GITS_BF_CTRL_REG_BASER_PAGESIZE_MASK UINT64_C(0x0000000000000300)
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| 293 | /** GITS_BASER: Shareability attributes of the table. */
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| 294 | #define GITS_BF_CTRL_REG_BASER_SHAREABILITY_SHIFT 10
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| 295 | #define GITS_BF_CTRL_REG_BASER_SHAREABILITY_MASK UINT64_C(0x0000000000000c00)
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| 296 | /** GITS_BASER: Physical_Address - Physical address of the table. */
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| 297 | #define GITS_BF_CTRL_REG_BASER_PHYS_ADDR_SHIFT 12
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| 298 | #define GITS_BF_CTRL_REG_BASER_PHYS_ADDR_MASK UINT64_C(0x0000fffffffff000)
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| 299 | /** GITS_BASER: Entry_Size - Size of each table entry minus one in bytes. */
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| 300 | #define GITS_BF_CTRL_REG_BASER_ENTRY_SIZE_SHIFT 48
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| 301 | #define GITS_BF_CTRL_REG_BASER_ENTRY_SIZE_MASK UINT64_C(0x001f000000000000)
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| 302 | /** GITS_BASER: OuterCache - Outer cacheability attributes of the table. */
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| 303 | #define GITS_BF_CTRL_REG_BASER_OUTER_CACHE_SHIFT 53
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| 304 | #define GITS_BF_CTRL_REG_BASER_OUTER_CACHE_MASK UINT64_C(0x00e0000000000000)
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| 305 | /** GITS_BASER: Type - The type of entity. */
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| 306 | #define GITS_BF_CTRL_REG_BASER_TYPE_SHIFT 56
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| 307 | #define GITS_BF_CTRL_REG_BASER_TYPE_MASK UINT64_C(0x0700000000000000)
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| 308 | /** GITS_BASER: InnerCache - Inner cacheability attribtues of the table. */
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| 309 | #define GITS_BF_CTRL_REG_BASER_INNER_CACHE_SHIFT 59
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| 310 | #define GITS_BF_CTRL_REG_BASER_INNER_CACHE_MASK UINT64_C(0x3800000000000000)
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| 311 | /** GITS_BASER: Indirect - Whether this is a single or two-level table. */
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| 312 | #define GITS_BF_CTRL_REG_BASER_INDIRECT_SHIFT 62
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| 313 | #define GITS_BF_CTRL_REG_BASER_INDIRECT_MASK UINT64_C(0x4000000000000000)
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| 314 | /** GITS_BASER: Valid - Whether memory has been allocated for the table. */
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| 315 | #define GITS_BF_CTRL_REG_BASER_VALID_SHIFT 63
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| 316 | #define GITS_BF_CTRL_REG_BASER_VALID_MASK UINT64_C(0x8000000000000000)
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| 317 | /* Sigh C macros... "PAGE_SIZE" is already defined here, just use "PAGESIZE" instead of temporarily undef, redef. */
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| 318 | RT_BF_ASSERT_COMPILE_CHECKS(GITS_BF_CTRL_REG_BASER_, UINT64_C(0), UINT64_MAX,
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| 319 | (SIZE, PAGESIZE, SHAREABILITY, PHYS_ADDR, ENTRY_SIZE, OUTER_CACHE, TYPE, INNER_CACHE, INDIRECT,
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| 320 | VALID));
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| 321 |
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| 322 | /** GITS_PIDR2: ITS Peripheral ID2 register - RO. */
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| 323 | #define GITS_CTRL_REG_PIDR2_OFF 0xffe8
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| 324 | /** GITS_PIDR2: JEDEC - JEP code. */
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| 325 | #define GITS_BF_CTRL_REG_PIDR2_JEDEC_SHIFT 0
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| 326 | #define GITS_BF_CTRL_REG_PIDR2_JEDEC_MASK UINT32_C(0x00000007)
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| 327 | /** GITS_PIDR2: DES_1 - JEP106 identification code (bits 6:4). */
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| 328 | #define GITS_BF_CTRL_REG_PIDR2_DES_1_SHIFT 3
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| 329 | #define GITS_BF_CTRL_REG_PIDR2_DES_1_MASK UINT32_C(0x00000008)
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| 330 | /** GITS_PIDR2: Architecture revision . */
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| 331 | #define GITS_BF_CTRL_REG_PIDR2_ARCHREV_SHIFT 4
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| 332 | #define GITS_BF_CTRL_REG_PIDR2_ARCHREV_MASK UINT32_C(0x000000f0)
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| 333 | /** GITS_PIDR2: Reserved (bits 31:8). */
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| 334 | #define GITS_BF_CTRL_REG_PIDR2_RSVD_31_8_SHIFT 8
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| 335 | #define GITS_BF_CTRL_REG_PIDR2_RSVD_31_8_MASK UINT32_C(0xffffff00)
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| 336 | RT_BF_ASSERT_COMPILE_CHECKS(GITS_BF_CTRL_REG_PIDR2_, UINT32_C(0), UINT32_MAX,
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| 337 | (JEDEC, DES_1, ARCHREV, RSVD_31_8));
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| 338 |
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| 339 | /** GITS_PIDR2: GICv1 architecture revision. */
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| 340 | #define GITS_CTRL_REG_PIDR2_ARCHREV_GICV1 0x1
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| 341 | /** GITS_PIDR2: GICv2 architecture revision. */
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| 342 | #define GITS_CTRL_REG_PIDR2_ARCHREV_GICV2 0x2
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| 343 | /** GITS_PIDR2: GICv3 architecture revision. */
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| 344 | #define GITS_CTRL_REG_PIDR2_ARCHREV_GICV3 0x3
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| 345 | /** GITS_PIDR2: GICv4 architecture revision. */
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| 346 | #define GITS_CTRL_REG_PIDR2_ARCHREV_GICV4 0x4
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| 347 |
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| 348 | /** GITS_TRANSLATER register. */
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| 349 | #define GITS_TRANSLATION_REG_TRANSLATER 0x0040
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| 350 |
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| 351 | /** GITS Two-level (indirect) table entry. */
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| 352 | #define GITS_BF_ITE_LVL2_RSVD_11_0_SHIFT 0
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| 353 | #define GITS_BF_ITE_LVL2_RSVD_11_0_MASK UINT64_C(0x0000000000000fff)
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| 354 | #define GITS_BF_ITE_LVL2_PHYS_ADDR_SHIFT 12
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| 355 | #define GITS_BF_ITE_LVL2_PHYS_ADDR_MASK UINT64_C(0x000ffffffffff000)
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| 356 | #define GITS_BF_ITE_LVL2_RSVD_62_52_SHIFT 52
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| 357 | #define GITS_BF_ITE_LVL2_RSVD_62_52_MASK UINT64_C(0x7ff0000000000000)
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| 358 | #define GITS_BF_ITE_LVL2_VALID_SHIFT 63
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| 359 | #define GITS_BF_ITE_LVL2_VALID_MASK UINT64_C(0x8000000000000000)
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| 360 | RT_BF_ASSERT_COMPILE_CHECKS(GITS_BF_ITE_LVL2_, UINT64_C(0), UINT64_MAX,
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| 361 | (RSVD_11_0, PHYS_ADDR, RSVD_62_52, VALID));
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| 362 |
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| 363 | /**
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| 364 | * Memory shareability attributes.
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| 365 | * In accordance to the ARM GIC spec.
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| 366 | */
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| 367 | typedef enum GITSATTRSHARE
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| 368 | {
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| 369 | GITSATTRSHARE_NON_SHAREABLE = 0,
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| 370 | GITSATTRSHARE_INNER_SHAREABLE,
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| 371 | GITSATTRSHARE_OUTER_SHAREABLE,
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| 372 | GITSATTRSHARE_RSVD
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| 373 | } GITSATTRSHARE;
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| 374 |
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| 375 | /**
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| 376 | * Memory cacheability attribute.
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| 377 | * In accordance to the ARM GIC spec.
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| 378 | */
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| 379 | typedef enum GITSATTRMEM
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| 380 | {
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| 381 | GITSATTRMEM_DEFAULT = 0,
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| 382 | GITSATTRMEM_NOCACHE,
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| 383 | GITSATTRMEM_CACHE_RD_ALLOC_WT,
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| 384 | GITSATTRMEM_CACHE_RD_ALLOC_WB,
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| 385 | GITSATTRMEM_CACHE_WR_ALLOC_WT,
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| 386 | GITSATTRMEM_CACHE_WR_ALLOC_WB,
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| 387 | GITSATTRMEM_CACHE_RW_ALLOC_WT,
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| 388 | GITSATTRMEM_CACHE_RW_ALLOC_WB
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| 389 | } GITSMEMATTR;
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| 390 |
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| 391 | /**
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| 392 | * GITS entry type.
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| 393 | * In accordance to the ARM GIC spec.
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| 394 | */
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| 395 | typedef enum GITSITSTYPE
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| 396 | {
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| 397 | GITSITSTYPE_UNIMPLEMENTED = 0,
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| 398 | GITSITSTYPE_DEVICES,
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| 399 | GITSITSTYPE_VPES,
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| 400 | GITSITSTYPE_INTR_COLLECTIONS
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| 401 | } GITSITSTYPE;
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| 402 |
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| 403 | /**
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| 404 | * ITS command.
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|---|
| 405 | * In accordance to the ARM GIC spec.
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| 406 | */
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| 407 | typedef union GITSCMD
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| 408 | {
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| 409 | RTUINT64U au64[4];
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| 410 | struct
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|---|
| 411 | {
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|---|
| 412 | uint8_t uCmdId;
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| 413 | uint8_t auData[31];
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| 414 | } common;
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| 415 | } GITSCMD;
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| 416 | /** Pointer to an ITS command. */
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| 417 | typedef GITSCMD *PGITSCMD;
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| 418 | /** Pointer to a const ITS command. */
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| 419 | typedef GITSCMD const *PCGITSCMD;
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| 420 | AssertCompileSize(GITSCMD, GITS_CMD_SIZE);
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| 421 |
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| 422 | /** @name GITS command IDs.
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|---|
| 423 | * @{ */
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| 424 | #define GITS_CMD_ID_CLEAR 0x04
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| 425 | #define GITS_CMD_ID_DISCARD 0x0f
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| 426 | #define GITS_CMD_ID_INT 0x03
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| 427 | #define GITS_CMD_ID_INV 0x0c
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| 428 | #define GITS_CMD_ID_INVALL 0x0d
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| 429 | #define GITS_CMD_ID_INVDB 0x2e
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| 430 | #define GITS_CMD_ID_MAPC 0x09
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| 431 | #define GITS_CMD_ID_MAPD 0x08
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| 432 | #define GITS_CMD_ID_MAPI 0x0b
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| 433 | #define GITS_CMD_ID_MAPTI 0x0a
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| 434 | #define GITS_CMD_ID_MOVALL 0x0e
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| 435 | #define GITS_CMD_ID_MOVI 0x01
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| 436 | #define GITS_CMD_ID_SYNC 0x05
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| 437 | #define GITS_CMD_ID_VINVALL 0x2d
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| 438 | #define GITS_CMD_ID_VMAPI 0x2b
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| 439 | #define GITS_CMD_ID_VMAPP 0x29
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| 440 | #define GITS_CMD_ID_VMAPTI 0x2a
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| 441 | #define GITS_CMD_ID_VMOVI 0x21
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| 442 | #define GITS_CMD_ID_VMOVP 0x22
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| 443 | #define GITS_CMD_ID_VSGI 0x23
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| 444 | #define GITS_CMD_ID_VSYNC 0x25
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| 445 | /** @} */
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| 446 |
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| 447 | /** @name GITS command: MAPC.
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|---|
| 448 | * @{ */
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|---|
| 449 | /** MAPC DW0: Command Id. */
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| 450 | #define GITS_BF_CMD_MAPC_DW0_CMD_ID_SHIFT 0
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| 451 | #define GITS_BF_CMD_MAPC_DW0_CMD_ID_MASK UINT64_C(0x00000000000000ff)
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| 452 | /** MAPC DW0: Reserved (bits 63:8). */
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| 453 | #define GITS_BF_CMD_MAPC_DW0_RSVD_63_8_SHIFT 8
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|---|
| 454 | #define GITS_BF_CMD_MAPC_DW0_RSVD_63_8_MASK UINT64_C(0xffffffffffffff00)
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| 455 | RT_BF_ASSERT_COMPILE_CHECKS(GITS_BF_CMD_MAPC_DW0_, UINT64_C(0), UINT64_MAX,
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|---|
| 456 | (CMD_ID, RSVD_63_8));
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| 457 |
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| 458 | /** MAPC DW1: Reserved (bits 63:0). */
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|---|
| 459 | #define GITS_BF_CMD_MAPC_DW1_RSVD_63_0_MASK UINT64_MAX
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|---|
| 460 |
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| 461 | /** MAPC DW2: IC ID - The interrupt collection ID. */
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|---|
| 462 | #define GITS_BF_CMD_MAPC_DW2_IC_ID_SHIFT 0
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|---|
| 463 | #define GITS_BF_CMD_MAPC_DW2_IC_ID_MASK UINT64_C(0x000000000000ffff)
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| 464 | /** MAPC DW2: RDBase - The target redistributor base address or PE number. */
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|---|
| 465 | #define GITS_BF_CMD_MAPC_DW2_RDBASE_SHIFT 16
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|---|
| 466 | #define GITS_BF_CMD_MAPC_DW2_RDBASE_MASK UINT64_C(0x0007ffffffff0000)
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|---|
| 467 | /** MAPC DW2: Reserved (bits 62:51). */
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|---|
| 468 | #define GITS_BF_CMD_MAPC_DW2_RSVD_62_51_SHIFT 51
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|---|
| 469 | #define GITS_BF_CMD_MAPC_DW2_RSVD_62_51_MASK UINT64_C(0x7ff8000000000000)
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|---|
| 470 | /** MAPC DW2: Valid bit. */
|
|---|
| 471 | #define GITS_BF_CMD_MAPC_DW2_VALID_SHIFT 63
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|---|
| 472 | #define GITS_BF_CMD_MAPC_DW2_VALID_MASK UINT64_C(0x8000000000000000)
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|---|
| 473 | RT_BF_ASSERT_COMPILE_CHECKS(GITS_BF_CMD_MAPC_DW2_, UINT64_C(0), UINT64_MAX,
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|---|
| 474 | (IC_ID, RDBASE, RSVD_62_51, VALID));
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|---|
| 475 | /** @} */
|
|---|
| 476 |
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|---|
| 477 | #endif /* !VBOX_INCLUDED_gic_its_h */
|
|---|
| 478 |
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