VirtualBox

source: vbox/trunk/include/VBox/gic-its.h@ 108919

Last change on this file since 108919 was 108919, checked in by vboxsync, 11 days ago

VMM/GIC: bugref:10877 gic-its.h -- missing file during previous commit.

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1/** @file
2 * ARMv8 GIC Interrupt Translation Service (ITS) definitions.
3 */
4
5/*
6 * Copyright (C) 2025 Oracle and/or its affiliates.
7 *
8 * This file is part of VirtualBox base platform packages, as
9 * available from https://www.virtualbox.org.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * as published by the Free Software Foundation, in version 3 of the
14 * License.
15 *
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, see <https://www.gnu.org/licenses>.
23 *
24 * The contents of this file may alternatively be used under the terms
25 * of the Common Development and Distribution License Version 1.0
26 * (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
27 * in the VirtualBox distribution, in which case the provisions of the
28 * CDDL are applicable instead of those of the GPL.
29 *
30 * You may elect to license modified versions of this file under the
31 * terms and conditions of either the GPL or the CDDL or both.
32 *
33 * SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
34 */
35
36#ifndef VBOX_INCLUDED_gic_its_h
37#define VBOX_INCLUDED_gic_its_h
38#ifndef RT_WITHOUT_PRAGMA_ONCE
39# pragma once
40#endif
41
42#include <iprt/types.h>
43#include <iprt/assertcompile.h>
44
45/** Size of the ITS register frame. */
46#define GITS_REG_FRAME_SIZE _64K
47
48/** The GITS command queue page size. */
49#define GITS_CMD_QUEUE_PAGE_SIZE 0x1000
50/** The GITS command queue page offset mask. */
51#define GITS_CMD_QUEUE_PAGE_OFFSET_MASK 0xfff
52/** The guest page shift (x86). */
53#define GITS_CMD_QUEUE_PAGE_SHIFT 12
54
55/** The GITS command size in bytes. */
56#define GITS_CMD_SIZE 32
57
58/** GITS_CTLR: Control register - RW. */
59#define GITS_CTRL_REG_CTLR_OFF 0x0000
60/** GITS_CTLR: Enabled. */
61#define GITS_BF_CTRL_REG_CTLR_ENABLED_SHIFT 0
62#define GITS_BF_CTRL_REG_CTLR_ENABLED_MASK UINT32_C(0x00000001)
63/** GITS_CTLR: ImDe - Implementation Defined. */
64#define GITS_BF_CTRL_REG_CTLR_IM_DE_SHIFT 1
65#define GITS_BF_CTRL_REG_CTLR_IM_DE_MASK UINT32_C(0x00000002)
66/** GITS_CTLR: Reserved (bits 3:2). */
67#define GITS_BF_CTRL_REG_CTLR_RSVD_3_2_SHIFT 2
68#define GITS_BF_CTRL_REG_CTLR_RSVD_3_2_MASK UINT32_C(0x0000000c)
69/** GITS_CTLR: ITS_Number (0 for GICv3). */
70#define GITS_BF_CTRL_REG_CTLR_ITS_NUMBER_SHIFT 4
71#define GITS_BF_CTRL_REG_CTLR_ITS_NUMBER_MASK UINT32_C(0x000000f0)
72/** GITS_CTLR: UMSIirq - Unmapped MSI reporting interrupt enable. */
73#define GITS_BF_CTRL_REG_CTLR_UMSI_IRQ_SHIFT 8
74#define GITS_BF_CTRL_REG_CTLR_UMSI_IRQ_MASK UINT32_C(0x00000100)
75/** GITS_CTLR: Reserved (bits 30:9). */
76#define GITS_BF_CTRL_REG_CTLR_RSVD_30_9_SHIFT 9
77#define GITS_BF_CTRL_REG_CTLR_RSVD_30_9_MASK UINT32_C(0x7ffffe00)
78/** GITS_CTLR: Quiescent. */
79#define GITS_BF_CTRL_REG_CTLR_QUIESCENT_SHIFT 31
80#define GITS_BF_CTRL_REG_CTLR_QUIESCENT_MASK UINT32_C(0x80000000)
81RT_BF_ASSERT_COMPILE_CHECKS(GITS_BF_CTRL_REG_CTLR_, UINT32_C(0), UINT32_MAX,
82 (ENABLED, IM_DE, RSVD_3_2, ITS_NUMBER, UMSI_IRQ, RSVD_30_9, QUIESCENT));
83/** GITS_CTLR: Mask of valid read-write bits. */
84#define GITS_BF_CTRL_REG_CTLR_RW_MASK (UINT32_MAX & ~( GITS_BF_CTRL_REG_CTLR_IM_DE_MASK \
85 | GITS_BF_CTRL_REG_CTLR_RSVD_3_2_MASK \
86 | GITS_BF_CTRL_REG_CTLR_ITS_NUMBER_MASK \
87 | GITS_BF_CTRL_REG_CTLR_RSVD_30_9_MASK))
88
89/** GITS_IIDR: Implementer and revision register - RO. */
90#define GITS_CTRL_REG_IIDR_OFF 0x0004
91/** GITS_IIDR: Implementer - JEP106 identification code. */
92#define GITS_BF_CTRL_REG_IIDR_IMPL_ID_CODE_SHIFT 0
93#define GITS_BF_CTRL_REG_IIDR_IMPL_ID_CODE_MASK UINT32_C(0x0000007f)
94/** GITS_IIDR: Implementer - Reserved (bit 7). */
95#define GITS_BF_CTRL_REG_IIDR_IMPL_ZERO_7_SHIFT 7
96#define GITS_BF_CTRL_REG_IIDR_IMPL_ZERO_7_MASK UINT32_C(0x00000080)
97/** GITS_IIDR: Implementer - JEP106 continuation code. */
98#define GITS_BF_CTRL_REG_IIDR_IMPL_CONT_CODE_SHIFT 8
99#define GITS_BF_CTRL_REG_IIDR_IMPL_CONT_CODE_MASK UINT32_C(0x00000f00)
100/** GITS_IIDR: Revision. */
101#define GITS_BF_CTRL_REG_IIDR_REVISION_SHIFT 12
102#define GITS_BF_CTRL_REG_IIDR_REVISION_MASK UINT32_C(0x0000f000)
103/** GITS_IIDR: Variant. */
104#define GITS_BF_CTRL_REG_IIDR_VARIANT_SHIFT 16
105#define GITS_BF_CTRL_REG_IIDR_VARIANT_MASK UINT32_C(0x000f0000)
106/** GITS_IIDR: Reserved (bits 23:20). */
107#define GITS_BF_CTRL_REG_IIDR_RSVD_23_20_SHIFT 20
108#define GITS_BF_CTRL_REG_IIDR_RSVD_23_20_MASK UINT32_C(0x00f00000)
109/** GITS_IIDR: Product ID. */
110#define GITS_BF_CTRL_REG_IIDR_PRODUCT_ID_SHIFT 24
111#define GITS_BF_CTRL_REG_IIDR_PRODUCT_ID_MASK UINT32_C(0xff000000)
112RT_BF_ASSERT_COMPILE_CHECKS(GITS_BF_CTRL_REG_IIDR_, UINT32_C(0), UINT32_MAX,
113 (IMPL_ID_CODE, IMPL_ZERO_7, IMPL_CONT_CODE, REVISION, VARIANT, RSVD_23_20, PRODUCT_ID));
114
115/** GITS_TYPER: Feature register - RO. */
116#define GITS_CTRL_REG_TYPER_OFF 0x0008
117/** GITS_TYPER: Physical - Physical LPI support. */
118#define GITS_BF_CTRL_REG_TYPER_PHYSICAL_SHIFT 0
119#define GITS_BF_CTRL_REG_TYPER_PHYSICAL_MASK UINT64_C(0x0000000000000001)
120/** GITS_TYPER: Virtual - Virtual LPI support. */
121#define GITS_BF_CTRL_REG_TYPER_VIRTUAL_SHIFT 1
122#define GITS_BF_CTRL_REG_TYPER_VIRTUAL_MASK UINT64_C(0x0000000000000002)
123/** GITS_TYPER: CCT - Cumulative Collections Table. */
124#define GITS_BF_CTRL_REG_TYPER_CCT_SHIFT 2
125#define GITS_BF_CTRL_REG_TYPER_CCT_MASK UINT64_C(0x0000000000000004)
126/** GITS_TYPER: Implementation Defined. */
127#define GITS_BF_CTRL_REG_TYPER_IM_DE_SHIFT 3
128#define GITS_BF_CTRL_REG_TYPER_IM_DE_MASK UINT64_C(0x0000000000000008)
129/** GITS_TYPER: ITT_entry_size - Size of translation table entry. */
130#define GITS_BF_CTRL_REG_TYPER_ITT_ENTRY_SIZE_SHIFT 4
131#define GITS_BF_CTRL_REG_TYPER_ITT_ENTRY_SIZE_MASK UINT64_C(0x00000000000000f0)
132/** GITS_TYPER: ID_bits - Number of event ID bits implemented (minus one). */
133#define GITS_BF_CTRL_REG_TYPER_ID_BITS_SHIFT 8
134#define GITS_BF_CTRL_REG_TYPER_ID_BITS_MASK UINT64_C(0x0000000000001f00)
135/** GITS_TYPER: Devbits - Number of device ID bits implemented (minus one). */
136#define GITS_BF_CTRL_REG_TYPER_DEV_BITS_SHIFT 13
137#define GITS_BF_CTRL_REG_TYPER_DEV_BITS_MASK UINT64_C(0x000000000003e000)
138/** GITS_TYPER: SEIS - SEI support for virtual CPUs. */
139#define GITS_BF_CTRL_REG_TYPER_SEIS_SHIFT 18
140#define GITS_BF_CTRL_REG_TYPER_SEIS_MASK UINT64_C(0x0000000000040000)
141/** GITS_TYPER: PTA - Physical target address format. */
142#define GITS_BF_CTRL_REG_TYPER_PTA_SHIFT 19
143#define GITS_BF_CTRL_REG_TYPER_PTA_MASK UINT64_C(0x0000000000080000)
144/** GITS_TYPER: Reserved (bits 23:20). */
145#define GITS_BF_CTRL_REG_TYPER_RSVD_23_20_SHIFT 20
146#define GITS_BF_CTRL_REG_TYPER_RSVD_23_20_MASK UINT64_C(0x0000000000f00000)
147/** GITS_TYPER: HCC - Hardware collection count. */
148#define GITS_BF_CTRL_REG_TYPER_HCC_SHIFT 24
149#define GITS_BF_CTRL_REG_TYPER_HCC_MASK UINT64_C(0x00000000ff000000)
150/** GITS_TYPER: CIDbits - Number of collection ID bits (minus one). */
151#define GITS_BF_CTRL_REG_TYPER_CID_BITS_SHIFT 32
152#define GITS_BF_CTRL_REG_TYPER_CID_BITS_MASK UINT64_C(0x0000000f00000000)
153/** GITS_TYPER: CIL - Collection ID limit. */
154#define GITS_BF_CTRL_REG_TYPER_CIL_SHIFT 36
155#define GITS_BF_CTRL_REG_TYPER_CIL_MASK UINT64_C(0x0000001000000000)
156/** GITS_TYPER: VMOVP - Form of VMOVP command. */
157#define GITS_BF_CTRL_REG_TYPER_VMOVP_SHIFT 37
158#define GITS_BF_CTRL_REG_TYPER_VMOVP_MASK UINT64_C(0x0000002000000000)
159/** GITS_TYPER: MPAM - Memory partitioning and monitoring support. */
160#define GITS_BF_CTRL_REG_TYPER_MPAM_SHIFT 38
161#define GITS_BF_CTRL_REG_TYPER_MPAM_MASK UINT64_C(0x0000004000000000)
162/** GITS_TYPER: VSGI - Direct injection of virtual SGI support. */
163#define GITS_BF_CTRL_REG_TYPER_VSGI_SHIFT 39
164#define GITS_BF_CTRL_REG_TYPER_VSGI_MASK UINT64_C(0x0000008000000000)
165/** GITS_TYPER: VMAPP - VMAPP command support. */
166#define GITS_BF_CTRL_REG_TYPER_VMAPP_SHIFT 40
167#define GITS_BF_CTRL_REG_TYPER_VMAPP_MASK UINT64_C(0x0000010000000000)
168/** GITS_TYPER: SVPET - Shared VPE table configuration. */
169#define GITS_BF_CTRL_REG_TYPER_SVPET_SHIFT 41
170#define GITS_BF_CTRL_REG_TYPER_SVPET_MASK UINT64_C(0x0000060000000000)
171/** GITS_TYPER: nID - Individual doorbell interrupt support. */
172#define GITS_BF_CTRL_REG_TYPER_NID_SHIFT 43
173#define GITS_BF_CTRL_REG_TYPER_NID_MASK UINT64_C(0x0000080000000000)
174/** GITS_TYPER: UMSI - Support for reporting receipts of unmapped MSI. */
175#define GITS_BF_CTRL_REG_TYPER_UMSI_SHIFT 44
176#define GITS_BF_CTRL_REG_TYPER_UMSI_MASK UINT64_C(0x0000100000000000)
177/** GITS_TYPER: UMSIirq - Support for generating interrupt on receiving unmapped MSI. */
178#define GITS_BF_CTRL_REG_TYPER_UMSI_IRQ_SHIFT 45
179#define GITS_BF_CTRL_REG_TYPER_UMSI_IRQ_MASK UINT64_C(0x0000200000000000)
180/** GITS_TYPER: INV - Invalidate ITS cache on disable. */
181#define GITS_BF_CTRL_REG_TYPER_INV_SHIFT 46
182#define GITS_BF_CTRL_REG_TYPER_INV_MASK UINT64_C(0x0000400000000000)
183/** GITS_TYPER: Reserved (bits 63:47). */
184#define GITS_BF_CTRL_REG_TYPER_RSVD_63_47_SHIFT 47
185#define GITS_BF_CTRL_REG_TYPER_RSVD_63_47_MASK UINT64_C(0xffff800000000000)
186RT_BF_ASSERT_COMPILE_CHECKS(GITS_BF_CTRL_REG_TYPER_, UINT64_C(0), UINT64_MAX,
187 (PHYSICAL, VIRTUAL, CCT, IM_DE, ITT_ENTRY_SIZE, ID_BITS, DEV_BITS, SEIS, PTA, RSVD_23_20, HCC,
188 CID_BITS, CIL, VMOVP, MPAM, VSGI, VMAPP, SVPET, NID, UMSI, UMSI_IRQ, INV, RSVD_63_47));
189
190/** GITS_MPAMIDR: Memory partitioning ID sizes. */
191#define GITS_CTRL_REG_MPAMIDR_OFF 0x0010
192/** GITS_MPAMIDR: PARTIDmax - Maximum PARTID value supported. */
193#define GITS_BF_CTRL_REG_MPAMIDR_PARTID_MAX_SHIFT 0
194#define GITS_BF_CTRL_REG_MPAMIDR_PARTID_MAX_MASK UINT32_C(0x0000ffff)
195/** GITS_MPAMIDR: PMGmax - Maximum PMG value supported. */
196#define GITS_BF_CTRL_REG_MPAMIDR_PMG_MAX_SHIFT 16
197#define GITS_BF_CTRL_REG_MPAMIDR_PMG_MAX_MASK UINT32_C(0x00ff0000)
198/** GITS_MPAMIDR: Reserved (bits 24:31). */
199#define GITS_BF_CTRL_REG_MPAMIDR_RSVD_31_24_SHIFT 24
200#define GITS_BF_CTRL_REG_MPAMIDR_RSVD_31_24_MASK UINT32_C(0xff000000)
201RT_BF_ASSERT_COMPILE_CHECKS(GITS_BF_CTRL_REG_MPAMIDR_, UINT32_C(0), UINT32_MAX, (PARTID_MAX, PMG_MAX, RSVD_31_24));
202
203/** GITS_PARTID: PARTID and PMG values register. */
204#define GITS_CTRL_REG_PARTIDR_OFF 0x0014
205/** GITS_PARTID: PARTID - PARTID when ITS accesses memory. */
206#define GITS_BF_CTRL_REG_PARTIDR_PARTID_SHIFT 0
207#define GITS_BF_CTRL_REG_PARTIDR_PARTID_MASK UINT32_C(0x0000ffff)
208/** GITS_PARTID: PMG - PMG value when ITS accesses memory. */
209#define GITS_BF_CTRL_REG_PARTIDR_PMG_SHIFT 16
210#define GITS_BF_CTRL_REG_PARTIDR_PMG_MASK UINT32_C(0x00ff0000)
211/** GITS_PARTID: Reserved (bits 24:31). */
212#define GITS_BF_CTRL_REG_PARTIDR_RSVD_31_24_SHIFT 24
213#define GITS_BF_CTRL_REG_PARTIDR_RSVD_31_24_MASK UINT32_C(0xff000000)
214RT_BF_ASSERT_COMPILE_CHECKS(GITS_BF_CTRL_REG_PARTIDR_, UINT32_C(0), UINT32_MAX, (PARTID, PMG, RSVD_31_24));
215
216#define GITS_CTRL_REG_MPIDR_OFF 0x0018
217#define GITS_CTRL_REG_STATUSR_OFF 0x0040
218#define GITS_CTRL_REG_UMSIR_OFF 0x0048
219
220/** GITS_CBASER: ITS command queue base register - RW. */
221#define GITS_CTRL_REG_CBASER_OFF 0x0080
222#define GITS_BF_CTRL_REG_CBASER_SIZE_SHIFT 0
223#define GITS_BF_CTRL_REG_CBASER_SIZE_MASK UINT64_C(0x00000000000000ff)
224#define GITS_BF_CTRL_REG_CBASER_RSVD_9_8_SHIFT 8
225#define GITS_BF_CTRL_REG_CBASER_RSVD_9_8_MASK UINT64_C(0x0000000000000300)
226#define GITS_BF_CTRL_REG_CBASER_SHAREABILITY_SHIFT 10
227#define GITS_BF_CTRL_REG_CBASER_SHAREABILITY_MASK UINT64_C(0x0000000000000c00)
228#define GITS_BF_CTRL_REG_CBASER_PHYS_ADDR_SHIFT 12
229#define GITS_BF_CTRL_REG_CBASER_PHYS_ADDR_MASK UINT64_C(0x000ffffffffff000)
230#define GITS_BF_CTRL_REG_CBASER_RSVD_52_SHIFT 52
231#define GITS_BF_CTRL_REG_CBASER_RSVD_52_MASK UINT64_C(0x0010000000000000)
232#define GITS_BF_CTRL_REG_CBASER_OUTER_CACHE_SHIFT 53
233#define GITS_BF_CTRL_REG_CBASER_OUTER_CACHE_MASK UINT64_C(0x00e0000000000000)
234#define GITS_BF_CTRL_REG_CBASER_RSVD_58_56_SHIFT 56
235#define GITS_BF_CTRL_REG_CBASER_RSVD_58_56_MASK UINT64_C(0x0700000000000000)
236#define GITS_BF_CTRL_REG_CBASER_INNER_CACHE_SHIFT 59
237#define GITS_BF_CTRL_REG_CBASER_INNER_CACHE_MASK UINT64_C(0x3800000000000000)
238#define GITS_BF_CTRL_REG_CBASER_RSVD_62_SHIFT 62
239#define GITS_BF_CTRL_REG_CBASER_RSVD_62_MASK UINT64_C(0x4000000000000000)
240#define GITS_BF_CTRL_REG_CBASER_VALID_SHIFT 63
241#define GITS_BF_CTRL_REG_CBASER_VALID_MASK UINT64_C(0x8000000000000000)
242RT_BF_ASSERT_COMPILE_CHECKS(GITS_BF_CTRL_REG_CBASER_, UINT64_C(0), UINT64_MAX,
243 (SIZE, RSVD_9_8, SHAREABILITY, PHYS_ADDR, RSVD_52, OUTER_CACHE, RSVD_58_56, INNER_CACHE, RSVD_62,
244 VALID));
245/** GITS_CBASER: Physical address bits [15:12] are reserved MBZ. */
246#define GITS_CTRL_REG_CBASER_PHYS_ADDR_RSVD_15_12_MASK UINT64_C(0x000000000000f000)
247/** GITS_CBASER: Mask of valid read-write bits. */
248#define GITS_CTRL_REG_CBASER_RW_MASK (UINT64_MAX & ~(GITS_BF_CTRL_REG_CBASER_RSVD_9_8_MASK | \
249 GITS_BF_CTRL_REG_CBASER_RSVD_52_MASK | \
250 GITS_BF_CTRL_REG_CBASER_RSVD_58_56_MASK | \
251 GITS_BF_CTRL_REG_CBASER_RSVD_62_MASK | \
252 GITS_CTRL_REG_CBASER_PHYS_ADDR_RSVD_15_12_MASK))
253
254/** GITS_CWRITER: ITS command queue write register - RW. */
255#define GITS_CTRL_REG_CWRITER_OFF 0x0088
256#define GITS_BF_CTRL_REG_CWRITER_RETRY_SHIFT 0
257#define GITS_BF_CTRL_REG_CWRITER_RETRY_MASK UINT64_C(0x0000000000000001)
258#define GITS_BF_CTRL_REG_CWRITER_RSVD_4_1_SHIFT 1
259#define GITS_BF_CTRL_REG_CWRITER_RSVD_4_1_MASK UINT64_C(0x000000000000001e)
260#define GITS_BF_CTRL_REG_CWRITER_OFFSET_SHIFT 5
261#define GITS_BF_CTRL_REG_CWRITER_OFFSET_MASK UINT64_C(0x00000000000fffe0)
262#define GITS_BF_CTRL_REG_CWRITER_RSVD_63_20_SHIFT 20
263#define GITS_BF_CTRL_REG_CWRITER_RSVD_63_20_MASK UINT64_C(0xfffffffffff00000)
264RT_BF_ASSERT_COMPILE_CHECKS(GITS_BF_CTRL_REG_CWRITER_, UINT64_C(0), UINT64_MAX,
265 (RETRY, RSVD_4_1, OFFSET, RSVD_63_20));
266#define GITS_CTRL_REG_CWRITER_RW_MASK (UINT64_MAX & ~(GITS_BF_CTRL_REG_CWRITER_RSVD_4_1_MASK | \
267 GITS_BF_CTRL_REG_CWRITER_RSVD_63_20_MASK))
268
269/** GITS_CREADR: Command read register - RO. */
270#define GITS_CTRL_REG_CREADR_OFF 0x0090
271#define GITS_BF_CTRL_REG_CREADR_STALLED_SHIFT 0
272#define GITS_BF_CTRL_REG_CREADR_STALLED_MASK UINT64_C(0x0000000000000001)
273#define GITS_BF_CTRL_REG_CREADR_RSVD_4_1_SHIFT 1
274#define GITS_BF_CTRL_REG_CREADR_RSVD_4_1_MASK UINT64_C(0x000000000000001e)
275#define GITS_BF_CTRL_REG_CREADR_OFFSET_SHIFT 5
276#define GITS_BF_CTRL_REG_CREADR_OFFSET_MASK UINT64_C(0x00000000000fffe0)
277#define GITS_BF_CTRL_REG_CREADR_RSVD_63_20_SHIFT 20
278#define GITS_BF_CTRL_REG_CREADR_RSVD_63_20_MASK UINT64_C(0xfffffffffff00000)
279RT_BF_ASSERT_COMPILE_CHECKS(GITS_BF_CTRL_REG_CREADR_, UINT64_C(0), UINT64_MAX,
280 (STALLED, RSVD_4_1, OFFSET, RSVD_63_20));
281
282/** GITS_BASER: ITS Table Descriptors - RW. */
283#define GITS_CTRL_REG_BASER_OFF_FIRST 0x0100
284#define GITS_CTRL_REG_BASER_OFF_LAST 0x0138
285#define GITS_CTRL_REG_BASER_RANGE_SIZE (GITS_CTRL_REG_BASER_OFF_LAST + sizeof(uint64_t) - GITS_CTRL_REG_BASER_OFF_FIRST)
286/** GITS_BASER: Size - Number of pages allocated to the table minus one. */
287#define GITS_BF_CTRL_REG_BASER_SIZE_SHIFT 0
288#define GITS_BF_CTRL_REG_BASER_SIZE_MASK UINT64_C(0x00000000000000ff)
289/** GITS_BASER: Page_Size - Size of the page that the table uses. */
290#define GITS_BF_CTRL_REG_BASER_PAGESIZE_SHIFT 8
291#define GITS_BF_CTRL_REG_BASER_PAGESIZE_MASK UINT64_C(0x0000000000000300)
292/** GITS_BASER: Shareability attributes of the table. */
293#define GITS_BF_CTRL_REG_BASER_SHAREABILITY_SHIFT 10
294#define GITS_BF_CTRL_REG_BASER_SHAREABILITY_MASK UINT64_C(0x0000000000000c00)
295/** GITS_BASER: Physical_Address - Physical address of the table. */
296#define GITS_BF_CTRL_REG_BASER_PHYS_ADDR_SHIFT 12
297#define GITS_BF_CTRL_REG_BASER_PHYS_ADDR_MASK UINT64_C(0x0000fffffffff000)
298/** GITS_BASER: Entry_Size - Size of each table entry minus one in bytes. */
299#define GITS_BF_CTRL_REG_BASER_ENTRY_SIZE_SHIFT 48
300#define GITS_BF_CTRL_REG_BASER_ENTRY_SIZE_MASK UINT64_C(0x001f000000000000)
301/** GITS_BASER: OuterCache - Outer cacheability attributes of the table. */
302#define GITS_BF_CTRL_REG_BASER_OUTER_CACHE_SHIFT 53
303#define GITS_BF_CTRL_REG_BASER_OUTER_CACHE_MASK UINT64_C(0x00e0000000000000)
304/** GITS_BASER: Type - The type of entity. */
305#define GITS_BF_CTRL_REG_BASER_TYPE_SHIFT 56
306#define GITS_BF_CTRL_REG_BASER_TYPE_MASK UINT64_C(0x0700000000000000)
307/** GITS_BASER: InnerCache - Inner cacheability attribtues of the table. */
308#define GITS_BF_CTRL_REG_BASER_INNER_CACHE_SHIFT 59
309#define GITS_BF_CTRL_REG_BASER_INNER_CACHE_MASK UINT64_C(0x3800000000000000)
310/** GITS_BASER: Indirect - Whether this is a single or two-level table. */
311#define GITS_BF_CTRL_REG_BASER_INDIRECT_SHIFT 62
312#define GITS_BF_CTRL_REG_BASER_INDIRECT_MASK UINT64_C(0x4000000000000000)
313/** GITS_BASER: Valid - Whether memory has been allocated for the table. */
314#define GITS_BF_CTRL_REG_BASER_VALID_SHIFT 63
315#define GITS_BF_CTRL_REG_BASER_VALID_MASK UINT64_C(0x8000000000000000)
316/* Sigh C macros... "PAGE_SIZE" is already defined here, just use "PAGESIZE" instead of temporarily undef, redef. */
317RT_BF_ASSERT_COMPILE_CHECKS(GITS_BF_CTRL_REG_BASER_, UINT64_C(0), UINT64_MAX,
318 (SIZE, PAGESIZE, SHAREABILITY, PHYS_ADDR, ENTRY_SIZE, OUTER_CACHE, TYPE, INNER_CACHE, INDIRECT,
319 VALID));
320/** GITS_BASER: Mask of valid read-write bits. */
321#define GITS_CTRL_REG_BASER_RW_MASK (UINT64_MAX & ~( GITS_BF_CTRL_REG_BASER_ENTRY_SIZE_MASK \
322 | GITS_BF_CTRL_REG_BASER_TYPE_MASK))
323
324/** GITS_BASER: Table type - Unimplemented (not a table). */
325#define GITS_BASER_TYPE_UNIMPL 0
326/** GITS_BASER: Table type - Devices. */
327#define GITS_BASER_TYPE_DEVICES 1
328/** GITS_BASER: Table type - vPE. */
329#define GITS_BASER_TYPE_VPES 2
330/** GITS_BASER: Table type - Interrupt Collections. */
331#define GITS_BASER_TYPE_INTR_COLLECTION 3
332
333/** GITS_PIDR2: ITS Peripheral ID2 register - RO. */
334#define GITS_CTRL_REG_PIDR2_OFF 0xffe8
335/** GITS_PIDR2: JEDEC - JEP code. */
336#define GITS_BF_CTRL_REG_PIDR2_JEDEC_SHIFT 0
337#define GITS_BF_CTRL_REG_PIDR2_JEDEC_MASK UINT32_C(0x00000007)
338/** GITS_PIDR2: DES_1 - JEP106 identification code (bits 6:4). */
339#define GITS_BF_CTRL_REG_PIDR2_DES_1_SHIFT 3
340#define GITS_BF_CTRL_REG_PIDR2_DES_1_MASK UINT32_C(0x00000008)
341/** GITS_PIDR2: Architecture revision . */
342#define GITS_BF_CTRL_REG_PIDR2_ARCHREV_SHIFT 4
343#define GITS_BF_CTRL_REG_PIDR2_ARCHREV_MASK UINT32_C(0x000000f0)
344/** GITS_PIDR2: Reserved (bits 31:8). */
345#define GITS_BF_CTRL_REG_PIDR2_RSVD_31_8_SHIFT 8
346#define GITS_BF_CTRL_REG_PIDR2_RSVD_31_8_MASK UINT32_C(0xffffff00)
347RT_BF_ASSERT_COMPILE_CHECKS(GITS_BF_CTRL_REG_PIDR2_, UINT32_C(0), UINT32_MAX,
348 (JEDEC, DES_1, ARCHREV, RSVD_31_8));
349
350/** GITS_PIDR2: GICv1 architecture revision. */
351#define GITS_CTRL_REG_PIDR2_ARCHREV_GICV1 0x1
352/** GITS_PIDR2: GICv2 architecture revision. */
353#define GITS_CTRL_REG_PIDR2_ARCHREV_GICV2 0x2
354/** GITS_PIDR2: GICv3 architecture revision. */
355#define GITS_CTRL_REG_PIDR2_ARCHREV_GICV3 0x3
356/** GITS_PIDR2: GICv4 architecture revision. */
357#define GITS_CTRL_REG_PIDR2_ARCHREV_GICV4 0x4
358
359/** GITS_TRANSLATER register. */
360#define GITS_TRANSLATION_REG_TRANSLATER 0x0040
361
362/** GITS Two-level (indirect) table entry. */
363#define GITS_BF_ITE_LVL2_RSVD_11_0_SHIFT 0
364#define GITS_BF_ITE_LVL2_RSVD_11_0_MASK UINT64_C(0x0000000000000fff)
365#define GITS_BF_ITE_LVL2_PHYS_ADDR_SHIFT 12
366#define GITS_BF_ITE_LVL2_PHYS_ADDR_MASK UINT64_C(0x000ffffffffff000)
367#define GITS_BF_ITE_LVL2_RSVD_62_52_SHIFT 52
368#define GITS_BF_ITE_LVL2_RSVD_62_52_MASK UINT64_C(0x7ff0000000000000)
369#define GITS_BF_ITE_LVL2_VALID_SHIFT 63
370#define GITS_BF_ITE_LVL2_VALID_MASK UINT64_C(0x8000000000000000)
371RT_BF_ASSERT_COMPILE_CHECKS(GITS_BF_ITE_LVL2_, UINT64_C(0), UINT64_MAX,
372 (RSVD_11_0, PHYS_ADDR, RSVD_62_52, VALID));
373
374/**
375 * Memory shareability attributes.
376 * In accordance to the ARM GIC spec.
377 */
378typedef enum GITSATTRSHARE
379{
380 GITSATTRSHARE_NON_SHAREABLE = 0,
381 GITSATTRSHARE_INNER_SHAREABLE,
382 GITSATTRSHARE_OUTER_SHAREABLE,
383 GITSATTRSHARE_RSVD
384} GITSATTRSHARE;
385
386/**
387 * Memory cacheability attribute.
388 * In accordance to the ARM GIC spec.
389 */
390typedef enum GITSATTRMEM
391{
392 GITSATTRMEM_DEFAULT = 0,
393 GITSATTRMEM_NOCACHE,
394 GITSATTRMEM_CACHE_RD_ALLOC_WT,
395 GITSATTRMEM_CACHE_RD_ALLOC_WB,
396 GITSATTRMEM_CACHE_WR_ALLOC_WT,
397 GITSATTRMEM_CACHE_WR_ALLOC_WB,
398 GITSATTRMEM_CACHE_RW_ALLOC_WT,
399 GITSATTRMEM_CACHE_RW_ALLOC_WB
400} GITSMEMATTR;
401
402/**
403 * GITS entry type.
404 * In accordance to the ARM GIC spec.
405 */
406typedef enum GITSITSTYPE
407{
408 GITSITSTYPE_UNIMPLEMENTED = 0,
409 GITSITSTYPE_DEVICES,
410 GITSITSTYPE_VPES,
411 GITSITSTYPE_INTR_COLLECTIONS
412} GITSITSTYPE;
413
414/**
415 * ITS command.
416 * In accordance to the ARM GIC spec.
417 */
418typedef union GITSCMD
419{
420 RTUINT64U au64[4];
421 struct
422 {
423 uint8_t uCmdId;
424 uint8_t auData[31];
425 } common;
426} GITSCMD;
427/** Pointer to an ITS command. */
428typedef GITSCMD *PGITSCMD;
429/** Pointer to a const ITS command. */
430typedef GITSCMD const *PCGITSCMD;
431AssertCompileSize(GITSCMD, GITS_CMD_SIZE);
432
433/** @name GITS command IDs.
434 * @{ */
435#define GITS_CMD_ID_CLEAR 0x04
436#define GITS_CMD_ID_DISCARD 0x0f
437#define GITS_CMD_ID_INT 0x03
438#define GITS_CMD_ID_INV 0x0c
439#define GITS_CMD_ID_INVALL 0x0d
440#define GITS_CMD_ID_INVDB 0x2e
441#define GITS_CMD_ID_MAPC 0x09
442#define GITS_CMD_ID_MAPD 0x08
443#define GITS_CMD_ID_MAPI 0x0b
444#define GITS_CMD_ID_MAPTI 0x0a
445#define GITS_CMD_ID_MOVALL 0x0e
446#define GITS_CMD_ID_MOVI 0x01
447#define GITS_CMD_ID_SYNC 0x05
448#define GITS_CMD_ID_VINVALL 0x2d
449#define GITS_CMD_ID_VMAPI 0x2b
450#define GITS_CMD_ID_VMAPP 0x29
451#define GITS_CMD_ID_VMAPTI 0x2a
452#define GITS_CMD_ID_VMOVI 0x21
453#define GITS_CMD_ID_VMOVP 0x22
454#define GITS_CMD_ID_VSGI 0x23
455#define GITS_CMD_ID_VSYNC 0x25
456/** @} */
457
458/** @name GITS command: MAPC.
459 * @{ */
460/** MAPC DW0: Command Id. */
461#define GITS_BF_CMD_MAPC_DW0_CMD_ID_SHIFT 0
462#define GITS_BF_CMD_MAPC_DW0_CMD_ID_MASK UINT64_C(0x00000000000000ff)
463/** MAPC DW0: Reserved (bits 63:8). */
464#define GITS_BF_CMD_MAPC_DW0_RSVD_63_8_SHIFT 8
465#define GITS_BF_CMD_MAPC_DW0_RSVD_63_8_MASK UINT64_C(0xffffffffffffff00)
466RT_BF_ASSERT_COMPILE_CHECKS(GITS_BF_CMD_MAPC_DW0_, UINT64_C(0), UINT64_MAX,
467 (CMD_ID, RSVD_63_8));
468
469/** MAPC DW1: Reserved (bits 63:0). */
470#define GITS_BF_CMD_MAPC_DW1_RSVD_63_0_MASK UINT64_MAX
471
472/** MAPC DW2: IC ID - The interrupt collection ID. */
473#define GITS_BF_CMD_MAPC_DW2_IC_ID_SHIFT 0
474#define GITS_BF_CMD_MAPC_DW2_IC_ID_MASK UINT64_C(0x000000000000ffff)
475/** MAPC DW2: RDBase - The target redistributor base address or PE number. */
476#define GITS_BF_CMD_MAPC_DW2_RDBASE_SHIFT 16
477#define GITS_BF_CMD_MAPC_DW2_RDBASE_MASK UINT64_C(0x0007ffffffff0000)
478/** MAPC DW2: Reserved (bits 62:51). */
479#define GITS_BF_CMD_MAPC_DW2_RSVD_62_51_SHIFT 51
480#define GITS_BF_CMD_MAPC_DW2_RSVD_62_51_MASK UINT64_C(0x7ff8000000000000)
481/** MAPC DW2: Valid bit. */
482#define GITS_BF_CMD_MAPC_DW2_VALID_SHIFT 63
483#define GITS_BF_CMD_MAPC_DW2_VALID_MASK UINT64_C(0x8000000000000000)
484RT_BF_ASSERT_COMPILE_CHECKS(GITS_BF_CMD_MAPC_DW2_, UINT64_C(0), UINT64_MAX,
485 (IC_ID, RDBASE, RSVD_62_51, VALID));
486/** @} */
487
488#endif /* !VBOX_INCLUDED_gic_its_h */
489
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