gic.h@ 109019

Last change on this file since 109019 was 108997, checked in by vboxsync, 6 days ago
VMM/GIC: bugref:10877 LPI, work-in-progress.
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1	/** @file
2	* ARMv8 Generic Interrupt Controller Architecture (GIC) definitions.
3	*/
4
5	/*
6	* Copyright (C) 2023-2024 Oracle and/or its affiliates.
7	*
8	* This file is part of VirtualBox base platform packages, as
9	* available from https://www.virtualbox.org.
10	*
11	* This program is free software; you can redistribute it and/or
12	* modify it under the terms of the GNU General Public License
13	* as published by the Free Software Foundation, in version 3 of the
14	* License.
15	*
16	* This program is distributed in the hope that it will be useful, but
17	* WITHOUT ANY WARRANTY; without even the implied warranty of
18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19	* General Public License for more details.
20	*
21	* You should have received a copy of the GNU General Public License
22	* along with this program; if not, see <https://www.gnu.org/licenses>.
23	*
24	* The contents of this file may alternatively be used under the terms
25	* of the Common Development and Distribution License Version 1.0
26	* (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
27	* in the VirtualBox distribution, in which case the provisions of the
28	* CDDL are applicable instead of those of the GPL.
29	*
30	* You may elect to license modified versions of this file under the
31	* terms and conditions of either the GPL or the CDDL or both.
32	*
33	* SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
34	*/
35
36	#ifndef VBOX_INCLUDED_gic_h
37	#define VBOX_INCLUDED_gic_h
38	#ifndef RT_WITHOUT_PRAGMA_ONCE
39	# pragma once
40	#endif
41
42	#include <iprt/types.h>
43	#include <iprt/armv8.h>
44
45	/** @name INTIDs - Interrupt identifier ranges.
46	* @{ */
47	/** Start of the SGI (Software Generated Interrupts) range. */
48	#define GIC_INTID_RANGE_SGI_START 0
49	/** Last valid SGI (Software Generated Interrupts) identifier. */
50	#define GIC_INTID_RANGE_SGI_LAST 15
51	/** Number of SGIs. */
52	#define GIC_INTID_SGI_RANGE_SIZE (GIC_INTID_RANGE_SGI_LAST - GIC_INTID_RANGE_SGI_START + 1)
53
54	/** Start of the PPI (Private Peripheral Interrupts) range. */
55	#define GIC_INTID_RANGE_PPI_START 16
56	/** Last valid PPI (Private Peripheral Interrupts) identifier. */
57	#define GIC_INTID_RANGE_PPI_LAST 31
58	/** Number of PPIs. */
59	#define GIC_INTID_PPI_RANGE_SIZE (GIC_INTID_RANGE_PPI_LAST - GIC_INTID_RANGE_PPI_START + 1)
60
61	/** Start of the SPI (Shared Peripheral Interrupts) range. */
62	#define GIC_INTID_RANGE_SPI_START 32
63	/** Last valid SPI (Shared Peripheral Interrupts) identifier. */
64	#define GIC_INTID_RANGE_SPI_LAST 1019
65	/** The size of the SPI range. */
66	#define GIC_INTID_SPI_RANGE_SIZE (GIC_INTID_RANGE_SPI_LAST - GIC_INTID_RANGE_SPI_START + 1)
67
68	/** Start of the special interrupt range. */
69	#define GIC_INTID_RANGE_SPECIAL_START 1020
70	/** Last valid special interrupt identifier. */
71	#define GIC_INTID_RANGE_SPECIAL_LAST 1023
72	/** Value for an interrupt acknowledge if no pending interrupt with sufficient
73	* priority, security state or interrupt group. */
74	# define GIC_INTID_RANGE_SPECIAL_NO_INTERRUPT 1023
75	/** The size of the extended PPI range. */
76	#define GIC_INTID_SPECIAL_RANGE_SIZE (GIC_INTID_RANGE_SPECIAL_NO_INTERRUPT - GIC_INTID_RANGE_SPECIAL_START + 1)
77
78	/** Start of the extended PPI (Private Peripheral Interrupts) range. */
79	#define GIC_INTID_RANGE_EXT_PPI_START 1056
80	/** Last valid extended PPI (Private Peripheral Interrupts) identifier. */
81	#define GIC_INTID_RANGE_EXT_PPI_LAST 1119
82	/** The size of the extended PPI range. */
83	#define GIC_INTID_EXT_PPI_RANGE_SIZE (GIC_INTID_RANGE_EXT_PPI_LAST - GIC_INTID_RANGE_EXT_PPI_START + 1)
84
85	/** Start of the extended SPI (Shared Peripheral Interrupts) range. */
86	#define GIC_INTID_RANGE_EXT_SPI_START 4096
87	/** Last valid extended SPI (Shared Peripheral Interrupts) identifier. */
88	#define GIC_INTID_RANGE_EXT_SPI_LAST 5119
89	/** The size of the extended SPI range. */
90	#define GIC_INTID_EXT_SPI_RANGE_SIZE (GIC_INTID_RANGE_EXT_SPI_LAST - GIC_INTID_RANGE_EXT_SPI_START + 1)
91
92	/** Start of the LPI (Locality-specific Peripheral Interrupts) range. */
93	#define GIC_INTID_RANGE_LPI_START 8192
94	/** @} */
95
96
97	/** @name GICD - GIC Distributor registers.
98	* @{ */
99	/** Size of the distributor register frame. */
100	#define GIC_DIST_REG_FRAME_SIZE _64K
101
102	/** Distributor Control Register - RW. */
103	#define GIC_DIST_REG_CTLR_OFF 0x0000
104	/** Bit 0 - Enable Group 0 interrupts. */
105	# define GIC_DIST_REG_CTRL_ENABLE_GRP0 RT_BIT_32(0)
106	# define GIC_DIST_REG_CTRL_ENABLE_GRP0_BIT 0
107	/** Bit 1 - Enable Non-secure Group 1 interrupts. */
108	# define GIC_DIST_REG_CTRL_ENABLE_GRP1_NS RT_BIT_32(1)
109	# define GIC_DIST_REG_CTRL_ENABLE_GRP1_NS_BIT 1
110	/** Bit 2 - Enable Secure Group 1 interrupts. */
111	# define GIC_DIST_REG_CTRL_ENABLE_GRP1_S RT_BIT_32(2)
112	# define GIC_DIST_REG_CTRL_ENABLE_GRP1_S_BIT 2
113	/** Bit 4 - Affinity Routing Enable, Secure state. */
114	# define GIC_DIST_REG_CTRL_ARE_S RT_BIT_32(4)
115	# define GIC_DIST_REG_CTRL_ARE_S_BIT 4
116	/** Bit 5 - Affinity Routing Enable, Non-secure state. */
117	# define GIC_DIST_REG_CTRL_ARE_NS RT_BIT_32(5)
118	# define GIC_DIST_REG_CTRL_ARE_NS_BIT 5
119	/** Bit 6 - Disable Security. */
120	# define GIC_DIST_REG_CTRL_DS RT_BIT_32(6)
121	# define GIC_DIST_REG_CTRL_DS_BIT 6
122	/** Bit 7 - Enable 1 of N Wakeup Functionality. */
123	# define GIC_DIST_REG_CTRL_E1NWF RT_BIT_32(7)
124	# define GIC_DIST_REG_CTRL_E1NWF_BIT 7
125	/** Bit 31 - Register Write Pending. */
126	# define GIC_DIST_REG_CTRL_RWP RT_BIT_32(31)
127	# define GIC_DIST_REG_CTRL_RWP_BIT 31
128
129	/** Interrupt Controller Type Register - RO. */
130	#define GIC_DIST_REG_TYPER_OFF 0x0004
131	/** Bit 0 - 4 - Maximum number of SPIs supported. */
132	# define GIC_DIST_REG_TYPER_NUM_ITLINES ( RT_BIT_32(0) \| RT_BIT_32(1) \| RT_BIT(2) \
133	\| RT_BIT_32(3) \| RT_BIT_32(4))
134	# define GIC_DIST_REG_TYPER_NUM_ITLINES_SET(a_NumSpis) ((a_NumSpis) & GIC_DIST_REG_TYPER_NUM_ITLINES)
135	/** Bit 5 - 7 - Reports number of PEs that can be used when affinity routing is not enabled, minus 1. */
136	# define GIC_DIST_REG_TYPER_NUM_PES (RT_BIT_32(5) \| RT_BIT_32(6) \| RT_BIT(7))
137	# define GIC_DIST_REG_TYPER_NUM_PES_SET(a_Pes) (((a_Pes) << 5) & GIC_DIST_REG_TYPER_NUM_PES)
138	/** Bit 8 - Extended SPI range implemented. */
139	# define GIC_DIST_REG_TYPER_ESPI RT_BIT_32(8)
140	# define GIC_DIST_REG_TYPER_ESPI_BIT 8
141	/** Bit 9 - Non-maskable interrupt priority supported. */
142	# define GIC_DIST_REG_TYPER_NMI RT_BIT_32(9)
143	# define GIC_DIST_REG_TYPER_NMI_BIT 9
144	/** Bit 10 - Indicates whether the implementation supports two security states. */
145	# define GIC_DIST_REG_TYPER_SECURITY_EXTN RT_BIT_32(10)
146	# define GIC_DIST_REG_TYPER_SECURITY_EXTN_BIT 10
147	/** Bit 11 - 15 - The number of supported LPIs. */
148	# define GIC_DIST_REG_TYPER_NUM_LPIS ( RT_BIT_32(11) \| RT_BIT_32(12) \| RT_BIT(13) \
149	\| RT_BIT_32(14) \| RT_BIT_32(15))
150	# define GIC_DIST_REG_TYPER_NUM_LPIS_SET(a_Lpis) (((a_Lpis) << 11) & GIC_DIST_REG_TYPER_NUM_LPIS)
151	/** Bit 16 - Indicates whether the implementation supports message based interrupts by writing to Distributor registers. */
152	# define GIC_DIST_REG_TYPER_MBIS RT_BIT_32(16)
153	# define GIC_DIST_REG_TYPER_MBIS_BIT 16
154	/** Bit 17 - Indicates whether the implementation supports LPIs. */
155	# define GIC_DIST_REG_TYPER_LPIS RT_BIT_32(17)
156	# define GIC_DIST_REG_TYPER_LPIS_BIT 17
157	/** Bit 18 - Indicates whether the implementation supports Direct Virtual LPI injection (FEAT_GICv4). */
158	# define GIC_DIST_REG_TYPER_DVIS RT_BIT_32(18)
159	# define GIC_DIST_REG_TYPER_DVIS_BIT 18
160	/** Bit 19 - 23 - The number of interrupt identifer bits supported, minus one. */
161	# define GIC_DIST_REG_TYPER_IDBITS ( RT_BIT_32(19) \| RT_BIT_32(20) \| RT_BIT(21) \
162	\| RT_BIT_32(22) \| RT_BIT_32(23))
163	# define GIC_DIST_REG_TYPER_IDBITS_SET(a_Bits) (((a_Bits) << 19) & GIC_DIST_REG_TYPER_IDBITS)
164	/** Bit 24 - Affinity 3 valid. Indicates whether the Distributor supports nonzero values of Affinity level 3. */
165	# define GIC_DIST_REG_TYPER_A3V RT_BIT_32(24)
166	# define GIC_DIST_REG_TYPER_A3V_BIT 24
167	/** Bit 25 - Indicates whether 1 of N SPI interrupts are supported. */
168	# define GIC_DIST_REG_TYPER_NO1N RT_BIT_32(25)
169	# define GIC_DIST_REG_TYPER_NO1N_BIT 25
170	/** Bit 26 - Range Selector Support. */
171	# define GIC_DIST_REG_TYPER_RSS RT_BIT_32(26)
172	# define GIC_DIST_REG_TYPER_RSS_BIT 26
173	/** Bit 27 - 31 - Indicates maximum INTID in the Extended SPI range. */
174	# define GIC_DIST_REG_TYPER_ESPI_RANGE ( RT_BIT_32(27) \| RT_BIT_32(28) \| RT_BIT(29) \
175	\| RT_BIT_32(30) \| RT_BIT_32(31))
176	# define GIC_DIST_REG_TYPER_ESPI_RANGE_BIT 27
177	# define GIC_DIST_REG_TYPER_ESPI_RANGE_SET(a_Range) (((a_Range) << 27) & GIC_DIST_REG_TYPER_ESPI_RANGE)
178
179	/** Distributor Implementer Identification Register - RO. */
180	#define GIC_DIST_REG_IIDR_OFF 0x0008
181	/** Bits 0 - 6 - Implementer ID code. */
182	# define GIC_DIST_REG_IIDR_IMPL_ID UINT32_C(0x0000007f)
183	# define GIC_DIST_REG_IIDR_IMPL_ID_BIT 0
184	/** Bits 0 - 6 - Implementer continuation code. */
185	# define GIC_DIST_REG_IIDR_IMPL_CONT UINT32_C(0x00000f00)
186	# define GIC_DIST_REG_IIDR_IMPL_CONT_BIT 8
187	# define GIC_DIST_REG_IIDR_IMPL_SET(a_Id, a_Cont) ((a_Id) \| \
188	(((a_Cont) << GIC_DIST_REG_IIDR_IMPL_CONT_BIT) & GIC_DIST_REG_IIDR_IMPL_CONT))
189
190	/** Interrupt Controller Type Register 2 - RO. */
191	#define GIC_DIST_REG_TYPER2_OFF 0x000c
192	/** Error Reporting Status Register (optional) - RW. */
193	#define GIC_DIST_REG_STATUSR_OFF 0x0010
194	/** Set SPI Register - WO. */
195	#define GIC_DIST_REG_SETSPI_NSR_OFF 0x0040
196	/** Clear SPI Register - WO. */
197	#define GIC_DIST_REG_CLRSPI_NSR_OFF 0x0048
198	/** Set SPI, Secure Register - WO. */
199	#define GIC_DIST_REG_SETSPI_SR_OFF 0x0050
200	/** Clear SPI, Secure Register - WO. */
201	#define GIC_DIST_REG_CLRSPI_SR_OFF 0x0058
202
203	/** Interrupt Group Registers, start offset - RW. */
204	#define GIC_DIST_REG_IGROUPRn_OFF_START 0x0080
205	/** Interrupt Group Registers, last offset - RW. */
206	#define GIC_DIST_REG_IGROUPRn_OFF_LAST 0x00fc
207	/** Interrupt Group Registers, range in bytes. */
208	#define GIC_DIST_REG_IGROUPRn_RANGE_SIZE (GIC_DIST_REG_IGROUPRn_OFF_LAST + sizeof(uint32_t) - GIC_DIST_REG_IGROUPRn_OFF_START)
209
210	/** Interrupt Set Enable Registers, start offset - RW. */
211	#define GIC_DIST_REG_ISENABLERn_OFF_START 0x0100
212	/** Interrupt Set Enable Registers, last offset - RW. */
213	#define GIC_DIST_REG_ISENABLERn_OFF_LAST 0x017c
214	/** Interrupt Set Enable Registers, range in bytes. */
215	#define GIC_DIST_REG_ISENABLERn_RANGE_SIZE (GIC_DIST_REG_ISENABLERn_OFF_LAST + sizeof(uint32_t) - GIC_DIST_REG_ISENABLERn_OFF_START)
216
217	/** Interrupt Clear Enable Registers, start offset - RW. */
218	#define GIC_DIST_REG_ICENABLERn_OFF_START 0x0180
219	/** Interrupt Clear Enable Registers, last offset - RW. */
220	#define GIC_DIST_REG_ICENABLERn_OFF_LAST 0x01fc
221	/** Interrupt Clear Enable Registers, range in bytes. */
222	#define GIC_DIST_REG_ICENABLERn_RANGE_SIZE (GIC_DIST_REG_ICENABLERn_OFF_LAST + sizeof(uint32_t) - GIC_DIST_REG_ICENABLERn_OFF_START)
223
224	/** Interrupt Set Pending Registers, start offset - RW. */
225	#define GIC_DIST_REG_ISPENDRn_OFF_START 0x0200
226	/** Interrupt Set Pending Registers, last offset - RW. */
227	#define GIC_DIST_REG_ISPENDRn_OFF_LAST 0x027c
228	/** Interrupt Set Pending Registers, range in bytes. */
229	#define GIC_DIST_REG_ISPENDRn_RANGE_SIZE (GIC_DIST_REG_ISPENDRn_OFF_LAST + sizeof(uint32_t) - GIC_DIST_REG_ISPENDRn_OFF_START)
230
231	/** Interrupt Clear Pending Registers, start offset - RW. */
232	#define GIC_DIST_REG_ICPENDRn_OFF_START 0x0280
233	/** Interrupt Clear Pending Registers, last offset - RW. */
234	#define GIC_DIST_REG_ICPENDRn_OFF_LAST 0x02fc
235	/** Interrupt Clear Pending Registers, range in bytes. */
236	#define GIC_DIST_REG_ICPENDRn_RANGE_SIZE (GIC_DIST_REG_ICPENDRn_OFF_LAST + sizeof(uint32_t) - GIC_DIST_REG_ICPENDRn_OFF_START)
237
238	/** Interrupt Set Active Registers, start offset - RW. */
239	#define GIC_DIST_REG_ISACTIVERn_OFF_START 0x0300
240	/** Interrupt Set Active Registers, last offset - RW. */
241	#define GIC_DIST_REG_ISACTIVERn_OFF_LAST 0x037c
242	/** Interrupt Set Active Registers, range in bytes. */
243	#define GIC_DIST_REG_ISACTIVERn_RANGE_SIZE (GIC_DIST_REG_ISACTIVERn_OFF_LAST + sizeof(uint32_t) - GIC_DIST_REG_ISACTIVERn_OFF_START)
244
245	/** Interrupt Clear Active Registers, start offset - RW. */
246	#define GIC_DIST_REG_ICACTIVERn_OFF_START 0x0380
247	/** Interrupt Clear Active Registers, last offset - RW. */
248	#define GIC_DIST_REG_ICACTIVERn_OFF_LAST 0x03fc
249	/** Interrupt Clear Active Registers, range in bytes. */
250	#define GIC_DIST_REG_ICACTIVERn_RANGE_SIZE (GIC_DIST_REG_ICACTIVERn_OFF_LAST + sizeof(uint32_t) - GIC_DIST_REG_ICACTIVERn_OFF_START)
251
252	/** Interrupt Priority Registers, start offset - RW. */
253	#define GIC_DIST_REG_IPRIORITYRn_OFF_START 0x0400
254	/** Interrupt Priority Registers, last offset - RW. */
255	#define GIC_DIST_REG_IPRIORITYRn_OFF_LAST 0x07f8
256	/** Interrupt Priority Registers, range in bytes. */
257	#define GIC_DIST_REG_IPRIORITYRn_RANGE_SIZE (GIC_DIST_REG_IPRIORITYRn_OFF_LAST + sizeof(uint32_t) - GIC_DIST_REG_IPRIORITYRn_OFF_START)
258
259	/** Interrupt Processor Targets Registers, start offset - RO/RW. */
260	#define GIC_DIST_REG_ITARGETSRn_OFF_START 0x0800
261	/** Interrupt Processor Targets Registers, last offset - RO/RW. */
262	#define GIC_DIST_REG_ITARGETSRn_OFF_LAST 0x0bf8
263
264	/** Interrupt Configuration Registers, start offset - RW. */
265	#define GIC_DIST_REG_ICFGRn_OFF_START 0x0c00
266	/** Interrupt Configuration Registers, last offset - RW. */
267	#define GIC_DIST_REG_ICFGRn_OFF_LAST 0x0cfc
268	/** Interrupt Configuration Registers, range in bytes. */
269	#define GIC_DIST_REG_ICFGRn_RANGE_SIZE (GIC_DIST_REG_ICFGRn_OFF_LAST + sizeof(uint32_t) - GIC_DIST_REG_ICFGRn_OFF_START)
270
271	/** Interrupt Group Modifier Registers, start offset - RW. */
272	#define GIC_DIST_REG_IGRPMODRn_OFF_START 0x0d00
273	/** Interrupt Group Modifier Registers, last offset - RW. */
274	#define GIC_DIST_REG_IGRPMODRn_OFF_LAST 0x0d7c
275
276	/** Non-secure Access Control Registers, start offset - RW. */
277	#define GIC_DIST_REG_NSACRn_OFF_START 0x0e00
278	/** Non-secure Access Control Registers, last offset - RW. */
279	#define GIC_DIST_REG_NSACRn_OFF_LAST 0x0efc
280
281	/** Software Generated Interrupt Register - RW. */
282	#define GIC_DIST_REG_SGIR_OFF 0x0f00
283
284	/** SGI Clear Pending Registers, start offset - RW. */
285	#define GIC_DIST_REG_CPENDSGIRn_OFF_START 0x0f10
286	/** SGI Clear Pending Registers, last offset - RW. */
287	#define GIC_DIST_REG_CPENDSGIRn_OFF_LAST 0x0f1c
288	/** SGI Set Pending Registers, start offset - RW. */
289	#define GIC_DIST_REG_SPENDSGIRn_OFF_START 0x0f20
290	/** SGI Set Pending Registers, last offset - RW. */
291	#define GIC_DIST_REG_SPENDSGIRn_OFF_LAST 0x0f2c
292
293	/** Non-maskable Interrupt Registers, start offset - RW. */
294	#define GIC_DIST_REG_INMIn_OFF_START 0x0f80
295	/** Non-maskable Interrupt Registers, last offset - RW. */
296	#define GIC_DIST_REG_INMIn_OFF_LAST 0x0ffc
297
298	/** Interrupt Group Registers for extended SPI range, start offset - RW. */
299	#define GIC_DIST_REG_IGROUPRnE_OFF_START 0x1000
300	/** Interrupt Group Registers for extended SPI range, last offset - RW. */
301	#define GIC_DIST_REG_IGROUPRnE_OFF_LAST 0x107c
302	/** Interrupt Group Registers for extended SPI range, range in bytes. */
303	#define GIC_DIST_REG_IGROUPRnE_RANGE_SIZE (GIC_DIST_REG_IGROUPRnE_OFF_LAST + sizeof(uint32_t) - GIC_DIST_REG_IGROUPRnE_OFF_START)
304
305	/** Interrupt Set Enable Registers for extended SPI range, start offset - RW. */
306	#define GIC_DIST_REG_ISENABLERnE_OFF_START 0x1200
307	/** Interrupt Set Enable Registers for extended SPI range, last offset - RW. */
308	#define GIC_DIST_REG_ISENABLERnE_OFF_LAST 0x127c
309	/** Interrupt Set Enable Registers for extended SPI range, range in bytes. */
310	#define GIC_DIST_REG_ISENABLERnE_RANGE_SIZE (GIC_DIST_REG_ISENABLERnE_OFF_LAST + sizeof(uint32_t) - GIC_DIST_REG_ISENABLERnE_OFF_START)
311
312	/** Interrupt Clear Enable Registers for extended SPI range, start offset - RW. */
313	#define GIC_DIST_REG_ICENABLERnE_OFF_START 0x1400
314	/** Interrupt Clear Enable Registers for extended SPI range, last offset - RW. */
315	#define GIC_DIST_REG_ICENABLERnE_OFF_LAST 0x147c
316	/** Interrupt Clear Enable Registers for extended SPI range, range in bytes. */
317	#define GIC_DIST_REG_ICENABLERnE_RANGE_SIZE (GIC_DIST_REG_ICENABLERnE_OFF_LAST + sizeof(uint32_t) - GIC_DIST_REG_ICENABLERnE_OFF_START)
318
319	/** Interrupt Set Pending Registers for extended SPI range, start offset - RW. */
320	#define GIC_DIST_REG_ISPENDRnE_OFF_START 0x1600
321	/** Interrupt Set Pending Registers for extended SPI range, last offset - RW. */
322	#define GIC_DIST_REG_ISPENDRnE_OFF_LAST 0x167c
323	/** Interrupt Set Pending Registers for extended SPI range, range in bytes. */
324	#define GIC_DIST_REG_ISPENDRnE_RANGE_SIZE (GIC_DIST_REG_ISPENDRnE_OFF_LAST + sizeof(uint32_t) - GIC_DIST_REG_ISPENDRnE_OFF_START)
325
326	/** Interrupt Clear Pending Registers for extended SPI range, start offset - RW. */
327	#define GIC_DIST_REG_ICPENDRnE_OFF_START 0x1800
328	/** Interrupt Clear Pending Registers for extended SPI range, last offset - RW. */
329	#define GIC_DIST_REG_ICPENDRnE_OFF_LAST 0x187c
330	/** Interrupt Clear Pending Registers for extended SPI range, range in bytes. */
331	#define GIC_DIST_REG_ICPENDRnE_RANGE_SIZE (GIC_DIST_REG_ICPENDRnE_OFF_LAST + sizeof(uint32_t) - GIC_DIST_REG_ICPENDRnE_OFF_START)
332
333	/** Interrupt Set Active Registers for extended SPI range, start offset - RW. */
334	#define GIC_DIST_REG_ISACTIVERnE_OFF_START 0x1a00
335	/** Interrupt Set Active Registers for extended SPI range, last offset - RW. */
336	#define GIC_DIST_REG_ISACTIVERnE_OFF_LAST 0x1a7c
337	/** Interrupt Set Active Registers for extended SPI range, range in bytes. */
338	#define GIC_DIST_REG_ISACTIVERnE_RANGE_SIZE (GIC_DIST_REG_ISACTIVERnE_OFF_LAST + sizeof(uint32_t) - GIC_DIST_REG_ISACTIVERnE_OFF_START)
339
340	/** Interrupt Clear Active Registers for extended SPI range, start offset - RW. */
341	#define GIC_DIST_REG_ICACTIVERnE_OFF_START 0x1c00
342	/** Interrupt Clear Active Registers for extended SPI range, last offset - RW. */
343	#define GIC_DIST_REG_ICACTIVERnE_OFF_LAST 0x1c7c
344	/** Interrupt Clear Active Registers for extended SPI range, range in bytes. */
345	#define GIC_DIST_REG_ICACTIVERnE_RANGE_SIZE (GIC_DIST_REG_ICACTIVERnE_OFF_LAST + sizeof(uint32_t) - GIC_DIST_REG_ICACTIVERnE_OFF_START)
346
347	/** Interrupt Priority Registers for extended SPI range, start offset - RW. */
348	#define GIC_DIST_REG_IPRIORITYRnE_OFF_START 0x2000
349	/** Interrupt Priority Registers for extended SPI range, last offset - RW. */
350	#define GIC_DIST_REG_IPRIORITYRnE_OFF_LAST 0x23fc
351	/** Interrupt Priority Registers for extended SPI range, range in bytes. */
352	#define GIC_DIST_REG_IPRIORITYRnE_RANGE_SIZE (GIC_DIST_REG_IPRIORITYRnE_OFF_LAST + sizeof(uint32_t) - GIC_DIST_REG_IPRIORITYRnE_OFF_START)
353
354	/** Interrupt Configuration Registers for extended SPI range, start offset - RW. */
355	#define GIC_DIST_REG_ICFGRnE_OFF_START 0x3000
356	/** Interrupt Configuration Registers for extended SPI range, last offset - RW. */
357	#define GIC_DIST_REG_ICFGRnE_OFF_LAST 0x30fc
358	/** Interrupt Configuration Registers for extended SPI range, range in bytes. */
359	#define GIC_DIST_REG_ICFGRnE_RANGE_SIZE (GIC_DIST_REG_ICFGRnE_OFF_LAST + sizeof(uint32_t) - GIC_DIST_REG_ICFGRnE_OFF_START)
360
361	/** Interrupt Group Modifier Registers for extended SPI range, start offset - RW. */
362	#define GIC_DIST_REG_IGRPMODRnE_OFF_START 0x3400
363	/** Interrupt Group Modifier Registers for extended SPI range, last offset - RW. */
364	#define GIC_DIST_REG_IGRPMODRnE_OFF_LAST 0x347c
365
366	/** Non-secure Access Control Registers for extended SPI range, start offset - RW. */
367	#define GIC_DIST_REG_NSACRnE_OFF_START 0x3600
368	/** Non-secure Access Control Registers for extended SPI range, last offset - RW. */
369	#define GIC_DIST_REG_NSACRnE_OFF_LAST 0x367c
370
371	/** Non-maskable Interrupt Registers for extended SPIs, start offset - RW. */
372	#define GIC_DIST_REG_INMInE_OFF_START 0x3b00
373	/** Non-maskable Interrupt Registers for extended SPIs, last offset - RW. */
374	#define GIC_DIST_REG_INMInE_OFF_LAST 0x3b7c
375
376	/** Interrupt Routing Registers, start offset - RW. */
377	#define GIC_DIST_REG_IROUTERn_OFF_START 0x6100
378	/** Interrupt Routing Registers, last offset - RW. */
379	#define GIC_DIST_REG_IROUTERn_OFF_LAST 0x7fd8
380	/** Interrupt Routing Registers range in bytes. */
381	#define GIC_DIST_REG_IROUTERn_RANGE_SIZE (GIC_DIST_REG_IROUTERn_OFF_LAST + sizeof(uint64_t) - GIC_DIST_REG_IROUTERn_OFF_START)
382
383	/** Interrupt Routing Registers for extended SPI range, start offset - RW. */
384	#define GIC_DIST_REG_IROUTERnE_OFF_START 0x8000
385	/** Interrupt Routing Registers for extended SPI range, last offset - RW. */
386	#define GIC_DIST_REG_IROUTERnE_OFF_LAST 0x9ffc
387	/** Interrupt Routing Registers for extended SPI range, range in bytes. */
388	#define GIC_DIST_REG_IROUTERnE_RANGE_SIZE (GIC_DIST_REG_IROUTERnE_OFF_LAST + sizeof(uint64_t) - GIC_DIST_REG_IROUTERnE_OFF_START)
389
390	#define GIC_DIST_REG_IROUTERn_IRM_BIT 31
391	#define GIC_DIST_REG_IROUTERn_MASK (RT_BIT_32(GIC_DIST_REG_IROUTERn_IRM_BIT) \| 0xffffff)
392	#define GIC_DIST_REG_IROUTERnE_MASK 0xff
393
394	#define GIC_DIST_REG_IROUTERn_IRM_GET(a_Reg) (((a_Reg) >> GIC_DIST_REG_IROUTERn_IRM_BIT) & 1)
395	#define GIC_DIST_REG_IROUTERn_SET(a_fIrm, a_Reg) ((((a_fIrm) << GIC_DIST_REG_IROUTERn_IRM_BIT) \| (a_Reg)) & GIC_DIST_REG_IROUTERn_MASK)
396
397	/** Distributor Peripheral ID2 Register - RO. */
398	#define GIC_DIST_REG_PIDR2_OFF 0xffe8
399	/** Bit 4 - 7 - GIC architecture revision */
400	# define GIC_DIST_REG_PIDR2_ARCHREV (RT_BIT_32(4) \| RT_BIT_32(5) \| RT_BIT_32(6) \| RT_BIT_32(7))
401	# define GIC_DIST_REG_PIDR2_ARCHREV_SET(a_ArchRev) (((a_ArchRev) << 4) & GIC_DIST_REG_PIDR2_ARCHREV)
402	/** GICv1 architecture revision. */
403	# define GIC_DIST_REG_PIDR2_ARCHREV_GICV1 0x1
404	/** GICv2 architecture revision. */
405	# define GIC_DIST_REG_PIDR2_ARCHREV_GICV2 0x2
406	/** GICv3 architecture revision. */
407	# define GIC_DIST_REG_PIDR2_ARCHREV_GICV3 0x3
408	/** GICv4 architecture revision. */
409	# define GIC_DIST_REG_PIDR2_ARCHREV_GICV4 0x4
410	/** @} */
411
412
413	/** @name GICD - GIC Redistributor registers.
414	* @{ */
415	/** Size of the redistributor register frame. */
416	#define GIC_REDIST_REG_FRAME_SIZE _64K
417
418	/** Redistributor Control Register - RW. */
419	#define GIC_REDIST_REG_CTLR_OFF 0x0000
420	/** Bit 0 - Enable LPIs. */
421	#define GIC_REDIST_REG_CTLR_ENABLE_LPI_BIT 0
422	#define GIC_REDIST_REG_CTLR_ENABLE_LPI RT_BIT_32(0)
423	/** Bit 1 - Clear Enable Support. */
424	#define GIC_REDIST_REG_CTLR_CES_BIT 1
425	#define GIC_REDIST_REG_CTLR_CES RT_BIT_32(1)
426	#define GIC_REDIST_REG_CTLR_CES_SET(a_Ces) (((a_Ces) << GIC_REDIST_REG_CTLR_CES_BIT) & GIC_REDIST_REG_CTLR_CES)
427	/** Bit 2 - LPI invalidate registers supported. */
428	#define GIC_REDIST_REG_CTLR_IR_BIT 2
429	#define GIC_REDIST_REG_CTLR_IR RT_BIT_32(2)
430	/** Bit 3 - Register Write Pending. */
431	#define GIC_REDIST_REG_CTLR_RWP_BIT 3
432	#define GIC_REDIST_REG_CTLR_RWP RT_BIT_32(3)
433	/** Bit 24 - Disable Processor selection for Group 0 interrupt. */
434	#define GIC_REDIST_REG_CTLR_DPG0_BIT 24
435	#define GIC_REDIST_REG_CTLR_DPG0 RT_BIT_32(24)
436	/** Bit 25 - Disable Processor selection for Group 1 non-secure interrupt. */
437	#define GIC_REDIST_REG_CTLR_DPG1NS_BIT 25
438	#define GIC_REDIST_REG_CTLR_DPG1NS RT_BIT_32(25)
439	/** Bit 26 - Disable Processor selection for Group 1 secure interrupt. */
440	#define GIC_REDIST_REG_CTLR_DPG1S_BIT 26
441	#define GIC_REDIST_REG_CTLR_DPG1S RT_BIT_32(26)
442	/** Bit 31 - Upstream Write Pending. */
443	#define GIC_REDIST_REG_CTLR_UWP_BIT 31
444	#define GIC_REDIST_REG_CTLR_UWP RT_BIT_32(31)
445	/** GICR_CTLR: Mask of valid read-write bits. */
446	#define GIC_REDIST_REG_CTLR_RW_MASK ( GIC_REDIST_REG_CTLR_ENABLE_LPI \
447	\| GIC_REDIST_REG_CTLR_DPG0 \
448	\| GIC_REDIST_REG_CTLR_DPG1NS \
449	\| GIC_REDIST_REG_CTLR_DPG1S)
450
451	/** Implementer Identification Register - RO. */
452	#define GIC_REDIST_REG_IIDR_OFF 0x0004
453	/** Bits 0 - 6 - Implementer ID code. */
454	# define GIC_REDIST_REG_IIDR_IMPL_ID GIC_DIST_REG_IIDR_IMPL_ID
455	# define GIC_REDIST_REG_IIDR_IMPL_ID_BIT GIC_DIST_REG_IIDR_IMPL_ID_BIT
456	/** Bits 0 - 6 - Implementer continuation code. */
457	# define GIC_REDIST_REG_IIDR_IMPL_CONT GIC_DIST_REG_IIDR_IMPL_CONT
458	# define GIC_REDIST_REG_IIDR_IMPL_CONT_BIT GIC_DIST_REG_IIDR_IMPL_CONT_BIT
459	# define GIC_REDIST_REG_IIDR_IMPL_SET(a_Id, a_Cont) GIC_DIST_REG_IIDR_IMPL_SET(a_Id, a_Cont)
460
461	/** Redistributor Type Register - RO. */
462	#define GIC_REDIST_REG_TYPER_OFF 0x0008
463	/** Bit 0 - Indicates whether the GIC implementation supports physical LPIs. */
464	# define GIC_REDIST_REG_TYPER_PLPIS RT_BIT_32(0)
465	# define GIC_REDIST_REG_TYPER_PLPIS_BIT 0
466	/** Bit 1 - Indicates whether the GIC implementation supports virtual LPIs and the direct injection of those. */
467	# define GIC_REDIST_REG_TYPER_VLPIS RT_BIT_32(1)
468	# define GIC_REDIST_REG_TYPER_VLPIS_BIT 1
469	/** Bit 2 - Controls the functionality of GICR_VPENDBASER.Dirty. */
470	# define GIC_REDIST_REG_TYPER_DIRTY RT_BIT_32(2)
471	# define GIC_REDIST_REG_TYPER_DIRTY_BIT 2
472	/** Bit 3 - Indicates whether the redistributor supports direct injection of LPIs. */
473	# define GIC_REDIST_REG_TYPER_DIRECT_LPI RT_BIT_32(3)
474	# define GIC_REDIST_REG_TYPER_DIRECT_LPI_BIT 3
475	/** Bit 4 - Indicates whether this redistributor is the highest numbered Redistributor in a series. */
476	# define GIC_REDIST_REG_TYPER_LAST RT_BIT_32(4)
477	# define GIC_REDIST_REG_TYPER_LAST_BIT 4
478	/** Bit 5 - Sets support for GICR_CTLR.DPG* bits. */
479	# define GIC_REDIST_REG_TYPER_DPGS RT_BIT_32(5)
480	# define GIC_REDIST_REG_TYPER_DPGS_BIT 5
481	/** Bit 6 - Indicates whether MPAM is supported. */
482	# define GIC_REDIST_REG_TYPER_MPAM RT_BIT_32(6)
483	# define GIC_REDIST_REG_TYPER_MPAM_BIT 6
484	/** Bit 7 - Indicates how the resident vPE is specified. */
485	# define GIC_REDIST_REG_TYPER_RVPEID RT_BIT_32(7)
486	# define GIC_REDIST_REG_TYPER_RVPEID_BIT 7
487	/** Bit 8 - 23 - A unique identifier for the PE. */
488	# define GIC_REDIST_REG_TYPER_CPU_NUMBER UINT32_C(0x00ffff00)
489	# define GIC_REDIST_REG_TYPER_CPU_NUMBER_SET(a_CpuNum) (((a_CpuNum) << 8) & GIC_REDIST_REG_TYPER_CPU_NUMBER)
490	/** Bit 24 - 25 - The affinity level at Redistributors share an LPI Configuration
491	* table. */
492	# define GIC_REDIST_REG_TYPER_CMN_LPI_AFF (RT_BIT_32(24) \| RT_BIT_32(25))
493	# define GIC_REDIST_REG_TYPER_CMN_LPI_AFF_SET(a_LpiAff) (((a_LpiAff) << 24) & GIC_REDIST_REG_TYPER_CMN_LPI_AFF)
494	/** All Redistributors must share an LPI Configuration table. */
495	# define GIC_REDIST_REG_TYPER_CMN_LPI_AFF_ALL 0
496	/** All Redistributors with the same affinity 3 value must share an LPI Configuration table. */
497	# define GIC_REDIST_REG_TYPER_CMN_LPI_AFF_3 1
498	/** All Redistributors with the same affinity 3.2 value must share an LPI Configuration table. */
499	# define GIC_REDIST_REG_TYPER_CMN_LPI_AFF_3_2 2
500	/** All Redistributors with the same affinity 3.2.1 value must share an LPI Configuration table. */
501	# define GIC_REDIST_REG_TYPER_CMN_LPI_AFF_3_2_1 3
502	/** Bit 26 - Indicates whether vSGIs are supported. */
503	# define GIC_REDIST_REG_TYPER_VSGI RT_BIT_32(26)
504	# define GIC_REDIST_REG_TYPER_VSGI_BIT 26
505	/** Bit 27 - 31 - Indicates the maximum PPI INTID that a GIC implementation can support. */
506	# define GIC_REDIST_REG_TYPER_PPI_NUM ( RT_BIT_32(27) \| RT_BIT_32(28) \| RT_BIT_32(29) \
507	\| RT_BIT_32(30) \| RT_BIT_32(31))
508	# define GIC_REDIST_REG_TYPER_PPI_NUM_SET(a_PpiNum) (((a_PpiNum) << 27) & GIC_REDIST_REG_TYPER_PPI_NUM)
509	/** Maximum PPI INTID is 31. */
510	# define GIC_REDIST_REG_TYPER_PPI_NUM_MAX_31 0
511	/** Maximum PPI INTID is 1087. */
512	# define GIC_REDIST_REG_TYPER_PPI_NUM_MAX_1087 1
513	/** Maximum PPI INTID is 1119. */
514	# define GIC_REDIST_REG_TYPER_PPI_NUM_MAX_1119 2
515	# define GIC_REDIST_REG_TYPER_CPU_NUMBER_MASK (GIC_REDIST_REG_TYPER_CPU_NUMBER >> 8)
516
517	/** Redistributor Type Register (the affinity value of the 64-bit register) - RO. */
518	#define GIC_REDIST_REG_TYPER_AFFINITY_OFF 0x000c
519	/** Bit 0 - 31 - The identity of the PE associated with this Redistributor. */
520	# define GIC_REDIST_REG_TYPER_AFFINITY_VALUE UINT32_C(0xffffffff)
521	# define GIC_REDIST_REG_TYPER_AFFINITY_VALUE_SET(a_Aff) ((a_Aff) & GIC_REDIST_REG_TYPER_AFFINITY_VALUE)
522
523
524	/** Redistributor Error Reporting Status Register (optional) - RW. */
525	#define GIC_REDIST_REG_STATUSR_OFF 0x0010
526	/** Redistributor Wake Register - RW. */
527	#define GIC_REDIST_REG_WAKER_OFF 0x0014
528	/** Redistributor Report maximum PARTID and PMG Register - RO. */
529	#define GIC_REDIST_REG_MPAMIDR_OFF 0x0018
530	/** Redistributor Set PARTID and PMG Register - RW. */
531	#define GIC_REDIST_REG_PARTIDR_OFF 0x001c
532	/** Redistributor Set LPI Pending Register - WO. */
533	#define GIC_REDIST_REG_SETLPIR_OFF 0x0040
534	/** Redistributor Clear LPI Pending Register - WO. */
535	#define GIC_REDIST_REG_CLRLPIR_OFF 0x0048
536
537	/** Redistributor Properties Base Address Register - RW. */
538	#define GIC_REDIST_REG_PROPBASER_OFF 0x0070
539	#define GIC_BF_REDIST_REG_PROPBASER_ID_BITS_SHIFT 0
540	#define GIC_BF_REDIST_REG_PROPBASER_ID_BITS_MASK UINT64_C(0x000000000000001f)
541	#define GIC_BF_REDIST_REG_PROPBASER_RSVD_6_5_SHIFT 5
542	#define GIC_BF_REDIST_REG_PROPBASER_RSVD_6_5_MASK UINT64_C(0x0000000000000060)
543	#define GIC_BF_REDIST_REG_PROPBASER_INNER_CACHE_SHIFT 7
544	#define GIC_BF_REDIST_REG_PROPBASER_INNER_CACHE_MASK UINT64_C(0x0000000000000380)
545	#define GIC_BF_REDIST_REG_PROPBASER_SHAREABILITY_SHIFT 10
546	#define GIC_BF_REDIST_REG_PROPBASER_SHAREABILITY_MASK UINT64_C(0x0000000000000c00)
547	#define GIC_BF_REDIST_REG_PROPBASER_PHYS_ADDR_SHIFT 12
548	#define GIC_BF_REDIST_REG_PROPBASER_PHYS_ADDR_MASK UINT64_C(0x000ffffffffff000)
549	#define GIC_BF_REDIST_REG_PROPBASER_RSVD_55_52_SHIFT 52
550	#define GIC_BF_REDIST_REG_PROPBASER_RSVD_55_52_MASK UINT64_C(0x00f0000000000000)
551	#define GIC_BF_REDIST_REG_PROPBASER_OUTER_CACHE_SHIFT 56
552	#define GIC_BF_REDIST_REG_PROPBASER_OUTER_CACHE_MASK UINT64_C(0x0700000000000000)
553	#define GIC_BF_REDIST_REG_PROPBASER_RSVD_63_59_SHIFT 59
554	#define GIC_BF_REDIST_REG_PROPBASER_RSVD_63_59_MASK UINT64_C(0xf800000000000000)
555	RT_BF_ASSERT_COMPILE_CHECKS(GIC_BF_REDIST_REG_PROPBASER_, UINT64_C(0), UINT64_MAX,
556	(ID_BITS, RSVD_6_5, INNER_CACHE, SHAREABILITY, PHYS_ADDR, RSVD_55_52, OUTER_CACHE, RSVD_63_59));
557	#define GIC_REDIST_REG_PROPBASER_RW_MASK (UINT64_MAX & ~( GIC_BF_REDIST_REG_PROPBASER_RSVD_6_5_MASK \
558	\| GIC_BF_REDIST_REG_PROPBASER_RSVD_55_52_MASK \
559	\| GIC_BF_REDIST_REG_PROPBASER_RSVD_63_59_MASK))
560
561	/** Redistributor LPI Pending Table Base Address Register - RW. */
562	#define GIC_REDIST_REG_PENDBASER_OFF 0x0078
563	#define GIC_BF_REDIST_REG_PENDBASER_RSVD_6_0_SHIFT 0
564	#define GIC_BF_REDIST_REG_PENDBASER_RSVD_6_0_MASK UINT64_C(0x000000000000007f)
565	#define GIC_BF_REDIST_REG_PENDBASER_INNER_CACHE_SHIFT 7
566	#define GIC_BF_REDIST_REG_PENDBASER_INNER_CACHE_MASK UINT64_C(0x0000000000000380)
567	#define GIC_BF_REDIST_REG_PENDBASER_SHAREABILITY_SHIFT 10
568	#define GIC_BF_REDIST_REG_PENDBASER_SHAREABILITY_MASK UINT64_C(0x0000000000000c00)
569	#define GIC_BF_REDIST_REG_PENDBASER_RSVD_15_12_SHIFT 12
570	#define GIC_BF_REDIST_REG_PENDBASER_RSVD_15_12_MASK UINT64_C(0x000000000000f000)
571	#define GIC_BF_REDIST_REG_PENDBASER_PHYS_ADDR_SHIFT 16
572	#define GIC_BF_REDIST_REG_PENDBASER_PHYS_ADDR_MASK UINT64_C(0x000fffffffff0000)
573	#define GIC_BF_REDIST_REG_PENDBASER_RSVD_55_52_SHIFT 52
574	#define GIC_BF_REDIST_REG_PENDBASER_RSVD_55_52_MASK UINT64_C(0x00f0000000000000)
575	#define GIC_BF_REDIST_REG_PENDBASER_OUTER_CACHE_SHIFT 56
576	#define GIC_BF_REDIST_REG_PENDBASER_OUTER_CACHE_MASK UINT64_C(0x0700000000000000)
577	#define GIC_BF_REDIST_REG_PENDBASER_RSVD_61_59_SHIFT 59
578	#define GIC_BF_REDIST_REG_PENDBASER_RSVD_61_59_MASK UINT64_C(0x3800000000000000)
579	#define GIC_BF_REDIST_REG_PENDBASER_PTZ_SHIFT 62
580	#define GIC_BF_REDIST_REG_PENDBASER_PTZ_MASK UINT64_C(0x4000000000000000)
581	#define GIC_BF_REDIST_REG_PENDBASER_RSVD_63_SHIFT 63
582	#define GIC_BF_REDIST_REG_PENDBASER_RSVD_63_MASK UINT64_C(0x8000000000000000)
583	RT_BF_ASSERT_COMPILE_CHECKS(GIC_BF_REDIST_REG_PENDBASER_, UINT64_C(0), UINT64_MAX,
584	(RSVD_6_0, INNER_CACHE, SHAREABILITY, RSVD_15_12, PHYS_ADDR, RSVD_55_52, OUTER_CACHE, RSVD_61_59,
585	PTZ, RSVD_63));
586	#define GIC_REDIST_REG_PENDBASER_RW_MASK (UINT64_MAX & ~( GIC_BF_REDIST_REG_PENDBASER_RSVD_6_0_MASK \
587	\| GIC_BF_REDIST_REG_PENDBASER_RSVD_15_12_MASK \
588	\| GIC_BF_REDIST_REG_PENDBASER_RSVD_55_52_MASK \
589	\| GIC_BF_REDIST_REG_PENDBASER_RSVD_61_59_MASK \
590	\| GIC_BF_REDIST_REG_PENDBASER_RSVD_63_MASK))
591
592	/** Redistributor Invalidate LPI Register - WO. */
593	#define GIC_REDIST_REG_INVLPIR_OFF 0x00a0
594	/** Redistributor Invalidate All Register - WO. */
595	#define GIC_REDIST_REG_INVALLR_OFF 0x00b0
596	/** Redistributor Synchronize Register - RO. */
597	#define GIC_REDIST_REG_SYNCR_OFF 0x00c0
598
599	/** Redistributor Peripheral ID2 Register - RO. */
600	#define GIC_REDIST_REG_PIDR2_OFF 0xffe8
601	/** Bit 4 - 7 - GIC architecture revision */
602	# define GIC_REDIST_REG_PIDR2_ARCHREV (RT_BIT_32(4) \| RT_BIT_32(5) \| RT_BIT_32(6) \| RT_BIT_32(7))
603	# define GIC_REDIST_REG_PIDR2_ARCHREV_SET(a_ArchRev) (((a_ArchRev) << 4) & GIC_REDIST_REG_PIDR2_ARCHREV)
604	/** GICv1 architecture revision. */
605	# define GIC_REDIST_REG_PIDR2_ARCHREV_GICV1 0x1
606	/** GICv2 architecture revision. */
607	# define GIC_REDIST_REG_PIDR2_ARCHREV_GICV2 0x2
608	/** GICv3 architecture revision. */
609	# define GIC_REDIST_REG_PIDR2_ARCHREV_GICV3 0x3
610	/** GICv4 architecture revision. */
611	# define GIC_REDIST_REG_PIDR2_ARCHREV_GICV4 0x4
612	/** @} */
613
614
615	/** @name GICD - GIC SGI and PPI Redistributor registers (Adjacent to the GIC Redistributor register space).
616	* @{ */
617	/** Size of the SGI and PPI redistributor register frame. */
618	#define GIC_REDIST_SGI_PPI_REG_FRAME_SIZE _64K
619
620	/** Interrupt Group Register 0 - RW. */
621	#define GIC_REDIST_SGI_PPI_REG_IGROUPR0_OFF 0x0080
622	/** Interrupt Group Register 2 for extended PPI range - RW, last offset. */
623	#define GIC_REDIST_SGI_PPI_REG_IGROUPRnE_OFF_LAST 0x0088
624	/** Interrupt Group Register, range in bytes. */
625	#define GIC_REDIST_SGI_PPI_REG_IGROUPRnE_RANGE_SIZE (GIC_REDIST_SGI_PPI_REG_IGROUPRnE_OFF_LAST + sizeof(uint32_t) - GIC_REDIST_SGI_PPI_REG_IGROUPR0_OFF)
626
627	/** Interrupt Set Enable Register 0 - RW. */
628	#define GIC_REDIST_SGI_PPI_REG_ISENABLER0_OFF 0x0100
629	/** Interrupt Set Enable Register 1 for extended PPI range - RW. */
630	#define GIC_REDIST_SGI_PPI_REG_ISENABLER1E_OFF 0x0104
631	/** Interrupt Set Enable Register 2 for extended PPI range - RW. */
632	#define GIC_REDIST_SGI_PPI_REG_ISENABLER2E_OFF 0x0108
633	#define GIC_REDIST_SGI_PPI_REG_ISENABLERnE_OFF_LAST GIC_REDIST_SGI_PPI_REG_ISENABLER2E_OFF
634	/** Interrupt Set Enable Register, range in bytes. */
635	#define GIC_REDIST_SGI_PPI_REG_ISENABLERnE_RANGE_SIZE (GIC_REDIST_SGI_PPI_REG_ISENABLERnE_OFF_LAST + sizeof(uint32_t) - GIC_REDIST_SGI_PPI_REG_ISENABLER0_OFF)
636
637	/** Interrupt Clear Enable Register 0 - RW. */
638	#define GIC_REDIST_SGI_PPI_REG_ICENABLER0_OFF 0x0180
639	/** Interrupt Clear Enable Register for extended PPI range, start offset - RW. */
640	#define GIC_REDIST_SGI_PPI_REG_ICENABLERnE_OFF_START 0x0184
641	/** Interrupt Clear Enable Register for extended PPI range, last offset - RW. */
642	#define GIC_REDIST_SGI_PPI_REG_ICENABLERnE_OFF_LAST 0x0188
643	/** Interrupt Clear Enable Register, range in bytes. */
644	#define GIC_REDIST_SGI_PPI_REG_ICENABLERnE_RANGE_SIZE (GIC_REDIST_SGI_PPI_REG_ICENABLERnE_OFF_LAST + sizeof(uint32_t) - GIC_REDIST_SGI_PPI_REG_ICENABLER0_OFF)
645
646	/** Interrupt Set Pending Register 0 - RW. */
647	#define GIC_REDIST_SGI_PPI_REG_ISPENDR0_OFF 0x0200
648	/** Interrupt Set Pending Registers for extended PPI range, last offset - RW. */
649	#define GIC_REDIST_SGI_PPI_REG_ISPENDRnE_OFF_LAST 0x0208
650	/** Interrupt Set Pending Registers for extended PPI range, range in bytes. */
651	#define GIC_REDIST_SGI_PPI_REG_ISPENDRnE_RANGE_SIZE (GIC_REDIST_SGI_PPI_REG_ISPENDRnE_OFF_LAST + sizeof(uint32_t) - GIC_REDIST_SGI_PPI_REG_ISPENDR0_OFF)
652
653	/** Interrupt Clear Pending Register 0 - RW. */
654	#define GIC_REDIST_SGI_PPI_REG_ICPENDR0_OFF 0x0280
655	/** Interrupt Clear Pending Registers for extended PPI range, last offset - RW. */
656	#define GIC_REDIST_SGI_PPI_REG_ICPENDRnE_OFF_LAST 0x0288
657	/** Interrupt Clear Pending Register for extended PPI range, range in bytes. */
658	#define GIC_REDIST_SGI_PPI_REG_ICPENDRnE_RANGE_SIZE (GIC_REDIST_SGI_PPI_REG_ICPENDRnE_OFF_LAST + sizeof(uint32_t) - GIC_REDIST_SGI_PPI_REG_ICPENDR0_OFF)
659
660	/** Interrupt Set Active Register 0 - RW. */
661	#define GIC_REDIST_SGI_PPI_REG_ISACTIVER0_OFF 0x0300
662	/** Interrupt Set Active Registers for extended PPI range, last offset - RW. */
663	#define GIC_REDIST_SGI_PPI_REG_ISACTIVERnE_OFF_LAST 0x0308
664	/** Interrupt Set Active Registers for extended PPI range, range in bytes. */
665	#define GIC_REDIST_SGI_PPI_REG_ISACTIVERnE_RANGE_SIZE (GIC_REDIST_SGI_PPI_REG_ISACTIVERnE_OFF_LAST + sizeof(uint32_t) - GIC_REDIST_SGI_PPI_REG_ISACTIVER0_OFF)
666
667	/** Interrupt Clear Active Register 0 - RW. */
668	#define GIC_REDIST_SGI_PPI_REG_ICACTIVER0_OFF 0x0380
669	/** Interrupt Clear Active Registers for extended PPI range, last offset - RW. */
670	#define GIC_REDIST_SGI_PPI_REG_ICACTIVERnE_OFF_LAST 0x0388
671	/** Interrupt Clear Active Register for extended PPI range, range in bytes. */
672	#define GIC_REDIST_SGI_PPI_REG_ICACTIVERnE_RANGE_SIZE (GIC_REDIST_SGI_PPI_REG_ICACTIVERnE_OFF_LAST + sizeof(uint32_t) - GIC_REDIST_SGI_PPI_REG_ICACTIVER0_OFF)
673
674	/** Interrupt Priority Registers, start offset - RW. */
675	#define GIC_REDIST_SGI_PPI_REG_IPRIORITYRn_OFF_START 0x0400
676	/** Interrupt Priority Registers, last offset - RW. */
677	#define GIC_REDIST_SGI_PPI_REG_IPRIORITYRn_OFF_LAST 0x041c
678	/** Interrupt Priority Registers for extended PPI range, start offset - RW. */
679	#define GIC_REDIST_SGI_PPI_REG_IPRIORITYRnE_OFF_START 0x0420
680	/** Interrupt Priority Registers for extended PPI range, last offset - RW. */
681	#define GIC_REDIST_SGI_PPI_REG_IPRIORITYRnE_OFF_LAST 0x045c
682	/** Interrupt Priority Registers for extended PPI range, range in bytes. */
683	#define GIC_REDIST_SGI_PPI_REG_IPRIORITYRnE_RANGE_SIZE (GIC_REDIST_SGI_PPI_REG_IPRIORITYRnE_OFF_LAST + sizeof(uint32_t) - GIC_REDIST_SGI_PPI_REG_IPRIORITYRn_OFF_START)
684
685	/** SGI Configuration Register - RW. */
686	#define GIC_REDIST_SGI_PPI_REG_ICFGR0_OFF 0x0c00
687	/** PPI Configuration Register - RW. */
688	#define GIC_REDIST_SGI_PPI_REG_ICFGR1_OFF 0x0c04
689	/** Extended PPI Configuration Register, start offset - RW. */
690	#define GIC_REDIST_SGI_PPI_REG_ICFGRnE_OFF_START 0x0c08
691	/** Extended PPI Configuration Register, last offset - RW. */
692	#define GIC_REDIST_SGI_PPI_REG_ICFGRnE_OFF_LAST 0x0c14
693	/** SGI Configure Register, range in bytes. */
694	#define GIC_REDIST_SGI_PPI_REG_ICFGRnE_RANGE_SIZE (GIC_REDIST_SGI_PPI_REG_ICFGRnE_OFF_LAST + sizeof(uint32_t) - GIC_REDIST_SGI_PPI_REG_ICFGR0_OFF)
695
696	/** Interrupt Group Modifier Register 0 - RW. */
697	#define GIC_REDIST_SGI_PPI_REG_IGRPMODR0_OFF 0x0d00
698	/** Interrupt Group Modifier Register 1 for extended PPI range - RW. */
699	#define GIC_REDIST_SGI_PPI_REG_IGRPMODR1E_OFF 0x0d04
700	/** Interrupt Group Modifier Register 2 for extended PPI range - RW. */
701	#define GIC_REDIST_SGI_PPI_REG_IGRPMODR2E_OFF 0x0d08
702
703	/** Non Secure Access Control Register - RW. */
704	#define GIC_REDIST_SGI_PPI_REG_NSACR_OFF 0x0e00
705
706	/** Non maskable Interrupt Register for PPIs - RW. */
707	#define GIC_REDIST_SGI_PPI_REG_INMIR0_OFF 0x0f80
708	/** Non maskable Interrupt Register for Extended PPIs, start offset - RW. */
709	#define GIC_REDIST_SGI_PPI_REG_INMIRnE_OFF_START 0x0f84
710	/** Non maskable Interrupt Register for Extended PPIs, last offset - RW. */
711	#define GIC_REDIST_SGI_PPI_REG_INMIRnE_OFF_LAST 0x0ffc
712	/** Non maskable Interrupt Register for Extended PPIs, range in bytes. */
713	#define GIC_REDIST_SGI_PPI_REG_INMIRnE_RANGE_SIZE (GIC_REDIST_SGI_PPI_REG_INMIRnE_OFF_LAST + sizeof(uint32_t) - GIC_REDIST_SGI_PPI_REG_INMIR0_OFF)
714	/** @} */
715
716
717	/** @name JEDEC codes for ARM.
718	* @{ */
719	/** JEP106 identification code. */
720	#define GIC_JEDEC_JEP106_IDENTIFICATION_CODE 0x3b
721	/** JEP106 continuation code. */
722	#define GIC_JEDEC_JEP106_CONTINUATION_CODE 0x4
723
724	/** DES_0 - JEP106 identification code bits (3:0). */
725	#define GIC_JEDEC_JEP10_DES_0(a_JepIdCode) ((a_JepIdCode) & 0xf)
726	/** DES_1 - JEP106 identification code bits (6:4). */
727	#define GIC_JEDEC_JEP10_DES_1(a_JepIdCode) (((a_JepIdCode) >> 4) & 0x70)
728	/** @} */
729
730
731	/** @name LPI configuration table entry.
732	* @{ */
733	/** GITS LPI Configuration */
734	/** GITS LPI CTE: Enable. */
735	#define GIC_BF_LPI_CTE_ENABLE_SHIFT 0
736	#define GIC_BF_LPI_CTE_ENABLE_MASK UINT8_C(0x1)
737	/** GITS LPI CTE: Reserved (bit 1). */
738	#define GIC_BF_LPI_CTE_RSVD_1_SHIFT 1
739	#define GIC_BF_LPI_CTE_RSVD_1_MASK UINT8_C(0x2)
740	/** GITS LPI CTE: Priority. */
741	#define GIC_BF_LPI_CTE_PRIORITY_SHIFT 2
742	#define GIC_BF_LPI_CTE_PRIORITY_MASK UINT8_C(0xfc)
743	RT_BF_ASSERT_COMPILE_CHECKS(GIC_BF_LPI_CTE_, UINT8_C(0), UINT8_MAX,
744	(ENABLE, RSVD_1, PRIORITY));
745
746	/** Minimum number of bits required to enable LPIs (i.e. should accomodate
747	* GIC_INTID_RANGE_LPI_START). */
748	#define GIC_LPI_ID_BITS_MIN 14
749
750	/** @} */
751
752	#endif /* !VBOX_INCLUDED_gic_h */
753

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source: vbox/trunk/include/VBox/gic.h@ 109019

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