gic.h@ 99547

Last change on this file since 99547 was 99485, checked in by vboxsync, 20 months ago
include/VBox: Add header containing definitions for the ARM Generic Interrupt Controller Architecture v3 (GIC), bugref:10404
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 16.8 KB

Line
1	/** @file
2	* ARMv8 Generic Interrupt Controller Architecture v3 (GICv3) definitions.
3	*/
4
5	/*
6	* Copyright (C) 2023 Oracle and/or its affiliates.
7	*
8	* This file is part of VirtualBox base platform packages, as
9	* available from https://www.virtualbox.org.
10	*
11	* This program is free software; you can redistribute it and/or
12	* modify it under the terms of the GNU General Public License
13	* as published by the Free Software Foundation, in version 3 of the
14	* License.
15	*
16	* This program is distributed in the hope that it will be useful, but
17	* WITHOUT ANY WARRANTY; without even the implied warranty of
18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19	* General Public License for more details.
20	*
21	* You should have received a copy of the GNU General Public License
22	* along with this program; if not, see <https://www.gnu.org/licenses>.
23	*
24	* The contents of this file may alternatively be used under the terms
25	* of the Common Development and Distribution License Version 1.0
26	* (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
27	* in the VirtualBox distribution, in which case the provisions of the
28	* CDDL are applicable instead of those of the GPL.
29	*
30	* You may elect to license modified versions of this file under the
31	* terms and conditions of either the GPL or the CDDL or both.
32	*
33	* SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
34	*/
35
36	#ifndef VBOX_INCLUDED_gic_h
37	#define VBOX_INCLUDED_gic_h
38	#ifndef RT_WITHOUT_PRAGMA_ONCE
39	# pragma once
40	#endif
41
42	#include <iprt/types.h>
43	#include <iprt/armv8.h>
44
45
46	/** @name GICD - GIC Distributor registers.
47	* @{ */
48	/** Size of the distributor register frame. */
49	#define GIC_DIST_REG_FRAME_SIZE _64K
50	/** Distributor Control Register - RW. */
51	#define GIC_DIST_REG_CTLR_OFF 0x0000
52	/** Interrupt Controller Type Register - RO. */
53	#define GIC_DIST_REG_TYPER_OFF 0x0004
54	/** Distributor Implementer Identification Register - RO. */
55	#define GIC_DIST_REG_IIDR_OFF 0x0008
56	/** Interrupt Controller Type Register 2 - RO. */
57	#define GIC_DIST_REG_TYPER2_OFF 0x000c
58	/** Error Reporting Status Register (optional) - RW. */
59	#define GIC_DIST_RG_STATUSR_OFF 0x0010
60	/** Set SPI Register - WO. */
61	#define GIC_DIST_REG_SETSPI_NSR_OFF 0x0040
62	/** Clear SPI Register - WO. */
63	#define GIC_DIST_REG_CLRSPI_NSR_OFF 0x0048
64	/** Set SPI, Secure Register - WO. */
65	#define GIC_DIST_REG_SETSPI_SR_OFF 0x0050
66	/** Clear SPI, Secure Register - WO. */
67	#define GIC_DIST_REG_CLRSPI_SR_OFF 0x0058
68
69	/** Interrupt Group Registers, start offset - RW. */
70	#define GIC_DIST_REG_IGROUPRn_OFF_START 0x0080
71	/** Interrupt Group Registers, last offset - RW. */
72	#define GIC_DIST_REG_IGROUPRn_OFF_LAST 0x00fc
73
74	/** Interrupt Set Enable Registers, start offset - RW. */
75	#define GIC_DIST_REG_ISENABLERn_OFF_START 0x0100
76	/** Interrupt Set Enable Registers, last offset - RW. */
77	#define GIC_DIST_REG_ISENABLERn_OFF_LAST 0x017c
78	/** Interrupt Clear Enable Registers, start offset - RW. */
79	#define GIC_DIST_REG_ICENABLERn_OFF_START 0x0180
80	/** Interrupt Clear Enable Registers, last offset - RW. */
81	#define GIC_DIST_REG_ICENABLERn_OFF_LAST 0x01fc
82
83	/** Interrupt Set Pending Registers, start offset - RW. */
84	#define GIC_DIST_REG_ISPENDRn_OFF_START 0x0200
85	/** Interrupt Set Pending Registers, last offset - RW. */
86	#define GIC_DIST_REG_ISPENDRn_OFF_LAST 0x027c
87	/** Interrupt Clear Pending Registers, start offset - RW. */
88	#define GIC_DIST_REG_ICPENDRn_OFF_START 0x0280
89	/** Interrupt Clear Pending Registers, last offset - RW. */
90	#define GIC_DIST_REG_ICPENDRn_OFF_LAST 0x02fc
91
92	/** Interrupt Set Active Registers, start offset - RW. */
93	#define GIC_DIST_REG_ISACTIVERn_OFF_START 0x0300
94	/** Interrupt Set Active Registers, last offset - RW. */
95	#define GIC_DIST_REG_ISACTIVERn_OFF_LAST 0x037c
96	/** Interrupt Clear Active Registers, start offset - RW. */
97	#define GIC_DIST_REG_ICACTIVERn_OFF_START 0x0380
98	/** Interrupt Clear Active Registers, last offset - RW. */
99	#define GIC_DIST_REG_ICACTIVERn_OFF_LAST 0x03fc
100
101	/** Interrupt Priority Registers, start offset - RW. */
102	#define GIC_DIST_REG_IPRIORITYn_OFF_START 0x0400
103	/** Interrupt Priority Registers, last offset - RW. */
104	#define GIC_DIST_REG_IPRIORITYn_OFF_LAST 0x07f8
105
106	/** Interrupt Processor Targets Registers, start offset - RO/RW. */
107	#define GIC_DIST_REG_ITARGETSRn_OFF_START 0x0800
108	/** Interrupt Processor Targets Registers, last offset - RO/RW. */
109	#define GIC_DIST_REG_ITARGETSRn_OFF_LAST 0x0bf8
110
111	/** Interrupt Configuration Registers, start offset - RW. */
112	#define GIC_DIST_REG_ICFGRn_OFF_START 0x0c00
113	/** Interrupt Configuration Registers, last offset - RW. */
114	#define GIC_DIST_REG_ICFGRn_OFF_LAST 0x0cfc
115
116	/** Interrupt Group Modifier Registers, start offset - RW. */
117	#define GIC_DIST_REG_IGRPMODRn_OFF_START 0x0d00
118	/** Interrupt Group Modifier Registers, last offset - RW. */
119	#define GIC_DIST_REG_IGRPMODRn_OFF_LAST 0x0d7c
120
121	/** Non-secure Access Control Registers, start offset - RW. */
122	#define GIC_DIST_REG_NSACRn_OFF_START 0x0e00
123	/** Non-secure Access Control Registers, last offset - RW. */
124	#define GIC_DIST_REG_NSACRn_OFF_LAST 0x0efc
125
126	/** Software Generated Interrupt Register - RW. */
127	#define GIC_DIST_REG_SGIR_OFF 0x0f00
128
129	/** SGI Clear Pending Registers, start offset - RW. */
130	#define GIC_DIST_REG_CPENDSGIRn_OFF_START 0x0f10
131	/** SGI Clear Pending Registers, last offset - RW. */
132	#define GIC_DIST_REG_CPENDSGIRn_OFF_LAST 0x0f1c
133	/** SGI Set Pending Registers, start offset - RW. */
134	#define GIC_DIST_REG_SPENDSGIRn_OFF_START 0x0f20
135	/** SGI Set Pending Registers, last offset - RW. */
136	#define GIC_DIST_REG_SPENDSGIRn_OFF_LAST 0x0f2c
137
138	/** Non-maskable Interrupt Registers, start offset - RW. */
139	#define GIC_DIST_REG_INMIn_OFF_START 0x0f80
140	/** Non-maskable Interrupt Registers, last offset - RW. */
141	#define GIC_DIST_REG_INMIn_OFF_LAST 0x0ffc
142
143
144	/** Interrupt Group Registers for extended SPI range, start offset - RW. */
145	#define GIC_DIST_REG_IGROUPRnE_OFF_START 0x1000
146	/** Interrupt Group Registers for extended SPI range, last offset - RW. */
147	#define GIC_DIST_REG_IGROUPRnE_OFF_LAST 0x107c
148
149	/** Interrupt Set Enable Registers for extended SPI range, start offset - RW. */
150	#define GIC_DIST_REG_ISENABLERnE_OFF_START 0x1200
151	/** Interrupt Set Enable Registers for extended SPI range, last offset - RW. */
152	#define GIC_DIST_REG_ISENABLERnE_OFF_LAST 0x127c
153	/** Interrupt Clear Enable Registers for extended SPI range, start offset - RW. */
154	#define GIC_DIST_REG_ICENABLERnE_OFF_START 0x1400
155	/** Interrupt Clear Enable Registers for extended SPI range, last offset - RW. */
156	#define GIC_DIST_REG_ICENABLERnE_OFF_LAST 0x147c
157
158	/** Interrupt Set Pending Registers for extended SPI range, start offset - RW. */
159	#define GIC_DIST_REG_ISPENDRnE_OFF_START 0x1600
160	/** Interrupt Set Pending Registers for extended SPI range, last offset - RW. */
161	#define GIC_DIST_REG_ISPENDRnE_OFF_LAST 0x167c
162	/** Interrupt Clear Pending Registers for extended SPI range, start offset - RW. */
163	#define GIC_DIST_REG_ICPENDRnE_OFF_START 0x1800
164	/** Interrupt Clear Pending Registers for extended SPI range, last offset - RW. */
165	#define GIC_DIST_REG_ICPENDRnE_OFF_LAST 0x187c
166
167	/** Interrupt Set Active Registers for extended SPI range, start offset - RW. */
168	#define GIC_DIST_REG_ISACTIVERnE_OFF_START 0x1a00
169	/** Interrupt Set Active Registers for extended SPI range, last offset - RW. */
170	#define GIC_DIST_REG_ISACTIVERnE_OFF_LAST 0x1a7c
171	/** Interrupt Clear Active Registers for extended SPI range, start offset - RW. */
172	#define GIC_DIST_REG_ICACTIVERnE_OFF_START 0x1c00
173	/** Interrupt Clear Active Registers for extended SPI range, last offset - RW. */
174	#define GIC_DIST_REG_ICACTIVERnE_OFF_LAST 0x1c7c
175
176	/** Interrupt Priority Registers for extended SPI range, start offset - RW. */
177	#define GIC_DIST_REG_IPRIORITYnE_OFF_START 0x2000
178	/** Interrupt Priority Registers for extended SPI range, last offset - RW. */
179	#define GIC_DIST_REG_IPRIORITYnE_OFF_LAST 0x23fc
180
181	/** Interrupt Configuration Registers for extended SPI range, start offset - RW. */
182	#define GIC_DIST_REG_ICFGRnE_OFF_START 0x3000
183	/** Interrupt Configuration Registers for extended SPI range, last offset - RW. */
184	#define GIC_DIST_REG_ICFGRnE_OFF_LAST 0x30fc
185
186	/** Interrupt Group Modifier Registers for extended SPI range, start offset - RW. */
187	#define GIC_DIST_REG_IGRPMODRnE_OFF_START 0x3400
188	/** Interrupt Group Modifier Registers for extended SPI range, last offset - RW. */
189	#define GIC_DIST_REG_IGRPMODRnE_OFF_LAST 0x347c
190
191	/** Non-secure Access Control Registers for extended SPI range, start offset - RW. */
192	#define GIC_DIST_REG_NSACRnE_OFF_START 0x3600
193	/** Non-secure Access Control Registers for extended SPI range, last offset - RW. */
194	#define GIC_DIST_REG_NSACRnE_OFF_LAST 0x367c
195
196	/** Non-maskable Interrupt Registers for extended SPIs, start offset - RW. */
197	#define GIC_DIST_REG_INMInE_OFF_START 0x3b00
198	/** Non-maskable Interrupt Registers for extended SPIs, last offset - RW. */
199	#define GIC_DIST_REG_INMInE_OFF_LAST 0x3b7c
200
201	/** Interrupt Routing Registers, start offset - RW. */
202	#define GIC_DIST_REG_IROUTERn_OFF_START 0x6100
203	/** Interrupt Routing Registers, last offset - RW. */
204	#define GIC_DIST_REG_IROUTERn_OFF_LAST 0x7fd8
205	/** Interrupt Routing Registers for extended SPI range, start offset - RW. */
206	#define GIC_DIST_REG_IROUTERnE_OFF_START 0x8000
207	/** Interrupt Routing Registers for extended SPI range, last offset - RW. */
208	#define GIC_DIST_REG_IROUTERnE_OFF_LAST 0x9ffc
209
210	/** Distributor Peripheral ID2 Register - RO. */
211	#define GIC_DIST_REG_PIDR2_OFF 0xffe8
212	/** @} */
213
214
215	/** @name GICD - GIC Redistributor registers.
216	* @{ */
217	/** Size of the redistributor register frame. */
218	#define GIC_REDIST_REG_FRAME_SIZE _64K
219	/** Redistributor Control Register - RW. */
220	#define GIC_REDIST_REG_CTLR_OFF 0x0000
221	/** Implementer Identification Register - RO. */
222	#define GIC_REDIST_REG_IIDR_OFF 0x0004
223	/** Redistributor Type Register - RO. */
224	#define GIC_REDIST_REG_TYPER_OFF 0x0008
225	/** Redistributor Error Reporting Status Register (optional) - RW. */
226	#define GIC_REDIST_REG_STATUSR_OFF 0x0010
227	/** Redistributor Wake Register - RW. */
228	#define GIC_REDIST_REG_WAKER_OFF 0x0014
229	/** Redistributor Report maximum PARTID and PMG Register - RO. */
230	#define GIC_REDIST_REG_MPAMIDR_OFF 0x0018
231	/** Redistributor Set PARTID and PMG Register - RW. */
232	#define GIC_REDIST_REG_PARTIDR_OFF 0x001c
233	/** Redistributor Set LPI Pending Register - WO. */
234	#define GIC_REDIST_REG_SETLPIR_OFF 0x0040
235	/** Redistributor Clear LPI Pending Register - WO. */
236	#define GIC_REDIST_REG_CLRLPIR_OFF 0x0048
237	/** Redistributor Properties Base Address Register - RW. */
238	#define GIC_REDIST_REG_PROPBASER_OFF 0x0070
239	/** Redistributor LPI Pending Table Base Address Register - RW. */
240	#define GIC_REDIST_REG_PENDBASER_OFF 0x0078
241	/** Redistributor Invalidate LPI Register - WO. */
242	#define GIC_REDIST_REG_INVLPIR_OFF 0x00a0
243	/** Redistributor Invalidate All Register - WO. */
244	#define GIC_REDIST_REG_INVALLR_OFF 0x00b0
245	/** Redistributor Synchronize Register - RO. */
246	#define GIC_REDIST_REG_SYNCR_OFF 0x00c0
247
248	/** Redistributor Peripheral ID2 Register - RO. */
249	#define GIC_REDIST_REG_PIDR2_OFF 0xffe8
250	/** @} */
251
252
253	/** @name GICD - GIC SGI and PPI Redistributor registers (Adjacent to the GIC Redistributor register space).
254	* @{ */
255	/** Size of the SGI and PPI redistributor register frame. */
256	#define GIC_REDIST_SGI_PPI_REG_FRAME_SIZE _64K
257
258	/** Interrupt Group Register 0 - RW. */
259	#define GIC_REDIST_SGI_PPI_REG_IGROUPR0_OFF 0x0080
260	/** Interrupt Group Register 1 for extended PPI range - RW. */
261	#define GIC_REDIST_SGI_PPI_REG_IGROUPR1E_OFF 0x0084
262	/** Interrupt Group Register 2 for extended PPI range - RW. */
263	#define GIC_REDIST_SGI_PPI_REG_IGROUPR2E_OFF 0x0084
264
265	/** Interrupt Set Enable Register 0 - RW. */
266	#define GIC_REDIST_SGI_PPI_REG_ISENABLER0_OFF 0x0100
267	/** Interrupt Set Enable Register 1 for extended PPI range - RW. */
268	#define GIC_REDIST_SGI_PPI_REG_ISENABLER1E_OFF 0x0104
269	/** Interrupt Set Enable Register 2 for extended PPI range - RW. */
270	#define GIC_REDIST_SGI_PPI_REG_ISENABLER2E_OFF 0x0108
271
272	/** Interrupt Clear Enable Register 0 - RW. */
273	#define GIC_REDIST_SGI_PPI_REG_ICENABLER0_OFF 0x0100
274	/** Interrupt Clear Enable Register 1 for extended PPI range - RW. */
275	#define GIC_REDIST_SGI_PPI_REG_ICENABLER1E_OFF 0x0104
276	/** Interrupt Clear Enable Register 2 for extended PPI range - RW. */
277	#define GIC_REDIST_SGI_PPI_REG_ICENABLER2E_OFF 0x0108
278
279	/** Interrupt Set Pend Register 0 - RW. */
280	#define GIC_REDIST_SGI_PPI_REG_ISPENDR0_OFF 0x0200
281	/** Interrupt Set Pend Register 1 for extended PPI range - RW. */
282	#define GIC_REDIST_SGI_PPI_REG_ISPENDR1E_OFF 0x0204
283	/** Interrupt Set Pend Register 2 for extended PPI range - RW. */
284	#define GIC_REDIST_SGI_PPI_REG_ISPENDR2E_OFF 0x0208
285
286	/** Interrupt Clear Pend Register 0 - RW. */
287	#define GIC_REDIST_SGI_PPI_REG_ICPENDR0_OFF 0x0280
288	/** Interrupt Clear Pend Register 1 for extended PPI range - RW. */
289	#define GIC_REDIST_SGI_PPI_REG_ICPENDR1E_OFF 0x0284
290	/** Interrupt Clear Pend Register 2 for extended PPI range - RW. */
291	#define GIC_REDIST_SGI_PPI_REG_ICPENDR2E_OFF 0x0288
292
293	/** Interrupt Set Active Register 0 - RW. */
294	#define GIC_REDIST_SGI_PPI_REG_ISACTIVER0_OFF 0x0300
295	/** Interrupt Set Active Register 1 for extended PPI range - RW. */
296	#define GIC_REDIST_SGI_PPI_REG_ISACTIVER1E_OFF 0x0304
297	/** Interrupt Set Active Register 2 for extended PPI range - RW. */
298	#define GIC_REDIST_SGI_PPI_REG_ISACTIVER2E_OFF 0x0308
299
300	/** Interrupt Clear Active Register 0 - RW. */
301	#define GIC_REDIST_SGI_PPI_REG_ICACTIVER0_OFF 0x0380
302	/** Interrupt Clear Active Register 1 for extended PPI range - RW. */
303	#define GIC_REDIST_SGI_PPI_REG_ICACTIVER1E_OFF 0x0384
304	/** Interrupt Clear Active Register 2 for extended PPI range - RW. */
305	#define GIC_REDIST_SGI_PPI_REG_ICACTIVER2E_OFF 0x0388
306
307	/** Interrupt Priority Registers, start offset - RW. */
308	#define GIC_REDIST_SGI_PPI_REG_IPRIORITYn_OFF_START 0x0400
309	/** Interrupt Priority Registers, last offset - RW. */
310	#define GIC_REDIST_SGI_PPI_REG_IPRIORITYn_OFF_LAST 0x041c
311	/** Interrupt Priority Registers for extended PPI range, start offset - RW. */
312	#define GIC_REDIST_SGI_PPI_REG_IPRIORITYnE_OFF_START 0x0420
313	/** Interrupt Priority Registers for extended PPI range, last offset - RW. */
314	#define GIC_REDIST_SGI_PPI_REG_IPRIORITYnE_OFF_LAST 0x045c
315
316	/** SGI Configuration Register - RW. */
317	#define GIC_REDIST_SGI_PPI_REG_ICFGR0_OFF 0x0c00
318	/** PPI Configuration Register - RW. */
319	#define GIC_REDIST_SGI_PPI_REG_ICFGR1_OFF 0x0c04
320	/** Extended PPI Configuration Register, start offset - RW. */
321	#define GIC_REDIST_SGI_PPI_REG_ICFGRnE_OFF_START 0x0c08
322	/** Extended PPI Configuration Register, last offset - RW. */
323	#define GIC_REDIST_SGI_PPI_REG_ICFGRnE_OFF_LAST 0x0c14
324
325	/** Interrupt Group Modifier Register 0 - RW. */
326	#define GIC_REDIST_SGI_PPI_REG_IGRPMODR0_OFF 0x0d00
327	/** Interrupt Group Modifier Register 1 for extended PPI range - RW. */
328	#define GIC_REDIST_SGI_PPI_REG_IGRPMODR1E_OFF 0x0d04
329	/** Interrupt Group Modifier Register 2 for extended PPI range - RW. */
330	#define GIC_REDIST_SGI_PPI_REG_IGRPMODR2E_OFF 0x0d08
331
332	/** Non Secure Access Control Register - RW. */
333	#define GIC_REDIST_SGI_PPI_REG_NSACR_OFF 0x0e00
334
335	/** Non maskable Interrupt Register for PPIs - RW. */
336	#define GIC_REDIST_SGI_PPI_REG_INMIR0_OFF 0x0f80
337	/** Non maskable Interrupt Register for Extended PPIs, start offset - RW. */
338	#define GIC_REDIST_SGI_PPI_REG_INMIRnE_OFF_START 0x0f84
339	/** Non maskable Interrupt Register for Extended PPIs, last offset - RW. */
340	#define GIC_REDIST_SGI_PPI_REG_INMIRnE_OFF_LAST 0x0ffc
341	/** @} */
342
343
344	#endif /* !VBOX_INCLUDED_gic_h */
345

Note: See TracBrowser for help on using the repository browser.

source: vbox/trunk/include/VBox/gic.h@ 99547

Download in other formats: