hwacc_svm.h@ 8113

Last change on this file since 8113 was 7133, checked in by vboxsync, 17 years ago
Eliminate cpum.h dependency (shuts up a bunch of .c warnings). Fixed the header tests.
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 22.2 KB

Line
1	/** @file
2	* SVM Structures and Definitions.
3	*/
4
5	/*
6	* Copyright (C) 2006-2007 innotek GmbH
7	*
8	* This file is part of VirtualBox Open Source Edition (OSE), as
9	* available from http://www.virtualbox.org. This file is free software;
10	* you can redistribute it and/or modify it under the terms of the GNU
11	* General Public License (GPL) as published by the Free Software
12	* Foundation, in version 2 as it comes in the "COPYING" file of the
13	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15	*
16	* The contents of this file may alternatively be used under the terms
17	* of the Common Development and Distribution License Version 1.0
18	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19	* VirtualBox OSE distribution, in which case the provisions of the
20	* CDDL are applicable instead of those of the GPL.
21	*
22	* You may elect to license modified versions of this file under the
23	* terms and conditions of either the GPL or the CDDL or both.
24	*/
25
26	#ifndef ___VBox_svm_h
27	#define ___VBox_svm_h
28
29	#include <VBox/types.h>
30	#include <VBox/err.h>
31	#include <iprt/assert.h>
32	#include <iprt/asm.h>
33
34	/** @defgroup grp_svm svm Types and Definitions
35	* @ingroup grp_hwaccm
36	* @{
37	*/
38
39
40	/** @name SVM Basic Exit Reasons.
41	* @{
42	*/
43	/** Invalid guest state in VMCB. */
44	#define SVM_EXIT_INVALID -1
45	/** Read from CR0-CR15. */
46	#define SVM_EXIT_READ_CR0 0x0
47	#define SVM_EXIT_READ_CR1 0x1
48	#define SVM_EXIT_READ_CR2 0x2
49	#define SVM_EXIT_READ_CR3 0x3
50	#define SVM_EXIT_READ_CR4 0x4
51	#define SVM_EXIT_READ_CR5 0x5
52	#define SVM_EXIT_READ_CR6 0x6
53	#define SVM_EXIT_READ_CR7 0x7
54	#define SVM_EXIT_READ_CR8 0x8
55	#define SVM_EXIT_READ_CR9 0x9
56	#define SVM_EXIT_READ_CR10 0xA
57	#define SVM_EXIT_READ_CR11 0xB
58	#define SVM_EXIT_READ_CR12 0xC
59	#define SVM_EXIT_READ_CR13 0xD
60	#define SVM_EXIT_READ_CR14 0xE
61	#define SVM_EXIT_READ_CR15 0xF
62	/** Writes to CR0-CR15. */
63	#define SVM_EXIT_WRITE_CR0 0x10
64	#define SVM_EXIT_WRITE_CR1 0x11
65	#define SVM_EXIT_WRITE_CR2 0x12
66	#define SVM_EXIT_WRITE_CR3 0x13
67	#define SVM_EXIT_WRITE_CR4 0x14
68	#define SVM_EXIT_WRITE_CR5 0x15
69	#define SVM_EXIT_WRITE_CR6 0x16
70	#define SVM_EXIT_WRITE_CR7 0x17
71	#define SVM_EXIT_WRITE_CR8 0x18
72	#define SVM_EXIT_WRITE_CR9 0x19
73	#define SVM_EXIT_WRITE_CR10 0x1A
74	#define SVM_EXIT_WRITE_CR11 0x1B
75	#define SVM_EXIT_WRITE_CR12 0x1C
76	#define SVM_EXIT_WRITE_CR13 0x1D
77	#define SVM_EXIT_WRITE_CR14 0x1E
78	#define SVM_EXIT_WRITE_CR15 0x1F
79	/** Read from DR0-DR15. */
80	#define SVM_EXIT_READ_DR0 0x20
81	#define SVM_EXIT_READ_DR1 0x21
82	#define SVM_EXIT_READ_DR2 0x22
83	#define SVM_EXIT_READ_DR3 0x23
84	#define SVM_EXIT_READ_DR4 0x24
85	#define SVM_EXIT_READ_DR5 0x25
86	#define SVM_EXIT_READ_DR6 0x26
87	#define SVM_EXIT_READ_DR7 0x27
88	#define SVM_EXIT_READ_DR8 0x28
89	#define SVM_EXIT_READ_DR9 0x29
90	#define SVM_EXIT_READ_DR10 0x2A
91	#define SVM_EXIT_READ_DR11 0x2B
92	#define SVM_EXIT_READ_DR12 0x2C
93	#define SVM_EXIT_READ_DR13 0x2D
94	#define SVM_EXIT_READ_DR14 0x2E
95	#define SVM_EXIT_READ_DR15 0x2F
96	/** Writes to DR0-DR15. */
97	#define SVM_EXIT_WRITE_DR0 0x30
98	#define SVM_EXIT_WRITE_DR1 0x31
99	#define SVM_EXIT_WRITE_DR2 0x32
100	#define SVM_EXIT_WRITE_DR3 0x33
101	#define SVM_EXIT_WRITE_DR4 0x34
102	#define SVM_EXIT_WRITE_DR5 0x35
103	#define SVM_EXIT_WRITE_DR6 0x36
104	#define SVM_EXIT_WRITE_DR7 0x37
105	#define SVM_EXIT_WRITE_DR8 0x38
106	#define SVM_EXIT_WRITE_DR9 0x39
107	#define SVM_EXIT_WRITE_DR10 0x3A
108	#define SVM_EXIT_WRITE_DR11 0x3B
109	#define SVM_EXIT_WRITE_DR12 0x3C
110	#define SVM_EXIT_WRITE_DR13 0x3D
111	#define SVM_EXIT_WRITE_DR14 0x3E
112	#define SVM_EXIT_WRITE_DR15 0x3F
113	/* Exception 0-31. */
114	#define SVM_EXIT_EXCEPTION_0 0x40
115	#define SVM_EXIT_EXCEPTION_1 0x41
116	#define SVM_EXIT_EXCEPTION_2 0x42
117	#define SVM_EXIT_EXCEPTION_3 0x43
118	#define SVM_EXIT_EXCEPTION_4 0x44
119	#define SVM_EXIT_EXCEPTION_5 0x45
120	#define SVM_EXIT_EXCEPTION_6 0x46
121	#define SVM_EXIT_EXCEPTION_7 0x47
122	#define SVM_EXIT_EXCEPTION_8 0x48
123	#define SVM_EXIT_EXCEPTION_9 0x49
124	#define SVM_EXIT_EXCEPTION_A 0x4A
125	#define SVM_EXIT_EXCEPTION_B 0x4B
126	#define SVM_EXIT_EXCEPTION_C 0x4C
127	#define SVM_EXIT_EXCEPTION_D 0x4D
128	#define SVM_EXIT_EXCEPTION_E 0x4E
129	#define SVM_EXIT_EXCEPTION_F 0x4F
130	#define SVM_EXIT_EXCEPTION_10 0x50
131	#define SVM_EXIT_EXCEPTION_11 0x51
132	#define SVM_EXIT_EXCEPTION_12 0x52
133	#define SVM_EXIT_EXCEPTION_13 0x53
134	#define SVM_EXIT_EXCEPTION_14 0x54
135	#define SVM_EXIT_EXCEPTION_15 0x55
136	#define SVM_EXIT_EXCEPTION_16 0x56
137	#define SVM_EXIT_EXCEPTION_17 0x57
138	#define SVM_EXIT_EXCEPTION_18 0x58
139	#define SVM_EXIT_EXCEPTION_19 0x59
140	#define SVM_EXIT_EXCEPTION_1A 0x5A
141	#define SVM_EXIT_EXCEPTION_1B 0x5B
142	#define SVM_EXIT_EXCEPTION_1C 0x5C
143	#define SVM_EXIT_EXCEPTION_1D 0x5D
144	#define SVM_EXIT_EXCEPTION_1E 0x5E
145	#define SVM_EXIT_EXCEPTION_1F 0x5F
146	/** Physical maskable interrupt. */
147	#define SVM_EXIT_INTR 0x60
148	/** Non-maskable interrupt. */
149	#define SVM_EXIT_NMI 0x61
150	/** System Management interrupt. */
151	#define SVM_EXIT_SMI 0x62
152	/** Physical INIT signal. */
153	#define SVM_EXIT_INIT 0x63
154	/** Virtual interrupt. */
155	#define SVM_EXIT_VINTR 0x64
156	/** Write to CR0 that changed any bits other than CR0.TS or CR0.MP. */
157	#define SVM_EXIT_CR0_SEL_WRITE 0x65
158	/** IDTR read. */
159	#define SVM_EXIT_IDTR_READ 0x66
160	/** GDTR read. */
161	#define SVM_EXIT_GDTR_READ 0x67
162	/** LDTR read. */
163	#define SVM_EXIT_LDTR_READ 0x68
164	/** TR read. */
165	#define SVM_EXIT_TR_READ 0x69
166	/** IDTR write. */
167	#define SVM_EXIT_IDTR_WRITE 0x6A
168	/** GDTR write. */
169	#define SVM_EXIT_GDTR_WRITE 0x6B
170	/** LDTR write. */
171	#define SVM_EXIT_LDTR_WRITE 0x6C
172	/** TR write. */
173	#define SVM_EXIT_TR_WRITE 0x6D
174	/** RDTSC instruction. */
175	#define SVM_EXIT_RDTSC 0x6E
176	/** RDPMC instruction. */
177	#define SVM_EXIT_RDPMC 0x6F
178	/** PUSHF instruction. */
179	#define SVM_EXIT_PUSHF 0x70
180	/** POPF instruction. */
181	#define SVM_EXIT_POPF 0x71
182	/** CPUID instruction. */
183	#define SVM_EXIT_CPUID 0x72
184	/** RSM instruction. */
185	#define SVM_EXIT_RSM 0x73
186	/** IRET instruction. */
187	#define SVM_EXIT_IRET 0x74
188	/** software interrupt (INTn instructions). */
189	#define SVM_EXIT_SWINT 0x75
190	/** INVD instruction. */
191	#define SVM_EXIT_INVD 0x76
192	/** PAUSE instruction. */
193	#define SVM_EXIT_PAUSE 0x77
194	/** HLT instruction. */
195	#define SVM_EXIT_HLT 0x78
196	/** INVLPG instructions. */
197	#define SVM_EXIT_INVLPG 0x79
198	/** INVLPGA instruction. */
199	#define SVM_EXIT_INVLPGA 0x7A
200	/** IN or OUT accessing protected port (the EXITINFO1 field provides more information). */
201	#define SVM_EXIT_IOIO 0x7B
202	/** RDMSR or WRMSR access to protected MSR. */
203	#define SVM_EXIT_MSR 0x7C
204	/** task switch. */
205	#define SVM_EXIT_TASK_SWITCH 0x7D
206	/** FP legacy handling enabled, and processor is frozen in an x87/mmx instruction waiting for an interrupt. */
207	#define SVM_EXIT_FERR_FREEZE 0x7E
208	/** Shutdown. */
209	#define SVM_EXIT_SHUTDOWN 0x7F
210	/** VMRUN instruction. */
211	#define SVM_EXIT_VMRUN 0x80
212	/** VMMCALL instruction. */
213	#define SVM_EXIT_VMMCALL 0x81
214	/** VMLOAD instruction. */
215	#define SVM_EXIT_VMLOAD 0x82
216	/** VMSAVE instruction. */
217	#define SVM_EXIT_VMSAVE 0x83
218	/** STGI instruction. */
219	#define SVM_EXIT_STGI 0x84
220	/** CLGI instruction. */
221	#define SVM_EXIT_CLGI 0x85
222	/** SKINIT instruction. */
223	#define SVM_EXIT_SKINIT 0x86
224	/** RDTSCP instruction. */
225	#define SVM_EXIT_RDTSCP 0x87
226	/** ICEBP instruction. */
227	#define SVM_EXIT_ICEBP 0x88
228	/** WBINVD instruction. */
229	#define SVM_INVD 0x89
230	/** Nested paging: host-level page fault occurred (EXITINFO1 contains fault errorcode; EXITINFO2 contains the guest physical address causing the fault.). */
231	#define SVM_EXIT_NPF 0x400
232
233	/** @} */
234
235
236	/** @name SVM_VMCB.ctrl.u32InterceptCtrl1
237	* @{
238	*/
239	/* 0 Intercept INTR (physical maskable interrupt) */
240	#define SVM_CTRL1_INTERCEPT_INTR RT_BIT(0)
241	/* 1 Intercept NMI */
242	#define SVM_CTRL1_INTERCEPT_NMI RT_BIT(1)
243	/* 2 Intercept SMI */
244	#define SVM_CTRL1_INTERCEPT_SMI RT_BIT(2)
245	/* 3 Intercept INIT */
246	#define SVM_CTRL1_INTERCEPT_INIT RT_BIT(3)
247	/* 4 Intercept VINTR (virtual maskable interrupt) */
248	#define SVM_CTRL1_INTERCEPT_VINTR RT_BIT(4)
249	/* 5 Intercept CR0 writes that change bits other than CR0.TS or CR0.MP */
250	#define SVM_CTRL1_INTERCEPT_CR0 RT_BIT(5)
251	/* 6 Intercept reads of IDTR */
252	#define SVM_CTRL1_INTERCEPT_IDTR_READS RT_BIT(6)
253	/* 7 Intercept reads of GDTR */
254	#define SVM_CTRL1_INTERCEPT_GDTR_READS RT_BIT(7)
255	/* 8 Intercept reads of LDTR */
256	#define SVM_CTRL1_INTERCEPT_LDTR_READS RT_BIT(8)
257	/* 9 Intercept reads of TR */
258	#define SVM_CTRL1_INTERCEPT_TR_READS RT_BIT(9)
259	/* 10 Intercept writes of IDTR */
260	#define SVM_CTRL1_INTERCEPT_IDTR_WRITES RT_BIT(10)
261	/* 11 Intercept writes of GDTR */
262	#define SVM_CTRL1_INTERCEPT_GDTR_WRITES RT_BIT(11)
263	/* 12 Intercept writes of LDTR */
264	#define SVM_CTRL1_INTERCEPT_LDTR_WRITES RT_BIT(12)
265	/* 13 Intercept writes of TR */
266	#define SVM_CTRL1_INTERCEPT_TR_WRITES RT_BIT(13)
267	/* 14 Intercept RDTSC instruction */
268	#define SVM_CTRL1_INTERCEPT_RDTSC RT_BIT(14)
269	/* 15 Intercept RDPMC instruction */
270	#define SVM_CTRL1_INTERCEPT_RDPMC RT_BIT(15)
271	/* 16 Intercept PUSHF instruction */
272	#define SVM_CTRL1_INTERCEPT_PUSHF RT_BIT(16)
273	/* 17 Intercept POPF instruction */
274	#define SVM_CTRL1_INTERCEPT_POPF RT_BIT(17)
275	/* 18 Intercept CPUID instruction */
276	#define SVM_CTRL1_INTERCEPT_CPUID RT_BIT(18)
277	/* 19 Intercept RSM instruction */
278	#define SVM_CTRL1_INTERCEPT_RSM RT_BIT(19)
279	/* 20 Intercept IRET instruction */
280	#define SVM_CTRL1_INTERCEPT_IRET RT_BIT(20)
281	/* 21 Intercept INTn instruction */
282	#define SVM_CTRL1_INTERCEPT_INTN RT_BIT(21)
283	/* 22 Intercept INVD instruction */
284	#define SVM_CTRL1_INTERCEPT_INVD RT_BIT(22)
285	/* 23 Intercept PAUSE instruction */
286	#define SVM_CTRL1_INTERCEPT_PAUSE RT_BIT(23)
287	/* 24 Intercept HLT instruction */
288	#define SVM_CTRL1_INTERCEPT_HLT RT_BIT(24)
289	/* 25 Intercept INVLPG instruction */
290	#define SVM_CTRL1_INTERCEPT_INVLPG RT_BIT(25)
291	/* 26 Intercept INVLPGA instruction */
292	#define SVM_CTRL1_INTERCEPT_INVLPGA RT_BIT(26)
293	/* 27 IOIO_PROT Intercept IN/OUT accesses to selected ports. */
294	#define SVM_CTRL1_INTERCEPT_INOUT_BITMAP RT_BIT(27)
295	/* 28 MSR_PROT Intercept RDMSR or WRMSR accesses to selected MSRs. */
296	#define SVM_CTRL1_INTERCEPT_MSR_SHADOW RT_BIT(28)
297	/* 29 Intercept task switches. */
298	#define SVM_CTRL1_INTERCEPT_TASK_SWITCH RT_BIT(29)
299	/* 30 FERR_FREEZE: intercept processor "freezing" during legacy FERR handling. */
300	#define SVM_CTRL1_INTERCEPT_FERR_FREEZE RT_BIT(30)
301	/* 31 Intercept shutdown events. */
302	#define SVM_CTRL1_INTERCEPT_SHUTDOWN RT_BIT(31)
303	/** @} */
304
305
306	/** @name SVM_VMCB.ctrl.u32InterceptCtrl2
307	* @{
308	*/
309	/* 0 Intercept VMRUN instruction */
310	#define SVM_CTRL2_INTERCEPT_VMRUN RT_BIT(0)
311	/* 1 Intercept VMMCALL instruction */
312	#define SVM_CTRL2_INTERCEPT_VMMCALL RT_BIT(1)
313	/* 2 Intercept VMLOAD instruction */
314	#define SVM_CTRL2_INTERCEPT_VMLOAD RT_BIT(2)
315	/* 3 Intercept VMSAVE instruction */
316	#define SVM_CTRL2_INTERCEPT_VMSAVE RT_BIT(3)
317	/* 4 Intercept STGI instruction */
318	#define SVM_CTRL2_INTERCEPT_STGI RT_BIT(4)
319	/* 5 Intercept CLGI instruction */
320	#define SVM_CTRL2_INTERCEPT_CLGI RT_BIT(5)
321	/* 6 Intercept SKINIT instruction */
322	#define SVM_CTRL2_INTERCEPT_SKINIT RT_BIT(6)
323	/* 7 Intercept RDTSCP instruction */
324	#define SVM_CTRL2_INTERCEPT_RDTSCP RT_BIT(7)
325	/* 8 Intercept ICEBP instruction */
326	#define SVM_CTRL2_INTERCEPT_ICEBP RT_BIT(8)
327	/* 9 Intercept WBINVD instruction */
328	#define SVM_CTRL2_INTERCEPT_WBINVD RT_BIT(9)
329	/** @} */
330
331	/** @name SVM_VMCB.ctrl.u64NestedPaging
332	* @{
333	*/
334	#define SVM_NESTED_PAGING_ENABLE RT_BIT(0)
335	/** @} */
336
337	/** @name SVM_VMCB.ctrl.u64IntShadow
338	* @{
339	*/
340	#define SVM_INTERRUPT_SHADOW_ACTIVE RT_BIT(0)
341	/** @} */
342
343
344	/** @name SVM_INTCTRL.u3Type
345	* @{
346	*/
347	/** External or virtual interrupt. */
348	#define SVM_EVENT_EXTERNAL_IRQ 0
349	/** Non-maskable interrupt. */
350	#define SVM_EVENT_NMI 1
351	/** Exception; fault or trap. */
352	#define SVM_EVENT_EXCEPTION 3
353	/** Software interrupt. */
354	#define SVM_EVENT_SOFTWARE_INT 4
355	/** @} */
356
357
358
359
360	/**
361	* SVM Selector type; includes hidden parts
362	*/
363	#pragma pack(1)
364	typedef struct
365	{
366	uint16_t u16Sel;
367	uint16_t u16Attr;
368	uint32_t u32Limit;
369	uint64_t u64Base; /* Only lower 32 bits are implemented for CS, DS, ES & SS. */
370	} SVMSEL;
371	#pragma pack()
372
373	/**
374	* SVM GDTR/IDTR type
375	*/
376	#pragma pack(1)
377	typedef struct
378	{
379	uint16_t u16Reserved1;
380	uint16_t u16Reserved2;
381	uint32_t u32Limit; /* Only lower 16 bits are implemented. */
382	uint64_t u64Base;
383	} SVMGDTR;
384	#pragma pack()
385
386	typedef SVMGDTR SVMIDTR;
387
388	/**
389	* SVM Event injection structure
390	*/
391	#pragma pack(1)
392	typedef union
393	{
394	struct
395	{
396	uint32_t u8Vector : 8;
397	uint32_t u3Type : 3;
398	uint32_t u1ErrorCodeValid : 1;
399	uint32_t u19Reserved : 19;
400	uint32_t u1Valid : 1;
401	uint32_t u32ErrorCode : 32;
402	} n;
403	uint64_t au64[1];
404	} SVM_EVENT;
405	#pragma pack()
406
407
408	/**
409	* SVM Interrupt control structure
410	*/
411	#pragma pack(1)
412	typedef union
413	{
414	struct
415	{
416	uint32_t u8VTPR : 8;
417	uint32_t u1VIrqValid : 1;
418	uint32_t u7Reserved : 7;
419	uint32_t u4VIrqPriority : 4;
420	uint32_t u1IgnoreTPR : 1;
421	uint32_t u3Reserved : 3;
422	uint32_t u1VIrqMasking : 1;
423	uint32_t u7Reserved2 : 7;
424	uint32_t u8VIrqVector : 8;
425	uint32_t u24Reserved : 24;
426	} n;
427	uint64_t au64[1];
428	} SVM_INTCTRL;
429	#pragma pack()
430
431
432	/**
433	* SVM TLB control structure
434	*/
435	#pragma pack(1)
436	typedef union
437	{
438	struct
439	{
440	uint32_t u32ASID : 32;
441	uint32_t u1TLBFlush : 1;
442	uint32_t u7Reserved : 7;
443	uint32_t u24Reserved : 24;
444	} n;
445	uint64_t au64[1];
446	} SVM_TLBCTRL;
447	#pragma pack()
448
449
450	/**
451	* SVM IOIO exit structure
452	*/
453	#pragma pack(1)
454	typedef union
455	{
456	struct
457	{
458	uint32_t u1Type : 1; /* 0 = out, 1 = in */
459	uint32_t u1Reserved : 1;
460	uint32_t u1STR : 1;
461	uint32_t u1REP : 1;
462	uint32_t u1OP8 : 1;
463	uint32_t u1OP16 : 1;
464	uint32_t u1OP32 : 1;
465	uint32_t u1ADDR16 : 1;
466	uint32_t u1ADDR32 : 1;
467	uint32_t u1ADDR64 : 1;
468	uint32_t u6Reserved : 6;
469	uint32_t u16Port : 16;
470	} n;
471	uint32_t au32[1];
472	} SVM_IOIO_EXIT;
473	#pragma pack()
474
475
476	/**
477	* SVM VM Control Block. (VMCB)
478	*/
479	#pragma pack(1)
480	typedef struct _SVM_VMCB
481	{
482	/** Control Area. */
483	struct
484	{
485	/** Offset 0x00 - Intercept reads of CR0-15. */
486	uint16_t u16InterceptRdCRx;
487	/** Offset 0x02 - Intercept writes to CR0-15. */
488	uint16_t u16InterceptWrCRx;
489	/** Offset 0x04 - Intercept reads of DR0-15. */
490	uint16_t u16InterceptRdDRx;
491	/** Offset 0x06 - Intercept writes to DR0-15. */
492	uint16_t u16InterceptWrDRx;
493	/** Offset 0x08 - Intercept exception vectors 0-31. */
494	uint32_t u32InterceptException;
495	/** Offset 0x0C - Intercept control field 1. */
496	uint32_t u32InterceptCtrl1;
497	/** Offset 0x0C - Intercept control field 2. */
498	uint32_t u32InterceptCtrl2;
499	/** Offset 0x14-0x3F - Reserved. */
500	uint8_t u8Reserved[0x40-0x14];
501	/** Offset 0x40 - Physical address of IOPM. */
502	uint64_t u64IOPMPhysAddr;
503	/** Offset 0x48 - Physical address of MSRPM. */
504	uint64_t u64MSRPMPhysAddr;
505	/** Offset 0x50 - TSC Offset. */
506	uint64_t u64TSCOffset;
507	/** Offset 0x58 - TLB control field. */
508	SVM_TLBCTRL TLBCtrl;
509	/** Offset 0x60 - Interrupt control field. */
510	SVM_INTCTRL IntCtrl;
511	/** Offset 0x68 - Interrupt shadow. */
512	uint64_t u64IntShadow;
513	/** Offset 0x70 - Exit code. */
514	uint64_t u64ExitCode;
515	/** Offset 0x78 - Exit info 1. */
516	uint64_t u64ExitInfo1;
517	/** Offset 0x80 - Exit info 2. */
518	uint64_t u64ExitInfo2;
519	/** Offset 0x88 - Exit Interrupt info. */
520	SVM_EVENT ExitIntInfo;
521	/** Offset 0x90 - Nested Paging. */
522	uint64_t u64NestedPaging;
523	/** Offset 0x98-0xA7 - Reserved. */
524	uint8_t u8Reserved2[0xA8-0x98];
525	/** Offset 0xA8 - Event injection. */
526	SVM_EVENT EventInject;
527	/** Offset 0xB0 - Host CR3 for nested paging. */
528	uint64_t u64HostCR3;
529	/** Offset 0xB8 - LBR Virtualization. */
530	uint64_t u64LBRVirt;
531	} ctrl;
532
533	/** Offset 0xC0-0x3FF - Reserved. */
534	uint8_t u8Reserved3[0x400-0xC0];
535
536	/* State Save Area. Starts at offset 0x400. */
537	struct
538	{
539	/** Offset 0x400 - Guest ES register + hidden parts. */
540	SVMSEL ES;
541	/** Offset 0x410 - Guest CS register + hidden parts. */
542	SVMSEL CS;
543	/** Offset 0x420 - Guest SS register + hidden parts. */
544	SVMSEL SS;
545	/** Offset 0x430 - Guest DS register + hidden parts. */
546	SVMSEL DS;
547	/** Offset 0x440 - Guest FS register + hidden parts. */
548	SVMSEL FS;
549	/** Offset 0x450 - Guest GS register + hidden parts. */
550	SVMSEL GS;
551	/** Offset 0x460 - Guest GDTR register. */
552	SVMGDTR GDTR;
553	/** Offset 0x470 - Guest LDTR register + hidden parts. */
554	SVMSEL LDTR;
555	/** Offset 0x480 - Guest IDTR register. */
556	SVMIDTR IDTR;
557	/** Offset 0x490 - Guest TR register + hidden parts. */
558	SVMSEL TR;
559	/** Offset 0x4A0-0x4CA - Reserved. */
560	uint8_t u8Reserved4[0x4CB-0x4A0];
561	/** Offset 0x4CB - CPL. */
562	uint8_t u8CPL;
563	/** Offset 0x4CC-0x4CF - Reserved. */
564	uint8_t u8Reserved5[0x4D0-0x4CC];
565	/** Offset 0x4D0 - EFER. */
566	uint64_t u64EFER;
567	/** Offset 0x4D8-0x547 - Reserved. */
568	uint8_t u8Reserved6[0x548-0x4D8];
569	/** Offset 0x548 - CR4. */
570	uint64_t u64CR4;
571	/** Offset 0x550 - CR3. */
572	uint64_t u64CR3;
573	/** Offset 0x558 - CR0. */
574	uint64_t u64CR0;
575	/** Offset 0x560 - DR7. */
576	uint64_t u64DR7;
577	/** Offset 0x568 - DR6. */
578	uint64_t u64DR6;
579	/** Offset 0x570 - RFLAGS. */
580	uint64_t u64RFlags;
581	/** Offset 0x578 - RIP. */
582	uint64_t u64RIP;
583	/** Offset 0x580-0x5D7 - Reserved. */
584	uint8_t u8Reserved7[0x5D8-0x580];
585	/** Offset 0x5D8 - RSP. */
586	uint64_t u64RSP;
587	/** Offset 0x5E0-0x5F7 - Reserved. */
588	uint8_t u8Reserved8[0x5F8-0x5E0];
589	/** Offset 0x5F8 - RAX. */
590	uint64_t u64RAX;
591	/** Offset 0x600 - STAR. */
592	uint64_t u64STAR;
593	/** Offset 0x608 - LSTAR. */
594	uint64_t u64LSTAR;
595	/** Offset 0x610 - CSTAR. */
596	uint64_t u64CSTAR;
597	/** Offset 0x618 - SFMASK. */
598	uint64_t u64SFMASK;
599	/** Offset 0x620 - KernelGSBase. */
600	uint64_t u64KernelGSBase;
601	/** Offset 0x628 - SYSENTER_CS. */
602	uint64_t u64SysEnterCS;
603	/** Offset 0x630 - SYSENTER_ESP. */
604	uint64_t u64SysEnterESP;
605	/** Offset 0x638 - SYSENTER_EIP. */
606	uint64_t u64SysEnterEIP;
607	/** Offset 0x640 - CR2. */
608	uint64_t u64CR2;
609	/** Offset 0x648-0x667 - Reserved. */
610	uint8_t u8Reserved9[0x668-0x648];
611	/** Offset 0x668 - G_PAT. */
612	uint64_t u64GPAT;
613	/** Offset 0x670 - DBGCTL. */
614	uint64_t u64DBGCTL;
615	/** Offset 0x678 - BR_FROM. */
616	uint64_t u64BR_FROM;
617	/** Offset 0x680 - BR_TO. */
618	uint64_t u64BR_TO;
619	/** Offset 0x688 - LASTEXCPFROM. */
620	uint64_t u64LASTEXCPFROM;
621	/** Offset 0x690 - LASTEXCPTO. */
622	uint64_t u64LASTEXCPTO;
623	} guest;
624
625	/** Offset 0x698-0xFFF- Reserved. */
626	uint8_t u8Reserved10[0x1000-0x698];
627	} SVM_VMCB;
628	#pragma pack()
629
630
631	/**
632	* Prepares for and executes VMRUN.
633	*
634	* @returns VBox status code.
635	* @param pVMCBHostPhys Physical address of host VMCB.
636	* @param pVMCBPhys Physical address of the VMCB.
637	* @param pCtx Guest context.
638	*/
639	DECLASM(int) SVMVMRun(RTHCPHYS pVMCBHostPhys, RTHCPHYS pVMCBPhys, PCPUMCTX pCtx);
640
641	/**
642	* Executes INVLPGA.
643	*
644	* @param pPageGC Virtual page to invalidate.
645	* @param u32ASID Tagged TLB id.
646	*/
647	DECLASM(void) SVMInvlpgA(RTGCPTR pPageGC, uint32_t u32ASID);
648
649	/** @} */
650
651	#endif
652

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source: vbox/trunk/include/VBox/hwacc_svm.h@ 8113

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