1 | /** @file
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2 | * HWACCM - SVM Structures and Definitions. (VMM)
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3 | */
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4 |
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5 | /*
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6 | * Copyright (C) 2006-2007 Sun Microsystems, Inc.
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7 | *
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8 | * This file is part of VirtualBox Open Source Edition (OSE), as
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9 | * available from http://www.virtualbox.org. This file is free software;
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10 | * you can redistribute it and/or modify it under the terms of the GNU
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11 | * General Public License (GPL) as published by the Free Software
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12 | * Foundation, in version 2 as it comes in the "COPYING" file of the
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13 | * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
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14 | * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
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15 | *
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16 | * The contents of this file may alternatively be used under the terms
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17 | * of the Common Development and Distribution License Version 1.0
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18 | * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
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19 | * VirtualBox OSE distribution, in which case the provisions of the
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20 | * CDDL are applicable instead of those of the GPL.
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21 | *
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22 | * You may elect to license modified versions of this file under the
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23 | * terms and conditions of either the GPL or the CDDL or both.
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24 | *
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25 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
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26 | * Clara, CA 95054 USA or visit http://www.sun.com if you need
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27 | * additional information or have any questions.
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28 | */
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29 |
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30 | #ifndef ___VBox_svm_h
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31 | #define ___VBox_svm_h
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32 |
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33 | #include <VBox/types.h>
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34 | #include <VBox/err.h>
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35 | #include <iprt/assert.h>
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36 | #include <iprt/asm.h>
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37 |
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38 | /** @defgroup grp_svm svm Types and Definitions
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39 | * @ingroup grp_hwaccm
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40 | * @{
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41 | */
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42 |
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43 | /** @name SVM features for cpuid 0x8000000a
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44 | * @{
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45 | */
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46 | #define AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING RT_BIT(0)
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47 | #define AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT RT_BIT(1)
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48 | #define AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK RT_BIT(2)
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49 | #define AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE RT_BIT(3)
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50 | #define AMD_CPUID_SVM_FEATURE_EDX_SSE_3_5_DISABLE RT_BIT(9)
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51 | /** @} */
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52 |
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53 |
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54 | /** @name SVM Basic Exit Reasons.
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55 | * @{
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56 | */
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57 | /** Invalid guest state in VMCB. */
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58 | #define SVM_EXIT_INVALID -1
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59 | /** Read from CR0-CR15. */
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60 | #define SVM_EXIT_READ_CR0 0x0
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61 | #define SVM_EXIT_READ_CR1 0x1
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62 | #define SVM_EXIT_READ_CR2 0x2
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63 | #define SVM_EXIT_READ_CR3 0x3
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64 | #define SVM_EXIT_READ_CR4 0x4
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65 | #define SVM_EXIT_READ_CR5 0x5
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66 | #define SVM_EXIT_READ_CR6 0x6
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67 | #define SVM_EXIT_READ_CR7 0x7
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68 | #define SVM_EXIT_READ_CR8 0x8
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69 | #define SVM_EXIT_READ_CR9 0x9
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70 | #define SVM_EXIT_READ_CR10 0xA
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71 | #define SVM_EXIT_READ_CR11 0xB
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72 | #define SVM_EXIT_READ_CR12 0xC
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73 | #define SVM_EXIT_READ_CR13 0xD
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74 | #define SVM_EXIT_READ_CR14 0xE
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75 | #define SVM_EXIT_READ_CR15 0xF
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76 | /** Writes to CR0-CR15. */
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77 | #define SVM_EXIT_WRITE_CR0 0x10
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78 | #define SVM_EXIT_WRITE_CR1 0x11
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79 | #define SVM_EXIT_WRITE_CR2 0x12
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80 | #define SVM_EXIT_WRITE_CR3 0x13
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81 | #define SVM_EXIT_WRITE_CR4 0x14
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82 | #define SVM_EXIT_WRITE_CR5 0x15
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83 | #define SVM_EXIT_WRITE_CR6 0x16
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84 | #define SVM_EXIT_WRITE_CR7 0x17
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85 | #define SVM_EXIT_WRITE_CR8 0x18
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86 | #define SVM_EXIT_WRITE_CR9 0x19
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87 | #define SVM_EXIT_WRITE_CR10 0x1A
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88 | #define SVM_EXIT_WRITE_CR11 0x1B
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89 | #define SVM_EXIT_WRITE_CR12 0x1C
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90 | #define SVM_EXIT_WRITE_CR13 0x1D
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91 | #define SVM_EXIT_WRITE_CR14 0x1E
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92 | #define SVM_EXIT_WRITE_CR15 0x1F
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93 | /** Read from DR0-DR15. */
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94 | #define SVM_EXIT_READ_DR0 0x20
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95 | #define SVM_EXIT_READ_DR1 0x21
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96 | #define SVM_EXIT_READ_DR2 0x22
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97 | #define SVM_EXIT_READ_DR3 0x23
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98 | #define SVM_EXIT_READ_DR4 0x24
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99 | #define SVM_EXIT_READ_DR5 0x25
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100 | #define SVM_EXIT_READ_DR6 0x26
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101 | #define SVM_EXIT_READ_DR7 0x27
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102 | #define SVM_EXIT_READ_DR8 0x28
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103 | #define SVM_EXIT_READ_DR9 0x29
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104 | #define SVM_EXIT_READ_DR10 0x2A
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105 | #define SVM_EXIT_READ_DR11 0x2B
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106 | #define SVM_EXIT_READ_DR12 0x2C
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107 | #define SVM_EXIT_READ_DR13 0x2D
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108 | #define SVM_EXIT_READ_DR14 0x2E
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109 | #define SVM_EXIT_READ_DR15 0x2F
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110 | /** Writes to DR0-DR15. */
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111 | #define SVM_EXIT_WRITE_DR0 0x30
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112 | #define SVM_EXIT_WRITE_DR1 0x31
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113 | #define SVM_EXIT_WRITE_DR2 0x32
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114 | #define SVM_EXIT_WRITE_DR3 0x33
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115 | #define SVM_EXIT_WRITE_DR4 0x34
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116 | #define SVM_EXIT_WRITE_DR5 0x35
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117 | #define SVM_EXIT_WRITE_DR6 0x36
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118 | #define SVM_EXIT_WRITE_DR7 0x37
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119 | #define SVM_EXIT_WRITE_DR8 0x38
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120 | #define SVM_EXIT_WRITE_DR9 0x39
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121 | #define SVM_EXIT_WRITE_DR10 0x3A
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122 | #define SVM_EXIT_WRITE_DR11 0x3B
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123 | #define SVM_EXIT_WRITE_DR12 0x3C
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124 | #define SVM_EXIT_WRITE_DR13 0x3D
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125 | #define SVM_EXIT_WRITE_DR14 0x3E
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126 | #define SVM_EXIT_WRITE_DR15 0x3F
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127 | /* Exception 0-31. */
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128 | #define SVM_EXIT_EXCEPTION_0 0x40
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129 | #define SVM_EXIT_EXCEPTION_1 0x41
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130 | #define SVM_EXIT_EXCEPTION_2 0x42
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131 | #define SVM_EXIT_EXCEPTION_3 0x43
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132 | #define SVM_EXIT_EXCEPTION_4 0x44
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133 | #define SVM_EXIT_EXCEPTION_5 0x45
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134 | #define SVM_EXIT_EXCEPTION_6 0x46
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135 | #define SVM_EXIT_EXCEPTION_7 0x47
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136 | #define SVM_EXIT_EXCEPTION_8 0x48
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137 | #define SVM_EXIT_EXCEPTION_9 0x49
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138 | #define SVM_EXIT_EXCEPTION_A 0x4A
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139 | #define SVM_EXIT_EXCEPTION_B 0x4B
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140 | #define SVM_EXIT_EXCEPTION_C 0x4C
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141 | #define SVM_EXIT_EXCEPTION_D 0x4D
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142 | #define SVM_EXIT_EXCEPTION_E 0x4E
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143 | #define SVM_EXIT_EXCEPTION_F 0x4F
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144 | #define SVM_EXIT_EXCEPTION_10 0x50
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145 | #define SVM_EXIT_EXCEPTION_11 0x51
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146 | #define SVM_EXIT_EXCEPTION_12 0x52
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147 | #define SVM_EXIT_EXCEPTION_13 0x53
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148 | #define SVM_EXIT_EXCEPTION_14 0x54
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149 | #define SVM_EXIT_EXCEPTION_15 0x55
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150 | #define SVM_EXIT_EXCEPTION_16 0x56
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151 | #define SVM_EXIT_EXCEPTION_17 0x57
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152 | #define SVM_EXIT_EXCEPTION_18 0x58
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153 | #define SVM_EXIT_EXCEPTION_19 0x59
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154 | #define SVM_EXIT_EXCEPTION_1A 0x5A
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155 | #define SVM_EXIT_EXCEPTION_1B 0x5B
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156 | #define SVM_EXIT_EXCEPTION_1C 0x5C
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157 | #define SVM_EXIT_EXCEPTION_1D 0x5D
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158 | #define SVM_EXIT_EXCEPTION_1E 0x5E
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159 | #define SVM_EXIT_EXCEPTION_1F 0x5F
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160 | /** Physical maskable interrupt. */
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161 | #define SVM_EXIT_INTR 0x60
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162 | /** Non-maskable interrupt. */
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163 | #define SVM_EXIT_NMI 0x61
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164 | /** System Management interrupt. */
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165 | #define SVM_EXIT_SMI 0x62
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166 | /** Physical INIT signal. */
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167 | #define SVM_EXIT_INIT 0x63
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168 | /** Virtual interrupt. */
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169 | #define SVM_EXIT_VINTR 0x64
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170 | /** Write to CR0 that changed any bits other than CR0.TS or CR0.MP. */
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171 | #define SVM_EXIT_CR0_SEL_WRITE 0x65
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172 | /** IDTR read. */
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173 | #define SVM_EXIT_IDTR_READ 0x66
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174 | /** GDTR read. */
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175 | #define SVM_EXIT_GDTR_READ 0x67
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176 | /** LDTR read. */
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177 | #define SVM_EXIT_LDTR_READ 0x68
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178 | /** TR read. */
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179 | #define SVM_EXIT_TR_READ 0x69
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180 | /** IDTR write. */
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181 | #define SVM_EXIT_IDTR_WRITE 0x6A
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182 | /** GDTR write. */
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183 | #define SVM_EXIT_GDTR_WRITE 0x6B
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184 | /** LDTR write. */
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185 | #define SVM_EXIT_LDTR_WRITE 0x6C
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186 | /** TR write. */
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187 | #define SVM_EXIT_TR_WRITE 0x6D
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188 | /** RDTSC instruction. */
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189 | #define SVM_EXIT_RDTSC 0x6E
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190 | /** RDPMC instruction. */
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191 | #define SVM_EXIT_RDPMC 0x6F
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192 | /** PUSHF instruction. */
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193 | #define SVM_EXIT_PUSHF 0x70
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194 | /** POPF instruction. */
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195 | #define SVM_EXIT_POPF 0x71
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196 | /** CPUID instruction. */
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197 | #define SVM_EXIT_CPUID 0x72
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198 | /** RSM instruction. */
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199 | #define SVM_EXIT_RSM 0x73
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200 | /** IRET instruction. */
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201 | #define SVM_EXIT_IRET 0x74
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202 | /** software interrupt (INTn instructions). */
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203 | #define SVM_EXIT_SWINT 0x75
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204 | /** INVD instruction. */
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205 | #define SVM_EXIT_INVD 0x76
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206 | /** PAUSE instruction. */
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207 | #define SVM_EXIT_PAUSE 0x77
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208 | /** HLT instruction. */
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209 | #define SVM_EXIT_HLT 0x78
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210 | /** INVLPG instructions. */
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211 | #define SVM_EXIT_INVLPG 0x79
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212 | /** INVLPGA instruction. */
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213 | #define SVM_EXIT_INVLPGA 0x7A
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214 | /** IN or OUT accessing protected port (the EXITINFO1 field provides more information). */
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215 | #define SVM_EXIT_IOIO 0x7B
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216 | /** RDMSR or WRMSR access to protected MSR. */
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217 | #define SVM_EXIT_MSR 0x7C
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218 | /** task switch. */
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219 | #define SVM_EXIT_TASK_SWITCH 0x7D
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220 | /** FP legacy handling enabled, and processor is frozen in an x87/mmx instruction waiting for an interrupt. */
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221 | #define SVM_EXIT_FERR_FREEZE 0x7E
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222 | /** Shutdown. */
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223 | #define SVM_EXIT_SHUTDOWN 0x7F
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224 | /** VMRUN instruction. */
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225 | #define SVM_EXIT_VMRUN 0x80
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226 | /** VMMCALL instruction. */
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227 | #define SVM_EXIT_VMMCALL 0x81
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228 | /** VMLOAD instruction. */
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229 | #define SVM_EXIT_VMLOAD 0x82
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230 | /** VMSAVE instruction. */
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231 | #define SVM_EXIT_VMSAVE 0x83
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232 | /** STGI instruction. */
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233 | #define SVM_EXIT_STGI 0x84
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234 | /** CLGI instruction. */
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235 | #define SVM_EXIT_CLGI 0x85
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236 | /** SKINIT instruction. */
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237 | #define SVM_EXIT_SKINIT 0x86
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238 | /** RDTSCP instruction. */
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239 | #define SVM_EXIT_RDTSCP 0x87
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240 | /** ICEBP instruction. */
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241 | #define SVM_EXIT_ICEBP 0x88
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242 | /** WBINVD instruction. */
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243 | #define SVM_EXIT_WBINVD 0x89
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244 | /** MONITOR instruction. */
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245 | #define SVM_EXIT_MONITOR 0x8A
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246 | /** MWAIT instruction uncond. */
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247 | #define SVM_EXIT_MWAIT_UNCOND 0x8B
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248 | /** MWAIT instruction when armed. */
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249 | #define SVM_EXIT_MWAIT_ARMED 0x8C
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250 | /** Nested paging: host-level page fault occurred (EXITINFO1 contains fault errorcode; EXITINFO2 contains the guest physical address causing the fault). */
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251 | #define SVM_EXIT_NPF 0x400
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252 |
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253 | /** @} */
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254 |
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255 |
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256 | /** @name SVM_VMCB.ctrl.u32InterceptCtrl1
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257 | * @{
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258 | */
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259 | /** 0 Intercept INTR (physical maskable interrupt) */
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260 | #define SVM_CTRL1_INTERCEPT_INTR RT_BIT(0)
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261 | /** 1 Intercept NMI */
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262 | #define SVM_CTRL1_INTERCEPT_NMI RT_BIT(1)
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263 | /** 2 Intercept SMI */
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264 | #define SVM_CTRL1_INTERCEPT_SMI RT_BIT(2)
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265 | /** 3 Intercept INIT */
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266 | #define SVM_CTRL1_INTERCEPT_INIT RT_BIT(3)
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267 | /** 4 Intercept VINTR (virtual maskable interrupt) */
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268 | #define SVM_CTRL1_INTERCEPT_VINTR RT_BIT(4)
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269 | /** 5 Intercept CR0 writes that change bits other than CR0.TS or CR0.MP */
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270 | #define SVM_CTRL1_INTERCEPT_CR0 RT_BIT(5)
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271 | /** 6 Intercept reads of IDTR */
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272 | #define SVM_CTRL1_INTERCEPT_IDTR_READS RT_BIT(6)
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273 | /** 7 Intercept reads of GDTR */
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274 | #define SVM_CTRL1_INTERCEPT_GDTR_READS RT_BIT(7)
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275 | /** 8 Intercept reads of LDTR */
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276 | #define SVM_CTRL1_INTERCEPT_LDTR_READS RT_BIT(8)
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277 | /** 9 Intercept reads of TR */
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278 | #define SVM_CTRL1_INTERCEPT_TR_READS RT_BIT(9)
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279 | /** 10 Intercept writes of IDTR */
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280 | #define SVM_CTRL1_INTERCEPT_IDTR_WRITES RT_BIT(10)
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281 | /** 11 Intercept writes of GDTR */
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282 | #define SVM_CTRL1_INTERCEPT_GDTR_WRITES RT_BIT(11)
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283 | /** 12 Intercept writes of LDTR */
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284 | #define SVM_CTRL1_INTERCEPT_LDTR_WRITES RT_BIT(12)
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285 | /** 13 Intercept writes of TR */
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286 | #define SVM_CTRL1_INTERCEPT_TR_WRITES RT_BIT(13)
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287 | /** 14 Intercept RDTSC instruction */
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288 | #define SVM_CTRL1_INTERCEPT_RDTSC RT_BIT(14)
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289 | /** 15 Intercept RDPMC instruction */
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290 | #define SVM_CTRL1_INTERCEPT_RDPMC RT_BIT(15)
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291 | /** 16 Intercept PUSHF instruction */
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292 | #define SVM_CTRL1_INTERCEPT_PUSHF RT_BIT(16)
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293 | /** 17 Intercept POPF instruction */
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294 | #define SVM_CTRL1_INTERCEPT_POPF RT_BIT(17)
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295 | /** 18 Intercept CPUID instruction */
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296 | #define SVM_CTRL1_INTERCEPT_CPUID RT_BIT(18)
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297 | /** 19 Intercept RSM instruction */
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298 | #define SVM_CTRL1_INTERCEPT_RSM RT_BIT(19)
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299 | /** 20 Intercept IRET instruction */
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300 | #define SVM_CTRL1_INTERCEPT_IRET RT_BIT(20)
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301 | /** 21 Intercept INTn instruction */
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302 | #define SVM_CTRL1_INTERCEPT_INTN RT_BIT(21)
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303 | /** 22 Intercept INVD instruction */
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304 | #define SVM_CTRL1_INTERCEPT_INVD RT_BIT(22)
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305 | /** 23 Intercept PAUSE instruction */
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306 | #define SVM_CTRL1_INTERCEPT_PAUSE RT_BIT(23)
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307 | /** 24 Intercept HLT instruction */
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308 | #define SVM_CTRL1_INTERCEPT_HLT RT_BIT(24)
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309 | /** 25 Intercept INVLPG instruction */
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310 | #define SVM_CTRL1_INTERCEPT_INVLPG RT_BIT(25)
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311 | /** 26 Intercept INVLPGA instruction */
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312 | #define SVM_CTRL1_INTERCEPT_INVLPGA RT_BIT(26)
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313 | /** 27 IOIO_PROT Intercept IN/OUT accesses to selected ports. */
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314 | #define SVM_CTRL1_INTERCEPT_INOUT_BITMAP RT_BIT(27)
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315 | /** 28 MSR_PROT Intercept RDMSR or WRMSR accesses to selected MSRs. */
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316 | #define SVM_CTRL1_INTERCEPT_MSR_SHADOW RT_BIT(28)
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317 | /** 29 Intercept task switches. */
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318 | #define SVM_CTRL1_INTERCEPT_TASK_SWITCH RT_BIT(29)
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319 | /** 30 FERR_FREEZE: intercept processor "freezing" during legacy FERR handling. */
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320 | #define SVM_CTRL1_INTERCEPT_FERR_FREEZE RT_BIT(30)
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321 | /** 31 Intercept shutdown events. */
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322 | #define SVM_CTRL1_INTERCEPT_SHUTDOWN RT_BIT(31)
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323 | /** @} */
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324 |
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325 |
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326 | /** @name SVM_VMCB.ctrl.u32InterceptCtrl2
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327 | * @{
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328 | */
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329 | /** 0 Intercept VMRUN instruction */
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330 | #define SVM_CTRL2_INTERCEPT_VMRUN RT_BIT(0)
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331 | /** 1 Intercept VMMCALL instruction */
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332 | #define SVM_CTRL2_INTERCEPT_VMMCALL RT_BIT(1)
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333 | /** 2 Intercept VMLOAD instruction */
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334 | #define SVM_CTRL2_INTERCEPT_VMLOAD RT_BIT(2)
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335 | /** 3 Intercept VMSAVE instruction */
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336 | #define SVM_CTRL2_INTERCEPT_VMSAVE RT_BIT(3)
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337 | /** 4 Intercept STGI instruction */
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338 | #define SVM_CTRL2_INTERCEPT_STGI RT_BIT(4)
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339 | /** 5 Intercept CLGI instruction */
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340 | #define SVM_CTRL2_INTERCEPT_CLGI RT_BIT(5)
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341 | /** 6 Intercept SKINIT instruction */
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342 | #define SVM_CTRL2_INTERCEPT_SKINIT RT_BIT(6)
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343 | /** 7 Intercept RDTSCP instruction */
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344 | #define SVM_CTRL2_INTERCEPT_RDTSCP RT_BIT(7)
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345 | /** 8 Intercept ICEBP instruction */
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346 | #define SVM_CTRL2_INTERCEPT_ICEBP RT_BIT(8)
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347 | /** 9 Intercept WBINVD instruction */
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348 | #define SVM_CTRL2_INTERCEPT_WBINVD RT_BIT(9)
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349 | /** 10 Intercept MONITOR instruction */
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350 | #define SVM_CTRL2_INTERCEPT_MONITOR RT_BIT(10)
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351 | /** 11 Intercept MWAIT instruction unconditionally */
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352 | #define SVM_CTRL2_INTERCEPT_MWAIT_UNCOND RT_BIT(11)
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353 | /** 12 Intercept MWAIT instruction when armed */
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354 | #define SVM_CTRL2_INTERCEPT_MWAIT_ARMED RT_BIT(12)
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355 | /** @} */
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356 |
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357 | /** @name SVM_VMCB.ctrl.u64NestedPaging
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358 | * @{
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359 | */
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360 | #define SVM_NESTED_PAGING_ENABLE RT_BIT(0)
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361 | /** @} */
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362 |
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363 | /** @name SVM_VMCB.ctrl.u64IntShadow
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364 | * @{
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365 | */
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366 | #define SVM_INTERRUPT_SHADOW_ACTIVE RT_BIT(0)
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367 | /** @} */
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368 |
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369 |
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370 | /** @name SVM_INTCTRL.u3Type
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371 | * @{
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372 | */
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373 | /** External or virtual interrupt. */
|
---|
374 | #define SVM_EVENT_EXTERNAL_IRQ 0
|
---|
375 | /** Non-maskable interrupt. */
|
---|
376 | #define SVM_EVENT_NMI 2
|
---|
377 | /** Exception; fault or trap. */
|
---|
378 | #define SVM_EVENT_EXCEPTION 3
|
---|
379 | /** Software interrupt. */
|
---|
380 | #define SVM_EVENT_SOFTWARE_INT 4
|
---|
381 | /** @} */
|
---|
382 |
|
---|
383 |
|
---|
384 |
|
---|
385 |
|
---|
386 | /**
|
---|
387 | * SVM Selector type; includes hidden parts
|
---|
388 | */
|
---|
389 | #pragma pack(1)
|
---|
390 | typedef struct
|
---|
391 | {
|
---|
392 | uint16_t u16Sel;
|
---|
393 | uint16_t u16Attr;
|
---|
394 | uint32_t u32Limit;
|
---|
395 | uint64_t u64Base; /**< Only lower 32 bits are implemented for CS, DS, ES & SS. */
|
---|
396 | } SVMSEL;
|
---|
397 | #pragma pack()
|
---|
398 |
|
---|
399 | /**
|
---|
400 | * SVM GDTR/IDTR type
|
---|
401 | */
|
---|
402 | #pragma pack(1)
|
---|
403 | typedef struct
|
---|
404 | {
|
---|
405 | uint16_t u16Reserved1;
|
---|
406 | uint16_t u16Reserved2;
|
---|
407 | uint32_t u32Limit; /**< Only lower 16 bits are implemented. */
|
---|
408 | uint64_t u64Base;
|
---|
409 | } SVMGDTR;
|
---|
410 | #pragma pack()
|
---|
411 |
|
---|
412 | typedef SVMGDTR SVMIDTR;
|
---|
413 |
|
---|
414 | /**
|
---|
415 | * SVM Event injection structure
|
---|
416 | */
|
---|
417 | #pragma pack(1)
|
---|
418 | typedef union
|
---|
419 | {
|
---|
420 | struct
|
---|
421 | {
|
---|
422 | uint32_t u8Vector : 8;
|
---|
423 | uint32_t u3Type : 3;
|
---|
424 | uint32_t u1ErrorCodeValid : 1;
|
---|
425 | uint32_t u19Reserved : 19;
|
---|
426 | uint32_t u1Valid : 1;
|
---|
427 | uint32_t u32ErrorCode : 32;
|
---|
428 | } n;
|
---|
429 | uint64_t au64[1];
|
---|
430 | } SVM_EVENT;
|
---|
431 | #pragma pack()
|
---|
432 |
|
---|
433 |
|
---|
434 | /**
|
---|
435 | * SVM Interrupt control structure
|
---|
436 | */
|
---|
437 | #pragma pack(1)
|
---|
438 | typedef union
|
---|
439 | {
|
---|
440 | struct
|
---|
441 | {
|
---|
442 | uint32_t u8VTPR : 8;
|
---|
443 | uint32_t u1VIrqValid : 1;
|
---|
444 | uint32_t u7Reserved : 7;
|
---|
445 | uint32_t u4VIrqPriority : 4;
|
---|
446 | uint32_t u1IgnoreTPR : 1;
|
---|
447 | uint32_t u3Reserved : 3;
|
---|
448 | uint32_t u1VIrqMasking : 1;
|
---|
449 | uint32_t u7Reserved2 : 7;
|
---|
450 | uint32_t u8VIrqVector : 8;
|
---|
451 | uint32_t u24Reserved : 24;
|
---|
452 | } n;
|
---|
453 | uint64_t au64[1];
|
---|
454 | } SVM_INTCTRL;
|
---|
455 | #pragma pack()
|
---|
456 |
|
---|
457 |
|
---|
458 | /**
|
---|
459 | * SVM TLB control structure
|
---|
460 | */
|
---|
461 | #pragma pack(1)
|
---|
462 | typedef union
|
---|
463 | {
|
---|
464 | struct
|
---|
465 | {
|
---|
466 | uint32_t u32ASID : 32;
|
---|
467 | uint32_t u1TLBFlush : 1;
|
---|
468 | uint32_t u7Reserved : 7;
|
---|
469 | uint32_t u24Reserved : 24;
|
---|
470 | } n;
|
---|
471 | uint64_t au64[1];
|
---|
472 | } SVM_TLBCTRL;
|
---|
473 | #pragma pack()
|
---|
474 |
|
---|
475 |
|
---|
476 | /**
|
---|
477 | * SVM IOIO exit structure
|
---|
478 | */
|
---|
479 | #pragma pack(1)
|
---|
480 | typedef union
|
---|
481 | {
|
---|
482 | struct
|
---|
483 | {
|
---|
484 | uint32_t u1Type : 1; /**< 0 = out, 1 = in */
|
---|
485 | uint32_t u1Reserved : 1;
|
---|
486 | uint32_t u1STR : 1;
|
---|
487 | uint32_t u1REP : 1;
|
---|
488 | uint32_t u1OP8 : 1;
|
---|
489 | uint32_t u1OP16 : 1;
|
---|
490 | uint32_t u1OP32 : 1;
|
---|
491 | uint32_t u1ADDR16 : 1;
|
---|
492 | uint32_t u1ADDR32 : 1;
|
---|
493 | uint32_t u1ADDR64 : 1;
|
---|
494 | uint32_t u6Reserved : 6;
|
---|
495 | uint32_t u16Port : 16;
|
---|
496 | } n;
|
---|
497 | uint32_t au32[1];
|
---|
498 | } SVM_IOIO_EXIT;
|
---|
499 | #pragma pack()
|
---|
500 |
|
---|
501 | /**
|
---|
502 | * SVM nested paging structure
|
---|
503 | */
|
---|
504 | #pragma pack(1)
|
---|
505 | typedef union
|
---|
506 | {
|
---|
507 | struct
|
---|
508 | {
|
---|
509 | uint32_t u1NestedPaging : 1; /**< enabled/disabled */
|
---|
510 | } n;
|
---|
511 | uint64_t au64[1];
|
---|
512 | } SVM_NPCTRL;
|
---|
513 | #pragma pack()
|
---|
514 |
|
---|
515 | /**
|
---|
516 | * SVM VM Control Block. (VMCB)
|
---|
517 | */
|
---|
518 | #pragma pack(1)
|
---|
519 | typedef struct _SVM_VMCB
|
---|
520 | {
|
---|
521 | /** Control Area. */
|
---|
522 | struct
|
---|
523 | {
|
---|
524 | /** Offset 0x00 - Intercept reads of CR0-15. */
|
---|
525 | uint16_t u16InterceptRdCRx;
|
---|
526 | /** Offset 0x02 - Intercept writes to CR0-15. */
|
---|
527 | uint16_t u16InterceptWrCRx;
|
---|
528 | /** Offset 0x04 - Intercept reads of DR0-15. */
|
---|
529 | uint16_t u16InterceptRdDRx;
|
---|
530 | /** Offset 0x06 - Intercept writes to DR0-15. */
|
---|
531 | uint16_t u16InterceptWrDRx;
|
---|
532 | /** Offset 0x08 - Intercept exception vectors 0-31. */
|
---|
533 | uint32_t u32InterceptException;
|
---|
534 | /** Offset 0x0C - Intercept control field 1. */
|
---|
535 | uint32_t u32InterceptCtrl1;
|
---|
536 | /** Offset 0x0C - Intercept control field 2. */
|
---|
537 | uint32_t u32InterceptCtrl2;
|
---|
538 | /** Offset 0x14-0x3F - Reserved. */
|
---|
539 | uint8_t u8Reserved[0x40-0x14];
|
---|
540 | /** Offset 0x40 - Physical address of IOPM. */
|
---|
541 | uint64_t u64IOPMPhysAddr;
|
---|
542 | /** Offset 0x48 - Physical address of MSRPM. */
|
---|
543 | uint64_t u64MSRPMPhysAddr;
|
---|
544 | /** Offset 0x50 - TSC Offset. */
|
---|
545 | uint64_t u64TSCOffset;
|
---|
546 | /** Offset 0x58 - TLB control field. */
|
---|
547 | SVM_TLBCTRL TLBCtrl;
|
---|
548 | /** Offset 0x60 - Interrupt control field. */
|
---|
549 | SVM_INTCTRL IntCtrl;
|
---|
550 | /** Offset 0x68 - Interrupt shadow. */
|
---|
551 | uint64_t u64IntShadow;
|
---|
552 | /** Offset 0x70 - Exit code. */
|
---|
553 | uint64_t u64ExitCode;
|
---|
554 | /** Offset 0x78 - Exit info 1. */
|
---|
555 | uint64_t u64ExitInfo1;
|
---|
556 | /** Offset 0x80 - Exit info 2. */
|
---|
557 | uint64_t u64ExitInfo2;
|
---|
558 | /** Offset 0x88 - Exit Interrupt info. */
|
---|
559 | SVM_EVENT ExitIntInfo;
|
---|
560 | /** Offset 0x90 - Nested Paging. */
|
---|
561 | SVM_NPCTRL NestedPaging;
|
---|
562 | /** Offset 0x98-0xA7 - Reserved. */
|
---|
563 | uint8_t u8Reserved2[0xA8-0x98];
|
---|
564 | /** Offset 0xA8 - Event injection. */
|
---|
565 | SVM_EVENT EventInject;
|
---|
566 | /** Offset 0xB0 - Host CR3 for nested paging. */
|
---|
567 | uint64_t u64NestedPagingCR3;
|
---|
568 | /** Offset 0xB8 - LBR Virtualization. */
|
---|
569 | uint64_t u64LBRVirt;
|
---|
570 | } ctrl;
|
---|
571 |
|
---|
572 | /** Offset 0xC0-0x3FF - Reserved. */
|
---|
573 | uint8_t u8Reserved3[0x400-0xC0];
|
---|
574 |
|
---|
575 | /** State Save Area. Starts at offset 0x400. */
|
---|
576 | struct
|
---|
577 | {
|
---|
578 | /** Offset 0x400 - Guest ES register + hidden parts. */
|
---|
579 | SVMSEL ES;
|
---|
580 | /** Offset 0x410 - Guest CS register + hidden parts. */
|
---|
581 | SVMSEL CS;
|
---|
582 | /** Offset 0x420 - Guest SS register + hidden parts. */
|
---|
583 | SVMSEL SS;
|
---|
584 | /** Offset 0x430 - Guest DS register + hidden parts. */
|
---|
585 | SVMSEL DS;
|
---|
586 | /** Offset 0x440 - Guest FS register + hidden parts. */
|
---|
587 | SVMSEL FS;
|
---|
588 | /** Offset 0x450 - Guest GS register + hidden parts. */
|
---|
589 | SVMSEL GS;
|
---|
590 | /** Offset 0x460 - Guest GDTR register. */
|
---|
591 | SVMGDTR GDTR;
|
---|
592 | /** Offset 0x470 - Guest LDTR register + hidden parts. */
|
---|
593 | SVMSEL LDTR;
|
---|
594 | /** Offset 0x480 - Guest IDTR register. */
|
---|
595 | SVMIDTR IDTR;
|
---|
596 | /** Offset 0x490 - Guest TR register + hidden parts. */
|
---|
597 | SVMSEL TR;
|
---|
598 | /** Offset 0x4A0-0x4CA - Reserved. */
|
---|
599 | uint8_t u8Reserved4[0x4CB-0x4A0];
|
---|
600 | /** Offset 0x4CB - CPL. */
|
---|
601 | uint8_t u8CPL;
|
---|
602 | /** Offset 0x4CC-0x4CF - Reserved. */
|
---|
603 | uint8_t u8Reserved5[0x4D0-0x4CC];
|
---|
604 | /** Offset 0x4D0 - EFER. */
|
---|
605 | uint64_t u64EFER;
|
---|
606 | /** Offset 0x4D8-0x547 - Reserved. */
|
---|
607 | uint8_t u8Reserved6[0x548-0x4D8];
|
---|
608 | /** Offset 0x548 - CR4. */
|
---|
609 | uint64_t u64CR4;
|
---|
610 | /** Offset 0x550 - CR3. */
|
---|
611 | uint64_t u64CR3;
|
---|
612 | /** Offset 0x558 - CR0. */
|
---|
613 | uint64_t u64CR0;
|
---|
614 | /** Offset 0x560 - DR7. */
|
---|
615 | uint64_t u64DR7;
|
---|
616 | /** Offset 0x568 - DR6. */
|
---|
617 | uint64_t u64DR6;
|
---|
618 | /** Offset 0x570 - RFLAGS. */
|
---|
619 | uint64_t u64RFlags;
|
---|
620 | /** Offset 0x578 - RIP. */
|
---|
621 | uint64_t u64RIP;
|
---|
622 | /** Offset 0x580-0x5D7 - Reserved. */
|
---|
623 | uint8_t u8Reserved7[0x5D8-0x580];
|
---|
624 | /** Offset 0x5D8 - RSP. */
|
---|
625 | uint64_t u64RSP;
|
---|
626 | /** Offset 0x5E0-0x5F7 - Reserved. */
|
---|
627 | uint8_t u8Reserved8[0x5F8-0x5E0];
|
---|
628 | /** Offset 0x5F8 - RAX. */
|
---|
629 | uint64_t u64RAX;
|
---|
630 | /** Offset 0x600 - STAR. */
|
---|
631 | uint64_t u64STAR;
|
---|
632 | /** Offset 0x608 - LSTAR. */
|
---|
633 | uint64_t u64LSTAR;
|
---|
634 | /** Offset 0x610 - CSTAR. */
|
---|
635 | uint64_t u64CSTAR;
|
---|
636 | /** Offset 0x618 - SFMASK. */
|
---|
637 | uint64_t u64SFMASK;
|
---|
638 | /** Offset 0x620 - KernelGSBase. */
|
---|
639 | uint64_t u64KernelGSBase;
|
---|
640 | /** Offset 0x628 - SYSENTER_CS. */
|
---|
641 | uint64_t u64SysEnterCS;
|
---|
642 | /** Offset 0x630 - SYSENTER_ESP. */
|
---|
643 | uint64_t u64SysEnterESP;
|
---|
644 | /** Offset 0x638 - SYSENTER_EIP. */
|
---|
645 | uint64_t u64SysEnterEIP;
|
---|
646 | /** Offset 0x640 - CR2. */
|
---|
647 | uint64_t u64CR2;
|
---|
648 | /** Offset 0x648-0x667 - Reserved. */
|
---|
649 | uint8_t u8Reserved9[0x668-0x648];
|
---|
650 | /** Offset 0x668 - G_PAT. */
|
---|
651 | uint64_t u64GPAT;
|
---|
652 | /** Offset 0x670 - DBGCTL. */
|
---|
653 | uint64_t u64DBGCTL;
|
---|
654 | /** Offset 0x678 - BR_FROM. */
|
---|
655 | uint64_t u64BR_FROM;
|
---|
656 | /** Offset 0x680 - BR_TO. */
|
---|
657 | uint64_t u64BR_TO;
|
---|
658 | /** Offset 0x688 - LASTEXCPFROM. */
|
---|
659 | uint64_t u64LASTEXCPFROM;
|
---|
660 | /** Offset 0x690 - LASTEXCPTO. */
|
---|
661 | uint64_t u64LASTEXCPTO;
|
---|
662 | } guest;
|
---|
663 |
|
---|
664 | /** Offset 0x698-0xFFF- Reserved. */
|
---|
665 | uint8_t u8Reserved10[0x1000-0x698];
|
---|
666 | } SVM_VMCB;
|
---|
667 | #pragma pack()
|
---|
668 |
|
---|
669 | #ifdef IN_RING0
|
---|
670 | VMMR0DECL(int) SVMR0InvalidatePage(PVM pVM, PVMCPU pVCpu, RTGCPTR GCVirt);
|
---|
671 | #endif /* IN_RING0 */
|
---|
672 |
|
---|
673 | /** @} */
|
---|
674 |
|
---|
675 | #endif
|
---|
676 |
|
---|