hwacc_svm.h@ 24130

Last change on this file since 24130 was 23637, checked in by vboxsync, 15 years ago
Addition cpuid & msr values
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1	/** @file
2	* HWACCM - SVM Structures and Definitions. (VMM)
3	*/
4
5	/*
6	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
7	*
8	* This file is part of VirtualBox Open Source Edition (OSE), as
9	* available from http://www.virtualbox.org. This file is free software;
10	* you can redistribute it and/or modify it under the terms of the GNU
11	* General Public License (GPL) as published by the Free Software
12	* Foundation, in version 2 as it comes in the "COPYING" file of the
13	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15	*
16	* The contents of this file may alternatively be used under the terms
17	* of the Common Development and Distribution License Version 1.0
18	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19	* VirtualBox OSE distribution, in which case the provisions of the
20	* CDDL are applicable instead of those of the GPL.
21	*
22	* You may elect to license modified versions of this file under the
23	* terms and conditions of either the GPL or the CDDL or both.
24	*
25	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
26	* Clara, CA 95054 USA or visit http://www.sun.com if you need
27	* additional information or have any questions.
28	*/
29
30	#ifndef ___VBox_svm_h
31	#define ___VBox_svm_h
32
33	#include <VBox/types.h>
34	#include <VBox/err.h>
35	#include <iprt/assert.h>
36	#include <iprt/asm.h>
37
38	/** @defgroup grp_svm svm Types and Definitions
39	* @ingroup grp_hwaccm
40	* @{
41	*/
42
43	/** @name SVM features for cpuid 0x8000000a
44	* @{
45	*/
46	#define AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING RT_BIT(0)
47	#define AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT RT_BIT(1)
48	#define AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK RT_BIT(2)
49	#define AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE RT_BIT(3)
50	#define AMD_CPUID_SVM_FEATURE_EDX_SSE_3_5_DISABLE RT_BIT(9)
51	#define AMD_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER RT_BIT(10)
52	/** @} */
53
54
55	/** @name SVM Basic Exit Reasons.
56	* @{
57	*/
58	/** Invalid guest state in VMCB. */
59	#define SVM_EXIT_INVALID -1
60	/** Read from CR0-CR15. */
61	#define SVM_EXIT_READ_CR0 0x0
62	#define SVM_EXIT_READ_CR1 0x1
63	#define SVM_EXIT_READ_CR2 0x2
64	#define SVM_EXIT_READ_CR3 0x3
65	#define SVM_EXIT_READ_CR4 0x4
66	#define SVM_EXIT_READ_CR5 0x5
67	#define SVM_EXIT_READ_CR6 0x6
68	#define SVM_EXIT_READ_CR7 0x7
69	#define SVM_EXIT_READ_CR8 0x8
70	#define SVM_EXIT_READ_CR9 0x9
71	#define SVM_EXIT_READ_CR10 0xA
72	#define SVM_EXIT_READ_CR11 0xB
73	#define SVM_EXIT_READ_CR12 0xC
74	#define SVM_EXIT_READ_CR13 0xD
75	#define SVM_EXIT_READ_CR14 0xE
76	#define SVM_EXIT_READ_CR15 0xF
77	/** Writes to CR0-CR15. */
78	#define SVM_EXIT_WRITE_CR0 0x10
79	#define SVM_EXIT_WRITE_CR1 0x11
80	#define SVM_EXIT_WRITE_CR2 0x12
81	#define SVM_EXIT_WRITE_CR3 0x13
82	#define SVM_EXIT_WRITE_CR4 0x14
83	#define SVM_EXIT_WRITE_CR5 0x15
84	#define SVM_EXIT_WRITE_CR6 0x16
85	#define SVM_EXIT_WRITE_CR7 0x17
86	#define SVM_EXIT_WRITE_CR8 0x18
87	#define SVM_EXIT_WRITE_CR9 0x19
88	#define SVM_EXIT_WRITE_CR10 0x1A
89	#define SVM_EXIT_WRITE_CR11 0x1B
90	#define SVM_EXIT_WRITE_CR12 0x1C
91	#define SVM_EXIT_WRITE_CR13 0x1D
92	#define SVM_EXIT_WRITE_CR14 0x1E
93	#define SVM_EXIT_WRITE_CR15 0x1F
94	/** Read from DR0-DR15. */
95	#define SVM_EXIT_READ_DR0 0x20
96	#define SVM_EXIT_READ_DR1 0x21
97	#define SVM_EXIT_READ_DR2 0x22
98	#define SVM_EXIT_READ_DR3 0x23
99	#define SVM_EXIT_READ_DR4 0x24
100	#define SVM_EXIT_READ_DR5 0x25
101	#define SVM_EXIT_READ_DR6 0x26
102	#define SVM_EXIT_READ_DR7 0x27
103	#define SVM_EXIT_READ_DR8 0x28
104	#define SVM_EXIT_READ_DR9 0x29
105	#define SVM_EXIT_READ_DR10 0x2A
106	#define SVM_EXIT_READ_DR11 0x2B
107	#define SVM_EXIT_READ_DR12 0x2C
108	#define SVM_EXIT_READ_DR13 0x2D
109	#define SVM_EXIT_READ_DR14 0x2E
110	#define SVM_EXIT_READ_DR15 0x2F
111	/** Writes to DR0-DR15. */
112	#define SVM_EXIT_WRITE_DR0 0x30
113	#define SVM_EXIT_WRITE_DR1 0x31
114	#define SVM_EXIT_WRITE_DR2 0x32
115	#define SVM_EXIT_WRITE_DR3 0x33
116	#define SVM_EXIT_WRITE_DR4 0x34
117	#define SVM_EXIT_WRITE_DR5 0x35
118	#define SVM_EXIT_WRITE_DR6 0x36
119	#define SVM_EXIT_WRITE_DR7 0x37
120	#define SVM_EXIT_WRITE_DR8 0x38
121	#define SVM_EXIT_WRITE_DR9 0x39
122	#define SVM_EXIT_WRITE_DR10 0x3A
123	#define SVM_EXIT_WRITE_DR11 0x3B
124	#define SVM_EXIT_WRITE_DR12 0x3C
125	#define SVM_EXIT_WRITE_DR13 0x3D
126	#define SVM_EXIT_WRITE_DR14 0x3E
127	#define SVM_EXIT_WRITE_DR15 0x3F
128	/* Exception 0-31. */
129	#define SVM_EXIT_EXCEPTION_0 0x40
130	#define SVM_EXIT_EXCEPTION_1 0x41
131	#define SVM_EXIT_EXCEPTION_2 0x42
132	#define SVM_EXIT_EXCEPTION_3 0x43
133	#define SVM_EXIT_EXCEPTION_4 0x44
134	#define SVM_EXIT_EXCEPTION_5 0x45
135	#define SVM_EXIT_EXCEPTION_6 0x46
136	#define SVM_EXIT_EXCEPTION_7 0x47
137	#define SVM_EXIT_EXCEPTION_8 0x48
138	#define SVM_EXIT_EXCEPTION_9 0x49
139	#define SVM_EXIT_EXCEPTION_A 0x4A
140	#define SVM_EXIT_EXCEPTION_B 0x4B
141	#define SVM_EXIT_EXCEPTION_C 0x4C
142	#define SVM_EXIT_EXCEPTION_D 0x4D
143	#define SVM_EXIT_EXCEPTION_E 0x4E
144	#define SVM_EXIT_EXCEPTION_F 0x4F
145	#define SVM_EXIT_EXCEPTION_10 0x50
146	#define SVM_EXIT_EXCEPTION_11 0x51
147	#define SVM_EXIT_EXCEPTION_12 0x52
148	#define SVM_EXIT_EXCEPTION_13 0x53
149	#define SVM_EXIT_EXCEPTION_14 0x54
150	#define SVM_EXIT_EXCEPTION_15 0x55
151	#define SVM_EXIT_EXCEPTION_16 0x56
152	#define SVM_EXIT_EXCEPTION_17 0x57
153	#define SVM_EXIT_EXCEPTION_18 0x58
154	#define SVM_EXIT_EXCEPTION_19 0x59
155	#define SVM_EXIT_EXCEPTION_1A 0x5A
156	#define SVM_EXIT_EXCEPTION_1B 0x5B
157	#define SVM_EXIT_EXCEPTION_1C 0x5C
158	#define SVM_EXIT_EXCEPTION_1D 0x5D
159	#define SVM_EXIT_EXCEPTION_1E 0x5E
160	#define SVM_EXIT_EXCEPTION_1F 0x5F
161	/** Physical maskable interrupt. */
162	#define SVM_EXIT_INTR 0x60
163	/** Non-maskable interrupt. */
164	#define SVM_EXIT_NMI 0x61
165	/** System Management interrupt. */
166	#define SVM_EXIT_SMI 0x62
167	/** Physical INIT signal. */
168	#define SVM_EXIT_INIT 0x63
169	/** Virtual interrupt. */
170	#define SVM_EXIT_VINTR 0x64
171	/** Write to CR0 that changed any bits other than CR0.TS or CR0.MP. */
172	#define SVM_EXIT_CR0_SEL_WRITE 0x65
173	/** IDTR read. */
174	#define SVM_EXIT_IDTR_READ 0x66
175	/** GDTR read. */
176	#define SVM_EXIT_GDTR_READ 0x67
177	/** LDTR read. */
178	#define SVM_EXIT_LDTR_READ 0x68
179	/** TR read. */
180	#define SVM_EXIT_TR_READ 0x69
181	/** IDTR write. */
182	#define SVM_EXIT_IDTR_WRITE 0x6A
183	/** GDTR write. */
184	#define SVM_EXIT_GDTR_WRITE 0x6B
185	/** LDTR write. */
186	#define SVM_EXIT_LDTR_WRITE 0x6C
187	/** TR write. */
188	#define SVM_EXIT_TR_WRITE 0x6D
189	/** RDTSC instruction. */
190	#define SVM_EXIT_RDTSC 0x6E
191	/** RDPMC instruction. */
192	#define SVM_EXIT_RDPMC 0x6F
193	/** PUSHF instruction. */
194	#define SVM_EXIT_PUSHF 0x70
195	/** POPF instruction. */
196	#define SVM_EXIT_POPF 0x71
197	/** CPUID instruction. */
198	#define SVM_EXIT_CPUID 0x72
199	/** RSM instruction. */
200	#define SVM_EXIT_RSM 0x73
201	/** IRET instruction. */
202	#define SVM_EXIT_IRET 0x74
203	/** software interrupt (INTn instructions). */
204	#define SVM_EXIT_SWINT 0x75
205	/** INVD instruction. */
206	#define SVM_EXIT_INVD 0x76
207	/** PAUSE instruction. */
208	#define SVM_EXIT_PAUSE 0x77
209	/** HLT instruction. */
210	#define SVM_EXIT_HLT 0x78
211	/** INVLPG instructions. */
212	#define SVM_EXIT_INVLPG 0x79
213	/** INVLPGA instruction. */
214	#define SVM_EXIT_INVLPGA 0x7A
215	/** IN or OUT accessing protected port (the EXITINFO1 field provides more information). */
216	#define SVM_EXIT_IOIO 0x7B
217	/** RDMSR or WRMSR access to protected MSR. */
218	#define SVM_EXIT_MSR 0x7C
219	/** task switch. */
220	#define SVM_EXIT_TASK_SWITCH 0x7D
221	/** FP legacy handling enabled, and processor is frozen in an x87/mmx instruction waiting for an interrupt. */
222	#define SVM_EXIT_FERR_FREEZE 0x7E
223	/** Shutdown. */
224	#define SVM_EXIT_SHUTDOWN 0x7F
225	/** VMRUN instruction. */
226	#define SVM_EXIT_VMRUN 0x80
227	/** VMMCALL instruction. */
228	#define SVM_EXIT_VMMCALL 0x81
229	/** VMLOAD instruction. */
230	#define SVM_EXIT_VMLOAD 0x82
231	/** VMSAVE instruction. */
232	#define SVM_EXIT_VMSAVE 0x83
233	/** STGI instruction. */
234	#define SVM_EXIT_STGI 0x84
235	/** CLGI instruction. */
236	#define SVM_EXIT_CLGI 0x85
237	/** SKINIT instruction. */
238	#define SVM_EXIT_SKINIT 0x86
239	/** RDTSCP instruction. */
240	#define SVM_EXIT_RDTSCP 0x87
241	/** ICEBP instruction. */
242	#define SVM_EXIT_ICEBP 0x88
243	/** WBINVD instruction. */
244	#define SVM_EXIT_WBINVD 0x89
245	/** MONITOR instruction. */
246	#define SVM_EXIT_MONITOR 0x8A
247	/** MWAIT instruction uncond. */
248	#define SVM_EXIT_MWAIT_UNCOND 0x8B
249	/** MWAIT instruction when armed. */
250	#define SVM_EXIT_MWAIT_ARMED 0x8C
251	/** Nested paging: host-level page fault occurred (EXITINFO1 contains fault errorcode; EXITINFO2 contains the guest physical address causing the fault). */
252	#define SVM_EXIT_NPF 0x400
253
254	/** @} */
255
256
257	/** @name SVM_VMCB.u64ExitInfo2
258	* @{
259	*/
260	/** Set to 1 if the task switch was caused by an IRET; else cleared to 0. */
261	#define SVM_EXIT2_TASK_SWITCH_IRET RT_BIT_64(36)
262	/** Set to 1 if the task switch was caused by a far jump; else cleared to 0. */
263	#define SVM_EXIT2_TASK_SWITCH_JMP RT_BIT_64(38)
264	/** Set to 1 if the task switch has an error code; else cleared to 0. */
265	#define SVM_EXIT2_TASK_SWITCH_HAS_ERROR_CODE RT_BIT_64(44)
266	/** The value of EFLAGS.RF that would be saved in the outgoing TSS if the task switch were not intercepted. */
267	#define SVM_EXIT2_TASK_SWITCH_EFLAGS_RF RT_BIT_64(48)
268	/** @} */
269
270	/** @name SVM_VMCB.ctrl.u32InterceptCtrl1
271	* @{
272	*/
273	/** 0 Intercept INTR (physical maskable interrupt) */
274	#define SVM_CTRL1_INTERCEPT_INTR RT_BIT(0)
275	/** 1 Intercept NMI */
276	#define SVM_CTRL1_INTERCEPT_NMI RT_BIT(1)
277	/** 2 Intercept SMI */
278	#define SVM_CTRL1_INTERCEPT_SMI RT_BIT(2)
279	/** 3 Intercept INIT */
280	#define SVM_CTRL1_INTERCEPT_INIT RT_BIT(3)
281	/** 4 Intercept VINTR (virtual maskable interrupt) */
282	#define SVM_CTRL1_INTERCEPT_VINTR RT_BIT(4)
283	/** 5 Intercept CR0 writes that change bits other than CR0.TS or CR0.MP */
284	#define SVM_CTRL1_INTERCEPT_CR0 RT_BIT(5)
285	/** 6 Intercept reads of IDTR */
286	#define SVM_CTRL1_INTERCEPT_IDTR_READS RT_BIT(6)
287	/** 7 Intercept reads of GDTR */
288	#define SVM_CTRL1_INTERCEPT_GDTR_READS RT_BIT(7)
289	/** 8 Intercept reads of LDTR */
290	#define SVM_CTRL1_INTERCEPT_LDTR_READS RT_BIT(8)
291	/** 9 Intercept reads of TR */
292	#define SVM_CTRL1_INTERCEPT_TR_READS RT_BIT(9)
293	/** 10 Intercept writes of IDTR */
294	#define SVM_CTRL1_INTERCEPT_IDTR_WRITES RT_BIT(10)
295	/** 11 Intercept writes of GDTR */
296	#define SVM_CTRL1_INTERCEPT_GDTR_WRITES RT_BIT(11)
297	/** 12 Intercept writes of LDTR */
298	#define SVM_CTRL1_INTERCEPT_LDTR_WRITES RT_BIT(12)
299	/** 13 Intercept writes of TR */
300	#define SVM_CTRL1_INTERCEPT_TR_WRITES RT_BIT(13)
301	/** 14 Intercept RDTSC instruction */
302	#define SVM_CTRL1_INTERCEPT_RDTSC RT_BIT(14)
303	/** 15 Intercept RDPMC instruction */
304	#define SVM_CTRL1_INTERCEPT_RDPMC RT_BIT(15)
305	/** 16 Intercept PUSHF instruction */
306	#define SVM_CTRL1_INTERCEPT_PUSHF RT_BIT(16)
307	/** 17 Intercept POPF instruction */
308	#define SVM_CTRL1_INTERCEPT_POPF RT_BIT(17)
309	/** 18 Intercept CPUID instruction */
310	#define SVM_CTRL1_INTERCEPT_CPUID RT_BIT(18)
311	/** 19 Intercept RSM instruction */
312	#define SVM_CTRL1_INTERCEPT_RSM RT_BIT(19)
313	/** 20 Intercept IRET instruction */
314	#define SVM_CTRL1_INTERCEPT_IRET RT_BIT(20)
315	/** 21 Intercept INTn instruction */
316	#define SVM_CTRL1_INTERCEPT_INTN RT_BIT(21)
317	/** 22 Intercept INVD instruction */
318	#define SVM_CTRL1_INTERCEPT_INVD RT_BIT(22)
319	/** 23 Intercept PAUSE instruction */
320	#define SVM_CTRL1_INTERCEPT_PAUSE RT_BIT(23)
321	/** 24 Intercept HLT instruction */
322	#define SVM_CTRL1_INTERCEPT_HLT RT_BIT(24)
323	/** 25 Intercept INVLPG instruction */
324	#define SVM_CTRL1_INTERCEPT_INVLPG RT_BIT(25)
325	/** 26 Intercept INVLPGA instruction */
326	#define SVM_CTRL1_INTERCEPT_INVLPGA RT_BIT(26)
327	/** 27 IOIO_PROT Intercept IN/OUT accesses to selected ports. */
328	#define SVM_CTRL1_INTERCEPT_INOUT_BITMAP RT_BIT(27)
329	/** 28 MSR_PROT Intercept RDMSR or WRMSR accesses to selected MSRs. */
330	#define SVM_CTRL1_INTERCEPT_MSR_SHADOW RT_BIT(28)
331	/** 29 Intercept task switches. */
332	#define SVM_CTRL1_INTERCEPT_TASK_SWITCH RT_BIT(29)
333	/** 30 FERR_FREEZE: intercept processor "freezing" during legacy FERR handling. */
334	#define SVM_CTRL1_INTERCEPT_FERR_FREEZE RT_BIT(30)
335	/** 31 Intercept shutdown events. */
336	#define SVM_CTRL1_INTERCEPT_SHUTDOWN RT_BIT(31)
337	/** @} */
338
339
340	/** @name SVM_VMCB.ctrl.u32InterceptCtrl2
341	* @{
342	*/
343	/** 0 Intercept VMRUN instruction */
344	#define SVM_CTRL2_INTERCEPT_VMRUN RT_BIT(0)
345	/** 1 Intercept VMMCALL instruction */
346	#define SVM_CTRL2_INTERCEPT_VMMCALL RT_BIT(1)
347	/** 2 Intercept VMLOAD instruction */
348	#define SVM_CTRL2_INTERCEPT_VMLOAD RT_BIT(2)
349	/** 3 Intercept VMSAVE instruction */
350	#define SVM_CTRL2_INTERCEPT_VMSAVE RT_BIT(3)
351	/** 4 Intercept STGI instruction */
352	#define SVM_CTRL2_INTERCEPT_STGI RT_BIT(4)
353	/** 5 Intercept CLGI instruction */
354	#define SVM_CTRL2_INTERCEPT_CLGI RT_BIT(5)
355	/** 6 Intercept SKINIT instruction */
356	#define SVM_CTRL2_INTERCEPT_SKINIT RT_BIT(6)
357	/** 7 Intercept RDTSCP instruction */
358	#define SVM_CTRL2_INTERCEPT_RDTSCP RT_BIT(7)
359	/** 8 Intercept ICEBP instruction */
360	#define SVM_CTRL2_INTERCEPT_ICEBP RT_BIT(8)
361	/** 9 Intercept WBINVD instruction */
362	#define SVM_CTRL2_INTERCEPT_WBINVD RT_BIT(9)
363	/** 10 Intercept MONITOR instruction */
364	#define SVM_CTRL2_INTERCEPT_MONITOR RT_BIT(10)
365	/** 11 Intercept MWAIT instruction unconditionally */
366	#define SVM_CTRL2_INTERCEPT_MWAIT_UNCOND RT_BIT(11)
367	/** 12 Intercept MWAIT instruction when armed */
368	#define SVM_CTRL2_INTERCEPT_MWAIT_ARMED RT_BIT(12)
369	/** @} */
370
371	/** @name SVM_VMCB.ctrl.u64NestedPaging
372	* @{
373	*/
374	#define SVM_NESTED_PAGING_ENABLE RT_BIT(0)
375	/** @} */
376
377	/** @name SVM_VMCB.ctrl.u64IntShadow
378	* @{
379	*/
380	#define SVM_INTERRUPT_SHADOW_ACTIVE RT_BIT(0)
381	/** @} */
382
383
384	/** @name SVM_INTCTRL.u3Type
385	* @{
386	*/
387	/** External or virtual interrupt. */
388	#define SVM_EVENT_EXTERNAL_IRQ 0
389	/** Non-maskable interrupt. */
390	#define SVM_EVENT_NMI 2
391	/** Exception; fault or trap. */
392	#define SVM_EVENT_EXCEPTION 3
393	/** Software interrupt. */
394	#define SVM_EVENT_SOFTWARE_INT 4
395	/** @} */
396
397
398
399
400	/**
401	* SVM Selector type; includes hidden parts
402	*/
403	#pragma pack(1)
404	typedef struct
405	{
406	uint16_t u16Sel;
407	uint16_t u16Attr;
408	uint32_t u32Limit;
409	uint64_t u64Base; /*< Only lower 32 bits are implemented for CS, DS, ES & SS. /
410	} SVMSEL;
411	#pragma pack()
412
413	/**
414	* SVM GDTR/IDTR type
415	*/
416	#pragma pack(1)
417	typedef struct
418	{
419	uint16_t u16Reserved1;
420	uint16_t u16Reserved2;
421	uint32_t u32Limit; /*< Only lower 16 bits are implemented. /
422	uint64_t u64Base;
423	} SVMGDTR;
424	#pragma pack()
425
426	typedef SVMGDTR SVMIDTR;
427
428	/**
429	* SVM Event injection structure
430	*/
431	#pragma pack(1)
432	typedef union
433	{
434	struct
435	{
436	uint32_t u8Vector : 8;
437	uint32_t u3Type : 3;
438	uint32_t u1ErrorCodeValid : 1;
439	uint32_t u19Reserved : 19;
440	uint32_t u1Valid : 1;
441	uint32_t u32ErrorCode : 32;
442	} n;
443	uint64_t au64[1];
444	} SVM_EVENT;
445	#pragma pack()
446
447
448	/**
449	* SVM Interrupt control structure
450	*/
451	#pragma pack(1)
452	typedef union
453	{
454	struct
455	{
456	uint32_t u8VTPR : 8;
457	uint32_t u1VIrqValid : 1;
458	uint32_t u7Reserved : 7;
459	uint32_t u4VIrqPriority : 4;
460	uint32_t u1IgnoreTPR : 1;
461	uint32_t u3Reserved : 3;
462	uint32_t u1VIrqMasking : 1;
463	uint32_t u7Reserved2 : 7;
464	uint32_t u8VIrqVector : 8;
465	uint32_t u24Reserved : 24;
466	} n;
467	uint64_t au64[1];
468	} SVM_INTCTRL;
469	#pragma pack()
470
471
472	/**
473	* SVM TLB control structure
474	*/
475	#pragma pack(1)
476	typedef union
477	{
478	struct
479	{
480	uint32_t u32ASID : 32;
481	uint32_t u1TLBFlush : 1;
482	uint32_t u7Reserved : 7;
483	uint32_t u24Reserved : 24;
484	} n;
485	uint64_t au64[1];
486	} SVM_TLBCTRL;
487	#pragma pack()
488
489
490	/**
491	* SVM IOIO exit structure
492	*/
493	#pragma pack(1)
494	typedef union
495	{
496	struct
497	{
498	uint32_t u1Type : 1; /*< 0 = out, 1 = in /
499	uint32_t u1Reserved : 1;
500	uint32_t u1STR : 1;
501	uint32_t u1REP : 1;
502	uint32_t u1OP8 : 1;
503	uint32_t u1OP16 : 1;
504	uint32_t u1OP32 : 1;
505	uint32_t u1ADDR16 : 1;
506	uint32_t u1ADDR32 : 1;
507	uint32_t u1ADDR64 : 1;
508	uint32_t u6Reserved : 6;
509	uint32_t u16Port : 16;
510	} n;
511	uint32_t au32[1];
512	} SVM_IOIO_EXIT;
513	#pragma pack()
514
515	/**
516	* SVM nested paging structure
517	*/
518	#pragma pack(1)
519	typedef union
520	{
521	struct
522	{
523	uint32_t u1NestedPaging : 1; /*< enabled/disabled /
524	} n;
525	uint64_t au64[1];
526	} SVM_NPCTRL;
527	#pragma pack()
528
529	/**
530	* SVM VM Control Block. (VMCB)
531	*/
532	#pragma pack(1)
533	typedef struct _SVM_VMCB
534	{
535	/** Control Area. */
536	struct
537	{
538	/** Offset 0x00 - Intercept reads of CR0-15. */
539	uint16_t u16InterceptRdCRx;
540	/** Offset 0x02 - Intercept writes to CR0-15. */
541	uint16_t u16InterceptWrCRx;
542	/** Offset 0x04 - Intercept reads of DR0-15. */
543	uint16_t u16InterceptRdDRx;
544	/** Offset 0x06 - Intercept writes to DR0-15. */
545	uint16_t u16InterceptWrDRx;
546	/** Offset 0x08 - Intercept exception vectors 0-31. */
547	uint32_t u32InterceptException;
548	/** Offset 0x0C - Intercept control field 1. */
549	uint32_t u32InterceptCtrl1;
550	/** Offset 0x0C - Intercept control field 2. */
551	uint32_t u32InterceptCtrl2;
552	/** Offset 0x14-0x3F - Reserved. */
553	uint8_t u8Reserved[0x40-0x14];
554	/** Offset 0x40 - Physical address of IOPM. */
555	uint64_t u64IOPMPhysAddr;
556	/** Offset 0x48 - Physical address of MSRPM. */
557	uint64_t u64MSRPMPhysAddr;
558	/** Offset 0x50 - TSC Offset. */
559	uint64_t u64TSCOffset;
560	/** Offset 0x58 - TLB control field. */
561	SVM_TLBCTRL TLBCtrl;
562	/** Offset 0x60 - Interrupt control field. */
563	SVM_INTCTRL IntCtrl;
564	/** Offset 0x68 - Interrupt shadow. */
565	uint64_t u64IntShadow;
566	/** Offset 0x70 - Exit code. */
567	uint64_t u64ExitCode;
568	/** Offset 0x78 - Exit info 1. */
569	uint64_t u64ExitInfo1;
570	/** Offset 0x80 - Exit info 2. */
571	uint64_t u64ExitInfo2;
572	/** Offset 0x88 - Exit Interrupt info. */
573	SVM_EVENT ExitIntInfo;
574	/** Offset 0x90 - Nested Paging. */
575	SVM_NPCTRL NestedPaging;
576	/** Offset 0x98-0xA7 - Reserved. */
577	uint8_t u8Reserved2[0xA8-0x98];
578	/** Offset 0xA8 - Event injection. */
579	SVM_EVENT EventInject;
580	/** Offset 0xB0 - Host CR3 for nested paging. */
581	uint64_t u64NestedPagingCR3;
582	/** Offset 0xB8 - LBR Virtualization. */
583	uint64_t u64LBRVirt;
584	} ctrl;
585
586	/** Offset 0xC0-0x3FF - Reserved. */
587	uint8_t u8Reserved3[0x400-0xC0];
588
589	/** State Save Area. Starts at offset 0x400. */
590	struct
591	{
592	/** Offset 0x400 - Guest ES register + hidden parts. */
593	SVMSEL ES;
594	/** Offset 0x410 - Guest CS register + hidden parts. */
595	SVMSEL CS;
596	/** Offset 0x420 - Guest SS register + hidden parts. */
597	SVMSEL SS;
598	/** Offset 0x430 - Guest DS register + hidden parts. */
599	SVMSEL DS;
600	/** Offset 0x440 - Guest FS register + hidden parts. */
601	SVMSEL FS;
602	/** Offset 0x450 - Guest GS register + hidden parts. */
603	SVMSEL GS;
604	/** Offset 0x460 - Guest GDTR register. */
605	SVMGDTR GDTR;
606	/** Offset 0x470 - Guest LDTR register + hidden parts. */
607	SVMSEL LDTR;
608	/** Offset 0x480 - Guest IDTR register. */
609	SVMIDTR IDTR;
610	/** Offset 0x490 - Guest TR register + hidden parts. */
611	SVMSEL TR;
612	/** Offset 0x4A0-0x4CA - Reserved. */
613	uint8_t u8Reserved4[0x4CB-0x4A0];
614	/** Offset 0x4CB - CPL. */
615	uint8_t u8CPL;
616	/** Offset 0x4CC-0x4CF - Reserved. */
617	uint8_t u8Reserved5[0x4D0-0x4CC];
618	/** Offset 0x4D0 - EFER. */
619	uint64_t u64EFER;
620	/** Offset 0x4D8-0x547 - Reserved. */
621	uint8_t u8Reserved6[0x548-0x4D8];
622	/** Offset 0x548 - CR4. */
623	uint64_t u64CR4;
624	/** Offset 0x550 - CR3. */
625	uint64_t u64CR3;
626	/** Offset 0x558 - CR0. */
627	uint64_t u64CR0;
628	/** Offset 0x560 - DR7. */
629	uint64_t u64DR7;
630	/** Offset 0x568 - DR6. */
631	uint64_t u64DR6;
632	/** Offset 0x570 - RFLAGS. */
633	uint64_t u64RFlags;
634	/** Offset 0x578 - RIP. */
635	uint64_t u64RIP;
636	/** Offset 0x580-0x5D7 - Reserved. */
637	uint8_t u8Reserved7[0x5D8-0x580];
638	/** Offset 0x5D8 - RSP. */
639	uint64_t u64RSP;
640	/** Offset 0x5E0-0x5F7 - Reserved. */
641	uint8_t u8Reserved8[0x5F8-0x5E0];
642	/** Offset 0x5F8 - RAX. */
643	uint64_t u64RAX;
644	/** Offset 0x600 - STAR. */
645	uint64_t u64STAR;
646	/** Offset 0x608 - LSTAR. */
647	uint64_t u64LSTAR;
648	/** Offset 0x610 - CSTAR. */
649	uint64_t u64CSTAR;
650	/** Offset 0x618 - SFMASK. */
651	uint64_t u64SFMASK;
652	/** Offset 0x620 - KernelGSBase. */
653	uint64_t u64KernelGSBase;
654	/** Offset 0x628 - SYSENTER_CS. */
655	uint64_t u64SysEnterCS;
656	/** Offset 0x630 - SYSENTER_ESP. */
657	uint64_t u64SysEnterESP;
658	/** Offset 0x638 - SYSENTER_EIP. */
659	uint64_t u64SysEnterEIP;
660	/** Offset 0x640 - CR2. */
661	uint64_t u64CR2;
662	/** Offset 0x648-0x667 - Reserved. */
663	uint8_t u8Reserved9[0x668-0x648];
664	/** Offset 0x668 - G_PAT. */
665	uint64_t u64GPAT;
666	/** Offset 0x670 - DBGCTL. */
667	uint64_t u64DBGCTL;
668	/** Offset 0x678 - BR_FROM. */
669	uint64_t u64BR_FROM;
670	/** Offset 0x680 - BR_TO. */
671	uint64_t u64BR_TO;
672	/** Offset 0x688 - LASTEXCPFROM. */
673	uint64_t u64LASTEXCPFROM;
674	/** Offset 0x690 - LASTEXCPTO. */
675	uint64_t u64LASTEXCPTO;
676	} guest;
677
678	/** Offset 0x698-0xFFF- Reserved. */
679	uint8_t u8Reserved10[0x1000-0x698];
680	} SVM_VMCB;
681	#pragma pack()
682
683	#ifdef IN_RING0
684	VMMR0DECL(int) SVMR0InvalidatePage(PVM pVM, PVMCPU pVCpu, RTGCPTR GCVirt);
685	#endif /* IN_RING0 */
686
687	/** @} */
688
689	#endif
690

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source: vbox/trunk/include/VBox/hwacc_svm.h@ 24130

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