VirtualBox

source: vbox/trunk/include/VBox/hwacc_svm.h@ 4388

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1/** @file
2 * SVM Structures and Definitions.
3 */
4
5/*
6 * Copyright (C) 2006-2007 innotek GmbH
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License as published by the Free Software Foundation,
12 * in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
13 * distribution. VirtualBox OSE is distributed in the hope that it will
14 * be useful, but WITHOUT ANY WARRANTY of any kind.
15 */
16
17#ifndef ___VBox_svm_h
18#define ___VBox_svm_h
19
20#include <VBox/types.h>
21#include <VBox/err.h>
22#include <VBox/cpum.h>
23#include <iprt/assert.h>
24#include <iprt/asm.h>
25
26/** @defgroup grp_svm svm Types and Definitions
27 * @ingroup grp_hwaccm
28 * @{
29 */
30
31
32/** @name SVM Basic Exit Reasons.
33 * @{
34 */
35/** Invalid guest state in VMCB. */
36#define SVM_EXIT_INVALID -1
37/** Read from CR0-CR15. */
38#define SVM_EXIT_READ_CR0 0x0
39#define SVM_EXIT_READ_CR1 0x1
40#define SVM_EXIT_READ_CR2 0x2
41#define SVM_EXIT_READ_CR3 0x3
42#define SVM_EXIT_READ_CR4 0x4
43#define SVM_EXIT_READ_CR5 0x5
44#define SVM_EXIT_READ_CR6 0x6
45#define SVM_EXIT_READ_CR7 0x7
46#define SVM_EXIT_READ_CR8 0x8
47#define SVM_EXIT_READ_CR9 0x9
48#define SVM_EXIT_READ_CR10 0xA
49#define SVM_EXIT_READ_CR11 0xB
50#define SVM_EXIT_READ_CR12 0xC
51#define SVM_EXIT_READ_CR13 0xD
52#define SVM_EXIT_READ_CR14 0xE
53#define SVM_EXIT_READ_CR15 0xF
54/** Writes to CR0-CR15. */
55#define SVM_EXIT_WRITE_CR0 0x10
56#define SVM_EXIT_WRITE_CR1 0x11
57#define SVM_EXIT_WRITE_CR2 0x12
58#define SVM_EXIT_WRITE_CR3 0x13
59#define SVM_EXIT_WRITE_CR4 0x14
60#define SVM_EXIT_WRITE_CR5 0x15
61#define SVM_EXIT_WRITE_CR6 0x16
62#define SVM_EXIT_WRITE_CR7 0x17
63#define SVM_EXIT_WRITE_CR8 0x18
64#define SVM_EXIT_WRITE_CR9 0x19
65#define SVM_EXIT_WRITE_CR10 0x1A
66#define SVM_EXIT_WRITE_CR11 0x1B
67#define SVM_EXIT_WRITE_CR12 0x1C
68#define SVM_EXIT_WRITE_CR13 0x1D
69#define SVM_EXIT_WRITE_CR14 0x1E
70#define SVM_EXIT_WRITE_CR15 0x1F
71/** Read from DR0-DR15. */
72#define SVM_EXIT_READ_DR0 0x20
73#define SVM_EXIT_READ_DR1 0x21
74#define SVM_EXIT_READ_DR2 0x22
75#define SVM_EXIT_READ_DR3 0x23
76#define SVM_EXIT_READ_DR4 0x24
77#define SVM_EXIT_READ_DR5 0x25
78#define SVM_EXIT_READ_DR6 0x26
79#define SVM_EXIT_READ_DR7 0x27
80#define SVM_EXIT_READ_DR8 0x28
81#define SVM_EXIT_READ_DR9 0x29
82#define SVM_EXIT_READ_DR10 0x2A
83#define SVM_EXIT_READ_DR11 0x2B
84#define SVM_EXIT_READ_DR12 0x2C
85#define SVM_EXIT_READ_DR13 0x2D
86#define SVM_EXIT_READ_DR14 0x2E
87#define SVM_EXIT_READ_DR15 0x2F
88/** Writes to DR0-DR15. */
89#define SVM_EXIT_WRITE_DR0 0x30
90#define SVM_EXIT_WRITE_DR1 0x31
91#define SVM_EXIT_WRITE_DR2 0x32
92#define SVM_EXIT_WRITE_DR3 0x33
93#define SVM_EXIT_WRITE_DR4 0x34
94#define SVM_EXIT_WRITE_DR5 0x35
95#define SVM_EXIT_WRITE_DR6 0x36
96#define SVM_EXIT_WRITE_DR7 0x37
97#define SVM_EXIT_WRITE_DR8 0x38
98#define SVM_EXIT_WRITE_DR9 0x39
99#define SVM_EXIT_WRITE_DR10 0x3A
100#define SVM_EXIT_WRITE_DR11 0x3B
101#define SVM_EXIT_WRITE_DR12 0x3C
102#define SVM_EXIT_WRITE_DR13 0x3D
103#define SVM_EXIT_WRITE_DR14 0x3E
104#define SVM_EXIT_WRITE_DR15 0x3F
105/* Exception 0-31. */
106#define SVM_EXIT_EXCEPTION_0 0x40
107#define SVM_EXIT_EXCEPTION_1 0x41
108#define SVM_EXIT_EXCEPTION_2 0x42
109#define SVM_EXIT_EXCEPTION_3 0x43
110#define SVM_EXIT_EXCEPTION_4 0x44
111#define SVM_EXIT_EXCEPTION_5 0x45
112#define SVM_EXIT_EXCEPTION_6 0x46
113#define SVM_EXIT_EXCEPTION_7 0x47
114#define SVM_EXIT_EXCEPTION_8 0x48
115#define SVM_EXIT_EXCEPTION_9 0x49
116#define SVM_EXIT_EXCEPTION_A 0x4A
117#define SVM_EXIT_EXCEPTION_B 0x4B
118#define SVM_EXIT_EXCEPTION_C 0x4C
119#define SVM_EXIT_EXCEPTION_D 0x4D
120#define SVM_EXIT_EXCEPTION_E 0x4E
121#define SVM_EXIT_EXCEPTION_F 0x4F
122#define SVM_EXIT_EXCEPTION_10 0x50
123#define SVM_EXIT_EXCEPTION_11 0x51
124#define SVM_EXIT_EXCEPTION_12 0x52
125#define SVM_EXIT_EXCEPTION_13 0x53
126#define SVM_EXIT_EXCEPTION_14 0x54
127#define SVM_EXIT_EXCEPTION_15 0x55
128#define SVM_EXIT_EXCEPTION_16 0x56
129#define SVM_EXIT_EXCEPTION_17 0x57
130#define SVM_EXIT_EXCEPTION_18 0x58
131#define SVM_EXIT_EXCEPTION_19 0x59
132#define SVM_EXIT_EXCEPTION_1A 0x5A
133#define SVM_EXIT_EXCEPTION_1B 0x5B
134#define SVM_EXIT_EXCEPTION_1C 0x5C
135#define SVM_EXIT_EXCEPTION_1D 0x5D
136#define SVM_EXIT_EXCEPTION_1E 0x5E
137#define SVM_EXIT_EXCEPTION_1F 0x5F
138/** Physical maskable interrupt. */
139#define SVM_EXIT_INTR 0x60
140/** Non-maskable interrupt. */
141#define SVM_EXIT_NMI 0x61
142/** System Management interrupt. */
143#define SVM_EXIT_SMI 0x62
144/** Physical INIT signal. */
145#define SVM_EXIT_INIT 0x63
146/** Virtual interrupt. */
147#define SVM_EXIT_VINTR 0x64
148/** Write to CR0 that changed any bits other than CR0.TS or CR0.MP. */
149#define SVM_EXIT_CR0_SEL_WRITE 0x65
150/** IDTR read. */
151#define SVM_EXIT_IDTR_READ 0x66
152/** GDTR read. */
153#define SVM_EXIT_GDTR_READ 0x67
154/** LDTR read. */
155#define SVM_EXIT_LDTR_READ 0x68
156/** TR read. */
157#define SVM_EXIT_TR_READ 0x69
158/** IDTR write. */
159#define SVM_EXIT_IDTR_WRITE 0x6A
160/** GDTR write. */
161#define SVM_EXIT_GDTR_WRITE 0x6B
162/** LDTR write. */
163#define SVM_EXIT_LDTR_WRITE 0x6C
164/** TR write. */
165#define SVM_EXIT_TR_WRITE 0x6D
166/** RDTSC instruction. */
167#define SVM_EXIT_RDTSC 0x6E
168/** RDPMC instruction. */
169#define SVM_EXIT_RDPMC 0x6F
170/** PUSHF instruction. */
171#define SVM_EXIT_PUSHF 0x70
172/** POPF instruction. */
173#define SVM_EXIT_POPF 0x71
174/** CPUID instruction. */
175#define SVM_EXIT_CPUID 0x72
176/** RSM instruction. */
177#define SVM_EXIT_RSM 0x73
178/** IRET instruction. */
179#define SVM_EXIT_IRET 0x74
180/** software interrupt (INTn instructions). */
181#define SVM_EXIT_SWINT 0x75
182/** INVD instruction. */
183#define SVM_EXIT_INVD 0x76
184/** PAUSE instruction. */
185#define SVM_EXIT_PAUSE 0x77
186/** HLT instruction. */
187#define SVM_EXIT_HLT 0x78
188/** INVLPG instructions. */
189#define SVM_EXIT_INVLPG 0x79
190/** INVLPGA instruction. */
191#define SVM_EXIT_INVLPGA 0x7A
192/** IN or OUT accessing protected port (the EXITINFO1 field provides more information). */
193#define SVM_EXIT_IOIO 0x7B
194/** RDMSR or WRMSR access to protected MSR. */
195#define SVM_EXIT_MSR 0x7C
196/** task switch. */
197#define SVM_EXIT_TASK_SWITCH 0x7D
198/** FP legacy handling enabled, and processor is frozen in an x87/mmx instruction waiting for an interrupt. */
199#define SVM_EXIT_FERR_FREEZE 0x7E
200/** Shutdown. */
201#define SVM_EXIT_SHUTDOWN 0x7F
202/** VMRUN instruction. */
203#define SVM_EXIT_VMRUN 0x80
204/** VMMCALL instruction. */
205#define SVM_EXIT_VMMCALL 0x81
206/** VMLOAD instruction. */
207#define SVM_EXIT_VMLOAD 0x82
208/** VMSAVE instruction. */
209#define SVM_EXIT_VMSAVE 0x83
210/** STGI instruction. */
211#define SVM_EXIT_STGI 0x84
212/** CLGI instruction. */
213#define SVM_EXIT_CLGI 0x85
214/** SKINIT instruction. */
215#define SVM_EXIT_SKINIT 0x86
216/** RDTSCP instruction. */
217#define SVM_EXIT_RDTSCP 0x87
218/** ICEBP instruction. */
219#define SVM_EXIT_ICEBP 0x88
220/** WBINVD instruction. */
221#define SVM_INVD 0x89
222/** Nested paging: host-level page fault occurred (EXITINFO1 contains fault errorcode; EXITINFO2 contains the guest physical address causing the fault.). */
223#define SVM_EXIT_NPF 0x400
224
225/** @} */
226
227
228/** @name SVM_VMCB.ctrl.u32InterceptCtrl1
229 * @{
230 */
231/* 0 Intercept INTR (physical maskable interrupt) */
232#define SVM_CTRL1_INTERCEPT_INTR BIT(0)
233/* 1 Intercept NMI */
234#define SVM_CTRL1_INTERCEPT_NMI BIT(1)
235/* 2 Intercept SMI */
236#define SVM_CTRL1_INTERCEPT_SMI BIT(2)
237/* 3 Intercept INIT */
238#define SVM_CTRL1_INTERCEPT_INIT BIT(3)
239/* 4 Intercept VINTR (virtual maskable interrupt) */
240#define SVM_CTRL1_INTERCEPT_VINTR BIT(4)
241/* 5 Intercept CR0 writes that change bits other than CR0.TS or CR0.MP */
242#define SVM_CTRL1_INTERCEPT_CR0 BIT(5)
243/* 6 Intercept reads of IDTR */
244#define SVM_CTRL1_INTERCEPT_IDTR_READS BIT(6)
245/* 7 Intercept reads of GDTR */
246#define SVM_CTRL1_INTERCEPT_GDTR_READS BIT(7)
247/* 8 Intercept reads of LDTR */
248#define SVM_CTRL1_INTERCEPT_LDTR_READS BIT(8)
249/* 9 Intercept reads of TR */
250#define SVM_CTRL1_INTERCEPT_TR_READS BIT(9)
251/* 10 Intercept writes of IDTR */
252#define SVM_CTRL1_INTERCEPT_IDTR_WRITES BIT(10)
253/* 11 Intercept writes of GDTR */
254#define SVM_CTRL1_INTERCEPT_GDTR_WRITES BIT(11)
255/* 12 Intercept writes of LDTR */
256#define SVM_CTRL1_INTERCEPT_LDTR_WRITES BIT(12)
257/* 13 Intercept writes of TR */
258#define SVM_CTRL1_INTERCEPT_TR_WRITES BIT(13)
259/* 14 Intercept RDTSC instruction */
260#define SVM_CTRL1_INTERCEPT_RDTSC BIT(14)
261/* 15 Intercept RDPMC instruction */
262#define SVM_CTRL1_INTERCEPT_RDPMC BIT(15)
263/* 16 Intercept PUSHF instruction */
264#define SVM_CTRL1_INTERCEPT_PUSHF BIT(16)
265/* 17 Intercept POPF instruction */
266#define SVM_CTRL1_INTERCEPT_POPF BIT(17)
267/* 18 Intercept CPUID instruction */
268#define SVM_CTRL1_INTERCEPT_CPUID BIT(18)
269/* 19 Intercept RSM instruction */
270#define SVM_CTRL1_INTERCEPT_RSM BIT(19)
271/* 20 Intercept IRET instruction */
272#define SVM_CTRL1_INTERCEPT_IRET BIT(20)
273/* 21 Intercept INTn instruction */
274#define SVM_CTRL1_INTERCEPT_INTN BIT(21)
275/* 22 Intercept INVD instruction */
276#define SVM_CTRL1_INTERCEPT_INVD BIT(22)
277/* 23 Intercept PAUSE instruction */
278#define SVM_CTRL1_INTERCEPT_PAUSE BIT(23)
279/* 24 Intercept HLT instruction */
280#define SVM_CTRL1_INTERCEPT_HLT BIT(24)
281/* 25 Intercept INVLPG instruction */
282#define SVM_CTRL1_INTERCEPT_INVLPG BIT(25)
283/* 26 Intercept INVLPGA instruction */
284#define SVM_CTRL1_INTERCEPT_INVLPGA BIT(26)
285/* 27 IOIO_PROT Intercept IN/OUT accesses to selected ports. */
286#define SVM_CTRL1_INTERCEPT_INOUT_BITMAP BIT(27)
287/* 28 MSR_PROT Intercept RDMSR or WRMSR accesses to selected MSRs. */
288#define SVM_CTRL1_INTERCEPT_MSR_SHADOW BIT(28)
289/* 29 Intercept task switches. */
290#define SVM_CTRL1_INTERCEPT_TASK_SWITCH BIT(29)
291/* 30 FERR_FREEZE: intercept processor "freezing" during legacy FERR handling. */
292#define SVM_CTRL1_INTERCEPT_FERR_FREEZE BIT(30)
293/* 31 Intercept shutdown events. */
294#define SVM_CTRL1_INTERCEPT_SHUTDOWN BIT(31)
295/** @} */
296
297
298/** @name SVM_VMCB.ctrl.u32InterceptCtrl2
299 * @{
300 */
301/* 0 Intercept VMRUN instruction */
302#define SVM_CTRL2_INTERCEPT_VMRUN BIT(0)
303/* 1 Intercept VMMCALL instruction */
304#define SVM_CTRL2_INTERCEPT_VMMCALL BIT(1)
305/* 2 Intercept VMLOAD instruction */
306#define SVM_CTRL2_INTERCEPT_VMLOAD BIT(2)
307/* 3 Intercept VMSAVE instruction */
308#define SVM_CTRL2_INTERCEPT_VMSAVE BIT(3)
309/* 4 Intercept STGI instruction */
310#define SVM_CTRL2_INTERCEPT_STGI BIT(4)
311/* 5 Intercept CLGI instruction */
312#define SVM_CTRL2_INTERCEPT_CLGI BIT(5)
313/* 6 Intercept SKINIT instruction */
314#define SVM_CTRL2_INTERCEPT_SKINIT BIT(6)
315/* 7 Intercept RDTSCP instruction */
316#define SVM_CTRL2_INTERCEPT_RDTSCP BIT(7)
317/* 8 Intercept ICEBP instruction */
318#define SVM_CTRL2_INTERCEPT_ICEBP BIT(8)
319/* 9 Intercept WBINVD instruction */
320#define SVM_CTRL2_INTERCEPT_WBINVD BIT(9)
321/** @} */
322
323/** @name SVM_VMCB.ctrl.u64NestedPaging
324 * @{
325 */
326#define SVM_NESTED_PAGING_ENABLE BIT(0)
327/** @} */
328
329/** @name SVM_VMCB.ctrl.u64IntShadow
330 * @{
331 */
332#define SVM_INTERRUPT_SHADOW_ACTIVE BIT(0)
333/** @} */
334
335
336/** @name SVM_INTCTRL.u3Type
337 * @{
338 */
339/** External or virtual interrupt. */
340#define SVM_EVENT_EXTERNAL_IRQ 0
341/** Non-maskable interrupt. */
342#define SVM_EVENT_NMI 1
343/** Exception; fault or trap. */
344#define SVM_EVENT_EXCEPTION 3
345/** Software interrupt. */
346#define SVM_EVENT_SOFTWARE_INT 4
347/** @} */
348
349
350
351
352/**
353 * SVM Selector type; includes hidden parts
354 */
355#pragma pack(1)
356typedef struct
357{
358 uint16_t u16Sel;
359 uint16_t u16Attr;
360 uint32_t u32Limit;
361 uint64_t u64Base; /* Only lower 32 bits are implemented for CS, DS, ES & SS. */
362} SVMSEL;
363#pragma pack()
364
365/**
366 * SVM GDTR/IDTR type
367 */
368#pragma pack(1)
369typedef struct
370{
371 uint16_t u16Reserved1;
372 uint16_t u16Reserved2;
373 uint32_t u32Limit; /* Only lower 16 bits are implemented. */
374 uint64_t u64Base;
375} SVMGDTR;
376#pragma pack()
377
378typedef SVMGDTR SVMIDTR;
379
380/**
381 * SVM Event injection structure
382 */
383#pragma pack(1)
384typedef union
385{
386 struct
387 {
388 uint32_t u8Vector : 8;
389 uint32_t u3Type : 3;
390 uint32_t u1ErrorCodeValid : 1;
391 uint32_t u19Reserved : 19;
392 uint32_t u1Valid : 1;
393 uint32_t u32ErrorCode : 32;
394 } n;
395 uint64_t au64[1];
396} SVM_EVENT;
397#pragma pack()
398
399
400/**
401 * SVM Interrupt control structure
402 */
403#pragma pack(1)
404typedef union
405{
406 struct
407 {
408 uint32_t u8VTPR : 8;
409 uint32_t u1VIrqValid : 1;
410 uint32_t u7Reserved : 7;
411 uint32_t u4VIrqPriority : 4;
412 uint32_t u1IgnoreTPR : 1;
413 uint32_t u3Reserved : 3;
414 uint32_t u1VIrqMasking : 1;
415 uint32_t u7Reserved2 : 7;
416 uint32_t u8VIrqVector : 8;
417 uint32_t u24Reserved : 24;
418 } n;
419 uint64_t au64[1];
420} SVM_INTCTRL;
421#pragma pack()
422
423
424/**
425 * SVM TLB control structure
426 */
427#pragma pack(1)
428typedef union
429{
430 struct
431 {
432 uint32_t u32ASID : 32;
433 uint32_t u1TLBFlush : 1;
434 uint32_t u7Reserved : 7;
435 uint32_t u24Reserved : 24;
436 } n;
437 uint64_t au64[1];
438} SVM_TLBCTRL;
439#pragma pack()
440
441
442/**
443 * SVM IOIO exit structure
444 */
445#pragma pack(1)
446typedef union
447{
448 struct
449 {
450 uint32_t u1Type : 1; /* 0 = out, 1 = in */
451 uint32_t u1Reserved : 1;
452 uint32_t u1STR : 1;
453 uint32_t u1REP : 1;
454 uint32_t u1OP8 : 1;
455 uint32_t u1OP16 : 1;
456 uint32_t u1OP32 : 1;
457 uint32_t u1ADDR16 : 1;
458 uint32_t u1ADDR32 : 1;
459 uint32_t u1ADDR64 : 1;
460 uint32_t u6Reserved : 6;
461 uint32_t u16Port : 16;
462 } n;
463 uint32_t au32[1];
464} SVM_IOIO_EXIT;
465#pragma pack()
466
467
468/**
469 * SVM VM Control Block. (VMCB)
470 */
471#pragma pack(1)
472typedef struct _SVM_VMCB
473{
474 /** Control Area. */
475 struct
476 {
477 /** Offset 0x00 - Intercept reads of CR0-15. */
478 uint16_t u16InterceptRdCRx;
479 /** Offset 0x02 - Intercept writes to CR0-15. */
480 uint16_t u16InterceptWrCRx;
481 /** Offset 0x04 - Intercept reads of DR0-15. */
482 uint16_t u16InterceptRdDRx;
483 /** Offset 0x06 - Intercept writes to DR0-15. */
484 uint16_t u16InterceptWrDRx;
485 /** Offset 0x08 - Intercept exception vectors 0-31. */
486 uint32_t u32InterceptException;
487 /** Offset 0x0C - Intercept control field 1. */
488 uint32_t u32InterceptCtrl1;
489 /** Offset 0x0C - Intercept control field 2. */
490 uint32_t u32InterceptCtrl2;
491 /** Offset 0x14-0x3F - Reserved. */
492 uint8_t u8Reserved[0x40-0x14];
493 /** Offset 0x40 - Physical address of IOPM. */
494 uint64_t u64IOPMPhysAddr;
495 /** Offset 0x48 - Physical address of MSRPM. */
496 uint64_t u64MSRPMPhysAddr;
497 /** Offset 0x50 - TSC Offset. */
498 uint64_t u64TSCOffset;
499 /** Offset 0x58 - TLB control field. */
500 SVM_TLBCTRL TLBCtrl;
501 /** Offset 0x60 - Interrupt control field. */
502 SVM_INTCTRL IntCtrl;
503 /** Offset 0x68 - Interrupt shadow. */
504 uint64_t u64IntShadow;
505 /** Offset 0x70 - Exit code. */
506 uint64_t u64ExitCode;
507 /** Offset 0x78 - Exit info 1. */
508 uint64_t u64ExitInfo1;
509 /** Offset 0x80 - Exit info 2. */
510 uint64_t u64ExitInfo2;
511 /** Offset 0x88 - Exit Interrupt info. */
512 SVM_EVENT ExitIntInfo;
513 /** Offset 0x90 - Nested Paging. */
514 uint64_t u64NestedPaging;
515 /** Offset 0x98-0xA7 - Reserved. */
516 uint8_t u8Reserved2[0xA8-0x98];
517 /** Offset 0xA8 - Event injection. */
518 SVM_EVENT EventInject;
519 /** Offset 0xB0 - Host CR3 for nested paging. */
520 uint64_t u64HostCR3;
521 /** Offset 0xB8 - LBR Virtualization. */
522 uint64_t u64LBRVirt;
523 } ctrl;
524
525 /** Offset 0xC0-0x3FF - Reserved. */
526 uint8_t u8Reserved3[0x400-0xC0];
527
528 /* State Save Area. Starts at offset 0x400. */
529 struct
530 {
531 /** Offset 0x400 - Guest ES register + hidden parts. */
532 SVMSEL ES;
533 /** Offset 0x410 - Guest CS register + hidden parts. */
534 SVMSEL CS;
535 /** Offset 0x420 - Guest SS register + hidden parts. */
536 SVMSEL SS;
537 /** Offset 0x430 - Guest DS register + hidden parts. */
538 SVMSEL DS;
539 /** Offset 0x440 - Guest FS register + hidden parts. */
540 SVMSEL FS;
541 /** Offset 0x450 - Guest GS register + hidden parts. */
542 SVMSEL GS;
543 /** Offset 0x460 - Guest GDTR register. */
544 SVMGDTR GDTR;
545 /** Offset 0x470 - Guest LDTR register + hidden parts. */
546 SVMSEL LDTR;
547 /** Offset 0x480 - Guest IDTR register. */
548 SVMIDTR IDTR;
549 /** Offset 0x490 - Guest TR register + hidden parts. */
550 SVMSEL TR;
551 /** Offset 0x4A0-0x4CA - Reserved. */
552 uint8_t u8Reserved4[0x4CB-0x4A0];
553 /** Offset 0x4CB - CPL. */
554 uint8_t u8CPL;
555 /** Offset 0x4CC-0x4CF - Reserved. */
556 uint8_t u8Reserved5[0x4D0-0x4CC];
557 /** Offset 0x4D0 - EFER. */
558 uint64_t u64EFER;
559 /** Offset 0x4D8-0x547 - Reserved. */
560 uint8_t u8Reserved6[0x548-0x4D8];
561 /** Offset 0x548 - CR4. */
562 uint64_t u64CR4;
563 /** Offset 0x550 - CR3. */
564 uint64_t u64CR3;
565 /** Offset 0x558 - CR0. */
566 uint64_t u64CR0;
567 /** Offset 0x560 - DR7. */
568 uint64_t u64DR7;
569 /** Offset 0x568 - DR6. */
570 uint64_t u64DR6;
571 /** Offset 0x570 - RFLAGS. */
572 uint64_t u64RFlags;
573 /** Offset 0x578 - RIP. */
574 uint64_t u64RIP;
575 /** Offset 0x580-0x5D7 - Reserved. */
576 uint8_t u8Reserved7[0x5D8-0x580];
577 /** Offset 0x5D8 - RSP. */
578 uint64_t u64RSP;
579 /** Offset 0x5E0-0x5F7 - Reserved. */
580 uint8_t u8Reserved8[0x5F8-0x5E0];
581 /** Offset 0x5F8 - RAX. */
582 uint64_t u64RAX;
583 /** Offset 0x600 - STAR. */
584 uint64_t u64STAR;
585 /** Offset 0x608 - LSTAR. */
586 uint64_t u64LSTAR;
587 /** Offset 0x610 - CSTAR. */
588 uint64_t u64CSTAR;
589 /** Offset 0x618 - SFMASK. */
590 uint64_t u64SFMASK;
591 /** Offset 0x620 - KernelGSBase. */
592 uint64_t u64KernelGSBase;
593 /** Offset 0x628 - SYSENTER_CS. */
594 uint64_t u64SysEnterCS;
595 /** Offset 0x630 - SYSENTER_ESP. */
596 uint64_t u64SysEnterESP;
597 /** Offset 0x638 - SYSENTER_EIP. */
598 uint64_t u64SysEnterEIP;
599 /** Offset 0x640 - CR2. */
600 uint64_t u64CR2;
601 /** Offset 0x648-0x667 - Reserved. */
602 uint8_t u8Reserved9[0x668-0x648];
603 /** Offset 0x668 - G_PAT. */
604 uint64_t u64GPAT;
605 /** Offset 0x670 - DBGCTL. */
606 uint64_t u64DBGCTL;
607 /** Offset 0x678 - BR_FROM. */
608 uint64_t u64BR_FROM;
609 /** Offset 0x680 - BR_TO. */
610 uint64_t u64BR_TO;
611 /** Offset 0x688 - LASTEXCPFROM. */
612 uint64_t u64LASTEXCPFROM;
613 /** Offset 0x690 - LASTEXCPTO. */
614 uint64_t u64LASTEXCPTO;
615 } guest;
616
617 /** Offset 0x698-0xFFF- Reserved. */
618 uint8_t u8Reserved10[0x1000-0x698];
619} SVM_VMCB;
620#pragma pack()
621
622
623/**
624 * Prepares for and executes VMRUN
625 *
626 * @returns VBox status code
627 * @param pVMCBHostPhys Physical address of host VMCB
628 * @param pVMCBPhys Physical address of the VMCB
629 * @param pCtx Guest context
630 */
631DECLASM(int) SVMVMRun(RTHCPHYS pVMCBHostPhys, RTHCPHYS pVMCBPhys, PCPUMCTX pCtx);
632
633
634/**
635 * Executes INVLPGA
636 *
637 * @param pPageGC Virtual page to invalidate
638 * @param uASID Tagged TLB id
639 */
640#if RT_INLINE_ASM_EXTERNAL
641DECLASM(void) SVMInvlpgA(RTGCPTR pPageGC, uint32_t uASID);
642#else
643DECLINLINE(void) SVMInvlpgA(RTGCPTR pPageGC, uint32_t uASID)
644{
645# if RT_INLINE_ASM_GNU_STYLE
646 AssertFailed();
647# else
648 __asm
649 {
650# ifdef RT_ARCH_AMD64
651 mov rax, pPageGC
652# else
653 mov eax, pPageGC
654# endif
655 push ecx
656 mov ecx, uASID
657 _emit 0x0F
658 _emit 0x01
659 _emit 0xDF /* invlpga rAX, ECX */
660
661 pop ecx
662 }
663# endif
664}
665#endif
666
667
668
669/** @} */
670
671#endif
672
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