VirtualBox

source: vbox/trunk/include/VBox/hwacc_vmx.h@ 8113

Last change on this file since 8113 was 7452, checked in by vboxsync, 17 years ago

MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE fix
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File size: 37.6 KB
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1/** @file
2 * HWACC/VMX - VMX Structures and Definitions.
3 */
4
5/*
6 * Copyright (C) 2006-2007 innotek GmbH
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * The contents of this file may alternatively be used under the terms
17 * of the Common Development and Distribution License Version 1.0
18 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19 * VirtualBox OSE distribution, in which case the provisions of the
20 * CDDL are applicable instead of those of the GPL.
21 *
22 * You may elect to license modified versions of this file under the
23 * terms and conditions of either the GPL or the CDDL or both.
24 */
25
26#ifndef ___VBox_vmx_h
27#define ___VBox_vmx_h
28
29#include <VBox/types.h>
30#include <VBox/err.h>
31#include <iprt/assert.h>
32#include <iprt/asm.h>
33
34/** @defgroup grp_vmx vmx Types and Definitions
35 * @ingroup grp_hwaccm
36 * @{
37 */
38
39/** VMX Basic Exit Reasons.
40 * @{
41 */
42/* And-mask for setting reserved bits to zero */
43#define VMX_EFLAGS_RESERVED_0 (~0xffc08028)
44/* Or-mask for setting reserved bits to 1 */
45#define VMX_EFLAGS_RESERVED_1 0x00000002
46/** @} */
47
48/** VMX Basic Exit Reasons.
49 * @{
50 */
51/** 0 Exception or non-maskable interrupt (NMI). */
52#define VMX_EXIT_EXCEPTION 0
53/** 1 External interrupt. */
54#define VMX_EXIT_EXTERNAL_IRQ 1
55/** 2 Triple fault. */
56#define VMX_EXIT_TRIPLE_FAULT 2
57/** 3 INIT signal. */
58#define VMX_EXIT_INIT_SIGNAL 3
59/** 4 Start-up IPI (SIPI). */
60#define VMX_EXIT_SIPI 4
61/** 5 I/O system-management interrupt (SMI). */
62#define VMX_EXIT_IO_SMI_IRQ 5
63/** 6 Other SMI. */
64#define VMX_EXIT_SMI_IRQ 6
65/** 7 Interrupt window. */
66#define VMX_EXIT_IRQ_WINDOW 7
67/** 9 Task switch. */
68#define VMX_EXIT_TASK_SWITCH 9
69/** 10 Guest software attempted to execute CPUID. */
70#define VMX_EXIT_CPUID 10
71/** 12 Guest software attempted to execute HLT. */
72#define VMX_EXIT_HLT 12
73/** 13 Guest software attempted to execute INVD. */
74#define VMX_EXIT_INVD 13
75/** 14 Guest software attempted to execute INVPG. */
76#define VMX_EXIT_INVPG 14
77/** 15 Guest software attempted to execute RDPMC. */
78#define VMX_EXIT_RDPMC 15
79/** 16 Guest software attempted to execute RDTSC. */
80#define VMX_EXIT_RDTSC 16
81/** 17 Guest software attempted to execute RSM in SMM. */
82#define VMX_EXIT_RSM 17
83/** 18 Guest software executed VMCALL. */
84#define VMX_EXIT_VMCALL 18
85/** 19 Guest software executed VMCLEAR. */
86#define VMX_EXIT_VMCLEAR 19
87/** 20 Guest software executed VMLAUNCH. */
88#define VMX_EXIT_VMLAUNCH 20
89/** 21 Guest software executed VMPTRLD. */
90#define VMX_EXIT_VMPTRLD 21
91/** 22 Guest software executed VMPTRST. */
92#define VMX_EXIT_VMPTRST 22
93/** 23 Guest software executed VMREAD. */
94#define VMX_EXIT_VMREAD 23
95/** 24 Guest software executed VMRESUME. */
96#define VMX_EXIT_VMRESUME 24
97/** 25 Guest software executed VMWRITE. */
98#define VMX_EXIT_VMWRITE 25
99/** 26 Guest software executed VMXOFF. */
100#define VMX_EXIT_VMXOFF 26
101/** 27 Guest software executed VMXON. */
102#define VMX_EXIT_VMXON 27
103/** 28 Control-register accesses. */
104#define VMX_EXIT_CRX_MOVE 28
105/** 29 Debug-register accesses. */
106#define VMX_EXIT_DRX_MOVE 29
107/** 30 I/O instruction. */
108#define VMX_EXIT_PORT_IO 30
109/** 31 RDMSR. Guest software attempted to execute RDMSR. */
110#define VMX_EXIT_RDMSR 31
111/** 32 WRMSR. Guest software attempted to execute WRMSR. */
112#define VMX_EXIT_WRMSR 32
113/** 33 VM-entry failure due to invalid guest state. */
114#define VMX_EXIT_ERR_INVALID_GUEST_STATE 33
115/** 34 VM-entry failure due to MSR loading. */
116#define VMX_EXIT_ERR_MSR_LOAD 34
117/** 36 Guest software executed MWAIT. */
118#define VMX_EXIT_MWAIT 36
119/** 39 Guest software attempted to execute MONITOR. */
120#define VMX_EXIT_MONITOR 39
121/** 40 Guest software attempted to execute PAUSE. */
122#define VMX_EXIT_PAUSE 40
123/** 41 VM-entry failure due to machine-check. */
124#define VMX_EXIT_ERR_MACHINE_CHECK 41
125/** 43 TPR below threshold. Guest software executed MOV to CR8. */
126#define VMX_EXIT_TPR 43
127
128/** @} */
129
130
131/** VM Instruction Errors
132 * @{
133 */
134/** 1 VMCALL executed in VMX root operation. */
135#define VMX_ERROR_VMCALL 1
136/** 2 VMCLEAR with invalid physical address. */
137#define VMX_ERROR_VMCLEAR_INVALID_PHYS_ADDR 2
138/** 3 VMCLEAR with VMXON pointer. */
139#define VMX_ERROR_VMCLEAR_INVALID_VMXON_PTR 3
140/** 4 VMLAUNCH with non-clear VMCS. */
141#define VMX_ERROR_VMLAUCH_NON_CLEAR_VMCS 4
142/** 5 VMRESUME with non-launched VMCS. */
143#define VMX_ERROR_VMRESUME_NON_LAUNCHED_VMCS 5
144/** 6 VMRESUME with a corrupted VMCS (indicates corruption of the current VMCS). */
145#define VMX_ERROR_VMRESUME_CORRUPTED_VMCS 6
146/** 7 VM entry with invalid control field(s). */
147#define VMX_ERROR_VMENTRY_INVALID_CONTROL_FIELDS 7
148/** 8 VM entry with invalid host-state field(s). */
149#define VMX_ERROR_VMENTRY_INVALID_HOST_STATE 8
150/** 9 VMPTRLD with invalid physical address. */
151#define VMX_ERROR_VMPTRLD_INVALID_PHYS_ADDR 9
152/** 10 VMPTRLD with VMXON pointer. */
153#define VMX_ERROR_VMPTRLD_VMXON_PTR 10
154/** 11 VMPTRLD with incorrect VMCS revision identifier. */
155#define VMX_ERROR_VMPTRLD_WRONG_VMCS_REVISION 11
156/** 12 VMREAD/VMWRITE from/to unsupported VMCS component. */
157#define VMX_ERROR_VMREAD_INVALID_COMPONENT 12
158#define VMX_ERROR_VMWRITE_INVALID_COMPONENT VMX_ERROR_VMREAD_INVALID_COMPONENT
159/** 13 VMWRITE to read-only VMCS component. */
160#define VMX_ERROR_VMWRITE_READONLY_COMPONENT 13
161/** 15 VMXON executed in VMX root operation. */
162#define VMX_ERROR_VMXON_IN_VMX_ROOT_OP 15
163/** 16 VM entry with invalid executive-VMCS pointer. */
164#define VMX_ERROR_VMENTRY_INVALID_VMCS_EXEC_PTR 16
165/** 17 VM entry with non-launched executive VMCS. */
166#define VMX_ERROR_VMENTRY_NON_LAUNCHED_EXEC_VMCS 17
167/** 18 VM entry with executive-VMCS pointer not VMXON pointer. */
168#define VMX_ERROR_VMENTRY_EXEC_VMCS_PTR 18
169/** 19 VMCALL with non-clear VMCS. */
170#define VMX_ERROR_VMCALL_NON_CLEAR_VMCS 19
171/** 20 VMCALL with invalid VM-exit control fields. */
172#define VMX_ERROR_VMCALL_INVALID_VMEXIT_FIELDS 20
173/** 22 VMCALL with incorrect MSEG revision identifier. */
174#define VMX_ERROR_VMCALL_INVALID_MSEG_REVISION 22
175/** 23 VMXOFF under dual-monitor treatment of SMIs and SMM. */
176#define VMX_ERROR_VMXOFF_DUAL_MONITOR 23
177/** 24 VMCALL with invalid SMM-monitor features. */
178#define VMX_ERROR_VMCALL_INVALID_SMM_MONITOR 24
179/** 25 VM entry with invalid VM-execution control fields in executive VMCS. */
180#define VMX_ERROR_VMENTRY_INVALID_VM_EXEC_CTRL 25
181/** 26 VM entry with events blocked by MOV SS. */
182#define VMX_ERROR_VMENTRY_MOV_SS 26
183
184/** @} */
185
186
187/** VMX MSR bit definitions
188 * @{
189 */
190
191/** Basic VMX information.
192 * @{
193 */
194/** VMCS revision identifier used by the processor. */
195#define MSR_IA32_VMX_BASIC_INFO_VMCS_ID(a) (a & 0x7FFFFFFF)
196/** Size of the VMCS. */
197#define MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(a) ((a >> 32ULL) & 0xFFF)
198/** Width of physical address used for the VMCS.
199 * 0 -> limited to the available amount of physical ram
200 * 1 -> within the first 4 GB
201 */
202#define MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(a) ((a >> 48ULL) & 1)
203/** Whether the processor supports the dual-monitor treatment of system-management interrupts and system-management code. (always 1) */
204#define MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(a) ((a >> 49ULL) & 1)
205/** Memory type that must be used for the VMCS. */
206#define MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(a) ((a >> 50ULL) & 0xF)
207/** @} */
208
209
210/** Misc VMX info.
211 * @{
212 */
213/** Activity states supported by the implementation. */
214#define MSR_IA32_VMX_MISC_ACTIVITY_STATES(a) ((a >> 6ULL) & 0x7)
215/** Number of CR3 target values supported by the processor. (0-256) */
216#define MSR_IA32_VMX_MISC_CR3_TARGET(a) ((a >> 16ULL) & 0x1FF)
217/** Maximum nr of MSRs in the VMCS. (N+1)*512. */
218#define MSR_IA32_VMX_MISC_MAX_MSR(a) ((((a >> 25ULL) & 0x7) + 1) * 512)
219/** MSEG revision identifier used by the processor. */
220#define MSR_IA32_VMX_MISC_MSEG_ID(a) (a >> 32ULL)
221/** @} */
222
223
224/** VMCS enumeration field info
225 * @{
226 */
227/** Highest field index. */
228#define MSR_IA32_VMX_VMCS_ENUM_HIGHEST_INDEX(a) ((a >> 1ULL) & 0x1FF)
229
230/** @} */
231
232/** @} */
233
234
235/** VMCS field encoding
236 * @{
237 */
238
239/* 16 bits guest fields
240 * @{
241 */
242#define VMX_VMCS_GUEST_FIELD_ES 0x800
243#define VMX_VMCS_GUEST_FIELD_CS 0x802
244#define VMX_VMCS_GUEST_FIELD_SS 0x804
245#define VMX_VMCS_GUEST_FIELD_DS 0x806
246#define VMX_VMCS_GUEST_FIELD_FS 0x808
247#define VMX_VMCS_GUEST_FIELD_GS 0x80A
248#define VMX_VMCS_GUEST_FIELD_LDTR 0x80C
249#define VMX_VMCS_GUEST_FIELD_TR 0x80E
250/** @} */
251
252/** 16 bits host fields
253 * @{
254 */
255#define VMX_VMCS_HOST_FIELD_ES 0xC00
256#define VMX_VMCS_HOST_FIELD_CS 0xC02
257#define VMX_VMCS_HOST_FIELD_SS 0xC04
258#define VMX_VMCS_HOST_FIELD_DS 0xC06
259#define VMX_VMCS_HOST_FIELD_FS 0xC08
260#define VMX_VMCS_HOST_FIELD_GS 0xC0A
261#define VMX_VMCS_HOST_FIELD_TR 0xC0C
262/** @} */
263
264/** 64 Bits control fields
265 * @{
266 */
267#define VMX_VMCS_CTRL_IO_BITMAP_A_FULL 0x2000
268#define VMX_VMCS_CTRL_IO_BITMAP_A_HIGH 0x2001
269#define VMX_VMCS_CTRL_IO_BITMAP_B_FULL 0x2002
270#define VMX_VMCS_CTRL_IO_BITMAP_B_HIGH 0x2003
271
272/* Optional */
273#define VMX_VMCS_CTRL_MSR_BITMAP_FULL 0x2004
274#define VMX_VMCS_CTRL_MSR_BITMAP_HIGH 0x2005
275
276#define VMX_VMCS_CTRL_VMEXIT_MSR_STORE_FULL 0x2006
277#define VMX_VMCS_CTRL_VMEXIT_MSR_STORE_HIGH 0x2007
278#define VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_FULL 0x2008
279#define VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_HIGH 0x2009
280
281#define VMX_VMCS_CTRL_VMENTRY_MSR_LOAD_FULL 0x200A
282#define VMX_VMCS_CTRL_VMENTRY_MSR_LOAD_HIGH 0x200B
283
284#define VMX_VMCS_CTRL_EXEC_VMCS_PTR_FULL 0x200C
285#define VMX_VMCS_CTRL_EXEC_VMCS_PTR_HIGH 0x200D
286
287#define VMX_VMCS_CTRL_TSC_OFFSET_FULL 0x2010
288#define VMX_VMCS_CTRL_TSC_OFFSET_HIGH 0x2011
289
290/* Optional */
291#define VMX_VMCS_CTRL_VAPIC_PAGEADDR_FULL 0x2012
292#define VMX_VMCS_CTRL_VAPIC_PAGEADDR_HIGH 0x2013
293/** @} */
294
295
296/** 64 Bits guest fields
297 * @{
298 */
299#define VMX_VMCS_GUEST_LINK_PTR_FULL 0x2800
300#define VMX_VMCS_GUEST_LINK_PTR_HIGH 0x2801
301#define VMX_VMCS_GUEST_DEBUGCTL_FULL 0x2802 /* MSR IA32_DEBUGCTL */
302#define VMX_VMCS_GUEST_DEBUGCTL_HIGH 0x2803 /* MSR IA32_DEBUGCTL */
303/** @} */
304
305
306/** 32 Bits control fields
307 * @{
308 */
309#define VMX_VMCS_CTRL_PIN_EXEC_CONTROLS 0x4000
310#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS 0x4002
311#define VMX_VMCS_CTRL_EXCEPTION_BITMAP 0x4004
312#define VMX_VMCS_CTRL_PAGEFAULT_ERROR_MASK 0x4006
313#define VMX_VMCS_CTRL_PAGEFAULT_ERROR_MATCH 0x4008
314#define VMX_VMCS_CTRL_CR3_TARGET_COUNT 0x400A
315#define VMX_VMCS_CTRL_EXIT_CONTROLS 0x400C
316#define VMX_VMCS_CTRL_EXIT_MSR_STORE_COUNT 0x400E
317#define VMX_VMCS_CTRL_EXIT_MSR_LOAD_COUNT 0x4010
318#define VMX_VMCS_CTRL_ENTRY_CONTROLS 0x4012
319#define VMX_VMCS_CTRL_ENTRY_MSR_LOAD_COUNT 0x4014
320#define VMX_VMCS_CTRL_ENTRY_IRQ_INFO 0x4016
321#define VMX_VMCS_CTRL_ENTRY_EXCEPTION_ERRCODE 0x4018
322#define VMX_VMCS_CTRL_ENTRY_INSTR_LENGTH 0x401A
323/* Optional */
324#define VMX_VMCS_CTRL_TPR_TRESHOLD 0x401C
325/** @} */
326
327
328/** VMX_VMCS_CTRL_PIN_EXEC_CONTROLS
329 * @{
330 */
331/* External interrupts cause VM exits if set; otherwise dispatched through the guest's IDT. */
332#define VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT RT_BIT(0)
333/* Non-maskable interrupts cause VM exits if set; otherwise dispatched through the guest's IDT. */
334#define VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT RT_BIT(3)
335/* All other bits are reserved and must be set according to MSR IA32_VMX_PROCBASED_CTLS. */
336/** @} */
337
338
339/** VMX_VMCS_CTRL_PROC_EXEC_CONTROLS
340 * @{
341 */
342/* VM Exit as soon as RFLAGS.IF=1 and no blocking is active. */
343#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT RT_BIT(2)
344/* Use timestamp counter offset. */
345#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET RT_BIT(3)
346/* VM Exit when executing the HLT instruction. */
347#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT RT_BIT(7)
348/* VM Exit when executing the INVLPG instruction. */
349#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT RT_BIT(9)
350/* VM Exit when executing the MWAIT instruction. */
351#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT RT_BIT(10)
352/* VM Exit when executing the RDPMC instruction. */
353#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT RT_BIT(11)
354/* VM Exit when executing the RDTSC instruction. */
355#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT RT_BIT(12)
356/* VM Exit on CR8 loads. */
357#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT RT_BIT(19)
358/* VM Exit on CR8 stores. */
359#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT RT_BIT(20)
360/* Use TPR shadow. */
361#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW RT_BIT(21)
362/* VM Exit when executing a MOV DRx instruction. */
363#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT RT_BIT(23)
364/* VM Exit when executing IO instructions. */
365#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT RT_BIT(24)
366/* Use IO bitmaps. */
367#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS RT_BIT(25)
368/* Use MSR bitmaps. */
369#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS RT_BIT(28)
370/* VM Exit when executing the MONITOR instruction. */
371#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT RT_BIT(29)
372/* VM Exit when executing the PAUSE instruction. */
373#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT RT_BIT(30)
374/** @} */
375
376
377/** VMX_VMCS_CTRL_ENTRY_CONTROLS
378 * @{
379 */
380/** 64 bits guest mode. Must be 0 for CPUs that don't support AMD64. */
381#define VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE RT_BIT(9)
382/** In SMM mode after VM-entry. */
383#define VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM RT_BIT(10)
384/** Disable dual treatment of SMI and SMM; must be zero for VM-entry outside of SMM. */
385#define VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON RT_BIT(11)
386/** @} */
387
388
389/** VMX_VMCS_CTRL_EXIT_CONTROLS
390 * @{
391 */
392/** Return to long mode after a VM-exit. */
393#define VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64 RT_BIT(9)
394/** Acknowledge external interrupts with the irq controller if one caused a VM-exit. */
395#define VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ RT_BIT(15)
396/** @} */
397
398/** 32 Bits read-only fields
399 * @{
400 */
401#define VMX_VMCS_RO_VM_INSTR_ERROR 0x4400
402#define VMX_VMCS_RO_EXIT_REASON 0x4402
403#define VMX_VMCS_RO_EXIT_INTERRUPTION_INFO 0x4404
404#define VMX_VMCS_RO_EXIT_INTERRUPTION_ERRCODE 0x4406
405#define VMX_VMCS_RO_IDT_INFO 0x4408
406#define VMX_VMCS_RO_IDT_ERRCODE 0x440A
407#define VMX_VMCS_RO_EXIT_INSTR_LENGTH 0x440C
408#define VMX_VMCS_RO_EXIT_INSTR_INFO 0x440E
409/** @} */
410
411/** VMX_VMCS_RO_EXIT_INTERRUPTION_INFO
412 * @{
413 */
414#define VMX_EXIT_INTERRUPTION_INFO_VECTOR(a) (a & 0xff)
415#define VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT 8
416#define VMX_EXIT_INTERRUPTION_INFO_TYPE(a) ((a >> VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT) & 7)
417#define VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID RT_BIT(11)
418#define VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID(a) (a & VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID)
419#define VMX_EXIT_INTERRUPTION_INFO_NMI_UNBLOCK(a) (a & RT_BIT(12))
420#define VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT 31
421#define VMX_EXIT_INTERRUPTION_INFO_VALID(a) (a & RT_BIT(31))
422/* Construct an irq event injection value from the exit interruption info value (same except that bit 12 is reserved). */
423#define VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(a) (a & ~RT_BIT(12))
424/** @} */
425
426/** VMX_VMCS_RO_EXIT_INTERRUPTION_INFO_TYPE
427 * @{
428 */
429#define VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT 0
430#define VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI 2
431#define VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT 3
432#define VMX_EXIT_INTERRUPTION_INFO_TYPE_SW 4 /* int xx */
433#define VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT 6
434/** @} */
435
436
437/** 32 Bits guest state fields
438 * @{
439 */
440#define VMX_VMCS_GUEST_ES_LIMIT 0x4800
441#define VMX_VMCS_GUEST_CS_LIMIT 0x4802
442#define VMX_VMCS_GUEST_SS_LIMIT 0x4804
443#define VMX_VMCS_GUEST_DS_LIMIT 0x4806
444#define VMX_VMCS_GUEST_FS_LIMIT 0x4808
445#define VMX_VMCS_GUEST_GS_LIMIT 0x480A
446#define VMX_VMCS_GUEST_LDTR_LIMIT 0x480C
447#define VMX_VMCS_GUEST_TR_LIMIT 0x480E
448#define VMX_VMCS_GUEST_GDTR_LIMIT 0x4810
449#define VMX_VMCS_GUEST_IDTR_LIMIT 0x4812
450#define VMX_VMCS_GUEST_ES_ACCESS_RIGHTS 0x4814
451#define VMX_VMCS_GUEST_CS_ACCESS_RIGHTS 0x4816
452#define VMX_VMCS_GUEST_SS_ACCESS_RIGHTS 0x4818
453#define VMX_VMCS_GUEST_DS_ACCESS_RIGHTS 0x481A
454#define VMX_VMCS_GUEST_FS_ACCESS_RIGHTS 0x481C
455#define VMX_VMCS_GUEST_GS_ACCESS_RIGHTS 0x481E
456#define VMX_VMCS_GUEST_LDTR_ACCESS_RIGHTS 0x4820
457#define VMX_VMCS_GUEST_TR_ACCESS_RIGHTS 0x4822
458#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE 0x4824
459#define VMX_VMCS_GUEST_ACTIVITY_STATE 0x4826
460#define VMX_VMCS_GUEST_SYSENTER_CS 0x482A /* MSR IA32_SYSENTER_CS */
461/** @} */
462
463
464/** VMX_VMCS_GUEST_ACTIVITY_STATE
465 * @{
466 */
467/* The logical processor is active. */
468#define VMX_CMS_GUEST_ACTIVITY_ACTIVE 0x0
469/* The logical processor is inactive, because executed a HLT instruction. */
470#define VMX_CMS_GUEST_ACTIVITY_HLT 0x1
471/* The logical processor is inactive, because of a triple fault or other serious error. */
472#define VMX_CMS_GUEST_ACTIVITY_SHUTDOWN 0x2
473/* The logical processor is inactive, because it's waiting for a startup-IPI */
474#define VMX_CMS_GUEST_ACTIVITY_SIPI_WAIT 0x3
475/** @} */
476
477
478/** VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE
479 * @{
480 */
481#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_STI RT_BIT(0)
482#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_MOVSS RT_BIT(1)
483#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_SMI RT_BIT(2)
484#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_NMI RT_BIT(3)
485/** @} */
486
487
488/** 32 Bits host state fields
489 * @{
490 */
491#define VMX_VMCS_HOST_SYSENTER_CS 0x4C00
492/** @} */
493
494/** Natural width control fields
495 * @{
496 */
497#define VMX_VMCS_CTRL_CR0_MASK 0x6000
498#define VMX_VMCS_CTRL_CR4_MASK 0x6002
499#define VMX_VMCS_CTRL_CR0_READ_SHADOW 0x6004
500#define VMX_VMCS_CTRL_CR4_READ_SHADOW 0x6006
501#define VMX_VMCS_CTRL_CR3_TARGET_VAL0 0x6008
502#define VMX_VMCS_CTRL_CR3_TARGET_VAL1 0x600A
503#define VMX_VMCS_CTRL_CR3_TARGET_VAL2 0x600C
504#define VMX_VMCS_CTRL_CR3_TARGET_VAL31 0x600E
505/** @} */
506
507
508/** Natural width read-only data fields
509 * @{
510 */
511#define VMX_VMCS_RO_EXIT_QUALIFICATION 0x6400
512#define VMX_VMCS_RO_IO_RCX 0x6402
513#define VMX_VMCS_RO_IO_RSX 0x6404
514#define VMX_VMCS_RO_IO_RDI 0x6406
515#define VMX_VMCS_RO_IO_RIP 0x6408
516#define VMX_VMCS_GUEST_LINEAR_ADDR 0x640A
517/** @} */
518
519
520/** VMX_VMCS_RO_EXIT_QUALIFICATION
521 * @{
522 */
523
524/** DRx moves
525 * @{
526 */
527/** 0-2: Debug register number */
528#define VMX_EXIT_QUALIFICATION_DRX_REGISTER(a) (a & 7)
529/** 3: Reserved; cleared to 0. */
530#define VMX_EXIT_QUALIFICATION_DRX_RES1(a) ((a >> 3) & 1)
531/** 4: Direction of move (0 = write, 1 = read) */
532#define VMX_EXIT_QUALIFICATION_DRX_DIRECTION(a) ((a >> 4) & 1)
533/** 5-7: Reserved; cleared to 0. */
534#define VMX_EXIT_QUALIFICATION_DRX_RES2(a) ((a >> 5) & 7)
535/** 8-11: General purpose register number. */
536#define VMX_EXIT_QUALIFICATION_DRX_GENREG(a) ((a >> 8) & 0xF)
537/** Rest: reserved. */
538
539/** VMX_EXIT_QUALIFICATION_DRX_DIRECTION
540 * @{
541 */
542#define VMX_EXIT_QUALIFICATION_DRX_DIRECTION_WRITE 0
543#define VMX_EXIT_QUALIFICATION_DRX_DIRECTION_READ 1
544/** @} */
545
546/** @} */
547
548
549/** CRx accesses
550 * @{
551 */
552/** 0-3: Control register number (0 for CLTS & LMSW) */
553#define VMX_EXIT_QUALIFICATION_CRX_REGISTER(a) (a & 0xF)
554/** 4-5: Access type. */
555#define VMX_EXIT_QUALIFICATION_CRX_ACCESS(a) ((a >> 4) & 3)
556/** 6: LMSW operand type */
557#define VMX_EXIT_QUALIFICATION_CRX_LMSW_OP(a) ((a >> 6) & 1)
558/** 7: Reserved; cleared to 0. */
559#define VMX_EXIT_QUALIFICATION_CRX_RES1(a) ((a >> 7) & 1)
560/** 8-11: General purpose register number (0 for CLTS & LMSW). */
561#define VMX_EXIT_QUALIFICATION_CRX_GENREG(a) ((a >> 8) & 0xF)
562/** 12-15: Reserved; cleared to 0. */
563#define VMX_EXIT_QUALIFICATION_CRX_RES2(a) ((a >> 12) & 0xF)
564/** 16-31: LMSW source data (else 0). */
565#define VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(a) ((a >> 16) & 0xFFFF)
566/** Rest: reserved. */
567
568
569/** VMX_EXIT_QUALIFICATION_CRX_ACCESS
570 * @{
571 */
572#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_WRITE 0
573#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_READ 1
574#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_CLTS 2
575#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_LMSW 3
576/** @} */
577
578/** @} */
579
580
581/** VMX_EXIT_PORT_IO
582 * @{
583 */
584/** 0-2: IO operation width. */
585#define VMX_EXIT_QUALIFICATION_IO_WIDTH(a) (a & 7)
586/** 3: IO operation direction. */
587#define VMX_EXIT_QUALIFICATION_IO_DIRECTION(a) ((a >> 3) & 1)
588/** 4: String IO operation. */
589#define VMX_EXIT_QUALIFICATION_IO_STRING(a) ((a >> 4) & 1)
590/** 5: Repeated IO operation. */
591#define VMX_EXIT_QUALIFICATION_IO_REP(a) ((a >> 5) & 1)
592/** 6: Operand encoding. */
593#define VMX_EXIT_QUALIFICATION_IO_ENCODING(a) ((a >> 6) & 1)
594/** 16-31: IO Port (0-0xffff). */
595#define VMX_EXIT_QUALIFICATION_IO_PORT(a) ((a >> 16) & 0xffff)
596/* Rest reserved. */
597/** @} */
598
599/** VMX_EXIT_QUALIFICATION_IO_DIRECTION
600 * @{
601 */
602#define VMX_EXIT_QUALIFICATION_IO_DIRECTION_OUT 0
603#define VMX_EXIT_QUALIFICATION_IO_DIRECTION_IN 1
604/** @} */
605
606
607/** VMX_EXIT_QUALIFICATION_IO_ENCODING
608 * @{
609 */
610#define VMX_EXIT_QUALIFICATION_IO_ENCODING_DX 0
611#define VMX_EXIT_QUALIFICATION_IO_ENCODING_IMM 1
612/** @} */
613
614/** @} */
615
616/** Natural width guest state fields
617 * @{
618 */
619#define VMX_VMCS_GUEST_CR0 0x6800
620#define VMX_VMCS_GUEST_CR3 0x6802
621#define VMX_VMCS_GUEST_CR4 0x6804
622#define VMX_VMCS_GUEST_ES_BASE 0x6806
623#define VMX_VMCS_GUEST_CS_BASE 0x6808
624#define VMX_VMCS_GUEST_SS_BASE 0x680A
625#define VMX_VMCS_GUEST_DS_BASE 0x680C
626#define VMX_VMCS_GUEST_FS_BASE 0x680E
627#define VMX_VMCS_GUEST_GS_BASE 0x6810
628#define VMX_VMCS_GUEST_LDTR_BASE 0x6812
629#define VMX_VMCS_GUEST_TR_BASE 0x6814
630#define VMX_VMCS_GUEST_GDTR_BASE 0x6816
631#define VMX_VMCS_GUEST_IDTR_BASE 0x6818
632#define VMX_VMCS_GUEST_DR7 0x681A
633#define VMX_VMCS_GUEST_RSP 0x681C
634#define VMX_VMCS_GUEST_RIP 0x681E
635#define VMX_VMCS_GUEST_RFLAGS 0x6820
636#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS 0x6822
637#define VMX_VMCS_GUEST_SYSENTER_ESP 0x6824 /* MSR IA32_SYSENTER_ESP */
638#define VMX_VMCS_GUEST_SYSENTER_EIP 0x6826 /* MSR IA32_SYSENTER_EIP */
639/** @} */
640
641
642/** VMX_VMCS_GUEST_DEBUG_EXCEPTIONS
643 * @{
644 */
645/* Hardware breakpoint 0 was met. */
646#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B0 RT_BIT(0)
647/* Hardware breakpoint 1 was met. */
648#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B1 RT_BIT(1)
649/* Hardware breakpoint 2 was met. */
650#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B2 RT_BIT(2)
651/* Hardware breakpoint 3 was met. */
652#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B3 RT_BIT(3)
653/* At least one data or IO breakpoint was hit. */
654#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_BREAKPOINT_ENABLED RT_BIT(12)
655/* A debug exception would have been triggered by single-step execution mode. */
656#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_BS RT_BIT(14)
657/* Bits 4-11, 13 and 15-63 are reserved. */
658
659
660
661
662/** @} */
663
664/** Natural width host state fields
665 * @{
666 */
667#define VMX_VMCS_HOST_CR0 0x6C00
668#define VMX_VMCS_HOST_CR3 0x6C02
669#define VMX_VMCS_HOST_CR4 0x6C04
670#define VMX_VMCS_HOST_FS_BASE 0x6C06
671#define VMX_VMCS_HOST_GS_BASE 0x6C08
672#define VMX_VMCS_HOST_TR_BASE 0x6C0A
673#define VMX_VMCS_HOST_GDTR_BASE 0x6C0C
674#define VMX_VMCS_HOST_IDTR_BASE 0x6C0E
675#define VMX_VMCS_HOST_SYSENTER_ESP 0x6C10
676#define VMX_VMCS_HOST_SYSENTER_EIP 0x6C12
677#define VMX_VMCS_HOST_RSP 0x6C14
678#define VMX_VMCS_HOST_RIP 0x6C16
679/** @} */
680
681/** @} */
682
683
684#if RT_INLINE_ASM_GNU_STYLE
685# define __STR(x) #x
686# define STR(x) __STR(x)
687#endif
688
689
690/** @} */
691
692/** @defgroup grp_vmx_asm vmx assembly helpers
693 * @ingroup grp_vmx
694 * @{
695 */
696
697/**
698 * Executes VMXON
699 *
700 * @returns VBox status code
701 * @param pVMXOn Physical address of VMXON structure
702 */
703#if RT_INLINE_ASM_EXTERNAL || HC_ARCH_BITS == 64
704DECLASM(int) VMXEnable(RTHCPHYS pVMXOn);
705#else
706DECLINLINE(int) VMXEnable(RTHCPHYS pVMXOn)
707{
708 int rc = VINF_SUCCESS;
709# if RT_INLINE_ASM_GNU_STYLE
710 __asm__ __volatile__ (
711 "push %3 \n\t"
712 "push %2 \n\t"
713 ".byte 0xF3, 0x0F, 0xC7, 0x34, 0x24 # VMXON [esp] \n\t"
714 "ja 2f \n\t"
715 "je 1f \n\t"
716 "movl $"STR(VERR_VMX_INVALID_VMXON_PTR)", %0 \n\t"
717 "jmp 2f \n\t"
718 "1: \n\t"
719 "movl $"STR(VERR_VMX_GENERIC)", %0 \n\t"
720 "2: \n\t"
721 "add $8, %%esp \n\t"
722 :"=rm"(rc)
723 :"0"(VINF_SUCCESS),
724 "ir"((uint32_t)pVMXOn), /* don't allow direct memory reference here, */
725 "ir"((uint32_t)(pVMXOn >> 32)) /* this would not work with -fomit-frame-pointer */
726 :"memory"
727 );
728# else
729 __asm
730 {
731 push dword ptr [pVMXOn+4]
732 push dword ptr [pVMXOn]
733 _emit 0xF3
734 _emit 0x0F
735 _emit 0xC7
736 _emit 0x34
737 _emit 0x24 /* VMXON [esp] */
738 jnc vmxon_good
739 mov dword ptr [rc], VERR_VMX_INVALID_VMXON_PTR
740 jmp the_end
741
742vmxon_good:
743 jnz the_end
744 mov dword ptr [rc], VERR_VMX_GENERIC
745the_end:
746 add esp, 8
747 }
748# endif
749 return rc;
750}
751#endif
752
753
754/**
755 * Executes VMXOFF
756 */
757#if RT_INLINE_ASM_EXTERNAL || HC_ARCH_BITS == 64
758DECLASM(void) VMXDisable(void);
759#else
760DECLINLINE(void) VMXDisable(void)
761{
762# if RT_INLINE_ASM_GNU_STYLE
763 __asm__ __volatile__ (
764 ".byte 0x0F, 0x01, 0xC4 # VMXOFF \n\t"
765 );
766# else
767 __asm
768 {
769 _emit 0x0F
770 _emit 0x01
771 _emit 0xC4 /* VMXOFF */
772 }
773# endif
774}
775#endif
776
777
778/**
779 * Executes VMCLEAR
780 *
781 * @returns VBox status code
782 * @param pVMCS Physical address of VM control structure
783 */
784#if RT_INLINE_ASM_EXTERNAL || HC_ARCH_BITS == 64
785DECLASM(int) VMXClearVMCS(RTHCPHYS pVMCS);
786#else
787DECLINLINE(int) VMXClearVMCS(RTHCPHYS pVMCS)
788{
789 int rc = VINF_SUCCESS;
790# if RT_INLINE_ASM_GNU_STYLE
791 __asm__ __volatile__ (
792 "push %3 \n\t"
793 "push %2 \n\t"
794 ".byte 0x66, 0x0F, 0xC7, 0x34, 0x24 # VMCLEAR [esp] \n\t"
795 "jnc 1f \n\t"
796 "movl $"STR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
797 "1: \n\t"
798 "add $8, %%esp \n\t"
799 :"=rm"(rc)
800 :"0"(VINF_SUCCESS),
801 "ir"((uint32_t)pVMCS), /* don't allow direct memory reference here, */
802 "ir"((uint32_t)(pVMCS >> 32)) /* this would not work with -fomit-frame-pointer */
803 :"memory"
804 );
805# else
806 __asm
807 {
808 push dword ptr [pVMCS+4]
809 push dword ptr [pVMCS]
810 _emit 0x66
811 _emit 0x0F
812 _emit 0xC7
813 _emit 0x34
814 _emit 0x24 /* VMCLEAR [esp] */
815 jnc success
816 mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
817success:
818 add esp, 8
819 }
820# endif
821 return rc;
822}
823#endif
824
825
826/**
827 * Executes VMPTRLD
828 *
829 * @returns VBox status code
830 * @param pVMCS Physical address of VMCS structure
831 */
832#if RT_INLINE_ASM_EXTERNAL || HC_ARCH_BITS == 64
833DECLASM(int) VMXActivateVMCS(RTHCPHYS pVMCS);
834#else
835DECLINLINE(int) VMXActivateVMCS(RTHCPHYS pVMCS)
836{
837 int rc = VINF_SUCCESS;
838# if RT_INLINE_ASM_GNU_STYLE
839 __asm__ __volatile__ (
840 "push %3 \n\t"
841 "push %2 \n\t"
842 ".byte 0x0F, 0xC7, 0x34, 0x24 # VMPTRLD [esp] \n\t"
843 "jnc 1f \n\t"
844 "movl $"STR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
845 "1: \n\t"
846 "add $8, %%esp \n\t"
847 :"=rm"(rc)
848 :"0"(VINF_SUCCESS),
849 "ir"((uint32_t)pVMCS), /* don't allow direct memory reference here, */
850 "ir"((uint32_t)(pVMCS >> 32)) /* this will not work with -fomit-frame-pointer */
851 );
852# else
853 __asm
854 {
855 push dword ptr [pVMCS+4]
856 push dword ptr [pVMCS]
857 _emit 0x0F
858 _emit 0xC7
859 _emit 0x34
860 _emit 0x24 /* VMPTRLD [esp] */
861 jnc success
862 mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
863
864success:
865 add esp, 8
866 }
867# endif
868 return rc;
869}
870#endif
871
872
873/**
874 * Executes VMWRITE
875 *
876 * @returns VBox status code
877 * @param idxField VMCS index
878 * @param u64Val 16, 32 or 64 bits value
879 */
880DECLASM(int) VMXWriteVMCS64(uint32_t idxField, uint64_t u64Val);
881
882/**
883 * Executes VMWRITE
884 *
885 * @returns VBox status code
886 * @param idxField VMCS index
887 * @param u32Val 32 bits value
888 */
889#if RT_INLINE_ASM_EXTERNAL || HC_ARCH_BITS == 64
890DECLASM(int) VMXWriteVMCS32(uint32_t idxField, uint32_t u32Val);
891#else
892DECLINLINE(int) VMXWriteVMCS32(uint32_t idxField, uint32_t u32Val)
893{
894 int rc = VINF_SUCCESS;
895# if RT_INLINE_ASM_GNU_STYLE
896 __asm__ __volatile__ (
897 ".byte 0x0F, 0x79, 0xC2 # VMWRITE eax, edx \n\t"
898 "ja 2f \n\t"
899 "je 1f \n\t"
900 "movl $"STR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
901 "jmp 2f \n\t"
902 "1: \n\t"
903 "movl $"STR(VERR_VMX_INVALID_VMCS_FIELD)", %0 \n\t"
904 "2: \n\t"
905 :"=rm"(rc)
906 :"0"(VINF_SUCCESS),
907 "a"(idxField),
908 "d"(u32Val)
909 );
910# else
911 __asm
912 {
913 push dword ptr [u32Val]
914 mov eax, [idxField]
915 _emit 0x0F
916 _emit 0x79
917 _emit 0x04
918 _emit 0x24 /* VMWRITE eax, [esp] */
919 jnc valid_vmcs
920 mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
921 jmp the_end
922
923valid_vmcs:
924 jnz the_end
925 mov dword ptr [rc], VERR_VMX_INVALID_VMCS_FIELD
926the_end:
927 add esp, 4
928 }
929# endif
930 return rc;
931}
932#endif
933
934#if HC_ARCH_BITS == 64
935#define VMXWriteVMCS VMXWriteVMCS64
936#else
937#define VMXWriteVMCS VMXWriteVMCS32
938#endif /* HC_ARCH_BITS == 64 */
939
940
941/**
942 * Executes VMREAD
943 *
944 * @returns VBox status code
945 * @param idxField VMCS index
946 * @param pData Ptr to store VM field value
947 */
948DECLASM(int) VMXReadVMCS64(uint32_t idxField, uint64_t *pData);
949
950/**
951 * Executes VMREAD
952 *
953 * @returns VBox status code
954 * @param idxField VMCS index
955 * @param pData Ptr to store VM field value
956 */
957#if RT_INLINE_ASM_EXTERNAL || HC_ARCH_BITS == 64
958DECLASM(int) VMXReadVMCS32(uint32_t idxField, uint32_t *pData);
959#else
960DECLINLINE(int) VMXReadVMCS32(uint32_t idxField, uint32_t *pData)
961{
962 int rc = VINF_SUCCESS;
963# if RT_INLINE_ASM_GNU_STYLE
964 __asm__ __volatile__ (
965 "movl $"STR(VINF_SUCCESS)", %0 \n\t"
966 ".byte 0x0F, 0x78, 0xc2 # VMREAD eax, edx \n\t"
967 "ja 2f \n\t"
968 "je 1f \n\t"
969 "movl $"STR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
970 "jmp 2f \n\t"
971 "1: \n\t"
972 "movl $"STR(VERR_VMX_INVALID_VMCS_FIELD)", %0 \n\t"
973 "2: \n\t"
974 :"=&r"(rc),
975 "=d"(*pData)
976 :"a"(idxField),
977 "d"(0)
978 );
979# else
980 __asm
981 {
982 sub esp, 4
983 mov dword ptr [esp], 0
984 mov eax, [idxField]
985 _emit 0x0F
986 _emit 0x78
987 _emit 0x04
988 _emit 0x24 /* VMREAD eax, [esp] */
989 mov edx, pData
990 pop dword ptr [edx]
991 jnc valid_vmcs
992 mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
993 jmp the_end
994
995valid_vmcs:
996 jnz the_end
997 mov dword ptr [rc], VERR_VMX_INVALID_VMCS_FIELD
998the_end:
999 }
1000# endif
1001 return rc;
1002}
1003#endif
1004
1005#if HC_ARCH_BITS == 64
1006#define VMXReadVMCS VMXReadVMCS64
1007#else
1008#define VMXReadVMCS VMXReadVMCS32
1009#endif /* HC_ARCH_BITS == 64 */
1010
1011/**
1012 * Prepares for and executes VMLAUNCH
1013 *
1014 * @returns VBox status code
1015 * @param pCtx Guest context
1016 */
1017DECLASM(int) VMXStartVM(PCPUMCTX pCtx);
1018
1019/**
1020 * Prepares for and executes VMRESUME
1021 *
1022 * @returns VBox status code
1023 * @param pCtx Guest context
1024 */
1025DECLASM(int) VMXResumeVM(PCPUMCTX pCtx);
1026
1027/**
1028 * Gets the last instruction error value from the current VMCS
1029 *
1030 * @returns error value
1031 */
1032DECLINLINE(uint32_t) VMXGetLastError(void)
1033{
1034#if HC_ARCH_BITS == 64
1035 uint64_t uLastError = 0;
1036 int rc = VMXReadVMCS(VMX_VMCS_RO_VM_INSTR_ERROR, &uLastError);
1037 AssertRC(rc);
1038 return (uint32_t)uLastError;
1039
1040#else /* 32-bit host: */
1041 uint32_t lasterr = 0;
1042 int rc;
1043
1044 rc = VMXReadVMCS32(VMX_VMCS_RO_VM_INSTR_ERROR, &lasterr);
1045 AssertRC(rc);
1046 return lasterr;
1047#endif
1048}
1049
1050/** @} */
1051
1052#endif
1053
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