VirtualBox

source: vbox/trunk/include/VBox/hwacc_vmx.h@ 11814

Last change on this file since 11814 was 11756, checked in by vboxsync, 16 years ago

Use the wbinvd intercept if it's present in the secondary control.
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1/** @file
2 * HWACC/VMX - VMX Structures and Definitions.
3 */
4
5/*
6 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * The contents of this file may alternatively be used under the terms
17 * of the Common Development and Distribution License Version 1.0
18 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19 * VirtualBox OSE distribution, in which case the provisions of the
20 * CDDL are applicable instead of those of the GPL.
21 *
22 * You may elect to license modified versions of this file under the
23 * terms and conditions of either the GPL or the CDDL or both.
24 *
25 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
26 * Clara, CA 95054 USA or visit http://www.sun.com if you need
27 * additional information or have any questions.
28 */
29
30#ifndef ___VBox_vmx_h
31#define ___VBox_vmx_h
32
33#include <VBox/types.h>
34#include <VBox/err.h>
35#include <iprt/assert.h>
36#include <iprt/asm.h>
37
38/** @defgroup grp_vmx vmx Types and Definitions
39 * @ingroup grp_hwaccm
40 * @{
41 */
42
43/**
44 * Extended Page Directory Pointer. Bit view.
45 */
46#pragma pack(1)
47typedef struct VTXEPTPBITS
48{
49 /** EPT Table Memory Type. */
50 uint64_t u3ETMT : 3;
51 /** Guest Address Width. */
52 uint64_t u3GAW : 3;
53 /** Reserved. */
54 uint64_t u6Reserved : 6;
55 /** Address Space Root; page frame address of the first level EPT page. Actual width depends on the maximum physical address width of the CPU. */
56 uint64_t u52ASR : 52;
57} VTXEPTPBITS;
58#pragma pack()
59/** Pointer to an extended page directory pointer. */
60typedef VTXEPTPBITS *PVTXEPTPBITS;
61/** Pointer to a const extended page directory pointer. */
62typedef const VTXEPTPBITS *PCVTXEPTPBITS;
63
64/**
65 * Extended Page Directory Pointer.
66 */
67#pragma pack(1)
68typedef union VTXEPTP
69{
70 VTXEPTPBITS n;
71 /** 64 bit unsigned integer view. */
72 uint64_t au64[1];
73} VTXEPTP;
74#pragma pack()
75/** Pointer to an extended page directory pointer. */
76typedef VTXEPTP *PVTXEPTP;
77/** Pointer to a const extended page directory pointer. */
78typedef const VTXEPTP *PCVTXEPTP;
79
80
81/**
82 * Extended Page Directory Table Entry. Bit view.
83 */
84#pragma pack(1)
85typedef union VTXEPTEBITS
86{
87 /** Readable bit. */
88 uint64_t u1Readable : 1;
89 /** Writable bit. */
90 uint64_t u1Writable : 1;
91 /** Executable bit. */
92 uint64_t u1Executable : 1;
93 /** EPT Table Memory Type. MBZ for non-leaf nodes. */
94 uint64_t u3EMT : 3;
95 /** IGMT (Ignore Guest Memory Type) (leaf nodes). MBZ for non-leaf nodes. */
96 uint64_t u1IGMT : 1;
97 /** Super page (non-leaf) / available (leaf). */
98 uint64_t u1SP : 1;
99 /** Available for software. */
100 uint64_t u4Available : 4;
101 /** Physical address of next leaf/super page. Restricted by maximum physical address width of the cpu. */
102 uint64_t u45PhysAddr : 45;
103 /** Reserved (MBZ). */
104 uint64_t u5Reserved : 5;
105 /** Availabe for software. */
106 uint64_t u2Available : 2;
107} VTXEPTEBITS;
108#pragma pack()
109/** Pointer to an extended page table entry. */
110typedef VTXEPTEBITS *PVTXEPTEBITS;
111/** Pointer to a const extended table entry. */
112typedef const VTXEPTEBITS *PCVTXEPTEBITS;
113
114/**
115 * Extended Page Directory Table Entry.
116 */
117#pragma pack(1)
118typedef union VTXEPTE
119{
120 VTXEPTEBITS n;
121 /** 64 bit unsigned integer view. */
122 uint64_t au64[1];
123} VTXEPTE;
124#pragma pack()
125/** Pointer to an extended page table entry. */
126typedef VTXEPTE *PVTXEPTE;
127/** Pointer to a const extended table entry. */
128typedef const VTXEPTE *PCVTXEPTE;
129
130/**
131 * Number of page table entries in the EPT.
132 */
133#define VTX_PT_ENTRIES 512
134
135/**
136 * Extended Page Directory Table.
137 */
138#pragma pack(1)
139typedef union VTXEPT
140{
141 VTXEPTE a[VTX_PT_ENTRIES];
142} VTXEPT;
143#pragma pack()
144/** Pointer to an extended page table. */
145typedef VTXEPT *PVTXEPT;
146/** Pointer to a const extended table. */
147typedef const VTXEPT *PCVTXEPT;
148
149/** VMX Basic Exit Reasons.
150 * @{
151 */
152/* And-mask for setting reserved bits to zero */
153#define VMX_EFLAGS_RESERVED_0 (~0xffc08028)
154/* Or-mask for setting reserved bits to 1 */
155#define VMX_EFLAGS_RESERVED_1 0x00000002
156/** @} */
157
158/** VMX Basic Exit Reasons.
159 * @{
160 */
161/** 0 Exception or non-maskable interrupt (NMI). */
162#define VMX_EXIT_EXCEPTION 0
163/** 1 External interrupt. */
164#define VMX_EXIT_EXTERNAL_IRQ 1
165/** 2 Triple fault. */
166#define VMX_EXIT_TRIPLE_FAULT 2
167/** 3 INIT signal. */
168#define VMX_EXIT_INIT_SIGNAL 3
169/** 4 Start-up IPI (SIPI). */
170#define VMX_EXIT_SIPI 4
171/** 5 I/O system-management interrupt (SMI). */
172#define VMX_EXIT_IO_SMI_IRQ 5
173/** 6 Other SMI. */
174#define VMX_EXIT_SMI_IRQ 6
175/** 7 Interrupt window. */
176#define VMX_EXIT_IRQ_WINDOW 7
177/** 9 Task switch. */
178#define VMX_EXIT_TASK_SWITCH 9
179/** 10 Guest software attempted to execute CPUID. */
180#define VMX_EXIT_CPUID 10
181/** 12 Guest software attempted to execute HLT. */
182#define VMX_EXIT_HLT 12
183/** 13 Guest software attempted to execute INVD. */
184#define VMX_EXIT_INVD 13
185/** 14 Guest software attempted to execute INVPG. */
186#define VMX_EXIT_INVPG 14
187/** 15 Guest software attempted to execute RDPMC. */
188#define VMX_EXIT_RDPMC 15
189/** 16 Guest software attempted to execute RDTSC. */
190#define VMX_EXIT_RDTSC 16
191/** 17 Guest software attempted to execute RSM in SMM. */
192#define VMX_EXIT_RSM 17
193/** 18 Guest software executed VMCALL. */
194#define VMX_EXIT_VMCALL 18
195/** 19 Guest software executed VMCLEAR. */
196#define VMX_EXIT_VMCLEAR 19
197/** 20 Guest software executed VMLAUNCH. */
198#define VMX_EXIT_VMLAUNCH 20
199/** 21 Guest software executed VMPTRLD. */
200#define VMX_EXIT_VMPTRLD 21
201/** 22 Guest software executed VMPTRST. */
202#define VMX_EXIT_VMPTRST 22
203/** 23 Guest software executed VMREAD. */
204#define VMX_EXIT_VMREAD 23
205/** 24 Guest software executed VMRESUME. */
206#define VMX_EXIT_VMRESUME 24
207/** 25 Guest software executed VMWRITE. */
208#define VMX_EXIT_VMWRITE 25
209/** 26 Guest software executed VMXOFF. */
210#define VMX_EXIT_VMXOFF 26
211/** 27 Guest software executed VMXON. */
212#define VMX_EXIT_VMXON 27
213/** 28 Control-register accesses. */
214#define VMX_EXIT_CRX_MOVE 28
215/** 29 Debug-register accesses. */
216#define VMX_EXIT_DRX_MOVE 29
217/** 30 I/O instruction. */
218#define VMX_EXIT_PORT_IO 30
219/** 31 RDMSR. Guest software attempted to execute RDMSR. */
220#define VMX_EXIT_RDMSR 31
221/** 32 WRMSR. Guest software attempted to execute WRMSR. */
222#define VMX_EXIT_WRMSR 32
223/** 33 VM-entry failure due to invalid guest state. */
224#define VMX_EXIT_ERR_INVALID_GUEST_STATE 33
225/** 34 VM-entry failure due to MSR loading. */
226#define VMX_EXIT_ERR_MSR_LOAD 34
227/** 36 Guest software executed MWAIT. */
228#define VMX_EXIT_MWAIT 36
229/** 39 Guest software attempted to execute MONITOR. */
230#define VMX_EXIT_MONITOR 39
231/** 40 Guest software attempted to execute PAUSE. */
232#define VMX_EXIT_PAUSE 40
233/** 41 VM-entry failure due to machine-check. */
234#define VMX_EXIT_ERR_MACHINE_CHECK 41
235/** 43 TPR below threshold. Guest software executed MOV to CR8. */
236#define VMX_EXIT_TPR 43
237/** 54 WBINVD. Guest software attempted to execute WBINVD. */
238#define VMX_EXIT_WBINVD 54
239
240/** @} */
241
242
243/** VM Instruction Errors
244 * @{
245 */
246/** 1 VMCALL executed in VMX root operation. */
247#define VMX_ERROR_VMCALL 1
248/** 2 VMCLEAR with invalid physical address. */
249#define VMX_ERROR_VMCLEAR_INVALID_PHYS_ADDR 2
250/** 3 VMCLEAR with VMXON pointer. */
251#define VMX_ERROR_VMCLEAR_INVALID_VMXON_PTR 3
252/** 4 VMLAUNCH with non-clear VMCS. */
253#define VMX_ERROR_VMLAUCH_NON_CLEAR_VMCS 4
254/** 5 VMRESUME with non-launched VMCS. */
255#define VMX_ERROR_VMRESUME_NON_LAUNCHED_VMCS 5
256/** 6 VMRESUME with a corrupted VMCS (indicates corruption of the current VMCS). */
257#define VMX_ERROR_VMRESUME_CORRUPTED_VMCS 6
258/** 7 VM entry with invalid control field(s). */
259#define VMX_ERROR_VMENTRY_INVALID_CONTROL_FIELDS 7
260/** 8 VM entry with invalid host-state field(s). */
261#define VMX_ERROR_VMENTRY_INVALID_HOST_STATE 8
262/** 9 VMPTRLD with invalid physical address. */
263#define VMX_ERROR_VMPTRLD_INVALID_PHYS_ADDR 9
264/** 10 VMPTRLD with VMXON pointer. */
265#define VMX_ERROR_VMPTRLD_VMXON_PTR 10
266/** 11 VMPTRLD with incorrect VMCS revision identifier. */
267#define VMX_ERROR_VMPTRLD_WRONG_VMCS_REVISION 11
268/** 12 VMREAD/VMWRITE from/to unsupported VMCS component. */
269#define VMX_ERROR_VMREAD_INVALID_COMPONENT 12
270#define VMX_ERROR_VMWRITE_INVALID_COMPONENT VMX_ERROR_VMREAD_INVALID_COMPONENT
271/** 13 VMWRITE to read-only VMCS component. */
272#define VMX_ERROR_VMWRITE_READONLY_COMPONENT 13
273/** 15 VMXON executed in VMX root operation. */
274#define VMX_ERROR_VMXON_IN_VMX_ROOT_OP 15
275/** 16 VM entry with invalid executive-VMCS pointer. */
276#define VMX_ERROR_VMENTRY_INVALID_VMCS_EXEC_PTR 16
277/** 17 VM entry with non-launched executive VMCS. */
278#define VMX_ERROR_VMENTRY_NON_LAUNCHED_EXEC_VMCS 17
279/** 18 VM entry with executive-VMCS pointer not VMXON pointer. */
280#define VMX_ERROR_VMENTRY_EXEC_VMCS_PTR 18
281/** 19 VMCALL with non-clear VMCS. */
282#define VMX_ERROR_VMCALL_NON_CLEAR_VMCS 19
283/** 20 VMCALL with invalid VM-exit control fields. */
284#define VMX_ERROR_VMCALL_INVALID_VMEXIT_FIELDS 20
285/** 22 VMCALL with incorrect MSEG revision identifier. */
286#define VMX_ERROR_VMCALL_INVALID_MSEG_REVISION 22
287/** 23 VMXOFF under dual-monitor treatment of SMIs and SMM. */
288#define VMX_ERROR_VMXOFF_DUAL_MONITOR 23
289/** 24 VMCALL with invalid SMM-monitor features. */
290#define VMX_ERROR_VMCALL_INVALID_SMM_MONITOR 24
291/** 25 VM entry with invalid VM-execution control fields in executive VMCS. */
292#define VMX_ERROR_VMENTRY_INVALID_VM_EXEC_CTRL 25
293/** 26 VM entry with events blocked by MOV SS. */
294#define VMX_ERROR_VMENTRY_MOV_SS 26
295
296/** @} */
297
298
299/** VMX MSR bit definitions
300 * @{
301 */
302
303/** Basic VMX information.
304 * @{
305 */
306/** VMCS revision identifier used by the processor. */
307#define MSR_IA32_VMX_BASIC_INFO_VMCS_ID(a) (a & 0x7FFFFFFF)
308/** Size of the VMCS. */
309#define MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(a) ((a >> 32ULL) & 0xFFF)
310/** Width of physical address used for the VMCS.
311 * 0 -> limited to the available amount of physical ram
312 * 1 -> within the first 4 GB
313 */
314#define MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(a) ((a >> 48ULL) & 1)
315/** Whether the processor supports the dual-monitor treatment of system-management interrupts and system-management code. (always 1) */
316#define MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(a) ((a >> 49ULL) & 1)
317/** Memory type that must be used for the VMCS. */
318#define MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(a) ((a >> 50ULL) & 0xF)
319/** @} */
320
321
322/** Misc VMX info.
323 * @{
324 */
325/** Activity states supported by the implementation. */
326#define MSR_IA32_VMX_MISC_ACTIVITY_STATES(a) ((a >> 6ULL) & 0x7)
327/** Number of CR3 target values supported by the processor. (0-256) */
328#define MSR_IA32_VMX_MISC_CR3_TARGET(a) ((a >> 16ULL) & 0x1FF)
329/** Maximum nr of MSRs in the VMCS. (N+1)*512. */
330#define MSR_IA32_VMX_MISC_MAX_MSR(a) ((((a >> 25ULL) & 0x7) + 1) * 512)
331/** MSEG revision identifier used by the processor. */
332#define MSR_IA32_VMX_MISC_MSEG_ID(a) (a >> 32ULL)
333/** @} */
334
335
336/** VMCS enumeration field info
337 * @{
338 */
339/** Highest field index. */
340#define MSR_IA32_VMX_VMCS_ENUM_HIGHEST_INDEX(a) ((a >> 1ULL) & 0x1FF)
341
342/** @} */
343
344
345/** MSR_IA32_VMX_EPT_CAPS; EPT capabilities MSR
346 * @{
347 */
348#define MSR_IA32_VMX_EPT_CAPS_RWX_X_ONLY RT_BIT_64(0)
349#define MSR_IA32_VMX_EPT_CAPS_RWX_W_ONLY RT_BIT_64(1)
350#define MSR_IA32_VMX_EPT_CAPS_RWX_WX_ONLY RT_BIT_64(2)
351#define MSR_IA32_VMX_EPT_CAPS_GAW_21_BITS RT_BIT_64(3)
352#define MSR_IA32_VMX_EPT_CAPS_GAW_30_BITS RT_BIT_64(4)
353#define MSR_IA32_VMX_EPT_CAPS_GAW_39_BITS RT_BIT_64(5)
354#define MSR_IA32_VMX_EPT_CAPS_GAW_48_BITS RT_BIT_64(6)
355#define MSR_IA32_VMX_EPT_CAPS_GAW_57_BITS RT_BIT_64(7)
356#define MSR_IA32_VMX_EPT_CAPS_EMT_UC RT_BIT_64(8)
357#define MSR_IA32_VMX_EPT_CAPS_EMT_WC RT_BIT_64(9)
358#define MSR_IA32_VMX_EPT_CAPS_EMT_WT RT_BIT_64(12)
359#define MSR_IA32_VMX_EPT_CAPS_EMT_WP RT_BIT_64(13)
360#define MSR_IA32_VMX_EPT_CAPS_EMT_WB RT_BIT_64(14)
361#define MSR_IA32_VMX_EPT_CAPS_SP_21_BITS RT_BIT_64(16)
362#define MSR_IA32_VMX_EPT_CAPS_SP_30_BITS RT_BIT_64(17)
363#define MSR_IA32_VMX_EPT_CAPS_SP_39_BITS RT_BIT_64(18)
364#define MSR_IA32_VMX_EPT_CAPS_SP_48_BITS RT_BIT_64(19)
365#define MSR_IA32_VMX_EPT_CAPS_INVEPT RT_BIT_64(20)
366#define MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV RT_BIT_64(24)
367#define MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT RT_BIT_64(25)
368#define MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL RT_BIT_64(26)
369#define MSR_IA32_VMX_EPT_CAPS_INVVPID RT_BIT_64(32)
370#define MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV RT_BIT_64(40)
371#define MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT RT_BIT_64(41)
372#define MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL RT_BIT_64(42)
373#define MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT_GLOBAL RT_BIT_64(43)
374
375/** @} */
376
377/** @} */
378
379
380/** VMCS field encoding
381 * @{
382 */
383
384/* 16 bits guest fields
385 * @{
386 */
387#define VMX_VMCS_GUEST_FIELD_VPID 0x0
388#define VMX_VMCS_GUEST_FIELD_ES 0x800
389#define VMX_VMCS_GUEST_FIELD_CS 0x802
390#define VMX_VMCS_GUEST_FIELD_SS 0x804
391#define VMX_VMCS_GUEST_FIELD_DS 0x806
392#define VMX_VMCS_GUEST_FIELD_FS 0x808
393#define VMX_VMCS_GUEST_FIELD_GS 0x80A
394#define VMX_VMCS_GUEST_FIELD_LDTR 0x80C
395#define VMX_VMCS_GUEST_FIELD_TR 0x80E
396/** @} */
397
398/** 16 bits host fields
399 * @{
400 */
401#define VMX_VMCS_HOST_FIELD_ES 0xC00
402#define VMX_VMCS_HOST_FIELD_CS 0xC02
403#define VMX_VMCS_HOST_FIELD_SS 0xC04
404#define VMX_VMCS_HOST_FIELD_DS 0xC06
405#define VMX_VMCS_HOST_FIELD_FS 0xC08
406#define VMX_VMCS_HOST_FIELD_GS 0xC0A
407#define VMX_VMCS_HOST_FIELD_TR 0xC0C
408/** @} */
409
410/** 64 bits host fields
411 * @{
412 */
413#define VMX_VMCS_HOST_FIELD_PAT_FULL 0x2C00
414#define VMX_VMCS_HOST_FIELD_PAT_HIGH 0x2C01
415#define VMX_VMCS_HOST_FIELD_EFER_FULL 0x2C02
416#define VMX_VMCS_HOST_FIELD_EFER_HIGH 0x2C03
417#define VMX_VMCS_HOST_PERF_GLOBAL_CTRL_FULL 0x2C04 /* MSR IA32_PERF_GLOBAL_CTRL */
418#define VMX_VMCS_HOST_PERF_GLOBAL_CTRL_HIGH 0x2C05 /* MSR IA32_PERF_GLOBAL_CTRL */
419/** @} */
420
421
422/** 64 Bits control fields
423 * @{
424 */
425#define VMX_VMCS_CTRL_IO_BITMAP_A_FULL 0x2000
426#define VMX_VMCS_CTRL_IO_BITMAP_A_HIGH 0x2001
427#define VMX_VMCS_CTRL_IO_BITMAP_B_FULL 0x2002
428#define VMX_VMCS_CTRL_IO_BITMAP_B_HIGH 0x2003
429
430/* Optional */
431#define VMX_VMCS_CTRL_MSR_BITMAP_FULL 0x2004
432#define VMX_VMCS_CTRL_MSR_BITMAP_HIGH 0x2005
433
434#define VMX_VMCS_CTRL_VMEXIT_MSR_STORE_FULL 0x2006
435#define VMX_VMCS_CTRL_VMEXIT_MSR_STORE_HIGH 0x2007
436#define VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_FULL 0x2008
437#define VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_HIGH 0x2009
438
439#define VMX_VMCS_CTRL_VMENTRY_MSR_LOAD_FULL 0x200A
440#define VMX_VMCS_CTRL_VMENTRY_MSR_LOAD_HIGH 0x200B
441
442#define VMX_VMCS_CTRL_EXEC_VMCS_PTR_FULL 0x200C
443#define VMX_VMCS_CTRL_EXEC_VMCS_PTR_HIGH 0x200D
444
445#define VMX_VMCS_CTRL_TSC_OFFSET_FULL 0x2010
446#define VMX_VMCS_CTRL_TSC_OFFSET_HIGH 0x2011
447
448/* Optional (VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW) */
449#define VMX_VMCS_CTRL_VAPIC_PAGEADDR_FULL 0x2012
450#define VMX_VMCS_CTRL_VAPIC_PAGEADDR_HIGH 0x2013
451
452/* Optional (VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC) */
453#define VMX_VMCS_CTRL_APIC_ACCESSADDR_FULL 0x2014
454#define VMX_VMCS_CTRL_APIC_ACCESSADDR_HIGH 0x2015
455
456/** Extended page table pointer. */
457#define VMX_VMCS_CTRL_EPTP_FULL 0x201a
458#define VMX_VMCS_CTRL_EPTP_HIGH 0x201b
459
460/** VM-exit phyiscal address. */
461#define VMX_VMCS_EXIT_PHYS_ADDR_FULL 0x2400
462#define VMX_VMCS_EXIT_PHYS_ADDR_HIGH 0x2401
463/** @} */
464
465
466/** 64 Bits guest fields
467 * @{
468 */
469#define VMX_VMCS_GUEST_LINK_PTR_FULL 0x2800
470#define VMX_VMCS_GUEST_LINK_PTR_HIGH 0x2801
471#define VMX_VMCS_GUEST_DEBUGCTL_FULL 0x2802 /* MSR IA32_DEBUGCTL */
472#define VMX_VMCS_GUEST_DEBUGCTL_HIGH 0x2803 /* MSR IA32_DEBUGCTL */
473#define VMX_VMCS_GUEST_PAT_FULL 0x2804
474#define VMX_VMCS_GUEST_PAT_HIGH 0x2805
475#define VMX_VMCS_GUEST_EFER_FULL 0x2806
476#define VMX_VMCS_GUEST_EFER_HIGH 0x2807
477#define VMX_VMCS_GUEST_PERF_GLOBAL_CTRL_FULL 0x2808 /* MSR IA32_PERF_GLOBAL_CTRL */
478#define VMX_VMCS_GUEST_PERF_GLOBAL_CTRL_HIGH 0x2809 /* MSR IA32_PERF_GLOBAL_CTRL */
479#define VMX_VMCS_GUEST_PDPTR0_FULL 0x280A
480#define VMX_VMCS_GUEST_PDPTR0_HIGH 0x280B
481#define VMX_VMCS_GUEST_PDPTR1_FULL 0x280C
482#define VMX_VMCS_GUEST_PDPTR1_HIGH 0x280D
483#define VMX_VMCS_GUEST_PDPTR2_FULL 0x280E
484#define VMX_VMCS_GUEST_PDPTR2_HIGH 0x280F
485#define VMX_VMCS_GUEST_PDPTR3_FULL 0x2810
486#define VMX_VMCS_GUEST_PDPTR3_HIGH 0x2811
487/** @} */
488
489
490/** 32 Bits control fields
491 * @{
492 */
493#define VMX_VMCS_CTRL_PIN_EXEC_CONTROLS 0x4000
494#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS 0x4002
495#define VMX_VMCS_CTRL_EXCEPTION_BITMAP 0x4004
496#define VMX_VMCS_CTRL_PAGEFAULT_ERROR_MASK 0x4006
497#define VMX_VMCS_CTRL_PAGEFAULT_ERROR_MATCH 0x4008
498#define VMX_VMCS_CTRL_CR3_TARGET_COUNT 0x400A
499#define VMX_VMCS_CTRL_EXIT_CONTROLS 0x400C
500#define VMX_VMCS_CTRL_EXIT_MSR_STORE_COUNT 0x400E
501#define VMX_VMCS_CTRL_EXIT_MSR_LOAD_COUNT 0x4010
502#define VMX_VMCS_CTRL_ENTRY_CONTROLS 0x4012
503#define VMX_VMCS_CTRL_ENTRY_MSR_LOAD_COUNT 0x4014
504#define VMX_VMCS_CTRL_ENTRY_IRQ_INFO 0x4016
505#define VMX_VMCS_CTRL_ENTRY_EXCEPTION_ERRCODE 0x4018
506#define VMX_VMCS_CTRL_ENTRY_INSTR_LENGTH 0x401A
507/** This field exists only on processors that support the 1-setting of the “use TPR shadow” VM-execution control. */
508#define VMX_VMCS_CTRL_TPR_THRESHOLD 0x401C
509/** This field exists only on processors that support the 1-setting of the “activate secondary controls” VM-execution control. */
510#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS2 0x401E
511/** @} */
512
513
514/** VMX_VMCS_CTRL_PIN_EXEC_CONTROLS
515 * @{
516 */
517/* External interrupts cause VM exits if set; otherwise dispatched through the guest's IDT. */
518#define VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT RT_BIT(0)
519/* Non-maskable interrupts cause VM exits if set; otherwise dispatched through the guest's IDT. */
520#define VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT RT_BIT(3)
521/* All other bits are reserved and must be set according to MSR IA32_VMX_PROCBASED_CTLS. */
522/** @} */
523
524/** VMX_VMCS_CTRL_PROC_EXEC_CONTROLS
525 * @{
526 */
527/* VM Exit as soon as RFLAGS.IF=1 and no blocking is active. */
528#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT RT_BIT(2)
529/* Use timestamp counter offset. */
530#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET RT_BIT(3)
531/* VM Exit when executing the HLT instruction. */
532#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT RT_BIT(7)
533/* VM Exit when executing the INVLPG instruction. */
534#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT RT_BIT(9)
535/* VM Exit when executing the MWAIT instruction. */
536#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT RT_BIT(10)
537/* VM Exit when executing the RDPMC instruction. */
538#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT RT_BIT(11)
539/* VM Exit when executing the RDTSC instruction. */
540#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT RT_BIT(12)
541/* VM Exit on CR8 loads. */
542#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT RT_BIT(19)
543/* VM Exit on CR8 stores. */
544#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT RT_BIT(20)
545/* Use TPR shadow. */
546#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW RT_BIT(21)
547/* VM Exit when executing a MOV DRx instruction. */
548#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT RT_BIT(23)
549/* VM Exit when executing IO instructions. */
550#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT RT_BIT(24)
551/* Use IO bitmaps. */
552#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS RT_BIT(25)
553/* Use MSR bitmaps. */
554#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS RT_BIT(28)
555/* VM Exit when executing the MONITOR instruction. */
556#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT RT_BIT(29)
557/* VM Exit when executing the PAUSE instruction. */
558#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT RT_BIT(30)
559/* Determines whether the secondary processor based VM-execution controls are used. */
560#define VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL RT_BIT(31)
561/** @} */
562
563/** VMX_VMCS_CTRL_PROC_EXEC_CONTROLS2
564 * @{
565 */
566/** Virtualize APIC access. */
567#define VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC RT_BIT(0)
568/** EPT supported/enabled. */
569#define VMX_VMCS_CTRL_PROC_EXEC2_EPT RT_BIT(1)
570/** VPID supported/enabled. */
571#define VMX_VMCS_CTRL_PROC_EXEC2_VPID RT_BIT(5)
572/** VM Exit when executing the WBINVD instruction. */
573#define VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT RT_BIT(6)
574/** @} */
575
576
577/** VMX_VMCS_CTRL_ENTRY_CONTROLS
578 * @{
579 */
580/** 64 bits guest mode. Must be 0 for CPUs that don't support AMD64. */
581#define VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE RT_BIT(9)
582/** In SMM mode after VM-entry. */
583#define VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM RT_BIT(10)
584/** Disable dual treatment of SMI and SMM; must be zero for VM-entry outside of SMM. */
585#define VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON RT_BIT(11)
586/** @} */
587
588
589/** VMX_VMCS_CTRL_EXIT_CONTROLS
590 * @{
591 */
592/** Return to long mode after a VM-exit. */
593#define VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64 RT_BIT(9)
594/** Acknowledge external interrupts with the irq controller if one caused a VM-exit. */
595#define VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ RT_BIT(15)
596/** @} */
597
598/** 32 Bits read-only fields
599 * @{
600 */
601#define VMX_VMCS_RO_VM_INSTR_ERROR 0x4400
602#define VMX_VMCS_RO_EXIT_REASON 0x4402
603#define VMX_VMCS_RO_EXIT_INTERRUPTION_INFO 0x4404
604#define VMX_VMCS_RO_EXIT_INTERRUPTION_ERRCODE 0x4406
605#define VMX_VMCS_RO_IDT_INFO 0x4408
606#define VMX_VMCS_RO_IDT_ERRCODE 0x440A
607#define VMX_VMCS_RO_EXIT_INSTR_LENGTH 0x440C
608#define VMX_VMCS_RO_EXIT_INSTR_INFO 0x440E
609/** @} */
610
611/** VMX_VMCS_RO_EXIT_INTERRUPTION_INFO
612 * @{
613 */
614#define VMX_EXIT_INTERRUPTION_INFO_VECTOR(a) (a & 0xff)
615#define VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT 8
616#define VMX_EXIT_INTERRUPTION_INFO_TYPE(a) ((a >> VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT) & 7)
617#define VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID RT_BIT(11)
618#define VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID(a) (a & VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID)
619#define VMX_EXIT_INTERRUPTION_INFO_NMI_UNBLOCK(a) (a & RT_BIT(12))
620#define VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT 31
621#define VMX_EXIT_INTERRUPTION_INFO_VALID(a) (a & RT_BIT(31))
622/* Construct an irq event injection value from the exit interruption info value (same except that bit 12 is reserved). */
623#define VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(a) (a & ~RT_BIT(12))
624/** @} */
625
626/** VMX_VMCS_RO_EXIT_INTERRUPTION_INFO_TYPE
627 * @{
628 */
629#define VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT 0
630#define VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI 2
631#define VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT 3
632#define VMX_EXIT_INTERRUPTION_INFO_TYPE_SW 4 /* int xx */
633#define VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT 6
634/** @} */
635
636
637/** 32 Bits guest state fields
638 * @{
639 */
640#define VMX_VMCS_GUEST_ES_LIMIT 0x4800
641#define VMX_VMCS_GUEST_CS_LIMIT 0x4802
642#define VMX_VMCS_GUEST_SS_LIMIT 0x4804
643#define VMX_VMCS_GUEST_DS_LIMIT 0x4806
644#define VMX_VMCS_GUEST_FS_LIMIT 0x4808
645#define VMX_VMCS_GUEST_GS_LIMIT 0x480A
646#define VMX_VMCS_GUEST_LDTR_LIMIT 0x480C
647#define VMX_VMCS_GUEST_TR_LIMIT 0x480E
648#define VMX_VMCS_GUEST_GDTR_LIMIT 0x4810
649#define VMX_VMCS_GUEST_IDTR_LIMIT 0x4812
650#define VMX_VMCS_GUEST_ES_ACCESS_RIGHTS 0x4814
651#define VMX_VMCS_GUEST_CS_ACCESS_RIGHTS 0x4816
652#define VMX_VMCS_GUEST_SS_ACCESS_RIGHTS 0x4818
653#define VMX_VMCS_GUEST_DS_ACCESS_RIGHTS 0x481A
654#define VMX_VMCS_GUEST_FS_ACCESS_RIGHTS 0x481C
655#define VMX_VMCS_GUEST_GS_ACCESS_RIGHTS 0x481E
656#define VMX_VMCS_GUEST_LDTR_ACCESS_RIGHTS 0x4820
657#define VMX_VMCS_GUEST_TR_ACCESS_RIGHTS 0x4822
658#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE 0x4824
659#define VMX_VMCS_GUEST_ACTIVITY_STATE 0x4826
660#define VMX_VMCS_GUEST_SYSENTER_CS 0x482A /* MSR IA32_SYSENTER_CS */
661/** @} */
662
663
664/** VMX_VMCS_GUEST_ACTIVITY_STATE
665 * @{
666 */
667/* The logical processor is active. */
668#define VMX_CMS_GUEST_ACTIVITY_ACTIVE 0x0
669/* The logical processor is inactive, because executed a HLT instruction. */
670#define VMX_CMS_GUEST_ACTIVITY_HLT 0x1
671/* The logical processor is inactive, because of a triple fault or other serious error. */
672#define VMX_CMS_GUEST_ACTIVITY_SHUTDOWN 0x2
673/* The logical processor is inactive, because it's waiting for a startup-IPI */
674#define VMX_CMS_GUEST_ACTIVITY_SIPI_WAIT 0x3
675/** @} */
676
677
678/** VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE
679 * @{
680 */
681#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_STI RT_BIT(0)
682#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_MOVSS RT_BIT(1)
683#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_SMI RT_BIT(2)
684#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_NMI RT_BIT(3)
685/** @} */
686
687
688/** 32 Bits host state fields
689 * @{
690 */
691#define VMX_VMCS_HOST_SYSENTER_CS 0x4C00
692/** @} */
693
694/** Natural width control fields
695 * @{
696 */
697#define VMX_VMCS_CTRL_CR0_MASK 0x6000
698#define VMX_VMCS_CTRL_CR4_MASK 0x6002
699#define VMX_VMCS_CTRL_CR0_READ_SHADOW 0x6004
700#define VMX_VMCS_CTRL_CR4_READ_SHADOW 0x6006
701#define VMX_VMCS_CTRL_CR3_TARGET_VAL0 0x6008
702#define VMX_VMCS_CTRL_CR3_TARGET_VAL1 0x600A
703#define VMX_VMCS_CTRL_CR3_TARGET_VAL2 0x600C
704#define VMX_VMCS_CTRL_CR3_TARGET_VAL31 0x600E
705/** @} */
706
707
708/** Natural width read-only data fields
709 * @{
710 */
711#define VMX_VMCS_RO_EXIT_QUALIFICATION 0x6400
712#define VMX_VMCS_RO_IO_RCX 0x6402
713#define VMX_VMCS_RO_IO_RSX 0x6404
714#define VMX_VMCS_RO_IO_RDI 0x6406
715#define VMX_VMCS_RO_IO_RIP 0x6408
716#define VMX_VMCS_EXIT_GUEST_LINEAR_ADDR 0x640A
717/** @} */
718
719
720/** VMX_VMCS_RO_EXIT_QUALIFICATION
721 * @{
722 */
723
724/** DRx moves
725 * @{
726 */
727/** 0-2: Debug register number */
728#define VMX_EXIT_QUALIFICATION_DRX_REGISTER(a) (a & 7)
729/** 3: Reserved; cleared to 0. */
730#define VMX_EXIT_QUALIFICATION_DRX_RES1(a) ((a >> 3) & 1)
731/** 4: Direction of move (0 = write, 1 = read) */
732#define VMX_EXIT_QUALIFICATION_DRX_DIRECTION(a) ((a >> 4) & 1)
733/** 5-7: Reserved; cleared to 0. */
734#define VMX_EXIT_QUALIFICATION_DRX_RES2(a) ((a >> 5) & 7)
735/** 8-11: General purpose register number. */
736#define VMX_EXIT_QUALIFICATION_DRX_GENREG(a) ((a >> 8) & 0xF)
737/** Rest: reserved. */
738
739/** VMX_EXIT_QUALIFICATION_DRX_DIRECTION
740 * @{
741 */
742#define VMX_EXIT_QUALIFICATION_DRX_DIRECTION_WRITE 0
743#define VMX_EXIT_QUALIFICATION_DRX_DIRECTION_READ 1
744/** @} */
745
746/** @} */
747
748
749/** CRx accesses
750 * @{
751 */
752/** 0-3: Control register number (0 for CLTS & LMSW) */
753#define VMX_EXIT_QUALIFICATION_CRX_REGISTER(a) (a & 0xF)
754/** 4-5: Access type. */
755#define VMX_EXIT_QUALIFICATION_CRX_ACCESS(a) ((a >> 4) & 3)
756/** 6: LMSW operand type */
757#define VMX_EXIT_QUALIFICATION_CRX_LMSW_OP(a) ((a >> 6) & 1)
758/** 7: Reserved; cleared to 0. */
759#define VMX_EXIT_QUALIFICATION_CRX_RES1(a) ((a >> 7) & 1)
760/** 8-11: General purpose register number (0 for CLTS & LMSW). */
761#define VMX_EXIT_QUALIFICATION_CRX_GENREG(a) ((a >> 8) & 0xF)
762/** 12-15: Reserved; cleared to 0. */
763#define VMX_EXIT_QUALIFICATION_CRX_RES2(a) ((a >> 12) & 0xF)
764/** 16-31: LMSW source data (else 0). */
765#define VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(a) ((a >> 16) & 0xFFFF)
766/** Rest: reserved. */
767
768
769/** VMX_EXIT_QUALIFICATION_CRX_ACCESS
770 * @{
771 */
772#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_WRITE 0
773#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_READ 1
774#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_CLTS 2
775#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_LMSW 3
776/** @} */
777
778/** @} */
779
780
781/** VMX_EXIT_PORT_IO
782 * @{
783 */
784/** 0-2: IO operation width. */
785#define VMX_EXIT_QUALIFICATION_IO_WIDTH(a) (a & 7)
786/** 3: IO operation direction. */
787#define VMX_EXIT_QUALIFICATION_IO_DIRECTION(a) ((a >> 3) & 1)
788/** 4: String IO operation. */
789#define VMX_EXIT_QUALIFICATION_IO_STRING(a) ((a >> 4) & 1)
790/** 5: Repeated IO operation. */
791#define VMX_EXIT_QUALIFICATION_IO_REP(a) ((a >> 5) & 1)
792/** 6: Operand encoding. */
793#define VMX_EXIT_QUALIFICATION_IO_ENCODING(a) ((a >> 6) & 1)
794/** 16-31: IO Port (0-0xffff). */
795#define VMX_EXIT_QUALIFICATION_IO_PORT(a) ((a >> 16) & 0xffff)
796/* Rest reserved. */
797/** @} */
798
799/** VMX_EXIT_QUALIFICATION_IO_DIRECTION
800 * @{
801 */
802#define VMX_EXIT_QUALIFICATION_IO_DIRECTION_OUT 0
803#define VMX_EXIT_QUALIFICATION_IO_DIRECTION_IN 1
804/** @} */
805
806
807/** VMX_EXIT_QUALIFICATION_IO_ENCODING
808 * @{
809 */
810#define VMX_EXIT_QUALIFICATION_IO_ENCODING_DX 0
811#define VMX_EXIT_QUALIFICATION_IO_ENCODING_IMM 1
812/** @} */
813
814/** @} */
815
816/** Natural width guest state fields
817 * @{
818 */
819#define VMX_VMCS_GUEST_CR0 0x6800
820#define VMX_VMCS_GUEST_CR3 0x6802
821#define VMX_VMCS_GUEST_CR4 0x6804
822#define VMX_VMCS_GUEST_ES_BASE 0x6806
823#define VMX_VMCS_GUEST_CS_BASE 0x6808
824#define VMX_VMCS_GUEST_SS_BASE 0x680A
825#define VMX_VMCS_GUEST_DS_BASE 0x680C
826#define VMX_VMCS_GUEST_FS_BASE 0x680E
827#define VMX_VMCS_GUEST_GS_BASE 0x6810
828#define VMX_VMCS_GUEST_LDTR_BASE 0x6812
829#define VMX_VMCS_GUEST_TR_BASE 0x6814
830#define VMX_VMCS_GUEST_GDTR_BASE 0x6816
831#define VMX_VMCS_GUEST_IDTR_BASE 0x6818
832#define VMX_VMCS_GUEST_DR7 0x681A
833#define VMX_VMCS_GUEST_RSP 0x681C
834#define VMX_VMCS_GUEST_RIP 0x681E
835#define VMX_VMCS_GUEST_RFLAGS 0x6820
836#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS 0x6822
837#define VMX_VMCS_GUEST_SYSENTER_ESP 0x6824 /* MSR IA32_SYSENTER_ESP */
838#define VMX_VMCS_GUEST_SYSENTER_EIP 0x6826 /* MSR IA32_SYSENTER_EIP */
839/** @} */
840
841
842/** VMX_VMCS_GUEST_DEBUG_EXCEPTIONS
843 * @{
844 */
845/* Hardware breakpoint 0 was met. */
846#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B0 RT_BIT(0)
847/* Hardware breakpoint 1 was met. */
848#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B1 RT_BIT(1)
849/* Hardware breakpoint 2 was met. */
850#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B2 RT_BIT(2)
851/* Hardware breakpoint 3 was met. */
852#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B3 RT_BIT(3)
853/* At least one data or IO breakpoint was hit. */
854#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_BREAKPOINT_ENABLED RT_BIT(12)
855/* A debug exception would have been triggered by single-step execution mode. */
856#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_BS RT_BIT(14)
857/* Bits 4-11, 13 and 15-63 are reserved. */
858
859
860
861
862/** @} */
863
864/** Natural width host state fields
865 * @{
866 */
867#define VMX_VMCS_HOST_CR0 0x6C00
868#define VMX_VMCS_HOST_CR3 0x6C02
869#define VMX_VMCS_HOST_CR4 0x6C04
870#define VMX_VMCS_HOST_FS_BASE 0x6C06
871#define VMX_VMCS_HOST_GS_BASE 0x6C08
872#define VMX_VMCS_HOST_TR_BASE 0x6C0A
873#define VMX_VMCS_HOST_GDTR_BASE 0x6C0C
874#define VMX_VMCS_HOST_IDTR_BASE 0x6C0E
875#define VMX_VMCS_HOST_SYSENTER_ESP 0x6C10
876#define VMX_VMCS_HOST_SYSENTER_EIP 0x6C12
877#define VMX_VMCS_HOST_RSP 0x6C14
878#define VMX_VMCS_HOST_RIP 0x6C16
879/** @} */
880
881/** @} */
882
883
884#if RT_INLINE_ASM_GNU_STYLE
885# define __STR(x) #x
886# define STR(x) __STR(x)
887#endif
888
889
890/** @} */
891
892/** @defgroup grp_vmx_asm vmx assembly helpers
893 * @ingroup grp_vmx
894 * @{
895 */
896
897/**
898 * Executes VMXON
899 *
900 * @returns VBox status code
901 * @param pVMXOn Physical address of VMXON structure
902 */
903#if RT_INLINE_ASM_EXTERNAL || HC_ARCH_BITS == 64
904DECLASM(int) VMXEnable(RTHCPHYS pVMXOn);
905#else
906DECLINLINE(int) VMXEnable(RTHCPHYS pVMXOn)
907{
908 int rc = VINF_SUCCESS;
909# if RT_INLINE_ASM_GNU_STYLE
910 __asm__ __volatile__ (
911 "push %3 \n\t"
912 "push %2 \n\t"
913 ".byte 0xF3, 0x0F, 0xC7, 0x34, 0x24 # VMXON [esp] \n\t"
914 "ja 2f \n\t"
915 "je 1f \n\t"
916 "movl $"STR(VERR_VMX_INVALID_VMXON_PTR)", %0 \n\t"
917 "jmp 2f \n\t"
918 "1: \n\t"
919 "movl $"STR(VERR_VMX_GENERIC)", %0 \n\t"
920 "2: \n\t"
921 "add $8, %%esp \n\t"
922 :"=rm"(rc)
923 :"0"(VINF_SUCCESS),
924 "ir"((uint32_t)pVMXOn), /* don't allow direct memory reference here, */
925 "ir"((uint32_t)(pVMXOn >> 32)) /* this would not work with -fomit-frame-pointer */
926 :"memory"
927 );
928# else
929 __asm
930 {
931 push dword ptr [pVMXOn+4]
932 push dword ptr [pVMXOn]
933 _emit 0xF3
934 _emit 0x0F
935 _emit 0xC7
936 _emit 0x34
937 _emit 0x24 /* VMXON [esp] */
938 jnc vmxon_good
939 mov dword ptr [rc], VERR_VMX_INVALID_VMXON_PTR
940 jmp the_end
941
942vmxon_good:
943 jnz the_end
944 mov dword ptr [rc], VERR_VMX_GENERIC
945the_end:
946 add esp, 8
947 }
948# endif
949 return rc;
950}
951#endif
952
953
954/**
955 * Executes VMXOFF
956 */
957#if RT_INLINE_ASM_EXTERNAL || HC_ARCH_BITS == 64
958DECLASM(void) VMXDisable(void);
959#else
960DECLINLINE(void) VMXDisable(void)
961{
962# if RT_INLINE_ASM_GNU_STYLE
963 __asm__ __volatile__ (
964 ".byte 0x0F, 0x01, 0xC4 # VMXOFF \n\t"
965 );
966# else
967 __asm
968 {
969 _emit 0x0F
970 _emit 0x01
971 _emit 0xC4 /* VMXOFF */
972 }
973# endif
974}
975#endif
976
977
978/**
979 * Executes VMCLEAR
980 *
981 * @returns VBox status code
982 * @param pVMCS Physical address of VM control structure
983 */
984#if RT_INLINE_ASM_EXTERNAL || HC_ARCH_BITS == 64
985DECLASM(int) VMXClearVMCS(RTHCPHYS pVMCS);
986#else
987DECLINLINE(int) VMXClearVMCS(RTHCPHYS pVMCS)
988{
989 int rc = VINF_SUCCESS;
990# if RT_INLINE_ASM_GNU_STYLE
991 __asm__ __volatile__ (
992 "push %3 \n\t"
993 "push %2 \n\t"
994 ".byte 0x66, 0x0F, 0xC7, 0x34, 0x24 # VMCLEAR [esp] \n\t"
995 "jnc 1f \n\t"
996 "movl $"STR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
997 "1: \n\t"
998 "add $8, %%esp \n\t"
999 :"=rm"(rc)
1000 :"0"(VINF_SUCCESS),
1001 "ir"((uint32_t)pVMCS), /* don't allow direct memory reference here, */
1002 "ir"((uint32_t)(pVMCS >> 32)) /* this would not work with -fomit-frame-pointer */
1003 :"memory"
1004 );
1005# else
1006 __asm
1007 {
1008 push dword ptr [pVMCS+4]
1009 push dword ptr [pVMCS]
1010 _emit 0x66
1011 _emit 0x0F
1012 _emit 0xC7
1013 _emit 0x34
1014 _emit 0x24 /* VMCLEAR [esp] */
1015 jnc success
1016 mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
1017success:
1018 add esp, 8
1019 }
1020# endif
1021 return rc;
1022}
1023#endif
1024
1025
1026/**
1027 * Executes VMPTRLD
1028 *
1029 * @returns VBox status code
1030 * @param pVMCS Physical address of VMCS structure
1031 */
1032#if RT_INLINE_ASM_EXTERNAL || HC_ARCH_BITS == 64
1033DECLASM(int) VMXActivateVMCS(RTHCPHYS pVMCS);
1034#else
1035DECLINLINE(int) VMXActivateVMCS(RTHCPHYS pVMCS)
1036{
1037 int rc = VINF_SUCCESS;
1038# if RT_INLINE_ASM_GNU_STYLE
1039 __asm__ __volatile__ (
1040 "push %3 \n\t"
1041 "push %2 \n\t"
1042 ".byte 0x0F, 0xC7, 0x34, 0x24 # VMPTRLD [esp] \n\t"
1043 "jnc 1f \n\t"
1044 "movl $"STR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
1045 "1: \n\t"
1046 "add $8, %%esp \n\t"
1047 :"=rm"(rc)
1048 :"0"(VINF_SUCCESS),
1049 "ir"((uint32_t)pVMCS), /* don't allow direct memory reference here, */
1050 "ir"((uint32_t)(pVMCS >> 32)) /* this will not work with -fomit-frame-pointer */
1051 );
1052# else
1053 __asm
1054 {
1055 push dword ptr [pVMCS+4]
1056 push dword ptr [pVMCS]
1057 _emit 0x0F
1058 _emit 0xC7
1059 _emit 0x34
1060 _emit 0x24 /* VMPTRLD [esp] */
1061 jnc success
1062 mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
1063
1064success:
1065 add esp, 8
1066 }
1067# endif
1068 return rc;
1069}
1070#endif
1071
1072
1073/**
1074 * Executes VMWRITE
1075 *
1076 * @returns VBox status code
1077 * @param idxField VMCS index
1078 * @param u64Val 16, 32 or 64 bits value
1079 */
1080DECLASM(int) VMXWriteVMCS64(uint32_t idxField, uint64_t u64Val);
1081
1082/**
1083 * Executes VMWRITE
1084 *
1085 * @returns VBox status code
1086 * @param idxField VMCS index
1087 * @param u32Val 32 bits value
1088 */
1089#if RT_INLINE_ASM_EXTERNAL || HC_ARCH_BITS == 64
1090DECLASM(int) VMXWriteVMCS32(uint32_t idxField, uint32_t u32Val);
1091#else
1092DECLINLINE(int) VMXWriteVMCS32(uint32_t idxField, uint32_t u32Val)
1093{
1094 int rc = VINF_SUCCESS;
1095# if RT_INLINE_ASM_GNU_STYLE
1096 __asm__ __volatile__ (
1097 ".byte 0x0F, 0x79, 0xC2 # VMWRITE eax, edx \n\t"
1098 "ja 2f \n\t"
1099 "je 1f \n\t"
1100 "movl $"STR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
1101 "jmp 2f \n\t"
1102 "1: \n\t"
1103 "movl $"STR(VERR_VMX_INVALID_VMCS_FIELD)", %0 \n\t"
1104 "2: \n\t"
1105 :"=rm"(rc)
1106 :"0"(VINF_SUCCESS),
1107 "a"(idxField),
1108 "d"(u32Val)
1109 );
1110# else
1111 __asm
1112 {
1113 push dword ptr [u32Val]
1114 mov eax, [idxField]
1115 _emit 0x0F
1116 _emit 0x79
1117 _emit 0x04
1118 _emit 0x24 /* VMWRITE eax, [esp] */
1119 jnc valid_vmcs
1120 mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
1121 jmp the_end
1122
1123valid_vmcs:
1124 jnz the_end
1125 mov dword ptr [rc], VERR_VMX_INVALID_VMCS_FIELD
1126the_end:
1127 add esp, 4
1128 }
1129# endif
1130 return rc;
1131}
1132#endif
1133
1134#if HC_ARCH_BITS == 64
1135#define VMXWriteVMCS VMXWriteVMCS64
1136#else
1137#define VMXWriteVMCS VMXWriteVMCS32
1138#endif /* HC_ARCH_BITS == 64 */
1139
1140
1141/**
1142 * Executes VMREAD
1143 *
1144 * @returns VBox status code
1145 * @param idxField VMCS index
1146 * @param pData Ptr to store VM field value
1147 */
1148DECLASM(int) VMXReadVMCS64(uint32_t idxField, uint64_t *pData);
1149
1150/**
1151 * Executes VMREAD
1152 *
1153 * @returns VBox status code
1154 * @param idxField VMCS index
1155 * @param pData Ptr to store VM field value
1156 */
1157#if RT_INLINE_ASM_EXTERNAL || HC_ARCH_BITS == 64
1158DECLASM(int) VMXReadVMCS32(uint32_t idxField, uint32_t *pData);
1159#else
1160DECLINLINE(int) VMXReadVMCS32(uint32_t idxField, uint32_t *pData)
1161{
1162 int rc = VINF_SUCCESS;
1163# if RT_INLINE_ASM_GNU_STYLE
1164 __asm__ __volatile__ (
1165 "movl $"STR(VINF_SUCCESS)", %0 \n\t"
1166 ".byte 0x0F, 0x78, 0xc2 # VMREAD eax, edx \n\t"
1167 "ja 2f \n\t"
1168 "je 1f \n\t"
1169 "movl $"STR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
1170 "jmp 2f \n\t"
1171 "1: \n\t"
1172 "movl $"STR(VERR_VMX_INVALID_VMCS_FIELD)", %0 \n\t"
1173 "2: \n\t"
1174 :"=&r"(rc),
1175 "=d"(*pData)
1176 :"a"(idxField),
1177 "d"(0)
1178 );
1179# else
1180 __asm
1181 {
1182 sub esp, 4
1183 mov dword ptr [esp], 0
1184 mov eax, [idxField]
1185 _emit 0x0F
1186 _emit 0x78
1187 _emit 0x04
1188 _emit 0x24 /* VMREAD eax, [esp] */
1189 mov edx, pData
1190 pop dword ptr [edx]
1191 jnc valid_vmcs
1192 mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
1193 jmp the_end
1194
1195valid_vmcs:
1196 jnz the_end
1197 mov dword ptr [rc], VERR_VMX_INVALID_VMCS_FIELD
1198the_end:
1199 }
1200# endif
1201 return rc;
1202}
1203#endif
1204
1205#if HC_ARCH_BITS == 64
1206#define VMXReadVMCS VMXReadVMCS64
1207#else
1208#define VMXReadVMCS VMXReadVMCS32
1209#endif /* HC_ARCH_BITS == 64 */
1210
1211/**
1212 * Gets the last instruction error value from the current VMCS
1213 *
1214 * @returns error value
1215 */
1216DECLINLINE(uint32_t) VMXGetLastError(void)
1217{
1218#if HC_ARCH_BITS == 64
1219 uint64_t uLastError = 0;
1220 int rc = VMXReadVMCS(VMX_VMCS_RO_VM_INSTR_ERROR, &uLastError);
1221 AssertRC(rc);
1222 return (uint32_t)uLastError;
1223
1224#else /* 32-bit host: */
1225 uint32_t lasterr = 0;
1226 int rc;
1227
1228 rc = VMXReadVMCS32(VMX_VMCS_RO_VM_INSTR_ERROR, &lasterr);
1229 AssertRC(rc);
1230 return lasterr;
1231#endif
1232}
1233
1234/** @} */
1235
1236#endif
1237
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