VirtualBox

source: vbox/trunk/include/VBox/hwacc_vmx.h@ 12742

Last change on this file since 12742 was 12702, checked in by vboxsync, 16 years ago

#1865: HWACCM - alignment fix+check for 32-bit gcc, doxygen.
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1/** @file
2 * HWACCM - VMX Structures and Definitions.
3 */
4
5/*
6 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * The contents of this file may alternatively be used under the terms
17 * of the Common Development and Distribution License Version 1.0
18 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19 * VirtualBox OSE distribution, in which case the provisions of the
20 * CDDL are applicable instead of those of the GPL.
21 *
22 * You may elect to license modified versions of this file under the
23 * terms and conditions of either the GPL or the CDDL or both.
24 *
25 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
26 * Clara, CA 95054 USA or visit http://www.sun.com if you need
27 * additional information or have any questions.
28 */
29
30#ifndef ___VBox_vmx_h
31#define ___VBox_vmx_h
32
33#include <VBox/types.h>
34#include <VBox/err.h>
35#include <iprt/assert.h>
36#include <iprt/asm.h>
37
38/** @defgroup grp_vmx vmx Types and Definitions
39 * @ingroup grp_hwaccm
40 * @{
41 */
42
43/**
44 * Extended Page Directory Pointer. Bit view.
45 */
46#pragma pack(1)
47typedef struct VTXEPTPBITS
48{
49 /** EPT Table Memory Type. */
50 uint64_t u3ETMT : 3;
51 /** Guest Address Width. */
52 uint64_t u3GAW : 3;
53 /** Reserved. */
54 uint64_t u6Reserved : 6;
55 /** Address Space Root; page frame address of the first level EPT page. Actual width depends on the maximum physical address width of the CPU. */
56 uint64_t u52ASR : 52;
57} VTXEPTPBITS;
58#pragma pack()
59/** Pointer to an extended page directory pointer. */
60typedef VTXEPTPBITS *PVTXEPTPBITS;
61/** Pointer to a const extended page directory pointer. */
62typedef const VTXEPTPBITS *PCVTXEPTPBITS;
63
64/**
65 * Extended Page Directory Pointer.
66 */
67#pragma pack(1)
68typedef union VTXEPTP
69{
70 VTXEPTPBITS n;
71 /** 64 bit unsigned integer view. */
72 uint64_t au64[1];
73} VTXEPTP;
74#pragma pack()
75/** Pointer to an extended page directory pointer. */
76typedef VTXEPTP *PVTXEPTP;
77/** Pointer to a const extended page directory pointer. */
78typedef const VTXEPTP *PCVTXEPTP;
79
80
81/**
82 * Extended Page Directory Table Entry. Bit view.
83 */
84#pragma pack(1)
85typedef union VTXEPTEBITS
86{
87 /** Readable bit. */
88 uint64_t u1Readable : 1;
89 /** Writable bit. */
90 uint64_t u1Writable : 1;
91 /** Executable bit. */
92 uint64_t u1Executable : 1;
93 /** EPT Table Memory Type. MBZ for non-leaf nodes. */
94 uint64_t u3EMT : 3;
95 /** IGMT (Ignore Guest Memory Type) (leaf nodes). MBZ for non-leaf nodes. */
96 uint64_t u1IGMT : 1;
97 /** Super page (non-leaf) / available (leaf). */
98 uint64_t u1SP : 1;
99 /** Available for software. */
100 uint64_t u4Available : 4;
101 /** Physical address of next leaf/super page. Restricted by maximum physical address width of the cpu. */
102 uint64_t u45PhysAddr : 45;
103 /** Reserved (MBZ). */
104 uint64_t u5Reserved : 5;
105 /** Availabe for software. */
106 uint64_t u2Available : 2;
107} VTXEPTEBITS;
108#pragma pack()
109/** Pointer to an extended page table entry. */
110typedef VTXEPTEBITS *PVTXEPTEBITS;
111/** Pointer to a const extended table entry. */
112typedef const VTXEPTEBITS *PCVTXEPTEBITS;
113
114/**
115 * Extended Page Directory Table Entry.
116 */
117#pragma pack(1)
118typedef union VTXEPTE
119{
120 VTXEPTEBITS n;
121 /** 64 bit unsigned integer view. */
122 uint64_t au64[1];
123} VTXEPTE;
124#pragma pack()
125/** Pointer to an extended page table entry. */
126typedef VTXEPTE *PVTXEPTE;
127/** Pointer to a const extended table entry. */
128typedef const VTXEPTE *PCVTXEPTE;
129
130/**
131 * Number of page table entries in the EPT.
132 */
133#define VTX_PT_ENTRIES 512
134
135/**
136 * Extended Page Directory Table.
137 */
138#pragma pack(1)
139typedef union VTXEPT
140{
141 VTXEPTE a[VTX_PT_ENTRIES];
142} VTXEPT;
143#pragma pack()
144/** Pointer to an extended page table. */
145typedef VTXEPT *PVTXEPT;
146/** Pointer to a const extended table. */
147typedef const VTXEPT *PCVTXEPT;
148
149/** @name VMX Basic Exit Reasons.
150 * @{
151 */
152/** And-mask for setting reserved bits to zero */
153#define VMX_EFLAGS_RESERVED_0 (~0xffc08028)
154/** Or-mask for setting reserved bits to 1 */
155#define VMX_EFLAGS_RESERVED_1 0x00000002
156/** @} */
157
158/** @name VMX Basic Exit Reasons.
159 * @{
160 */
161/** 0 Exception or non-maskable interrupt (NMI). */
162#define VMX_EXIT_EXCEPTION 0
163/** 1 External interrupt. */
164#define VMX_EXIT_EXTERNAL_IRQ 1
165/** 2 Triple fault. */
166#define VMX_EXIT_TRIPLE_FAULT 2
167/** 3 INIT signal. */
168#define VMX_EXIT_INIT_SIGNAL 3
169/** 4 Start-up IPI (SIPI). */
170#define VMX_EXIT_SIPI 4
171/** 5 I/O system-management interrupt (SMI). */
172#define VMX_EXIT_IO_SMI_IRQ 5
173/** 6 Other SMI. */
174#define VMX_EXIT_SMI_IRQ 6
175/** 7 Interrupt window. */
176#define VMX_EXIT_IRQ_WINDOW 7
177/** 9 Task switch. */
178#define VMX_EXIT_TASK_SWITCH 9
179/** 10 Guest software attempted to execute CPUID. */
180#define VMX_EXIT_CPUID 10
181/** 12 Guest software attempted to execute HLT. */
182#define VMX_EXIT_HLT 12
183/** 13 Guest software attempted to execute INVD. */
184#define VMX_EXIT_INVD 13
185/** 14 Guest software attempted to execute INVPG. */
186#define VMX_EXIT_INVPG 14
187/** 15 Guest software attempted to execute RDPMC. */
188#define VMX_EXIT_RDPMC 15
189/** 16 Guest software attempted to execute RDTSC. */
190#define VMX_EXIT_RDTSC 16
191/** 17 Guest software attempted to execute RSM in SMM. */
192#define VMX_EXIT_RSM 17
193/** 18 Guest software executed VMCALL. */
194#define VMX_EXIT_VMCALL 18
195/** 19 Guest software executed VMCLEAR. */
196#define VMX_EXIT_VMCLEAR 19
197/** 20 Guest software executed VMLAUNCH. */
198#define VMX_EXIT_VMLAUNCH 20
199/** 21 Guest software executed VMPTRLD. */
200#define VMX_EXIT_VMPTRLD 21
201/** 22 Guest software executed VMPTRST. */
202#define VMX_EXIT_VMPTRST 22
203/** 23 Guest software executed VMREAD. */
204#define VMX_EXIT_VMREAD 23
205/** 24 Guest software executed VMRESUME. */
206#define VMX_EXIT_VMRESUME 24
207/** 25 Guest software executed VMWRITE. */
208#define VMX_EXIT_VMWRITE 25
209/** 26 Guest software executed VMXOFF. */
210#define VMX_EXIT_VMXOFF 26
211/** 27 Guest software executed VMXON. */
212#define VMX_EXIT_VMXON 27
213/** 28 Control-register accesses. */
214#define VMX_EXIT_CRX_MOVE 28
215/** 29 Debug-register accesses. */
216#define VMX_EXIT_DRX_MOVE 29
217/** 30 I/O instruction. */
218#define VMX_EXIT_PORT_IO 30
219/** 31 RDMSR. Guest software attempted to execute RDMSR. */
220#define VMX_EXIT_RDMSR 31
221/** 32 WRMSR. Guest software attempted to execute WRMSR. */
222#define VMX_EXIT_WRMSR 32
223/** 33 VM-entry failure due to invalid guest state. */
224#define VMX_EXIT_ERR_INVALID_GUEST_STATE 33
225/** 34 VM-entry failure due to MSR loading. */
226#define VMX_EXIT_ERR_MSR_LOAD 34
227/** 36 Guest software executed MWAIT. */
228#define VMX_EXIT_MWAIT 36
229/** 39 Guest software attempted to execute MONITOR. */
230#define VMX_EXIT_MONITOR 39
231/** 40 Guest software attempted to execute PAUSE. */
232#define VMX_EXIT_PAUSE 40
233/** 41 VM-entry failure due to machine-check. */
234#define VMX_EXIT_ERR_MACHINE_CHECK 41
235/** 43 TPR below threshold. Guest software executed MOV to CR8. */
236#define VMX_EXIT_TPR 43
237/** 54 WBINVD. Guest software attempted to execute WBINVD. */
238#define VMX_EXIT_WBINVD 54
239
240/** @} */
241
242
243/** @name VM Instruction Errors
244 * @{
245 */
246/** 1 VMCALL executed in VMX root operation. */
247#define VMX_ERROR_VMCALL 1
248/** 2 VMCLEAR with invalid physical address. */
249#define VMX_ERROR_VMCLEAR_INVALID_PHYS_ADDR 2
250/** 3 VMCLEAR with VMXON pointer. */
251#define VMX_ERROR_VMCLEAR_INVALID_VMXON_PTR 3
252/** 4 VMLAUNCH with non-clear VMCS. */
253#define VMX_ERROR_VMLAUCH_NON_CLEAR_VMCS 4
254/** 5 VMRESUME with non-launched VMCS. */
255#define VMX_ERROR_VMRESUME_NON_LAUNCHED_VMCS 5
256/** 6 VMRESUME with a corrupted VMCS (indicates corruption of the current VMCS). */
257#define VMX_ERROR_VMRESUME_CORRUPTED_VMCS 6
258/** 7 VM entry with invalid control field(s). */
259#define VMX_ERROR_VMENTRY_INVALID_CONTROL_FIELDS 7
260/** 8 VM entry with invalid host-state field(s). */
261#define VMX_ERROR_VMENTRY_INVALID_HOST_STATE 8
262/** 9 VMPTRLD with invalid physical address. */
263#define VMX_ERROR_VMPTRLD_INVALID_PHYS_ADDR 9
264/** 10 VMPTRLD with VMXON pointer. */
265#define VMX_ERROR_VMPTRLD_VMXON_PTR 10
266/** 11 VMPTRLD with incorrect VMCS revision identifier. */
267#define VMX_ERROR_VMPTRLD_WRONG_VMCS_REVISION 11
268/** 12 VMREAD/VMWRITE from/to unsupported VMCS component. */
269#define VMX_ERROR_VMREAD_INVALID_COMPONENT 12
270#define VMX_ERROR_VMWRITE_INVALID_COMPONENT VMX_ERROR_VMREAD_INVALID_COMPONENT
271/** 13 VMWRITE to read-only VMCS component. */
272#define VMX_ERROR_VMWRITE_READONLY_COMPONENT 13
273/** 15 VMXON executed in VMX root operation. */
274#define VMX_ERROR_VMXON_IN_VMX_ROOT_OP 15
275/** 16 VM entry with invalid executive-VMCS pointer. */
276#define VMX_ERROR_VMENTRY_INVALID_VMCS_EXEC_PTR 16
277/** 17 VM entry with non-launched executive VMCS. */
278#define VMX_ERROR_VMENTRY_NON_LAUNCHED_EXEC_VMCS 17
279/** 18 VM entry with executive-VMCS pointer not VMXON pointer. */
280#define VMX_ERROR_VMENTRY_EXEC_VMCS_PTR 18
281/** 19 VMCALL with non-clear VMCS. */
282#define VMX_ERROR_VMCALL_NON_CLEAR_VMCS 19
283/** 20 VMCALL with invalid VM-exit control fields. */
284#define VMX_ERROR_VMCALL_INVALID_VMEXIT_FIELDS 20
285/** 22 VMCALL with incorrect MSEG revision identifier. */
286#define VMX_ERROR_VMCALL_INVALID_MSEG_REVISION 22
287/** 23 VMXOFF under dual-monitor treatment of SMIs and SMM. */
288#define VMX_ERROR_VMXOFF_DUAL_MONITOR 23
289/** 24 VMCALL with invalid SMM-monitor features. */
290#define VMX_ERROR_VMCALL_INVALID_SMM_MONITOR 24
291/** 25 VM entry with invalid VM-execution control fields in executive VMCS. */
292#define VMX_ERROR_VMENTRY_INVALID_VM_EXEC_CTRL 25
293/** 26 VM entry with events blocked by MOV SS. */
294#define VMX_ERROR_VMENTRY_MOV_SS 26
295
296/** @} */
297
298
299/** @name VMX MSRs - Basic VMX information.
300 * @{
301 */
302/** VMCS revision identifier used by the processor. */
303#define MSR_IA32_VMX_BASIC_INFO_VMCS_ID(a) (a & 0x7FFFFFFF)
304/** Size of the VMCS. */
305#define MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(a) ((a >> 32ULL) & 0xFFF)
306/** Width of physical address used for the VMCS.
307 * 0 -> limited to the available amount of physical ram
308 * 1 -> within the first 4 GB
309 */
310#define MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(a) ((a >> 48ULL) & 1)
311/** Whether the processor supports the dual-monitor treatment of system-management interrupts and system-management code. (always 1) */
312#define MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(a) ((a >> 49ULL) & 1)
313/** Memory type that must be used for the VMCS. */
314#define MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(a) ((a >> 50ULL) & 0xF)
315/** @} */
316
317
318/** @name VMX MSRs - Misc VMX info.
319 * @{
320 */
321/** Activity states supported by the implementation. */
322#define MSR_IA32_VMX_MISC_ACTIVITY_STATES(a) ((a >> 6ULL) & 0x7)
323/** Number of CR3 target values supported by the processor. (0-256) */
324#define MSR_IA32_VMX_MISC_CR3_TARGET(a) ((a >> 16ULL) & 0x1FF)
325/** Maximum nr of MSRs in the VMCS. (N+1)*512. */
326#define MSR_IA32_VMX_MISC_MAX_MSR(a) ((((a >> 25ULL) & 0x7) + 1) * 512)
327/** MSEG revision identifier used by the processor. */
328#define MSR_IA32_VMX_MISC_MSEG_ID(a) (a >> 32ULL)
329/** @} */
330
331
332/** @name VMX MSRs - VMCS enumeration field info
333 * @{
334 */
335/** Highest field index. */
336#define MSR_IA32_VMX_VMCS_ENUM_HIGHEST_INDEX(a) ((a >> 1ULL) & 0x1FF)
337
338/** @} */
339
340
341/** @name MSR_IA32_VMX_EPT_CAPS; EPT capabilities MSR
342 * @{
343 */
344#define MSR_IA32_VMX_EPT_CAPS_RWX_X_ONLY RT_BIT_64(0)
345#define MSR_IA32_VMX_EPT_CAPS_RWX_W_ONLY RT_BIT_64(1)
346#define MSR_IA32_VMX_EPT_CAPS_RWX_WX_ONLY RT_BIT_64(2)
347#define MSR_IA32_VMX_EPT_CAPS_GAW_21_BITS RT_BIT_64(3)
348#define MSR_IA32_VMX_EPT_CAPS_GAW_30_BITS RT_BIT_64(4)
349#define MSR_IA32_VMX_EPT_CAPS_GAW_39_BITS RT_BIT_64(5)
350#define MSR_IA32_VMX_EPT_CAPS_GAW_48_BITS RT_BIT_64(6)
351#define MSR_IA32_VMX_EPT_CAPS_GAW_57_BITS RT_BIT_64(7)
352#define MSR_IA32_VMX_EPT_CAPS_EMT_UC RT_BIT_64(8)
353#define MSR_IA32_VMX_EPT_CAPS_EMT_WC RT_BIT_64(9)
354#define MSR_IA32_VMX_EPT_CAPS_EMT_WT RT_BIT_64(12)
355#define MSR_IA32_VMX_EPT_CAPS_EMT_WP RT_BIT_64(13)
356#define MSR_IA32_VMX_EPT_CAPS_EMT_WB RT_BIT_64(14)
357#define MSR_IA32_VMX_EPT_CAPS_SP_21_BITS RT_BIT_64(16)
358#define MSR_IA32_VMX_EPT_CAPS_SP_30_BITS RT_BIT_64(17)
359#define MSR_IA32_VMX_EPT_CAPS_SP_39_BITS RT_BIT_64(18)
360#define MSR_IA32_VMX_EPT_CAPS_SP_48_BITS RT_BIT_64(19)
361#define MSR_IA32_VMX_EPT_CAPS_INVEPT RT_BIT_64(20)
362#define MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV RT_BIT_64(24)
363#define MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT RT_BIT_64(25)
364#define MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL RT_BIT_64(26)
365#define MSR_IA32_VMX_EPT_CAPS_INVVPID RT_BIT_64(32)
366#define MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV RT_BIT_64(40)
367#define MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT RT_BIT_64(41)
368#define MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL RT_BIT_64(42)
369#define MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT_GLOBAL RT_BIT_64(43)
370
371/** @} */
372
373
374/** @name VMCS field encoding - 16 bits guest fields
375 * @{
376 */
377#define VMX_VMCS_GUEST_FIELD_VPID 0x0
378#define VMX_VMCS_GUEST_FIELD_ES 0x800
379#define VMX_VMCS_GUEST_FIELD_CS 0x802
380#define VMX_VMCS_GUEST_FIELD_SS 0x804
381#define VMX_VMCS_GUEST_FIELD_DS 0x806
382#define VMX_VMCS_GUEST_FIELD_FS 0x808
383#define VMX_VMCS_GUEST_FIELD_GS 0x80A
384#define VMX_VMCS_GUEST_FIELD_LDTR 0x80C
385#define VMX_VMCS_GUEST_FIELD_TR 0x80E
386/** @} */
387
388/** @name VMCS field encoding - 16 bits host fields
389 * @{
390 */
391#define VMX_VMCS_HOST_FIELD_ES 0xC00
392#define VMX_VMCS_HOST_FIELD_CS 0xC02
393#define VMX_VMCS_HOST_FIELD_SS 0xC04
394#define VMX_VMCS_HOST_FIELD_DS 0xC06
395#define VMX_VMCS_HOST_FIELD_FS 0xC08
396#define VMX_VMCS_HOST_FIELD_GS 0xC0A
397#define VMX_VMCS_HOST_FIELD_TR 0xC0C
398/** @} */
399
400/** @name VMCS field encoding - 64 bits host fields
401 * @{
402 */
403#define VMX_VMCS_HOST_FIELD_PAT_FULL 0x2C00
404#define VMX_VMCS_HOST_FIELD_PAT_HIGH 0x2C01
405#define VMX_VMCS_HOST_FIELD_EFER_FULL 0x2C02
406#define VMX_VMCS_HOST_FIELD_EFER_HIGH 0x2C03
407#define VMX_VMCS_HOST_PERF_GLOBAL_CTRL_FULL 0x2C04 /**< MSR IA32_PERF_GLOBAL_CTRL */
408#define VMX_VMCS_HOST_PERF_GLOBAL_CTRL_HIGH 0x2C05 /**< MSR IA32_PERF_GLOBAL_CTRL */
409/** @} */
410
411
412/** @name VMCS field encoding - 64 Bits control fields
413 * @{
414 */
415#define VMX_VMCS_CTRL_IO_BITMAP_A_FULL 0x2000
416#define VMX_VMCS_CTRL_IO_BITMAP_A_HIGH 0x2001
417#define VMX_VMCS_CTRL_IO_BITMAP_B_FULL 0x2002
418#define VMX_VMCS_CTRL_IO_BITMAP_B_HIGH 0x2003
419
420/* Optional */
421#define VMX_VMCS_CTRL_MSR_BITMAP_FULL 0x2004
422#define VMX_VMCS_CTRL_MSR_BITMAP_HIGH 0x2005
423
424#define VMX_VMCS_CTRL_VMEXIT_MSR_STORE_FULL 0x2006
425#define VMX_VMCS_CTRL_VMEXIT_MSR_STORE_HIGH 0x2007
426#define VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_FULL 0x2008
427#define VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_HIGH 0x2009
428
429#define VMX_VMCS_CTRL_VMENTRY_MSR_LOAD_FULL 0x200A
430#define VMX_VMCS_CTRL_VMENTRY_MSR_LOAD_HIGH 0x200B
431
432#define VMX_VMCS_CTRL_EXEC_VMCS_PTR_FULL 0x200C
433#define VMX_VMCS_CTRL_EXEC_VMCS_PTR_HIGH 0x200D
434
435#define VMX_VMCS_CTRL_TSC_OFFSET_FULL 0x2010
436#define VMX_VMCS_CTRL_TSC_OFFSET_HIGH 0x2011
437
438/** Optional (VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW) */
439#define VMX_VMCS_CTRL_VAPIC_PAGEADDR_FULL 0x2012
440#define VMX_VMCS_CTRL_VAPIC_PAGEADDR_HIGH 0x2013
441
442/** Optional (VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC) */
443#define VMX_VMCS_CTRL_APIC_ACCESSADDR_FULL 0x2014
444#define VMX_VMCS_CTRL_APIC_ACCESSADDR_HIGH 0x2015
445
446/** Extended page table pointer. */
447#define VMX_VMCS_CTRL_EPTP_FULL 0x201a
448#define VMX_VMCS_CTRL_EPTP_HIGH 0x201b
449
450/** VM-exit phyiscal address. */
451#define VMX_VMCS_EXIT_PHYS_ADDR_FULL 0x2400
452#define VMX_VMCS_EXIT_PHYS_ADDR_HIGH 0x2401
453/** @} */
454
455
456/** @name VMCS field encoding - 64 Bits guest fields
457 * @{
458 */
459#define VMX_VMCS_GUEST_LINK_PTR_FULL 0x2800
460#define VMX_VMCS_GUEST_LINK_PTR_HIGH 0x2801
461#define VMX_VMCS_GUEST_DEBUGCTL_FULL 0x2802 /**< MSR IA32_DEBUGCTL */
462#define VMX_VMCS_GUEST_DEBUGCTL_HIGH 0x2803 /**< MSR IA32_DEBUGCTL */
463#define VMX_VMCS_GUEST_PAT_FULL 0x2804
464#define VMX_VMCS_GUEST_PAT_HIGH 0x2805
465#define VMX_VMCS_GUEST_EFER_FULL 0x2806
466#define VMX_VMCS_GUEST_EFER_HIGH 0x2807
467#define VMX_VMCS_GUEST_PERF_GLOBAL_CTRL_FULL 0x2808 /**< MSR IA32_PERF_GLOBAL_CTRL */
468#define VMX_VMCS_GUEST_PERF_GLOBAL_CTRL_HIGH 0x2809 /**< MSR IA32_PERF_GLOBAL_CTRL */
469#define VMX_VMCS_GUEST_PDPTR0_FULL 0x280A
470#define VMX_VMCS_GUEST_PDPTR0_HIGH 0x280B
471#define VMX_VMCS_GUEST_PDPTR1_FULL 0x280C
472#define VMX_VMCS_GUEST_PDPTR1_HIGH 0x280D
473#define VMX_VMCS_GUEST_PDPTR2_FULL 0x280E
474#define VMX_VMCS_GUEST_PDPTR2_HIGH 0x280F
475#define VMX_VMCS_GUEST_PDPTR3_FULL 0x2810
476#define VMX_VMCS_GUEST_PDPTR3_HIGH 0x2811
477/** @} */
478
479
480/** @name VMCS field encoding - 32 Bits control fields
481 * @{
482 */
483#define VMX_VMCS_CTRL_PIN_EXEC_CONTROLS 0x4000
484#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS 0x4002
485#define VMX_VMCS_CTRL_EXCEPTION_BITMAP 0x4004
486#define VMX_VMCS_CTRL_PAGEFAULT_ERROR_MASK 0x4006
487#define VMX_VMCS_CTRL_PAGEFAULT_ERROR_MATCH 0x4008
488#define VMX_VMCS_CTRL_CR3_TARGET_COUNT 0x400A
489#define VMX_VMCS_CTRL_EXIT_CONTROLS 0x400C
490#define VMX_VMCS_CTRL_EXIT_MSR_STORE_COUNT 0x400E
491#define VMX_VMCS_CTRL_EXIT_MSR_LOAD_COUNT 0x4010
492#define VMX_VMCS_CTRL_ENTRY_CONTROLS 0x4012
493#define VMX_VMCS_CTRL_ENTRY_MSR_LOAD_COUNT 0x4014
494#define VMX_VMCS_CTRL_ENTRY_IRQ_INFO 0x4016
495#define VMX_VMCS_CTRL_ENTRY_EXCEPTION_ERRCODE 0x4018
496#define VMX_VMCS_CTRL_ENTRY_INSTR_LENGTH 0x401A
497/** This field exists only on processors that support the 1-setting of the “use TPR shadow” VM-execution control. */
498#define VMX_VMCS_CTRL_TPR_THRESHOLD 0x401C
499/** This field exists only on processors that support the 1-setting of the “activate secondary controls” VM-execution control. */
500#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS2 0x401E
501/** @} */
502
503
504/** @name VMX_VMCS_CTRL_PIN_EXEC_CONTROLS
505 * @{
506 */
507/** External interrupts cause VM exits if set; otherwise dispatched through the guest's IDT. */
508#define VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT RT_BIT(0)
509/** Non-maskable interrupts cause VM exits if set; otherwise dispatched through the guest's IDT. */
510#define VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT RT_BIT(3)
511/* All other bits are reserved and must be set according to MSR IA32_VMX_PROCBASED_CTLS. */
512/** @} */
513
514/** @name VMX_VMCS_CTRL_PROC_EXEC_CONTROLS
515 * @{
516 */
517/** VM Exit as soon as RFLAGS.IF=1 and no blocking is active. */
518#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT RT_BIT(2)
519/** Use timestamp counter offset. */
520#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET RT_BIT(3)
521/** VM Exit when executing the HLT instruction. */
522#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT RT_BIT(7)
523/** VM Exit when executing the INVLPG instruction. */
524#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT RT_BIT(9)
525/** VM Exit when executing the MWAIT instruction. */
526#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT RT_BIT(10)
527/** VM Exit when executing the RDPMC instruction. */
528#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT RT_BIT(11)
529/** VM Exit when executing the RDTSC instruction. */
530#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT RT_BIT(12)
531/** VM Exit on CR8 loads. */
532#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT RT_BIT(19)
533/** VM Exit on CR8 stores. */
534#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT RT_BIT(20)
535/** Use TPR shadow. */
536#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW RT_BIT(21)
537/** VM Exit when executing a MOV DRx instruction. */
538#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT RT_BIT(23)
539/** VM Exit when executing IO instructions. */
540#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT RT_BIT(24)
541/** Use IO bitmaps. */
542#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS RT_BIT(25)
543/** Use MSR bitmaps. */
544#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS RT_BIT(28)
545/** VM Exit when executing the MONITOR instruction. */
546#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT RT_BIT(29)
547/** VM Exit when executing the PAUSE instruction. */
548#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT RT_BIT(30)
549/** Determines whether the secondary processor based VM-execution controls are used. */
550#define VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL RT_BIT(31)
551/** @} */
552
553/** @name VMX_VMCS_CTRL_PROC_EXEC_CONTROLS2
554 * @{
555 */
556/** Virtualize APIC access. */
557#define VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC RT_BIT(0)
558/** EPT supported/enabled. */
559#define VMX_VMCS_CTRL_PROC_EXEC2_EPT RT_BIT(1)
560/** VPID supported/enabled. */
561#define VMX_VMCS_CTRL_PROC_EXEC2_VPID RT_BIT(5)
562/** VM Exit when executing the WBINVD instruction. */
563#define VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT RT_BIT(6)
564/** @} */
565
566
567/** @name VMX_VMCS_CTRL_ENTRY_CONTROLS
568 * @{
569 */
570/** 64 bits guest mode. Must be 0 for CPUs that don't support AMD64. */
571#define VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE RT_BIT(9)
572/** In SMM mode after VM-entry. */
573#define VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM RT_BIT(10)
574/** Disable dual treatment of SMI and SMM; must be zero for VM-entry outside of SMM. */
575#define VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON RT_BIT(11)
576/** @} */
577
578
579/** @name VMX_VMCS_CTRL_EXIT_CONTROLS
580 * @{
581 */
582/** Return to long mode after a VM-exit. */
583#define VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64 RT_BIT(9)
584/** Acknowledge external interrupts with the irq controller if one caused a VM-exit. */
585#define VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ RT_BIT(15)
586/** @} */
587
588/** @name VMCS field encoding - 32 Bits read-only fields
589 * @{
590 */
591#define VMX_VMCS_RO_VM_INSTR_ERROR 0x4400
592#define VMX_VMCS_RO_EXIT_REASON 0x4402
593#define VMX_VMCS_RO_EXIT_INTERRUPTION_INFO 0x4404
594#define VMX_VMCS_RO_EXIT_INTERRUPTION_ERRCODE 0x4406
595#define VMX_VMCS_RO_IDT_INFO 0x4408
596#define VMX_VMCS_RO_IDT_ERRCODE 0x440A
597#define VMX_VMCS_RO_EXIT_INSTR_LENGTH 0x440C
598#define VMX_VMCS_RO_EXIT_INSTR_INFO 0x440E
599/** @} */
600
601/** @name VMX_VMCS_RO_EXIT_INTERRUPTION_INFO
602 * @{
603 */
604#define VMX_EXIT_INTERRUPTION_INFO_VECTOR(a) (a & 0xff)
605#define VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT 8
606#define VMX_EXIT_INTERRUPTION_INFO_TYPE(a) ((a >> VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT) & 7)
607#define VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID RT_BIT(11)
608#define VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID(a) (a & VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID)
609#define VMX_EXIT_INTERRUPTION_INFO_NMI_UNBLOCK(a) (a & RT_BIT(12))
610#define VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT 31
611#define VMX_EXIT_INTERRUPTION_INFO_VALID(a) (a & RT_BIT(31))
612/** Construct an irq event injection value from the exit interruption info value (same except that bit 12 is reserved). */
613#define VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(a) (a & ~RT_BIT(12))
614/** @} */
615
616/** @name VMX_VMCS_RO_EXIT_INTERRUPTION_INFO_TYPE
617 * @{
618 */
619#define VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT 0
620#define VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI 2
621#define VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT 3
622#define VMX_EXIT_INTERRUPTION_INFO_TYPE_SW 4 /**< int xx */
623#define VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT 6
624/** @} */
625
626
627/** @name VMCS field encoding - 32 Bits guest state fields
628 * @{
629 */
630#define VMX_VMCS_GUEST_ES_LIMIT 0x4800
631#define VMX_VMCS_GUEST_CS_LIMIT 0x4802
632#define VMX_VMCS_GUEST_SS_LIMIT 0x4804
633#define VMX_VMCS_GUEST_DS_LIMIT 0x4806
634#define VMX_VMCS_GUEST_FS_LIMIT 0x4808
635#define VMX_VMCS_GUEST_GS_LIMIT 0x480A
636#define VMX_VMCS_GUEST_LDTR_LIMIT 0x480C
637#define VMX_VMCS_GUEST_TR_LIMIT 0x480E
638#define VMX_VMCS_GUEST_GDTR_LIMIT 0x4810
639#define VMX_VMCS_GUEST_IDTR_LIMIT 0x4812
640#define VMX_VMCS_GUEST_ES_ACCESS_RIGHTS 0x4814
641#define VMX_VMCS_GUEST_CS_ACCESS_RIGHTS 0x4816
642#define VMX_VMCS_GUEST_SS_ACCESS_RIGHTS 0x4818
643#define VMX_VMCS_GUEST_DS_ACCESS_RIGHTS 0x481A
644#define VMX_VMCS_GUEST_FS_ACCESS_RIGHTS 0x481C
645#define VMX_VMCS_GUEST_GS_ACCESS_RIGHTS 0x481E
646#define VMX_VMCS_GUEST_LDTR_ACCESS_RIGHTS 0x4820
647#define VMX_VMCS_GUEST_TR_ACCESS_RIGHTS 0x4822
648#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE 0x4824
649#define VMX_VMCS_GUEST_ACTIVITY_STATE 0x4826
650#define VMX_VMCS_GUEST_SYSENTER_CS 0x482A /**< MSR IA32_SYSENTER_CS */
651/** @} */
652
653
654/** @name VMX_VMCS_GUEST_ACTIVITY_STATE
655 * @{
656 */
657/** The logical processor is active. */
658#define VMX_CMS_GUEST_ACTIVITY_ACTIVE 0x0
659/** The logical processor is inactive, because executed a HLT instruction. */
660#define VMX_CMS_GUEST_ACTIVITY_HLT 0x1
661/** The logical processor is inactive, because of a triple fault or other serious error. */
662#define VMX_CMS_GUEST_ACTIVITY_SHUTDOWN 0x2
663/** The logical processor is inactive, because it's waiting for a startup-IPI */
664#define VMX_CMS_GUEST_ACTIVITY_SIPI_WAIT 0x3
665/** @} */
666
667
668/** @name VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE
669 * @{
670 */
671#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_STI RT_BIT(0)
672#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_MOVSS RT_BIT(1)
673#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_SMI RT_BIT(2)
674#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_NMI RT_BIT(3)
675/** @} */
676
677
678/** @name VMCS field encoding - 32 Bits host state fields
679 * @{
680 */
681#define VMX_VMCS_HOST_SYSENTER_CS 0x4C00
682/** @} */
683
684/** @name Natural width control fields
685 * @{
686 */
687#define VMX_VMCS_CTRL_CR0_MASK 0x6000
688#define VMX_VMCS_CTRL_CR4_MASK 0x6002
689#define VMX_VMCS_CTRL_CR0_READ_SHADOW 0x6004
690#define VMX_VMCS_CTRL_CR4_READ_SHADOW 0x6006
691#define VMX_VMCS_CTRL_CR3_TARGET_VAL0 0x6008
692#define VMX_VMCS_CTRL_CR3_TARGET_VAL1 0x600A
693#define VMX_VMCS_CTRL_CR3_TARGET_VAL2 0x600C
694#define VMX_VMCS_CTRL_CR3_TARGET_VAL31 0x600E
695/** @} */
696
697
698/** @name Natural width read-only data fields
699 * @{
700 */
701#define VMX_VMCS_RO_EXIT_QUALIFICATION 0x6400
702#define VMX_VMCS_RO_IO_RCX 0x6402
703#define VMX_VMCS_RO_IO_RSX 0x6404
704#define VMX_VMCS_RO_IO_RDI 0x6406
705#define VMX_VMCS_RO_IO_RIP 0x6408
706#define VMX_VMCS_EXIT_GUEST_LINEAR_ADDR 0x640A
707/** @} */
708
709
710/** @name VMX_VMCS_RO_EXIT_QUALIFICATION
711 * @{
712 */
713/** 0-2: Debug register number */
714#define VMX_EXIT_QUALIFICATION_DRX_REGISTER(a) (a & 7)
715/** 3: Reserved; cleared to 0. */
716#define VMX_EXIT_QUALIFICATION_DRX_RES1(a) ((a >> 3) & 1)
717/** 4: Direction of move (0 = write, 1 = read) */
718#define VMX_EXIT_QUALIFICATION_DRX_DIRECTION(a) ((a >> 4) & 1)
719/** 5-7: Reserved; cleared to 0. */
720#define VMX_EXIT_QUALIFICATION_DRX_RES2(a) ((a >> 5) & 7)
721/** 8-11: General purpose register number. */
722#define VMX_EXIT_QUALIFICATION_DRX_GENREG(a) ((a >> 8) & 0xF)
723/** Rest: reserved. */
724/** @} */
725
726/** @name VMX_EXIT_QUALIFICATION_DRX_DIRECTION values
727 * @{
728 */
729#define VMX_EXIT_QUALIFICATION_DRX_DIRECTION_WRITE 0
730#define VMX_EXIT_QUALIFICATION_DRX_DIRECTION_READ 1
731/** @} */
732
733
734
735/** @name CRx accesses
736 * @{
737 */
738/** 0-3: Control register number (0 for CLTS & LMSW) */
739#define VMX_EXIT_QUALIFICATION_CRX_REGISTER(a) (a & 0xF)
740/** 4-5: Access type. */
741#define VMX_EXIT_QUALIFICATION_CRX_ACCESS(a) ((a >> 4) & 3)
742/** 6: LMSW operand type */
743#define VMX_EXIT_QUALIFICATION_CRX_LMSW_OP(a) ((a >> 6) & 1)
744/** 7: Reserved; cleared to 0. */
745#define VMX_EXIT_QUALIFICATION_CRX_RES1(a) ((a >> 7) & 1)
746/** 8-11: General purpose register number (0 for CLTS & LMSW). */
747#define VMX_EXIT_QUALIFICATION_CRX_GENREG(a) ((a >> 8) & 0xF)
748/** 12-15: Reserved; cleared to 0. */
749#define VMX_EXIT_QUALIFICATION_CRX_RES2(a) ((a >> 12) & 0xF)
750/** 16-31: LMSW source data (else 0). */
751#define VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(a) ((a >> 16) & 0xFFFF)
752/** Rest: reserved. */
753/** @} */
754
755/** @name VMX_EXIT_QUALIFICATION_CRX_ACCESS
756 * @{
757 */
758#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_WRITE 0
759#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_READ 1
760#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_CLTS 2
761#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_LMSW 3
762/** @} */
763
764
765
766/** @name VMX_EXIT_PORT_IO
767 * @{
768 */
769/** 0-2: IO operation width. */
770#define VMX_EXIT_QUALIFICATION_IO_WIDTH(a) (a & 7)
771/** 3: IO operation direction. */
772#define VMX_EXIT_QUALIFICATION_IO_DIRECTION(a) ((a >> 3) & 1)
773/** 4: String IO operation. */
774#define VMX_EXIT_QUALIFICATION_IO_STRING(a) ((a >> 4) & 1)
775/** 5: Repeated IO operation. */
776#define VMX_EXIT_QUALIFICATION_IO_REP(a) ((a >> 5) & 1)
777/** 6: Operand encoding. */
778#define VMX_EXIT_QUALIFICATION_IO_ENCODING(a) ((a >> 6) & 1)
779/** 16-31: IO Port (0-0xffff). */
780#define VMX_EXIT_QUALIFICATION_IO_PORT(a) ((a >> 16) & 0xffff)
781/* Rest reserved. */
782/** @} */
783
784/** @name VMX_EXIT_QUALIFICATION_IO_DIRECTION
785 * @{
786 */
787#define VMX_EXIT_QUALIFICATION_IO_DIRECTION_OUT 0
788#define VMX_EXIT_QUALIFICATION_IO_DIRECTION_IN 1
789/** @} */
790
791
792/** @name VMX_EXIT_QUALIFICATION_IO_ENCODING
793 * @{
794 */
795#define VMX_EXIT_QUALIFICATION_IO_ENCODING_DX 0
796#define VMX_EXIT_QUALIFICATION_IO_ENCODING_IMM 1
797/** @} */
798
799/** @} */
800
801/** @name VMCS field encoding - Natural width guest state fields
802 * @{
803 */
804#define VMX_VMCS_GUEST_CR0 0x6800
805#define VMX_VMCS_GUEST_CR3 0x6802
806#define VMX_VMCS_GUEST_CR4 0x6804
807#define VMX_VMCS_GUEST_ES_BASE 0x6806
808#define VMX_VMCS_GUEST_CS_BASE 0x6808
809#define VMX_VMCS_GUEST_SS_BASE 0x680A
810#define VMX_VMCS_GUEST_DS_BASE 0x680C
811#define VMX_VMCS_GUEST_FS_BASE 0x680E
812#define VMX_VMCS_GUEST_GS_BASE 0x6810
813#define VMX_VMCS_GUEST_LDTR_BASE 0x6812
814#define VMX_VMCS_GUEST_TR_BASE 0x6814
815#define VMX_VMCS_GUEST_GDTR_BASE 0x6816
816#define VMX_VMCS_GUEST_IDTR_BASE 0x6818
817#define VMX_VMCS_GUEST_DR7 0x681A
818#define VMX_VMCS_GUEST_RSP 0x681C
819#define VMX_VMCS_GUEST_RIP 0x681E
820#define VMX_VMCS_GUEST_RFLAGS 0x6820
821#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS 0x6822
822#define VMX_VMCS_GUEST_SYSENTER_ESP 0x6824 /**< MSR IA32_SYSENTER_ESP */
823#define VMX_VMCS_GUEST_SYSENTER_EIP 0x6826 /**< MSR IA32_SYSENTER_EIP */
824/** @} */
825
826
827/** @name VMX_VMCS_GUEST_DEBUG_EXCEPTIONS
828 * @{
829 */
830/** Hardware breakpoint 0 was met. */
831#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B0 RT_BIT(0)
832/** Hardware breakpoint 1 was met. */
833#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B1 RT_BIT(1)
834/** Hardware breakpoint 2 was met. */
835#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B2 RT_BIT(2)
836/** Hardware breakpoint 3 was met. */
837#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B3 RT_BIT(3)
838/** At least one data or IO breakpoint was hit. */
839#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_BREAKPOINT_ENABLED RT_BIT(12)
840/** A debug exception would have been triggered by single-step execution mode. */
841#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_BS RT_BIT(14)
842/** Bits 4-11, 13 and 15-63 are reserved. */
843
844/** @} */
845
846/** @name VMCS field encoding - Natural width host state fields
847 * @{
848 */
849#define VMX_VMCS_HOST_CR0 0x6C00
850#define VMX_VMCS_HOST_CR3 0x6C02
851#define VMX_VMCS_HOST_CR4 0x6C04
852#define VMX_VMCS_HOST_FS_BASE 0x6C06
853#define VMX_VMCS_HOST_GS_BASE 0x6C08
854#define VMX_VMCS_HOST_TR_BASE 0x6C0A
855#define VMX_VMCS_HOST_GDTR_BASE 0x6C0C
856#define VMX_VMCS_HOST_IDTR_BASE 0x6C0E
857#define VMX_VMCS_HOST_SYSENTER_ESP 0x6C10
858#define VMX_VMCS_HOST_SYSENTER_EIP 0x6C12
859#define VMX_VMCS_HOST_RSP 0x6C14
860#define VMX_VMCS_HOST_RIP 0x6C16
861/** @} */
862
863/** @} */
864
865
866#if RT_INLINE_ASM_GNU_STYLE
867# define __STR(x) #x
868# define STR(x) __STR(x)
869#endif
870
871
872/** @defgroup grp_vmx_asm vmx assembly helpers
873 * @ingroup grp_vmx
874 * @{
875 */
876
877/**
878 * Executes VMXON
879 *
880 * @returns VBox status code
881 * @param pVMXOn Physical address of VMXON structure
882 */
883#if RT_INLINE_ASM_EXTERNAL || HC_ARCH_BITS == 64
884DECLASM(int) VMXEnable(RTHCPHYS pVMXOn);
885#else
886DECLINLINE(int) VMXEnable(RTHCPHYS pVMXOn)
887{
888 int rc = VINF_SUCCESS;
889# if RT_INLINE_ASM_GNU_STYLE
890 __asm__ __volatile__ (
891 "push %3 \n\t"
892 "push %2 \n\t"
893 ".byte 0xF3, 0x0F, 0xC7, 0x34, 0x24 # VMXON [esp] \n\t"
894 "ja 2f \n\t"
895 "je 1f \n\t"
896 "movl $"STR(VERR_VMX_INVALID_VMXON_PTR)", %0 \n\t"
897 "jmp 2f \n\t"
898 "1: \n\t"
899 "movl $"STR(VERR_VMX_GENERIC)", %0 \n\t"
900 "2: \n\t"
901 "add $8, %%esp \n\t"
902 :"=rm"(rc)
903 :"0"(VINF_SUCCESS),
904 "ir"((uint32_t)pVMXOn), /* don't allow direct memory reference here, */
905 "ir"((uint32_t)(pVMXOn >> 32)) /* this would not work with -fomit-frame-pointer */
906 :"memory"
907 );
908# else
909 __asm
910 {
911 push dword ptr [pVMXOn+4]
912 push dword ptr [pVMXOn]
913 _emit 0xF3
914 _emit 0x0F
915 _emit 0xC7
916 _emit 0x34
917 _emit 0x24 /* VMXON [esp] */
918 jnc vmxon_good
919 mov dword ptr [rc], VERR_VMX_INVALID_VMXON_PTR
920 jmp the_end
921
922vmxon_good:
923 jnz the_end
924 mov dword ptr [rc], VERR_VMX_GENERIC
925the_end:
926 add esp, 8
927 }
928# endif
929 return rc;
930}
931#endif
932
933
934/**
935 * Executes VMXOFF
936 */
937#if RT_INLINE_ASM_EXTERNAL || HC_ARCH_BITS == 64
938DECLASM(void) VMXDisable(void);
939#else
940DECLINLINE(void) VMXDisable(void)
941{
942# if RT_INLINE_ASM_GNU_STYLE
943 __asm__ __volatile__ (
944 ".byte 0x0F, 0x01, 0xC4 # VMXOFF \n\t"
945 );
946# else
947 __asm
948 {
949 _emit 0x0F
950 _emit 0x01
951 _emit 0xC4 /* VMXOFF */
952 }
953# endif
954}
955#endif
956
957
958/**
959 * Executes VMCLEAR
960 *
961 * @returns VBox status code
962 * @param pVMCS Physical address of VM control structure
963 */
964#if RT_INLINE_ASM_EXTERNAL || HC_ARCH_BITS == 64
965DECLASM(int) VMXClearVMCS(RTHCPHYS pVMCS);
966#else
967DECLINLINE(int) VMXClearVMCS(RTHCPHYS pVMCS)
968{
969 int rc = VINF_SUCCESS;
970# if RT_INLINE_ASM_GNU_STYLE
971 __asm__ __volatile__ (
972 "push %3 \n\t"
973 "push %2 \n\t"
974 ".byte 0x66, 0x0F, 0xC7, 0x34, 0x24 # VMCLEAR [esp] \n\t"
975 "jnc 1f \n\t"
976 "movl $"STR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
977 "1: \n\t"
978 "add $8, %%esp \n\t"
979 :"=rm"(rc)
980 :"0"(VINF_SUCCESS),
981 "ir"((uint32_t)pVMCS), /* don't allow direct memory reference here, */
982 "ir"((uint32_t)(pVMCS >> 32)) /* this would not work with -fomit-frame-pointer */
983 :"memory"
984 );
985# else
986 __asm
987 {
988 push dword ptr [pVMCS+4]
989 push dword ptr [pVMCS]
990 _emit 0x66
991 _emit 0x0F
992 _emit 0xC7
993 _emit 0x34
994 _emit 0x24 /* VMCLEAR [esp] */
995 jnc success
996 mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
997success:
998 add esp, 8
999 }
1000# endif
1001 return rc;
1002}
1003#endif
1004
1005
1006/**
1007 * Executes VMPTRLD
1008 *
1009 * @returns VBox status code
1010 * @param pVMCS Physical address of VMCS structure
1011 */
1012#if RT_INLINE_ASM_EXTERNAL || HC_ARCH_BITS == 64
1013DECLASM(int) VMXActivateVMCS(RTHCPHYS pVMCS);
1014#else
1015DECLINLINE(int) VMXActivateVMCS(RTHCPHYS pVMCS)
1016{
1017 int rc = VINF_SUCCESS;
1018# if RT_INLINE_ASM_GNU_STYLE
1019 __asm__ __volatile__ (
1020 "push %3 \n\t"
1021 "push %2 \n\t"
1022 ".byte 0x0F, 0xC7, 0x34, 0x24 # VMPTRLD [esp] \n\t"
1023 "jnc 1f \n\t"
1024 "movl $"STR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
1025 "1: \n\t"
1026 "add $8, %%esp \n\t"
1027 :"=rm"(rc)
1028 :"0"(VINF_SUCCESS),
1029 "ir"((uint32_t)pVMCS), /* don't allow direct memory reference here, */
1030 "ir"((uint32_t)(pVMCS >> 32)) /* this will not work with -fomit-frame-pointer */
1031 );
1032# else
1033 __asm
1034 {
1035 push dword ptr [pVMCS+4]
1036 push dword ptr [pVMCS]
1037 _emit 0x0F
1038 _emit 0xC7
1039 _emit 0x34
1040 _emit 0x24 /* VMPTRLD [esp] */
1041 jnc success
1042 mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
1043
1044success:
1045 add esp, 8
1046 }
1047# endif
1048 return rc;
1049}
1050#endif
1051
1052/**
1053 * Executes VMPTRST
1054 *
1055 * @returns VBox status code
1056 * @param pVMCS Address that will receive the current pointer
1057 */
1058DECLASM(int) VMXGetActivateVMCS(RTHCPHYS *pVMCS);
1059
1060/**
1061 * Executes VMWRITE
1062 *
1063 * @returns VBox status code
1064 * @param idxField VMCS index
1065 * @param u64Val 16, 32 or 64 bits value
1066 */
1067DECLASM(int) VMXWriteVMCS64(uint32_t idxField, uint64_t u64Val);
1068
1069/**
1070 * Executes VMWRITE
1071 *
1072 * @returns VBox status code
1073 * @param idxField VMCS index
1074 * @param u32Val 32 bits value
1075 */
1076#if RT_INLINE_ASM_EXTERNAL || HC_ARCH_BITS == 64
1077DECLASM(int) VMXWriteVMCS32(uint32_t idxField, uint32_t u32Val);
1078#else
1079DECLINLINE(int) VMXWriteVMCS32(uint32_t idxField, uint32_t u32Val)
1080{
1081 int rc = VINF_SUCCESS;
1082# if RT_INLINE_ASM_GNU_STYLE
1083 __asm__ __volatile__ (
1084 ".byte 0x0F, 0x79, 0xC2 # VMWRITE eax, edx \n\t"
1085 "ja 2f \n\t"
1086 "je 1f \n\t"
1087 "movl $"STR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
1088 "jmp 2f \n\t"
1089 "1: \n\t"
1090 "movl $"STR(VERR_VMX_INVALID_VMCS_FIELD)", %0 \n\t"
1091 "2: \n\t"
1092 :"=rm"(rc)
1093 :"0"(VINF_SUCCESS),
1094 "a"(idxField),
1095 "d"(u32Val)
1096 );
1097# else
1098 __asm
1099 {
1100 push dword ptr [u32Val]
1101 mov eax, [idxField]
1102 _emit 0x0F
1103 _emit 0x79
1104 _emit 0x04
1105 _emit 0x24 /* VMWRITE eax, [esp] */
1106 jnc valid_vmcs
1107 mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
1108 jmp the_end
1109
1110valid_vmcs:
1111 jnz the_end
1112 mov dword ptr [rc], VERR_VMX_INVALID_VMCS_FIELD
1113the_end:
1114 add esp, 4
1115 }
1116# endif
1117 return rc;
1118}
1119#endif
1120
1121#if HC_ARCH_BITS == 64
1122#define VMXWriteVMCS VMXWriteVMCS64
1123#else
1124#define VMXWriteVMCS VMXWriteVMCS32
1125#endif /* HC_ARCH_BITS == 64 */
1126
1127
1128/**
1129 * Executes VMREAD
1130 *
1131 * @returns VBox status code
1132 * @param idxField VMCS index
1133 * @param pData Ptr to store VM field value
1134 */
1135DECLASM(int) VMXReadVMCS64(uint32_t idxField, uint64_t *pData);
1136
1137/**
1138 * Executes VMREAD
1139 *
1140 * @returns VBox status code
1141 * @param idxField VMCS index
1142 * @param pData Ptr to store VM field value
1143 */
1144#if RT_INLINE_ASM_EXTERNAL || HC_ARCH_BITS == 64
1145DECLASM(int) VMXReadVMCS32(uint32_t idxField, uint32_t *pData);
1146#else
1147DECLINLINE(int) VMXReadVMCS32(uint32_t idxField, uint32_t *pData)
1148{
1149 int rc = VINF_SUCCESS;
1150# if RT_INLINE_ASM_GNU_STYLE
1151 __asm__ __volatile__ (
1152 "movl $"STR(VINF_SUCCESS)", %0 \n\t"
1153 ".byte 0x0F, 0x78, 0xc2 # VMREAD eax, edx \n\t"
1154 "ja 2f \n\t"
1155 "je 1f \n\t"
1156 "movl $"STR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
1157 "jmp 2f \n\t"
1158 "1: \n\t"
1159 "movl $"STR(VERR_VMX_INVALID_VMCS_FIELD)", %0 \n\t"
1160 "2: \n\t"
1161 :"=&r"(rc),
1162 "=d"(*pData)
1163 :"a"(idxField),
1164 "d"(0)
1165 );
1166# else
1167 __asm
1168 {
1169 sub esp, 4
1170 mov dword ptr [esp], 0
1171 mov eax, [idxField]
1172 _emit 0x0F
1173 _emit 0x78
1174 _emit 0x04
1175 _emit 0x24 /* VMREAD eax, [esp] */
1176 mov edx, pData
1177 pop dword ptr [edx]
1178 jnc valid_vmcs
1179 mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
1180 jmp the_end
1181
1182valid_vmcs:
1183 jnz the_end
1184 mov dword ptr [rc], VERR_VMX_INVALID_VMCS_FIELD
1185the_end:
1186 }
1187# endif
1188 return rc;
1189}
1190#endif
1191
1192#if HC_ARCH_BITS == 64
1193# define VMXReadVMCS VMXReadVMCS64
1194#else
1195# define VMXReadVMCS VMXReadVMCS32
1196#endif /* HC_ARCH_BITS == 64 */
1197
1198/**
1199 * Gets the last instruction error value from the current VMCS
1200 *
1201 * @returns error value
1202 */
1203DECLINLINE(uint32_t) VMXGetLastError(void)
1204{
1205#if HC_ARCH_BITS == 64
1206 uint64_t uLastError = 0;
1207 int rc = VMXReadVMCS(VMX_VMCS_RO_VM_INSTR_ERROR, &uLastError);
1208 AssertRC(rc);
1209 return (uint32_t)uLastError;
1210
1211#else /* 32-bit host: */
1212 uint32_t uLastError = 0;
1213 int rc = VMXReadVMCS32(VMX_VMCS_RO_VM_INSTR_ERROR, &uLastError);
1214 AssertRC(rc);
1215 return uLastError;
1216#endif
1217}
1218
1219/** @} */
1220
1221#endif
1222
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