hwacc_vmx.h@ 13043

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1	/** @file
2	* HWACCM - VMX Structures and Definitions.
3	*/
4
5	/*
6	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
7	*
8	* This file is part of VirtualBox Open Source Edition (OSE), as
9	* available from http://www.virtualbox.org. This file is free software;
10	* you can redistribute it and/or modify it under the terms of the GNU
11	* General Public License (GPL) as published by the Free Software
12	* Foundation, in version 2 as it comes in the "COPYING" file of the
13	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15	*
16	* The contents of this file may alternatively be used under the terms
17	* of the Common Development and Distribution License Version 1.0
18	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19	* VirtualBox OSE distribution, in which case the provisions of the
20	* CDDL are applicable instead of those of the GPL.
21	*
22	* You may elect to license modified versions of this file under the
23	* terms and conditions of either the GPL or the CDDL or both.
24	*
25	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
26	* Clara, CA 95054 USA or visit http://www.sun.com if you need
27	* additional information or have any questions.
28	*/
29
30	#ifndef ___VBox_vmx_h
31	#define ___VBox_vmx_h
32
33	#include <VBox/types.h>
34	#include <VBox/err.h>
35	#include <iprt/assert.h>
36	#include <iprt/asm.h>
37
38	/** @defgroup grp_vmx vmx Types and Definitions
39	* @ingroup grp_hwaccm
40	* @{
41	*/
42
43	/** @name VMX EPT paging structures
44	* @{
45	*/
46
47	/**
48	* Number of page table entries in the EPT. (PDPTE/PDE/PTE)
49	*/
50	#define EPT_PG_ENTRIES X86_PG_PAE_ENTRIES
51
52	/**
53	* EPT Page Directory Pointer Entry. Bit view.
54	*/
55	#pragma pack(1)
56	typedef struct EPTPML4EBITS
57	{
58	/** Present bit. */
59	uint64_t u1Present : 1;
60	/** Writable bit. */
61	uint64_t u1Write : 1;
62	/** Executable bit. */
63	uint64_t u1Execute : 1;
64	/** Reserved (must be 0). */
65	uint64_t u5Reserved : 5;
66	/** Available for software. */
67	uint64_t u4Available : 4;
68	/** Physical address of the next level (PD). Restricted by maximum physical address width of the cpu. */
69	uint64_t u40PhysAddr : 40;
70	/** Availabe for software. */
71	uint64_t u12Available : 12;
72	} EPTPML4EBITS;
73	#pragma pack()
74
75	/** Bits 12-51 - - EPT - Physical Page number of the next level. */
76	#define EPT_PML4E_PG_MASK X86_PML4E_PG_MASK_FULL
77	/** The page shift to get the PML4 index. */
78	#define EPT_PML4_SHIFT X86_PML4_SHIFT
79	/** The PML4 index mask (apply to a shifted page address). */
80	#define EPT_PML4_MASK X86_PML4_MASK
81
82	/**
83	* EPT PML4E.
84	*/
85	#pragma pack(1)
86	typedef union EPTPML4E
87	{
88	/** Normal view. */
89	EPTPML4EBITS n;
90	/** Unsigned integer view. */
91	X86PGUINT u;
92	/** 64 bit unsigned integer view. */
93	uint64_t au64[1];
94	/** 32 bit unsigned integer view. */
95	uint32_t au32[2];
96	} EPTPML4E;
97	#pragma pack()
98	/** Pointer to a PML4 table entry. */
99	typedef EPTPML4E *PEPTPML4E;
100	/** Pointer to a const PML4 table entry. */
101	typedef const EPTPML4E *PCEPTPML4E;
102	AssertCompileSize(EPTPML4E, 8);
103
104	/**
105	* EPT PML4 Table.
106	*/
107	#pragma pack(1)
108	typedef union EPTPML4
109	{
110	EPTPML4E a[EPT_PG_ENTRIES];
111	} EPTPML4;
112	#pragma pack()
113	/** Pointer to an EPT PML4 Table. */
114	typedef EPTPML4 *PEPTPML4;
115	/** Pointer to a const EPT PML4 Table. */
116	typedef const EPTPML4 *PCEPTPML4;
117
118	/**
119	* EPT Page Directory Pointer Entry. Bit view.
120	*/
121	#pragma pack(1)
122	typedef struct EPTPDPTEBITS
123	{
124	/** Present bit. */
125	uint64_t u1Present : 1;
126	/** Writable bit. */
127	uint64_t u1Write : 1;
128	/** Executable bit. */
129	uint64_t u1Execute : 1;
130	/** Reserved (must be 0). */
131	uint64_t u5Reserved : 5;
132	/** Available for software. */
133	uint64_t u4Available : 4;
134	/** Physical address of the next level (PD). Restricted by maximum physical address width of the cpu. */
135	uint64_t u40PhysAddr : 40;
136	/** Availabe for software. */
137	uint64_t u12Available : 12;
138	} EPTPDPTEBITS;
139	#pragma pack()
140
141	/** Bits 12-51 - - EPT - Physical Page number of the next level. */
142	#define EPT_PDPTE_PG_MASK X86_PDPE_PG_MASK_FULL
143	/** The page shift to get the PDPT index. */
144	#define EPT_PDPT_SHIFT X86_PDPT_SHIFT
145	/** The PDPT index mask (apply to a shifted page address). */
146	#define EPT_PDPT_MASK X86_PDPT_MASK_AMD64
147
148	/**
149	* EPT Page Directory Pointer.
150	*/
151	#pragma pack(1)
152	typedef union EPTPDPTE
153	{
154	/** Normal view. */
155	EPTPDPTEBITS n;
156	/** Unsigned integer view. */
157	X86PGUINT u;
158	/** 64 bit unsigned integer view. */
159	uint64_t au64[1];
160	/** 32 bit unsigned integer view. */
161	uint32_t au32[2];
162	} EPTPDPTE;
163	#pragma pack()
164	/** Pointer to an EPT Page Directory Pointer Entry. */
165	typedef EPTPDPTE *PEPTPDPTE;
166	/** Pointer to a const EPT Page Directory Pointer Entry. */
167	typedef const EPTPDPTE *PCEPTPDPTE;
168	AssertCompileSize(EPTPDPTE, 8);
169
170	/**
171	* EPT Page Directory Pointer Table.
172	*/
173	#pragma pack(1)
174	typedef union EPTPDPT
175	{
176	EPTPDPTE a[EPT_PG_ENTRIES];
177	} EPTPDPT;
178	#pragma pack()
179	/** Pointer to an EPT Page Directory Pointer Table. */
180	typedef EPTPDPT *PEPTPDPT;
181	/** Pointer to a const EPT Page Directory Pointer Table. */
182	typedef const EPTPDPT *PCEPTPDPT;
183
184
185	/**
186	* EPT Page Directory Table Entry. Bit view.
187	*/
188	#pragma pack(1)
189	typedef union EPTPDEBITS
190	{
191	/** Present bit. */
192	uint64_t u1Present : 1;
193	/** Writable bit. */
194	uint64_t u1Write : 1;
195	/** Executable bit. */
196	uint64_t u1Execute : 1;
197	/** Reserved (must be 0). */
198	uint64_t u4Reserved : 4;
199	/** Big page (must be 0 here). */
200	uint64_t u1Big : 1;
201	/** Available for software. */
202	uint64_t u4Available : 4;
203	/** Physical address of page table. Restricted by maximum physical address width of the cpu. */
204	uint64_t u40PhysAddr : 40;
205	/** Availabe for software. */
206	uint64_t u12Available : 12;
207	} EPTPDEBITS;
208	#pragma pack()
209
210	/** Bits 12-51 - - EPT - Physical Page number of the next level. */
211	#define EPT_PDE_PG_MASK X86_PDE_PAE_PG_MASK_FULL
212	/** The page shift to get the PD index. */
213	#define EPT_PD_SHIFT X86_PD_PAE_SHIFT
214	/** The PD index mask (apply to a shifted page address). */
215	#define EPT_PD_MASK X86_PD_PAE_MASK
216
217	/**
218	* EPT 2MB Page Directory Table Entry. Bit view.
219	*/
220	#pragma pack(1)
221	typedef union EPTPDE2MBITS
222	{
223	/** Present bit. */
224	uint64_t u1Present : 1;
225	/** Writable bit. */
226	uint64_t u1Write : 1;
227	/** Executable bit. */
228	uint64_t u1Execute : 1;
229	/** EPT Table Memory Type. MBZ for non-leaf nodes. */
230	uint64_t u3EMT : 3;
231	/** Ignore PAT memory type */
232	uint64_t u1IgnorePAT : 1;
233	/** Big page (must be 1 here). */
234	uint64_t u1Big : 1;
235	/** Available for software. */
236	uint64_t u4Available : 4;
237	/** Reserved (must be 0). */
238	uint64_t u9Reserved : 9;
239	/** Physical address of the 2MB page. Restricted by maximum physical address width of the cpu. */
240	uint64_t u31PhysAddr : 31;
241	/** Availabe for software. */
242	uint64_t u12Available : 12;
243	} EPTPDE2MBITS;
244	#pragma pack()
245
246	/** Bits 21-51 - - EPT - Physical Page number of the next level. */
247	#define EPT_PDE2M_PG_MASK ( 0x000fffffffe00000ULL )
248
249	/**
250	* EPT Page Directory Table Entry.
251	*/
252	#pragma pack(1)
253	typedef union EPTPDE
254	{
255	/** Normal view. */
256	EPTPDEBITS n;
257	/** 2MB view (big). */
258	EPTPDE2MBITS b;
259	/** Unsigned integer view. */
260	X86PGUINT u;
261	/** 64 bit unsigned integer view. */
262	uint64_t au64[1];
263	/** 32 bit unsigned integer view. */
264	uint32_t au32[2];
265	} EPTPDE;
266	#pragma pack()
267	/** Pointer to an EPT Page Directory Table Entry. */
268	typedef EPTPDE *PEPTPDE;
269	/** Pointer to a const EPT Page Directory Table Entry. */
270	typedef const EPTPDE *PCEPTPDE;
271	AssertCompileSize(EPTPDE, 8);
272
273	/**
274	* EPT Page Directory Table.
275	*/
276	#pragma pack(1)
277	typedef union EPTPD
278	{
279	EPTPDE a[EPT_PG_ENTRIES];
280	} EPTPD;
281	#pragma pack()
282	/** Pointer to an EPT Page Directory Table. */
283	typedef EPTPD *PEPTPD;
284	/** Pointer to a const EPT Page Directory Table. */
285	typedef const EPTPD *PCEPTPD;
286
287
288	/**
289	* EPT Page Table Entry. Bit view.
290	*/
291	#pragma pack(1)
292	typedef union EPTPTEBITS
293	{
294	/** Present bit. */
295	uint64_t u1Present : 1;
296	/** Writable bit. */
297	uint64_t u1Write : 1;
298	/** Executable bit. */
299	uint64_t u1Execute : 1;
300	/** EPT Table Memory Type. MBZ for non-leaf nodes. */
301	uint64_t u3EMT : 3;
302	/** Ignore PAT memory type */
303	uint64_t u1IgnorePAT : 1;
304	/** Available for software. */
305	uint64_t u5Available : 5;
306	/** Physical address of page. Restricted by maximum physical address width of the cpu. */
307	uint64_t u40PhysAddr : 40;
308	/** Availabe for software. */
309	uint64_t u12Available : 12;
310	} EPTPTEBITS;
311	#pragma pack()
312
313	/** Bits 12-51 - - EPT - Physical Page number of the next level. */
314	#define EPT_PTE_PG_MASK X86_PTE_PAE_PG_MASK_FULL
315	/** The page shift to get the EPT PTE index. */
316	#define EPT_PT_SHIFT X86_PT_PAE_SHIFT
317	/** The EPT PT index mask (apply to a shifted page address). */
318	#define EPT_PT_MASK X86_PT_PAE_MASK
319
320	/**
321	* EPT Page Table Entry.
322	*/
323	#pragma pack(1)
324	typedef union EPTPTE
325	{
326	/** Normal view. */
327	EPTPTEBITS n;
328	/** Unsigned integer view. */
329	X86PGUINT u;
330	/** 64 bit unsigned integer view. */
331	uint64_t au64[1];
332	/** 32 bit unsigned integer view. */
333	uint32_t au32[2];
334	} EPTPTE;
335	#pragma pack()
336	/** Pointer to an EPT Page Directory Table Entry. */
337	typedef EPTPTE *PEPTPTE;
338	/** Pointer to a const EPT Page Directory Table Entry. */
339	typedef const EPTPTE *PCEPTPTE;
340	AssertCompileSize(EPTPTE, 8);
341
342	/**
343	* EPT Page Table.
344	*/
345	#pragma pack(1)
346	typedef union EPTPT
347	{
348	EPTPTE a[EPT_PG_ENTRIES];
349	} EPTPT;
350	#pragma pack()
351	/** Pointer to an extended page table. */
352	typedef EPTPT *PEPTPT;
353	/** Pointer to a const extended table. */
354	typedef const EPTPT *PCEPTPT;
355
356	/** @} */
357
358
359	/** @name VMX Basic Exit Reasons.
360	* @{
361	*/
362	/** And-mask for setting reserved bits to zero */
363	#define VMX_EFLAGS_RESERVED_0 (~0xffc08028)
364	/** Or-mask for setting reserved bits to 1 */
365	#define VMX_EFLAGS_RESERVED_1 0x00000002
366	/** @} */
367
368	/** @name VMX Basic Exit Reasons.
369	* @{
370	*/
371	/** 0 Exception or non-maskable interrupt (NMI). */
372	#define VMX_EXIT_EXCEPTION 0
373	/** 1 External interrupt. */
374	#define VMX_EXIT_EXTERNAL_IRQ 1
375	/** 2 Triple fault. */
376	#define VMX_EXIT_TRIPLE_FAULT 2
377	/** 3 INIT signal. */
378	#define VMX_EXIT_INIT_SIGNAL 3
379	/** 4 Start-up IPI (SIPI). */
380	#define VMX_EXIT_SIPI 4
381	/** 5 I/O system-management interrupt (SMI). */
382	#define VMX_EXIT_IO_SMI_IRQ 5
383	/** 6 Other SMI. */
384	#define VMX_EXIT_SMI_IRQ 6
385	/** 7 Interrupt window. */
386	#define VMX_EXIT_IRQ_WINDOW 7
387	/** 9 Task switch. */
388	#define VMX_EXIT_TASK_SWITCH 9
389	/** 10 Guest software attempted to execute CPUID. */
390	#define VMX_EXIT_CPUID 10
391	/** 12 Guest software attempted to execute HLT. */
392	#define VMX_EXIT_HLT 12
393	/** 13 Guest software attempted to execute INVD. */
394	#define VMX_EXIT_INVD 13
395	/** 14 Guest software attempted to execute INVPG. */
396	#define VMX_EXIT_INVPG 14
397	/** 15 Guest software attempted to execute RDPMC. */
398	#define VMX_EXIT_RDPMC 15
399	/** 16 Guest software attempted to execute RDTSC. */
400	#define VMX_EXIT_RDTSC 16
401	/** 17 Guest software attempted to execute RSM in SMM. */
402	#define VMX_EXIT_RSM 17
403	/** 18 Guest software executed VMCALL. */
404	#define VMX_EXIT_VMCALL 18
405	/** 19 Guest software executed VMCLEAR. */
406	#define VMX_EXIT_VMCLEAR 19
407	/** 20 Guest software executed VMLAUNCH. */
408	#define VMX_EXIT_VMLAUNCH 20
409	/** 21 Guest software executed VMPTRLD. */
410	#define VMX_EXIT_VMPTRLD 21
411	/** 22 Guest software executed VMPTRST. */
412	#define VMX_EXIT_VMPTRST 22
413	/** 23 Guest software executed VMREAD. */
414	#define VMX_EXIT_VMREAD 23
415	/** 24 Guest software executed VMRESUME. */
416	#define VMX_EXIT_VMRESUME 24
417	/** 25 Guest software executed VMWRITE. */
418	#define VMX_EXIT_VMWRITE 25
419	/** 26 Guest software executed VMXOFF. */
420	#define VMX_EXIT_VMXOFF 26
421	/** 27 Guest software executed VMXON. */
422	#define VMX_EXIT_VMXON 27
423	/** 28 Control-register accesses. */
424	#define VMX_EXIT_CRX_MOVE 28
425	/** 29 Debug-register accesses. */
426	#define VMX_EXIT_DRX_MOVE 29
427	/** 30 I/O instruction. */
428	#define VMX_EXIT_PORT_IO 30
429	/** 31 RDMSR. Guest software attempted to execute RDMSR. */
430	#define VMX_EXIT_RDMSR 31
431	/** 32 WRMSR. Guest software attempted to execute WRMSR. */
432	#define VMX_EXIT_WRMSR 32
433	/** 33 VM-entry failure due to invalid guest state. */
434	#define VMX_EXIT_ERR_INVALID_GUEST_STATE 33
435	/** 34 VM-entry failure due to MSR loading. */
436	#define VMX_EXIT_ERR_MSR_LOAD 34
437	/** 36 Guest software executed MWAIT. */
438	#define VMX_EXIT_MWAIT 36
439	/** 39 Guest software attempted to execute MONITOR. */
440	#define VMX_EXIT_MONITOR 39
441	/** 40 Guest software attempted to execute PAUSE. */
442	#define VMX_EXIT_PAUSE 40
443	/** 41 VM-entry failure due to machine-check. */
444	#define VMX_EXIT_ERR_MACHINE_CHECK 41
445	/** 43 TPR below threshold. Guest software executed MOV to CR8. */
446	#define VMX_EXIT_TPR 43
447	/** 44 APIC access. Guest software attempted to access memory at a physical address on the APIC-access page. */
448	#define VMX_EXIT_APIC_ACCESS 44
449	/** 46 Access to GDTR or IDTR. Guest software attempted to execute LGDT, LIDT, SGDT, or SIDT. */
450	#define VMX_EXIT_XDTR_ACCESS 46
451	/** 47 Access to LDTR or TR. Guest software attempted to execute LLDT, LTR, SLDT, or STR. */
452	#define VMX_EXIT_TR_ACCESS 47
453	/** 48 EPT violation. An attempt to access memory with a guest-physical address was disallowed by the configuration of the EPT paging structures. */
454	#define VMX_EXIT_EPT_VIOLATION 48
455	/** 49 EPT misconfiguration. An attempt to access memory with a guest-physical address encountered a misconfigured EPT paging-structure entry. */
456	#define VMX_EXIT_EPT_MISCONFIG 49
457	/** 50 INVEPT. Guest software attempted to execute INVEPT. */
458	#define VMX_EXIT_INVEPT 50
459	/** 52 VMX-preemption timer expired. The preemption timer counted down to zero. */
460	#define VMX_EXIT_PREEMPTION_TIMER 52
461	/** 53 INVVPID. Guest software attempted to execute INVVPID. */
462	#define VMX_EXIT_INVVPID 53
463	/** 54 WBINVD. Guest software attempted to execute WBINVD. */
464	#define VMX_EXIT_WBINVD 54
465	/** 55 XSETBV. Guest software attempted to execute XSETBV. */
466	#define VMX_EXIT_XSETBV 55
467	/** @} */
468
469
470	/** @name VM Instruction Errors
471	* @{
472	*/
473	/** 1 VMCALL executed in VMX root operation. */
474	#define VMX_ERROR_VMCALL 1
475	/** 2 VMCLEAR with invalid physical address. */
476	#define VMX_ERROR_VMCLEAR_INVALID_PHYS_ADDR 2
477	/** 3 VMCLEAR with VMXON pointer. */
478	#define VMX_ERROR_VMCLEAR_INVALID_VMXON_PTR 3
479	/** 4 VMLAUNCH with non-clear VMCS. */
480	#define VMX_ERROR_VMLAUCH_NON_CLEAR_VMCS 4
481	/** 5 VMRESUME with non-launched VMCS. */
482	#define VMX_ERROR_VMRESUME_NON_LAUNCHED_VMCS 5
483	/** 6 VMRESUME with a corrupted VMCS (indicates corruption of the current VMCS). */
484	#define VMX_ERROR_VMRESUME_CORRUPTED_VMCS 6
485	/** 7 VM entry with invalid control field(s). */
486	#define VMX_ERROR_VMENTRY_INVALID_CONTROL_FIELDS 7
487	/** 8 VM entry with invalid host-state field(s). */
488	#define VMX_ERROR_VMENTRY_INVALID_HOST_STATE 8
489	/** 9 VMPTRLD with invalid physical address. */
490	#define VMX_ERROR_VMPTRLD_INVALID_PHYS_ADDR 9
491	/** 10 VMPTRLD with VMXON pointer. */
492	#define VMX_ERROR_VMPTRLD_VMXON_PTR 10
493	/** 11 VMPTRLD with incorrect VMCS revision identifier. */
494	#define VMX_ERROR_VMPTRLD_WRONG_VMCS_REVISION 11
495	/** 12 VMREAD/VMWRITE from/to unsupported VMCS component. */
496	#define VMX_ERROR_VMREAD_INVALID_COMPONENT 12
497	#define VMX_ERROR_VMWRITE_INVALID_COMPONENT VMX_ERROR_VMREAD_INVALID_COMPONENT
498	/** 13 VMWRITE to read-only VMCS component. */
499	#define VMX_ERROR_VMWRITE_READONLY_COMPONENT 13
500	/** 15 VMXON executed in VMX root operation. */
501	#define VMX_ERROR_VMXON_IN_VMX_ROOT_OP 15
502	/** 16 VM entry with invalid executive-VMCS pointer. */
503	#define VMX_ERROR_VMENTRY_INVALID_VMCS_EXEC_PTR 16
504	/** 17 VM entry with non-launched executive VMCS. */
505	#define VMX_ERROR_VMENTRY_NON_LAUNCHED_EXEC_VMCS 17
506	/** 18 VM entry with executive-VMCS pointer not VMXON pointer. */
507	#define VMX_ERROR_VMENTRY_EXEC_VMCS_PTR 18
508	/** 19 VMCALL with non-clear VMCS. */
509	#define VMX_ERROR_VMCALL_NON_CLEAR_VMCS 19
510	/** 20 VMCALL with invalid VM-exit control fields. */
511	#define VMX_ERROR_VMCALL_INVALID_VMEXIT_FIELDS 20
512	/** 22 VMCALL with incorrect MSEG revision identifier. */
513	#define VMX_ERROR_VMCALL_INVALID_MSEG_REVISION 22
514	/** 23 VMXOFF under dual-monitor treatment of SMIs and SMM. */
515	#define VMX_ERROR_VMXOFF_DUAL_MONITOR 23
516	/** 24 VMCALL with invalid SMM-monitor features. */
517	#define VMX_ERROR_VMCALL_INVALID_SMM_MONITOR 24
518	/** 25 VM entry with invalid VM-execution control fields in executive VMCS. */
519	#define VMX_ERROR_VMENTRY_INVALID_VM_EXEC_CTRL 25
520	/** 26 VM entry with events blocked by MOV SS. */
521	#define VMX_ERROR_VMENTRY_MOV_SS 26
522
523	/** @} */
524
525
526	/** @name VMX MSRs - Basic VMX information.
527	* @{
528	*/
529	/** VMCS revision identifier used by the processor. */
530	#define MSR_IA32_VMX_BASIC_INFO_VMCS_ID(a) (a & 0x7FFFFFFF)
531	/** Size of the VMCS. */
532	#define MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(a) ((a >> 32ULL) & 0xFFF)
533	/** Width of physical address used for the VMCS.
534	* 0 -> limited to the available amount of physical ram
535	* 1 -> within the first 4 GB
536	*/
537	#define MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(a) ((a >> 48ULL) & 1)
538	/** Whether the processor supports the dual-monitor treatment of system-management interrupts and system-management code. (always 1) */
539	#define MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(a) ((a >> 49ULL) & 1)
540	/** Memory type that must be used for the VMCS. */
541	#define MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(a) ((a >> 50ULL) & 0xF)
542	/** @} */
543
544
545	/** @name VMX MSRs - Misc VMX info.
546	* @{
547	*/
548	/** Activity states supported by the implementation. */
549	#define MSR_IA32_VMX_MISC_ACTIVITY_STATES(a) ((a >> 6ULL) & 0x7)
550	/** Number of CR3 target values supported by the processor. (0-256) */
551	#define MSR_IA32_VMX_MISC_CR3_TARGET(a) ((a >> 16ULL) & 0x1FF)
552	/** Maximum nr of MSRs in the VMCS. (N+1)512. /
553	#define MSR_IA32_VMX_MISC_MAX_MSR(a) ((((a >> 25ULL) & 0x7) + 1) * 512)
554	/** MSEG revision identifier used by the processor. */
555	#define MSR_IA32_VMX_MISC_MSEG_ID(a) (a >> 32ULL)
556	/** @} */
557
558
559	/** @name VMX MSRs - VMCS enumeration field info
560	* @{
561	*/
562	/** Highest field index. */
563	#define MSR_IA32_VMX_VMCS_ENUM_HIGHEST_INDEX(a) ((a >> 1ULL) & 0x1FF)
564
565	/** @} */
566
567
568	/** @name MSR_IA32_VMX_EPT_CAPS; EPT capabilities MSR
569	* @{
570	*/
571	#define MSR_IA32_VMX_EPT_CAPS_RWX_X_ONLY RT_BIT_64(0)
572	#define MSR_IA32_VMX_EPT_CAPS_RWX_W_ONLY RT_BIT_64(1)
573	#define MSR_IA32_VMX_EPT_CAPS_RWX_WX_ONLY RT_BIT_64(2)
574	#define MSR_IA32_VMX_EPT_CAPS_GAW_21_BITS RT_BIT_64(3)
575	#define MSR_IA32_VMX_EPT_CAPS_GAW_30_BITS RT_BIT_64(4)
576	#define MSR_IA32_VMX_EPT_CAPS_GAW_39_BITS RT_BIT_64(5)
577	#define MSR_IA32_VMX_EPT_CAPS_GAW_48_BITS RT_BIT_64(6)
578	#define MSR_IA32_VMX_EPT_CAPS_GAW_57_BITS RT_BIT_64(7)
579	#define MSR_IA32_VMX_EPT_CAPS_EMT_UC RT_BIT_64(8)
580	#define MSR_IA32_VMX_EPT_CAPS_EMT_WC RT_BIT_64(9)
581	#define MSR_IA32_VMX_EPT_CAPS_EMT_WT RT_BIT_64(12)
582	#define MSR_IA32_VMX_EPT_CAPS_EMT_WP RT_BIT_64(13)
583	#define MSR_IA32_VMX_EPT_CAPS_EMT_WB RT_BIT_64(14)
584	#define MSR_IA32_VMX_EPT_CAPS_SP_21_BITS RT_BIT_64(16)
585	#define MSR_IA32_VMX_EPT_CAPS_SP_30_BITS RT_BIT_64(17)
586	#define MSR_IA32_VMX_EPT_CAPS_SP_39_BITS RT_BIT_64(18)
587	#define MSR_IA32_VMX_EPT_CAPS_SP_48_BITS RT_BIT_64(19)
588	#define MSR_IA32_VMX_EPT_CAPS_INVEPT RT_BIT_64(20)
589	#define MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV RT_BIT_64(24)
590	#define MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT RT_BIT_64(25)
591	#define MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL RT_BIT_64(26)
592	#define MSR_IA32_VMX_EPT_CAPS_INVVPID RT_BIT_64(32)
593	#define MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV RT_BIT_64(40)
594	#define MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT RT_BIT_64(41)
595	#define MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL RT_BIT_64(42)
596	#define MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT_GLOBAL RT_BIT_64(43)
597
598	/** @} */
599
600	/** @name Extended Page Table Pointer (EPTP)
601	* @{
602	*/
603	/** Uncachable EPT paging structure memory type. */
604	#define VMX_EPT_MEMTYPE_UC 0
605	/** Write-back EPT paging structure memory type. */
606	#define VMX_EPT_MEMTYPE_WB 6
607	/** Shift value to get the EPT page walk length (bits 5-3) */
608	#define VMX_EPT_PAGE_WALK_LENGTH_SHIFT 3
609	/** Mask value to get the EPT page walk length (bits 5-3) */
610	#define VMX_EPT_PAGE_WALK_LENGTH_MASK 7
611	/** Default EPT page walk length */
612	#define VMX_EPT_PAGE_WALK_LENGTH_DEFAULT 3
613	/** @} */
614
615
616	/** @name VMCS field encoding - 16 bits guest fields
617	* @{
618	*/
619	#define VMX_VMCS_GUEST_FIELD_VPID 0x0
620	#define VMX_VMCS_GUEST_FIELD_ES 0x800
621	#define VMX_VMCS_GUEST_FIELD_CS 0x802
622	#define VMX_VMCS_GUEST_FIELD_SS 0x804
623	#define VMX_VMCS_GUEST_FIELD_DS 0x806
624	#define VMX_VMCS_GUEST_FIELD_FS 0x808
625	#define VMX_VMCS_GUEST_FIELD_GS 0x80A
626	#define VMX_VMCS_GUEST_FIELD_LDTR 0x80C
627	#define VMX_VMCS_GUEST_FIELD_TR 0x80E
628	/** @} */
629
630	/** @name VMCS field encoding - 16 bits host fields
631	* @{
632	*/
633	#define VMX_VMCS_HOST_FIELD_ES 0xC00
634	#define VMX_VMCS_HOST_FIELD_CS 0xC02
635	#define VMX_VMCS_HOST_FIELD_SS 0xC04
636	#define VMX_VMCS_HOST_FIELD_DS 0xC06
637	#define VMX_VMCS_HOST_FIELD_FS 0xC08
638	#define VMX_VMCS_HOST_FIELD_GS 0xC0A
639	#define VMX_VMCS_HOST_FIELD_TR 0xC0C
640	/** @} */
641
642	/** @name VMCS field encoding - 64 bits host fields
643	* @{
644	*/
645	#define VMX_VMCS_HOST_FIELD_PAT_FULL 0x2C00
646	#define VMX_VMCS_HOST_FIELD_PAT_HIGH 0x2C01
647	#define VMX_VMCS_HOST_FIELD_EFER_FULL 0x2C02
648	#define VMX_VMCS_HOST_FIELD_EFER_HIGH 0x2C03
649	#define VMX_VMCS_HOST_PERF_GLOBAL_CTRL_FULL 0x2C04 /*< MSR IA32_PERF_GLOBAL_CTRL /
650	#define VMX_VMCS_HOST_PERF_GLOBAL_CTRL_HIGH 0x2C05 /*< MSR IA32_PERF_GLOBAL_CTRL /
651	/** @} */
652
653
654	/** @name VMCS field encoding - 64 Bits control fields
655	* @{
656	*/
657	#define VMX_VMCS_CTRL_IO_BITMAP_A_FULL 0x2000
658	#define VMX_VMCS_CTRL_IO_BITMAP_A_HIGH 0x2001
659	#define VMX_VMCS_CTRL_IO_BITMAP_B_FULL 0x2002
660	#define VMX_VMCS_CTRL_IO_BITMAP_B_HIGH 0x2003
661
662	/* Optional */
663	#define VMX_VMCS_CTRL_MSR_BITMAP_FULL 0x2004
664	#define VMX_VMCS_CTRL_MSR_BITMAP_HIGH 0x2005
665
666	#define VMX_VMCS_CTRL_VMEXIT_MSR_STORE_FULL 0x2006
667	#define VMX_VMCS_CTRL_VMEXIT_MSR_STORE_HIGH 0x2007
668	#define VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_FULL 0x2008
669	#define VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_HIGH 0x2009
670
671	#define VMX_VMCS_CTRL_VMENTRY_MSR_LOAD_FULL 0x200A
672	#define VMX_VMCS_CTRL_VMENTRY_MSR_LOAD_HIGH 0x200B
673
674	#define VMX_VMCS_CTRL_EXEC_VMCS_PTR_FULL 0x200C
675	#define VMX_VMCS_CTRL_EXEC_VMCS_PTR_HIGH 0x200D
676
677	#define VMX_VMCS_CTRL_TSC_OFFSET_FULL 0x2010
678	#define VMX_VMCS_CTRL_TSC_OFFSET_HIGH 0x2011
679
680	/** Optional (VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW) */
681	#define VMX_VMCS_CTRL_VAPIC_PAGEADDR_FULL 0x2012
682	#define VMX_VMCS_CTRL_VAPIC_PAGEADDR_HIGH 0x2013
683
684	/** Optional (VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC) */
685	#define VMX_VMCS_CTRL_APIC_ACCESSADDR_FULL 0x2014
686	#define VMX_VMCS_CTRL_APIC_ACCESSADDR_HIGH 0x2015
687
688	/** Extended page table pointer. */
689	#define VMX_VMCS_CTRL_EPTP_FULL 0x201a
690	#define VMX_VMCS_CTRL_EPTP_HIGH 0x201b
691
692	/** VM-exit phyiscal address. */
693	#define VMX_VMCS_EXIT_PHYS_ADDR_FULL 0x2400
694	#define VMX_VMCS_EXIT_PHYS_ADDR_HIGH 0x2401
695	/** @} */
696
697
698	/** @name VMCS field encoding - 64 Bits guest fields
699	* @{
700	*/
701	#define VMX_VMCS_GUEST_LINK_PTR_FULL 0x2800
702	#define VMX_VMCS_GUEST_LINK_PTR_HIGH 0x2801
703	#define VMX_VMCS_GUEST_DEBUGCTL_FULL 0x2802 /*< MSR IA32_DEBUGCTL /
704	#define VMX_VMCS_GUEST_DEBUGCTL_HIGH 0x2803 /*< MSR IA32_DEBUGCTL /
705	#define VMX_VMCS_GUEST_PAT_FULL 0x2804
706	#define VMX_VMCS_GUEST_PAT_HIGH 0x2805
707	#define VMX_VMCS_GUEST_EFER_FULL 0x2806
708	#define VMX_VMCS_GUEST_EFER_HIGH 0x2807
709	#define VMX_VMCS_GUEST_PERF_GLOBAL_CTRL_FULL 0x2808 /*< MSR IA32_PERF_GLOBAL_CTRL /
710	#define VMX_VMCS_GUEST_PERF_GLOBAL_CTRL_HIGH 0x2809 /*< MSR IA32_PERF_GLOBAL_CTRL /
711	#define VMX_VMCS_GUEST_PDPTR0_FULL 0x280A
712	#define VMX_VMCS_GUEST_PDPTR0_HIGH 0x280B
713	#define VMX_VMCS_GUEST_PDPTR1_FULL 0x280C
714	#define VMX_VMCS_GUEST_PDPTR1_HIGH 0x280D
715	#define VMX_VMCS_GUEST_PDPTR2_FULL 0x280E
716	#define VMX_VMCS_GUEST_PDPTR2_HIGH 0x280F
717	#define VMX_VMCS_GUEST_PDPTR3_FULL 0x2810
718	#define VMX_VMCS_GUEST_PDPTR3_HIGH 0x2811
719	/** @} */
720
721
722	/** @name VMCS field encoding - 32 Bits control fields
723	* @{
724	*/
725	#define VMX_VMCS_CTRL_PIN_EXEC_CONTROLS 0x4000
726	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS 0x4002
727	#define VMX_VMCS_CTRL_EXCEPTION_BITMAP 0x4004
728	#define VMX_VMCS_CTRL_PAGEFAULT_ERROR_MASK 0x4006
729	#define VMX_VMCS_CTRL_PAGEFAULT_ERROR_MATCH 0x4008
730	#define VMX_VMCS_CTRL_CR3_TARGET_COUNT 0x400A
731	#define VMX_VMCS_CTRL_EXIT_CONTROLS 0x400C
732	#define VMX_VMCS_CTRL_EXIT_MSR_STORE_COUNT 0x400E
733	#define VMX_VMCS_CTRL_EXIT_MSR_LOAD_COUNT 0x4010
734	#define VMX_VMCS_CTRL_ENTRY_CONTROLS 0x4012
735	#define VMX_VMCS_CTRL_ENTRY_MSR_LOAD_COUNT 0x4014
736	#define VMX_VMCS_CTRL_ENTRY_IRQ_INFO 0x4016
737	#define VMX_VMCS_CTRL_ENTRY_EXCEPTION_ERRCODE 0x4018
738	#define VMX_VMCS_CTRL_ENTRY_INSTR_LENGTH 0x401A
739	/** This field exists only on processors that support the 1-setting of the use TPR shadow VM-execution control. */
740	#define VMX_VMCS_CTRL_TPR_THRESHOLD 0x401C
741	/** This field exists only on processors that support the 1-setting of the activate secondary controls VM-execution control. */
742	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS2 0x401E
743	/** @} */
744
745
746	/** @name VMX_VMCS_CTRL_PIN_EXEC_CONTROLS
747	* @{
748	*/
749	/** External interrupts cause VM exits if set; otherwise dispatched through the guest's IDT. */
750	#define VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT RT_BIT(0)
751	/** Non-maskable interrupts cause VM exits if set; otherwise dispatched through the guest's IDT. */
752	#define VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT RT_BIT(3)
753	/* All other bits are reserved and must be set according to MSR IA32_VMX_PROCBASED_CTLS. */
754	/** @} */
755
756	/** @name VMX_VMCS_CTRL_PROC_EXEC_CONTROLS
757	* @{
758	*/
759	/** VM Exit as soon as RFLAGS.IF=1 and no blocking is active. */
760	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT RT_BIT(2)
761	/** Use timestamp counter offset. */
762	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET RT_BIT(3)
763	/** VM Exit when executing the HLT instruction. */
764	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT RT_BIT(7)
765	/** VM Exit when executing the INVLPG instruction. */
766	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT RT_BIT(9)
767	/** VM Exit when executing the MWAIT instruction. */
768	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT RT_BIT(10)
769	/** VM Exit when executing the RDPMC instruction. */
770	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT RT_BIT(11)
771	/** VM Exit when executing the RDTSC instruction. */
772	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT RT_BIT(12)
773	/** VM Exit when executing the MOV to CR3 instruction. */
774	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT RT_BIT(15)
775	/** VM Exit when executing the MOV from CR3 instruction. */
776	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT RT_BIT(16)
777	/** VM Exit on CR8 loads. */
778	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT RT_BIT(19)
779	/** VM Exit on CR8 stores. */
780	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT RT_BIT(20)
781	/** Use TPR shadow. */
782	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW RT_BIT(21)
783	/** VM Exit when executing a MOV DRx instruction. */
784	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT RT_BIT(23)
785	/** VM Exit when executing IO instructions. */
786	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT RT_BIT(24)
787	/** Use IO bitmaps. */
788	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS RT_BIT(25)
789	/** Monitor trap flag. */
790	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG RT_BIT(27)
791	/** Use MSR bitmaps. */
792	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS RT_BIT(28)
793	/** VM Exit when executing the MONITOR instruction. */
794	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT RT_BIT(29)
795	/** VM Exit when executing the PAUSE instruction. */
796	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT RT_BIT(30)
797	/** Determines whether the secondary processor based VM-execution controls are used. */
798	#define VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL RT_BIT(31)
799	/** @} */
800
801	/** @name VMX_VMCS_CTRL_PROC_EXEC_CONTROLS2
802	* @{
803	*/
804	/** Virtualize APIC access. */
805	#define VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC RT_BIT(0)
806	/** EPT supported/enabled. */
807	#define VMX_VMCS_CTRL_PROC_EXEC2_EPT RT_BIT(1)
808	/** VPID supported/enabled. */
809	#define VMX_VMCS_CTRL_PROC_EXEC2_VPID RT_BIT(5)
810	/** VM Exit when executing the WBINVD instruction. */
811	#define VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT RT_BIT(6)
812	/** @} */
813
814
815	/** @name VMX_VMCS_CTRL_ENTRY_CONTROLS
816	* @{
817	*/
818	/** 64 bits guest mode. Must be 0 for CPUs that don't support AMD64. */
819	#define VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE RT_BIT(9)
820	/** In SMM mode after VM-entry. */
821	#define VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM RT_BIT(10)
822	/** Disable dual treatment of SMI and SMM; must be zero for VM-entry outside of SMM. */
823	#define VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON RT_BIT(11)
824	/** @} */
825
826
827	/** @name VMX_VMCS_CTRL_EXIT_CONTROLS
828	* @{
829	*/
830	/** Save debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the 'first' VT-x capable CPUs) */
831	#define VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG RT_BIT(2)
832	/** Return to long mode after a VM-exit. */
833	#define VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64 RT_BIT(9)
834	/** This control determines whether the IA32_PERF_GLOBAL_CTRL MSR is loaded on VM exit. */
835	#define VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_PERF_MSR RT_BIT(12)
836	/** Acknowledge external interrupts with the irq controller if one caused a VM-exit. */
837	#define VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ RT_BIT(15)
838	/** This control determines whether the guest IA32_PAT MSR is saved on VM exit. */
839	#define VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR RT_BIT(18)
840	/** This control determines whether the host IA32_PAT MSR is loaded on VM exit. */
841	#define VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR RT_BIT(19)
842	/** This control determines whether the guest IA32_EFER MSR is saved on VM exit. */
843	#define VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR RT_BIT(20)
844	/** This control determines whether the host IA32_EFER MSR is loaded on VM exit. */
845	#define VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR RT_BIT(21)
846	/** This control determines whether the value of the VMX preemption timer is saved on VM exit. */
847	#define VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER RT_BIT(22)
848	/** @} */
849
850	/** @name VMCS field encoding - 32 Bits read-only fields
851	* @{
852	*/
853	#define VMX_VMCS_RO_VM_INSTR_ERROR 0x4400
854	#define VMX_VMCS_RO_EXIT_REASON 0x4402
855	#define VMX_VMCS_RO_EXIT_INTERRUPTION_INFO 0x4404
856	#define VMX_VMCS_RO_EXIT_INTERRUPTION_ERRCODE 0x4406
857	#define VMX_VMCS_RO_IDT_INFO 0x4408
858	#define VMX_VMCS_RO_IDT_ERRCODE 0x440A
859	#define VMX_VMCS_RO_EXIT_INSTR_LENGTH 0x440C
860	#define VMX_VMCS_RO_EXIT_INSTR_INFO 0x440E
861	/** @} */
862
863	/** @name VMX_VMCS_RO_EXIT_INTERRUPTION_INFO
864	* @{
865	*/
866	#define VMX_EXIT_INTERRUPTION_INFO_VECTOR(a) (a & 0xff)
867	#define VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT 8
868	#define VMX_EXIT_INTERRUPTION_INFO_TYPE(a) ((a >> VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT) & 7)
869	#define VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID RT_BIT(11)
870	#define VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID(a) (a & VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID)
871	#define VMX_EXIT_INTERRUPTION_INFO_NMI_UNBLOCK(a) (a & RT_BIT(12))
872	#define VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT 31
873	#define VMX_EXIT_INTERRUPTION_INFO_VALID(a) (a & RT_BIT(31))
874	/** Construct an irq event injection value from the exit interruption info value (same except that bit 12 is reserved). */
875	#define VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(a) (a & ~RT_BIT(12))
876	/** @} */
877
878	/** @name VMX_VMCS_RO_EXIT_INTERRUPTION_INFO_TYPE
879	* @{
880	*/
881	#define VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT 0
882	#define VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI 2
883	#define VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT 3
884	#define VMX_EXIT_INTERRUPTION_INFO_TYPE_SW 4 /*< int xx /
885	#define VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT 6
886	/** @} */
887
888
889	/** @name VMCS field encoding - 32 Bits guest state fields
890	* @{
891	*/
892	#define VMX_VMCS_GUEST_ES_LIMIT 0x4800
893	#define VMX_VMCS_GUEST_CS_LIMIT 0x4802
894	#define VMX_VMCS_GUEST_SS_LIMIT 0x4804
895	#define VMX_VMCS_GUEST_DS_LIMIT 0x4806
896	#define VMX_VMCS_GUEST_FS_LIMIT 0x4808
897	#define VMX_VMCS_GUEST_GS_LIMIT 0x480A
898	#define VMX_VMCS_GUEST_LDTR_LIMIT 0x480C
899	#define VMX_VMCS_GUEST_TR_LIMIT 0x480E
900	#define VMX_VMCS_GUEST_GDTR_LIMIT 0x4810
901	#define VMX_VMCS_GUEST_IDTR_LIMIT 0x4812
902	#define VMX_VMCS_GUEST_ES_ACCESS_RIGHTS 0x4814
903	#define VMX_VMCS_GUEST_CS_ACCESS_RIGHTS 0x4816
904	#define VMX_VMCS_GUEST_SS_ACCESS_RIGHTS 0x4818
905	#define VMX_VMCS_GUEST_DS_ACCESS_RIGHTS 0x481A
906	#define VMX_VMCS_GUEST_FS_ACCESS_RIGHTS 0x481C
907	#define VMX_VMCS_GUEST_GS_ACCESS_RIGHTS 0x481E
908	#define VMX_VMCS_GUEST_LDTR_ACCESS_RIGHTS 0x4820
909	#define VMX_VMCS_GUEST_TR_ACCESS_RIGHTS 0x4822
910	#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE 0x4824
911	#define VMX_VMCS_GUEST_ACTIVITY_STATE 0x4826
912	#define VMX_VMCS_GUEST_SYSENTER_CS 0x482A /*< MSR IA32_SYSENTER_CS /
913	#define VMX_VMCS_GUEST_PREEMPTION_TIMER_VALUE 0x482E
914	/** @} */
915
916
917	/** @name VMX_VMCS_GUEST_ACTIVITY_STATE
918	* @{
919	*/
920	/** The logical processor is active. */
921	#define VMX_CMS_GUEST_ACTIVITY_ACTIVE 0x0
922	/** The logical processor is inactive, because executed a HLT instruction. */
923	#define VMX_CMS_GUEST_ACTIVITY_HLT 0x1
924	/** The logical processor is inactive, because of a triple fault or other serious error. */
925	#define VMX_CMS_GUEST_ACTIVITY_SHUTDOWN 0x2
926	/** The logical processor is inactive, because it's waiting for a startup-IPI */
927	#define VMX_CMS_GUEST_ACTIVITY_SIPI_WAIT 0x3
928	/** @} */
929
930
931	/** @name VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE
932	* @{
933	*/
934	#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_STI RT_BIT(0)
935	#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_MOVSS RT_BIT(1)
936	#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_SMI RT_BIT(2)
937	#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_NMI RT_BIT(3)
938	/** @} */
939
940
941	/** @name VMCS field encoding - 32 Bits host state fields
942	* @{
943	*/
944	#define VMX_VMCS_HOST_SYSENTER_CS 0x4C00
945	/** @} */
946
947	/** @name Natural width control fields
948	* @{
949	*/
950	#define VMX_VMCS_CTRL_CR0_MASK 0x6000
951	#define VMX_VMCS_CTRL_CR4_MASK 0x6002
952	#define VMX_VMCS_CTRL_CR0_READ_SHADOW 0x6004
953	#define VMX_VMCS_CTRL_CR4_READ_SHADOW 0x6006
954	#define VMX_VMCS_CTRL_CR3_TARGET_VAL0 0x6008
955	#define VMX_VMCS_CTRL_CR3_TARGET_VAL1 0x600A
956	#define VMX_VMCS_CTRL_CR3_TARGET_VAL2 0x600C
957	#define VMX_VMCS_CTRL_CR3_TARGET_VAL31 0x600E
958	/** @} */
959
960
961	/** @name Natural width read-only data fields
962	* @{
963	*/
964	#define VMX_VMCS_RO_EXIT_QUALIFICATION 0x6400
965	#define VMX_VMCS_RO_IO_RCX 0x6402
966	#define VMX_VMCS_RO_IO_RSX 0x6404
967	#define VMX_VMCS_RO_IO_RDI 0x6406
968	#define VMX_VMCS_RO_IO_RIP 0x6408
969	#define VMX_VMCS_EXIT_GUEST_LINEAR_ADDR 0x640A
970	/** @} */
971
972
973	/** @name VMX_VMCS_RO_EXIT_QUALIFICATION
974	* @{
975	*/
976	/** 0-2: Debug register number */
977	#define VMX_EXIT_QUALIFICATION_DRX_REGISTER(a) (a & 7)
978	/** 3: Reserved; cleared to 0. */
979	#define VMX_EXIT_QUALIFICATION_DRX_RES1(a) ((a >> 3) & 1)
980	/** 4: Direction of move (0 = write, 1 = read) */
981	#define VMX_EXIT_QUALIFICATION_DRX_DIRECTION(a) ((a >> 4) & 1)
982	/** 5-7: Reserved; cleared to 0. */
983	#define VMX_EXIT_QUALIFICATION_DRX_RES2(a) ((a >> 5) & 7)
984	/** 8-11: General purpose register number. */
985	#define VMX_EXIT_QUALIFICATION_DRX_GENREG(a) ((a >> 8) & 0xF)
986	/** Rest: reserved. */
987	/** @} */
988
989	/** @name VMX_EXIT_QUALIFICATION_DRX_DIRECTION values
990	* @{
991	*/
992	#define VMX_EXIT_QUALIFICATION_DRX_DIRECTION_WRITE 0
993	#define VMX_EXIT_QUALIFICATION_DRX_DIRECTION_READ 1
994	/** @} */
995
996
997
998	/** @name CRx accesses
999	* @{
1000	*/
1001	/** 0-3: Control register number (0 for CLTS & LMSW) */
1002	#define VMX_EXIT_QUALIFICATION_CRX_REGISTER(a) (a & 0xF)
1003	/** 4-5: Access type. */
1004	#define VMX_EXIT_QUALIFICATION_CRX_ACCESS(a) ((a >> 4) & 3)
1005	/** 6: LMSW operand type */
1006	#define VMX_EXIT_QUALIFICATION_CRX_LMSW_OP(a) ((a >> 6) & 1)
1007	/** 7: Reserved; cleared to 0. */
1008	#define VMX_EXIT_QUALIFICATION_CRX_RES1(a) ((a >> 7) & 1)
1009	/** 8-11: General purpose register number (0 for CLTS & LMSW). */
1010	#define VMX_EXIT_QUALIFICATION_CRX_GENREG(a) ((a >> 8) & 0xF)
1011	/** 12-15: Reserved; cleared to 0. */
1012	#define VMX_EXIT_QUALIFICATION_CRX_RES2(a) ((a >> 12) & 0xF)
1013	/** 16-31: LMSW source data (else 0). */
1014	#define VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(a) ((a >> 16) & 0xFFFF)
1015	/** Rest: reserved. */
1016	/** @} */
1017
1018	/** @name VMX_EXIT_QUALIFICATION_CRX_ACCESS
1019	* @{
1020	*/
1021	#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_WRITE 0
1022	#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_READ 1
1023	#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_CLTS 2
1024	#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_LMSW 3
1025	/** @} */
1026
1027
1028
1029	/** @name VMX_EXIT_PORT_IO
1030	* @{
1031	*/
1032	/** 0-2: IO operation width. */
1033	#define VMX_EXIT_QUALIFICATION_IO_WIDTH(a) (a & 7)
1034	/** 3: IO operation direction. */
1035	#define VMX_EXIT_QUALIFICATION_IO_DIRECTION(a) ((a >> 3) & 1)
1036	/** 4: String IO operation. */
1037	#define VMX_EXIT_QUALIFICATION_IO_STRING(a) ((a >> 4) & 1)
1038	/** 5: Repeated IO operation. */
1039	#define VMX_EXIT_QUALIFICATION_IO_REP(a) ((a >> 5) & 1)
1040	/** 6: Operand encoding. */
1041	#define VMX_EXIT_QUALIFICATION_IO_ENCODING(a) ((a >> 6) & 1)
1042	/** 16-31: IO Port (0-0xffff). */
1043	#define VMX_EXIT_QUALIFICATION_IO_PORT(a) ((a >> 16) & 0xffff)
1044	/* Rest reserved. */
1045	/** @} */
1046
1047	/** @name VMX_EXIT_QUALIFICATION_IO_DIRECTION
1048	* @{
1049	*/
1050	#define VMX_EXIT_QUALIFICATION_IO_DIRECTION_OUT 0
1051	#define VMX_EXIT_QUALIFICATION_IO_DIRECTION_IN 1
1052	/** @} */
1053
1054
1055	/** @name VMX_EXIT_QUALIFICATION_IO_ENCODING
1056	* @{
1057	*/
1058	#define VMX_EXIT_QUALIFICATION_IO_ENCODING_DX 0
1059	#define VMX_EXIT_QUALIFICATION_IO_ENCODING_IMM 1
1060	/** @} */
1061
1062	/** @} */
1063
1064	/** @name VMCS field encoding - Natural width guest state fields
1065	* @{
1066	*/
1067	#define VMX_VMCS_GUEST_CR0 0x6800
1068	#define VMX_VMCS_GUEST_CR3 0x6802
1069	#define VMX_VMCS_GUEST_CR4 0x6804
1070	#define VMX_VMCS_GUEST_ES_BASE 0x6806
1071	#define VMX_VMCS_GUEST_CS_BASE 0x6808
1072	#define VMX_VMCS_GUEST_SS_BASE 0x680A
1073	#define VMX_VMCS_GUEST_DS_BASE 0x680C
1074	#define VMX_VMCS_GUEST_FS_BASE 0x680E
1075	#define VMX_VMCS_GUEST_GS_BASE 0x6810
1076	#define VMX_VMCS_GUEST_LDTR_BASE 0x6812
1077	#define VMX_VMCS_GUEST_TR_BASE 0x6814
1078	#define VMX_VMCS_GUEST_GDTR_BASE 0x6816
1079	#define VMX_VMCS_GUEST_IDTR_BASE 0x6818
1080	#define VMX_VMCS_GUEST_DR7 0x681A
1081	#define VMX_VMCS_GUEST_RSP 0x681C
1082	#define VMX_VMCS_GUEST_RIP 0x681E
1083	#define VMX_VMCS_GUEST_RFLAGS 0x6820
1084	#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS 0x6822
1085	#define VMX_VMCS_GUEST_SYSENTER_ESP 0x6824 /*< MSR IA32_SYSENTER_ESP /
1086	#define VMX_VMCS_GUEST_SYSENTER_EIP 0x6826 /*< MSR IA32_SYSENTER_EIP /
1087	/** @} */
1088
1089
1090	/** @name VMX_VMCS_GUEST_DEBUG_EXCEPTIONS
1091	* @{
1092	*/
1093	/** Hardware breakpoint 0 was met. */
1094	#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B0 RT_BIT(0)
1095	/** Hardware breakpoint 1 was met. */
1096	#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B1 RT_BIT(1)
1097	/** Hardware breakpoint 2 was met. */
1098	#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B2 RT_BIT(2)
1099	/** Hardware breakpoint 3 was met. */
1100	#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B3 RT_BIT(3)
1101	/** At least one data or IO breakpoint was hit. */
1102	#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_BREAKPOINT_ENABLED RT_BIT(12)
1103	/** A debug exception would have been triggered by single-step execution mode. */
1104	#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_BS RT_BIT(14)
1105	/** Bits 4-11, 13 and 15-63 are reserved. */
1106
1107	/** @} */
1108
1109	/** @name VMCS field encoding - Natural width host state fields
1110	* @{
1111	*/
1112	#define VMX_VMCS_HOST_CR0 0x6C00
1113	#define VMX_VMCS_HOST_CR3 0x6C02
1114	#define VMX_VMCS_HOST_CR4 0x6C04
1115	#define VMX_VMCS_HOST_FS_BASE 0x6C06
1116	#define VMX_VMCS_HOST_GS_BASE 0x6C08
1117	#define VMX_VMCS_HOST_TR_BASE 0x6C0A
1118	#define VMX_VMCS_HOST_GDTR_BASE 0x6C0C
1119	#define VMX_VMCS_HOST_IDTR_BASE 0x6C0E
1120	#define VMX_VMCS_HOST_SYSENTER_ESP 0x6C10
1121	#define VMX_VMCS_HOST_SYSENTER_EIP 0x6C12
1122	#define VMX_VMCS_HOST_RSP 0x6C14
1123	#define VMX_VMCS_HOST_RIP 0x6C16
1124	/** @} */
1125
1126	/** @} */
1127
1128
1129	#if RT_INLINE_ASM_GNU_STYLE
1130	# define __STR(x) #x
1131	# define STR(x) __STR(x)
1132	#endif
1133
1134
1135	/** @defgroup grp_vmx_asm vmx assembly helpers
1136	* @ingroup grp_vmx
1137	* @{
1138	*/
1139
1140	/**
1141	* Executes VMXON
1142	*
1143	* @returns VBox status code
1144	* @param pVMXOn Physical address of VMXON structure
1145	*/
1146	#if RT_INLINE_ASM_EXTERNAL \|\| HC_ARCH_BITS == 64
1147	DECLASM(int) VMXEnable(RTHCPHYS pVMXOn);
1148	#else
1149	DECLINLINE(int) VMXEnable(RTHCPHYS pVMXOn)
1150	{
1151	int rc = VINF_SUCCESS;
1152	# if RT_INLINE_ASM_GNU_STYLE
1153	__asm__ __volatile__ (
1154	"push %3 \n\t"
1155	"push %2 \n\t"
1156	".byte 0xF3, 0x0F, 0xC7, 0x34, 0x24 # VMXON [esp] \n\t"
1157	"ja 2f \n\t"
1158	"je 1f \n\t"
1159	"movl $"STR(VERR_VMX_INVALID_VMXON_PTR)", %0 \n\t"
1160	"jmp 2f \n\t"
1161	"1: \n\t"
1162	"movl $"STR(VERR_VMX_GENERIC)", %0 \n\t"
1163	"2: \n\t"
1164	"add $8, %%esp \n\t"
1165	:"=rm"(rc)
1166	:"0"(VINF_SUCCESS),
1167	"ir"((uint32_t)pVMXOn), /* don't allow direct memory reference here, */
1168	"ir"((uint32_t)(pVMXOn >> 32)) /* this would not work with -fomit-frame-pointer */
1169	:"memory"
1170	);
1171	# else
1172	__asm
1173	{
1174	push dword ptr [pVMXOn+4]
1175	push dword ptr [pVMXOn]
1176	_emit 0xF3
1177	_emit 0x0F
1178	_emit 0xC7
1179	_emit 0x34
1180	_emit 0x24 /* VMXON [esp] */
1181	jnc vmxon_good
1182	mov dword ptr [rc], VERR_VMX_INVALID_VMXON_PTR
1183	jmp the_end
1184
1185	vmxon_good:
1186	jnz the_end
1187	mov dword ptr [rc], VERR_VMX_GENERIC
1188	the_end:
1189	add esp, 8
1190	}
1191	# endif
1192	return rc;
1193	}
1194	#endif
1195
1196
1197	/**
1198	* Executes VMXOFF
1199	*/
1200	#if RT_INLINE_ASM_EXTERNAL \|\| HC_ARCH_BITS == 64
1201	DECLASM(void) VMXDisable(void);
1202	#else
1203	DECLINLINE(void) VMXDisable(void)
1204	{
1205	# if RT_INLINE_ASM_GNU_STYLE
1206	__asm__ __volatile__ (
1207	".byte 0x0F, 0x01, 0xC4 # VMXOFF \n\t"
1208	);
1209	# else
1210	__asm
1211	{
1212	_emit 0x0F
1213	_emit 0x01
1214	_emit 0xC4 /* VMXOFF */
1215	}
1216	# endif
1217	}
1218	#endif
1219
1220
1221	/**
1222	* Executes VMCLEAR
1223	*
1224	* @returns VBox status code
1225	* @param pVMCS Physical address of VM control structure
1226	*/
1227	#if RT_INLINE_ASM_EXTERNAL \|\| HC_ARCH_BITS == 64
1228	DECLASM(int) VMXClearVMCS(RTHCPHYS pVMCS);
1229	#else
1230	DECLINLINE(int) VMXClearVMCS(RTHCPHYS pVMCS)
1231	{
1232	int rc = VINF_SUCCESS;
1233	# if RT_INLINE_ASM_GNU_STYLE
1234	__asm__ __volatile__ (
1235	"push %3 \n\t"
1236	"push %2 \n\t"
1237	".byte 0x66, 0x0F, 0xC7, 0x34, 0x24 # VMCLEAR [esp] \n\t"
1238	"jnc 1f \n\t"
1239	"movl $"STR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
1240	"1: \n\t"
1241	"add $8, %%esp \n\t"
1242	:"=rm"(rc)
1243	:"0"(VINF_SUCCESS),
1244	"ir"((uint32_t)pVMCS), /* don't allow direct memory reference here, */
1245	"ir"((uint32_t)(pVMCS >> 32)) /* this would not work with -fomit-frame-pointer */
1246	:"memory"
1247	);
1248	# else
1249	__asm
1250	{
1251	push dword ptr [pVMCS+4]
1252	push dword ptr [pVMCS]
1253	_emit 0x66
1254	_emit 0x0F
1255	_emit 0xC7
1256	_emit 0x34
1257	_emit 0x24 /* VMCLEAR [esp] */
1258	jnc success
1259	mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
1260	success:
1261	add esp, 8
1262	}
1263	# endif
1264	return rc;
1265	}
1266	#endif
1267
1268
1269	/**
1270	* Executes VMPTRLD
1271	*
1272	* @returns VBox status code
1273	* @param pVMCS Physical address of VMCS structure
1274	*/
1275	#if RT_INLINE_ASM_EXTERNAL \|\| HC_ARCH_BITS == 64
1276	DECLASM(int) VMXActivateVMCS(RTHCPHYS pVMCS);
1277	#else
1278	DECLINLINE(int) VMXActivateVMCS(RTHCPHYS pVMCS)
1279	{
1280	int rc = VINF_SUCCESS;
1281	# if RT_INLINE_ASM_GNU_STYLE
1282	__asm__ __volatile__ (
1283	"push %3 \n\t"
1284	"push %2 \n\t"
1285	".byte 0x0F, 0xC7, 0x34, 0x24 # VMPTRLD [esp] \n\t"
1286	"jnc 1f \n\t"
1287	"movl $"STR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
1288	"1: \n\t"
1289	"add $8, %%esp \n\t"
1290	:"=rm"(rc)
1291	:"0"(VINF_SUCCESS),
1292	"ir"((uint32_t)pVMCS), /* don't allow direct memory reference here, */
1293	"ir"((uint32_t)(pVMCS >> 32)) /* this will not work with -fomit-frame-pointer */
1294	);
1295	# else
1296	__asm
1297	{
1298	push dword ptr [pVMCS+4]
1299	push dword ptr [pVMCS]
1300	_emit 0x0F
1301	_emit 0xC7
1302	_emit 0x34
1303	_emit 0x24 /* VMPTRLD [esp] */
1304	jnc success
1305	mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
1306
1307	success:
1308	add esp, 8
1309	}
1310	# endif
1311	return rc;
1312	}
1313	#endif
1314
1315	/**
1316	* Executes VMPTRST
1317	*
1318	* @returns VBox status code
1319	* @param pVMCS Address that will receive the current pointer
1320	*/
1321	DECLASM(int) VMXGetActivateVMCS(RTHCPHYS *pVMCS);
1322
1323	/**
1324	* Executes VMWRITE
1325	*
1326	* @returns VBox status code
1327	* @param idxField VMCS index
1328	* @param u64Val 16, 32 or 64 bits value
1329	*/
1330	DECLASM(int) VMXWriteVMCS64(uint32_t idxField, uint64_t u64Val);
1331
1332	/**
1333	* Executes VMWRITE
1334	*
1335	* @returns VBox status code
1336	* @param idxField VMCS index
1337	* @param u32Val 32 bits value
1338	*/
1339	#if RT_INLINE_ASM_EXTERNAL \|\| HC_ARCH_BITS == 64
1340	DECLASM(int) VMXWriteVMCS32(uint32_t idxField, uint32_t u32Val);
1341	#else
1342	DECLINLINE(int) VMXWriteVMCS32(uint32_t idxField, uint32_t u32Val)
1343	{
1344	int rc = VINF_SUCCESS;
1345	# if RT_INLINE_ASM_GNU_STYLE
1346	__asm__ __volatile__ (
1347	".byte 0x0F, 0x79, 0xC2 # VMWRITE eax, edx \n\t"
1348	"ja 2f \n\t"
1349	"je 1f \n\t"
1350	"movl $"STR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
1351	"jmp 2f \n\t"
1352	"1: \n\t"
1353	"movl $"STR(VERR_VMX_INVALID_VMCS_FIELD)", %0 \n\t"
1354	"2: \n\t"
1355	:"=rm"(rc)
1356	:"0"(VINF_SUCCESS),
1357	"a"(idxField),
1358	"d"(u32Val)
1359	);
1360	# else
1361	__asm
1362	{
1363	push dword ptr [u32Val]
1364	mov eax, [idxField]
1365	_emit 0x0F
1366	_emit 0x79
1367	_emit 0x04
1368	_emit 0x24 /* VMWRITE eax, [esp] */
1369	jnc valid_vmcs
1370	mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
1371	jmp the_end
1372
1373	valid_vmcs:
1374	jnz the_end
1375	mov dword ptr [rc], VERR_VMX_INVALID_VMCS_FIELD
1376	the_end:
1377	add esp, 4
1378	}
1379	# endif
1380	return rc;
1381	}
1382	#endif
1383
1384	#if HC_ARCH_BITS == 64
1385	#define VMXWriteVMCS VMXWriteVMCS64
1386	#else
1387	#define VMXWriteVMCS VMXWriteVMCS32
1388	#endif /* HC_ARCH_BITS == 64 */
1389
1390
1391	/**
1392	* Executes VMREAD
1393	*
1394	* @returns VBox status code
1395	* @param idxField VMCS index
1396	* @param pData Ptr to store VM field value
1397	*/
1398	DECLASM(int) VMXReadVMCS64(uint32_t idxField, uint64_t *pData);
1399
1400	/**
1401	* Executes VMREAD
1402	*
1403	* @returns VBox status code
1404	* @param idxField VMCS index
1405	* @param pData Ptr to store VM field value
1406	*/
1407	#if RT_INLINE_ASM_EXTERNAL \|\| HC_ARCH_BITS == 64
1408	DECLASM(int) VMXReadVMCS32(uint32_t idxField, uint32_t *pData);
1409	#else
1410	DECLINLINE(int) VMXReadVMCS32(uint32_t idxField, uint32_t *pData)
1411	{
1412	int rc = VINF_SUCCESS;
1413	# if RT_INLINE_ASM_GNU_STYLE
1414	__asm__ __volatile__ (
1415	"movl $"STR(VINF_SUCCESS)", %0 \n\t"
1416	".byte 0x0F, 0x78, 0xc2 # VMREAD eax, edx \n\t"
1417	"ja 2f \n\t"
1418	"je 1f \n\t"
1419	"movl $"STR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
1420	"jmp 2f \n\t"
1421	"1: \n\t"
1422	"movl $"STR(VERR_VMX_INVALID_VMCS_FIELD)", %0 \n\t"
1423	"2: \n\t"
1424	:"=&r"(rc),
1425	"=d"(*pData)
1426	:"a"(idxField),
1427	"d"(0)
1428	);
1429	# else
1430	__asm
1431	{
1432	sub esp, 4
1433	mov dword ptr [esp], 0
1434	mov eax, [idxField]
1435	_emit 0x0F
1436	_emit 0x78
1437	_emit 0x04
1438	_emit 0x24 /* VMREAD eax, [esp] */
1439	mov edx, pData
1440	pop dword ptr [edx]
1441	jnc valid_vmcs
1442	mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
1443	jmp the_end
1444
1445	valid_vmcs:
1446	jnz the_end
1447	mov dword ptr [rc], VERR_VMX_INVALID_VMCS_FIELD
1448	the_end:
1449	}
1450	# endif
1451	return rc;
1452	}
1453	#endif
1454
1455	#if HC_ARCH_BITS == 64
1456	# define VMXReadVMCS VMXReadVMCS64
1457	#else
1458	# define VMXReadVMCS VMXReadVMCS32
1459	#endif /* HC_ARCH_BITS == 64 */
1460
1461	/**
1462	* Gets the last instruction error value from the current VMCS
1463	*
1464	* @returns error value
1465	*/
1466	DECLINLINE(uint32_t) VMXGetLastError(void)
1467	{
1468	#if HC_ARCH_BITS == 64
1469	uint64_t uLastError = 0;
1470	int rc = VMXReadVMCS(VMX_VMCS_RO_VM_INSTR_ERROR, &uLastError);
1471	AssertRC(rc);
1472	return (uint32_t)uLastError;
1473
1474	#else /* 32-bit host: */
1475	uint32_t uLastError = 0;
1476	int rc = VMXReadVMCS32(VMX_VMCS_RO_VM_INSTR_ERROR, &uLastError);
1477	AssertRC(rc);
1478	return uLastError;
1479	#endif
1480	}
1481
1482	#ifdef IN_RING0
1483	VMMR0DECL(int) VMXR0InvalidatePage(PVM pVM, RTGCPTR GCVirt);
1484	VMMR0DECL(int) VMXR0InvalidatePhysPage(PVM pVM, RTGCPHYS GCPhys);
1485	#endif /* IN_RING0 */
1486
1487	/** @} */
1488
1489	#endif
1490

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source: vbox/trunk/include/VBox/hwacc_vmx.h@ 13043

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