hwacc_vmx.h@ 15743

Last change on this file since 15743 was 15730, checked in by vboxsync, 16 years ago
Added MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 60.4 KB

Line
1	/** @file
2	* HWACCM - VMX Structures and Definitions.
3	*/
4
5	/*
6	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
7	*
8	* This file is part of VirtualBox Open Source Edition (OSE), as
9	* available from http://www.virtualbox.org. This file is free software;
10	* you can redistribute it and/or modify it under the terms of the GNU
11	* General Public License (GPL) as published by the Free Software
12	* Foundation, in version 2 as it comes in the "COPYING" file of the
13	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15	*
16	* The contents of this file may alternatively be used under the terms
17	* of the Common Development and Distribution License Version 1.0
18	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19	* VirtualBox OSE distribution, in which case the provisions of the
20	* CDDL are applicable instead of those of the GPL.
21	*
22	* You may elect to license modified versions of this file under the
23	* terms and conditions of either the GPL or the CDDL or both.
24	*
25	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
26	* Clara, CA 95054 USA or visit http://www.sun.com if you need
27	* additional information or have any questions.
28	*/
29
30	#ifndef ___VBox_vmx_h
31	#define ___VBox_vmx_h
32
33	#include <VBox/types.h>
34	#include <VBox/err.h>
35	#include <iprt/assert.h>
36	#include <iprt/asm.h>
37	#include <VBox/x86.h>
38
39	/** @defgroup grp_vmx vmx Types and Definitions
40	* @ingroup grp_hwaccm
41	* @{
42	*/
43
44	/** @name VMX EPT paging structures
45	* @{
46	*/
47
48	/**
49	* Number of page table entries in the EPT. (PDPTE/PDE/PTE)
50	*/
51	#define EPT_PG_ENTRIES X86_PG_PAE_ENTRIES
52
53	/**
54	* EPT Page Directory Pointer Entry. Bit view.
55	* @todo uint64_t isn't safe for bitfields (gcc pedantic warnings, and IIRC,
56	* this did cause trouble with one compiler/version).
57	*/
58	#pragma pack(1)
59	typedef struct EPTPML4EBITS
60	{
61	/** Present bit. */
62	uint64_t u1Present : 1;
63	/** Writable bit. */
64	uint64_t u1Write : 1;
65	/** Executable bit. */
66	uint64_t u1Execute : 1;
67	/** Reserved (must be 0). */
68	uint64_t u5Reserved : 5;
69	/** Available for software. */
70	uint64_t u4Available : 4;
71	/** Physical address of the next level (PD). Restricted by maximum physical address width of the cpu. */
72	uint64_t u40PhysAddr : 40;
73	/** Availabe for software. */
74	uint64_t u12Available : 12;
75	} EPTPML4EBITS;
76	#pragma pack()
77	AssertCompileSize(EPTPML4EBITS, 8);
78
79	/** Bits 12-51 - - EPT - Physical Page number of the next level. */
80	#define EPT_PML4E_PG_MASK X86_PML4E_PG_MASK_FULL
81	/** The page shift to get the PML4 index. */
82	#define EPT_PML4_SHIFT X86_PML4_SHIFT
83	/** The PML4 index mask (apply to a shifted page address). */
84	#define EPT_PML4_MASK X86_PML4_MASK
85
86	/**
87	* EPT PML4E.
88	*/
89	#pragma pack(1)
90	typedef union EPTPML4E
91	{
92	/** Normal view. */
93	EPTPML4EBITS n;
94	/** Unsigned integer view. */
95	X86PGPAEUINT u;
96	/** 64 bit unsigned integer view. */
97	uint64_t au64[1];
98	/** 32 bit unsigned integer view. */
99	uint32_t au32[2];
100	} EPTPML4E;
101	#pragma pack()
102	/** Pointer to a PML4 table entry. */
103	typedef EPTPML4E *PEPTPML4E;
104	/** Pointer to a const PML4 table entry. */
105	typedef const EPTPML4E *PCEPTPML4E;
106	AssertCompileSize(EPTPML4E, 8);
107
108	/**
109	* EPT PML4 Table.
110	*/
111	#pragma pack(1)
112	typedef struct EPTPML4
113	{
114	EPTPML4E a[EPT_PG_ENTRIES];
115	} EPTPML4;
116	#pragma pack()
117	/** Pointer to an EPT PML4 Table. */
118	typedef EPTPML4 *PEPTPML4;
119	/** Pointer to a const EPT PML4 Table. */
120	typedef const EPTPML4 *PCEPTPML4;
121
122	/**
123	* EPT Page Directory Pointer Entry. Bit view.
124	*/
125	#pragma pack(1)
126	typedef struct EPTPDPTEBITS
127	{
128	/** Present bit. */
129	uint64_t u1Present : 1;
130	/** Writable bit. */
131	uint64_t u1Write : 1;
132	/** Executable bit. */
133	uint64_t u1Execute : 1;
134	/** Reserved (must be 0). */
135	uint64_t u5Reserved : 5;
136	/** Available for software. */
137	uint64_t u4Available : 4;
138	/** Physical address of the next level (PD). Restricted by maximum physical address width of the cpu. */
139	uint64_t u40PhysAddr : 40;
140	/** Availabe for software. */
141	uint64_t u12Available : 12;
142	} EPTPDPTEBITS;
143	#pragma pack()
144	AssertCompileSize(EPTPDPTEBITS, 8);
145
146	/** Bits 12-51 - - EPT - Physical Page number of the next level. */
147	#define EPT_PDPTE_PG_MASK X86_PDPE_PG_MASK_FULL
148	/** The page shift to get the PDPT index. */
149	#define EPT_PDPT_SHIFT X86_PDPT_SHIFT
150	/** The PDPT index mask (apply to a shifted page address). */
151	#define EPT_PDPT_MASK X86_PDPT_MASK_AMD64
152
153	/**
154	* EPT Page Directory Pointer.
155	*/
156	#pragma pack(1)
157	typedef union EPTPDPTE
158	{
159	/** Normal view. */
160	EPTPDPTEBITS n;
161	/** Unsigned integer view. */
162	X86PGPAEUINT u;
163	/** 64 bit unsigned integer view. */
164	uint64_t au64[1];
165	/** 32 bit unsigned integer view. */
166	uint32_t au32[2];
167	} EPTPDPTE;
168	#pragma pack()
169	/** Pointer to an EPT Page Directory Pointer Entry. */
170	typedef EPTPDPTE *PEPTPDPTE;
171	/** Pointer to a const EPT Page Directory Pointer Entry. */
172	typedef const EPTPDPTE *PCEPTPDPTE;
173	AssertCompileSize(EPTPDPTE, 8);
174
175	/**
176	* EPT Page Directory Pointer Table.
177	*/
178	#pragma pack(1)
179	typedef struct EPTPDPT
180	{
181	EPTPDPTE a[EPT_PG_ENTRIES];
182	} EPTPDPT;
183	#pragma pack()
184	/** Pointer to an EPT Page Directory Pointer Table. */
185	typedef EPTPDPT *PEPTPDPT;
186	/** Pointer to a const EPT Page Directory Pointer Table. */
187	typedef const EPTPDPT *PCEPTPDPT;
188
189
190	/**
191	* EPT Page Directory Table Entry. Bit view.
192	*/
193	#pragma pack(1)
194	typedef struct EPTPDEBITS
195	{
196	/** Present bit. */
197	uint64_t u1Present : 1;
198	/** Writable bit. */
199	uint64_t u1Write : 1;
200	/** Executable bit. */
201	uint64_t u1Execute : 1;
202	/** Reserved (must be 0). */
203	uint64_t u4Reserved : 4;
204	/** Big page (must be 0 here). */
205	uint64_t u1Big : 1;
206	/** Available for software. */
207	uint64_t u4Available : 4;
208	/** Physical address of page table. Restricted by maximum physical address width of the cpu. */
209	uint64_t u40PhysAddr : 40;
210	/** Availabe for software. */
211	uint64_t u12Available : 12;
212	} EPTPDEBITS;
213	#pragma pack()
214	AssertCompileSize(EPTPDEBITS, 8);
215
216	/** Bits 12-51 - - EPT - Physical Page number of the next level. */
217	#define EPT_PDE_PG_MASK X86_PDE_PAE_PG_MASK_FULL
218	/** The page shift to get the PD index. */
219	#define EPT_PD_SHIFT X86_PD_PAE_SHIFT
220	/** The PD index mask (apply to a shifted page address). */
221	#define EPT_PD_MASK X86_PD_PAE_MASK
222
223	/**
224	* EPT 2MB Page Directory Table Entry. Bit view.
225	*/
226	#pragma pack(1)
227	typedef struct EPTPDE2MBITS
228	{
229	/** Present bit. */
230	uint64_t u1Present : 1;
231	/** Writable bit. */
232	uint64_t u1Write : 1;
233	/** Executable bit. */
234	uint64_t u1Execute : 1;
235	/** EPT Table Memory Type. MBZ for non-leaf nodes. */
236	uint64_t u3EMT : 3;
237	/** Ignore PAT memory type */
238	uint64_t u1IgnorePAT : 1;
239	/** Big page (must be 1 here). */
240	uint64_t u1Size : 1;
241	/** Available for software. */
242	uint64_t u4Available : 4;
243	/** Reserved (must be 0). */
244	uint64_t u9Reserved : 9;
245	/** Physical address of the 2MB page. Restricted by maximum physical address width of the cpu. */
246	uint64_t u31PhysAddr : 31;
247	/** Availabe for software. */
248	uint64_t u12Available : 12;
249	} EPTPDE2MBITS;
250	#pragma pack()
251	AssertCompileSize(EPTPDE2MBITS, 8);
252
253	/** Bits 21-51 - - EPT - Physical Page number of the next level. */
254	#define EPT_PDE2M_PG_MASK ( 0x000fffffffe00000ULL )
255
256	/**
257	* EPT Page Directory Table Entry.
258	*/
259	#pragma pack(1)
260	typedef union EPTPDE
261	{
262	/** Normal view. */
263	EPTPDEBITS n;
264	/** 2MB view (big). */
265	EPTPDE2MBITS b;
266	/** Unsigned integer view. */
267	X86PGPAEUINT u;
268	/** 64 bit unsigned integer view. */
269	uint64_t au64[1];
270	/** 32 bit unsigned integer view. */
271	uint32_t au32[2];
272	} EPTPDE;
273	#pragma pack()
274	/** Pointer to an EPT Page Directory Table Entry. */
275	typedef EPTPDE *PEPTPDE;
276	/** Pointer to a const EPT Page Directory Table Entry. */
277	typedef const EPTPDE *PCEPTPDE;
278	AssertCompileSize(EPTPDE, 8);
279
280	/**
281	* EPT Page Directory Table.
282	*/
283	#pragma pack(1)
284	typedef struct EPTPD
285	{
286	EPTPDE a[EPT_PG_ENTRIES];
287	} EPTPD;
288	#pragma pack()
289	/** Pointer to an EPT Page Directory Table. */
290	typedef EPTPD *PEPTPD;
291	/** Pointer to a const EPT Page Directory Table. */
292	typedef const EPTPD *PCEPTPD;
293
294
295	/**
296	* EPT Page Table Entry. Bit view.
297	*/
298	#pragma pack(1)
299	typedef struct EPTPTEBITS
300	{
301	/** Present bit. */
302	uint64_t u1Present : 1;
303	/** Writable bit. */
304	uint64_t u1Write : 1;
305	/** Executable bit. */
306	uint64_t u1Execute : 1;
307	/** EPT Table Memory Type. MBZ for non-leaf nodes. */
308	uint64_t u3EMT : 3;
309	/** Ignore PAT memory type */
310	uint64_t u1IgnorePAT : 1;
311	/** Available for software. */
312	uint64_t u5Available : 5;
313	/** Physical address of page. Restricted by maximum physical address width of the cpu. */
314	uint64_t u40PhysAddr : 40;
315	/** Availabe for software. */
316	uint64_t u12Available : 12;
317	} EPTPTEBITS;
318	#pragma pack()
319	AssertCompileSize(EPTPTEBITS, 8);
320
321	/** Bits 12-51 - - EPT - Physical Page number of the next level. */
322	#define EPT_PTE_PG_MASK X86_PTE_PAE_PG_MASK_FULL
323	/** The page shift to get the EPT PTE index. */
324	#define EPT_PT_SHIFT X86_PT_PAE_SHIFT
325	/** The EPT PT index mask (apply to a shifted page address). */
326	#define EPT_PT_MASK X86_PT_PAE_MASK
327
328	/**
329	* EPT Page Table Entry.
330	*/
331	#pragma pack(1)
332	typedef union EPTPTE
333	{
334	/** Normal view. */
335	EPTPTEBITS n;
336	/** Unsigned integer view. */
337	X86PGPAEUINT u;
338	/** 64 bit unsigned integer view. */
339	uint64_t au64[1];
340	/** 32 bit unsigned integer view. */
341	uint32_t au32[2];
342	} EPTPTE;
343	#pragma pack()
344	/** Pointer to an EPT Page Directory Table Entry. */
345	typedef EPTPTE *PEPTPTE;
346	/** Pointer to a const EPT Page Directory Table Entry. */
347	typedef const EPTPTE *PCEPTPTE;
348	AssertCompileSize(EPTPTE, 8);
349
350	/**
351	* EPT Page Table.
352	*/
353	#pragma pack(1)
354	typedef struct EPTPT
355	{
356	EPTPTE a[EPT_PG_ENTRIES];
357	} EPTPT;
358	#pragma pack()
359	/** Pointer to an extended page table. */
360	typedef EPTPT *PEPTPT;
361	/** Pointer to a const extended table. */
362	typedef const EPTPT *PCEPTPT;
363
364	/**
365	* VPID and EPT flush types
366	*/
367	typedef enum
368	{
369	/* Invalidate a specific page. */
370	VMX_FLUSH_PAGE = 0,
371	/* Invalidate one context (VPID or EPT) */
372	VMX_FLUSH_SINGLE_CONTEXT = 1,
373	/* Invalidate all contexts (VPIDs or EPTs) */
374	VMX_FLUSH_ALL_CONTEXTS = 2,
375	/* Invalidate a single VPID context retaining global mappings. */
376	VMX_FLUSH_SINGLE_CONTEXT_WITHOUT_GLOBAL = 3,
377	/** 32bit hackishness. */
378	VMX_FLUSH_32BIT_HACK = 0x7fffffff
379	} VMX_FLUSH;
380
381	/** @} */
382
383
384	/** @name VMX Basic Exit Reasons.
385	* @{
386	*/
387	/** And-mask for setting reserved bits to zero */
388	#define VMX_EFLAGS_RESERVED_0 (~0xffc08028)
389	/** Or-mask for setting reserved bits to 1 */
390	#define VMX_EFLAGS_RESERVED_1 0x00000002
391	/** @} */
392
393	/** @name VMX Basic Exit Reasons.
394	* @{
395	*/
396	/** 0 Exception or non-maskable interrupt (NMI). */
397	#define VMX_EXIT_EXCEPTION 0
398	/** 1 External interrupt. */
399	#define VMX_EXIT_EXTERNAL_IRQ 1
400	/** 2 Triple fault. */
401	#define VMX_EXIT_TRIPLE_FAULT 2
402	/** 3 INIT signal. */
403	#define VMX_EXIT_INIT_SIGNAL 3
404	/** 4 Start-up IPI (SIPI). */
405	#define VMX_EXIT_SIPI 4
406	/** 5 I/O system-management interrupt (SMI). */
407	#define VMX_EXIT_IO_SMI_IRQ 5
408	/** 6 Other SMI. */
409	#define VMX_EXIT_SMI_IRQ 6
410	/** 7 Interrupt window. */
411	#define VMX_EXIT_IRQ_WINDOW 7
412	/** 9 Task switch. */
413	#define VMX_EXIT_TASK_SWITCH 9
414	/** 10 Guest software attempted to execute CPUID. */
415	#define VMX_EXIT_CPUID 10
416	/** 12 Guest software attempted to execute HLT. */
417	#define VMX_EXIT_HLT 12
418	/** 13 Guest software attempted to execute INVD. */
419	#define VMX_EXIT_INVD 13
420	/** 14 Guest software attempted to execute INVPG. */
421	#define VMX_EXIT_INVPG 14
422	/** 15 Guest software attempted to execute RDPMC. */
423	#define VMX_EXIT_RDPMC 15
424	/** 16 Guest software attempted to execute RDTSC. */
425	#define VMX_EXIT_RDTSC 16
426	/** 17 Guest software attempted to execute RSM in SMM. */
427	#define VMX_EXIT_RSM 17
428	/** 18 Guest software executed VMCALL. */
429	#define VMX_EXIT_VMCALL 18
430	/** 19 Guest software executed VMCLEAR. */
431	#define VMX_EXIT_VMCLEAR 19
432	/** 20 Guest software executed VMLAUNCH. */
433	#define VMX_EXIT_VMLAUNCH 20
434	/** 21 Guest software executed VMPTRLD. */
435	#define VMX_EXIT_VMPTRLD 21
436	/** 22 Guest software executed VMPTRST. */
437	#define VMX_EXIT_VMPTRST 22
438	/** 23 Guest software executed VMREAD. */
439	#define VMX_EXIT_VMREAD 23
440	/** 24 Guest software executed VMRESUME. */
441	#define VMX_EXIT_VMRESUME 24
442	/** 25 Guest software executed VMWRITE. */
443	#define VMX_EXIT_VMWRITE 25
444	/** 26 Guest software executed VMXOFF. */
445	#define VMX_EXIT_VMXOFF 26
446	/** 27 Guest software executed VMXON. */
447	#define VMX_EXIT_VMXON 27
448	/** 28 Control-register accesses. */
449	#define VMX_EXIT_CRX_MOVE 28
450	/** 29 Debug-register accesses. */
451	#define VMX_EXIT_DRX_MOVE 29
452	/** 30 I/O instruction. */
453	#define VMX_EXIT_PORT_IO 30
454	/** 31 RDMSR. Guest software attempted to execute RDMSR. */
455	#define VMX_EXIT_RDMSR 31
456	/** 32 WRMSR. Guest software attempted to execute WRMSR. */
457	#define VMX_EXIT_WRMSR 32
458	/** 33 VM-entry failure due to invalid guest state. */
459	#define VMX_EXIT_ERR_INVALID_GUEST_STATE 33
460	/** 34 VM-entry failure due to MSR loading. */
461	#define VMX_EXIT_ERR_MSR_LOAD 34
462	/** 36 Guest software executed MWAIT. */
463	#define VMX_EXIT_MWAIT 36
464	/** 39 Guest software attempted to execute MONITOR. */
465	#define VMX_EXIT_MONITOR 39
466	/** 40 Guest software attempted to execute PAUSE. */
467	#define VMX_EXIT_PAUSE 40
468	/** 41 VM-entry failure due to machine-check. */
469	#define VMX_EXIT_ERR_MACHINE_CHECK 41
470	/** 43 TPR below threshold. Guest software executed MOV to CR8. */
471	#define VMX_EXIT_TPR 43
472	/** 44 APIC access. Guest software attempted to access memory at a physical address on the APIC-access page. */
473	#define VMX_EXIT_APIC_ACCESS 44
474	/** 46 Access to GDTR or IDTR. Guest software attempted to execute LGDT, LIDT, SGDT, or SIDT. */
475	#define VMX_EXIT_XDTR_ACCESS 46
476	/** 47 Access to LDTR or TR. Guest software attempted to execute LLDT, LTR, SLDT, or STR. */
477	#define VMX_EXIT_TR_ACCESS 47
478	/** 48 EPT violation. An attempt to access memory with a guest-physical address was disallowed by the configuration of the EPT paging structures. */
479	#define VMX_EXIT_EPT_VIOLATION 48
480	/** 49 EPT misconfiguration. An attempt to access memory with a guest-physical address encountered a misconfigured EPT paging-structure entry. */
481	#define VMX_EXIT_EPT_MISCONFIG 49
482	/** 50 INVEPT. Guest software attempted to execute INVEPT. */
483	#define VMX_EXIT_INVEPT 50
484	/** 52 VMX-preemption timer expired. The preemption timer counted down to zero. */
485	#define VMX_EXIT_PREEMPTION_TIMER 52
486	/** 53 INVVPID. Guest software attempted to execute INVVPID. */
487	#define VMX_EXIT_INVVPID 53
488	/** 54 WBINVD. Guest software attempted to execute WBINVD. */
489	#define VMX_EXIT_WBINVD 54
490	/** 55 XSETBV. Guest software attempted to execute XSETBV. */
491	#define VMX_EXIT_XSETBV 55
492	/** @} */
493
494
495	/** @name VM Instruction Errors
496	* @{
497	*/
498	/** 1 VMCALL executed in VMX root operation. */
499	#define VMX_ERROR_VMCALL 1
500	/** 2 VMCLEAR with invalid physical address. */
501	#define VMX_ERROR_VMCLEAR_INVALID_PHYS_ADDR 2
502	/** 3 VMCLEAR with VMXON pointer. */
503	#define VMX_ERROR_VMCLEAR_INVALID_VMXON_PTR 3
504	/** 4 VMLAUNCH with non-clear VMCS. */
505	#define VMX_ERROR_VMLAUCH_NON_CLEAR_VMCS 4
506	/** 5 VMRESUME with non-launched VMCS. */
507	#define VMX_ERROR_VMRESUME_NON_LAUNCHED_VMCS 5
508	/** 6 VMRESUME with a corrupted VMCS (indicates corruption of the current VMCS). */
509	#define VMX_ERROR_VMRESUME_CORRUPTED_VMCS 6
510	/** 7 VM entry with invalid control field(s). */
511	#define VMX_ERROR_VMENTRY_INVALID_CONTROL_FIELDS 7
512	/** 8 VM entry with invalid host-state field(s). */
513	#define VMX_ERROR_VMENTRY_INVALID_HOST_STATE 8
514	/** 9 VMPTRLD with invalid physical address. */
515	#define VMX_ERROR_VMPTRLD_INVALID_PHYS_ADDR 9
516	/** 10 VMPTRLD with VMXON pointer. */
517	#define VMX_ERROR_VMPTRLD_VMXON_PTR 10
518	/** 11 VMPTRLD with incorrect VMCS revision identifier. */
519	#define VMX_ERROR_VMPTRLD_WRONG_VMCS_REVISION 11
520	/** 12 VMREAD/VMWRITE from/to unsupported VMCS component. */
521	#define VMX_ERROR_VMREAD_INVALID_COMPONENT 12
522	#define VMX_ERROR_VMWRITE_INVALID_COMPONENT VMX_ERROR_VMREAD_INVALID_COMPONENT
523	/** 13 VMWRITE to read-only VMCS component. */
524	#define VMX_ERROR_VMWRITE_READONLY_COMPONENT 13
525	/** 15 VMXON executed in VMX root operation. */
526	#define VMX_ERROR_VMXON_IN_VMX_ROOT_OP 15
527	/** 16 VM entry with invalid executive-VMCS pointer. */
528	#define VMX_ERROR_VMENTRY_INVALID_VMCS_EXEC_PTR 16
529	/** 17 VM entry with non-launched executive VMCS. */
530	#define VMX_ERROR_VMENTRY_NON_LAUNCHED_EXEC_VMCS 17
531	/** 18 VM entry with executive-VMCS pointer not VMXON pointer. */
532	#define VMX_ERROR_VMENTRY_EXEC_VMCS_PTR 18
533	/** 19 VMCALL with non-clear VMCS. */
534	#define VMX_ERROR_VMCALL_NON_CLEAR_VMCS 19
535	/** 20 VMCALL with invalid VM-exit control fields. */
536	#define VMX_ERROR_VMCALL_INVALID_VMEXIT_FIELDS 20
537	/** 22 VMCALL with incorrect MSEG revision identifier. */
538	#define VMX_ERROR_VMCALL_INVALID_MSEG_REVISION 22
539	/** 23 VMXOFF under dual-monitor treatment of SMIs and SMM. */
540	#define VMX_ERROR_VMXOFF_DUAL_MONITOR 23
541	/** 24 VMCALL with invalid SMM-monitor features. */
542	#define VMX_ERROR_VMCALL_INVALID_SMM_MONITOR 24
543	/** 25 VM entry with invalid VM-execution control fields in executive VMCS. */
544	#define VMX_ERROR_VMENTRY_INVALID_VM_EXEC_CTRL 25
545	/** 26 VM entry with events blocked by MOV SS. */
546	#define VMX_ERROR_VMENTRY_MOV_SS 26
547	/** 26 Invalid operand to INVEPT/INVVPID. */
548	#define VMX_ERROR_INVEPTVPID_INVALID_OPERAND 28
549
550	/** @} */
551
552
553	/** @name VMX MSRs - Basic VMX information.
554	* @{
555	*/
556	/** VMCS revision identifier used by the processor. */
557	#define MSR_IA32_VMX_BASIC_INFO_VMCS_ID(a) (a & 0x7FFFFFFF)
558	/** Size of the VMCS. */
559	#define MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(a) ((a >> 32ULL) & 0xFFF)
560	/** Width of physical address used for the VMCS.
561	* 0 -> limited to the available amount of physical ram
562	* 1 -> within the first 4 GB
563	*/
564	#define MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(a) ((a >> 48ULL) & 1)
565	/** Whether the processor supports the dual-monitor treatment of system-management interrupts and system-management code. (always 1) */
566	#define MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(a) ((a >> 49ULL) & 1)
567	/** Memory type that must be used for the VMCS. */
568	#define MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(a) ((a >> 50ULL) & 0xF)
569	/** @} */
570
571
572	/** @name VMX MSRs - Misc VMX info.
573	* @{
574	*/
575	/** Relationship between the preemption timer and tsc; count down every time bit x of the tsc changes. */
576	#define MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(a) (a & 0x1f)
577	/** Activity states supported by the implementation. */
578	#define MSR_IA32_VMX_MISC_ACTIVITY_STATES(a) ((a >> 6ULL) & 0x7)
579	/** Number of CR3 target values supported by the processor. (0-256) */
580	#define MSR_IA32_VMX_MISC_CR3_TARGET(a) ((a >> 16ULL) & 0x1FF)
581	/** Maximum nr of MSRs in the VMCS. (N+1)512. /
582	#define MSR_IA32_VMX_MISC_MAX_MSR(a) ((((a >> 25ULL) & 0x7) + 1) * 512)
583	/** MSEG revision identifier used by the processor. */
584	#define MSR_IA32_VMX_MISC_MSEG_ID(a) (a >> 32ULL)
585	/** @} */
586
587
588	/** @name VMX MSRs - VMCS enumeration field info
589	* @{
590	*/
591	/** Highest field index. */
592	#define MSR_IA32_VMX_VMCS_ENUM_HIGHEST_INDEX(a) ((a >> 1ULL) & 0x1FF)
593
594	/** @} */
595
596
597	/** @name MSR_IA32_VMX_EPT_CAPS; EPT capabilities MSR
598	* @{
599	*/
600	#define MSR_IA32_VMX_EPT_CAPS_RWX_X_ONLY RT_BIT_64(0)
601	#define MSR_IA32_VMX_EPT_CAPS_RWX_W_ONLY RT_BIT_64(1)
602	#define MSR_IA32_VMX_EPT_CAPS_RWX_WX_ONLY RT_BIT_64(2)
603	#define MSR_IA32_VMX_EPT_CAPS_GAW_21_BITS RT_BIT_64(3)
604	#define MSR_IA32_VMX_EPT_CAPS_GAW_30_BITS RT_BIT_64(4)
605	#define MSR_IA32_VMX_EPT_CAPS_GAW_39_BITS RT_BIT_64(5)
606	#define MSR_IA32_VMX_EPT_CAPS_GAW_48_BITS RT_BIT_64(6)
607	#define MSR_IA32_VMX_EPT_CAPS_GAW_57_BITS RT_BIT_64(7)
608	#define MSR_IA32_VMX_EPT_CAPS_EMT_UC RT_BIT_64(8)
609	#define MSR_IA32_VMX_EPT_CAPS_EMT_WC RT_BIT_64(9)
610	#define MSR_IA32_VMX_EPT_CAPS_EMT_WT RT_BIT_64(12)
611	#define MSR_IA32_VMX_EPT_CAPS_EMT_WP RT_BIT_64(13)
612	#define MSR_IA32_VMX_EPT_CAPS_EMT_WB RT_BIT_64(14)
613	#define MSR_IA32_VMX_EPT_CAPS_SP_21_BITS RT_BIT_64(16)
614	#define MSR_IA32_VMX_EPT_CAPS_SP_30_BITS RT_BIT_64(17)
615	#define MSR_IA32_VMX_EPT_CAPS_SP_39_BITS RT_BIT_64(18)
616	#define MSR_IA32_VMX_EPT_CAPS_SP_48_BITS RT_BIT_64(19)
617	#define MSR_IA32_VMX_EPT_CAPS_INVEPT RT_BIT_64(20)
618	#define MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV RT_BIT_64(24)
619	#define MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT RT_BIT_64(25)
620	#define MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL RT_BIT_64(26)
621	#define MSR_IA32_VMX_EPT_CAPS_INVVPID RT_BIT_64(32)
622	#define MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV RT_BIT_64(40)
623	#define MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT RT_BIT_64(41)
624	#define MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL RT_BIT_64(42)
625	#define MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT_GLOBAL RT_BIT_64(43)
626
627	/** @} */
628
629	/** @name Extended Page Table Pointer (EPTP)
630	* @{
631	*/
632	/** Uncachable EPT paging structure memory type. */
633	#define VMX_EPT_MEMTYPE_UC 0
634	/** Write-back EPT paging structure memory type. */
635	#define VMX_EPT_MEMTYPE_WB 6
636	/** Shift value to get the EPT page walk length (bits 5-3) */
637	#define VMX_EPT_PAGE_WALK_LENGTH_SHIFT 3
638	/** Mask value to get the EPT page walk length (bits 5-3) */
639	#define VMX_EPT_PAGE_WALK_LENGTH_MASK 7
640	/** Default EPT page walk length */
641	#define VMX_EPT_PAGE_WALK_LENGTH_DEFAULT 3
642	/** @} */
643
644
645	/** @name VMCS field encoding - 16 bits guest fields
646	* @{
647	*/
648	#define VMX_VMCS16_GUEST_FIELD_VPID 0x0
649	#define VMX_VMCS16_GUEST_FIELD_ES 0x800
650	#define VMX_VMCS16_GUEST_FIELD_CS 0x802
651	#define VMX_VMCS16_GUEST_FIELD_SS 0x804
652	#define VMX_VMCS16_GUEST_FIELD_DS 0x806
653	#define VMX_VMCS16_GUEST_FIELD_FS 0x808
654	#define VMX_VMCS16_GUEST_FIELD_GS 0x80A
655	#define VMX_VMCS16_GUEST_FIELD_LDTR 0x80C
656	#define VMX_VMCS16_GUEST_FIELD_TR 0x80E
657	/** @} */
658
659	/** @name VMCS field encoding - 16 bits host fields
660	* @{
661	*/
662	#define VMX_VMCS16_HOST_FIELD_ES 0xC00
663	#define VMX_VMCS16_HOST_FIELD_CS 0xC02
664	#define VMX_VMCS16_HOST_FIELD_SS 0xC04
665	#define VMX_VMCS16_HOST_FIELD_DS 0xC06
666	#define VMX_VMCS16_HOST_FIELD_FS 0xC08
667	#define VMX_VMCS16_HOST_FIELD_GS 0xC0A
668	#define VMX_VMCS16_HOST_FIELD_TR 0xC0C
669	/** @} */
670
671	/** @name VMCS field encoding - 64 bits host fields
672	* @{
673	*/
674	#define VMX_VMCS_HOST_FIELD_PAT_FULL 0x2C00
675	#define VMX_VMCS_HOST_FIELD_PAT_HIGH 0x2C01
676	#define VMX_VMCS_HOST_FIELD_EFER_FULL 0x2C02
677	#define VMX_VMCS_HOST_FIELD_EFER_HIGH 0x2C03
678	#define VMX_VMCS_HOST_PERF_GLOBAL_CTRL_FULL 0x2C04 /*< MSR IA32_PERF_GLOBAL_CTRL /
679	#define VMX_VMCS_HOST_PERF_GLOBAL_CTRL_HIGH 0x2C05 /*< MSR IA32_PERF_GLOBAL_CTRL /
680	/** @} */
681
682
683	/** @name VMCS field encoding - 64 Bits control fields
684	* @{
685	*/
686	#define VMX_VMCS_CTRL_IO_BITMAP_A_FULL 0x2000
687	#define VMX_VMCS_CTRL_IO_BITMAP_A_HIGH 0x2001
688	#define VMX_VMCS_CTRL_IO_BITMAP_B_FULL 0x2002
689	#define VMX_VMCS_CTRL_IO_BITMAP_B_HIGH 0x2003
690
691	/* Optional */
692	#define VMX_VMCS_CTRL_MSR_BITMAP_FULL 0x2004
693	#define VMX_VMCS_CTRL_MSR_BITMAP_HIGH 0x2005
694
695	#define VMX_VMCS_CTRL_VMEXIT_MSR_STORE_FULL 0x2006
696	#define VMX_VMCS_CTRL_VMEXIT_MSR_STORE_HIGH 0x2007
697	#define VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_FULL 0x2008
698	#define VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_HIGH 0x2009
699
700	#define VMX_VMCS_CTRL_VMENTRY_MSR_LOAD_FULL 0x200A
701	#define VMX_VMCS_CTRL_VMENTRY_MSR_LOAD_HIGH 0x200B
702
703	#define VMX_VMCS_CTRL_EXEC_VMCS_PTR_FULL 0x200C
704	#define VMX_VMCS_CTRL_EXEC_VMCS_PTR_HIGH 0x200D
705
706	#define VMX_VMCS_CTRL_TSC_OFFSET_FULL 0x2010
707	#define VMX_VMCS_CTRL_TSC_OFFSET_HIGH 0x2011
708
709	/** Optional (VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW) */
710	#define VMX_VMCS_CTRL_VAPIC_PAGEADDR_FULL 0x2012
711	#define VMX_VMCS_CTRL_VAPIC_PAGEADDR_HIGH 0x2013
712
713	/** Optional (VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC) */
714	#define VMX_VMCS_CTRL_APIC_ACCESSADDR_FULL 0x2014
715	#define VMX_VMCS_CTRL_APIC_ACCESSADDR_HIGH 0x2015
716
717	/** Extended page table pointer. */
718	#define VMX_VMCS_CTRL_EPTP_FULL 0x201a
719	#define VMX_VMCS_CTRL_EPTP_HIGH 0x201b
720
721	/** VM-exit phyiscal address. */
722	#define VMX_VMCS_EXIT_PHYS_ADDR_FULL 0x2400
723	#define VMX_VMCS_EXIT_PHYS_ADDR_HIGH 0x2401
724	/** @} */
725
726
727	/** @name VMCS field encoding - 64 Bits guest fields
728	* @{
729	*/
730	#define VMX_VMCS_GUEST_LINK_PTR_FULL 0x2800
731	#define VMX_VMCS_GUEST_LINK_PTR_HIGH 0x2801
732	#define VMX_VMCS_GUEST_DEBUGCTL_FULL 0x2802 /*< MSR IA32_DEBUGCTL /
733	#define VMX_VMCS_GUEST_DEBUGCTL_HIGH 0x2803 /*< MSR IA32_DEBUGCTL /
734	#define VMX_VMCS_GUEST_PAT_FULL 0x2804
735	#define VMX_VMCS_GUEST_PAT_HIGH 0x2805
736	#define VMX_VMCS_GUEST_EFER_FULL 0x2806
737	#define VMX_VMCS_GUEST_EFER_HIGH 0x2807
738	#define VMX_VMCS_GUEST_PERF_GLOBAL_CTRL_FULL 0x2808 /*< MSR IA32_PERF_GLOBAL_CTRL /
739	#define VMX_VMCS_GUEST_PERF_GLOBAL_CTRL_HIGH 0x2809 /*< MSR IA32_PERF_GLOBAL_CTRL /
740	#define VMX_VMCS_GUEST_PDPTR0_FULL 0x280A
741	#define VMX_VMCS_GUEST_PDPTR0_HIGH 0x280B
742	#define VMX_VMCS_GUEST_PDPTR1_FULL 0x280C
743	#define VMX_VMCS_GUEST_PDPTR1_HIGH 0x280D
744	#define VMX_VMCS_GUEST_PDPTR2_FULL 0x280E
745	#define VMX_VMCS_GUEST_PDPTR2_HIGH 0x280F
746	#define VMX_VMCS_GUEST_PDPTR3_FULL 0x2810
747	#define VMX_VMCS_GUEST_PDPTR3_HIGH 0x2811
748	/** @} */
749
750
751	/** @name VMCS field encoding - 32 Bits control fields
752	* @{
753	*/
754	#define VMX_VMCS_CTRL_PIN_EXEC_CONTROLS 0x4000
755	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS 0x4002
756	#define VMX_VMCS_CTRL_EXCEPTION_BITMAP 0x4004
757	#define VMX_VMCS_CTRL_PAGEFAULT_ERROR_MASK 0x4006
758	#define VMX_VMCS_CTRL_PAGEFAULT_ERROR_MATCH 0x4008
759	#define VMX_VMCS_CTRL_CR3_TARGET_COUNT 0x400A
760	#define VMX_VMCS_CTRL_EXIT_CONTROLS 0x400C
761	#define VMX_VMCS_CTRL_EXIT_MSR_STORE_COUNT 0x400E
762	#define VMX_VMCS_CTRL_EXIT_MSR_LOAD_COUNT 0x4010
763	#define VMX_VMCS_CTRL_ENTRY_CONTROLS 0x4012
764	#define VMX_VMCS_CTRL_ENTRY_MSR_LOAD_COUNT 0x4014
765	#define VMX_VMCS_CTRL_ENTRY_IRQ_INFO 0x4016
766	#define VMX_VMCS_CTRL_ENTRY_EXCEPTION_ERRCODE 0x4018
767	#define VMX_VMCS_CTRL_ENTRY_INSTR_LENGTH 0x401A
768	/** This field exists only on processors that support the 1-setting of the use TPR shadow VM-execution control. */
769	#define VMX_VMCS_CTRL_TPR_THRESHOLD 0x401C
770	/** This field exists only on processors that support the 1-setting of the activate secondary controls VM-execution control. */
771	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS2 0x401E
772	/** @} */
773
774
775	/** @name VMX_VMCS_CTRL_PIN_EXEC_CONTROLS
776	* @{
777	*/
778	/** External interrupts cause VM exits if set; otherwise dispatched through the guest's IDT. */
779	#define VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT RT_BIT(0)
780	/** Non-maskable interrupts cause VM exits if set; otherwise dispatched through the guest's IDT. */
781	#define VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT RT_BIT(3)
782	/** Virtual NMIs. */
783	#define VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI RT_BIT(5)
784	/** Activate VMX preemption timer. */
785	#define VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER RT_BIT(6)
786	/* All other bits are reserved and must be set according to MSR IA32_VMX_PROCBASED_CTLS. */
787	/** @} */
788
789	/** @name VMX_VMCS_CTRL_PROC_EXEC_CONTROLS
790	* @{
791	*/
792	/** VM Exit as soon as RFLAGS.IF=1 and no blocking is active. */
793	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT RT_BIT(2)
794	/** Use timestamp counter offset. */
795	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET RT_BIT(3)
796	/** VM Exit when executing the HLT instruction. */
797	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT RT_BIT(7)
798	/** VM Exit when executing the INVLPG instruction. */
799	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT RT_BIT(9)
800	/** VM Exit when executing the MWAIT instruction. */
801	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT RT_BIT(10)
802	/** VM Exit when executing the RDPMC instruction. */
803	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT RT_BIT(11)
804	/** VM Exit when executing the RDTSC instruction. */
805	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT RT_BIT(12)
806	/** VM Exit when executing the MOV to CR3 instruction. (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
807	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT RT_BIT(15)
808	/** VM Exit when executing the MOV from CR3 instruction. (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
809	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT RT_BIT(16)
810	/** VM Exit on CR8 loads. */
811	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT RT_BIT(19)
812	/** VM Exit on CR8 stores. */
813	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT RT_BIT(20)
814	/** Use TPR shadow. */
815	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW RT_BIT(21)
816	/** VM Exit when executing a MOV DRx instruction. */
817	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT RT_BIT(23)
818	/** VM Exit when executing IO instructions. */
819	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT RT_BIT(24)
820	/** Use IO bitmaps. */
821	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS RT_BIT(25)
822	/** Monitor trap flag. */
823	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG RT_BIT(27)
824	/** Use MSR bitmaps. */
825	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS RT_BIT(28)
826	/** VM Exit when executing the MONITOR instruction. */
827	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT RT_BIT(29)
828	/** VM Exit when executing the PAUSE instruction. */
829	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT RT_BIT(30)
830	/** Determines whether the secondary processor based VM-execution controls are used. */
831	#define VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL RT_BIT(31)
832	/** @} */
833
834	/** @name VMX_VMCS_CTRL_PROC_EXEC_CONTROLS2
835	* @{
836	*/
837	/** Virtualize APIC access. */
838	#define VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC RT_BIT(0)
839	/** EPT supported/enabled. */
840	#define VMX_VMCS_CTRL_PROC_EXEC2_EPT RT_BIT(1)
841	/** VPID supported/enabled. */
842	#define VMX_VMCS_CTRL_PROC_EXEC2_VPID RT_BIT(5)
843	/** VM Exit when executing the WBINVD instruction. */
844	#define VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT RT_BIT(6)
845	/** @} */
846
847
848	/** @name VMX_VMCS_CTRL_ENTRY_CONTROLS
849	* @{
850	*/
851	/** Load guest debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
852	#define VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG RT_BIT(2)
853	/** 64 bits guest mode. Must be 0 for CPUs that don't support AMD64. */
854	#define VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE RT_BIT(9)
855	/** In SMM mode after VM-entry. */
856	#define VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM RT_BIT(10)
857	/** Disable dual treatment of SMI and SMM; must be zero for VM-entry outside of SMM. */
858	#define VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON RT_BIT(11)
859	/** This control determines whether the guest IA32_PERF_GLOBAL_CTRL MSR is loaded on VM entry. */
860	#define VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR RT_BIT(13)
861	/** This control determines whether the guest IA32_PAT MSR is loaded on VM entry. */
862	#define VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR RT_BIT(14)
863	/** This control determines whether the guest IA32_EFER MSR is loaded on VM entry. */
864	#define VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR RT_BIT(15)
865	/** @} */
866
867
868	/** @name VMX_VMCS_CTRL_EXIT_CONTROLS
869	* @{
870	*/
871	/** Save guest debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
872	#define VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG RT_BIT(2)
873	/** Return to long mode after a VM-exit. */
874	#define VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64 RT_BIT(9)
875	/** This control determines whether the IA32_PERF_GLOBAL_CTRL MSR is loaded on VM exit. */
876	#define VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_PERF_MSR RT_BIT(12)
877	/** Acknowledge external interrupts with the irq controller if one caused a VM-exit. */
878	#define VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ RT_BIT(15)
879	/** This control determines whether the guest IA32_PAT MSR is saved on VM exit. */
880	#define VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR RT_BIT(18)
881	/** This control determines whether the host IA32_PAT MSR is loaded on VM exit. */
882	#define VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR RT_BIT(19)
883	/** This control determines whether the guest IA32_EFER MSR is saved on VM exit. */
884	#define VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR RT_BIT(20)
885	/** This control determines whether the host IA32_EFER MSR is loaded on VM exit. */
886	#define VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR RT_BIT(21)
887	/** This control determines whether the value of the VMX preemption timer is saved on VM exit. */
888	#define VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER RT_BIT(22)
889	/** @} */
890
891	/** @name VMCS field encoding - 32 Bits read-only fields
892	* @{
893	*/
894	#define VMX_VMCS32_RO_VM_INSTR_ERROR 0x4400
895	#define VMX_VMCS32_RO_EXIT_REASON 0x4402
896	#define VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO 0x4404
897	#define VMX_VMCS32_RO_EXIT_INTERRUPTION_ERRCODE 0x4406
898	#define VMX_VMCS32_RO_IDT_INFO 0x4408
899	#define VMX_VMCS32_RO_IDT_ERRCODE 0x440A
900	#define VMX_VMCS32_RO_EXIT_INSTR_LENGTH 0x440C
901	#define VMX_VMCS32_RO_EXIT_INSTR_INFO 0x440E
902	/** @} */
903
904	/** @name VMX_VMCS_RO_EXIT_INTERRUPTION_INFO
905	* @{
906	*/
907	#define VMX_EXIT_INTERRUPTION_INFO_VECTOR(a) (a & 0xff)
908	#define VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT 8
909	#define VMX_EXIT_INTERRUPTION_INFO_TYPE(a) ((a >> VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT) & 7)
910	#define VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID RT_BIT(11)
911	#define VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID(a) (a & VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID)
912	#define VMX_EXIT_INTERRUPTION_INFO_NMI_UNBLOCK(a) (a & RT_BIT(12))
913	#define VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT 31
914	#define VMX_EXIT_INTERRUPTION_INFO_VALID(a) (a & RT_BIT(31))
915	/** Construct an irq event injection value from the exit interruption info value (same except that bit 12 is reserved). */
916	#define VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(a) (a & ~RT_BIT(12))
917	/** @} */
918
919	/** @name VMX_VMCS_RO_EXIT_INTERRUPTION_INFO_TYPE
920	* @{
921	*/
922	#define VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT 0
923	#define VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI 2
924	#define VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT 3
925	#define VMX_EXIT_INTERRUPTION_INFO_TYPE_SW 4 /*< int xx /
926	#define VMX_EXIT_INTERRUPTION_INFO_TYPE_DBEXCPT 5 /*< Why are we getting this one?? /
927	#define VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT 6
928	/** @} */
929
930
931	/** @name VMCS field encoding - 32 Bits guest state fields
932	* @{
933	*/
934	#define VMX_VMCS32_GUEST_ES_LIMIT 0x4800
935	#define VMX_VMCS32_GUEST_CS_LIMIT 0x4802
936	#define VMX_VMCS32_GUEST_SS_LIMIT 0x4804
937	#define VMX_VMCS32_GUEST_DS_LIMIT 0x4806
938	#define VMX_VMCS32_GUEST_FS_LIMIT 0x4808
939	#define VMX_VMCS32_GUEST_GS_LIMIT 0x480A
940	#define VMX_VMCS32_GUEST_LDTR_LIMIT 0x480C
941	#define VMX_VMCS32_GUEST_TR_LIMIT 0x480E
942	#define VMX_VMCS32_GUEST_GDTR_LIMIT 0x4810
943	#define VMX_VMCS32_GUEST_IDTR_LIMIT 0x4812
944	#define VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS 0x4814
945	#define VMX_VMCS32_GUEST_CS_ACCESS_RIGHTS 0x4816
946	#define VMX_VMCS32_GUEST_SS_ACCESS_RIGHTS 0x4818
947	#define VMX_VMCS32_GUEST_DS_ACCESS_RIGHTS 0x481A
948	#define VMX_VMCS32_GUEST_FS_ACCESS_RIGHTS 0x481C
949	#define VMX_VMCS32_GUEST_GS_ACCESS_RIGHTS 0x481E
950	#define VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS 0x4820
951	#define VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS 0x4822
952	#define VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE 0x4824
953	#define VMX_VMCS32_GUEST_ACTIVITY_STATE 0x4826
954	#define VMX_VMCS32_GUEST_SYSENTER_CS 0x482A /*< MSR IA32_SYSENTER_CS /
955	#define VMX_VMCS32_GUEST_PREEMPTION_TIMER_VALUE 0x482E
956	/** @} */
957
958
959	/** @name VMX_VMCS_GUEST_ACTIVITY_STATE
960	* @{
961	*/
962	/** The logical processor is active. */
963	#define VMX_CMS_GUEST_ACTIVITY_ACTIVE 0x0
964	/** The logical processor is inactive, because executed a HLT instruction. */
965	#define VMX_CMS_GUEST_ACTIVITY_HLT 0x1
966	/** The logical processor is inactive, because of a triple fault or other serious error. */
967	#define VMX_CMS_GUEST_ACTIVITY_SHUTDOWN 0x2
968	/** The logical processor is inactive, because it's waiting for a startup-IPI */
969	#define VMX_CMS_GUEST_ACTIVITY_SIPI_WAIT 0x3
970	/** @} */
971
972
973	/** @name VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE
974	* @{
975	*/
976	#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_STI RT_BIT(0)
977	#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_MOVSS RT_BIT(1)
978	#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_SMI RT_BIT(2)
979	#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_NMI RT_BIT(3)
980	/** @} */
981
982
983	/** @name VMCS field encoding - 32 Bits host state fields
984	* @{
985	*/
986	#define VMX_VMCS32_HOST_SYSENTER_CS 0x4C00
987	/** @} */
988
989	/** @name Natural width control fields
990	* @{
991	*/
992	#define VMX_VMCS_CTRL_CR0_MASK 0x6000
993	#define VMX_VMCS_CTRL_CR4_MASK 0x6002
994	#define VMX_VMCS_CTRL_CR0_READ_SHADOW 0x6004
995	#define VMX_VMCS_CTRL_CR4_READ_SHADOW 0x6006
996	#define VMX_VMCS_CTRL_CR3_TARGET_VAL0 0x6008
997	#define VMX_VMCS_CTRL_CR3_TARGET_VAL1 0x600A
998	#define VMX_VMCS_CTRL_CR3_TARGET_VAL2 0x600C
999	#define VMX_VMCS_CTRL_CR3_TARGET_VAL31 0x600E
1000	/** @} */
1001
1002
1003	/** @name Natural width read-only data fields
1004	* @{
1005	*/
1006	#define VMX_VMCS_RO_EXIT_QUALIFICATION 0x6400
1007	#define VMX_VMCS_RO_IO_RCX 0x6402
1008	#define VMX_VMCS_RO_IO_RSX 0x6404
1009	#define VMX_VMCS_RO_IO_RDI 0x6406
1010	#define VMX_VMCS_RO_IO_RIP 0x6408
1011	#define VMX_VMCS_EXIT_GUEST_LINEAR_ADDR 0x640A
1012	/** @} */
1013
1014
1015	/** @name VMX_VMCS_RO_EXIT_QUALIFICATION
1016	* @{
1017	*/
1018	/** 0-2: Debug register number */
1019	#define VMX_EXIT_QUALIFICATION_DRX_REGISTER(a) (a & 7)
1020	/** 3: Reserved; cleared to 0. */
1021	#define VMX_EXIT_QUALIFICATION_DRX_RES1(a) ((a >> 3) & 1)
1022	/** 4: Direction of move (0 = write, 1 = read) */
1023	#define VMX_EXIT_QUALIFICATION_DRX_DIRECTION(a) ((a >> 4) & 1)
1024	/** 5-7: Reserved; cleared to 0. */
1025	#define VMX_EXIT_QUALIFICATION_DRX_RES2(a) ((a >> 5) & 7)
1026	/** 8-11: General purpose register number. */
1027	#define VMX_EXIT_QUALIFICATION_DRX_GENREG(a) ((a >> 8) & 0xF)
1028	/** Rest: reserved. */
1029	/** @} */
1030
1031	/** @name VMX_EXIT_QUALIFICATION_DRX_DIRECTION values
1032	* @{
1033	*/
1034	#define VMX_EXIT_QUALIFICATION_DRX_DIRECTION_WRITE 0
1035	#define VMX_EXIT_QUALIFICATION_DRX_DIRECTION_READ 1
1036	/** @} */
1037
1038
1039
1040	/** @name CRx accesses
1041	* @{
1042	*/
1043	/** 0-3: Control register number (0 for CLTS & LMSW) */
1044	#define VMX_EXIT_QUALIFICATION_CRX_REGISTER(a) (a & 0xF)
1045	/** 4-5: Access type. */
1046	#define VMX_EXIT_QUALIFICATION_CRX_ACCESS(a) ((a >> 4) & 3)
1047	/** 6: LMSW operand type */
1048	#define VMX_EXIT_QUALIFICATION_CRX_LMSW_OP(a) ((a >> 6) & 1)
1049	/** 7: Reserved; cleared to 0. */
1050	#define VMX_EXIT_QUALIFICATION_CRX_RES1(a) ((a >> 7) & 1)
1051	/** 8-11: General purpose register number (0 for CLTS & LMSW). */
1052	#define VMX_EXIT_QUALIFICATION_CRX_GENREG(a) ((a >> 8) & 0xF)
1053	/** 12-15: Reserved; cleared to 0. */
1054	#define VMX_EXIT_QUALIFICATION_CRX_RES2(a) ((a >> 12) & 0xF)
1055	/** 16-31: LMSW source data (else 0). */
1056	#define VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(a) ((a >> 16) & 0xFFFF)
1057	/** Rest: reserved. */
1058	/** @} */
1059
1060	/** @name VMX_EXIT_QUALIFICATION_CRX_ACCESS
1061	* @{
1062	*/
1063	#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_WRITE 0
1064	#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_READ 1
1065	#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_CLTS 2
1066	#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_LMSW 3
1067	/** @} */
1068
1069
1070	/** @name VMX_EXIT_EPT_VIOLATION
1071	* @{
1072	*/
1073	/** Set if the violation was caused by a data read. */
1074	#define VMX_EXIT_QUALIFICATION_EPT_DATA_READ RT_BIT(0)
1075	/** Set if the violation was caused by a data write. */
1076	#define VMX_EXIT_QUALIFICATION_EPT_DATA_WRITE RT_BIT(1)
1077	/** Set if the violation was caused by an insruction fetch. */
1078	#define VMX_EXIT_QUALIFICATION_EPT_INSTR_FETCH RT_BIT(2)
1079	/** AND of the present bit of all EPT structures. */
1080	#define VMX_EXIT_QUALIFICATION_EPT_ENTRY_PRESENT RT_BIT(3)
1081	/** AND of the write bit of all EPT structures. */
1082	#define VMX_EXIT_QUALIFICATION_EPT_ENTRY_WRITE RT_BIT(4)
1083	/** AND of the execute bit of all EPT structures. */
1084	#define VMX_EXIT_QUALIFICATION_EPT_ENTRY_EXECUTE RT_BIT(5)
1085	/** Set if the guest linear address field contains the faulting address. */
1086	#define VMX_EXIT_QUALIFICATION_EPT_GUEST_ADDR_VALID RT_BIT(7)
1087	/** If bit 7 is one: (reserved otherwise)
1088	* 1 - violation due to physical address access.
1089	* 0 - violation caused by page walk or access/dirty bit updates
1090	*/
1091	#define VMX_EXIT_QUALIFICATION_EPT_TRANSLATED_ACCESS RT_BIT(8)
1092	/** @} */
1093
1094
1095	/** @name VMX_EXIT_PORT_IO
1096	* @{
1097	*/
1098	/** 0-2: IO operation width. */
1099	#define VMX_EXIT_QUALIFICATION_IO_WIDTH(a) (a & 7)
1100	/** 3: IO operation direction. */
1101	#define VMX_EXIT_QUALIFICATION_IO_DIRECTION(a) ((a >> 3) & 1)
1102	/** 4: String IO operation. */
1103	#define VMX_EXIT_QUALIFICATION_IO_STRING(a) ((a >> 4) & 1)
1104	/** 5: Repeated IO operation. */
1105	#define VMX_EXIT_QUALIFICATION_IO_REP(a) ((a >> 5) & 1)
1106	/** 6: Operand encoding. */
1107	#define VMX_EXIT_QUALIFICATION_IO_ENCODING(a) ((a >> 6) & 1)
1108	/** 16-31: IO Port (0-0xffff). */
1109	#define VMX_EXIT_QUALIFICATION_IO_PORT(a) ((a >> 16) & 0xffff)
1110	/* Rest reserved. */
1111	/** @} */
1112
1113	/** @name VMX_EXIT_QUALIFICATION_IO_DIRECTION
1114	* @{
1115	*/
1116	#define VMX_EXIT_QUALIFICATION_IO_DIRECTION_OUT 0
1117	#define VMX_EXIT_QUALIFICATION_IO_DIRECTION_IN 1
1118	/** @} */
1119
1120
1121	/** @name VMX_EXIT_QUALIFICATION_IO_ENCODING
1122	* @{
1123	*/
1124	#define VMX_EXIT_QUALIFICATION_IO_ENCODING_DX 0
1125	#define VMX_EXIT_QUALIFICATION_IO_ENCODING_IMM 1
1126	/** @} */
1127
1128	/** @} */
1129
1130	/** @name VMCS field encoding - Natural width guest state fields
1131	* @{
1132	*/
1133	#define VMX_VMCS64_GUEST_CR0 0x6800
1134	#define VMX_VMCS64_GUEST_CR3 0x6802
1135	#define VMX_VMCS64_GUEST_CR4 0x6804
1136	#define VMX_VMCS64_GUEST_ES_BASE 0x6806
1137	#define VMX_VMCS64_GUEST_CS_BASE 0x6808
1138	#define VMX_VMCS64_GUEST_SS_BASE 0x680A
1139	#define VMX_VMCS64_GUEST_DS_BASE 0x680C
1140	#define VMX_VMCS64_GUEST_FS_BASE 0x680E
1141	#define VMX_VMCS64_GUEST_GS_BASE 0x6810
1142	#define VMX_VMCS64_GUEST_LDTR_BASE 0x6812
1143	#define VMX_VMCS64_GUEST_TR_BASE 0x6814
1144	#define VMX_VMCS64_GUEST_GDTR_BASE 0x6816
1145	#define VMX_VMCS64_GUEST_IDTR_BASE 0x6818
1146	#define VMX_VMCS64_GUEST_DR7 0x681A
1147	#define VMX_VMCS64_GUEST_RSP 0x681C
1148	#define VMX_VMCS64_GUEST_RIP 0x681E
1149	#define VMX_VMCS_GUEST_RFLAGS 0x6820
1150	#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS 0x6822
1151	#define VMX_VMCS64_GUEST_SYSENTER_ESP 0x6824 /*< MSR IA32_SYSENTER_ESP /
1152	#define VMX_VMCS64_GUEST_SYSENTER_EIP 0x6826 /*< MSR IA32_SYSENTER_EIP /
1153	/** @} */
1154
1155
1156	/** @name VMX_VMCS_GUEST_DEBUG_EXCEPTIONS
1157	* @{
1158	*/
1159	/** Hardware breakpoint 0 was met. */
1160	#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B0 RT_BIT(0)
1161	/** Hardware breakpoint 1 was met. */
1162	#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B1 RT_BIT(1)
1163	/** Hardware breakpoint 2 was met. */
1164	#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B2 RT_BIT(2)
1165	/** Hardware breakpoint 3 was met. */
1166	#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B3 RT_BIT(3)
1167	/** At least one data or IO breakpoint was hit. */
1168	#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_BREAKPOINT_ENABLED RT_BIT(12)
1169	/** A debug exception would have been triggered by single-step execution mode. */
1170	#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_BS RT_BIT(14)
1171	/** Bits 4-11, 13 and 15-63 are reserved. */
1172
1173	/** @} */
1174
1175	/** @name VMCS field encoding - Natural width host state fields
1176	* @{
1177	*/
1178	#define VMX_VMCS_HOST_CR0 0x6C00
1179	#define VMX_VMCS_HOST_CR3 0x6C02
1180	#define VMX_VMCS_HOST_CR4 0x6C04
1181	#define VMX_VMCS_HOST_FS_BASE 0x6C06
1182	#define VMX_VMCS_HOST_GS_BASE 0x6C08
1183	#define VMX_VMCS_HOST_TR_BASE 0x6C0A
1184	#define VMX_VMCS_HOST_GDTR_BASE 0x6C0C
1185	#define VMX_VMCS_HOST_IDTR_BASE 0x6C0E
1186	#define VMX_VMCS_HOST_SYSENTER_ESP 0x6C10
1187	#define VMX_VMCS_HOST_SYSENTER_EIP 0x6C12
1188	#define VMX_VMCS_HOST_RSP 0x6C14
1189	#define VMX_VMCS_HOST_RIP 0x6C16
1190	/** @} */
1191
1192	/** @} */
1193
1194
1195	#if RT_INLINE_ASM_GNU_STYLE
1196	# define __STR(x) #x
1197	# define STR(x) __STR(x)
1198	#endif
1199
1200
1201	/** @defgroup grp_vmx_asm vmx assembly helpers
1202	* @ingroup grp_vmx
1203	* @{
1204	*/
1205
1206	/**
1207	* Executes VMXON
1208	*
1209	* @returns VBox status code
1210	* @param pVMXOn Physical address of VMXON structure
1211	*/
1212	#if RT_INLINE_ASM_EXTERNAL \|\| HC_ARCH_BITS == 64 \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1213	DECLASM(int) VMXEnable(RTHCPHYS pVMXOn);
1214	#else
1215	DECLINLINE(int) VMXEnable(RTHCPHYS pVMXOn)
1216	{
1217	int rc = VINF_SUCCESS;
1218	# if RT_INLINE_ASM_GNU_STYLE
1219	__asm__ __volatile__ (
1220	"push %3 \n\t"
1221	"push %2 \n\t"
1222	".byte 0xF3, 0x0F, 0xC7, 0x34, 0x24 # VMXON [esp] \n\t"
1223	"ja 2f \n\t"
1224	"je 1f \n\t"
1225	"movl $"STR(VERR_VMX_INVALID_VMXON_PTR)", %0 \n\t"
1226	"jmp 2f \n\t"
1227	"1: \n\t"
1228	"movl $"STR(VERR_VMX_GENERIC)", %0 \n\t"
1229	"2: \n\t"
1230	"add $8, %%esp \n\t"
1231	:"=rm"(rc)
1232	:"0"(VINF_SUCCESS),
1233	"ir"((uint32_t)pVMXOn), /* don't allow direct memory reference here, */
1234	"ir"((uint32_t)(pVMXOn >> 32)) /* this would not work with -fomit-frame-pointer */
1235	:"memory"
1236	);
1237	# else
1238	__asm
1239	{
1240	push dword ptr [pVMXOn+4]
1241	push dword ptr [pVMXOn]
1242	_emit 0xF3
1243	_emit 0x0F
1244	_emit 0xC7
1245	_emit 0x34
1246	_emit 0x24 /* VMXON [esp] */
1247	jnc vmxon_good
1248	mov dword ptr [rc], VERR_VMX_INVALID_VMXON_PTR
1249	jmp the_end
1250
1251	vmxon_good:
1252	jnz the_end
1253	mov dword ptr [rc], VERR_VMX_GENERIC
1254	the_end:
1255	add esp, 8
1256	}
1257	# endif
1258	return rc;
1259	}
1260	#endif
1261
1262
1263	/**
1264	* Executes VMXOFF
1265	*/
1266	#if RT_INLINE_ASM_EXTERNAL \|\| HC_ARCH_BITS == 64 \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1267	DECLASM(void) VMXDisable(void);
1268	#else
1269	DECLINLINE(void) VMXDisable(void)
1270	{
1271	# if RT_INLINE_ASM_GNU_STYLE
1272	__asm__ __volatile__ (
1273	".byte 0x0F, 0x01, 0xC4 # VMXOFF \n\t"
1274	);
1275	# else
1276	__asm
1277	{
1278	_emit 0x0F
1279	_emit 0x01
1280	_emit 0xC4 /* VMXOFF */
1281	}
1282	# endif
1283	}
1284	#endif
1285
1286
1287	/**
1288	* Executes VMCLEAR
1289	*
1290	* @returns VBox status code
1291	* @param pVMCS Physical address of VM control structure
1292	*/
1293	#if RT_INLINE_ASM_EXTERNAL \|\| HC_ARCH_BITS == 64 \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1294	DECLASM(int) VMXClearVMCS(RTHCPHYS pVMCS);
1295	#else
1296	DECLINLINE(int) VMXClearVMCS(RTHCPHYS pVMCS)
1297	{
1298	int rc = VINF_SUCCESS;
1299	# if RT_INLINE_ASM_GNU_STYLE
1300	__asm__ __volatile__ (
1301	"push %3 \n\t"
1302	"push %2 \n\t"
1303	".byte 0x66, 0x0F, 0xC7, 0x34, 0x24 # VMCLEAR [esp] \n\t"
1304	"jnc 1f \n\t"
1305	"movl $"STR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
1306	"1: \n\t"
1307	"add $8, %%esp \n\t"
1308	:"=rm"(rc)
1309	:"0"(VINF_SUCCESS),
1310	"ir"((uint32_t)pVMCS), /* don't allow direct memory reference here, */
1311	"ir"((uint32_t)(pVMCS >> 32)) /* this would not work with -fomit-frame-pointer */
1312	:"memory"
1313	);
1314	# else
1315	__asm
1316	{
1317	push dword ptr [pVMCS+4]
1318	push dword ptr [pVMCS]
1319	_emit 0x66
1320	_emit 0x0F
1321	_emit 0xC7
1322	_emit 0x34
1323	_emit 0x24 /* VMCLEAR [esp] */
1324	jnc success
1325	mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
1326	success:
1327	add esp, 8
1328	}
1329	# endif
1330	return rc;
1331	}
1332	#endif
1333
1334
1335	/**
1336	* Executes VMPTRLD
1337	*
1338	* @returns VBox status code
1339	* @param pVMCS Physical address of VMCS structure
1340	*/
1341	#if RT_INLINE_ASM_EXTERNAL \|\| HC_ARCH_BITS == 64 \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1342	DECLASM(int) VMXActivateVMCS(RTHCPHYS pVMCS);
1343	#else
1344	DECLINLINE(int) VMXActivateVMCS(RTHCPHYS pVMCS)
1345	{
1346	int rc = VINF_SUCCESS;
1347	# if RT_INLINE_ASM_GNU_STYLE
1348	__asm__ __volatile__ (
1349	"push %3 \n\t"
1350	"push %2 \n\t"
1351	".byte 0x0F, 0xC7, 0x34, 0x24 # VMPTRLD [esp] \n\t"
1352	"jnc 1f \n\t"
1353	"movl $"STR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
1354	"1: \n\t"
1355	"add $8, %%esp \n\t"
1356	:"=rm"(rc)
1357	:"0"(VINF_SUCCESS),
1358	"ir"((uint32_t)pVMCS), /* don't allow direct memory reference here, */
1359	"ir"((uint32_t)(pVMCS >> 32)) /* this will not work with -fomit-frame-pointer */
1360	);
1361	# else
1362	__asm
1363	{
1364	push dword ptr [pVMCS+4]
1365	push dword ptr [pVMCS]
1366	_emit 0x0F
1367	_emit 0xC7
1368	_emit 0x34
1369	_emit 0x24 /* VMPTRLD [esp] */
1370	jnc success
1371	mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
1372
1373	success:
1374	add esp, 8
1375	}
1376	# endif
1377	return rc;
1378	}
1379	#endif
1380
1381	/**
1382	* Executes VMPTRST
1383	*
1384	* @returns VBox status code
1385	* @param pVMCS Address that will receive the current pointer
1386	*/
1387	DECLASM(int) VMXGetActivateVMCS(RTHCPHYS *pVMCS);
1388
1389	/**
1390	* Executes VMWRITE
1391	*
1392	* @returns VBox status code
1393	* @param idxField VMCS index
1394	* @param u32Val 32 bits value
1395	*/
1396	#if RT_INLINE_ASM_EXTERNAL \|\| HC_ARCH_BITS == 64 \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1397	DECLASM(int) VMXWriteVMCS32(uint32_t idxField, uint32_t u32Val);
1398	#else
1399	DECLINLINE(int) VMXWriteVMCS32(uint32_t idxField, uint32_t u32Val)
1400	{
1401	int rc = VINF_SUCCESS;
1402	# if RT_INLINE_ASM_GNU_STYLE
1403	__asm__ __volatile__ (
1404	".byte 0x0F, 0x79, 0xC2 # VMWRITE eax, edx \n\t"
1405	"ja 2f \n\t"
1406	"je 1f \n\t"
1407	"movl $"STR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
1408	"jmp 2f \n\t"
1409	"1: \n\t"
1410	"movl $"STR(VERR_VMX_INVALID_VMCS_FIELD)", %0 \n\t"
1411	"2: \n\t"
1412	:"=rm"(rc)
1413	:"0"(VINF_SUCCESS),
1414	"a"(idxField),
1415	"d"(u32Val)
1416	);
1417	# else
1418	__asm
1419	{
1420	push dword ptr [u32Val]
1421	mov eax, [idxField]
1422	_emit 0x0F
1423	_emit 0x79
1424	_emit 0x04
1425	_emit 0x24 /* VMWRITE eax, [esp] */
1426	jnc valid_vmcs
1427	mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
1428	jmp the_end
1429
1430	valid_vmcs:
1431	jnz the_end
1432	mov dword ptr [rc], VERR_VMX_INVALID_VMCS_FIELD
1433	the_end:
1434	add esp, 4
1435	}
1436	# endif
1437	return rc;
1438	}
1439	#endif
1440
1441	/**
1442	* Executes VMWRITE
1443	*
1444	* @returns VBox status code
1445	* @param idxField VMCS index
1446	* @param u64Val 16, 32 or 64 bits value
1447	*/
1448	#if HC_ARCH_BITS == 64 \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1449	DECLASM(int) VMXWriteVMCS64(uint32_t idxField, uint64_t u64Val);
1450	#else
1451	VMMR0DECL(int) VMXWriteVMCS64Ex(PVMCPU pVCpu, uint32_t idxField, uint64_t u64Val);
1452
1453	#define VMXWriteVMCS64(idxField, u64Val) VMXWriteVMCS64Ex(pVCpu, idxField, u64Val)
1454	#endif
1455
1456	#if HC_ARCH_BITS == 64
1457	#define VMXWriteVMCS VMXWriteVMCS64
1458	#else
1459	#define VMXWriteVMCS VMXWriteVMCS32
1460	#endif /* HC_ARCH_BITS == 64 */
1461
1462
1463	/**
1464	* Invalidate a page using invept
1465	* @returns VBox status code
1466	* @param enmFlush Type of flush
1467	* @param pDescriptor Descriptor
1468	*/
1469	DECLASM(int) VMXR0InvEPT(VMX_FLUSH enmFlush, uint64_t *pDescriptor);
1470
1471	/**
1472	* Invalidate a page using invvpid
1473	* @returns VBox status code
1474	* @param enmFlush Type of flush
1475	* @param pDescriptor Descriptor
1476	*/
1477	DECLASM(int) VMXR0InvVPID(VMX_FLUSH enmFlush, uint64_t *pDescriptor);
1478
1479	/**
1480	* Executes VMREAD
1481	*
1482	* @returns VBox status code
1483	* @param idxField VMCS index
1484	* @param pData Ptr to store VM field value
1485	*/
1486	#if RT_INLINE_ASM_EXTERNAL \|\| HC_ARCH_BITS == 64 \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1487	DECLASM(int) VMXReadVMCS32(uint32_t idxField, uint32_t *pData);
1488	#else
1489	DECLINLINE(int) VMXReadVMCS32(uint32_t idxField, uint32_t *pData)
1490	{
1491	int rc = VINF_SUCCESS;
1492	# if RT_INLINE_ASM_GNU_STYLE
1493	__asm__ __volatile__ (
1494	"movl $"STR(VINF_SUCCESS)", %0 \n\t"
1495	".byte 0x0F, 0x78, 0xc2 # VMREAD eax, edx \n\t"
1496	"ja 2f \n\t"
1497	"je 1f \n\t"
1498	"movl $"STR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
1499	"jmp 2f \n\t"
1500	"1: \n\t"
1501	"movl $"STR(VERR_VMX_INVALID_VMCS_FIELD)", %0 \n\t"
1502	"2: \n\t"
1503	:"=&r"(rc),
1504	"=d"(*pData)
1505	:"a"(idxField),
1506	"d"(0)
1507	);
1508	# else
1509	__asm
1510	{
1511	sub esp, 4
1512	mov dword ptr [esp], 0
1513	mov eax, [idxField]
1514	_emit 0x0F
1515	_emit 0x78
1516	_emit 0x04
1517	_emit 0x24 /* VMREAD eax, [esp] */
1518	mov edx, pData
1519	pop dword ptr [edx]
1520	jnc valid_vmcs
1521	mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
1522	jmp the_end
1523
1524	valid_vmcs:
1525	jnz the_end
1526	mov dword ptr [rc], VERR_VMX_INVALID_VMCS_FIELD
1527	the_end:
1528	}
1529	# endif
1530	return rc;
1531	}
1532	#endif
1533
1534	/**
1535	* Executes VMREAD
1536	*
1537	* @returns VBox status code
1538	* @param idxField VMCS index
1539	* @param pData Ptr to store VM field value
1540	*/
1541	#if HC_ARCH_BITS == 64 \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1542	DECLASM(int) VMXReadVMCS64(uint32_t idxField, uint64_t *pData);
1543	#else
1544	DECLINLINE(int) VMXReadVMCS64(uint32_t idxField, uint64_t *pData)
1545	{
1546	int rc;
1547
1548	uint32_t val_hi, val;
1549	rc = VMXReadVMCS32(idxField, &val);
1550	rc \|= VMXReadVMCS32(idxField + 1, &val_hi);
1551	AssertRC(rc);
1552	*pData = RT_MAKE_U64(val, val_hi);
1553	return rc;
1554	}
1555	#endif
1556
1557	#if HC_ARCH_BITS == 64
1558	# define VMXReadVMCS VMXReadVMCS64
1559	#else
1560	# define VMXReadVMCS VMXReadVMCS32
1561	#endif /* HC_ARCH_BITS == 64 */
1562
1563	/**
1564	* Gets the last instruction error value from the current VMCS
1565	*
1566	* @returns error value
1567	*/
1568	DECLINLINE(uint32_t) VMXGetLastError(void)
1569	{
1570	#if HC_ARCH_BITS == 64
1571	uint64_t uLastError = 0;
1572	int rc = VMXReadVMCS(VMX_VMCS32_RO_VM_INSTR_ERROR, &uLastError);
1573	AssertRC(rc);
1574	return (uint32_t)uLastError;
1575
1576	#else /* 32-bit host: */
1577	uint32_t uLastError = 0;
1578	int rc = VMXReadVMCS32(VMX_VMCS32_RO_VM_INSTR_ERROR, &uLastError);
1579	AssertRC(rc);
1580	return uLastError;
1581	#endif
1582	}
1583
1584	#ifdef IN_RING0
1585	VMMR0DECL(int) VMXR0InvalidatePage(PVM pVM, PVMCPU pVCpu, RTGCPTR GCVirt);
1586	VMMR0DECL(int) VMXR0InvalidatePhysPage(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys);
1587	#endif /* IN_RING0 */
1588
1589	/** @} */
1590
1591	#endif
1592

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source: vbox/trunk/include/VBox/hwacc_vmx.h@ 15743

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