hwacc_vmx.h@ 29567

Last change on this file since 29567 was 29250, checked in by vboxsync, 15 years ago
iprt/asm.h: split out asm-math.h, don't include asm-.h from asm.h, don't include asm.h from sup.h. Fixed a couple file headers.
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1	/** @file
2	* HWACCM - VMX Structures and Definitions. (VMM)
3	*/
4
5	/*
6	* Copyright (C) 2006-2007 Oracle Corporation
7	*
8	* This file is part of VirtualBox Open Source Edition (OSE), as
9	* available from http://www.virtualbox.org. This file is free software;
10	* you can redistribute it and/or modify it under the terms of the GNU
11	* General Public License (GPL) as published by the Free Software
12	* Foundation, in version 2 as it comes in the "COPYING" file of the
13	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15	*
16	* The contents of this file may alternatively be used under the terms
17	* of the Common Development and Distribution License Version 1.0
18	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19	* VirtualBox OSE distribution, in which case the provisions of the
20	* CDDL are applicable instead of those of the GPL.
21	*
22	* You may elect to license modified versions of this file under the
23	* terms and conditions of either the GPL or the CDDL or both.
24	*/
25
26	#ifndef ___VBox_vmx_h
27	#define ___VBox_vmx_h
28
29	#include <VBox/types.h>
30	#include <VBox/err.h>
31	#include <VBox/x86.h>
32	#include <iprt/assert.h>
33
34	/** @defgroup grp_vmx vmx Types and Definitions
35	* @ingroup grp_hwaccm
36	* @{
37	*/
38
39	/** @name VMX EPT paging structures
40	* @{
41	*/
42
43	/**
44	* Number of page table entries in the EPT. (PDPTE/PDE/PTE)
45	*/
46	#define EPT_PG_ENTRIES X86_PG_PAE_ENTRIES
47
48	/**
49	* EPT Page Directory Pointer Entry. Bit view.
50	* @todo uint64_t isn't safe for bitfields (gcc pedantic warnings, and IIRC,
51	* this did cause trouble with one compiler/version).
52	*/
53	#pragma pack(1)
54	typedef struct EPTPML4EBITS
55	{
56	/** Present bit. */
57	uint64_t u1Present : 1;
58	/** Writable bit. */
59	uint64_t u1Write : 1;
60	/** Executable bit. */
61	uint64_t u1Execute : 1;
62	/** Reserved (must be 0). */
63	uint64_t u5Reserved : 5;
64	/** Available for software. */
65	uint64_t u4Available : 4;
66	/** Physical address of the next level (PD). Restricted by maximum physical address width of the cpu. */
67	uint64_t u40PhysAddr : 40;
68	/** Availabe for software. */
69	uint64_t u12Available : 12;
70	} EPTPML4EBITS;
71	#pragma pack()
72	AssertCompileSize(EPTPML4EBITS, 8);
73
74	/** Bits 12-51 - - EPT - Physical Page number of the next level. */
75	#define EPT_PML4E_PG_MASK X86_PML4E_PG_MASK_FULL
76	/** The page shift to get the PML4 index. */
77	#define EPT_PML4_SHIFT X86_PML4_SHIFT
78	/** The PML4 index mask (apply to a shifted page address). */
79	#define EPT_PML4_MASK X86_PML4_MASK
80
81	/**
82	* EPT PML4E.
83	*/
84	#pragma pack(1)
85	typedef union EPTPML4E
86	{
87	/** Normal view. */
88	EPTPML4EBITS n;
89	/** Unsigned integer view. */
90	X86PGPAEUINT u;
91	/** 64 bit unsigned integer view. */
92	uint64_t au64[1];
93	/** 32 bit unsigned integer view. */
94	uint32_t au32[2];
95	} EPTPML4E;
96	#pragma pack()
97	/** Pointer to a PML4 table entry. */
98	typedef EPTPML4E *PEPTPML4E;
99	/** Pointer to a const PML4 table entry. */
100	typedef const EPTPML4E *PCEPTPML4E;
101	AssertCompileSize(EPTPML4E, 8);
102
103	/**
104	* EPT PML4 Table.
105	*/
106	#pragma pack(1)
107	typedef struct EPTPML4
108	{
109	EPTPML4E a[EPT_PG_ENTRIES];
110	} EPTPML4;
111	#pragma pack()
112	/** Pointer to an EPT PML4 Table. */
113	typedef EPTPML4 *PEPTPML4;
114	/** Pointer to a const EPT PML4 Table. */
115	typedef const EPTPML4 *PCEPTPML4;
116
117	/**
118	* EPT Page Directory Pointer Entry. Bit view.
119	*/
120	#pragma pack(1)
121	typedef struct EPTPDPTEBITS
122	{
123	/** Present bit. */
124	uint64_t u1Present : 1;
125	/** Writable bit. */
126	uint64_t u1Write : 1;
127	/** Executable bit. */
128	uint64_t u1Execute : 1;
129	/** Reserved (must be 0). */
130	uint64_t u5Reserved : 5;
131	/** Available for software. */
132	uint64_t u4Available : 4;
133	/** Physical address of the next level (PD). Restricted by maximum physical address width of the cpu. */
134	uint64_t u40PhysAddr : 40;
135	/** Availabe for software. */
136	uint64_t u12Available : 12;
137	} EPTPDPTEBITS;
138	#pragma pack()
139	AssertCompileSize(EPTPDPTEBITS, 8);
140
141	/** Bits 12-51 - - EPT - Physical Page number of the next level. */
142	#define EPT_PDPTE_PG_MASK X86_PDPE_PG_MASK_FULL
143	/** The page shift to get the PDPT index. */
144	#define EPT_PDPT_SHIFT X86_PDPT_SHIFT
145	/** The PDPT index mask (apply to a shifted page address). */
146	#define EPT_PDPT_MASK X86_PDPT_MASK_AMD64
147
148	/**
149	* EPT Page Directory Pointer.
150	*/
151	#pragma pack(1)
152	typedef union EPTPDPTE
153	{
154	/** Normal view. */
155	EPTPDPTEBITS n;
156	/** Unsigned integer view. */
157	X86PGPAEUINT u;
158	/** 64 bit unsigned integer view. */
159	uint64_t au64[1];
160	/** 32 bit unsigned integer view. */
161	uint32_t au32[2];
162	} EPTPDPTE;
163	#pragma pack()
164	/** Pointer to an EPT Page Directory Pointer Entry. */
165	typedef EPTPDPTE *PEPTPDPTE;
166	/** Pointer to a const EPT Page Directory Pointer Entry. */
167	typedef const EPTPDPTE *PCEPTPDPTE;
168	AssertCompileSize(EPTPDPTE, 8);
169
170	/**
171	* EPT Page Directory Pointer Table.
172	*/
173	#pragma pack(1)
174	typedef struct EPTPDPT
175	{
176	EPTPDPTE a[EPT_PG_ENTRIES];
177	} EPTPDPT;
178	#pragma pack()
179	/** Pointer to an EPT Page Directory Pointer Table. */
180	typedef EPTPDPT *PEPTPDPT;
181	/** Pointer to a const EPT Page Directory Pointer Table. */
182	typedef const EPTPDPT *PCEPTPDPT;
183
184
185	/**
186	* EPT Page Directory Table Entry. Bit view.
187	*/
188	#pragma pack(1)
189	typedef struct EPTPDEBITS
190	{
191	/** Present bit. */
192	uint64_t u1Present : 1;
193	/** Writable bit. */
194	uint64_t u1Write : 1;
195	/** Executable bit. */
196	uint64_t u1Execute : 1;
197	/** Reserved (must be 0). */
198	uint64_t u4Reserved : 4;
199	/** Big page (must be 0 here). */
200	uint64_t u1Size : 1;
201	/** Available for software. */
202	uint64_t u4Available : 4;
203	/** Physical address of page table. Restricted by maximum physical address width of the cpu. */
204	uint64_t u40PhysAddr : 40;
205	/** Availabe for software. */
206	uint64_t u12Available : 12;
207	} EPTPDEBITS;
208	#pragma pack()
209	AssertCompileSize(EPTPDEBITS, 8);
210
211	/** Bits 12-51 - - EPT - Physical Page number of the next level. */
212	#define EPT_PDE_PG_MASK X86_PDE_PAE_PG_MASK_FULL
213	/** The page shift to get the PD index. */
214	#define EPT_PD_SHIFT X86_PD_PAE_SHIFT
215	/** The PD index mask (apply to a shifted page address). */
216	#define EPT_PD_MASK X86_PD_PAE_MASK
217
218	/**
219	* EPT 2MB Page Directory Table Entry. Bit view.
220	*/
221	#pragma pack(1)
222	typedef struct EPTPDE2MBITS
223	{
224	/** Present bit. */
225	uint64_t u1Present : 1;
226	/** Writable bit. */
227	uint64_t u1Write : 1;
228	/** Executable bit. */
229	uint64_t u1Execute : 1;
230	/** EPT Table Memory Type. MBZ for non-leaf nodes. */
231	uint64_t u3EMT : 3;
232	/** Ignore PAT memory type */
233	uint64_t u1IgnorePAT : 1;
234	/** Big page (must be 1 here). */
235	uint64_t u1Size : 1;
236	/** Available for software. */
237	uint64_t u4Available : 4;
238	/** Reserved (must be 0). */
239	uint64_t u9Reserved : 9;
240	/** Physical address of the 2MB page. Restricted by maximum physical address width of the cpu. */
241	uint64_t u31PhysAddr : 31;
242	/** Availabe for software. */
243	uint64_t u12Available : 12;
244	} EPTPDE2MBITS;
245	#pragma pack()
246	AssertCompileSize(EPTPDE2MBITS, 8);
247
248	/** Bits 21-51 - - EPT - Physical Page number of the next level. */
249	#define EPT_PDE2M_PG_MASK ( 0x000fffffffe00000ULL )
250
251	/**
252	* EPT Page Directory Table Entry.
253	*/
254	#pragma pack(1)
255	typedef union EPTPDE
256	{
257	/** Normal view. */
258	EPTPDEBITS n;
259	/** 2MB view (big). */
260	EPTPDE2MBITS b;
261	/** Unsigned integer view. */
262	X86PGPAEUINT u;
263	/** 64 bit unsigned integer view. */
264	uint64_t au64[1];
265	/** 32 bit unsigned integer view. */
266	uint32_t au32[2];
267	} EPTPDE;
268	#pragma pack()
269	/** Pointer to an EPT Page Directory Table Entry. */
270	typedef EPTPDE *PEPTPDE;
271	/** Pointer to a const EPT Page Directory Table Entry. */
272	typedef const EPTPDE *PCEPTPDE;
273	AssertCompileSize(EPTPDE, 8);
274
275	/**
276	* EPT Page Directory Table.
277	*/
278	#pragma pack(1)
279	typedef struct EPTPD
280	{
281	EPTPDE a[EPT_PG_ENTRIES];
282	} EPTPD;
283	#pragma pack()
284	/** Pointer to an EPT Page Directory Table. */
285	typedef EPTPD *PEPTPD;
286	/** Pointer to a const EPT Page Directory Table. */
287	typedef const EPTPD *PCEPTPD;
288
289
290	/**
291	* EPT Page Table Entry. Bit view.
292	*/
293	#pragma pack(1)
294	typedef struct EPTPTEBITS
295	{
296	/** Present bit. */
297	uint64_t u1Present : 1;
298	/** Writable bit. */
299	uint64_t u1Write : 1;
300	/** Executable bit. */
301	uint64_t u1Execute : 1;
302	/** EPT Table Memory Type. MBZ for non-leaf nodes. */
303	uint64_t u3EMT : 3;
304	/** Ignore PAT memory type */
305	uint64_t u1IgnorePAT : 1;
306	/** Available for software. */
307	uint64_t u5Available : 5;
308	/** Physical address of page. Restricted by maximum physical address width of the cpu. */
309	uint64_t u40PhysAddr : 40;
310	/** Availabe for software. */
311	uint64_t u12Available : 12;
312	} EPTPTEBITS;
313	#pragma pack()
314	AssertCompileSize(EPTPTEBITS, 8);
315
316	/** Bits 12-51 - - EPT - Physical Page number of the next level. */
317	#define EPT_PTE_PG_MASK X86_PTE_PAE_PG_MASK_FULL
318	/** The page shift to get the EPT PTE index. */
319	#define EPT_PT_SHIFT X86_PT_PAE_SHIFT
320	/** The EPT PT index mask (apply to a shifted page address). */
321	#define EPT_PT_MASK X86_PT_PAE_MASK
322
323	/**
324	* EPT Page Table Entry.
325	*/
326	#pragma pack(1)
327	typedef union EPTPTE
328	{
329	/** Normal view. */
330	EPTPTEBITS n;
331	/** Unsigned integer view. */
332	X86PGPAEUINT u;
333	/** 64 bit unsigned integer view. */
334	uint64_t au64[1];
335	/** 32 bit unsigned integer view. */
336	uint32_t au32[2];
337	} EPTPTE;
338	#pragma pack()
339	/** Pointer to an EPT Page Directory Table Entry. */
340	typedef EPTPTE *PEPTPTE;
341	/** Pointer to a const EPT Page Directory Table Entry. */
342	typedef const EPTPTE *PCEPTPTE;
343	AssertCompileSize(EPTPTE, 8);
344
345	/**
346	* EPT Page Table.
347	*/
348	#pragma pack(1)
349	typedef struct EPTPT
350	{
351	EPTPTE a[EPT_PG_ENTRIES];
352	} EPTPT;
353	#pragma pack()
354	/** Pointer to an extended page table. */
355	typedef EPTPT *PEPTPT;
356	/** Pointer to a const extended table. */
357	typedef const EPTPT *PCEPTPT;
358
359	/**
360	* VPID and EPT flush types
361	*/
362	typedef enum
363	{
364	/* Invalidate a specific page. */
365	VMX_FLUSH_PAGE = 0,
366	/* Invalidate one context (VPID or EPT) */
367	VMX_FLUSH_SINGLE_CONTEXT = 1,
368	/* Invalidate all contexts (VPIDs or EPTs) */
369	VMX_FLUSH_ALL_CONTEXTS = 2,
370	/* Invalidate a single VPID context retaining global mappings. */
371	VMX_FLUSH_SINGLE_CONTEXT_WITHOUT_GLOBAL = 3,
372	/** 32bit hackishness. */
373	VMX_FLUSH_32BIT_HACK = 0x7fffffff
374	} VMX_FLUSH;
375	/** @} */
376
377	/** @name MSR load/store elements
378	* @{
379	*/
380	#pragma pack(1)
381	typedef struct
382	{
383	uint32_t u32IndexMSR;
384	uint32_t u32Reserved;
385	uint64_t u64Value;
386	} VMXMSR;
387	#pragma pack()
388	/** Pointer to an MSR load/store element. */
389	typedef VMXMSR *PVMXMSR;
390	/** Pointer to a const MSR load/store element. */
391	typedef const VMXMSR *PCVMXMSR;
392
393	/** @} */
394
395
396	/** @name VT-x capability qword
397	* @{
398	*/
399	#pragma pack(1)
400	typedef union
401	{
402	struct
403	{
404	uint32_t disallowed0;
405	uint32_t allowed1;
406	} n;
407	uint64_t u;
408	} VMX_CAPABILITY;
409	#pragma pack()
410	/** @} */
411
412	/** @name VMX Basic Exit Reasons.
413	* @{
414	*/
415	/** And-mask for setting reserved bits to zero */
416	#define VMX_EFLAGS_RESERVED_0 (~0xffc08028)
417	/** Or-mask for setting reserved bits to 1 */
418	#define VMX_EFLAGS_RESERVED_1 0x00000002
419	/** @} */
420
421	/** @name VMX Basic Exit Reasons.
422	* @{
423	*/
424	/** -1 Invalid exit code */
425	#define VMX_EXIT_INVALID -1
426	/** 0 Exception or non-maskable interrupt (NMI). */
427	#define VMX_EXIT_EXCEPTION 0
428	/** 1 External interrupt. */
429	#define VMX_EXIT_EXTERNAL_IRQ 1
430	/** 2 Triple fault. */
431	#define VMX_EXIT_TRIPLE_FAULT 2
432	/** 3 INIT signal. */
433	#define VMX_EXIT_INIT_SIGNAL 3
434	/** 4 Start-up IPI (SIPI). */
435	#define VMX_EXIT_SIPI 4
436	/** 5 I/O system-management interrupt (SMI). */
437	#define VMX_EXIT_IO_SMI_IRQ 5
438	/** 6 Other SMI. */
439	#define VMX_EXIT_SMI_IRQ 6
440	/** 7 Interrupt window. */
441	#define VMX_EXIT_IRQ_WINDOW 7
442	/** 9 Task switch. */
443	#define VMX_EXIT_TASK_SWITCH 9
444	/** 10 Guest software attempted to execute CPUID. */
445	#define VMX_EXIT_CPUID 10
446	/** 12 Guest software attempted to execute HLT. */
447	#define VMX_EXIT_HLT 12
448	/** 13 Guest software attempted to execute INVD. */
449	#define VMX_EXIT_INVD 13
450	/** 14 Guest software attempted to execute INVPG. */
451	#define VMX_EXIT_INVPG 14
452	/** 15 Guest software attempted to execute RDPMC. */
453	#define VMX_EXIT_RDPMC 15
454	/** 16 Guest software attempted to execute RDTSC. */
455	#define VMX_EXIT_RDTSC 16
456	/** 17 Guest software attempted to execute RSM in SMM. */
457	#define VMX_EXIT_RSM 17
458	/** 18 Guest software executed VMCALL. */
459	#define VMX_EXIT_VMCALL 18
460	/** 19 Guest software executed VMCLEAR. */
461	#define VMX_EXIT_VMCLEAR 19
462	/** 20 Guest software executed VMLAUNCH. */
463	#define VMX_EXIT_VMLAUNCH 20
464	/** 21 Guest software executed VMPTRLD. */
465	#define VMX_EXIT_VMPTRLD 21
466	/** 22 Guest software executed VMPTRST. */
467	#define VMX_EXIT_VMPTRST 22
468	/** 23 Guest software executed VMREAD. */
469	#define VMX_EXIT_VMREAD 23
470	/** 24 Guest software executed VMRESUME. */
471	#define VMX_EXIT_VMRESUME 24
472	/** 25 Guest software executed VMWRITE. */
473	#define VMX_EXIT_VMWRITE 25
474	/** 26 Guest software executed VMXOFF. */
475	#define VMX_EXIT_VMXOFF 26
476	/** 27 Guest software executed VMXON. */
477	#define VMX_EXIT_VMXON 27
478	/** 28 Control-register accesses. */
479	#define VMX_EXIT_CRX_MOVE 28
480	/** 29 Debug-register accesses. */
481	#define VMX_EXIT_DRX_MOVE 29
482	/** 30 I/O instruction. */
483	#define VMX_EXIT_PORT_IO 30
484	/** 31 RDMSR. Guest software attempted to execute RDMSR. */
485	#define VMX_EXIT_RDMSR 31
486	/** 32 WRMSR. Guest software attempted to execute WRMSR. */
487	#define VMX_EXIT_WRMSR 32
488	/** 33 VM-entry failure due to invalid guest state. */
489	#define VMX_EXIT_ERR_INVALID_GUEST_STATE 33
490	/** 34 VM-entry failure due to MSR loading. */
491	#define VMX_EXIT_ERR_MSR_LOAD 34
492	/** 36 Guest software executed MWAIT. */
493	#define VMX_EXIT_MWAIT 36
494	/** 39 Guest software attempted to execute MONITOR. */
495	#define VMX_EXIT_MONITOR 39
496	/** 40 Guest software attempted to execute PAUSE. */
497	#define VMX_EXIT_PAUSE 40
498	/** 41 VM-entry failure due to machine-check. */
499	#define VMX_EXIT_ERR_MACHINE_CHECK 41
500	/** 43 TPR below threshold. Guest software executed MOV to CR8. */
501	#define VMX_EXIT_TPR 43
502	/** 44 APIC access. Guest software attempted to access memory at a physical address on the APIC-access page. */
503	#define VMX_EXIT_APIC_ACCESS 44
504	/** 46 Access to GDTR or IDTR. Guest software attempted to execute LGDT, LIDT, SGDT, or SIDT. */
505	#define VMX_EXIT_XDTR_ACCESS 46
506	/** 47 Access to LDTR or TR. Guest software attempted to execute LLDT, LTR, SLDT, or STR. */
507	#define VMX_EXIT_TR_ACCESS 47
508	/** 48 EPT violation. An attempt to access memory with a guest-physical address was disallowed by the configuration of the EPT paging structures. */
509	#define VMX_EXIT_EPT_VIOLATION 48
510	/** 49 EPT misconfiguration. An attempt to access memory with a guest-physical address encountered a misconfigured EPT paging-structure entry. */
511	#define VMX_EXIT_EPT_MISCONFIG 49
512	/** 50 INVEPT. Guest software attempted to execute INVEPT. */
513	#define VMX_EXIT_INVEPT 50
514	/** 52 VMX-preemption timer expired. The preemption timer counted down to zero. */
515	#define VMX_EXIT_PREEMPTION_TIMER 52
516	/** 53 INVVPID. Guest software attempted to execute INVVPID. */
517	#define VMX_EXIT_INVVPID 53
518	/** 54 WBINVD. Guest software attempted to execute WBINVD. */
519	#define VMX_EXIT_WBINVD 54
520	/** 55 XSETBV. Guest software attempted to execute XSETBV. */
521	#define VMX_EXIT_XSETBV 55
522	/** @} */
523
524
525	/** @name VM Instruction Errors
526	* @{
527	*/
528	/** 1 VMCALL executed in VMX root operation. */
529	#define VMX_ERROR_VMCALL 1
530	/** 2 VMCLEAR with invalid physical address. */
531	#define VMX_ERROR_VMCLEAR_INVALID_PHYS_ADDR 2
532	/** 3 VMCLEAR with VMXON pointer. */
533	#define VMX_ERROR_VMCLEAR_INVALID_VMXON_PTR 3
534	/** 4 VMLAUNCH with non-clear VMCS. */
535	#define VMX_ERROR_VMLAUCH_NON_CLEAR_VMCS 4
536	/** 5 VMRESUME with non-launched VMCS. */
537	#define VMX_ERROR_VMRESUME_NON_LAUNCHED_VMCS 5
538	/** 6 VMRESUME with a corrupted VMCS (indicates corruption of the current VMCS). */
539	#define VMX_ERROR_VMRESUME_CORRUPTED_VMCS 6
540	/** 7 VM entry with invalid control field(s). */
541	#define VMX_ERROR_VMENTRY_INVALID_CONTROL_FIELDS 7
542	/** 8 VM entry with invalid host-state field(s). */
543	#define VMX_ERROR_VMENTRY_INVALID_HOST_STATE 8
544	/** 9 VMPTRLD with invalid physical address. */
545	#define VMX_ERROR_VMPTRLD_INVALID_PHYS_ADDR 9
546	/** 10 VMPTRLD with VMXON pointer. */
547	#define VMX_ERROR_VMPTRLD_VMXON_PTR 10
548	/** 11 VMPTRLD with incorrect VMCS revision identifier. */
549	#define VMX_ERROR_VMPTRLD_WRONG_VMCS_REVISION 11
550	/** 12 VMREAD/VMWRITE from/to unsupported VMCS component. */
551	#define VMX_ERROR_VMREAD_INVALID_COMPONENT 12
552	#define VMX_ERROR_VMWRITE_INVALID_COMPONENT VMX_ERROR_VMREAD_INVALID_COMPONENT
553	/** 13 VMWRITE to read-only VMCS component. */
554	#define VMX_ERROR_VMWRITE_READONLY_COMPONENT 13
555	/** 15 VMXON executed in VMX root operation. */
556	#define VMX_ERROR_VMXON_IN_VMX_ROOT_OP 15
557	/** 16 VM entry with invalid executive-VMCS pointer. */
558	#define VMX_ERROR_VMENTRY_INVALID_VMCS_EXEC_PTR 16
559	/** 17 VM entry with non-launched executive VMCS. */
560	#define VMX_ERROR_VMENTRY_NON_LAUNCHED_EXEC_VMCS 17
561	/** 18 VM entry with executive-VMCS pointer not VMXON pointer. */
562	#define VMX_ERROR_VMENTRY_EXEC_VMCS_PTR 18
563	/** 19 VMCALL with non-clear VMCS. */
564	#define VMX_ERROR_VMCALL_NON_CLEAR_VMCS 19
565	/** 20 VMCALL with invalid VM-exit control fields. */
566	#define VMX_ERROR_VMCALL_INVALID_VMEXIT_FIELDS 20
567	/** 22 VMCALL with incorrect MSEG revision identifier. */
568	#define VMX_ERROR_VMCALL_INVALID_MSEG_REVISION 22
569	/** 23 VMXOFF under dual-monitor treatment of SMIs and SMM. */
570	#define VMX_ERROR_VMXOFF_DUAL_MONITOR 23
571	/** 24 VMCALL with invalid SMM-monitor features. */
572	#define VMX_ERROR_VMCALL_INVALID_SMM_MONITOR 24
573	/** 25 VM entry with invalid VM-execution control fields in executive VMCS. */
574	#define VMX_ERROR_VMENTRY_INVALID_VM_EXEC_CTRL 25
575	/** 26 VM entry with events blocked by MOV SS. */
576	#define VMX_ERROR_VMENTRY_MOV_SS 26
577	/** 26 Invalid operand to INVEPT/INVVPID. */
578	#define VMX_ERROR_INVEPTVPID_INVALID_OPERAND 28
579
580	/** @} */
581
582
583	/** @name VMX MSRs - Basic VMX information.
584	* @{
585	*/
586	/** VMCS revision identifier used by the processor. */
587	#define MSR_IA32_VMX_BASIC_INFO_VMCS_ID(a) (a & 0x7FFFFFFF)
588	/** Size of the VMCS. */
589	#define MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(a) ((a >> 32ULL) & 0xFFF)
590	/** Width of physical address used for the VMCS.
591	* 0 -> limited to the available amount of physical ram
592	* 1 -> within the first 4 GB
593	*/
594	#define MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(a) ((a >> 48ULL) & 1)
595	/** Whether the processor supports the dual-monitor treatment of system-management interrupts and system-management code. (always 1) */
596	#define MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(a) ((a >> 49ULL) & 1)
597	/** Memory type that must be used for the VMCS. */
598	#define MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(a) ((a >> 50ULL) & 0xF)
599	/** @} */
600
601
602	/** @name VMX MSRs - Misc VMX info.
603	* @{
604	*/
605	/** Relationship between the preemption timer and tsc; count down every time bit x of the tsc changes. */
606	#define MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(a) (a & 0x1f)
607	/** Activity states supported by the implementation. */
608	#define MSR_IA32_VMX_MISC_ACTIVITY_STATES(a) ((a >> 6ULL) & 0x7)
609	/** Number of CR3 target values supported by the processor. (0-256) */
610	#define MSR_IA32_VMX_MISC_CR3_TARGET(a) ((a >> 16ULL) & 0x1FF)
611	/** Maximum nr of MSRs in the VMCS. (N+1)512. /
612	#define MSR_IA32_VMX_MISC_MAX_MSR(a) ((((a >> 25ULL) & 0x7) + 1) * 512)
613	/** MSEG revision identifier used by the processor. */
614	#define MSR_IA32_VMX_MISC_MSEG_ID(a) (a >> 32ULL)
615	/** @} */
616
617
618	/** @name VMX MSRs - VMCS enumeration field info
619	* @{
620	*/
621	/** Highest field index. */
622	#define MSR_IA32_VMX_VMCS_ENUM_HIGHEST_INDEX(a) ((a >> 1ULL) & 0x1FF)
623
624	/** @} */
625
626
627	/** @name MSR_IA32_VMX_EPT_CAPS; EPT capabilities MSR
628	* @{
629	*/
630	#define MSR_IA32_VMX_EPT_CAPS_RWX_X_ONLY RT_BIT_64(0)
631	#define MSR_IA32_VMX_EPT_CAPS_RWX_W_ONLY RT_BIT_64(1)
632	#define MSR_IA32_VMX_EPT_CAPS_RWX_WX_ONLY RT_BIT_64(2)
633	#define MSR_IA32_VMX_EPT_CAPS_GAW_21_BITS RT_BIT_64(3)
634	#define MSR_IA32_VMX_EPT_CAPS_GAW_30_BITS RT_BIT_64(4)
635	#define MSR_IA32_VMX_EPT_CAPS_GAW_39_BITS RT_BIT_64(5)
636	#define MSR_IA32_VMX_EPT_CAPS_GAW_48_BITS RT_BIT_64(6)
637	#define MSR_IA32_VMX_EPT_CAPS_GAW_57_BITS RT_BIT_64(7)
638	#define MSR_IA32_VMX_EPT_CAPS_EMT_UC RT_BIT_64(8)
639	#define MSR_IA32_VMX_EPT_CAPS_EMT_WC RT_BIT_64(9)
640	#define MSR_IA32_VMX_EPT_CAPS_EMT_WT RT_BIT_64(12)
641	#define MSR_IA32_VMX_EPT_CAPS_EMT_WP RT_BIT_64(13)
642	#define MSR_IA32_VMX_EPT_CAPS_EMT_WB RT_BIT_64(14)
643	#define MSR_IA32_VMX_EPT_CAPS_SP_21_BITS RT_BIT_64(16)
644	#define MSR_IA32_VMX_EPT_CAPS_SP_30_BITS RT_BIT_64(17)
645	#define MSR_IA32_VMX_EPT_CAPS_SP_39_BITS RT_BIT_64(18)
646	#define MSR_IA32_VMX_EPT_CAPS_SP_48_BITS RT_BIT_64(19)
647	#define MSR_IA32_VMX_EPT_CAPS_INVEPT RT_BIT_64(20)
648	#define MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV RT_BIT_64(24)
649	#define MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT RT_BIT_64(25)
650	#define MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL RT_BIT_64(26)
651	#define MSR_IA32_VMX_EPT_CAPS_INVVPID RT_BIT_64(32)
652	#define MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV RT_BIT_64(40)
653	#define MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT RT_BIT_64(41)
654	#define MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL RT_BIT_64(42)
655	#define MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT_GLOBAL RT_BIT_64(43)
656
657	/** @} */
658
659	/** @name Extended Page Table Pointer (EPTP)
660	* @{
661	*/
662	/** Uncachable EPT paging structure memory type. */
663	#define VMX_EPT_MEMTYPE_UC 0
664	/** Write-back EPT paging structure memory type. */
665	#define VMX_EPT_MEMTYPE_WB 6
666	/** Shift value to get the EPT page walk length (bits 5-3) */
667	#define VMX_EPT_PAGE_WALK_LENGTH_SHIFT 3
668	/** Mask value to get the EPT page walk length (bits 5-3) */
669	#define VMX_EPT_PAGE_WALK_LENGTH_MASK 7
670	/** Default EPT page walk length */
671	#define VMX_EPT_PAGE_WALK_LENGTH_DEFAULT 3
672	/** @} */
673
674
675	/** @name VMCS field encoding - 16 bits guest fields
676	* @{
677	*/
678	#define VMX_VMCS16_GUEST_FIELD_VPID 0x0
679	#define VMX_VMCS16_GUEST_FIELD_ES 0x800
680	#define VMX_VMCS16_GUEST_FIELD_CS 0x802
681	#define VMX_VMCS16_GUEST_FIELD_SS 0x804
682	#define VMX_VMCS16_GUEST_FIELD_DS 0x806
683	#define VMX_VMCS16_GUEST_FIELD_FS 0x808
684	#define VMX_VMCS16_GUEST_FIELD_GS 0x80A
685	#define VMX_VMCS16_GUEST_FIELD_LDTR 0x80C
686	#define VMX_VMCS16_GUEST_FIELD_TR 0x80E
687	/** @} */
688
689	/** @name VMCS field encoding - 16 bits host fields
690	* @{
691	*/
692	#define VMX_VMCS16_HOST_FIELD_ES 0xC00
693	#define VMX_VMCS16_HOST_FIELD_CS 0xC02
694	#define VMX_VMCS16_HOST_FIELD_SS 0xC04
695	#define VMX_VMCS16_HOST_FIELD_DS 0xC06
696	#define VMX_VMCS16_HOST_FIELD_FS 0xC08
697	#define VMX_VMCS16_HOST_FIELD_GS 0xC0A
698	#define VMX_VMCS16_HOST_FIELD_TR 0xC0C
699	/** @} */
700
701	/** @name VMCS field encoding - 64 bits host fields
702	* @{
703	*/
704	#define VMX_VMCS_HOST_FIELD_PAT_FULL 0x2C00
705	#define VMX_VMCS_HOST_FIELD_PAT_HIGH 0x2C01
706	#define VMX_VMCS_HOST_FIELD_EFER_FULL 0x2C02
707	#define VMX_VMCS_HOST_FIELD_EFER_HIGH 0x2C03
708	#define VMX_VMCS_HOST_PERF_GLOBAL_CTRL_FULL 0x2C04 /*< MSR IA32_PERF_GLOBAL_CTRL /
709	#define VMX_VMCS_HOST_PERF_GLOBAL_CTRL_HIGH 0x2C05 /*< MSR IA32_PERF_GLOBAL_CTRL /
710	/** @} */
711
712
713	/** @name VMCS field encoding - 64 Bits control fields
714	* @{
715	*/
716	#define VMX_VMCS_CTRL_IO_BITMAP_A_FULL 0x2000
717	#define VMX_VMCS_CTRL_IO_BITMAP_A_HIGH 0x2001
718	#define VMX_VMCS_CTRL_IO_BITMAP_B_FULL 0x2002
719	#define VMX_VMCS_CTRL_IO_BITMAP_B_HIGH 0x2003
720
721	/* Optional */
722	#define VMX_VMCS_CTRL_MSR_BITMAP_FULL 0x2004
723	#define VMX_VMCS_CTRL_MSR_BITMAP_HIGH 0x2005
724
725	#define VMX_VMCS_CTRL_VMEXIT_MSR_STORE_FULL 0x2006
726	#define VMX_VMCS_CTRL_VMEXIT_MSR_STORE_HIGH 0x2007
727	#define VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_FULL 0x2008
728	#define VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_HIGH 0x2009
729
730	#define VMX_VMCS_CTRL_VMENTRY_MSR_LOAD_FULL 0x200A
731	#define VMX_VMCS_CTRL_VMENTRY_MSR_LOAD_HIGH 0x200B
732
733	#define VMX_VMCS_CTRL_EXEC_VMCS_PTR_FULL 0x200C
734	#define VMX_VMCS_CTRL_EXEC_VMCS_PTR_HIGH 0x200D
735
736	#define VMX_VMCS_CTRL_TSC_OFFSET_FULL 0x2010
737	#define VMX_VMCS_CTRL_TSC_OFFSET_HIGH 0x2011
738
739	/** Optional (VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW) */
740	#define VMX_VMCS_CTRL_VAPIC_PAGEADDR_FULL 0x2012
741	#define VMX_VMCS_CTRL_VAPIC_PAGEADDR_HIGH 0x2013
742
743	/** Optional (VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC) */
744	#define VMX_VMCS_CTRL_APIC_ACCESSADDR_FULL 0x2014
745	#define VMX_VMCS_CTRL_APIC_ACCESSADDR_HIGH 0x2015
746
747	/** Extended page table pointer. */
748	#define VMX_VMCS_CTRL_EPTP_FULL 0x201a
749	#define VMX_VMCS_CTRL_EPTP_HIGH 0x201b
750
751	/** VM-exit phyiscal address. */
752	#define VMX_VMCS_EXIT_PHYS_ADDR_FULL 0x2400
753	#define VMX_VMCS_EXIT_PHYS_ADDR_HIGH 0x2401
754	/** @} */
755
756
757	/** @name VMCS field encoding - 64 Bits guest fields
758	* @{
759	*/
760	#define VMX_VMCS_GUEST_LINK_PTR_FULL 0x2800
761	#define VMX_VMCS_GUEST_LINK_PTR_HIGH 0x2801
762	#define VMX_VMCS_GUEST_DEBUGCTL_FULL 0x2802 /*< MSR IA32_DEBUGCTL /
763	#define VMX_VMCS_GUEST_DEBUGCTL_HIGH 0x2803 /*< MSR IA32_DEBUGCTL /
764	#define VMX_VMCS_GUEST_PAT_FULL 0x2804
765	#define VMX_VMCS_GUEST_PAT_HIGH 0x2805
766	#define VMX_VMCS_GUEST_EFER_FULL 0x2806
767	#define VMX_VMCS_GUEST_EFER_HIGH 0x2807
768	#define VMX_VMCS_GUEST_PERF_GLOBAL_CTRL_FULL 0x2808 /*< MSR IA32_PERF_GLOBAL_CTRL /
769	#define VMX_VMCS_GUEST_PERF_GLOBAL_CTRL_HIGH 0x2809 /*< MSR IA32_PERF_GLOBAL_CTRL /
770	#define VMX_VMCS_GUEST_PDPTR0_FULL 0x280A
771	#define VMX_VMCS_GUEST_PDPTR0_HIGH 0x280B
772	#define VMX_VMCS_GUEST_PDPTR1_FULL 0x280C
773	#define VMX_VMCS_GUEST_PDPTR1_HIGH 0x280D
774	#define VMX_VMCS_GUEST_PDPTR2_FULL 0x280E
775	#define VMX_VMCS_GUEST_PDPTR2_HIGH 0x280F
776	#define VMX_VMCS_GUEST_PDPTR3_FULL 0x2810
777	#define VMX_VMCS_GUEST_PDPTR3_HIGH 0x2811
778	/** @} */
779
780
781	/** @name VMCS field encoding - 32 Bits control fields
782	* @{
783	*/
784	#define VMX_VMCS_CTRL_PIN_EXEC_CONTROLS 0x4000
785	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS 0x4002
786	#define VMX_VMCS_CTRL_EXCEPTION_BITMAP 0x4004
787	#define VMX_VMCS_CTRL_PAGEFAULT_ERROR_MASK 0x4006
788	#define VMX_VMCS_CTRL_PAGEFAULT_ERROR_MATCH 0x4008
789	#define VMX_VMCS_CTRL_CR3_TARGET_COUNT 0x400A
790	#define VMX_VMCS_CTRL_EXIT_CONTROLS 0x400C
791	#define VMX_VMCS_CTRL_EXIT_MSR_STORE_COUNT 0x400E
792	#define VMX_VMCS_CTRL_EXIT_MSR_LOAD_COUNT 0x4010
793	#define VMX_VMCS_CTRL_ENTRY_CONTROLS 0x4012
794	#define VMX_VMCS_CTRL_ENTRY_MSR_LOAD_COUNT 0x4014
795	#define VMX_VMCS_CTRL_ENTRY_IRQ_INFO 0x4016
796	#define VMX_VMCS_CTRL_ENTRY_EXCEPTION_ERRCODE 0x4018
797	#define VMX_VMCS_CTRL_ENTRY_INSTR_LENGTH 0x401A
798	/** This field exists only on processors that support the 1-setting of the use TPR shadow VM-execution control. */
799	#define VMX_VMCS_CTRL_TPR_THRESHOLD 0x401C
800	/** This field exists only on processors that support the 1-setting of the activate secondary controls VM-execution control. */
801	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS2 0x401E
802	/** @} */
803
804
805	/** @name VMX_VMCS_CTRL_PIN_EXEC_CONTROLS
806	* @{
807	*/
808	/** External interrupts cause VM exits if set; otherwise dispatched through the guest's IDT. */
809	#define VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT RT_BIT(0)
810	/** Non-maskable interrupts cause VM exits if set; otherwise dispatched through the guest's IDT. */
811	#define VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT RT_BIT(3)
812	/** Virtual NMIs. */
813	#define VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI RT_BIT(5)
814	/** Activate VMX preemption timer. */
815	#define VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER RT_BIT(6)
816	/* All other bits are reserved and must be set according to MSR IA32_VMX_PROCBASED_CTLS. */
817	/** @} */
818
819	/** @name VMX_VMCS_CTRL_PROC_EXEC_CONTROLS
820	* @{
821	*/
822	/** VM Exit as soon as RFLAGS.IF=1 and no blocking is active. */
823	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT RT_BIT(2)
824	/** Use timestamp counter offset. */
825	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET RT_BIT(3)
826	/** VM Exit when executing the HLT instruction. */
827	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT RT_BIT(7)
828	/** VM Exit when executing the INVLPG instruction. */
829	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT RT_BIT(9)
830	/** VM Exit when executing the MWAIT instruction. */
831	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT RT_BIT(10)
832	/** VM Exit when executing the RDPMC instruction. */
833	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT RT_BIT(11)
834	/** VM Exit when executing the RDTSC instruction. */
835	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT RT_BIT(12)
836	/** VM Exit when executing the MOV to CR3 instruction. (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
837	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT RT_BIT(15)
838	/** VM Exit when executing the MOV from CR3 instruction. (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
839	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT RT_BIT(16)
840	/** VM Exit on CR8 loads. */
841	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT RT_BIT(19)
842	/** VM Exit on CR8 stores. */
843	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT RT_BIT(20)
844	/** Use TPR shadow. */
845	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW RT_BIT(21)
846	/** VM Exit when virtual nmi blocking is disabled. */
847	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT RT_BIT(22)
848	/** VM Exit when executing a MOV DRx instruction. */
849	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT RT_BIT(23)
850	/** VM Exit when executing IO instructions. */
851	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT RT_BIT(24)
852	/** Use IO bitmaps. */
853	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS RT_BIT(25)
854	/** Monitor trap flag. */
855	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG RT_BIT(27)
856	/** Use MSR bitmaps. */
857	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS RT_BIT(28)
858	/** VM Exit when executing the MONITOR instruction. */
859	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT RT_BIT(29)
860	/** VM Exit when executing the PAUSE instruction. */
861	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT RT_BIT(30)
862	/** Determines whether the secondary processor based VM-execution controls are used. */
863	#define VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL RT_BIT(31)
864	/** @} */
865
866	/** @name VMX_VMCS_CTRL_PROC_EXEC_CONTROLS2
867	* @{
868	*/
869	/** Virtualize APIC access. */
870	#define VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC RT_BIT(0)
871	/** EPT supported/enabled. */
872	#define VMX_VMCS_CTRL_PROC_EXEC2_EPT RT_BIT(1)
873	/** Descriptor table instructions cause VM-exits. */
874	#define VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT RT_BIT(2)
875	/** RDTSCP causes a VM-exit. */
876	#define VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP_EXIT RT_BIT(3)
877	/** Virtualize x2APIC mode. */
878	#define VMX_VMCS_CTRL_PROC_EXEC2_X2APIC RT_BIT(4)
879	/** VPID supported/enabled. */
880	#define VMX_VMCS_CTRL_PROC_EXEC2_VPID RT_BIT(5)
881	/** VM Exit when executing the WBINVD instruction. */
882	#define VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT RT_BIT(6)
883	/** Unrestricted guest execution. */
884	#define VMX_VMCS_CTRL_PROC_EXEC2_REAL_MODE RT_BIT(7)
885	/** A specified nr of pause loops cause a VM-exit. */
886	#define VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT RT_BIT(10)
887	/** @} */
888
889
890	/** @name VMX_VMCS_CTRL_ENTRY_CONTROLS
891	* @{
892	*/
893	/** Load guest debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
894	#define VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG RT_BIT(2)
895	/** 64 bits guest mode. Must be 0 for CPUs that don't support AMD64. */
896	#define VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE RT_BIT(9)
897	/** In SMM mode after VM-entry. */
898	#define VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM RT_BIT(10)
899	/** Disable dual treatment of SMI and SMM; must be zero for VM-entry outside of SMM. */
900	#define VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON RT_BIT(11)
901	/** This control determines whether the guest IA32_PERF_GLOBAL_CTRL MSR is loaded on VM entry. */
902	#define VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR RT_BIT(13)
903	/** This control determines whether the guest IA32_PAT MSR is loaded on VM entry. */
904	#define VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR RT_BIT(14)
905	/** This control determines whether the guest IA32_EFER MSR is loaded on VM entry. */
906	#define VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR RT_BIT(15)
907	/** @} */
908
909
910	/** @name VMX_VMCS_CTRL_EXIT_CONTROLS
911	* @{
912	*/
913	/** Save guest debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
914	#define VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG RT_BIT(2)
915	/** Return to long mode after a VM-exit. */
916	#define VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64 RT_BIT(9)
917	/** This control determines whether the IA32_PERF_GLOBAL_CTRL MSR is loaded on VM exit. */
918	#define VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_PERF_MSR RT_BIT(12)
919	/** Acknowledge external interrupts with the irq controller if one caused a VM-exit. */
920	#define VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ RT_BIT(15)
921	/** This control determines whether the guest IA32_PAT MSR is saved on VM exit. */
922	#define VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR RT_BIT(18)
923	/** This control determines whether the host IA32_PAT MSR is loaded on VM exit. */
924	#define VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR RT_BIT(19)
925	/** This control determines whether the guest IA32_EFER MSR is saved on VM exit. */
926	#define VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR RT_BIT(20)
927	/** This control determines whether the host IA32_EFER MSR is loaded on VM exit. */
928	#define VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR RT_BIT(21)
929	/** This control determines whether the value of the VMX preemption timer is saved on VM exit. */
930	#define VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER RT_BIT(22)
931	/** @} */
932
933	/** @name VMCS field encoding - 32 Bits read-only fields
934	* @{
935	*/
936	#define VMX_VMCS32_RO_VM_INSTR_ERROR 0x4400
937	#define VMX_VMCS32_RO_EXIT_REASON 0x4402
938	#define VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO 0x4404
939	#define VMX_VMCS32_RO_EXIT_INTERRUPTION_ERRCODE 0x4406
940	#define VMX_VMCS32_RO_IDT_INFO 0x4408
941	#define VMX_VMCS32_RO_IDT_ERRCODE 0x440A
942	#define VMX_VMCS32_RO_EXIT_INSTR_LENGTH 0x440C
943	#define VMX_VMCS32_RO_EXIT_INSTR_INFO 0x440E
944	/** @} */
945
946	/** @name VMX_VMCS_RO_EXIT_INTERRUPTION_INFO
947	* @{
948	*/
949	#define VMX_EXIT_INTERRUPTION_INFO_VECTOR(a) (a & 0xff)
950	#define VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT 8
951	#define VMX_EXIT_INTERRUPTION_INFO_TYPE(a) ((a >> VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT) & 7)
952	#define VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID RT_BIT(11)
953	#define VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID(a) (a & VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID)
954	#define VMX_EXIT_INTERRUPTION_INFO_NMI_UNBLOCK(a) (a & RT_BIT(12))
955	#define VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT 31
956	#define VMX_EXIT_INTERRUPTION_INFO_VALID(a) (a & RT_BIT(31))
957	/** Construct an irq event injection value from the exit interruption info value (same except that bit 12 is reserved). */
958	#define VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(a) (a & ~RT_BIT(12))
959	/** @} */
960
961	/** @name VMX_VMCS_RO_EXIT_INTERRUPTION_INFO_TYPE
962	* @{
963	*/
964	#define VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT 0
965	#define VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI 2
966	#define VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT 3
967	#define VMX_EXIT_INTERRUPTION_INFO_TYPE_SW 4 /*< int xx /
968	#define VMX_EXIT_INTERRUPTION_INFO_TYPE_DBEXCPT 5 /*< Why are we getting this one?? /
969	#define VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT 6
970	/** @} */
971
972
973	/** @name VMCS field encoding - 32 Bits guest state fields
974	* @{
975	*/
976	#define VMX_VMCS32_GUEST_ES_LIMIT 0x4800
977	#define VMX_VMCS32_GUEST_CS_LIMIT 0x4802
978	#define VMX_VMCS32_GUEST_SS_LIMIT 0x4804
979	#define VMX_VMCS32_GUEST_DS_LIMIT 0x4806
980	#define VMX_VMCS32_GUEST_FS_LIMIT 0x4808
981	#define VMX_VMCS32_GUEST_GS_LIMIT 0x480A
982	#define VMX_VMCS32_GUEST_LDTR_LIMIT 0x480C
983	#define VMX_VMCS32_GUEST_TR_LIMIT 0x480E
984	#define VMX_VMCS32_GUEST_GDTR_LIMIT 0x4810
985	#define VMX_VMCS32_GUEST_IDTR_LIMIT 0x4812
986	#define VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS 0x4814
987	#define VMX_VMCS32_GUEST_CS_ACCESS_RIGHTS 0x4816
988	#define VMX_VMCS32_GUEST_SS_ACCESS_RIGHTS 0x4818
989	#define VMX_VMCS32_GUEST_DS_ACCESS_RIGHTS 0x481A
990	#define VMX_VMCS32_GUEST_FS_ACCESS_RIGHTS 0x481C
991	#define VMX_VMCS32_GUEST_GS_ACCESS_RIGHTS 0x481E
992	#define VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS 0x4820
993	#define VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS 0x4822
994	#define VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE 0x4824
995	#define VMX_VMCS32_GUEST_ACTIVITY_STATE 0x4826
996	#define VMX_VMCS32_GUEST_SYSENTER_CS 0x482A /*< MSR IA32_SYSENTER_CS /
997	#define VMX_VMCS32_GUEST_PREEMPTION_TIMER_VALUE 0x482E
998	/** @} */
999
1000
1001	/** @name VMX_VMCS_GUEST_ACTIVITY_STATE
1002	* @{
1003	*/
1004	/** The logical processor is active. */
1005	#define VMX_CMS_GUEST_ACTIVITY_ACTIVE 0x0
1006	/** The logical processor is inactive, because executed a HLT instruction. */
1007	#define VMX_CMS_GUEST_ACTIVITY_HLT 0x1
1008	/** The logical processor is inactive, because of a triple fault or other serious error. */
1009	#define VMX_CMS_GUEST_ACTIVITY_SHUTDOWN 0x2
1010	/** The logical processor is inactive, because it's waiting for a startup-IPI */
1011	#define VMX_CMS_GUEST_ACTIVITY_SIPI_WAIT 0x3
1012	/** @} */
1013
1014
1015	/** @name VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE
1016	* @{
1017	*/
1018	#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_STI RT_BIT(0)
1019	#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_MOVSS RT_BIT(1)
1020	#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_SMI RT_BIT(2)
1021	#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_NMI RT_BIT(3)
1022	/** @} */
1023
1024
1025	/** @name VMCS field encoding - 32 Bits host state fields
1026	* @{
1027	*/
1028	#define VMX_VMCS32_HOST_SYSENTER_CS 0x4C00
1029	/** @} */
1030
1031	/** @name Natural width control fields
1032	* @{
1033	*/
1034	#define VMX_VMCS_CTRL_CR0_MASK 0x6000
1035	#define VMX_VMCS_CTRL_CR4_MASK 0x6002
1036	#define VMX_VMCS_CTRL_CR0_READ_SHADOW 0x6004
1037	#define VMX_VMCS_CTRL_CR4_READ_SHADOW 0x6006
1038	#define VMX_VMCS_CTRL_CR3_TARGET_VAL0 0x6008
1039	#define VMX_VMCS_CTRL_CR3_TARGET_VAL1 0x600A
1040	#define VMX_VMCS_CTRL_CR3_TARGET_VAL2 0x600C
1041	#define VMX_VMCS_CTRL_CR3_TARGET_VAL31 0x600E
1042	/** @} */
1043
1044
1045	/** @name Natural width read-only data fields
1046	* @{
1047	*/
1048	#define VMX_VMCS_RO_EXIT_QUALIFICATION 0x6400
1049	#define VMX_VMCS_RO_IO_RCX 0x6402
1050	#define VMX_VMCS_RO_IO_RSX 0x6404
1051	#define VMX_VMCS_RO_IO_RDI 0x6406
1052	#define VMX_VMCS_RO_IO_RIP 0x6408
1053	#define VMX_VMCS_EXIT_GUEST_LINEAR_ADDR 0x640A
1054	/** @} */
1055
1056
1057	/** @name VMX_VMCS_RO_EXIT_QUALIFICATION
1058	* @{
1059	*/
1060	/** 0-2: Debug register number */
1061	#define VMX_EXIT_QUALIFICATION_DRX_REGISTER(a) (a & 7)
1062	/** 3: Reserved; cleared to 0. */
1063	#define VMX_EXIT_QUALIFICATION_DRX_RES1(a) ((a >> 3) & 1)
1064	/** 4: Direction of move (0 = write, 1 = read) */
1065	#define VMX_EXIT_QUALIFICATION_DRX_DIRECTION(a) ((a >> 4) & 1)
1066	/** 5-7: Reserved; cleared to 0. */
1067	#define VMX_EXIT_QUALIFICATION_DRX_RES2(a) ((a >> 5) & 7)
1068	/** 8-11: General purpose register number. */
1069	#define VMX_EXIT_QUALIFICATION_DRX_GENREG(a) ((a >> 8) & 0xF)
1070	/** Rest: reserved. */
1071	/** @} */
1072
1073	/** @name VMX_EXIT_QUALIFICATION_DRX_DIRECTION values
1074	* @{
1075	*/
1076	#define VMX_EXIT_QUALIFICATION_DRX_DIRECTION_WRITE 0
1077	#define VMX_EXIT_QUALIFICATION_DRX_DIRECTION_READ 1
1078	/** @} */
1079
1080
1081
1082	/** @name CRx accesses
1083	* @{
1084	*/
1085	/** 0-3: Control register number (0 for CLTS & LMSW) */
1086	#define VMX_EXIT_QUALIFICATION_CRX_REGISTER(a) (a & 0xF)
1087	/** 4-5: Access type. */
1088	#define VMX_EXIT_QUALIFICATION_CRX_ACCESS(a) ((a >> 4) & 3)
1089	/** 6: LMSW operand type */
1090	#define VMX_EXIT_QUALIFICATION_CRX_LMSW_OP(a) ((a >> 6) & 1)
1091	/** 7: Reserved; cleared to 0. */
1092	#define VMX_EXIT_QUALIFICATION_CRX_RES1(a) ((a >> 7) & 1)
1093	/** 8-11: General purpose register number (0 for CLTS & LMSW). */
1094	#define VMX_EXIT_QUALIFICATION_CRX_GENREG(a) ((a >> 8) & 0xF)
1095	/** 12-15: Reserved; cleared to 0. */
1096	#define VMX_EXIT_QUALIFICATION_CRX_RES2(a) ((a >> 12) & 0xF)
1097	/** 16-31: LMSW source data (else 0). */
1098	#define VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(a) ((a >> 16) & 0xFFFF)
1099	/** Rest: reserved. */
1100	/** @} */
1101
1102	/** @name VMX_EXIT_QUALIFICATION_CRX_ACCESS
1103	* @{
1104	*/
1105	#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_WRITE 0
1106	#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_READ 1
1107	#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_CLTS 2
1108	#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_LMSW 3
1109	/** @} */
1110
1111	/** @name VMX_EXIT_QUALIFICATION_TASK_SWITCH
1112	* @{
1113	*/
1114	#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_SELECTOR(a) (a & 0xffff)
1115	#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE(a) ((a >> 30)& 0x3)
1116	/** Task switch caused by a call instruction. */
1117	#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE_CALL 0
1118	/** Task switch caused by an iret instruction. */
1119	#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE_IRET 1
1120	/** Task switch caused by a jmp instruction. */
1121	#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE_JMP 2
1122	/** Task switch caused by an interrupt gate. */
1123	#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE_IDT 3
1124
1125	/** @} */
1126
1127
1128	/** @name VMX_EXIT_EPT_VIOLATION
1129	* @{
1130	*/
1131	/** Set if the violation was caused by a data read. */
1132	#define VMX_EXIT_QUALIFICATION_EPT_DATA_READ RT_BIT(0)
1133	/** Set if the violation was caused by a data write. */
1134	#define VMX_EXIT_QUALIFICATION_EPT_DATA_WRITE RT_BIT(1)
1135	/** Set if the violation was caused by an insruction fetch. */
1136	#define VMX_EXIT_QUALIFICATION_EPT_INSTR_FETCH RT_BIT(2)
1137	/** AND of the present bit of all EPT structures. */
1138	#define VMX_EXIT_QUALIFICATION_EPT_ENTRY_PRESENT RT_BIT(3)
1139	/** AND of the write bit of all EPT structures. */
1140	#define VMX_EXIT_QUALIFICATION_EPT_ENTRY_WRITE RT_BIT(4)
1141	/** AND of the execute bit of all EPT structures. */
1142	#define VMX_EXIT_QUALIFICATION_EPT_ENTRY_EXECUTE RT_BIT(5)
1143	/** Set if the guest linear address field contains the faulting address. */
1144	#define VMX_EXIT_QUALIFICATION_EPT_GUEST_ADDR_VALID RT_BIT(7)
1145	/** If bit 7 is one: (reserved otherwise)
1146	* 1 - violation due to physical address access.
1147	* 0 - violation caused by page walk or access/dirty bit updates
1148	*/
1149	#define VMX_EXIT_QUALIFICATION_EPT_TRANSLATED_ACCESS RT_BIT(8)
1150	/** @} */
1151
1152
1153	/** @name VMX_EXIT_PORT_IO
1154	* @{
1155	*/
1156	/** 0-2: IO operation width. */
1157	#define VMX_EXIT_QUALIFICATION_IO_WIDTH(a) (a & 7)
1158	/** 3: IO operation direction. */
1159	#define VMX_EXIT_QUALIFICATION_IO_DIRECTION(a) ((a >> 3) & 1)
1160	/** 4: String IO operation. */
1161	#define VMX_EXIT_QUALIFICATION_IO_STRING(a) ((a >> 4) & 1)
1162	/** 5: Repeated IO operation. */
1163	#define VMX_EXIT_QUALIFICATION_IO_REP(a) ((a >> 5) & 1)
1164	/** 6: Operand encoding. */
1165	#define VMX_EXIT_QUALIFICATION_IO_ENCODING(a) ((a >> 6) & 1)
1166	/** 16-31: IO Port (0-0xffff). */
1167	#define VMX_EXIT_QUALIFICATION_IO_PORT(a) ((a >> 16) & 0xffff)
1168	/* Rest reserved. */
1169	/** @} */
1170
1171	/** @name VMX_EXIT_QUALIFICATION_IO_DIRECTION
1172	* @{
1173	*/
1174	#define VMX_EXIT_QUALIFICATION_IO_DIRECTION_OUT 0
1175	#define VMX_EXIT_QUALIFICATION_IO_DIRECTION_IN 1
1176	/** @} */
1177
1178
1179	/** @name VMX_EXIT_QUALIFICATION_IO_ENCODING
1180	* @{
1181	*/
1182	#define VMX_EXIT_QUALIFICATION_IO_ENCODING_DX 0
1183	#define VMX_EXIT_QUALIFICATION_IO_ENCODING_IMM 1
1184	/** @} */
1185
1186	/** @name VMX_EXIT_APIC_ACCESS
1187	* @{
1188	*/
1189	/** 0-11: If the APIC-access VM exit is due to a linear access, the offset of access within the APIC page. */
1190	#define VMX_EXIT_QUALIFICATION_APIC_ACCESS_OFFSET(a) (a & 0xfff)
1191	/** 12-15: Access type. */
1192	#define VMX_EXIT_QUALIFICATION_APIC_ACCESS_TYPE(a) ((a >> 12) & 0xf)
1193	/* Rest reserved. */
1194	/** @} */
1195
1196
1197	/** @name VMX_EXIT_QUALIFICATION_APIC_ACCESS_TYPE; access types
1198	* @{
1199	*/
1200	/** Linear read access. */
1201	#define VMX_APIC_ACCESS_TYPE_LINEAR_READ 0
1202	/** Linear write access. */
1203	#define VMX_APIC_ACCESS_TYPE_LINEAR_WRITE 1
1204	/** Linear instruction fetch access. */
1205	#define VMX_APIC_ACCESS_TYPE_LINEAR_INSTR_FETCH 2
1206	/** Linear read/write access during event delivery. */
1207	#define VMX_APIC_ACCESS_TYPE_LINEAR_EVENT_DELIVERY 3
1208	/** Physical read/write access during event delivery. */
1209	#define VMX_APIC_ACCESS_TYPE_PHYSICAL_EVENT_DELIVERY 10
1210	/** Physical access for an instruction fetch or during instruction execution. */
1211	#define VMX_APIC_ACCESS_TYPE_PHYSICAL_INSTR 15
1212	/** @} */
1213
1214	/** @} */
1215
1216	/** @name VMCS field encoding - Natural width guest state fields
1217	* @{
1218	*/
1219	#define VMX_VMCS64_GUEST_CR0 0x6800
1220	#define VMX_VMCS64_GUEST_CR3 0x6802
1221	#define VMX_VMCS64_GUEST_CR4 0x6804
1222	#define VMX_VMCS64_GUEST_ES_BASE 0x6806
1223	#define VMX_VMCS64_GUEST_CS_BASE 0x6808
1224	#define VMX_VMCS64_GUEST_SS_BASE 0x680A
1225	#define VMX_VMCS64_GUEST_DS_BASE 0x680C
1226	#define VMX_VMCS64_GUEST_FS_BASE 0x680E
1227	#define VMX_VMCS64_GUEST_GS_BASE 0x6810
1228	#define VMX_VMCS64_GUEST_LDTR_BASE 0x6812
1229	#define VMX_VMCS64_GUEST_TR_BASE 0x6814
1230	#define VMX_VMCS64_GUEST_GDTR_BASE 0x6816
1231	#define VMX_VMCS64_GUEST_IDTR_BASE 0x6818
1232	#define VMX_VMCS64_GUEST_DR7 0x681A
1233	#define VMX_VMCS64_GUEST_RSP 0x681C
1234	#define VMX_VMCS64_GUEST_RIP 0x681E
1235	#define VMX_VMCS_GUEST_RFLAGS 0x6820
1236	#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS 0x6822
1237	#define VMX_VMCS64_GUEST_SYSENTER_ESP 0x6824 /*< MSR IA32_SYSENTER_ESP /
1238	#define VMX_VMCS64_GUEST_SYSENTER_EIP 0x6826 /*< MSR IA32_SYSENTER_EIP /
1239	/** @} */
1240
1241
1242	/** @name VMX_VMCS_GUEST_DEBUG_EXCEPTIONS
1243	* @{
1244	*/
1245	/** Hardware breakpoint 0 was met. */
1246	#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B0 RT_BIT(0)
1247	/** Hardware breakpoint 1 was met. */
1248	#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B1 RT_BIT(1)
1249	/** Hardware breakpoint 2 was met. */
1250	#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B2 RT_BIT(2)
1251	/** Hardware breakpoint 3 was met. */
1252	#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B3 RT_BIT(3)
1253	/** At least one data or IO breakpoint was hit. */
1254	#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_BREAKPOINT_ENABLED RT_BIT(12)
1255	/** A debug exception would have been triggered by single-step execution mode. */
1256	#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_BS RT_BIT(14)
1257	/** Bits 4-11, 13 and 15-63 are reserved. */
1258
1259	/** @} */
1260
1261	/** @name VMCS field encoding - Natural width host state fields
1262	* @{
1263	*/
1264	#define VMX_VMCS_HOST_CR0 0x6C00
1265	#define VMX_VMCS_HOST_CR3 0x6C02
1266	#define VMX_VMCS_HOST_CR4 0x6C04
1267	#define VMX_VMCS_HOST_FS_BASE 0x6C06
1268	#define VMX_VMCS_HOST_GS_BASE 0x6C08
1269	#define VMX_VMCS_HOST_TR_BASE 0x6C0A
1270	#define VMX_VMCS_HOST_GDTR_BASE 0x6C0C
1271	#define VMX_VMCS_HOST_IDTR_BASE 0x6C0E
1272	#define VMX_VMCS_HOST_SYSENTER_ESP 0x6C10
1273	#define VMX_VMCS_HOST_SYSENTER_EIP 0x6C12
1274	#define VMX_VMCS_HOST_RSP 0x6C14
1275	#define VMX_VMCS_HOST_RIP 0x6C16
1276	/** @} */
1277
1278	/** @} */
1279
1280
1281	#if RT_INLINE_ASM_GNU_STYLE
1282	# define __STR(x) #x
1283	# define STR(x) __STR(x)
1284	#endif
1285
1286
1287	/** @defgroup grp_vmx_asm vmx assembly helpers
1288	* @ingroup grp_vmx
1289	* @{
1290	*/
1291
1292	/**
1293	* Executes VMXON
1294	*
1295	* @returns VBox status code
1296	* @param pVMXOn Physical address of VMXON structure
1297	*/
1298	#if RT_INLINE_ASM_EXTERNAL \|\| HC_ARCH_BITS == 64 \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1299	DECLASM(int) VMXEnable(RTHCPHYS pVMXOn);
1300	#else
1301	DECLINLINE(int) VMXEnable(RTHCPHYS pVMXOn)
1302	{
1303	int rc = VINF_SUCCESS;
1304	# if RT_INLINE_ASM_GNU_STYLE
1305	__asm__ __volatile__ (
1306	"push %3 \n\t"
1307	"push %2 \n\t"
1308	".byte 0xF3, 0x0F, 0xC7, 0x34, 0x24 # VMXON [esp] \n\t"
1309	"ja 2f \n\t"
1310	"je 1f \n\t"
1311	"movl $"STR(VERR_VMX_INVALID_VMXON_PTR)", %0 \n\t"
1312	"jmp 2f \n\t"
1313	"1: \n\t"
1314	"movl $"STR(VERR_VMX_GENERIC)", %0 \n\t"
1315	"2: \n\t"
1316	"add $8, %%esp \n\t"
1317	:"=rm"(rc)
1318	:"0"(VINF_SUCCESS),
1319	"ir"((uint32_t)pVMXOn), /* don't allow direct memory reference here, */
1320	"ir"((uint32_t)(pVMXOn >> 32)) /* this would not work with -fomit-frame-pointer */
1321	:"memory"
1322	);
1323	# else
1324	__asm
1325	{
1326	push dword ptr [pVMXOn+4]
1327	push dword ptr [pVMXOn]
1328	_emit 0xF3
1329	_emit 0x0F
1330	_emit 0xC7
1331	_emit 0x34
1332	_emit 0x24 /* VMXON [esp] */
1333	jnc vmxon_good
1334	mov dword ptr [rc], VERR_VMX_INVALID_VMXON_PTR
1335	jmp the_end
1336
1337	vmxon_good:
1338	jnz the_end
1339	mov dword ptr [rc], VERR_VMX_GENERIC
1340	the_end:
1341	add esp, 8
1342	}
1343	# endif
1344	return rc;
1345	}
1346	#endif
1347
1348
1349	/**
1350	* Executes VMXOFF
1351	*/
1352	#if RT_INLINE_ASM_EXTERNAL \|\| HC_ARCH_BITS == 64 \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1353	DECLASM(void) VMXDisable(void);
1354	#else
1355	DECLINLINE(void) VMXDisable(void)
1356	{
1357	# if RT_INLINE_ASM_GNU_STYLE
1358	__asm__ __volatile__ (
1359	".byte 0x0F, 0x01, 0xC4 # VMXOFF \n\t"
1360	);
1361	# else
1362	__asm
1363	{
1364	_emit 0x0F
1365	_emit 0x01
1366	_emit 0xC4 /* VMXOFF */
1367	}
1368	# endif
1369	}
1370	#endif
1371
1372
1373	/**
1374	* Executes VMCLEAR
1375	*
1376	* @returns VBox status code
1377	* @param pVMCS Physical address of VM control structure
1378	*/
1379	#if RT_INLINE_ASM_EXTERNAL \|\| HC_ARCH_BITS == 64 \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1380	DECLASM(int) VMXClearVMCS(RTHCPHYS pVMCS);
1381	#else
1382	DECLINLINE(int) VMXClearVMCS(RTHCPHYS pVMCS)
1383	{
1384	int rc = VINF_SUCCESS;
1385	# if RT_INLINE_ASM_GNU_STYLE
1386	__asm__ __volatile__ (
1387	"push %3 \n\t"
1388	"push %2 \n\t"
1389	".byte 0x66, 0x0F, 0xC7, 0x34, 0x24 # VMCLEAR [esp] \n\t"
1390	"jnc 1f \n\t"
1391	"movl $"STR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
1392	"1: \n\t"
1393	"add $8, %%esp \n\t"
1394	:"=rm"(rc)
1395	:"0"(VINF_SUCCESS),
1396	"ir"((uint32_t)pVMCS), /* don't allow direct memory reference here, */
1397	"ir"((uint32_t)(pVMCS >> 32)) /* this would not work with -fomit-frame-pointer */
1398	:"memory"
1399	);
1400	# else
1401	__asm
1402	{
1403	push dword ptr [pVMCS+4]
1404	push dword ptr [pVMCS]
1405	_emit 0x66
1406	_emit 0x0F
1407	_emit 0xC7
1408	_emit 0x34
1409	_emit 0x24 /* VMCLEAR [esp] */
1410	jnc success
1411	mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
1412	success:
1413	add esp, 8
1414	}
1415	# endif
1416	return rc;
1417	}
1418	#endif
1419
1420
1421	/**
1422	* Executes VMPTRLD
1423	*
1424	* @returns VBox status code
1425	* @param pVMCS Physical address of VMCS structure
1426	*/
1427	#if RT_INLINE_ASM_EXTERNAL \|\| HC_ARCH_BITS == 64 \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1428	DECLASM(int) VMXActivateVMCS(RTHCPHYS pVMCS);
1429	#else
1430	DECLINLINE(int) VMXActivateVMCS(RTHCPHYS pVMCS)
1431	{
1432	int rc = VINF_SUCCESS;
1433	# if RT_INLINE_ASM_GNU_STYLE
1434	__asm__ __volatile__ (
1435	"push %3 \n\t"
1436	"push %2 \n\t"
1437	".byte 0x0F, 0xC7, 0x34, 0x24 # VMPTRLD [esp] \n\t"
1438	"jnc 1f \n\t"
1439	"movl $"STR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
1440	"1: \n\t"
1441	"add $8, %%esp \n\t"
1442	:"=rm"(rc)
1443	:"0"(VINF_SUCCESS),
1444	"ir"((uint32_t)pVMCS), /* don't allow direct memory reference here, */
1445	"ir"((uint32_t)(pVMCS >> 32)) /* this will not work with -fomit-frame-pointer */
1446	);
1447	# else
1448	__asm
1449	{
1450	push dword ptr [pVMCS+4]
1451	push dword ptr [pVMCS]
1452	_emit 0x0F
1453	_emit 0xC7
1454	_emit 0x34
1455	_emit 0x24 /* VMPTRLD [esp] */
1456	jnc success
1457	mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
1458
1459	success:
1460	add esp, 8
1461	}
1462	# endif
1463	return rc;
1464	}
1465	#endif
1466
1467	/**
1468	* Executes VMPTRST
1469	*
1470	* @returns VBox status code
1471	* @param pVMCS Address that will receive the current pointer
1472	*/
1473	DECLASM(int) VMXGetActivateVMCS(RTHCPHYS *pVMCS);
1474
1475	/**
1476	* Executes VMWRITE
1477	*
1478	* @returns VBox status code
1479	* @param idxField VMCS index
1480	* @param u32Val 32 bits value
1481	*/
1482	#if RT_INLINE_ASM_EXTERNAL \|\| HC_ARCH_BITS == 64 \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1483	DECLASM(int) VMXWriteVMCS32(uint32_t idxField, uint32_t u32Val);
1484	#else
1485	DECLINLINE(int) VMXWriteVMCS32(uint32_t idxField, uint32_t u32Val)
1486	{
1487	int rc = VINF_SUCCESS;
1488	# if RT_INLINE_ASM_GNU_STYLE
1489	__asm__ __volatile__ (
1490	".byte 0x0F, 0x79, 0xC2 # VMWRITE eax, edx \n\t"
1491	"ja 2f \n\t"
1492	"je 1f \n\t"
1493	"movl $"STR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
1494	"jmp 2f \n\t"
1495	"1: \n\t"
1496	"movl $"STR(VERR_VMX_INVALID_VMCS_FIELD)", %0 \n\t"
1497	"2: \n\t"
1498	:"=rm"(rc)
1499	:"0"(VINF_SUCCESS),
1500	"a"(idxField),
1501	"d"(u32Val)
1502	);
1503	# else
1504	__asm
1505	{
1506	push dword ptr [u32Val]
1507	mov eax, [idxField]
1508	_emit 0x0F
1509	_emit 0x79
1510	_emit 0x04
1511	_emit 0x24 /* VMWRITE eax, [esp] */
1512	jnc valid_vmcs
1513	mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
1514	jmp the_end
1515
1516	valid_vmcs:
1517	jnz the_end
1518	mov dword ptr [rc], VERR_VMX_INVALID_VMCS_FIELD
1519	the_end:
1520	add esp, 4
1521	}
1522	# endif
1523	return rc;
1524	}
1525	#endif
1526
1527	/**
1528	* Executes VMWRITE
1529	*
1530	* @returns VBox status code
1531	* @param idxField VMCS index
1532	* @param u64Val 16, 32 or 64 bits value
1533	*/
1534	#if HC_ARCH_BITS == 64 \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1535	DECLASM(int) VMXWriteVMCS64(uint32_t idxField, uint64_t u64Val);
1536	#else
1537	VMMR0DECL(int) VMXWriteVMCS64Ex(PVMCPU pVCpu, uint32_t idxField, uint64_t u64Val);
1538
1539	#define VMXWriteVMCS64(idxField, u64Val) VMXWriteVMCS64Ex(pVCpu, idxField, u64Val)
1540	#endif
1541
1542	#if HC_ARCH_BITS == 64
1543	#define VMXWriteVMCS VMXWriteVMCS64
1544	#else
1545	#define VMXWriteVMCS VMXWriteVMCS32
1546	#endif /* HC_ARCH_BITS == 64 */
1547
1548
1549	/**
1550	* Invalidate a page using invept
1551	* @returns VBox status code
1552	* @param enmFlush Type of flush
1553	* @param pDescriptor Descriptor
1554	*/
1555	DECLASM(int) VMXR0InvEPT(VMX_FLUSH enmFlush, uint64_t *pDescriptor);
1556
1557	/**
1558	* Invalidate a page using invvpid
1559	* @returns VBox status code
1560	* @param enmFlush Type of flush
1561	* @param pDescriptor Descriptor
1562	*/
1563	DECLASM(int) VMXR0InvVPID(VMX_FLUSH enmFlush, uint64_t *pDescriptor);
1564
1565	/**
1566	* Executes VMREAD
1567	*
1568	* @returns VBox status code
1569	* @param idxField VMCS index
1570	* @param pData Ptr to store VM field value
1571	*/
1572	#if RT_INLINE_ASM_EXTERNAL \|\| HC_ARCH_BITS == 64 \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1573	DECLASM(int) VMXReadVMCS32(uint32_t idxField, uint32_t *pData);
1574	#else
1575	DECLINLINE(int) VMXReadVMCS32(uint32_t idxField, uint32_t *pData)
1576	{
1577	int rc = VINF_SUCCESS;
1578	# if RT_INLINE_ASM_GNU_STYLE
1579	__asm__ __volatile__ (
1580	"movl $"STR(VINF_SUCCESS)", %0 \n\t"
1581	".byte 0x0F, 0x78, 0xc2 # VMREAD eax, edx \n\t"
1582	"ja 2f \n\t"
1583	"je 1f \n\t"
1584	"movl $"STR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
1585	"jmp 2f \n\t"
1586	"1: \n\t"
1587	"movl $"STR(VERR_VMX_INVALID_VMCS_FIELD)", %0 \n\t"
1588	"2: \n\t"
1589	:"=&r"(rc),
1590	"=d"(*pData)
1591	:"a"(idxField),
1592	"d"(0)
1593	);
1594	# else
1595	__asm
1596	{
1597	sub esp, 4
1598	mov dword ptr [esp], 0
1599	mov eax, [idxField]
1600	_emit 0x0F
1601	_emit 0x78
1602	_emit 0x04
1603	_emit 0x24 /* VMREAD eax, [esp] */
1604	mov edx, pData
1605	pop dword ptr [edx]
1606	jnc valid_vmcs
1607	mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
1608	jmp the_end
1609
1610	valid_vmcs:
1611	jnz the_end
1612	mov dword ptr [rc], VERR_VMX_INVALID_VMCS_FIELD
1613	the_end:
1614	}
1615	# endif
1616	return rc;
1617	}
1618	#endif
1619
1620	/**
1621	* Executes VMREAD
1622	*
1623	* @returns VBox status code
1624	* @param idxField VMCS index
1625	* @param pData Ptr to store VM field value
1626	*/
1627	#if HC_ARCH_BITS == 64 \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1628	DECLASM(int) VMXReadVMCS64(uint32_t idxField, uint64_t *pData);
1629	#else
1630	DECLINLINE(int) VMXReadVMCS64(uint32_t idxField, uint64_t *pData)
1631	{
1632	int rc;
1633
1634	uint32_t val_hi, val;
1635	rc = VMXReadVMCS32(idxField, &val);
1636	rc \|= VMXReadVMCS32(idxField + 1, &val_hi);
1637	AssertRC(rc);
1638	*pData = RT_MAKE_U64(val, val_hi);
1639	return rc;
1640	}
1641	#endif
1642
1643	#if HC_ARCH_BITS == 64
1644	# define VMXReadVMCS VMXReadVMCS64
1645	#else
1646	# define VMXReadVMCS VMXReadVMCS32
1647	#endif /* HC_ARCH_BITS == 64 */
1648
1649	/**
1650	* Gets the last instruction error value from the current VMCS
1651	*
1652	* @returns error value
1653	*/
1654	DECLINLINE(uint32_t) VMXGetLastError(void)
1655	{
1656	#if HC_ARCH_BITS == 64
1657	uint64_t uLastError = 0;
1658	int rc = VMXReadVMCS(VMX_VMCS32_RO_VM_INSTR_ERROR, &uLastError);
1659	AssertRC(rc);
1660	return (uint32_t)uLastError;
1661
1662	#else /* 32-bit host: */
1663	uint32_t uLastError = 0;
1664	int rc = VMXReadVMCS32(VMX_VMCS32_RO_VM_INSTR_ERROR, &uLastError);
1665	AssertRC(rc);
1666	return uLastError;
1667	#endif
1668	}
1669
1670	#ifdef IN_RING0
1671	VMMR0DECL(int) VMXR0InvalidatePage(PVM pVM, PVMCPU pVCpu, RTGCPTR GCVirt);
1672	VMMR0DECL(int) VMXR0InvalidatePhysPage(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys);
1673	#endif /* IN_RING0 */
1674
1675	/** @} */
1676
1677	#endif
1678

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source: vbox/trunk/include/VBox/hwacc_vmx.h@ 29567

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