hwacc_vmx.h@ 32780

Last change on this file since 32780 was 32385, checked in by vboxsync, 14 years ago
hwacc_vmx.h: some macro safty nits.
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1	/** @file
2	* HWACCM - VMX Structures and Definitions. (VMM)
3	*/
4
5	/*
6	* Copyright (C) 2006-2007 Oracle Corporation
7	*
8	* This file is part of VirtualBox Open Source Edition (OSE), as
9	* available from http://www.virtualbox.org. This file is free software;
10	* you can redistribute it and/or modify it under the terms of the GNU
11	* General Public License (GPL) as published by the Free Software
12	* Foundation, in version 2 as it comes in the "COPYING" file of the
13	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15	*
16	* The contents of this file may alternatively be used under the terms
17	* of the Common Development and Distribution License Version 1.0
18	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19	* VirtualBox OSE distribution, in which case the provisions of the
20	* CDDL are applicable instead of those of the GPL.
21	*
22	* You may elect to license modified versions of this file under the
23	* terms and conditions of either the GPL or the CDDL or both.
24	*/
25
26	#ifndef ___VBox_vmx_h
27	#define ___VBox_vmx_h
28
29	#include <VBox/types.h>
30	#include <VBox/err.h>
31	#include <VBox/x86.h>
32	#include <iprt/assert.h>
33
34	/** @defgroup grp_vmx vmx Types and Definitions
35	* @ingroup grp_hwaccm
36	* @{
37	*/
38
39	/** @name VMX EPT paging structures
40	* @{
41	*/
42
43	/**
44	* Number of page table entries in the EPT. (PDPTE/PDE/PTE)
45	*/
46	#define EPT_PG_ENTRIES X86_PG_PAE_ENTRIES
47
48	/**
49	* EPT Page Directory Pointer Entry. Bit view.
50	* @todo uint64_t isn't safe for bitfields (gcc pedantic warnings, and IIRC,
51	* this did cause trouble with one compiler/version).
52	*/
53	#pragma pack(1)
54	typedef struct EPTPML4EBITS
55	{
56	/** Present bit. */
57	uint64_t u1Present : 1;
58	/** Writable bit. */
59	uint64_t u1Write : 1;
60	/** Executable bit. */
61	uint64_t u1Execute : 1;
62	/** Reserved (must be 0). */
63	uint64_t u5Reserved : 5;
64	/** Available for software. */
65	uint64_t u4Available : 4;
66	/** Physical address of the next level (PD). Restricted by maximum physical address width of the cpu. */
67	uint64_t u40PhysAddr : 40;
68	/** Availabe for software. */
69	uint64_t u12Available : 12;
70	} EPTPML4EBITS;
71	#pragma pack()
72	AssertCompileSize(EPTPML4EBITS, 8);
73
74	/** Bits 12-51 - - EPT - Physical Page number of the next level. */
75	#define EPT_PML4E_PG_MASK X86_PML4E_PG_MASK
76	/** The page shift to get the PML4 index. */
77	#define EPT_PML4_SHIFT X86_PML4_SHIFT
78	/** The PML4 index mask (apply to a shifted page address). */
79	#define EPT_PML4_MASK X86_PML4_MASK
80
81	/**
82	* EPT PML4E.
83	*/
84	#pragma pack(1)
85	typedef union EPTPML4E
86	{
87	/** Normal view. */
88	EPTPML4EBITS n;
89	/** Unsigned integer view. */
90	X86PGPAEUINT u;
91	/** 64 bit unsigned integer view. */
92	uint64_t au64[1];
93	/** 32 bit unsigned integer view. */
94	uint32_t au32[2];
95	} EPTPML4E;
96	#pragma pack()
97	/** Pointer to a PML4 table entry. */
98	typedef EPTPML4E *PEPTPML4E;
99	/** Pointer to a const PML4 table entry. */
100	typedef const EPTPML4E *PCEPTPML4E;
101	AssertCompileSize(EPTPML4E, 8);
102
103	/**
104	* EPT PML4 Table.
105	*/
106	#pragma pack(1)
107	typedef struct EPTPML4
108	{
109	EPTPML4E a[EPT_PG_ENTRIES];
110	} EPTPML4;
111	#pragma pack()
112	/** Pointer to an EPT PML4 Table. */
113	typedef EPTPML4 *PEPTPML4;
114	/** Pointer to a const EPT PML4 Table. */
115	typedef const EPTPML4 *PCEPTPML4;
116
117	/**
118	* EPT Page Directory Pointer Entry. Bit view.
119	*/
120	#pragma pack(1)
121	typedef struct EPTPDPTEBITS
122	{
123	/** Present bit. */
124	uint64_t u1Present : 1;
125	/** Writable bit. */
126	uint64_t u1Write : 1;
127	/** Executable bit. */
128	uint64_t u1Execute : 1;
129	/** Reserved (must be 0). */
130	uint64_t u5Reserved : 5;
131	/** Available for software. */
132	uint64_t u4Available : 4;
133	/** Physical address of the next level (PD). Restricted by maximum physical address width of the cpu. */
134	uint64_t u40PhysAddr : 40;
135	/** Availabe for software. */
136	uint64_t u12Available : 12;
137	} EPTPDPTEBITS;
138	#pragma pack()
139	AssertCompileSize(EPTPDPTEBITS, 8);
140
141	/** Bits 12-51 - - EPT - Physical Page number of the next level. */
142	#define EPT_PDPTE_PG_MASK X86_PDPE_PG_MASK
143	/** The page shift to get the PDPT index. */
144	#define EPT_PDPT_SHIFT X86_PDPT_SHIFT
145	/** The PDPT index mask (apply to a shifted page address). */
146	#define EPT_PDPT_MASK X86_PDPT_MASK_AMD64
147
148	/**
149	* EPT Page Directory Pointer.
150	*/
151	#pragma pack(1)
152	typedef union EPTPDPTE
153	{
154	/** Normal view. */
155	EPTPDPTEBITS n;
156	/** Unsigned integer view. */
157	X86PGPAEUINT u;
158	/** 64 bit unsigned integer view. */
159	uint64_t au64[1];
160	/** 32 bit unsigned integer view. */
161	uint32_t au32[2];
162	} EPTPDPTE;
163	#pragma pack()
164	/** Pointer to an EPT Page Directory Pointer Entry. */
165	typedef EPTPDPTE *PEPTPDPTE;
166	/** Pointer to a const EPT Page Directory Pointer Entry. */
167	typedef const EPTPDPTE *PCEPTPDPTE;
168	AssertCompileSize(EPTPDPTE, 8);
169
170	/**
171	* EPT Page Directory Pointer Table.
172	*/
173	#pragma pack(1)
174	typedef struct EPTPDPT
175	{
176	EPTPDPTE a[EPT_PG_ENTRIES];
177	} EPTPDPT;
178	#pragma pack()
179	/** Pointer to an EPT Page Directory Pointer Table. */
180	typedef EPTPDPT *PEPTPDPT;
181	/** Pointer to a const EPT Page Directory Pointer Table. */
182	typedef const EPTPDPT *PCEPTPDPT;
183
184
185	/**
186	* EPT Page Directory Table Entry. Bit view.
187	*/
188	#pragma pack(1)
189	typedef struct EPTPDEBITS
190	{
191	/** Present bit. */
192	uint64_t u1Present : 1;
193	/** Writable bit. */
194	uint64_t u1Write : 1;
195	/** Executable bit. */
196	uint64_t u1Execute : 1;
197	/** Reserved (must be 0). */
198	uint64_t u4Reserved : 4;
199	/** Big page (must be 0 here). */
200	uint64_t u1Size : 1;
201	/** Available for software. */
202	uint64_t u4Available : 4;
203	/** Physical address of page table. Restricted by maximum physical address width of the cpu. */
204	uint64_t u40PhysAddr : 40;
205	/** Availabe for software. */
206	uint64_t u12Available : 12;
207	} EPTPDEBITS;
208	#pragma pack()
209	AssertCompileSize(EPTPDEBITS, 8);
210
211	/** Bits 12-51 - - EPT - Physical Page number of the next level. */
212	#define EPT_PDE_PG_MASK X86_PDE_PAE_PG_MASK
213	/** The page shift to get the PD index. */
214	#define EPT_PD_SHIFT X86_PD_PAE_SHIFT
215	/** The PD index mask (apply to a shifted page address). */
216	#define EPT_PD_MASK X86_PD_PAE_MASK
217
218	/**
219	* EPT 2MB Page Directory Table Entry. Bit view.
220	*/
221	#pragma pack(1)
222	typedef struct EPTPDE2MBITS
223	{
224	/** Present bit. */
225	uint64_t u1Present : 1;
226	/** Writable bit. */
227	uint64_t u1Write : 1;
228	/** Executable bit. */
229	uint64_t u1Execute : 1;
230	/** EPT Table Memory Type. MBZ for non-leaf nodes. */
231	uint64_t u3EMT : 3;
232	/** Ignore PAT memory type */
233	uint64_t u1IgnorePAT : 1;
234	/** Big page (must be 1 here). */
235	uint64_t u1Size : 1;
236	/** Available for software. */
237	uint64_t u4Available : 4;
238	/** Reserved (must be 0). */
239	uint64_t u9Reserved : 9;
240	/** Physical address of the 2MB page. Restricted by maximum physical address width of the cpu. */
241	uint64_t u31PhysAddr : 31;
242	/** Availabe for software. */
243	uint64_t u12Available : 12;
244	} EPTPDE2MBITS;
245	#pragma pack()
246	AssertCompileSize(EPTPDE2MBITS, 8);
247
248	/** Bits 21-51 - - EPT - Physical Page number of the next level. */
249	#define EPT_PDE2M_PG_MASK ( 0x000fffffffe00000ULL )
250
251	/**
252	* EPT Page Directory Table Entry.
253	*/
254	#pragma pack(1)
255	typedef union EPTPDE
256	{
257	/** Normal view. */
258	EPTPDEBITS n;
259	/** 2MB view (big). */
260	EPTPDE2MBITS b;
261	/** Unsigned integer view. */
262	X86PGPAEUINT u;
263	/** 64 bit unsigned integer view. */
264	uint64_t au64[1];
265	/** 32 bit unsigned integer view. */
266	uint32_t au32[2];
267	} EPTPDE;
268	#pragma pack()
269	/** Pointer to an EPT Page Directory Table Entry. */
270	typedef EPTPDE *PEPTPDE;
271	/** Pointer to a const EPT Page Directory Table Entry. */
272	typedef const EPTPDE *PCEPTPDE;
273	AssertCompileSize(EPTPDE, 8);
274
275	/**
276	* EPT Page Directory Table.
277	*/
278	#pragma pack(1)
279	typedef struct EPTPD
280	{
281	EPTPDE a[EPT_PG_ENTRIES];
282	} EPTPD;
283	#pragma pack()
284	/** Pointer to an EPT Page Directory Table. */
285	typedef EPTPD *PEPTPD;
286	/** Pointer to a const EPT Page Directory Table. */
287	typedef const EPTPD *PCEPTPD;
288
289
290	/**
291	* EPT Page Table Entry. Bit view.
292	*/
293	#pragma pack(1)
294	typedef struct EPTPTEBITS
295	{
296	/** 0 - Present bit.
297	* @remark This is a convenience "misnomer". The bit actually indicates
298	* read access and the CPU will consider an entry with any of the
299	* first three bits set as present. Since all our valid entries
300	* will have this bit set, it can be used as a present indicator
301	* and allow some code sharing. */
302	uint64_t u1Present : 1;
303	/** 1 - Writable bit. */
304	uint64_t u1Write : 1;
305	/** 2 - Executable bit. */
306	uint64_t u1Execute : 1;
307	/** 5:3 - EPT Memory Type. MBZ for non-leaf nodes. */
308	uint64_t u3EMT : 3;
309	/** 6 - Ignore PAT memory type */
310	uint64_t u1IgnorePAT : 1;
311	/** 11:7 - Available for software. */
312	uint64_t u5Available : 5;
313	/** 51:12 - Physical address of page. Restricted by maximum physical
314	* address width of the cpu. */
315	uint64_t u40PhysAddr : 40;
316	/** 63:52 - Available for software. */
317	uint64_t u12Available : 12;
318	} EPTPTEBITS;
319	#pragma pack()
320	AssertCompileSize(EPTPTEBITS, 8);
321
322	/** Bits 12-51 - - EPT - Physical Page number of the next level. */
323	#define EPT_PTE_PG_MASK X86_PTE_PAE_PG_MASK
324	/** The page shift to get the EPT PTE index. */
325	#define EPT_PT_SHIFT X86_PT_PAE_SHIFT
326	/** The EPT PT index mask (apply to a shifted page address). */
327	#define EPT_PT_MASK X86_PT_PAE_MASK
328
329	/**
330	* EPT Page Table Entry.
331	*/
332	#pragma pack(1)
333	typedef union EPTPTE
334	{
335	/** Normal view. */
336	EPTPTEBITS n;
337	/** Unsigned integer view. */
338	X86PGPAEUINT u;
339	/** 64 bit unsigned integer view. */
340	uint64_t au64[1];
341	/** 32 bit unsigned integer view. */
342	uint32_t au32[2];
343	} EPTPTE;
344	#pragma pack()
345	/** Pointer to an EPT Page Directory Table Entry. */
346	typedef EPTPTE *PEPTPTE;
347	/** Pointer to a const EPT Page Directory Table Entry. */
348	typedef const EPTPTE *PCEPTPTE;
349	AssertCompileSize(EPTPTE, 8);
350
351	/**
352	* EPT Page Table.
353	*/
354	#pragma pack(1)
355	typedef struct EPTPT
356	{
357	EPTPTE a[EPT_PG_ENTRIES];
358	} EPTPT;
359	#pragma pack()
360	/** Pointer to an extended page table. */
361	typedef EPTPT *PEPTPT;
362	/** Pointer to a const extended table. */
363	typedef const EPTPT *PCEPTPT;
364
365	/**
366	* VPID and EPT flush types
367	*/
368	typedef enum
369	{
370	/* Invalidate a specific page. */
371	VMX_FLUSH_PAGE = 0,
372	/* Invalidate one context (VPID or EPT) */
373	VMX_FLUSH_SINGLE_CONTEXT = 1,
374	/* Invalidate all contexts (VPIDs or EPTs) */
375	VMX_FLUSH_ALL_CONTEXTS = 2,
376	/* Invalidate a single VPID context retaining global mappings. */
377	VMX_FLUSH_SINGLE_CONTEXT_WITHOUT_GLOBAL = 3,
378	/** 32bit hackishness. */
379	VMX_FLUSH_32BIT_HACK = 0x7fffffff
380	} VMX_FLUSH;
381	/** @} */
382
383	/** @name MSR load/store elements
384	* @{
385	*/
386	#pragma pack(1)
387	typedef struct
388	{
389	uint32_t u32IndexMSR;
390	uint32_t u32Reserved;
391	uint64_t u64Value;
392	} VMXMSR;
393	#pragma pack()
394	/** Pointer to an MSR load/store element. */
395	typedef VMXMSR *PVMXMSR;
396	/** Pointer to a const MSR load/store element. */
397	typedef const VMXMSR *PCVMXMSR;
398
399	/** @} */
400
401
402	/** @name VT-x capability qword
403	* @{
404	*/
405	#pragma pack(1)
406	typedef union
407	{
408	struct
409	{
410	uint32_t disallowed0;
411	uint32_t allowed1;
412	} n;
413	uint64_t u;
414	} VMX_CAPABILITY;
415	#pragma pack()
416	/** @} */
417
418	/** @name VMX Basic Exit Reasons.
419	* @{
420	*/
421	/** And-mask for setting reserved bits to zero */
422	#define VMX_EFLAGS_RESERVED_0 (~0xffc08028)
423	/** Or-mask for setting reserved bits to 1 */
424	#define VMX_EFLAGS_RESERVED_1 0x00000002
425	/** @} */
426
427	/** @name VMX Basic Exit Reasons.
428	* @{
429	*/
430	/** -1 Invalid exit code */
431	#define VMX_EXIT_INVALID -1
432	/** 0 Exception or non-maskable interrupt (NMI). */
433	#define VMX_EXIT_EXCEPTION 0
434	/** 1 External interrupt. */
435	#define VMX_EXIT_EXTERNAL_IRQ 1
436	/** 2 Triple fault. */
437	#define VMX_EXIT_TRIPLE_FAULT 2
438	/** 3 INIT signal. */
439	#define VMX_EXIT_INIT_SIGNAL 3
440	/** 4 Start-up IPI (SIPI). */
441	#define VMX_EXIT_SIPI 4
442	/** 5 I/O system-management interrupt (SMI). */
443	#define VMX_EXIT_IO_SMI_IRQ 5
444	/** 6 Other SMI. */
445	#define VMX_EXIT_SMI_IRQ 6
446	/** 7 Interrupt window. */
447	#define VMX_EXIT_IRQ_WINDOW 7
448	/** 9 Task switch. */
449	#define VMX_EXIT_TASK_SWITCH 9
450	/** 10 Guest software attempted to execute CPUID. */
451	#define VMX_EXIT_CPUID 10
452	/** 12 Guest software attempted to execute HLT. */
453	#define VMX_EXIT_HLT 12
454	/** 13 Guest software attempted to execute INVD. */
455	#define VMX_EXIT_INVD 13
456	/** 14 Guest software attempted to execute INVPG. */
457	#define VMX_EXIT_INVPG 14
458	/** 15 Guest software attempted to execute RDPMC. */
459	#define VMX_EXIT_RDPMC 15
460	/** 16 Guest software attempted to execute RDTSC. */
461	#define VMX_EXIT_RDTSC 16
462	/** 17 Guest software attempted to execute RSM in SMM. */
463	#define VMX_EXIT_RSM 17
464	/** 18 Guest software executed VMCALL. */
465	#define VMX_EXIT_VMCALL 18
466	/** 19 Guest software executed VMCLEAR. */
467	#define VMX_EXIT_VMCLEAR 19
468	/** 20 Guest software executed VMLAUNCH. */
469	#define VMX_EXIT_VMLAUNCH 20
470	/** 21 Guest software executed VMPTRLD. */
471	#define VMX_EXIT_VMPTRLD 21
472	/** 22 Guest software executed VMPTRST. */
473	#define VMX_EXIT_VMPTRST 22
474	/** 23 Guest software executed VMREAD. */
475	#define VMX_EXIT_VMREAD 23
476	/** 24 Guest software executed VMRESUME. */
477	#define VMX_EXIT_VMRESUME 24
478	/** 25 Guest software executed VMWRITE. */
479	#define VMX_EXIT_VMWRITE 25
480	/** 26 Guest software executed VMXOFF. */
481	#define VMX_EXIT_VMXOFF 26
482	/** 27 Guest software executed VMXON. */
483	#define VMX_EXIT_VMXON 27
484	/** 28 Control-register accesses. */
485	#define VMX_EXIT_CRX_MOVE 28
486	/** 29 Debug-register accesses. */
487	#define VMX_EXIT_DRX_MOVE 29
488	/** 30 I/O instruction. */
489	#define VMX_EXIT_PORT_IO 30
490	/** 31 RDMSR. Guest software attempted to execute RDMSR. */
491	#define VMX_EXIT_RDMSR 31
492	/** 32 WRMSR. Guest software attempted to execute WRMSR. */
493	#define VMX_EXIT_WRMSR 32
494	/** 33 VM-entry failure due to invalid guest state. */
495	#define VMX_EXIT_ERR_INVALID_GUEST_STATE 33
496	/** 34 VM-entry failure due to MSR loading. */
497	#define VMX_EXIT_ERR_MSR_LOAD 34
498	/** 36 Guest software executed MWAIT. */
499	#define VMX_EXIT_MWAIT 36
500	/** 39 Guest software attempted to execute MONITOR. */
501	#define VMX_EXIT_MONITOR 39
502	/** 40 Guest software attempted to execute PAUSE. */
503	#define VMX_EXIT_PAUSE 40
504	/** 41 VM-entry failure due to machine-check. */
505	#define VMX_EXIT_ERR_MACHINE_CHECK 41
506	/** 43 TPR below threshold. Guest software executed MOV to CR8. */
507	#define VMX_EXIT_TPR 43
508	/** 44 APIC access. Guest software attempted to access memory at a physical address on the APIC-access page. */
509	#define VMX_EXIT_APIC_ACCESS 44
510	/** 46 Access to GDTR or IDTR. Guest software attempted to execute LGDT, LIDT, SGDT, or SIDT. */
511	#define VMX_EXIT_XDTR_ACCESS 46
512	/** 47 Access to LDTR or TR. Guest software attempted to execute LLDT, LTR, SLDT, or STR. */
513	#define VMX_EXIT_TR_ACCESS 47
514	/** 48 EPT violation. An attempt to access memory with a guest-physical address was disallowed by the configuration of the EPT paging structures. */
515	#define VMX_EXIT_EPT_VIOLATION 48
516	/** 49 EPT misconfiguration. An attempt to access memory with a guest-physical address encountered a misconfigured EPT paging-structure entry. */
517	#define VMX_EXIT_EPT_MISCONFIG 49
518	/** 50 INVEPT. Guest software attempted to execute INVEPT. */
519	#define VMX_EXIT_INVEPT 50
520	/** 52 VMX-preemption timer expired. The preemption timer counted down to zero. */
521	#define VMX_EXIT_PREEMPTION_TIMER 52
522	/** 53 INVVPID. Guest software attempted to execute INVVPID. */
523	#define VMX_EXIT_INVVPID 53
524	/** 54 WBINVD. Guest software attempted to execute WBINVD. */
525	#define VMX_EXIT_WBINVD 54
526	/** 55 XSETBV. Guest software attempted to execute XSETBV. */
527	#define VMX_EXIT_XSETBV 55
528	/** @} */
529
530
531	/** @name VM Instruction Errors
532	* @{
533	*/
534	/** 1 VMCALL executed in VMX root operation. */
535	#define VMX_ERROR_VMCALL 1
536	/** 2 VMCLEAR with invalid physical address. */
537	#define VMX_ERROR_VMCLEAR_INVALID_PHYS_ADDR 2
538	/** 3 VMCLEAR with VMXON pointer. */
539	#define VMX_ERROR_VMCLEAR_INVALID_VMXON_PTR 3
540	/** 4 VMLAUNCH with non-clear VMCS. */
541	#define VMX_ERROR_VMLAUCH_NON_CLEAR_VMCS 4
542	/** 5 VMRESUME with non-launched VMCS. */
543	#define VMX_ERROR_VMRESUME_NON_LAUNCHED_VMCS 5
544	/** 6 VMRESUME with a corrupted VMCS (indicates corruption of the current VMCS). */
545	#define VMX_ERROR_VMRESUME_CORRUPTED_VMCS 6
546	/** 7 VM entry with invalid control field(s). */
547	#define VMX_ERROR_VMENTRY_INVALID_CONTROL_FIELDS 7
548	/** 8 VM entry with invalid host-state field(s). */
549	#define VMX_ERROR_VMENTRY_INVALID_HOST_STATE 8
550	/** 9 VMPTRLD with invalid physical address. */
551	#define VMX_ERROR_VMPTRLD_INVALID_PHYS_ADDR 9
552	/** 10 VMPTRLD with VMXON pointer. */
553	#define VMX_ERROR_VMPTRLD_VMXON_PTR 10
554	/** 11 VMPTRLD with incorrect VMCS revision identifier. */
555	#define VMX_ERROR_VMPTRLD_WRONG_VMCS_REVISION 11
556	/** 12 VMREAD/VMWRITE from/to unsupported VMCS component. */
557	#define VMX_ERROR_VMREAD_INVALID_COMPONENT 12
558	#define VMX_ERROR_VMWRITE_INVALID_COMPONENT VMX_ERROR_VMREAD_INVALID_COMPONENT
559	/** 13 VMWRITE to read-only VMCS component. */
560	#define VMX_ERROR_VMWRITE_READONLY_COMPONENT 13
561	/** 15 VMXON executed in VMX root operation. */
562	#define VMX_ERROR_VMXON_IN_VMX_ROOT_OP 15
563	/** 16 VM entry with invalid executive-VMCS pointer. */
564	#define VMX_ERROR_VMENTRY_INVALID_VMCS_EXEC_PTR 16
565	/** 17 VM entry with non-launched executive VMCS. */
566	#define VMX_ERROR_VMENTRY_NON_LAUNCHED_EXEC_VMCS 17
567	/** 18 VM entry with executive-VMCS pointer not VMXON pointer. */
568	#define VMX_ERROR_VMENTRY_EXEC_VMCS_PTR 18
569	/** 19 VMCALL with non-clear VMCS. */
570	#define VMX_ERROR_VMCALL_NON_CLEAR_VMCS 19
571	/** 20 VMCALL with invalid VM-exit control fields. */
572	#define VMX_ERROR_VMCALL_INVALID_VMEXIT_FIELDS 20
573	/** 22 VMCALL with incorrect MSEG revision identifier. */
574	#define VMX_ERROR_VMCALL_INVALID_MSEG_REVISION 22
575	/** 23 VMXOFF under dual-monitor treatment of SMIs and SMM. */
576	#define VMX_ERROR_VMXOFF_DUAL_MONITOR 23
577	/** 24 VMCALL with invalid SMM-monitor features. */
578	#define VMX_ERROR_VMCALL_INVALID_SMM_MONITOR 24
579	/** 25 VM entry with invalid VM-execution control fields in executive VMCS. */
580	#define VMX_ERROR_VMENTRY_INVALID_VM_EXEC_CTRL 25
581	/** 26 VM entry with events blocked by MOV SS. */
582	#define VMX_ERROR_VMENTRY_MOV_SS 26
583	/** 26 Invalid operand to INVEPT/INVVPID. */
584	#define VMX_ERROR_INVEPTVPID_INVALID_OPERAND 28
585
586	/** @} */
587
588
589	/** @name VMX MSRs - Basic VMX information.
590	* @{
591	*/
592	/** VMCS revision identifier used by the processor. */
593	#define MSR_IA32_VMX_BASIC_INFO_VMCS_ID(a) (a & 0x7FFFFFFF)
594	/** Size of the VMCS. */
595	#define MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(a) (((a) >> 32) & 0xFFF)
596	/** Width of physical address used for the VMCS.
597	* 0 -> limited to the available amount of physical ram
598	* 1 -> within the first 4 GB
599	*/
600	#define MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(a) (((a) >> 48) & 1)
601	/** Whether the processor supports the dual-monitor treatment of system-management interrupts and system-management code. (always 1) */
602	#define MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(a) (((a) >> 49) & 1)
603	/** Memory type that must be used for the VMCS. */
604	#define MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(a) (((a) >> 50) & 0xF)
605	/** @} */
606
607
608	/** @name VMX MSRs - Misc VMX info.
609	* @{
610	*/
611	/** Relationship between the preemption timer and tsc; count down every time bit x of the tsc changes. */
612	#define MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(a) ((a) & 0x1f)
613	/** Activity states supported by the implementation. */
614	#define MSR_IA32_VMX_MISC_ACTIVITY_STATES(a) (((a) >> 6) & 0x7)
615	/** Number of CR3 target values supported by the processor. (0-256) */
616	#define MSR_IA32_VMX_MISC_CR3_TARGET(a) (((a) >> 16) & 0x1FF)
617	/** Maximum nr of MSRs in the VMCS. (N+1)512. /
618	#define MSR_IA32_VMX_MISC_MAX_MSR(a) (((((a) >> 25) & 0x7) + 1) * 512)
619	/** MSEG revision identifier used by the processor. */
620	#define MSR_IA32_VMX_MISC_MSEG_ID(a) ((a) >> 32)
621	/** @} */
622
623
624	/** @name VMX MSRs - VMCS enumeration field info
625	* @{
626	*/
627	/** Highest field index. */
628	#define MSR_IA32_VMX_VMCS_ENUM_HIGHEST_INDEX(a) (((a) >> 1) & 0x1FF)
629
630	/** @} */
631
632
633	/** @name MSR_IA32_VMX_EPT_CAPS; EPT capabilities MSR
634	* @{
635	*/
636	#define MSR_IA32_VMX_EPT_CAPS_RWX_X_ONLY RT_BIT_64(0)
637	#define MSR_IA32_VMX_EPT_CAPS_RWX_W_ONLY RT_BIT_64(1)
638	#define MSR_IA32_VMX_EPT_CAPS_RWX_WX_ONLY RT_BIT_64(2)
639	#define MSR_IA32_VMX_EPT_CAPS_GAW_21_BITS RT_BIT_64(3)
640	#define MSR_IA32_VMX_EPT_CAPS_GAW_30_BITS RT_BIT_64(4)
641	#define MSR_IA32_VMX_EPT_CAPS_GAW_39_BITS RT_BIT_64(5)
642	#define MSR_IA32_VMX_EPT_CAPS_GAW_48_BITS RT_BIT_64(6)
643	#define MSR_IA32_VMX_EPT_CAPS_GAW_57_BITS RT_BIT_64(7)
644	#define MSR_IA32_VMX_EPT_CAPS_EMT_UC RT_BIT_64(8)
645	#define MSR_IA32_VMX_EPT_CAPS_EMT_WC RT_BIT_64(9)
646	#define MSR_IA32_VMX_EPT_CAPS_EMT_WT RT_BIT_64(12)
647	#define MSR_IA32_VMX_EPT_CAPS_EMT_WP RT_BIT_64(13)
648	#define MSR_IA32_VMX_EPT_CAPS_EMT_WB RT_BIT_64(14)
649	#define MSR_IA32_VMX_EPT_CAPS_SP_21_BITS RT_BIT_64(16)
650	#define MSR_IA32_VMX_EPT_CAPS_SP_30_BITS RT_BIT_64(17)
651	#define MSR_IA32_VMX_EPT_CAPS_SP_39_BITS RT_BIT_64(18)
652	#define MSR_IA32_VMX_EPT_CAPS_SP_48_BITS RT_BIT_64(19)
653	#define MSR_IA32_VMX_EPT_CAPS_INVEPT RT_BIT_64(20)
654	#define MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV RT_BIT_64(24)
655	#define MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT RT_BIT_64(25)
656	#define MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL RT_BIT_64(26)
657	#define MSR_IA32_VMX_EPT_CAPS_INVVPID RT_BIT_64(32)
658	#define MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV RT_BIT_64(40)
659	#define MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT RT_BIT_64(41)
660	#define MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL RT_BIT_64(42)
661	#define MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT_GLOBAL RT_BIT_64(43)
662
663	/** @} */
664
665	/** @name Extended Page Table Pointer (EPTP)
666	* @{
667	*/
668	/** Uncachable EPT paging structure memory type. */
669	#define VMX_EPT_MEMTYPE_UC 0
670	/** Write-back EPT paging structure memory type. */
671	#define VMX_EPT_MEMTYPE_WB 6
672	/** Shift value to get the EPT page walk length (bits 5-3) */
673	#define VMX_EPT_PAGE_WALK_LENGTH_SHIFT 3
674	/** Mask value to get the EPT page walk length (bits 5-3) */
675	#define VMX_EPT_PAGE_WALK_LENGTH_MASK 7
676	/** Default EPT page walk length */
677	#define VMX_EPT_PAGE_WALK_LENGTH_DEFAULT 3
678	/** @} */
679
680
681	/** @name VMCS field encoding - 16 bits guest fields
682	* @{
683	*/
684	#define VMX_VMCS16_GUEST_FIELD_VPID 0x0
685	#define VMX_VMCS16_GUEST_FIELD_ES 0x800
686	#define VMX_VMCS16_GUEST_FIELD_CS 0x802
687	#define VMX_VMCS16_GUEST_FIELD_SS 0x804
688	#define VMX_VMCS16_GUEST_FIELD_DS 0x806
689	#define VMX_VMCS16_GUEST_FIELD_FS 0x808
690	#define VMX_VMCS16_GUEST_FIELD_GS 0x80A
691	#define VMX_VMCS16_GUEST_FIELD_LDTR 0x80C
692	#define VMX_VMCS16_GUEST_FIELD_TR 0x80E
693	/** @} */
694
695	/** @name VMCS field encoding - 16 bits host fields
696	* @{
697	*/
698	#define VMX_VMCS16_HOST_FIELD_ES 0xC00
699	#define VMX_VMCS16_HOST_FIELD_CS 0xC02
700	#define VMX_VMCS16_HOST_FIELD_SS 0xC04
701	#define VMX_VMCS16_HOST_FIELD_DS 0xC06
702	#define VMX_VMCS16_HOST_FIELD_FS 0xC08
703	#define VMX_VMCS16_HOST_FIELD_GS 0xC0A
704	#define VMX_VMCS16_HOST_FIELD_TR 0xC0C
705	/** @} */
706
707	/** @name VMCS field encoding - 64 bits host fields
708	* @{
709	*/
710	#define VMX_VMCS_HOST_FIELD_PAT_FULL 0x2C00
711	#define VMX_VMCS_HOST_FIELD_PAT_HIGH 0x2C01
712	#define VMX_VMCS_HOST_FIELD_EFER_FULL 0x2C02
713	#define VMX_VMCS_HOST_FIELD_EFER_HIGH 0x2C03
714	#define VMX_VMCS_HOST_PERF_GLOBAL_CTRL_FULL 0x2C04 /*< MSR IA32_PERF_GLOBAL_CTRL /
715	#define VMX_VMCS_HOST_PERF_GLOBAL_CTRL_HIGH 0x2C05 /*< MSR IA32_PERF_GLOBAL_CTRL /
716	/** @} */
717
718
719	/** @name VMCS field encoding - 64 Bits control fields
720	* @{
721	*/
722	#define VMX_VMCS_CTRL_IO_BITMAP_A_FULL 0x2000
723	#define VMX_VMCS_CTRL_IO_BITMAP_A_HIGH 0x2001
724	#define VMX_VMCS_CTRL_IO_BITMAP_B_FULL 0x2002
725	#define VMX_VMCS_CTRL_IO_BITMAP_B_HIGH 0x2003
726
727	/* Optional */
728	#define VMX_VMCS_CTRL_MSR_BITMAP_FULL 0x2004
729	#define VMX_VMCS_CTRL_MSR_BITMAP_HIGH 0x2005
730
731	#define VMX_VMCS_CTRL_VMEXIT_MSR_STORE_FULL 0x2006
732	#define VMX_VMCS_CTRL_VMEXIT_MSR_STORE_HIGH 0x2007
733	#define VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_FULL 0x2008
734	#define VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_HIGH 0x2009
735
736	#define VMX_VMCS_CTRL_VMENTRY_MSR_LOAD_FULL 0x200A
737	#define VMX_VMCS_CTRL_VMENTRY_MSR_LOAD_HIGH 0x200B
738
739	#define VMX_VMCS_CTRL_EXEC_VMCS_PTR_FULL 0x200C
740	#define VMX_VMCS_CTRL_EXEC_VMCS_PTR_HIGH 0x200D
741
742	#define VMX_VMCS_CTRL_TSC_OFFSET_FULL 0x2010
743	#define VMX_VMCS_CTRL_TSC_OFFSET_HIGH 0x2011
744
745	/** Optional (VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW) */
746	#define VMX_VMCS_CTRL_VAPIC_PAGEADDR_FULL 0x2012
747	#define VMX_VMCS_CTRL_VAPIC_PAGEADDR_HIGH 0x2013
748
749	/** Optional (VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC) */
750	#define VMX_VMCS_CTRL_APIC_ACCESSADDR_FULL 0x2014
751	#define VMX_VMCS_CTRL_APIC_ACCESSADDR_HIGH 0x2015
752
753	/** Extended page table pointer. */
754	#define VMX_VMCS_CTRL_EPTP_FULL 0x201a
755	#define VMX_VMCS_CTRL_EPTP_HIGH 0x201b
756
757	/** VM-exit phyiscal address. */
758	#define VMX_VMCS_EXIT_PHYS_ADDR_FULL 0x2400
759	#define VMX_VMCS_EXIT_PHYS_ADDR_HIGH 0x2401
760	/** @} */
761
762
763	/** @name VMCS field encoding - 64 Bits guest fields
764	* @{
765	*/
766	#define VMX_VMCS_GUEST_LINK_PTR_FULL 0x2800
767	#define VMX_VMCS_GUEST_LINK_PTR_HIGH 0x2801
768	#define VMX_VMCS_GUEST_DEBUGCTL_FULL 0x2802 /*< MSR IA32_DEBUGCTL /
769	#define VMX_VMCS_GUEST_DEBUGCTL_HIGH 0x2803 /*< MSR IA32_DEBUGCTL /
770	#define VMX_VMCS_GUEST_PAT_FULL 0x2804
771	#define VMX_VMCS_GUEST_PAT_HIGH 0x2805
772	#define VMX_VMCS_GUEST_EFER_FULL 0x2806
773	#define VMX_VMCS_GUEST_EFER_HIGH 0x2807
774	#define VMX_VMCS_GUEST_PERF_GLOBAL_CTRL_FULL 0x2808 /*< MSR IA32_PERF_GLOBAL_CTRL /
775	#define VMX_VMCS_GUEST_PERF_GLOBAL_CTRL_HIGH 0x2809 /*< MSR IA32_PERF_GLOBAL_CTRL /
776	#define VMX_VMCS_GUEST_PDPTR0_FULL 0x280A
777	#define VMX_VMCS_GUEST_PDPTR0_HIGH 0x280B
778	#define VMX_VMCS_GUEST_PDPTR1_FULL 0x280C
779	#define VMX_VMCS_GUEST_PDPTR1_HIGH 0x280D
780	#define VMX_VMCS_GUEST_PDPTR2_FULL 0x280E
781	#define VMX_VMCS_GUEST_PDPTR2_HIGH 0x280F
782	#define VMX_VMCS_GUEST_PDPTR3_FULL 0x2810
783	#define VMX_VMCS_GUEST_PDPTR3_HIGH 0x2811
784	/** @} */
785
786
787	/** @name VMCS field encoding - 32 Bits control fields
788	* @{
789	*/
790	#define VMX_VMCS_CTRL_PIN_EXEC_CONTROLS 0x4000
791	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS 0x4002
792	#define VMX_VMCS_CTRL_EXCEPTION_BITMAP 0x4004
793	#define VMX_VMCS_CTRL_PAGEFAULT_ERROR_MASK 0x4006
794	#define VMX_VMCS_CTRL_PAGEFAULT_ERROR_MATCH 0x4008
795	#define VMX_VMCS_CTRL_CR3_TARGET_COUNT 0x400A
796	#define VMX_VMCS_CTRL_EXIT_CONTROLS 0x400C
797	#define VMX_VMCS_CTRL_EXIT_MSR_STORE_COUNT 0x400E
798	#define VMX_VMCS_CTRL_EXIT_MSR_LOAD_COUNT 0x4010
799	#define VMX_VMCS_CTRL_ENTRY_CONTROLS 0x4012
800	#define VMX_VMCS_CTRL_ENTRY_MSR_LOAD_COUNT 0x4014
801	#define VMX_VMCS_CTRL_ENTRY_IRQ_INFO 0x4016
802	#define VMX_VMCS_CTRL_ENTRY_EXCEPTION_ERRCODE 0x4018
803	#define VMX_VMCS_CTRL_ENTRY_INSTR_LENGTH 0x401A
804	/** This field exists only on processors that support the 1-setting of the use TPR shadow VM-execution control. */
805	#define VMX_VMCS_CTRL_TPR_THRESHOLD 0x401C
806	/** This field exists only on processors that support the 1-setting of the activate secondary controls VM-execution control. */
807	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS2 0x401E
808	/** @} */
809
810
811	/** @name VMX_VMCS_CTRL_PIN_EXEC_CONTROLS
812	* @{
813	*/
814	/** External interrupts cause VM exits if set; otherwise dispatched through the guest's IDT. */
815	#define VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT RT_BIT(0)
816	/** Non-maskable interrupts cause VM exits if set; otherwise dispatched through the guest's IDT. */
817	#define VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT RT_BIT(3)
818	/** Virtual NMIs. */
819	#define VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI RT_BIT(5)
820	/** Activate VMX preemption timer. */
821	#define VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER RT_BIT(6)
822	/* All other bits are reserved and must be set according to MSR IA32_VMX_PROCBASED_CTLS. */
823	/** @} */
824
825	/** @name VMX_VMCS_CTRL_PROC_EXEC_CONTROLS
826	* @{
827	*/
828	/** VM Exit as soon as RFLAGS.IF=1 and no blocking is active. */
829	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT RT_BIT(2)
830	/** Use timestamp counter offset. */
831	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET RT_BIT(3)
832	/** VM Exit when executing the HLT instruction. */
833	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT RT_BIT(7)
834	/** VM Exit when executing the INVLPG instruction. */
835	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT RT_BIT(9)
836	/** VM Exit when executing the MWAIT instruction. */
837	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT RT_BIT(10)
838	/** VM Exit when executing the RDPMC instruction. */
839	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT RT_BIT(11)
840	/** VM Exit when executing the RDTSC instruction. */
841	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT RT_BIT(12)
842	/** VM Exit when executing the MOV to CR3 instruction. (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
843	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT RT_BIT(15)
844	/** VM Exit when executing the MOV from CR3 instruction. (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
845	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT RT_BIT(16)
846	/** VM Exit on CR8 loads. */
847	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT RT_BIT(19)
848	/** VM Exit on CR8 stores. */
849	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT RT_BIT(20)
850	/** Use TPR shadow. */
851	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW RT_BIT(21)
852	/** VM Exit when virtual nmi blocking is disabled. */
853	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT RT_BIT(22)
854	/** VM Exit when executing a MOV DRx instruction. */
855	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT RT_BIT(23)
856	/** VM Exit when executing IO instructions. */
857	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT RT_BIT(24)
858	/** Use IO bitmaps. */
859	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS RT_BIT(25)
860	/** Monitor trap flag. */
861	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG RT_BIT(27)
862	/** Use MSR bitmaps. */
863	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS RT_BIT(28)
864	/** VM Exit when executing the MONITOR instruction. */
865	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT RT_BIT(29)
866	/** VM Exit when executing the PAUSE instruction. */
867	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT RT_BIT(30)
868	/** Determines whether the secondary processor based VM-execution controls are used. */
869	#define VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL RT_BIT(31)
870	/** @} */
871
872	/** @name VMX_VMCS_CTRL_PROC_EXEC_CONTROLS2
873	* @{
874	*/
875	/** Virtualize APIC access. */
876	#define VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC RT_BIT(0)
877	/** EPT supported/enabled. */
878	#define VMX_VMCS_CTRL_PROC_EXEC2_EPT RT_BIT(1)
879	/** Descriptor table instructions cause VM-exits. */
880	#define VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT RT_BIT(2)
881	/** RDTSCP causes a VM-exit. */
882	#define VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP_EXIT RT_BIT(3)
883	/** Virtualize x2APIC mode. */
884	#define VMX_VMCS_CTRL_PROC_EXEC2_X2APIC RT_BIT(4)
885	/** VPID supported/enabled. */
886	#define VMX_VMCS_CTRL_PROC_EXEC2_VPID RT_BIT(5)
887	/** VM Exit when executing the WBINVD instruction. */
888	#define VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT RT_BIT(6)
889	/** Unrestricted guest execution. */
890	#define VMX_VMCS_CTRL_PROC_EXEC2_REAL_MODE RT_BIT(7)
891	/** A specified nr of pause loops cause a VM-exit. */
892	#define VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT RT_BIT(10)
893	/** @} */
894
895
896	/** @name VMX_VMCS_CTRL_ENTRY_CONTROLS
897	* @{
898	*/
899	/** Load guest debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
900	#define VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG RT_BIT(2)
901	/** 64 bits guest mode. Must be 0 for CPUs that don't support AMD64. */
902	#define VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE RT_BIT(9)
903	/** In SMM mode after VM-entry. */
904	#define VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM RT_BIT(10)
905	/** Disable dual treatment of SMI and SMM; must be zero for VM-entry outside of SMM. */
906	#define VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON RT_BIT(11)
907	/** This control determines whether the guest IA32_PERF_GLOBAL_CTRL MSR is loaded on VM entry. */
908	#define VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR RT_BIT(13)
909	/** This control determines whether the guest IA32_PAT MSR is loaded on VM entry. */
910	#define VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR RT_BIT(14)
911	/** This control determines whether the guest IA32_EFER MSR is loaded on VM entry. */
912	#define VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR RT_BIT(15)
913	/** @} */
914
915
916	/** @name VMX_VMCS_CTRL_EXIT_CONTROLS
917	* @{
918	*/
919	/** Save guest debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
920	#define VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG RT_BIT(2)
921	/** Return to long mode after a VM-exit. */
922	#define VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64 RT_BIT(9)
923	/** This control determines whether the IA32_PERF_GLOBAL_CTRL MSR is loaded on VM exit. */
924	#define VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_PERF_MSR RT_BIT(12)
925	/** Acknowledge external interrupts with the irq controller if one caused a VM-exit. */
926	#define VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ RT_BIT(15)
927	/** This control determines whether the guest IA32_PAT MSR is saved on VM exit. */
928	#define VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR RT_BIT(18)
929	/** This control determines whether the host IA32_PAT MSR is loaded on VM exit. */
930	#define VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR RT_BIT(19)
931	/** This control determines whether the guest IA32_EFER MSR is saved on VM exit. */
932	#define VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR RT_BIT(20)
933	/** This control determines whether the host IA32_EFER MSR is loaded on VM exit. */
934	#define VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR RT_BIT(21)
935	/** This control determines whether the value of the VMX preemption timer is saved on VM exit. */
936	#define VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER RT_BIT(22)
937	/** @} */
938
939	/** @name VMCS field encoding - 32 Bits read-only fields
940	* @{
941	*/
942	#define VMX_VMCS32_RO_VM_INSTR_ERROR 0x4400
943	#define VMX_VMCS32_RO_EXIT_REASON 0x4402
944	#define VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO 0x4404
945	#define VMX_VMCS32_RO_EXIT_INTERRUPTION_ERRCODE 0x4406
946	#define VMX_VMCS32_RO_IDT_INFO 0x4408
947	#define VMX_VMCS32_RO_IDT_ERRCODE 0x440A
948	#define VMX_VMCS32_RO_EXIT_INSTR_LENGTH 0x440C
949	#define VMX_VMCS32_RO_EXIT_INSTR_INFO 0x440E
950	/** @} */
951
952	/** @name VMX_VMCS_RO_EXIT_INTERRUPTION_INFO
953	* @{
954	*/
955	#define VMX_EXIT_INTERRUPTION_INFO_VECTOR(a) (a & 0xff)
956	#define VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT 8
957	#define VMX_EXIT_INTERRUPTION_INFO_TYPE(a) ((a >> VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT) & 7)
958	#define VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID RT_BIT(11)
959	#define VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID(a) (a & VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID)
960	#define VMX_EXIT_INTERRUPTION_INFO_NMI_UNBLOCK(a) (a & RT_BIT(12))
961	#define VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT 31
962	#define VMX_EXIT_INTERRUPTION_INFO_VALID(a) (a & RT_BIT(31))
963	/** Construct an irq event injection value from the exit interruption info value (same except that bit 12 is reserved). */
964	#define VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(a) (a & ~RT_BIT(12))
965	/** @} */
966
967	/** @name VMX_VMCS_RO_EXIT_INTERRUPTION_INFO_TYPE
968	* @{
969	*/
970	#define VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT 0
971	#define VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI 2
972	#define VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT 3
973	#define VMX_EXIT_INTERRUPTION_INFO_TYPE_SW 4 /*< int xx /
974	#define VMX_EXIT_INTERRUPTION_INFO_TYPE_DBEXCPT 5 /*< Why are we getting this one?? /
975	#define VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT 6
976	/** @} */
977
978
979	/** @name VMCS field encoding - 32 Bits guest state fields
980	* @{
981	*/
982	#define VMX_VMCS32_GUEST_ES_LIMIT 0x4800
983	#define VMX_VMCS32_GUEST_CS_LIMIT 0x4802
984	#define VMX_VMCS32_GUEST_SS_LIMIT 0x4804
985	#define VMX_VMCS32_GUEST_DS_LIMIT 0x4806
986	#define VMX_VMCS32_GUEST_FS_LIMIT 0x4808
987	#define VMX_VMCS32_GUEST_GS_LIMIT 0x480A
988	#define VMX_VMCS32_GUEST_LDTR_LIMIT 0x480C
989	#define VMX_VMCS32_GUEST_TR_LIMIT 0x480E
990	#define VMX_VMCS32_GUEST_GDTR_LIMIT 0x4810
991	#define VMX_VMCS32_GUEST_IDTR_LIMIT 0x4812
992	#define VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS 0x4814
993	#define VMX_VMCS32_GUEST_CS_ACCESS_RIGHTS 0x4816
994	#define VMX_VMCS32_GUEST_SS_ACCESS_RIGHTS 0x4818
995	#define VMX_VMCS32_GUEST_DS_ACCESS_RIGHTS 0x481A
996	#define VMX_VMCS32_GUEST_FS_ACCESS_RIGHTS 0x481C
997	#define VMX_VMCS32_GUEST_GS_ACCESS_RIGHTS 0x481E
998	#define VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS 0x4820
999	#define VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS 0x4822
1000	#define VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE 0x4824
1001	#define VMX_VMCS32_GUEST_ACTIVITY_STATE 0x4826
1002	#define VMX_VMCS32_GUEST_SYSENTER_CS 0x482A /*< MSR IA32_SYSENTER_CS /
1003	#define VMX_VMCS32_GUEST_PREEMPTION_TIMER_VALUE 0x482E
1004	/** @} */
1005
1006
1007	/** @name VMX_VMCS_GUEST_ACTIVITY_STATE
1008	* @{
1009	*/
1010	/** The logical processor is active. */
1011	#define VMX_CMS_GUEST_ACTIVITY_ACTIVE 0x0
1012	/** The logical processor is inactive, because executed a HLT instruction. */
1013	#define VMX_CMS_GUEST_ACTIVITY_HLT 0x1
1014	/** The logical processor is inactive, because of a triple fault or other serious error. */
1015	#define VMX_CMS_GUEST_ACTIVITY_SHUTDOWN 0x2
1016	/** The logical processor is inactive, because it's waiting for a startup-IPI */
1017	#define VMX_CMS_GUEST_ACTIVITY_SIPI_WAIT 0x3
1018	/** @} */
1019
1020
1021	/** @name VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE
1022	* @{
1023	*/
1024	#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_STI RT_BIT(0)
1025	#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_MOVSS RT_BIT(1)
1026	#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_SMI RT_BIT(2)
1027	#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_NMI RT_BIT(3)
1028	/** @} */
1029
1030
1031	/** @name VMCS field encoding - 32 Bits host state fields
1032	* @{
1033	*/
1034	#define VMX_VMCS32_HOST_SYSENTER_CS 0x4C00
1035	/** @} */
1036
1037	/** @name Natural width control fields
1038	* @{
1039	*/
1040	#define VMX_VMCS_CTRL_CR0_MASK 0x6000
1041	#define VMX_VMCS_CTRL_CR4_MASK 0x6002
1042	#define VMX_VMCS_CTRL_CR0_READ_SHADOW 0x6004
1043	#define VMX_VMCS_CTRL_CR4_READ_SHADOW 0x6006
1044	#define VMX_VMCS_CTRL_CR3_TARGET_VAL0 0x6008
1045	#define VMX_VMCS_CTRL_CR3_TARGET_VAL1 0x600A
1046	#define VMX_VMCS_CTRL_CR3_TARGET_VAL2 0x600C
1047	#define VMX_VMCS_CTRL_CR3_TARGET_VAL31 0x600E
1048	/** @} */
1049
1050
1051	/** @name Natural width read-only data fields
1052	* @{
1053	*/
1054	#define VMX_VMCS_RO_EXIT_QUALIFICATION 0x6400
1055	#define VMX_VMCS_RO_IO_RCX 0x6402
1056	#define VMX_VMCS_RO_IO_RSX 0x6404
1057	#define VMX_VMCS_RO_IO_RDI 0x6406
1058	#define VMX_VMCS_RO_IO_RIP 0x6408
1059	#define VMX_VMCS_EXIT_GUEST_LINEAR_ADDR 0x640A
1060	/** @} */
1061
1062
1063	/** @name VMX_VMCS_RO_EXIT_QUALIFICATION
1064	* @{
1065	*/
1066	/** 0-2: Debug register number */
1067	#define VMX_EXIT_QUALIFICATION_DRX_REGISTER(a) (a & 7)
1068	/** 3: Reserved; cleared to 0. */
1069	#define VMX_EXIT_QUALIFICATION_DRX_RES1(a) ((a >> 3) & 1)
1070	/** 4: Direction of move (0 = write, 1 = read) */
1071	#define VMX_EXIT_QUALIFICATION_DRX_DIRECTION(a) ((a >> 4) & 1)
1072	/** 5-7: Reserved; cleared to 0. */
1073	#define VMX_EXIT_QUALIFICATION_DRX_RES2(a) ((a >> 5) & 7)
1074	/** 8-11: General purpose register number. */
1075	#define VMX_EXIT_QUALIFICATION_DRX_GENREG(a) ((a >> 8) & 0xF)
1076	/** Rest: reserved. */
1077	/** @} */
1078
1079	/** @name VMX_EXIT_QUALIFICATION_DRX_DIRECTION values
1080	* @{
1081	*/
1082	#define VMX_EXIT_QUALIFICATION_DRX_DIRECTION_WRITE 0
1083	#define VMX_EXIT_QUALIFICATION_DRX_DIRECTION_READ 1
1084	/** @} */
1085
1086
1087
1088	/** @name CRx accesses
1089	* @{
1090	*/
1091	/** 0-3: Control register number (0 for CLTS & LMSW) */
1092	#define VMX_EXIT_QUALIFICATION_CRX_REGISTER(a) (a & 0xF)
1093	/** 4-5: Access type. */
1094	#define VMX_EXIT_QUALIFICATION_CRX_ACCESS(a) ((a >> 4) & 3)
1095	/** 6: LMSW operand type */
1096	#define VMX_EXIT_QUALIFICATION_CRX_LMSW_OP(a) ((a >> 6) & 1)
1097	/** 7: Reserved; cleared to 0. */
1098	#define VMX_EXIT_QUALIFICATION_CRX_RES1(a) ((a >> 7) & 1)
1099	/** 8-11: General purpose register number (0 for CLTS & LMSW). */
1100	#define VMX_EXIT_QUALIFICATION_CRX_GENREG(a) ((a >> 8) & 0xF)
1101	/** 12-15: Reserved; cleared to 0. */
1102	#define VMX_EXIT_QUALIFICATION_CRX_RES2(a) ((a >> 12) & 0xF)
1103	/** 16-31: LMSW source data (else 0). */
1104	#define VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(a) ((a >> 16) & 0xFFFF)
1105	/** Rest: reserved. */
1106	/** @} */
1107
1108	/** @name VMX_EXIT_QUALIFICATION_CRX_ACCESS
1109	* @{
1110	*/
1111	#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_WRITE 0
1112	#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_READ 1
1113	#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_CLTS 2
1114	#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_LMSW 3
1115	/** @} */
1116
1117	/** @name VMX_EXIT_QUALIFICATION_TASK_SWITCH
1118	* @{
1119	*/
1120	#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_SELECTOR(a) (a & 0xffff)
1121	#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE(a) ((a >> 30)& 0x3)
1122	/** Task switch caused by a call instruction. */
1123	#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE_CALL 0
1124	/** Task switch caused by an iret instruction. */
1125	#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE_IRET 1
1126	/** Task switch caused by a jmp instruction. */
1127	#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE_JMP 2
1128	/** Task switch caused by an interrupt gate. */
1129	#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE_IDT 3
1130
1131	/** @} */
1132
1133
1134	/** @name VMX_EXIT_EPT_VIOLATION
1135	* @{
1136	*/
1137	/** Set if the violation was caused by a data read. */
1138	#define VMX_EXIT_QUALIFICATION_EPT_DATA_READ RT_BIT(0)
1139	/** Set if the violation was caused by a data write. */
1140	#define VMX_EXIT_QUALIFICATION_EPT_DATA_WRITE RT_BIT(1)
1141	/** Set if the violation was caused by an insruction fetch. */
1142	#define VMX_EXIT_QUALIFICATION_EPT_INSTR_FETCH RT_BIT(2)
1143	/** AND of the present bit of all EPT structures. */
1144	#define VMX_EXIT_QUALIFICATION_EPT_ENTRY_PRESENT RT_BIT(3)
1145	/** AND of the write bit of all EPT structures. */
1146	#define VMX_EXIT_QUALIFICATION_EPT_ENTRY_WRITE RT_BIT(4)
1147	/** AND of the execute bit of all EPT structures. */
1148	#define VMX_EXIT_QUALIFICATION_EPT_ENTRY_EXECUTE RT_BIT(5)
1149	/** Set if the guest linear address field contains the faulting address. */
1150	#define VMX_EXIT_QUALIFICATION_EPT_GUEST_ADDR_VALID RT_BIT(7)
1151	/** If bit 7 is one: (reserved otherwise)
1152	* 1 - violation due to physical address access.
1153	* 0 - violation caused by page walk or access/dirty bit updates
1154	*/
1155	#define VMX_EXIT_QUALIFICATION_EPT_TRANSLATED_ACCESS RT_BIT(8)
1156	/** @} */
1157
1158
1159	/** @name VMX_EXIT_PORT_IO
1160	* @{
1161	*/
1162	/** 0-2: IO operation width. */
1163	#define VMX_EXIT_QUALIFICATION_IO_WIDTH(a) (a & 7)
1164	/** 3: IO operation direction. */
1165	#define VMX_EXIT_QUALIFICATION_IO_DIRECTION(a) ((a >> 3) & 1)
1166	/** 4: String IO operation. */
1167	#define VMX_EXIT_QUALIFICATION_IO_STRING(a) ((a >> 4) & 1)
1168	/** 5: Repeated IO operation. */
1169	#define VMX_EXIT_QUALIFICATION_IO_REP(a) ((a >> 5) & 1)
1170	/** 6: Operand encoding. */
1171	#define VMX_EXIT_QUALIFICATION_IO_ENCODING(a) ((a >> 6) & 1)
1172	/** 16-31: IO Port (0-0xffff). */
1173	#define VMX_EXIT_QUALIFICATION_IO_PORT(a) ((a >> 16) & 0xffff)
1174	/* Rest reserved. */
1175	/** @} */
1176
1177	/** @name VMX_EXIT_QUALIFICATION_IO_DIRECTION
1178	* @{
1179	*/
1180	#define VMX_EXIT_QUALIFICATION_IO_DIRECTION_OUT 0
1181	#define VMX_EXIT_QUALIFICATION_IO_DIRECTION_IN 1
1182	/** @} */
1183
1184
1185	/** @name VMX_EXIT_QUALIFICATION_IO_ENCODING
1186	* @{
1187	*/
1188	#define VMX_EXIT_QUALIFICATION_IO_ENCODING_DX 0
1189	#define VMX_EXIT_QUALIFICATION_IO_ENCODING_IMM 1
1190	/** @} */
1191
1192	/** @name VMX_EXIT_APIC_ACCESS
1193	* @{
1194	*/
1195	/** 0-11: If the APIC-access VM exit is due to a linear access, the offset of access within the APIC page. */
1196	#define VMX_EXIT_QUALIFICATION_APIC_ACCESS_OFFSET(a) (a & 0xfff)
1197	/** 12-15: Access type. */
1198	#define VMX_EXIT_QUALIFICATION_APIC_ACCESS_TYPE(a) ((a >> 12) & 0xf)
1199	/* Rest reserved. */
1200	/** @} */
1201
1202
1203	/** @name VMX_EXIT_QUALIFICATION_APIC_ACCESS_TYPE; access types
1204	* @{
1205	*/
1206	/** Linear read access. */
1207	#define VMX_APIC_ACCESS_TYPE_LINEAR_READ 0
1208	/** Linear write access. */
1209	#define VMX_APIC_ACCESS_TYPE_LINEAR_WRITE 1
1210	/** Linear instruction fetch access. */
1211	#define VMX_APIC_ACCESS_TYPE_LINEAR_INSTR_FETCH 2
1212	/** Linear read/write access during event delivery. */
1213	#define VMX_APIC_ACCESS_TYPE_LINEAR_EVENT_DELIVERY 3
1214	/** Physical read/write access during event delivery. */
1215	#define VMX_APIC_ACCESS_TYPE_PHYSICAL_EVENT_DELIVERY 10
1216	/** Physical access for an instruction fetch or during instruction execution. */
1217	#define VMX_APIC_ACCESS_TYPE_PHYSICAL_INSTR 15
1218	/** @} */
1219
1220	/** @} */
1221
1222	/** @name VMCS field encoding - Natural width guest state fields
1223	* @{
1224	*/
1225	#define VMX_VMCS64_GUEST_CR0 0x6800
1226	#define VMX_VMCS64_GUEST_CR3 0x6802
1227	#define VMX_VMCS64_GUEST_CR4 0x6804
1228	#define VMX_VMCS64_GUEST_ES_BASE 0x6806
1229	#define VMX_VMCS64_GUEST_CS_BASE 0x6808
1230	#define VMX_VMCS64_GUEST_SS_BASE 0x680A
1231	#define VMX_VMCS64_GUEST_DS_BASE 0x680C
1232	#define VMX_VMCS64_GUEST_FS_BASE 0x680E
1233	#define VMX_VMCS64_GUEST_GS_BASE 0x6810
1234	#define VMX_VMCS64_GUEST_LDTR_BASE 0x6812
1235	#define VMX_VMCS64_GUEST_TR_BASE 0x6814
1236	#define VMX_VMCS64_GUEST_GDTR_BASE 0x6816
1237	#define VMX_VMCS64_GUEST_IDTR_BASE 0x6818
1238	#define VMX_VMCS64_GUEST_DR7 0x681A
1239	#define VMX_VMCS64_GUEST_RSP 0x681C
1240	#define VMX_VMCS64_GUEST_RIP 0x681E
1241	#define VMX_VMCS_GUEST_RFLAGS 0x6820
1242	#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS 0x6822
1243	#define VMX_VMCS64_GUEST_SYSENTER_ESP 0x6824 /*< MSR IA32_SYSENTER_ESP /
1244	#define VMX_VMCS64_GUEST_SYSENTER_EIP 0x6826 /*< MSR IA32_SYSENTER_EIP /
1245	/** @} */
1246
1247
1248	/** @name VMX_VMCS_GUEST_DEBUG_EXCEPTIONS
1249	* @{
1250	*/
1251	/** Hardware breakpoint 0 was met. */
1252	#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B0 RT_BIT(0)
1253	/** Hardware breakpoint 1 was met. */
1254	#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B1 RT_BIT(1)
1255	/** Hardware breakpoint 2 was met. */
1256	#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B2 RT_BIT(2)
1257	/** Hardware breakpoint 3 was met. */
1258	#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B3 RT_BIT(3)
1259	/** At least one data or IO breakpoint was hit. */
1260	#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_BREAKPOINT_ENABLED RT_BIT(12)
1261	/** A debug exception would have been triggered by single-step execution mode. */
1262	#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_BS RT_BIT(14)
1263	/** Bits 4-11, 13 and 15-63 are reserved. */
1264
1265	/** @} */
1266
1267	/** @name VMCS field encoding - Natural width host state fields
1268	* @{
1269	*/
1270	#define VMX_VMCS_HOST_CR0 0x6C00
1271	#define VMX_VMCS_HOST_CR3 0x6C02
1272	#define VMX_VMCS_HOST_CR4 0x6C04
1273	#define VMX_VMCS_HOST_FS_BASE 0x6C06
1274	#define VMX_VMCS_HOST_GS_BASE 0x6C08
1275	#define VMX_VMCS_HOST_TR_BASE 0x6C0A
1276	#define VMX_VMCS_HOST_GDTR_BASE 0x6C0C
1277	#define VMX_VMCS_HOST_IDTR_BASE 0x6C0E
1278	#define VMX_VMCS_HOST_SYSENTER_ESP 0x6C10
1279	#define VMX_VMCS_HOST_SYSENTER_EIP 0x6C12
1280	#define VMX_VMCS_HOST_RSP 0x6C14
1281	#define VMX_VMCS_HOST_RIP 0x6C16
1282	/** @} */
1283
1284	/** @} */
1285
1286
1287	#if RT_INLINE_ASM_GNU_STYLE
1288	# define __STR(x) #x
1289	# define STR(x) __STR(x)
1290	#endif
1291
1292
1293	/** @defgroup grp_vmx_asm vmx assembly helpers
1294	* @ingroup grp_vmx
1295	* @{
1296	*/
1297
1298	/**
1299	* Executes VMXON
1300	*
1301	* @returns VBox status code
1302	* @param pVMXOn Physical address of VMXON structure
1303	*/
1304	#if RT_INLINE_ASM_EXTERNAL \|\| HC_ARCH_BITS == 64 \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1305	DECLASM(int) VMXEnable(RTHCPHYS pVMXOn);
1306	#else
1307	DECLINLINE(int) VMXEnable(RTHCPHYS pVMXOn)
1308	{
1309	int rc = VINF_SUCCESS;
1310	# if RT_INLINE_ASM_GNU_STYLE
1311	__asm__ __volatile__ (
1312	"push %3 \n\t"
1313	"push %2 \n\t"
1314	".byte 0xF3, 0x0F, 0xC7, 0x34, 0x24 # VMXON [esp] \n\t"
1315	"ja 2f \n\t"
1316	"je 1f \n\t"
1317	"movl $"STR(VERR_VMX_INVALID_VMXON_PTR)", %0 \n\t"
1318	"jmp 2f \n\t"
1319	"1: \n\t"
1320	"movl $"STR(VERR_VMX_GENERIC)", %0 \n\t"
1321	"2: \n\t"
1322	"add $8, %%esp \n\t"
1323	:"=rm"(rc)
1324	:"0"(VINF_SUCCESS),
1325	"ir"((uint32_t)pVMXOn), /* don't allow direct memory reference here, */
1326	"ir"((uint32_t)(pVMXOn >> 32)) /* this would not work with -fomit-frame-pointer */
1327	:"memory"
1328	);
1329	# else
1330	__asm
1331	{
1332	push dword ptr [pVMXOn+4]
1333	push dword ptr [pVMXOn]
1334	_emit 0xF3
1335	_emit 0x0F
1336	_emit 0xC7
1337	_emit 0x34
1338	_emit 0x24 /* VMXON [esp] */
1339	jnc vmxon_good
1340	mov dword ptr [rc], VERR_VMX_INVALID_VMXON_PTR
1341	jmp the_end
1342
1343	vmxon_good:
1344	jnz the_end
1345	mov dword ptr [rc], VERR_VMX_GENERIC
1346	the_end:
1347	add esp, 8
1348	}
1349	# endif
1350	return rc;
1351	}
1352	#endif
1353
1354
1355	/**
1356	* Executes VMXOFF
1357	*/
1358	#if RT_INLINE_ASM_EXTERNAL \|\| HC_ARCH_BITS == 64 \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1359	DECLASM(void) VMXDisable(void);
1360	#else
1361	DECLINLINE(void) VMXDisable(void)
1362	{
1363	# if RT_INLINE_ASM_GNU_STYLE
1364	__asm__ __volatile__ (
1365	".byte 0x0F, 0x01, 0xC4 # VMXOFF \n\t"
1366	);
1367	# else
1368	__asm
1369	{
1370	_emit 0x0F
1371	_emit 0x01
1372	_emit 0xC4 /* VMXOFF */
1373	}
1374	# endif
1375	}
1376	#endif
1377
1378
1379	/**
1380	* Executes VMCLEAR
1381	*
1382	* @returns VBox status code
1383	* @param pVMCS Physical address of VM control structure
1384	*/
1385	#if RT_INLINE_ASM_EXTERNAL \|\| HC_ARCH_BITS == 64 \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1386	DECLASM(int) VMXClearVMCS(RTHCPHYS pVMCS);
1387	#else
1388	DECLINLINE(int) VMXClearVMCS(RTHCPHYS pVMCS)
1389	{
1390	int rc = VINF_SUCCESS;
1391	# if RT_INLINE_ASM_GNU_STYLE
1392	__asm__ __volatile__ (
1393	"push %3 \n\t"
1394	"push %2 \n\t"
1395	".byte 0x66, 0x0F, 0xC7, 0x34, 0x24 # VMCLEAR [esp] \n\t"
1396	"jnc 1f \n\t"
1397	"movl $"STR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
1398	"1: \n\t"
1399	"add $8, %%esp \n\t"
1400	:"=rm"(rc)
1401	:"0"(VINF_SUCCESS),
1402	"ir"((uint32_t)pVMCS), /* don't allow direct memory reference here, */
1403	"ir"((uint32_t)(pVMCS >> 32)) /* this would not work with -fomit-frame-pointer */
1404	:"memory"
1405	);
1406	# else
1407	__asm
1408	{
1409	push dword ptr [pVMCS+4]
1410	push dword ptr [pVMCS]
1411	_emit 0x66
1412	_emit 0x0F
1413	_emit 0xC7
1414	_emit 0x34
1415	_emit 0x24 /* VMCLEAR [esp] */
1416	jnc success
1417	mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
1418	success:
1419	add esp, 8
1420	}
1421	# endif
1422	return rc;
1423	}
1424	#endif
1425
1426
1427	/**
1428	* Executes VMPTRLD
1429	*
1430	* @returns VBox status code
1431	* @param pVMCS Physical address of VMCS structure
1432	*/
1433	#if RT_INLINE_ASM_EXTERNAL \|\| HC_ARCH_BITS == 64 \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1434	DECLASM(int) VMXActivateVMCS(RTHCPHYS pVMCS);
1435	#else
1436	DECLINLINE(int) VMXActivateVMCS(RTHCPHYS pVMCS)
1437	{
1438	int rc = VINF_SUCCESS;
1439	# if RT_INLINE_ASM_GNU_STYLE
1440	__asm__ __volatile__ (
1441	"push %3 \n\t"
1442	"push %2 \n\t"
1443	".byte 0x0F, 0xC7, 0x34, 0x24 # VMPTRLD [esp] \n\t"
1444	"jnc 1f \n\t"
1445	"movl $"STR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
1446	"1: \n\t"
1447	"add $8, %%esp \n\t"
1448	:"=rm"(rc)
1449	:"0"(VINF_SUCCESS),
1450	"ir"((uint32_t)pVMCS), /* don't allow direct memory reference here, */
1451	"ir"((uint32_t)(pVMCS >> 32)) /* this will not work with -fomit-frame-pointer */
1452	);
1453	# else
1454	__asm
1455	{
1456	push dword ptr [pVMCS+4]
1457	push dword ptr [pVMCS]
1458	_emit 0x0F
1459	_emit 0xC7
1460	_emit 0x34
1461	_emit 0x24 /* VMPTRLD [esp] */
1462	jnc success
1463	mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
1464
1465	success:
1466	add esp, 8
1467	}
1468	# endif
1469	return rc;
1470	}
1471	#endif
1472
1473	/**
1474	* Executes VMPTRST
1475	*
1476	* @returns VBox status code
1477	* @param pVMCS Address that will receive the current pointer
1478	*/
1479	DECLASM(int) VMXGetActivateVMCS(RTHCPHYS *pVMCS);
1480
1481	/**
1482	* Executes VMWRITE
1483	*
1484	* @returns VBox status code
1485	* @param idxField VMCS index
1486	* @param u32Val 32 bits value
1487	*/
1488	#if RT_INLINE_ASM_EXTERNAL \|\| HC_ARCH_BITS == 64 \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1489	DECLASM(int) VMXWriteVMCS32(uint32_t idxField, uint32_t u32Val);
1490	#else
1491	DECLINLINE(int) VMXWriteVMCS32(uint32_t idxField, uint32_t u32Val)
1492	{
1493	int rc = VINF_SUCCESS;
1494	# if RT_INLINE_ASM_GNU_STYLE
1495	__asm__ __volatile__ (
1496	".byte 0x0F, 0x79, 0xC2 # VMWRITE eax, edx \n\t"
1497	"ja 2f \n\t"
1498	"je 1f \n\t"
1499	"movl $"STR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
1500	"jmp 2f \n\t"
1501	"1: \n\t"
1502	"movl $"STR(VERR_VMX_INVALID_VMCS_FIELD)", %0 \n\t"
1503	"2: \n\t"
1504	:"=rm"(rc)
1505	:"0"(VINF_SUCCESS),
1506	"a"(idxField),
1507	"d"(u32Val)
1508	);
1509	# else
1510	__asm
1511	{
1512	push dword ptr [u32Val]
1513	mov eax, [idxField]
1514	_emit 0x0F
1515	_emit 0x79
1516	_emit 0x04
1517	_emit 0x24 /* VMWRITE eax, [esp] */
1518	jnc valid_vmcs
1519	mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
1520	jmp the_end
1521
1522	valid_vmcs:
1523	jnz the_end
1524	mov dword ptr [rc], VERR_VMX_INVALID_VMCS_FIELD
1525	the_end:
1526	add esp, 4
1527	}
1528	# endif
1529	return rc;
1530	}
1531	#endif
1532
1533	/**
1534	* Executes VMWRITE
1535	*
1536	* @returns VBox status code
1537	* @param idxField VMCS index
1538	* @param u64Val 16, 32 or 64 bits value
1539	*/
1540	#if HC_ARCH_BITS == 64 \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1541	DECLASM(int) VMXWriteVMCS64(uint32_t idxField, uint64_t u64Val);
1542	#else
1543	VMMR0DECL(int) VMXWriteVMCS64Ex(PVMCPU pVCpu, uint32_t idxField, uint64_t u64Val);
1544
1545	#define VMXWriteVMCS64(idxField, u64Val) VMXWriteVMCS64Ex(pVCpu, idxField, u64Val)
1546	#endif
1547
1548	#if HC_ARCH_BITS == 64
1549	#define VMXWriteVMCS VMXWriteVMCS64
1550	#else
1551	#define VMXWriteVMCS VMXWriteVMCS32
1552	#endif /* HC_ARCH_BITS == 64 */
1553
1554
1555	/**
1556	* Invalidate a page using invept
1557	* @returns VBox status code
1558	* @param enmFlush Type of flush
1559	* @param pDescriptor Descriptor
1560	*/
1561	DECLASM(int) VMXR0InvEPT(VMX_FLUSH enmFlush, uint64_t *pDescriptor);
1562
1563	/**
1564	* Invalidate a page using invvpid
1565	* @returns VBox status code
1566	* @param enmFlush Type of flush
1567	* @param pDescriptor Descriptor
1568	*/
1569	DECLASM(int) VMXR0InvVPID(VMX_FLUSH enmFlush, uint64_t *pDescriptor);
1570
1571	/**
1572	* Executes VMREAD
1573	*
1574	* @returns VBox status code
1575	* @param idxField VMCS index
1576	* @param pData Ptr to store VM field value
1577	*/
1578	#if RT_INLINE_ASM_EXTERNAL \|\| HC_ARCH_BITS == 64 \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1579	DECLASM(int) VMXReadVMCS32(uint32_t idxField, uint32_t *pData);
1580	#else
1581	DECLINLINE(int) VMXReadVMCS32(uint32_t idxField, uint32_t *pData)
1582	{
1583	int rc = VINF_SUCCESS;
1584	# if RT_INLINE_ASM_GNU_STYLE
1585	__asm__ __volatile__ (
1586	"movl $"STR(VINF_SUCCESS)", %0 \n\t"
1587	".byte 0x0F, 0x78, 0xc2 # VMREAD eax, edx \n\t"
1588	"ja 2f \n\t"
1589	"je 1f \n\t"
1590	"movl $"STR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
1591	"jmp 2f \n\t"
1592	"1: \n\t"
1593	"movl $"STR(VERR_VMX_INVALID_VMCS_FIELD)", %0 \n\t"
1594	"2: \n\t"
1595	:"=&r"(rc),
1596	"=d"(*pData)
1597	:"a"(idxField),
1598	"d"(0)
1599	);
1600	# else
1601	__asm
1602	{
1603	sub esp, 4
1604	mov dword ptr [esp], 0
1605	mov eax, [idxField]
1606	_emit 0x0F
1607	_emit 0x78
1608	_emit 0x04
1609	_emit 0x24 /* VMREAD eax, [esp] */
1610	mov edx, pData
1611	pop dword ptr [edx]
1612	jnc valid_vmcs
1613	mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
1614	jmp the_end
1615
1616	valid_vmcs:
1617	jnz the_end
1618	mov dword ptr [rc], VERR_VMX_INVALID_VMCS_FIELD
1619	the_end:
1620	}
1621	# endif
1622	return rc;
1623	}
1624	#endif
1625
1626	/**
1627	* Executes VMREAD
1628	*
1629	* @returns VBox status code
1630	* @param idxField VMCS index
1631	* @param pData Ptr to store VM field value
1632	*/
1633	#if HC_ARCH_BITS == 64 \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1634	DECLASM(int) VMXReadVMCS64(uint32_t idxField, uint64_t *pData);
1635	#else
1636	DECLINLINE(int) VMXReadVMCS64(uint32_t idxField, uint64_t *pData)
1637	{
1638	int rc;
1639
1640	uint32_t val_hi, val;
1641	rc = VMXReadVMCS32(idxField, &val);
1642	rc \|= VMXReadVMCS32(idxField + 1, &val_hi);
1643	AssertRC(rc);
1644	*pData = RT_MAKE_U64(val, val_hi);
1645	return rc;
1646	}
1647	#endif
1648
1649	#if HC_ARCH_BITS == 64
1650	# define VMXReadVMCS VMXReadVMCS64
1651	#else
1652	# define VMXReadVMCS VMXReadVMCS32
1653	#endif /* HC_ARCH_BITS == 64 */
1654
1655	/**
1656	* Gets the last instruction error value from the current VMCS
1657	*
1658	* @returns error value
1659	*/
1660	DECLINLINE(uint32_t) VMXGetLastError(void)
1661	{
1662	#if HC_ARCH_BITS == 64
1663	uint64_t uLastError = 0;
1664	int rc = VMXReadVMCS(VMX_VMCS32_RO_VM_INSTR_ERROR, &uLastError);
1665	AssertRC(rc);
1666	return (uint32_t)uLastError;
1667
1668	#else /* 32-bit host: */
1669	uint32_t uLastError = 0;
1670	int rc = VMXReadVMCS32(VMX_VMCS32_RO_VM_INSTR_ERROR, &uLastError);
1671	AssertRC(rc);
1672	return uLastError;
1673	#endif
1674	}
1675
1676	#ifdef IN_RING0
1677	VMMR0DECL(int) VMXR0InvalidatePage(PVM pVM, PVMCPU pVCpu, RTGCPTR GCVirt);
1678	VMMR0DECL(int) VMXR0InvalidatePhysPage(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys);
1679	#endif /* IN_RING0 */
1680
1681	/** @} */
1682
1683	#endif
1684

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source: vbox/trunk/include/VBox/hwacc_vmx.h@ 32780

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