iommu-amd.h@ 86065

Last change on this file since 86065 was 86030, checked in by vboxsync, 4 years ago
AMD IOMMU: bugref:9654 Fix IOMMU_DTE_QWORD_2_VALID_MASK.
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File size: 118.1 KB

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1	/** @file
2	* IOMMU - Input/Output Memory Management Unit (AMD).
3	*/
4
5	/*
6	* Copyright (C) 2020 Oracle Corporation
7	*
8	* This file is part of VirtualBox Open Source Edition (OSE), as
9	* available from http://www.virtualbox.org. This file is free software;
10	* you can redistribute it and/or modify it under the terms of the GNU
11	* General Public License (GPL) as published by the Free Software
12	* Foundation, in version 2 as it comes in the "COPYING" file of the
13	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15	*
16	* The contents of this file may alternatively be used under the terms
17	* of the Common Development and Distribution License Version 1.0
18	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19	* VirtualBox OSE distribution, in which case the provisions of the
20	* CDDL are applicable instead of those of the GPL.
21	*
22	* You may elect to license modified versions of this file under the
23	* terms and conditions of either the GPL or the CDDL or both.
24	*/
25
26	#ifndef VBOX_INCLUDED_iommu_amd_h
27	#define VBOX_INCLUDED_iommu_amd_h
28	#ifndef RT_WITHOUT_PRAGMA_ONCE
29	# pragma once
30	#endif
31
32	#include <iprt/types.h>
33	#include <iprt/assertcompile.h>
34
35	/**
36	* @name PCI configuration register offsets.
37	* In accordance with the AMD spec.
38	* @{
39	*/
40	#define IOMMU_PCI_OFF_CAP_HDR 0x40
41	#define IOMMU_PCI_OFF_BASE_ADDR_REG_LO 0x44
42	#define IOMMU_PCI_OFF_BASE_ADDR_REG_HI 0x48
43	#define IOMMU_PCI_OFF_RANGE_REG 0x4c
44	#define IOMMU_PCI_OFF_MISCINFO_REG_0 0x50
45	#define IOMMU_PCI_OFF_MISCINFO_REG_1 0x54
46	#define IOMMU_PCI_OFF_MSI_CAP_HDR 0x64
47	#define IOMMU_PCI_OFF_MSI_ADDR_LO 0x68
48	#define IOMMU_PCI_OFF_MSI_ADDR_HI 0x6c
49	#define IOMMU_PCI_OFF_MSI_DATA 0x70
50	#define IOMMU_PCI_OFF_MSI_MAP_CAP_HDR 0x74
51	/** @} */
52
53	/**
54	* @name MMIO register offsets.
55	* In accordance with the AMD spec.
56	* @{
57	*/
58	#define IOMMU_MMIO_OFF_DEV_TAB_BAR 0x00
59	#define IOMMU_MMIO_OFF_CMD_BUF_BAR 0x08
60	#define IOMMU_MMIO_OFF_EVT_LOG_BAR 0x10
61	#define IOMMU_MMIO_OFF_CTRL 0x18
62	#define IOMMU_MMIO_OFF_EXCL_BAR 0x20
63	#define IOMMU_MMIO_OFF_EXCL_RANGE_LIMIT 0x28
64	#define IOMMU_MMIO_OFF_EXT_FEAT 0x30
65
66	#define IOMMU_MMIO_OFF_PPR_LOG_BAR 0x38
67	#define IOMMU_MMIO_OFF_HW_EVT_HI 0x40
68	#define IOMMU_MMIO_OFF_HW_EVT_LO 0x48
69	#define IOMMU_MMIO_OFF_HW_EVT_STATUS 0x50
70
71	#define IOMMU_MMIO_OFF_SMI_FLT_FIRST 0x60
72	#define IOMMU_MMIO_OFF_SMI_FLT_LAST 0xd8
73
74	#define IOMMU_MMIO_OFF_GALOG_BAR 0xe0
75	#define IOMMU_MMIO_OFF_GALOG_TAIL_ADDR 0xe8
76
77	#define IOMMU_MMIO_OFF_PPR_LOG_B_BAR 0xf0
78	#define IOMMU_MMIO_OFF_PPR_EVT_B_BAR 0xf8
79
80	#define IOMMU_MMIO_OFF_DEV_TAB_SEG_FIRST 0x100
81	#define IOMMU_MMIO_OFF_DEV_TAB_SEG_1 0x100
82	#define IOMMU_MMIO_OFF_DEV_TAB_SEG_2 0x108
83	#define IOMMU_MMIO_OFF_DEV_TAB_SEG_3 0x110
84	#define IOMMU_MMIO_OFF_DEV_TAB_SEG_4 0x118
85	#define IOMMU_MMIO_OFF_DEV_TAB_SEG_5 0x120
86	#define IOMMU_MMIO_OFF_DEV_TAB_SEG_6 0x128
87	#define IOMMU_MMIO_OFF_DEV_TAB_SEG_7 0x130
88	#define IOMMU_MMIO_OFF_DEV_TAB_SEG_LAST 0x130
89
90	#define IOMMU_MMIO_OFF_DEV_SPECIFIC_FEAT 0x138
91	#define IOMMU_MMIO_OFF_DEV_SPECIFIC_CTRL 0x140
92	#define IOMMU_MMIO_OFF_DEV_SPECIFIC_STATUS 0x148
93
94	#define IOMMU_MMIO_OFF_MSI_VECTOR_0 0x150
95	#define IOMMU_MMIO_OFF_MSI_VECTOR_1 0x154
96	#define IOMMU_MMIO_OFF_MSI_CAP_HDR 0x158
97	#define IOMMU_MMIO_OFF_MSI_ADDR_LO 0x15c
98	#define IOMMU_MMIO_OFF_MSI_ADDR_HI 0x160
99	#define IOMMU_MMIO_OFF_MSI_DATA 0x164
100	#define IOMMU_MMIO_OFF_MSI_MAPPING_CAP_HDR 0x168
101
102	#define IOMMU_MMIO_OFF_PERF_OPT_CTRL 0x16c
103
104	#define IOMMU_MMIO_OFF_XT_GEN_INTR_CTRL 0x170
105	#define IOMMU_MMIO_OFF_XT_PPR_INTR_CTRL 0x178
106	#define IOMMU_MMIO_OFF_XT_GALOG_INT_CTRL 0x180
107
108	#define IOMMU_MMIO_OFF_MARC_APER_BAR_0 0x200
109	#define IOMMU_MMIO_OFF_MARC_APER_RELOC_0 0x208
110	#define IOMMU_MMIO_OFF_MARC_APER_LEN_0 0x210
111	#define IOMMU_MMIO_OFF_MARC_APER_BAR_1 0x218
112	#define IOMMU_MMIO_OFF_MARC_APER_RELOC_1 0x220
113	#define IOMMU_MMIO_OFF_MARC_APER_LEN_1 0x228
114	#define IOMMU_MMIO_OFF_MARC_APER_BAR_2 0x230
115	#define IOMMU_MMIO_OFF_MARC_APER_RELOC_2 0x238
116	#define IOMMU_MMIO_OFF_MARC_APER_LEN_2 0x240
117	#define IOMMU_MMIO_OFF_MARC_APER_BAR_3 0x248
118	#define IOMMU_MMIO_OFF_MARC_APER_RELOC_3 0x250
119	#define IOMMU_MMIO_OFF_MARC_APER_LEN_3 0x258
120
121	#define IOMMU_MMIO_OFF_RSVD_REG 0x1ff8
122
123	#define IOMMU_MMIO_CMD_BUF_HEAD_PTR 0x2000
124	#define IOMMU_MMIO_CMD_BUF_TAIL_PTR 0x2008
125	#define IOMMU_MMIO_EVT_LOG_HEAD_PTR 0x2010
126	#define IOMMU_MMIO_EVT_LOG_TAIL_PTR 0x2018
127
128	#define IOMMU_MMIO_OFF_STATUS 0x2020
129
130	#define IOMMU_MMIO_OFF_PPR_LOG_HEAD_PTR 0x2030
131	#define IOMMU_MMIO_OFF_PPR_LOG_TAIL_PTR 0x2038
132
133	#define IOMMU_MMIO_OFF_GALOG_HEAD_PTR 0x2040
134	#define IOMMU_MMIO_OFF_GALOG_TAIL_PTR 0x2048
135
136	#define IOMMU_MMIO_OFF_PPR_LOG_B_HEAD_PTR 0x2050
137	#define IOMMU_MMIO_OFF_PPR_LOG_B_TAIL_PTR 0x2058
138
139	#define IOMMU_MMIO_OFF_EVT_LOG_B_HEAD_PTR 0x2070
140	#define IOMMU_MMIO_OFF_EVT_LOG_B_TAIL_PTR 0x2078
141
142	#define IOMMU_MMIO_OFF_PPR_LOG_AUTO_RESP 0x2080
143	#define IOMMU_MMIO_OFF_PPR_LOG_OVERFLOW_EARLY 0x2088
144	#define IOMMU_MMIO_OFF_PPR_LOG_B_OVERFLOW_EARLY 0x2090
145	/** @} */
146
147	/**
148	* @name MMIO register-access table offsets.
149	* Each table [first..last] (both inclusive) represents the range of registers
150	* covered by a distinct register-access table. This is done due to arbitrary large
151	* gaps in the MMIO register offsets themselves.
152	* @{
153	*/
154	#define IOMMU_MMIO_OFF_TABLE_0_FIRST 0x00
155	#define IOMMU_MMIO_OFF_TABLE_0_LAST 0x258
156
157	#define IOMMU_MMIO_OFF_TABLE_1_FIRST 0x1ff8
158	#define IOMMU_MMIO_OFF_TABLE_1_LAST 0x2090
159	/** @} */
160
161	/**
162	* @name Commands.
163	* In accordance with the AMD spec.
164	* @{
165	*/
166	#define IOMMU_CMD_COMPLETION_WAIT 0x01
167	#define IOMMU_CMD_INV_DEV_TAB_ENTRY 0x02
168	#define IOMMU_CMD_INV_IOMMU_PAGES 0x03
169	#define IOMMU_CMD_INV_IOTLB_PAGES 0x04
170	#define IOMMU_CMD_INV_INTR_TABLE 0x05
171	#define IOMMU_CMD_PREFETCH_IOMMU_PAGES 0x06
172	#define IOMMU_CMD_COMPLETE_PPR_REQ 0x07
173	#define IOMMU_CMD_INV_IOMMU_ALL 0x08
174	/** @} */
175
176	/**
177	* @name Event codes.
178	* In accordance with the AMD spec.
179	* @{
180	*/
181	#define IOMMU_EVT_ILLEGAL_DEV_TAB_ENTRY 0x01
182	#define IOMMU_EVT_IO_PAGE_FAULT 0x02
183	#define IOMMU_EVT_DEV_TAB_HW_ERROR 0x03
184	#define IOMMU_EVT_PAGE_TAB_HW_ERROR 0x04
185	#define IOMMU_EVT_ILLEGAL_CMD_ERROR 0x05
186	#define IOMMU_EVT_COMMAND_HW_ERROR 0x06
187	#define IOMMU_EVT_IOTLB_INV_TIMEOUT 0x07
188	#define IOMMU_EVT_INVALID_DEV_REQ 0x08
189	#define IOMMU_EVT_INVALID_PPR_REQ 0x09
190	#define IOMMU_EVT_EVENT_COUNTER_ZERO 0x10
191	#define IOMMU_EVT_GUEST_EVENT_FAULT 0x11
192	/** @} */
193
194	/**
195	* @name IOMMU Capability Header.
196	* In accordance with the AMD spec.
197	* @{
198	*/
199	/** CapId: Capability ID. */
200	#define IOMMU_BF_CAPHDR_CAP_ID_SHIFT 0
201	#define IOMMU_BF_CAPHDR_CAP_ID_MASK UINT32_C(0x000000ff)
202	/** CapPtr: Capability Pointer. */
203	#define IOMMU_BF_CAPHDR_CAP_PTR_SHIFT 8
204	#define IOMMU_BF_CAPHDR_CAP_PTR_MASK UINT32_C(0x0000ff00)
205	/** CapType: Capability Type. */
206	#define IOMMU_BF_CAPHDR_CAP_TYPE_SHIFT 16
207	#define IOMMU_BF_CAPHDR_CAP_TYPE_MASK UINT32_C(0x00070000)
208	/** CapRev: Capability Revision. */
209	#define IOMMU_BF_CAPHDR_CAP_REV_SHIFT 19
210	#define IOMMU_BF_CAPHDR_CAP_REV_MASK UINT32_C(0x00f80000)
211	/** IoTlbSup: IO TLB Support. */
212	#define IOMMU_BF_CAPHDR_IOTLB_SUP_SHIFT 24
213	#define IOMMU_BF_CAPHDR_IOTLB_SUP_MASK UINT32_C(0x01000000)
214	/** HtTunnel: HyperTransport Tunnel translation support. */
215	#define IOMMU_BF_CAPHDR_HT_TUNNEL_SHIFT 25
216	#define IOMMU_BF_CAPHDR_HT_TUNNEL_MASK UINT32_C(0x02000000)
217	/** NpCache: Not Present table entries Cached. */
218	#define IOMMU_BF_CAPHDR_NP_CACHE_SHIFT 26
219	#define IOMMU_BF_CAPHDR_NP_CACHE_MASK UINT32_C(0x04000000)
220	/** EFRSup: Extended Feature Register (EFR) Supported. */
221	#define IOMMU_BF_CAPHDR_EFR_SUP_SHIFT 27
222	#define IOMMU_BF_CAPHDR_EFR_SUP_MASK UINT32_C(0x08000000)
223	/** CapExt: Miscellaneous Information Register Supported . */
224	#define IOMMU_BF_CAPHDR_CAP_EXT_SHIFT 28
225	#define IOMMU_BF_CAPHDR_CAP_EXT_MASK UINT32_C(0x10000000)
226	/** Bits 31:29 reserved. */
227	#define IOMMU_BF_CAPHDR_RSVD_29_31_SHIFT 29
228	#define IOMMU_BF_CAPHDR_RSVD_29_31_MASK UINT32_C(0xe0000000)
229	RT_BF_ASSERT_COMPILE_CHECKS(IOMMU_BF_CAPHDR_, UINT32_C(0), UINT32_MAX,
230	(CAP_ID, CAP_PTR, CAP_TYPE, CAP_REV, IOTLB_SUP, HT_TUNNEL, NP_CACHE, EFR_SUP, CAP_EXT, RSVD_29_31));
231	/** @} */
232
233	/**
234	* @name IOMMU Base Address Low Register.
235	* In accordance with the AMD spec.
236	* @{
237	*/
238	/** Enable: Enables access to the address specified in the Base Address Register. */
239	#define IOMMU_BF_BASEADDR_LO_ENABLE_SHIFT 0
240	#define IOMMU_BF_BASEADDR_LO_ENABLE_MASK UINT32_C(0x00000001)
241	/** Bits 13:1 reserved. */
242	#define IOMMU_BF_BASEADDR_LO_RSVD_1_13_SHIFT 1
243	#define IOMMU_BF_BASEADDR_LO_RSVD_1_13_MASK UINT32_C(0x00003ffe)
244	/** Base Address[31:14]: Low Base address of IOMMU MMIO control registers. */
245	#define IOMMU_BF_BASEADDR_LO_ADDR_SHIFT 14
246	#define IOMMU_BF_BASEADDR_LO_ADDR_MASK UINT32_C(0xffffc000)
247	RT_BF_ASSERT_COMPILE_CHECKS(IOMMU_BF_BASEADDR_LO_, UINT32_C(0), UINT32_MAX,
248	(ENABLE, RSVD_1_13, ADDR));
249	/** @} */
250
251	/**
252	* @name IOMMU Range Register.
253	* In accordance with the AMD spec.
254	* @{
255	*/
256	/** UnitID: HyperTransport Unit ID. */
257	#define IOMMU_BF_RANGE_UNIT_ID_SHIFT 0
258	#define IOMMU_BF_RANGE_UNIT_ID_MASK UINT32_C(0x0000001f)
259	/** Bits 6:5 reserved. */
260	#define IOMMU_BF_RANGE_RSVD_5_6_SHIFT 5
261	#define IOMMU_BF_RANGE_RSVD_5_6_MASK UINT32_C(0x00000060)
262	/** RngValid: Range valid. */
263	#define IOMMU_BF_RANGE_VALID_SHIFT 7
264	#define IOMMU_BF_RANGE_VALID_MASK UINT32_C(0x00000080)
265	/** BusNumber: Device range bus number. */
266	#define IOMMU_BF_RANGE_BUS_NUMBER_SHIFT 8
267	#define IOMMU_BF_RANGE_BUS_NUMBER_MASK UINT32_C(0x0000ff00)
268	/** First Device. */
269	#define IOMMU_BF_RANGE_FIRST_DEVICE_SHIFT 16
270	#define IOMMU_BF_RANGE_FIRST_DEVICE_MASK UINT32_C(0x00ff0000)
271	/** Last Device. */
272	#define IOMMU_BF_RANGE_LAST_DEVICE_SHIFT 24
273	#define IOMMU_BF_RANGE_LAST_DEVICE_MASK UINT32_C(0xff000000)
274	RT_BF_ASSERT_COMPILE_CHECKS(IOMMU_BF_RANGE_, UINT32_C(0), UINT32_MAX,
275	(UNIT_ID, RSVD_5_6, VALID, BUS_NUMBER, FIRST_DEVICE, LAST_DEVICE));
276	/** @} */
277
278	/**
279	* @name IOMMU Miscellaneous Information Register 0.
280	* In accordance with the AMD spec.
281	* @{
282	*/
283	/** MsiNum: MSI message number. */
284	#define IOMMU_BF_MISCINFO_0_MSI_NUM_SHIFT 0
285	#define IOMMU_BF_MISCINFO_0_MSI_NUM_MASK UINT32_C(0x0000001f)
286	/** GvaSize: Guest Virtual Address Size. */
287	#define IOMMU_BF_MISCINFO_0_GVA_SIZE_SHIFT 5
288	#define IOMMU_BF_MISCINFO_0_GVA_SIZE_MASK UINT32_C(0x000000e0)
289	/** PaSize: Physical Address Size. */
290	#define IOMMU_BF_MISCINFO_0_PA_SIZE_SHIFT 8
291	#define IOMMU_BF_MISCINFO_0_PA_SIZE_MASK UINT32_C(0x00007f00)
292	/** VaSize: Virtual Address Size. */
293	#define IOMMU_BF_MISCINFO_0_VA_SIZE_SHIFT 15
294	#define IOMMU_BF_MISCINFO_0_VA_SIZE_MASK UINT32_C(0x003f8000)
295	/** HtAtsResv: HyperTransport ATS Response Address range Reserved. */
296	#define IOMMU_BF_MISCINFO_0_HT_ATS_RESV_SHIFT 22
297	#define IOMMU_BF_MISCINFO_0_HT_ATS_RESV_MASK UINT32_C(0x00400000)
298	/** Bits 26:23 reserved. */
299	#define IOMMU_BF_MISCINFO_0_RSVD_23_26_SHIFT 23
300	#define IOMMU_BF_MISCINFO_0_RSVD_23_26_MASK UINT32_C(0x07800000)
301	/** MsiNumPPR: Peripheral Page Request MSI message number. */
302	#define IOMMU_BF_MISCINFO_0_MSI_NUM_PPR_SHIFT 27
303	#define IOMMU_BF_MISCINFO_0_MSI_NUM_PPR_MASK UINT32_C(0xf8000000)
304	RT_BF_ASSERT_COMPILE_CHECKS(IOMMU_BF_MISCINFO_0_, UINT32_C(0), UINT32_MAX,
305	(MSI_NUM, GVA_SIZE, PA_SIZE, VA_SIZE, HT_ATS_RESV, RSVD_23_26, MSI_NUM_PPR));
306	/** @} */
307
308	/**
309	* @name IOMMU Miscellaneous Information Register 1.
310	* In accordance with the AMD spec.
311	* @{
312	*/
313	/** MsiNumGA: MSI message number for guest virtual-APIC log. */
314	#define IOMMU_BF_MISCINFO_1_MSI_NUM_GA_SHIFT 0
315	#define IOMMU_BF_MISCINFO_1_MSI_NUM_GA_MASK UINT32_C(0x0000001f)
316	/** Bits 31:5 reserved. */
317	#define IOMMU_BF_MISCINFO_1_RSVD_5_31_SHIFT 5
318	#define IOMMU_BF_MISCINFO_1_RSVD_5_31_MASK UINT32_C(0xffffffe0)
319	RT_BF_ASSERT_COMPILE_CHECKS(IOMMU_BF_MISCINFO_1_, UINT32_C(0), UINT32_MAX,
320	(MSI_NUM_GA, RSVD_5_31));
321	/** @} */
322
323	/**
324	* @name MSI Capability Header Register.
325	* In accordance with the AMD spec.
326	* @{
327	*/
328	/** MsiCapId: Capability ID. */
329	#define IOMMU_BF_MSI_CAP_HDR_CAP_ID_SHIFT 0
330	#define IOMMU_BF_MSI_CAP_HDR_CAP_ID_MASK UINT32_C(0x000000ff)
331	/** MsiCapPtr: Pointer (PCI config offset) to the next capability. */
332	#define IOMMU_BF_MSI_CAP_HDR_CAP_PTR_SHIFT 8
333	#define IOMMU_BF_MSI_CAP_HDR_CAP_PTR_MASK UINT32_C(0x0000ff00)
334	/** MsiEn: Message Signal Interrupt enable. */
335	#define IOMMU_BF_MSI_CAP_HDR_EN_SHIFT 16
336	#define IOMMU_BF_MSI_CAP_HDR_EN_MASK UINT32_C(0x00010000)
337	/** MsiMultMessCap: MSI Multi-Message Capability. */
338	#define IOMMU_BF_MSI_CAP_HDR_MULTMESS_CAP_SHIFT 17
339	#define IOMMU_BF_MSI_CAP_HDR_MULTMESS_CAP_MASK UINT32_C(0x000e0000)
340	/** MsiMultMessEn: MSI Mult-Message Enable. */
341	#define IOMMU_BF_MSI_CAP_HDR_MULTMESS_EN_SHIFT 20
342	#define IOMMU_BF_MSI_CAP_HDR_MULTMESS_EN_MASK UINT32_C(0x00700000)
343	/** Msi64BitEn: MSI 64-bit Enabled. */
344	#define IOMMU_BF_MSI_CAP_HDR_64BIT_EN_SHIFT 23
345	#define IOMMU_BF_MSI_CAP_HDR_64BIT_EN_MASK UINT32_C(0x00800000)
346	/** Bits 31:24 reserved. */
347	#define IOMMU_BF_MSI_CAP_HDR_RSVD_24_31_SHIFT 24
348	#define IOMMU_BF_MSI_CAP_HDR_RSVD_24_31_MASK UINT32_C(0xff000000)
349	RT_BF_ASSERT_COMPILE_CHECKS(IOMMU_BF_MSI_CAP_HDR_, UINT32_C(0), UINT32_MAX,
350	(CAP_ID, CAP_PTR, EN, MULTMESS_CAP, MULTMESS_EN, 64BIT_EN, RSVD_24_31));
351	/** @} */
352
353	/**
354	* @name MSI Mapping Capability Header Register.
355	* In accordance with the AMD spec.
356	* @{
357	*/
358	/** MsiMapCapId: Capability ID. */
359	#define IOMMU_BF_MSI_MAP_CAPHDR_CAP_ID_SHIFT 0
360	#define IOMMU_BF_MSI_MAP_CAPHDR_CAP_ID_MASK UINT32_C(0x000000ff)
361	/** MsiMapCapPtr: Pointer (PCI config offset) to the next capability. */
362	#define IOMMU_BF_MSI_MAP_CAPHDR_CAP_PTR_SHIFT 8
363	#define IOMMU_BF_MSI_MAP_CAPHDR_CAP_PTR_MASK UINT32_C(0x0000ff00)
364	/** MsiMapEn: MSI mapping capability enable. */
365	#define IOMMU_BF_MSI_MAP_CAPHDR_EN_SHIFT 16
366	#define IOMMU_BF_MSI_MAP_CAPHDR_EN_MASK UINT32_C(0x00010000)
367	/** MsiMapFixd: MSI interrupt mapping range is not programmable. */
368	#define IOMMU_BF_MSI_MAP_CAPHDR_FIXED_SHIFT 17
369	#define IOMMU_BF_MSI_MAP_CAPHDR_FIXED_MASK UINT32_C(0x00020000)
370	/** Bits 18:28 reserved. */
371	#define IOMMU_BF_MSI_MAP_CAPHDR_RSVD_18_28_SHIFT 18
372	#define IOMMU_BF_MSI_MAP_CAPHDR_RSVD_18_28_MASK UINT32_C(0x07fc0000)
373	/** MsiMapCapType: MSI mapping capability. */
374	#define IOMMU_BF_MSI_MAP_CAPHDR_CAP_TYPE_SHIFT 27
375	#define IOMMU_BF_MSI_MAP_CAPHDR_CAP_TYPE_MASK UINT32_C(0xf8000000)
376	RT_BF_ASSERT_COMPILE_CHECKS(IOMMU_BF_MSI_MAP_CAPHDR_, UINT32_C(0), UINT32_MAX,
377	(CAP_ID, CAP_PTR, EN, FIXED, RSVD_18_28, CAP_TYPE));
378	/** @} */
379
380	/**
381	* @name IOMMU Status Register Bits.
382	* In accordance with the AMD spec.
383	* @{
384	*/
385	/** EventOverflow: Event log overflow. */
386	#define IOMMU_STATUS_EVT_LOG_OVERFLOW RT_BIT_64(0)
387	/** EventLogInt: Event log interrupt. */
388	#define IOMMU_STATUS_EVT_LOG_INTR RT_BIT_64(1)
389	/** ComWaitInt: Completion wait interrupt. */
390	#define IOMMU_STATUS_COMPLETION_WAIT_INTR RT_BIT_64(2)
391	/** EventLogRun: Event log is running. */
392	#define IOMMU_STATUS_EVT_LOG_RUNNING RT_BIT_64(3)
393	/** CmdBufRun: Command buffer is running. */
394	#define IOMMU_STATUS_CMD_BUF_RUNNING RT_BIT_64(4)
395	/** PprOverflow: Peripheral page request log overflow. */
396	#define IOMMU_STATUS_PPR_LOG_OVERFLOW RT_BIT_64(5)
397	/** PprInt: Peripheral page request log interrupt. */
398	#define IOMMU_STATUS_PPR_LOG_INTR RT_BIT_64(6)
399	/** PprLogRun: Peripheral page request log is running. */
400	#define IOMMU_STATUS_PPR_LOG_RUN RT_BIT_64(7)
401	/** GALogRun: Guest virtual-APIC log is running. */
402	#define IOMMU_STATUS_GA_LOG_RUN RT_BIT_64(8)
403	/** GALOverflow: Guest virtual-APIC log overflow. */
404	#define IOMMU_STATUS_GA_LOG_OVERFLOW RT_BIT_64(9)
405	/** GAInt: Guest virtual-APIC log interrupt. */
406	#define IOMMU_STATUS_GA_LOG_INTR RT_BIT_64(10)
407	/** PprOvrflwB: PPR Log B overflow. */
408	#define IOMMU_STATUS_PPR_LOG_B_OVERFLOW RT_BIT_64(11)
409	/** PprLogActive: PPR Log B is active. */
410	#define IOMMU_STATUS_PPR_LOG_B_ACTIVE RT_BIT_64(12)
411	/** EvtOvrflwB: Event log B overflow. */
412	#define IOMMU_STATUS_EVT_LOG_B_OVERFLOW RT_BIT_64(15)
413	/** EventLogActive: Event log B active. */
414	#define IOMMU_STATUS_EVT_LOG_B_ACTIVE RT_BIT_64(16)
415	/** PprOvrflwEarlyB: PPR log B overflow early warning. */
416	#define IOMMU_STATUS_PPR_LOG_B_OVERFLOW_EARLY RT_BIT_64(17)
417	/** PprOverflowEarly: PPR log overflow early warning. */
418	#define IOMMU_STATUS_PPR_LOG_OVERFLOW_EARLY RT_BIT_64(18)
419	/** @} */
420
421	/** @name IOMMU_IO_PERM_XXX: IOMMU I/O access permissions bits.
422	* In accordance with the AMD spec.
423	*
424	* These values match the shifted values of the IR and IW field of the DTE and the
425	* PTE, PDE of the I/O page tables.
426	*
427	* @{ */
428	#define IOMMU_IO_PERM_NONE (0)
429	#define IOMMU_IO_PERM_READ RT_BIT_64(0)
430	#define IOMMU_IO_PERM_WRITE RT_BIT_64(1)
431	#define IOMMU_IO_PERM_READ_WRITE (IOMMU_IO_PERM_READ \| IOMMU_IO_PERM_WRITE)
432	#define IOMMU_IO_PERM_SHIFT 61
433	#define IOMMU_IO_PERM_MASK 0x3
434	/** @} */
435
436	/** @name SYSMGT_TYPE_XXX: System Management Message Enable Types.
437	* In accordance with the AMD spec.
438	* @{ */
439	#define SYSMGTTYPE_DMA_DENY (0)
440	#define SYSMGTTYPE_MSG_ALL_ALLOW (1)
441	#define SYSMGTTYPE_MSG_INT_ALLOW (2)
442	#define SYSMGTTYPE_DMA_ALLOW (3)
443	/** @} */
444
445	/** @name IOMMU_INTR_CTRL_XX: DTE::IntCtl field values.
446	* These are control bits for handling fixed and arbitrated interrupts.
447	* In accordance with the AMD spec.
448	* @{ */
449	#define IOMMU_INTR_CTRL_TARGET_ABORT (0)
450	#define IOMMU_INTR_CTRL_FWD_UNMAPPED (1)
451	#define IOMMU_INTR_CTRL_REMAP (2)
452	#define IOMMU_INTR_CTRL_RSVD (3)
453	/** @} */
454
455	/**
456	* Gets the device table size given the size field.
457	*/
458	#define IOMMU_GET_DEV_TAB_SIZE(a_uSize) (((a_uSize) + 1) << X86_PAGE_4K_SHIFT)
459
460	/**
461	* The Device ID.
462	* In accordance with VirtualBox's PCI configuration.
463	*/
464	typedef union
465	{
466	struct
467	{
468	RT_GCC_EXTENSION uint16_t u3Function : 3; /*< Bits 2:0 - Function. /
469	RT_GCC_EXTENSION uint16_t u9Device : 9; /*< Bits 11:3 - Device. /
470	RT_GCC_EXTENSION uint16_t u4Bus : 4; /*< Bits 15:12 - Bus. /
471	} n;
472	/** The unsigned integer view. */
473	uint16_t u;
474	} DEVICE_ID_T;
475	AssertCompileSize(DEVICE_ID_T, 2);
476
477	/**
478	* Device Table Entry (DTE).
479	* In accordance with the AMD spec.
480	*/
481	typedef union
482	{
483	struct
484	{
485	RT_GCC_EXTENSION uint64_t u1Valid : 1; /*< Bit 0 - V: Valid. /
486	RT_GCC_EXTENSION uint64_t u1TranslationValid : 1; /*< Bit 1 - TV: Translation information Valid. /
487	RT_GCC_EXTENSION uint64_t u5Rsvd0 : 5; /*< Bits 6:2 - Reserved. /
488	RT_GCC_EXTENSION uint64_t u2Had : 2; /*< Bits 8:7 - HAD: Host Access Dirty. /
489	RT_GCC_EXTENSION uint64_t u3Mode : 3; /*< Bits 11:9 - Mode: Paging mode. /
490	RT_GCC_EXTENSION uint64_t u40PageTableRootPtrLo : 40; /*< Bits 51:12 - Page Table Root Pointer. /
491	RT_GCC_EXTENSION uint64_t u1Ppr : 1; /*< Bit 52 - PPR: Peripheral Page Request. /
492	RT_GCC_EXTENSION uint64_t u1GstPprRespPasid : 1; /*< Bit 53 - GRPR: Guest PPR Response with PASID. /
493	RT_GCC_EXTENSION uint64_t u1GstIoValid : 1; /*< Bit 54 - GIoV: Guest I/O Protection Valid. /
494	RT_GCC_EXTENSION uint64_t u1GstTranslateValid : 1; /*< Bit 55 - GV: Guest translation Valid. /
495	RT_GCC_EXTENSION uint64_t u2GstMode : 2; /*< Bits 57:56 - GLX: Guest Paging mode levels. /
496	RT_GCC_EXTENSION uint64_t u3GstCr3TableRootPtrLo : 3; /*< Bits 60:58 - GCR3 TRP: Guest CR3 Table Root Ptr (Lo). /
497	RT_GCC_EXTENSION uint64_t u1IoRead : 1; /*< Bit 61 - IR: I/O Read permission. /
498	RT_GCC_EXTENSION uint64_t u1IoWrite : 1; /*< Bit 62 - IW: I/O Write permission. /
499	RT_GCC_EXTENSION uint64_t u1Rsvd0 : 1; /*< Bit 63 - Reserved. /
500	RT_GCC_EXTENSION uint64_t u16DomainId : 16; /*< Bits 79:64 - Domain ID. /
501	RT_GCC_EXTENSION uint64_t u16GstCr3TableRootPtrMed : 16; /*< Bits 95:80 - GCR3 TRP: Guest CR3 Table Root Ptr (Mid). /
502	RT_GCC_EXTENSION uint64_t u1IoTlbEnable : 1; /*< Bit 96 - I: IOTLB Enable. /
503	RT_GCC_EXTENSION uint64_t u1SuppressPfEvents : 1; /*< Bit 97 - SE: Supress Page-fault events. /
504	RT_GCC_EXTENSION uint64_t u1SuppressAllPfEvents : 1; /*< Bit 98 - SA: Supress All Page-fault events. /
505	RT_GCC_EXTENSION uint64_t u2IoCtl : 2; /*< Bits 100:99 - IoCtl: Port I/O Control. /
506	RT_GCC_EXTENSION uint64_t u1Cache : 1; /*< Bit 101 - Cache: IOTLB Cache Hint. /
507	RT_GCC_EXTENSION uint64_t u1SnoopDisable : 1; /*< Bit 102 - SD: Snoop Disable. /
508	RT_GCC_EXTENSION uint64_t u1AllowExclusion : 1; /*< Bit 103 - EX: Allow Exclusion. /
509	RT_GCC_EXTENSION uint64_t u2SysMgt : 2; /*< Bits 105:104 - SysMgt: System Management message enable. /
510	RT_GCC_EXTENSION uint64_t u1Rsvd1 : 1; /*< Bit 106 - Reserved. /
511	RT_GCC_EXTENSION uint64_t u21GstCr3TableRootPtrHi : 21; /*< Bits 127:107 - GCR3 TRP: Guest CR3 Table Root Ptr (Hi). /
512	RT_GCC_EXTENSION uint64_t u1IntrMapValid : 1; /*< Bit 128 - IV: Interrupt map Valid. /
513	RT_GCC_EXTENSION uint64_t u4IntrTableLength : 4; /*< Bits 132:129 - IntTabLen: Interrupt Table Length. /
514	RT_GCC_EXTENSION uint64_t u1IgnoreUnmappedIntrs : 1; /*< Bits 133 - IG: Ignore unmapped interrupts. /
515	RT_GCC_EXTENSION uint64_t u46IntrTableRootPtr : 46; /*< Bits 179:134 - Interrupt Root Table Pointer. /
516	RT_GCC_EXTENSION uint64_t u4Rsvd0 : 4; /*< Bits 183:180 - Reserved. /
517	RT_GCC_EXTENSION uint64_t u1InitPassthru : 1; /*< Bits 184 - INIT Pass-through. /
518	RT_GCC_EXTENSION uint64_t u1ExtIntPassthru : 1; /*< Bits 185 - External Interrupt Pass-through. /
519	RT_GCC_EXTENSION uint64_t u1NmiPassthru : 1; /*< Bits 186 - NMI Pass-through. /
520	RT_GCC_EXTENSION uint64_t u1Rsvd2 : 1; /*< Bits 187 - Reserved. /
521	RT_GCC_EXTENSION uint64_t u2IntrCtrl : 2; /*< Bits 189:188 - IntCtl: Interrupt Control. /
522	RT_GCC_EXTENSION uint64_t u1Lint0Passthru : 1; /*< Bit 190 - Lint0Pass: LINT0 Pass-through. /
523	RT_GCC_EXTENSION uint64_t u1Lint1Passthru : 1; /*< Bit 191 - Lint1Pass: LINT1 Pass-through. /
524	RT_GCC_EXTENSION uint64_t u32Rsvd0 : 32; /*< Bits 223:192 - Reserved. /
525	RT_GCC_EXTENSION uint64_t u22Rsvd0 : 22; /*< Bits 245:224 - Reserved. /
526	RT_GCC_EXTENSION uint64_t u1AttrOverride : 1; /*< Bit 246 - AttrV: Attribute Override. /
527	RT_GCC_EXTENSION uint64_t u1Mode0FC: 1; /*< Bit 247 - Mode0FC. /
528	RT_GCC_EXTENSION uint64_t u8SnoopAttr: 8; /*< Bits 255:248 - Snoop Attribute. /
529	} n;
530	/** The 32-bit unsigned integer view. */
531	uint32_t au32[8];
532	/** The 64-bit unsigned integer view. */
533	uint64_t au64[4];
534	} DTE_T;
535	AssertCompileSize(DTE_T, 32);
536	/** Pointer to a device table entry. */
537	typedef DTE_T *PDTE_T;
538	/** Pointer to a const device table entry. */
539	typedef DTE_T const *PCDTE_T;
540
541	/** Mask of valid bits for EPHSUP (Enhanced Peripheral Page Request Handling
542	* Support) feature (bits 52:53). */
543	#define IOMMU_DTE_QWORD_0_FEAT_EPHSUP_MASK UINT64_C(0x0030000000000000)
544
545	/** Mask of valid bits for GTSup (Guest Translation Support) feature (bits 55:60,
546	* bits 80:95). */
547	#define IOMMU_DTE_QWORD_0_FEAT_GTSUP_MASK UINT64_C(0x1f80000000000000)
548	#define IOMMU_DTE_QWORD_1_FEAT_GTSUP_MASK UINT64_C(0x00000000ffff0000)
549
550	/* Mask of valid bits for GIoSup (Guest I/O Protection Support) feature (bit 54). */
551	#define IOMMU_DTE_QWORD_0_FEAT_GIOSUP_MASK UINT64_C(0x0040000000000000)
552
553	/* Mask of valid DTE feature bits. */
554	#define IOMMU_DTE_QWORD_0_FEAT_MASK ( IOMMU_DTE_QWORD_0_FEAT_EPHSUP_MASK \
555	\| IOMMU_DTE_QWORD_0_FEAT_GTSUP_MASK \
556	\| IOMMU_DTE_QWORD_0_FEAT_GIOSUP_MASK)
557	#define IOMMU_DTE_QWORD_1_FEAT_MASK (IOMMU_DTE_QWORD_0_FEAT_GIOSUP_MASK)
558
559	/* Mask of all valid DTE bits (including all feature bits). */
560	#define IOMMU_DTE_QWORD_0_VALID_MASK UINT64_C(0x7fffffffffffff83)
561	#define IOMMU_DTE_QWORD_1_VALID_MASK UINT64_C(0xfffffbffffffffff)
562	#define IOMMU_DTE_QWORD_2_VALID_MASK UINT64_C(0xff0fffffffffffff)
563	#define IOMMU_DTE_QWORD_3_VALID_MASK UINT64_C(0xffc0000000000000)
564
565	/* Mask of the interrupt table root pointer. */
566	#define IOMMU_DTE_IRTE_ROOT_PTR_MASK UINT64_C(0x000fffffffffffc0)
567
568	/**
569	* I/O Page Translation Entry.
570	* In accordance with the AMD spec.
571	*/
572	typedef union
573	{
574	struct
575	{
576	RT_GCC_EXTENSION uint64_t u1Present : 1; /*< Bit 0 - PR: Present. /
577	RT_GCC_EXTENSION uint64_t u4Ign0 : 4; /*< Bits 4:1 - Ignored. /
578	RT_GCC_EXTENSION uint64_t u1Accessed : 1; /*< Bit 5 - A: Accessed. /
579	RT_GCC_EXTENSION uint64_t u1Dirty : 1; /*< Bit 6 - D: Dirty. /
580	RT_GCC_EXTENSION uint64_t u2Ign0 : 2; /*< Bits 8:7 - Ignored. /
581	RT_GCC_EXTENSION uint64_t u3NextLevel : 3; /*< Bits 11:9 - Next Level: Next page translation level. /
582	RT_GCC_EXTENSION uint64_t u40PageAddr : 40; /*< Bits 51:12 - Page address. /
583	RT_GCC_EXTENSION uint64_t u7Rsvd0 : 7; /*< Bits 58:52 - Reserved. /
584	RT_GCC_EXTENSION uint64_t u1UntranslatedAccess : 1; /*< Bit 59 - U: Untranslated Access Only. /
585	RT_GCC_EXTENSION uint64_t u1ForceCoherent : 1; /*< Bit 60 - FC: Force Coherent. /
586	RT_GCC_EXTENSION uint64_t u1IoRead : 1; /*< Bit 61 - IR: I/O Read permission. /
587	RT_GCC_EXTENSION uint64_t u1IoWrite : 1; /*< Bit 62 - IW: I/O Wead permission. /
588	RT_GCC_EXTENSION uint64_t u1Ign0 : 1; /*< Bit 63 - Ignored. /
589	} n;
590	/** The 64-bit unsigned integer view. */
591	uint64_t u64;
592	} IOPTE_T;
593	AssertCompileSize(IOPTE_T, 8);
594
595	/**
596	* I/O Page Directory Entry.
597	* In accordance with the AMD spec.
598	*/
599	typedef union
600	{
601	struct
602	{
603	RT_GCC_EXTENSION uint64_t u1Present : 1; /*< Bit 0 - PR: Present. /
604	RT_GCC_EXTENSION uint64_t u4Ign0 : 4; /*< Bits 4:1 - Ignored. /
605	RT_GCC_EXTENSION uint64_t u1Accessed : 1; /*< Bit 5 - A: Accessed. /
606	RT_GCC_EXTENSION uint64_t u3Ign0 : 3; /*< Bits 8:6 - Ignored. /
607	RT_GCC_EXTENSION uint64_t u3NextLevel : 3; /*< Bits 11:9 - Next Level: Next page translation level. /
608	RT_GCC_EXTENSION uint64_t u40PageAddr : 40; /*< Bits 51:12 - Page address (Next Table Address). /
609	RT_GCC_EXTENSION uint64_t u9Rsvd0 : 9; /*< Bits 60:52 - Reserved. /
610	RT_GCC_EXTENSION uint64_t u1IoRead : 1; /*< Bit 61 - IR: I/O Read permission. /
611	RT_GCC_EXTENSION uint64_t u1IoWrite : 1; /*< Bit 62 - IW: I/O Wead permission. /
612	RT_GCC_EXTENSION uint64_t u1Ign0 : 1; /*< Bit 63 - Ignored. /
613	} n;
614	/** The 64-bit unsigned integer view. */
615	uint64_t u64;
616	} IOPDE_T;
617	AssertCompileSize(IOPDE_T, 8);
618
619	/**
620	* I/O Page Table Entity.
621	* In accordance with the AMD spec.
622	*
623	* This a common subset of an DTE.au64[0], PTE and PDE.
624	* Named as an "entity" to avoid confusing it with PTE.
625	*/
626	typedef union
627	{
628	struct
629	{
630	RT_GCC_EXTENSION uint64_t u1Present : 1; /*< Bit 0 - PR: Present. /
631	RT_GCC_EXTENSION uint64_t u8Ign0 : 8; /*< Bits 8:1 - Ignored. /
632	RT_GCC_EXTENSION uint64_t u3NextLevel : 3; /*< Bits 11:9 - Mode / Next Level: Next page translation level. /
633	RT_GCC_EXTENSION uint64_t u40Addr : 40; /*< Bits 51:12 - Page address. /
634	RT_GCC_EXTENSION uint64_t u9Ign0 : 9; /*< Bits 60:52 - Ignored. /
635	RT_GCC_EXTENSION uint64_t u1IoRead : 1; /*< Bit 61 - IR: I/O Read permission. /
636	RT_GCC_EXTENSION uint64_t u1IoWrite : 1; /*< Bit 62 - IW: I/O Wead permission. /
637	RT_GCC_EXTENSION uint64_t u1Ign0 : 1; /*< Bit 63 - Ignored. /
638	} n;
639	/** The 64-bit unsigned integer view. */
640	uint64_t u64;
641	} IOPTENTITY_T;
642	AssertCompileSize(IOPTENTITY_T, 8);
643	AssertCompile(sizeof(IOPTENTITY_T) == sizeof(IOPTE_T));
644	AssertCompile(sizeof(IOPTENTITY_T) == sizeof(IOPDE_T));
645	/** Pointer to an IOPT_ENTITY_T struct. */
646	typedef IOPTENTITY_T *PIOPTENTITY_T;
647	/** Pointer to a const IOPT_ENTITY_T struct. */
648	typedef IOPTENTITY_T const *PCIOPTENTITY_T;
649	/** Mask of the address field. */
650	#define IOMMU_PTENTITY_ADDR_MASK UINT64_C(0x000ffffffffff000)
651
652	/**
653	* Interrupt Remapping Table Entry (IRTE).
654	* In accordance with the AMD spec.
655	*/
656	typedef union
657	{
658	struct
659	{
660	uint32_t u1RemapEnable : 1; /*< Bit 0 - RemapEn: Remap Enable. /
661	uint32_t u1SuppressPf : 1; /*< Bit 1 - SupIOPF: Supress I/O Page Fault. /
662	uint32_t u3IntrType : 1; /*< Bits 4:2 - IntType: Interrupt Type. /
663	uint32_t u1ReqEoi : 1; /*< Bit 5 - RqEoi: Request EOI. /
664	uint32_t u1DestMode : 1; /*< Bit 6 - DM: Destination Mode. /
665	uint32_t u1GuestMode : 1; /*< Bit 7 - GuestMode. /
666	uint32_t u8Dest : 8; /*< Bits 15:8 - Destination. /
667	uint32_t u8Vector : 8; /*< Bits 23:16 - Vector. /
668	uint32_t u8Rsvd0 : 8; /*< Bits 31:24 - Reserved. /
669	} n;
670	/** The 32-bit unsigned integer view. */
671	uint32_t u32;
672	} IRTE_T;
673	AssertCompileSize(IRTE_T, 4);
674	/** The number of bits to shift the IRTE offset to get the IRTE. */
675	#define IOMMU_IRTE_SIZE_SHIFT (2)
676	/** Pointer to an IRTE_T struct. */
677	typedef IRTE_T *PIRTE_T;
678	/** Pointer to a const IRTE_T struct. */
679	typedef IRTE_T const *PCIRTE_T;
680
681	/** The IRTE offset corresponds directly to bits 10:0 of the originating MSI
682	* interrupt message. See AMD IOMMU spec. 2.2.5 "Interrupt Remapping Tables". */
683	#define IOMMU_MSI_DATA_IRTE_OFFSET_MASK UINT32_C(0x000007ff)
684
685	/**
686	* Command: Generic Command Buffer Entry.
687	* In accordance with the AMD spec.
688	*/
689	typedef union
690	{
691	struct
692	{
693	uint32_t u32Operand1Lo; /*< Bits 31:0 - Operand 1 (Lo). /
694	uint32_t u32Operand1Hi : 28; /*< Bits 59:32 - Operand 1 (Hi). /
695	uint32_t u4Opcode : 4; /*< Bits 63:60 - Op Code. /
696	uint64_t u64Operand2; /*< Bits 127:64 - Operand 2. /
697	} n;
698	/** The 64-bit unsigned integer view. */
699	uint64_t au64[2];
700	} CMD_GENERIC_T;
701	AssertCompileSize(CMD_GENERIC_T, 16);
702	/** Pointer to a generic command buffer entry. */
703	typedef CMD_GENERIC_T *PCMD_GENERIC_T;
704	/** Pointer to a const generic command buffer entry. */
705	typedef CMD_GENERIC_T const *PCCMD_GENERIC_T;
706
707	/** Number of bits to shift the byte offset of a command in the command buffer to
708	* get its index. */
709	#define IOMMU_CMD_GENERIC_SHIFT 4
710
711	/**
712	* Command: COMPLETION_WAIT.
713	* In accordance with the AMD spec.
714	*/
715	typedef union
716	{
717	struct
718	{
719	uint32_t u1Store : 1; /*< Bit 0 - S: Completion Store. /
720	uint32_t u1Interrupt : 1; /*< Bit 1 - I: Completion Interrupt. /
721	uint32_t u1Flush : 1; /*< Bit 2 - F: Flush Queue. /
722	uint32_t u29StoreAddrLo : 29; /*< Bits 31:3 - Store Address (Lo). /
723	uint32_t u20StoreAddrHi : 20; /*< Bits 51:32 - Store Address (Hi). /
724	uint32_t u8Rsvd0 : 8; /*< Bits 59:52 - Reserved. /
725	uint32_t u4OpCode : 4; /*< Bits 63:60 - OpCode (Command). /
726	uint64_t u64StoreData; /*< Bits 127:64 - Store Data. /
727	} n;
728	/** The 64-bit unsigned integer view. */
729	uint64_t au64[2];
730	} CMD_COMWAIT_T;
731	AssertCompileSize(CMD_COMWAIT_T, 16);
732	/** Pointer to a completion wait command. */
733	typedef CMD_COMWAIT_T *PCMD_COMWAIT_T;
734	/** Pointer to a const completion wait command. */
735	typedef CMD_COMWAIT_T const *PCCMD_COMWAIT_T;
736	#define IOMMU_CMD_COM_WAIT_QWORD_0_VALID_MASK UINT64_C(0xf00fffffffffffff)
737
738	/**
739	* Command: INVALIDATE_DEVTAB_ENTRY.
740	* In accordance with the AMD spec.
741	*/
742	typedef union
743	{
744	struct
745	{
746	uint16_t u16DevId; /*< Bits 15:0 - Device ID. /
747	uint16_t u16Rsvd0; /*< Bits 31:16 - Reserved. /
748	uint32_t u28Rsvd0 : 28; /*< Bits 59:32 - Reserved. /
749	uint32_t u4OpCode : 4; /*< Bits 63:60 - Op Code (Command). /
750	uint64_t u64Rsvd0; /*< Bits 127:64 - Reserved. /
751	} n;
752	/** The 64-bit unsigned integer view. */
753	uint64_t au64[2];
754	} CMD_INV_DTE_T;
755	AssertCompileSize(CMD_INV_DTE_T, 16);
756
757	/**
758	* Command: INVALIDATE_IOMMU_PAGES.
759	* In accordance with the AMD spec.
760	*/
761	typedef union
762	{
763	struct
764	{
765	uint32_t u20Pasid : 20; /*< Bits 19:0 - PASID: Process Address-Space ID. /
766	uint32_t u12Rsvd0 : 12; /*< Bits 31:20 - Reserved. /
767	uint32_t u16DomainId : 16; /*< Bits 47:32 - Domain ID. /
768	uint32_t u12Rsvd1 : 12; /*< Bits 59:48 - Reserved. /
769	uint32_t u4OpCode : 4; /*< Bits 63:60 - Op Code (Command). /
770	uint32_t u1Size : 1; /*< Bit 64 - S: Size. /
771	uint32_t u1PageDirEntries : 1; /*< Bit 65 - PDE: Page Directory Entries. /
772	uint32_t u1GuestOrNested : 1; /*< Bit 66 - GN: Guest (GPA) or Nested (GVA). /
773	uint32_t u9Rsvd0 : 9; /*< Bits 75:67 - Reserved. /
774	uint32_t u20AddrLo : 20; /*< Bits 95:76 - Address (Lo). /
775	uint32_t u32AddrHi; /*< Bits 127:96 - Address (Hi). /
776	} n;
777	/** The 64-bit unsigned integer view. */
778	uint64_t au64[2];
779	} CMD_INV_IOMMU_PAGES_T;
780	AssertCompileSize(CMD_INV_IOMMU_PAGES_T, 16);
781
782	/**
783	* Command: INVALIDATE_IOTLB_PAGES.
784	* In accordance with the AMD spec.
785	*/
786	typedef union
787	{
788	struct
789	{
790	uint16_t u16DevId; /*< Bits 15:0 - Device ID. /
791	uint8_t u8PasidLo; /*< Bits 23:16 - PASID: Process Address-Space ID (Lo). /
792	uint8_t u8MaxPend; /*< Bits 31:24 - Maxpend: Maximum simultaneous in-flight transactions. /
793	uint32_t u16QueueId : 16; /*< Bits 47:32 - Queue ID. /
794	uint32_t u12PasidHi : 12; /*< Bits 59:48 - PASID: Process Address-Space ID (Hi). /
795	uint32_t u4OpCode : 4; /*< Bits 63:60 - Op Code (Command). /
796	uint32_t u1Size : 1; /*< Bit 64 - S: Size. /
797	uint32_t u1Rsvd0: 1; /*< Bit 65 - Reserved. /
798	uint32_t u1GuestOrNested : 1; /*< Bit 66 - GN: Guest (GPA) or Nested (GVA). /
799	uint32_t u1Rsvd1 : 1; /*< Bit 67 - Reserved. /
800	uint32_t u2Type : 2; /*< Bit 69:68 - Type. /
801	uint32_t u6Rsvd0 : 6; /*< Bits 75:70 - Reserved. /
802	uint32_t u20AddrLo : 20; /*< Bits 95:76 - Address (Lo). /
803	uint32_t u32AddrHi; /*< Bits 127:96 - Address (Hi). /
804	} n;
805	/** The 64-bit unsigned integer view. */
806	uint64_t au64[2];
807	} CMD_INV_IOTLB_PAGES_T;
808	AssertCompileSize(CMD_INV_IOTLB_PAGES_T, 16);
809
810	/**
811	* Command: INVALIDATE_INTR_TABLE.
812	* In accordance with the AMD spec.
813	*/
814	typedef union
815	{
816	struct
817	{
818	uint16_t u16DevId; /*< Bits 15:0 - Device ID. /
819	uint16_t u16Rsvd0; /*< Bits 31:16 - Reserved. /
820	uint32_t u32Rsvd0 : 28; /*< Bits 59:32 - Reserved. /
821	uint32_t u4OpCode : 4; /*< Bits 63:60 - Op Code (Command). /
822	uint64_t u64Rsvd0; /*< Bits 127:64 - Reserved. /
823	} u;
824	/** The 64-bit unsigned integer view. */
825	uint64_t au64[2];
826	} CMD_INV_INTR_TABLE_T;
827	AssertCompileSize(CMD_INV_INTR_TABLE_T, 16);
828
829	/**
830	* Command: COMPLETE_PPR_REQ.
831	* In accordance with the AMD spec.
832	*/
833	typedef union
834	{
835	struct
836	{
837	uint16_t u16DevId; /*< Bits 15:0 - Device ID. /
838	uint16_t u16Rsvd0; /*< Bits 31:16 - Reserved. /
839	uint32_t u20Pasid : 20; /*< Bits 51:32 - PASID: Process Address-Space ID. /
840	uint32_t u8Rsvd0 : 8; /*< Bits 59:52 - Reserved. /
841	uint32_t u4OpCode : 4; /*< Bits 63:60 - Op Code (Command). /
842	uint32_t u2Rsvd0 : 2; /*< Bits 65:64 - Reserved. /
843	uint32_t u1GuestOrNested : 1; /*< Bit 66 - GN: Guest (GPA) or Nested (GVA). /
844	uint32_t u29Rsvd0 : 29; /*< Bits 95:67 - Reserved. /
845	uint32_t u16CompletionTag : 16; /*< Bits 111:96 - Completion Tag. /
846	uint32_t u16Rsvd1 : 16; /*< Bits 127:112 - Reserved. /
847	} n;
848	/** The 64-bit unsigned integer view. */
849	uint64_t au64[2];
850	} CMD_COMPLETE_PPR_REQ_T;
851	AssertCompileSize(CMD_COMPLETE_PPR_REQ_T, 16);
852
853	/**
854	* Command: INV_IOMMU_ALL.
855	* In accordance with the AMD spec.
856	*/
857	typedef union
858	{
859	struct
860	{
861	uint32_t u32Rsvd0; /*< Bits 31:0 - Reserved. /
862	uint32_t u28Rsvd0 : 28; /*< Bits 59:32 - Reserved. /
863	uint32_t u4OpCode : 4; /*< Bits 63:60 - Op Code (Command). /
864	uint64_t u64Rsvd0; /*< Bits 127:64 - Reserved. /
865	} n;
866	/** The 64-bit unsigned integer view. */
867	uint64_t au64[2];
868	} CMD_IOMMU_ALL_T;
869	AssertCompileSize(CMD_IOMMU_ALL_T, 16);
870
871	/**
872	* Event Log Entry: Generic.
873	* In accordance with the AMD spec.
874	*/
875	typedef union
876	{
877	struct
878	{
879	uint32_t u32Operand1Lo; /*< Bits 31:0 - Operand 1 (Lo). /
880	uint32_t u32Operand1Hi : 28; /*< Bits 59:32 - Operand 1 (Hi). /
881	uint32_t u4EvtCode : 4; /*< Bits 63:60 - Event code. /
882	uint32_t u32Operand2Lo; /*< Bits 95:64 - Operand 2 (Lo). /
883	uint32_t u32Operand2Hi; /*< Bits 127:96 - Operand 2 (Hi). /
884	} n;
885	/** The 32-bit unsigned integer view. */
886	uint32_t au32[4];
887	} EVT_GENERIC_T;
888	AssertCompileSize(EVT_GENERIC_T, 16);
889	/** Number of bits to shift the byte offset of an event entry in the event log
890	* buffer to get its index. */
891	#define IOMMU_EVT_GENERIC_SHIFT 4
892	/** Pointer to a generic event log entry. */
893	typedef EVT_GENERIC_T *PEVT_GENERIC_T;
894	/** Pointer to a const generic event log entry. */
895	typedef const EVT_GENERIC_T *PCEVT_GENERIC_T;
896
897	/**
898	* Hardware event types.
899	* In accordance with the AMD spec.
900	*/
901	typedef enum HWEVTTYPE
902	{
903	HWEVTTYPE_RSVD = 0,
904	HWEVTTYPE_MASTER_ABORT,
905	HWEVTTYPE_TARGET_ABORT,
906	HWEVTTYPE_DATA_ERROR
907	} HWEVTTYPE;
908	AssertCompileSize(HWEVTTYPE, 4);
909
910	/**
911	* Event Log Entry: ILLEGAL_DEV_TABLE_ENTRY.
912	* In accordance with the AMD spec.
913	*/
914	typedef union
915	{
916	struct
917	{
918	uint16_t u16DevId; /*< Bits 15:0 - Device ID. /
919	RT_GCC_EXTENSION uint16_t u4PasidHi : 4; /*< Bits 19:16 - PASID: Process Address-Space ID (Hi). /
920	RT_GCC_EXTENSION uint16_t u12Rsvd0 : 12; /*< Bits 31:20 - Reserved. /
921	uint16_t u16PasidLo; /*< Bits 47:32 - PASID: Process Address-Space ID (Lo). /
922	RT_GCC_EXTENSION uint16_t u1GuestOrNested : 1; /*< Bit 48 - GN: Guest (GPA) or Nested (GVA). /
923	RT_GCC_EXTENSION uint16_t u2Rsvd0 : 2; /*< Bits 50:49 - Reserved. /
924	RT_GCC_EXTENSION uint16_t u1Interrupt : 1; /*< Bit 51 - I: Interrupt. /
925	RT_GCC_EXTENSION uint16_t u1Rsvd0 : 1; /*< Bit 52 - Reserved. /
926	RT_GCC_EXTENSION uint16_t u1ReadWrite : 1; /*< Bit 53 - RW: Read/Write. /
927	RT_GCC_EXTENSION uint16_t u1Rsvd1 : 1; /*< Bit 54 - Reserved. /
928	RT_GCC_EXTENSION uint16_t u1RsvdNotZero : 1; /*< Bit 55 - RZ: Reserved bit not Zero (0=invalid level encoding). /
929	RT_GCC_EXTENSION uint16_t u1Translation : 1; /*< Bit 56 - TN: Translation. /
930	RT_GCC_EXTENSION uint16_t u3Rsvd0 : 3; /*< Bits 59:57 - Reserved. /
931	RT_GCC_EXTENSION uint16_t u4EvtCode : 4; /*< Bits 63:60 - Event code. /
932	uint64_t u64Addr; /*< Bits 127:64 - Address: I/O Virtual Address (IOVA). /
933	} n;
934	/** The 32-bit unsigned integer view. */
935	uint32_t au32[4];
936	/** The 64-bit unsigned integer view. */
937	uint64_t au64[2];
938	} EVT_ILLEGAL_DTE_T;
939	AssertCompileSize(EVT_ILLEGAL_DTE_T, 16);
940	/** Pointer to an illegal device table entry event. */
941	typedef EVT_ILLEGAL_DTE_T *PEVT_ILLEGAL_DTE_T;
942	/** Pointer to a const illegal device table entry event. */
943	typedef EVT_ILLEGAL_DTE_T const *PCEVT_ILLEGAL_DTE_T;
944
945	/**
946	* Event Log Entry: IO_PAGE_FAULT_EVENT.
947	* In accordance with the AMD spec.
948	*/
949	typedef union
950	{
951	struct
952	{
953	uint16_t u16DevId; /*< Bits 15:0 - Device ID. /
954	RT_GCC_EXTENSION uint16_t u4PasidHi : 4; /*< Bits 19:16 - PASID: Process Address-Space ID (Hi). /
955	RT_GCC_EXTENSION uint16_t u16DomainOrPasidLo; /*< Bits 47:32 - D/P: Domain ID or Process Address-Space ID (Lo). /
956	RT_GCC_EXTENSION uint16_t u1GuestOrNested : 1; /*< Bit 48 - GN: Guest (GPA) or Nested (GVA). /
957	RT_GCC_EXTENSION uint16_t u1NoExecute : 1; /*< Bit 49 - NX: No Execute. /
958	RT_GCC_EXTENSION uint16_t u1User : 1; /*< Bit 50 - US: User/Supervisor. /
959	RT_GCC_EXTENSION uint16_t u1Interrupt : 1; /*< Bit 51 - I: Interrupt. /
960	RT_GCC_EXTENSION uint16_t u1Present : 1; /*< Bit 52 - PR: Present. /
961	RT_GCC_EXTENSION uint16_t u1ReadWrite : 1; /*< Bit 53 - RW: Read/Write. /
962	RT_GCC_EXTENSION uint16_t u1PermDenied : 1; /*< Bit 54 - PE: Permission Indicator. /
963	RT_GCC_EXTENSION uint16_t u1RsvdNotZero : 1; /*< Bit 55 - RZ: Reserved bit not Zero (0=invalid level encoding). /
964	RT_GCC_EXTENSION uint16_t u1Translation : 1; /*< Bit 56 - TN: Translation. /
965	RT_GCC_EXTENSION uint16_t u3Rsvd0 : 3; /*< Bit 59:57 - Reserved. /
966	RT_GCC_EXTENSION uint16_t u4EvtCode : 4; /*< Bits 63:60 - Event code. /
967	uint64_t u64Addr; /*< Bits 127:64 - Address: I/O Virtual Address (IOVA). /
968	} n;
969	/** The 32-bit unsigned integer view. */
970	uint32_t au32[4];
971	/** The 64-bit unsigned integer view. */
972	uint64_t au64[2];
973	} EVT_IO_PAGE_FAULT_T;
974	AssertCompileSize(EVT_IO_PAGE_FAULT_T, 16);
975	/** Pointer to an I/O page fault event. */
976	typedef EVT_IO_PAGE_FAULT_T *PEVT_IO_PAGE_FAULT_T;
977	/** Pointer to a const I/O page fault event. */
978	typedef EVT_IO_PAGE_FAULT_T const *PCEVT_IO_PAGE_FAULT_T;
979
980
981	/**
982	* Event Log Entry: DEV_TAB_HARDWARE_ERROR.
983	* In accordance with the AMD spec.
984	*/
985	typedef union
986	{
987	struct
988	{
989	uint16_t u16DevId; /*< Bits 15:0 - Device ID. /
990	uint16_t u16Rsvd0; /*< Bits 31:16 - Reserved. /
991	uint32_t u19Rsvd0 : 19; /*< Bits 50:32 - Reserved. /
992	uint32_t u1Intr : 1; /*< Bit 51 - I: Interrupt (1=interrupt request, 0=memory request). /
993	uint32_t u1Rsvd0 : 1; /*< Bit 52 - Reserved. /
994	uint32_t u1ReadWrite : 1; /*< Bit 53 - RW: Read/Write transaction (only meaninful when I=0 and TR=0). /
995	uint32_t u2Rsvd0 : 2; /*< Bits 55:54 - Reserved. /
996	uint32_t u1Translation : 1; /*< Bit 56 - TR: Translation (1=translation, 0=transaction). /
997	uint32_t u2Type : 2; /*< Bits 58:57 - Type: The type of hardware error. /
998	uint32_t u1Rsvd1 : 1; /*< Bit 59 - Reserved. /
999	uint32_t u4EvtCode : 4; /*< Bits 63:60 - Event code. /
1000	uint64_t u64Addr; /*< Bits 127:64 - Address. /
1001	} n;
1002	/** The 32-bit unsigned integer view. */
1003	uint32_t au32[4];
1004	/** The 64-bit unsigned integer view. */
1005	uint64_t au64[2];
1006	} EVT_DEV_TAB_HW_ERROR_T;
1007	AssertCompileSize(EVT_DEV_TAB_HW_ERROR_T, 16);
1008	/** Pointer to a device table hardware error event. */
1009	typedef EVT_DEV_TAB_HW_ERROR_T *PEVT_DEV_TAB_HW_ERROR_T;
1010	/** Pointer to a const device table hardware error event. */
1011	typedef EVT_DEV_TAB_HW_ERROR_T const *PCEVT_DEV_TAB_HW_ERROR_T;
1012
1013	/**
1014	* Event Log Entry: EVT_PAGE_TAB_HARDWARE_ERROR.
1015	* In accordance with the AMD spec.
1016	*/
1017	typedef union
1018	{
1019	struct
1020	{
1021	uint16_t u16DevId; /*< Bits 15:0 - Device ID. /
1022	uint16_t u16Rsvd0; /*< Bits 31:16 - Reserved. /
1023	uint32_t u16DomainOrPasidLo : 16; /*< Bits 47:32 - D/P: Domain ID or Process Address-Space ID (Lo). /
1024	uint32_t u1GuestOrNested : 1; /*< Bit 48 - GN: Guest (GPA) or Nested (GVA). /
1025	uint32_t u2Rsvd0 : 2; /*< Bits 50:49 - Reserved. /
1026	uint32_t u1Interrupt : 1; /*< Bit 51 - I: Interrupt. /
1027	uint32_t u1Rsvd0 : 1; /*< Bit 52 - Reserved. /
1028	uint32_t u1ReadWrite : 1; /*< Bit 53 - RW: Read/Write. /
1029	uint32_t u2Rsvd1 : 2; /*< Bit 55:54 - Reserved. /
1030	uint32_t u1Translation : 1; /*< Bit 56 - TR: Translation. /
1031	uint32_t u2Type : 2; /*< Bits 58:57 - Type: The type of hardware error. /
1032	uint32_t u1Rsvd1 : 1; /*< Bit 59 - Reserved. /
1033	uint32_t u4EvtCode : 4; /*< Bit 63:60 - Event code. /
1034	/** @todo r=ramshankar: Figure 55: PAGE_TAB_HARDWARE_ERROR says Addr[31:3] but
1035	* table 58 mentions Addr[31:4], we just use the full 64-bits. Looks like a
1036	* typo in the figure.See AMD AMD IOMMU spec (3.05-PUB, Jan 2020). */
1037	uint64_t u64Addr; /** Bits 127:64 - Address: SPA of the page table entry. */
1038	} n;
1039	/** The 32-bit unsigned integer view. */
1040	uint32_t au32[4];
1041	/** The 64-bit unsigned integer view. */
1042	uint64_t au64[2];
1043	} EVT_PAGE_TAB_HW_ERR_T;
1044	AssertCompileSize(EVT_PAGE_TAB_HW_ERR_T, 16);
1045	/** Pointer to a page table hardware error event. */
1046	typedef EVT_PAGE_TAB_HW_ERR_T *PEVT_PAGE_TAB_HW_ERR_T;
1047	/** Pointer to a const page table hardware error event. */
1048	typedef EVT_PAGE_TAB_HW_ERR_T const *PCEVT_PAGE_TAB_HW_ERR_T;
1049
1050	/**
1051	* Event Log Entry: ILLEGAL_COMMAND_ERROR.
1052	* In accordance with the AMD spec.
1053	*/
1054	typedef union
1055	{
1056	struct
1057	{
1058	uint32_t u32Rsvd0; /*< Bits 31:0 - Reserved. /
1059	uint32_t u28Rsvd0 : 28; /*< Bits 47:32 - Reserved. /
1060	uint32_t u4EvtCode : 4; /*< Bits 63:60 - Event code. /
1061	uint64_t u64Addr; /*< Bits 127:64 - Address: SPA of the invalid command. /
1062	} n;
1063	/** The 32-bit unsigned integer view. */
1064	uint32_t au32[4];
1065	/** The 64-bit unsigned integer view. */
1066	uint64_t au64[2];
1067	} EVT_ILLEGAL_CMD_ERR_T;
1068	AssertCompileSize(EVT_ILLEGAL_CMD_ERR_T, 16);
1069	/** Pointer to an illegal command error event. */
1070	typedef EVT_ILLEGAL_CMD_ERR_T *PEVT_ILLEGAL_CMD_ERR_T;
1071	/** Pointer to a const illegal command error event. */
1072	typedef EVT_ILLEGAL_CMD_ERR_T const *PCEVT_ILLEGAL_CMD_ERR_T;
1073
1074	/**
1075	* Event Log Entry: COMMAND_HARDWARE_ERROR.
1076	* In accordance with the AMD spec.
1077	*/
1078	typedef union
1079	{
1080	struct
1081	{
1082	uint32_t u32Rsvd0; /*< Bits 31:0 - Reserved. /
1083	uint32_t u25Rsvd1 : 25; /*< Bits 56:32 - Reserved. /
1084	uint32_t u2Type : 2; /*< Bits 58:57 - Type: The type of hardware error. /
1085	uint32_t u1Rsvd1 : 1; /*< Bit 59 - Reserved. /
1086	uint32_t u4EvtCode : 4; /*< Bits 63:60 - Event code. /
1087	uint64_t u64Addr; /*< Bits 128:64 - Address: SPA of the attempted access. /
1088	} n;
1089	/** The 32-bit unsigned integer view. */
1090	uint32_t au32[4];
1091	/** The 64-bit unsigned integer view. */
1092	uint64_t au64[2];
1093	} EVT_CMD_HW_ERR_T;
1094	AssertCompileSize(EVT_CMD_HW_ERR_T, 16);
1095	/** Pointer to a command hardware error event. */
1096	typedef EVT_CMD_HW_ERR_T *PEVT_CMD_HW_ERR_T;
1097	/** Pointer to a const command hardware error event. */
1098	typedef EVT_CMD_HW_ERR_T const *PCEVT_CMD_HW_ERR_T;
1099
1100	/**
1101	* Event Log Entry: IOTLB_INV_TIMEOUT.
1102	* In accordance with the AMD spec.
1103	*/
1104	typedef union
1105	{
1106	struct
1107	{
1108	uint16_t u16DevId; /*< Bits 15:0 - Device ID. /
1109	uint16_t u16Rsvd0; /*< Bits 31:16 - Reserved./
1110	uint32_t u28Rsvd0 : 28; /*< Bits 59:32 - Reserved. /
1111	uint32_t u4EvtCode : 4; /*< Bits 63:60 - Event code. /
1112	uint32_t u4Rsvd0 : 4; /*< Bits 67:64 - Reserved. /
1113	uint32_t u28AddrLo : 28; /*< Bits 95:68 - Address: SPA of the invalidation command that timedout (Lo). /
1114	uint32_t u32AddrHi; /*< Bits 127:96 - Address: SPA of the invalidation command that timedout (Hi). /
1115	} n;
1116	/** The 32-bit unsigned integer view. */
1117	uint32_t au32[4];
1118	} EVT_IOTLB_INV_TIMEOUT_T;
1119	AssertCompileSize(EVT_IOTLB_INV_TIMEOUT_T, 16);
1120
1121	/**
1122	* Event Log Entry: INVALID_DEVICE_REQUEST.
1123	* In accordance with the AMD spec.
1124	*/
1125	typedef union
1126	{
1127	struct
1128	{
1129	uint32_t u16DevId : 16; /**< Bits 15:0 - Device ID. /
1130	uint32_t u4PasidHi : 4; /**< Bits 19:16 - PASID: Process Address-Space ID (Hi). /
1131	uint32_t u12Rsvd0 : 12; /**< Bits 31:20 - Reserved. /
1132	uint32_t u16PasidLo : 16; /**< Bits 47:32 - PASID: Process Address-Space ID (Lo). /
1133	uint32_t u1GuestOrNested : 1; /**< Bit 48 - GN: Guest (GPA) or Nested (GVA). /
1134	uint32_t u1User : 1; /**< Bit 49 - US: User/Supervisor. /
1135	uint32_t u6Rsvd0 : 6; /**< Bits 55:50 - Reserved. /
1136	uint32_t u1Translation: 1; /**< Bit 56 - TR: Translation. /
1137	uint32_t u3Type: 3; /**< Bits 59:57 - Type: The type of hardware error. /
1138	uint32_t u4EvtCode : 4; /**< Bits 63:60 - Event code. /
1139	uint64_t u64Addr; /**< Bits 127:64 - Address: Translation or access address. /
1140	} n;
1141	/** The 32-bit unsigned integer view. */
1142	uint32_t au32[4];
1143	} EVT_INVALID_DEV_REQ_T;
1144	AssertCompileSize(EVT_INVALID_DEV_REQ_T, 16);
1145
1146	/**
1147	* Event Log Entry: EVENT_COUNTER_ZERO.
1148	* In accordance with the AMD spec.
1149	*/
1150	typedef union
1151	{
1152	struct
1153	{
1154	uint32_t u32Rsvd0; /*< Bits 31:0 - Reserved. /
1155	uint32_t u28Rsvd0 : 28; /*< Bits 59:32 - Reserved. /
1156	uint32_t u4EvtCode : 4; /*< Bits 63:60 - Event code. /
1157	uint32_t u20CounterNoteHi : 20; /*< Bits 83:64 - CounterNote: Counter value for the event counter register (Hi). /
1158	uint32_t u12Rsvd0 : 12; /*< Bits 95:84 - Reserved. /
1159	uint32_t u32CounterNoteLo; /*< Bits 127:96 - CounterNote: Counter value for the event cuonter register (Lo). /
1160	} n;
1161	/** The 32-bit unsigned integer view. */
1162	uint32_t au32[4];
1163	} EVT_EVENT_COUNTER_ZERO_T;
1164	AssertCompileSize(EVT_EVENT_COUNTER_ZERO_T, 16);
1165
1166	/**
1167	* IOMMU Capability Header (PCI).
1168	* In accordance with the AMD spec.
1169	*/
1170	typedef union
1171	{
1172	struct
1173	{
1174	uint32_t u8CapId : 8; /*< Bits 7:0 - CapId: Capability ID. /
1175	uint32_t u8CapPtr : 8; /*< Bits 15:8 - CapPtr: Pointer (PCI config offset) to the next capability. /
1176	uint32_t u3CapType : 3; /*< Bits 18:16 - CapType: Capability Type. /
1177	uint32_t u5CapRev : 5; /*< Bits 23:19 - CapRev: Capability revision. /
1178	uint32_t u1IoTlbSup : 1; /*< Bit 24 - IotlbSup: IOTLB Support. /
1179	uint32_t u1HtTunnel : 1; /*< Bit 25 - HtTunnel: HyperTransport Tunnel translation support. /
1180	uint32_t u1NpCache : 1; /*< Bit 26 - NpCache: Not Present table entries are cached. /
1181	uint32_t u1EfrSup : 1; /*< Bit 27 - EFRSup: Extended Feature Register Support. /
1182	uint32_t u1CapExt : 1; /*< Bit 28 - CapExt: Misc. Information Register 1 Support. /
1183	uint32_t u3Rsvd0 : 3; /*< Bits 31:29 - Reserved. /
1184	} n;
1185	/** The 32-bit unsigned integer view. */
1186	uint32_t u32;
1187	} IOMMU_CAP_HDR_T;
1188	AssertCompileSize(IOMMU_CAP_HDR_T, 4);
1189
1190	/**
1191	* IOMMU Base Address (Lo and Hi) Register (PCI).
1192	* In accordance with the AMD spec.
1193	*/
1194	typedef union
1195	{
1196	struct
1197	{
1198	uint32_t u1Enable : 1; /*< Bit 1 - Enable: RW1S - Enable IOMMU MMIO region. /
1199	uint32_t u12Rsvd0 : 12; /*< Bits 13:1 - Reserved. /
1200	uint32_t u18BaseAddrLo : 18; /*< Bits 31:14 - Base address (Lo) of the MMIO region. /
1201	uint32_t u32BaseAddrHi; /*< Bits 63:32 - Base address (Hi) of the MMIO region. /
1202	} n;
1203	/** The 32-bit unsigned integer view. */
1204	uint32_t au32[2];
1205	/** The 64-bit unsigned integer view. */
1206	uint64_t u64;
1207	} IOMMU_BAR_T;
1208	AssertCompileSize(IOMMU_BAR_T, 8);
1209	#define IOMMU_BAR_VALID_MASK UINT64_C(0xffffffffffffc001)
1210
1211	/**
1212	* IOMMU Range Register (PCI).
1213	* In accordance with the AMD spec.
1214	*/
1215	typedef union
1216	{
1217	struct
1218	{
1219	uint32_t u5HtUnitId : 5; /*< Bits 4:0 - UnitID: IOMMU HyperTransport Unit ID (not used). /
1220	uint32_t u2Rsvd0 : 2; /*< Bits 6:5 - Reserved. /
1221	uint32_t u1RangeValid : 1; /*< Bit 7 - RngValid: Range Valid. /
1222	uint32_t u8Bus : 8; /*< Bits 15:8 - BusNumber: Bus number of the first and last device. /
1223	uint32_t u8FirstDevice : 8; /*< Bits 23:16 - FirstDevice: Device and function number of the first device. /
1224	uint32_t u8LastDevice: 8; /*< Bits 31:24 - LastDevice: Device and function number of the last device. /
1225	} n;
1226	/** The 32-bit unsigned integer view. */
1227	uint32_t u32;
1228	} IOMMU_RANGE_T;
1229	AssertCompileSize(IOMMU_RANGE_T, 4);
1230
1231	/**
1232	* Device Table Base Address Register (MMIO).
1233	* In accordance with the AMD spec.
1234	*/
1235	typedef union
1236	{
1237	struct
1238	{
1239	RT_GCC_EXTENSION uint64_t u9Size : 9; /*< Bits 8:0 - Size: Size of the device table. /
1240	RT_GCC_EXTENSION uint64_t u3Rsvd0 : 3; /*< Bits 11:9 - Reserved. /
1241	RT_GCC_EXTENSION uint64_t u40Base : 40; /*< Bits 51:12 - DevTabBase: Device table base address. /
1242	RT_GCC_EXTENSION uint64_t u12Rsvd0 : 12; /*< Bits 63:52 - Reserved. /
1243	} n;
1244	/** The 64-bit unsigned integer view. */
1245	uint64_t u64;
1246	} DEV_TAB_BAR_T;
1247	AssertCompileSize(DEV_TAB_BAR_T, 8);
1248	#define IOMMU_DEV_TAB_BAR_VALID_MASK UINT64_C(0x000ffffffffff1ff)
1249	#define IOMMU_DEV_TAB_SEG_BAR_VALID_MASK UINT64_C(0x000ffffffffff0ff)
1250
1251	/**
1252	* Command Buffer Base Address Register (MMIO).
1253	* In accordance with the AMD spec.
1254	*/
1255	typedef union
1256	{
1257	struct
1258	{
1259	RT_GCC_EXTENSION uint64_t u12Rsvd0 : 12; /*< Bits 11:0 - Reserved. /
1260	RT_GCC_EXTENSION uint64_t u40Base : 40; /*< Bits 51:12 - ComBase: Command buffer base address. /
1261	RT_GCC_EXTENSION uint64_t u4Rsvd0 : 4; /*< Bits 55:52 - Reserved. /
1262	RT_GCC_EXTENSION uint64_t u4Len : 4; /*< Bits 59:56 - ComLen: Command buffer length. /
1263	RT_GCC_EXTENSION uint64_t u4Rsvd1 : 4; /*< Bits 63:60 - Reserved. /
1264	} n;
1265	/** The 64-bit unsigned integer view. */
1266	uint64_t u64;
1267	} CMD_BUF_BAR_T;
1268	AssertCompileSize(CMD_BUF_BAR_T, 8);
1269	#define IOMMU_CMD_BUF_BAR_VALID_MASK UINT64_C(0x0f0ffffffffff000)
1270
1271	/**
1272	* Event Log Base Address Register (MMIO).
1273	* In accordance with the AMD spec.
1274	*/
1275	typedef union
1276	{
1277	struct
1278	{
1279	RT_GCC_EXTENSION uint64_t u12Rsvd0 : 12; /*< Bits 11:0 - Reserved. /
1280	RT_GCC_EXTENSION uint64_t u40Base : 40; /*< Bits 51:12 - EventBase: Event log base address. /
1281	RT_GCC_EXTENSION uint64_t u4Rsvd0 : 4; /*< Bits 55:52 - Reserved. /
1282	RT_GCC_EXTENSION uint64_t u4Len : 4; /*< Bits 59:56 - EventLen: Event log length. /
1283	RT_GCC_EXTENSION uint64_t u4Rsvd1 : 4; /*< Bits 63:60 - Reserved. /
1284	} n;
1285	/** The 64-bit unsigned integer view. */
1286	uint64_t u64;
1287	} EVT_LOG_BAR_T;
1288	AssertCompileSize(EVT_LOG_BAR_T, 8);
1289	#define IOMMU_EVT_LOG_BAR_VALID_MASK UINT64_C(0x0f0ffffffffff000)
1290
1291	/**
1292	* IOMMU Control Register (MMIO).
1293	* In accordance with the AMD spec.
1294	*/
1295	typedef union
1296	{
1297	struct
1298	{
1299	uint32_t u1IommuEn : 1; /*< Bit 0 - IommuEn: IOMMU Enable. /
1300	uint32_t u1HtTunEn : 1; /*< Bit 1 - HtTunEn: HyperTransport Tunnel Enable. /
1301	uint32_t u1EvtLogEn : 1; /*< Bit 2 - EventLogEn: Event Log Enable. /
1302	uint32_t u1EvtIntrEn : 1; /*< Bit 3 - EventIntEn: Event Log Interrupt Enable. /
1303	uint32_t u1CompWaitIntrEn : 1; /*< Bit 4 - ComWaitIntEn: Completion Wait Interrupt Enable. /
1304	uint32_t u3InvTimeOut : 3; /*< Bits 7:5 - InvTimeOut: Invalidation Timeout. /
1305	uint32_t u1PassPW : 1; /*< Bit 8 - PassPW: Pass Posted Write. /
1306	uint32_t u1ResPassPW : 1; /*< Bit 9 - ResPassPW: Response Pass Posted Write. /
1307	uint32_t u1Coherent : 1; /*< Bit 10 - Coherent: HT read request packet Coherent bit. /
1308	uint32_t u1Isoc : 1; /*< Bit 11 - Isoc: HT read request packet Isochronous bit. /
1309	uint32_t u1CmdBufEn : 1; /*< Bit 12 - CmdBufEn: Command Buffer Enable. /
1310	uint32_t u1PprLogEn : 1; /*< Bit 13 - PprLogEn: Peripheral Page Request (PPR) Log Enable. /
1311	uint32_t u1PprIntrEn : 1; /*< Bit 14 - PprIntrEn: Peripheral Page Request Interrupt Enable. /
1312	uint32_t u1PprEn : 1; /*< Bit 15 - PprEn: Peripheral Page Request processing Enable. /
1313	uint32_t u1GstTranslateEn : 1; /*< Bit 16 - GTEn: Guest Translate Enable. /
1314	uint32_t u1GstVirtApicEn : 1; /*< Bit 17 - GAEn: Guest Virtual-APIC Enable. /
1315	uint32_t u4Crw : 1; /*< Bits 21:18 - CRW: Intended for future use (not documented). /
1316	uint32_t u1SmiFilterEn : 1; /*< Bit 22 - SmiFEn: SMI Filter Enable. /
1317	uint32_t u1SelfWriteBackDis : 1; /*< Bit 23 - SlfWBDis: Self Write-Back Disable. /
1318	uint32_t u1SmiFilterLogEn : 1; /*< Bit 24 - SmiFLogEn: SMI Filter Log Enable. /
1319	uint32_t u3GstVirtApicModeEn : 3; /*< Bits 27:25 - GAMEn: Guest Virtual-APIC Mode Enable. /
1320	uint32_t u1GstLogEn : 1; /*< Bit 28 - GALogEn: Guest Virtual-APIC GA Log Enable. /
1321	uint32_t u1GstIntrEn : 1; /*< Bit 29 - GAIntEn: Guest Virtual-APIC Interrupt Enable. /
1322	uint32_t u2DualPprLogEn : 2; /*< Bits 31:30 - DualPprLogEn: Dual Peripheral Page Request Log Enable. /
1323	uint32_t u2DualEvtLogEn : 2; /*< Bits 33:32 - DualEventLogEn: Dual Event Log Enable. /
1324	uint32_t u3DevTabSegEn : 3; /*< Bits 36:34 - DevTblSegEn: Device Table Segment Enable. /
1325	uint32_t u2PrivAbortEn : 2; /*< Bits 38:37 - PrivAbrtEn: Privilege Abort Enable. /
1326	uint32_t u1PprAutoRespEn : 1; /*< Bit 39 - PprAutoRspEn: Peripheral Page Request Auto Response Enable. /
1327	uint32_t u1MarcEn : 1; /*< Bit 40 - MarcEn: Memory Address Routing and Control Enable. /
1328	uint32_t u1BlockStopMarkEn : 1; /*< Bit 41 - BlkStopMarkEn: Block StopMark messages Enable. /
1329	uint32_t u1PprAutoRespAlwaysOnEn : 1; /*< Bit 42 - PprAutoRspAon:: PPR Auto Response - Always On Enable. /
1330	uint32_t u1DomainIDPNE : 1; /*< Bit 43 - DomainIDPE: Reserved (not documented). /
1331	uint32_t u1Rsvd0 : 1; /*< Bit 44 - Reserved. /
1332	uint32_t u1EnhancedPpr : 1; /*< Bit 45 - EPHEn: Enhanced Peripheral Page Request Handling Enable. /
1333	uint32_t u2HstAccDirtyBitUpdate : 2; /*< Bits 47:46 - HADUpdate: Access and Dirty Bit updated in host page table. /
1334	uint32_t u1GstDirtyUpdateDis : 1; /*< Bit 48 - GDUpdateDis: Disable hardare update of Dirty bit in GPT. /
1335	uint32_t u1Rsvd1 : 1; /*< Bit 49 - Reserved. /
1336	uint32_t u1X2ApicEn : 1; /*< Bit 50 - XTEn: Enable X2APIC. /
1337	uint32_t u1X2ApicIntrGenEn : 1; /*< Bit 51 - IntCapXTEn: Enable IOMMU X2APIC Interrupt generation. /
1338	uint32_t u2Rsvd0 : 2; /*< Bits 53:52 - Reserved. /
1339	uint32_t u1GstAccessUpdateDis : 1; /*< Bit 54 - GAUpdateDis: Disable hardare update of Access bit in GPT. /
1340	uint32_t u8Rsvd0 : 8; /*< Bits 63:55 - Reserved. /
1341	} n;
1342	/** The 64-bit unsigned integer view. */
1343	uint64_t u64;
1344	} IOMMU_CTRL_T;
1345	AssertCompileSize(IOMMU_CTRL_T, 8);
1346	#define IOMMU_CTRL_VALID_MASK UINT64_C(0x004defffffffffff)
1347	#define IOMMU_CTRL_CMD_BUF_EN_MASK UINT64_C(0x0000000000001001)
1348
1349	/**
1350	* IOMMU Exclusion Base Register (MMIO).
1351	* In accordance with the AMD spec.
1352	*/
1353	typedef union
1354	{
1355	struct
1356	{
1357	RT_GCC_EXTENSION uint64_t u1ExclEnable : 1; /*< Bit 0 - ExEn: Exclusion Range Enable. /
1358	RT_GCC_EXTENSION uint64_t u1AllowAll : 1; /*< Bit 1 - Allow: Allow All Devices. /
1359	RT_GCC_EXTENSION uint64_t u10Rsvd0 : 10; /*< Bits 11:2 - Reserved. /
1360	RT_GCC_EXTENSION uint64_t u40ExclRangeBase : 40; /*< Bits 51:12 - Exclusion Range Base Address. /
1361	RT_GCC_EXTENSION uint64_t u12Rsvd0 : 12; /*< Bits 63:52 - Reserved. /
1362	} n;
1363	/** The 64-bit unsigned integer view. */
1364	uint64_t u64;
1365	} IOMMU_EXCL_RANGE_BAR_T;
1366	AssertCompileSize(IOMMU_EXCL_RANGE_BAR_T, 8);
1367	#define IOMMU_EXCL_RANGE_BAR_VALID_MASK UINT64_C(0x000ffffffffff003)
1368
1369	/**
1370	* IOMMU Exclusion Range Limit Register (MMIO).
1371	* In accordance with the AMD spec.
1372	*/
1373	typedef union
1374	{
1375	struct
1376	{
1377	RT_GCC_EXTENSION uint64_t u52ExclLimit : 52; /*< Bits 51:0 - Exclusion Range Limit (last 12 bits are treated as 1s). /
1378	RT_GCC_EXTENSION uint64_t u12Rsvd1 : 12; /*< Bits 63:52 - Reserved. /
1379	} n;
1380	/** The 64-bit unsigned integer view. */
1381	uint64_t u64;
1382	} IOMMU_EXCL_RANGE_LIMIT_T;
1383	AssertCompileSize(IOMMU_EXCL_RANGE_LIMIT_T, 8);
1384	#define IOMMU_EXCL_RANGE_LIMIT_VALID_MASK UINT64_C(0x000fffffffffffff)
1385
1386	/**
1387	* IOMMU Extended Feature Register (MMIO).
1388	* In accordance with the AMD spec.
1389	*/
1390	typedef union
1391	{
1392	struct
1393	{
1394	uint32_t u1PrefetchSup : 1; /*< Bit 0 - PreFSup: Prefetch Support. /
1395	uint32_t u1PprSup : 1; /*< Bit 1 - PPRSup: Peripheral Page Request Support. /
1396	uint32_t u1X2ApicSup : 1; /*< Bit 2 - XTSup: x2Apic Support. /
1397	uint32_t u1NoExecuteSup : 1; /*< Bit 3 - NXSup: No-Execute and Privilege Level Support. /
1398	uint32_t u1GstTranslateSup : 1; /*< Bit 4 - GTSup: Guest Translations (for GVAs) Support. /
1399	uint32_t u1Rsvd0 : 1; /*< Bit 5 - Reserved. /
1400	uint32_t u1InvAllSup : 1; /*< Bit 6 - IASup: Invalidate-All Support. /
1401	uint32_t u1GstVirtApicSup : 1; /*< Bit 7 - GASup: Guest Virtual-APIC Support. /
1402	uint32_t u1HwErrorSup : 1; /*< Bit 8 - HESup: Hardware Error registers Support. /
1403	uint32_t u1PerfCounterSup : 1; /*< Bit 8 - PCSup: Performance Counter Support. /
1404	uint32_t u2HostAddrTranslateSize : 2; /*< Bits 11:10 - HATS: Host Address Translation Size. /
1405	uint32_t u2GstAddrTranslateSize : 2; /*< Bits 13:12 - GATS: Guest Address Translation Size. /
1406	uint32_t u2GstCr3RootTblLevel : 2; /*< Bits 15:14 - GLXSup: Guest CR3 Root Table Level (Max) Size Support. /
1407	uint32_t u2SmiFilterSup : 2; /*< Bits 17:16 - SmiFSup: SMI Filter Register Support. /
1408	uint32_t u3SmiFilterCount : 3; /*< Bits 20:18 - SmiFRC: SMI Filter Register Count. /
1409	uint32_t u3GstVirtApicModeSup : 3; /*< Bits 23:21 - GAMSup: Guest Virtual-APIC Modes Supported. /
1410	uint32_t u2DualPprLogSup : 2; /*< Bits 25:24 - DualPprLogSup: Dual Peripheral Page Request Log Support. /
1411	uint32_t u2Rsvd0 : 2; /*< Bits 27:26 - Reserved. /
1412	uint32_t u2DualEvtLogSup : 2; /*< Bits 29:28 - DualEventLogSup: Dual Event Log Support. /
1413	uint32_t u2Rsvd1 : 2; /*< Bits 31:30 - Reserved. /
1414	uint32_t u5MaxPasidSup : 5; /*< Bits 36:32 - PASMax: Maximum PASID Supported. /
1415	uint32_t u1UserSupervisorSup : 1; /*< Bit 37 - USSup: User/Supervisor Page Protection Support. /
1416	uint32_t u2DevTabSegSup : 2; /*< Bits 39:38 - DevTlbSegSup: Segmented Device Table Support. /
1417	uint32_t u1PprLogOverflowWarn : 1; /*< Bit 40 - PprOvrflwEarlySup: PPR Log Overflow Early Warning Support. /
1418	uint32_t u1PprAutoRespSup : 1; /*< Bit 41 - PprAutoRspSup: PPR Automatic Response Support. /
1419	uint32_t u2MarcSup : 2; /*< Bit 43:42 - MarcSup: Memory Access Routing and Control Support. /
1420	uint32_t u1BlockStopMarkSup : 1; /*< Bit 44 - BlkStopMarkSup: Block StopMark messages Support. /
1421	uint32_t u1PerfOptSup : 1; /*< Bit 45 - PerfOptSup: IOMMU Performance Optimization Support. /
1422	uint32_t u1MsiCapMmioSup : 1; /*< Bit 46 - MsiCapMmioSup: MSI Capability Register MMIO Access Support. /
1423	uint32_t u1Rsvd1 : 1; /*< Bit 47 - Reserved. /
1424	uint32_t u1GstIoSup : 1; /*< Bit 48 - GIoSup: Guest I/O Protection Support. /
1425	uint32_t u1HostAccessSup : 1; /*< Bit 49 - HASup: Host Access Support. /
1426	uint32_t u1EnhancedPprSup : 1; /*< Bit 50 - EPHSup: Enhanced Peripheral Page Request Handling Support. /
1427	uint32_t u1AttrForwardSup : 1; /*< Bit 51 - AttrFWSup: Attribute Forward Support. /
1428	uint32_t u1HostDirtySup : 1; /*< Bit 52 - HDSup: Host Dirty Support. /
1429	uint32_t u1Rsvd2 : 1; /*< Bit 53 - Reserved. /
1430	uint32_t u1InvIoTlbTypeSup : 1; /*< Bit 54 - InvIotlbTypeSup: Invalidate IOTLB Type Support. /
1431	uint32_t u6Rsvd0 : 6; /*< Bit 60:55 - Reserved. /
1432	uint32_t u1GstUpdateDisSup : 1; /*< Bit 61 - GAUpdateDisSup: Disable hardware update on GPT Support. /
1433	uint32_t u1ForcePhysDstSup : 1; /*< Bit 62 - ForcePhyDestSup: Force Phys. Dst. Mode for Remapped Intr. /
1434	uint32_t u1Rsvd3 : 1; /*< Bit 63 - Reserved. /
1435	} n;
1436	/** The 64-bit unsigned integer view. */
1437	uint64_t u64;
1438	} IOMMU_EXT_FEAT_T;
1439	AssertCompileSize(IOMMU_EXT_FEAT_T, 8);
1440
1441	/**
1442	* Peripheral Page Request Log Base Address Register (MMIO).
1443	* In accordance with the AMD spec.
1444	*/
1445	typedef union
1446	{
1447	struct
1448	{
1449	RT_GCC_EXTENSION uint64_t u12Rsvd0 : 12; /*< Bit 11:0 - Reserved. /
1450	RT_GCC_EXTENSION uint64_t u40Base : 40; /*< Bits 51:12 - PPRLogBase: Peripheral Page Request Log Base Address. /
1451	RT_GCC_EXTENSION uint64_t u4Rsvd0 : 4; /*< Bits 55:52 - Reserved. /
1452	RT_GCC_EXTENSION uint64_t u4Len : 4; /*< Bits 59:56 - PPRLogLen: Peripheral Page Request Log Length. /
1453	RT_GCC_EXTENSION uint64_t u4Rsvd1 : 4; /*< Bits 63:60 - Reserved. /
1454	} n;
1455	/** The 64-bit unsigned integer view. */
1456	uint64_t u64;
1457	} PPR_LOG_BAR_T;
1458	AssertCompileSize(PPR_LOG_BAR_T, 8);
1459	#define IOMMU_PPR_LOG_BAR_VALID_MASK UINT64_C(0x0f0ffffffffff000)
1460
1461	/**
1462	* IOMMU Hardware Event Upper Register (MMIO).
1463	* In accordance with the AMD spec.
1464	*/
1465	typedef union
1466	{
1467	struct
1468	{
1469	RT_GCC_EXTENSION uint64_t u60FirstOperand : 60; /*< Bits 59:0 - First event code dependent operand. /
1470	RT_GCC_EXTENSION uint64_t u4EvtCode : 4; /*< Bits 63:60 - Event Code. /
1471	} n;
1472	/** The 64-bit unsigned integer view. */
1473	uint64_t u64;
1474	} IOMMU_HW_EVT_HI_T;
1475	AssertCompileSize(IOMMU_HW_EVT_HI_T, 8);
1476
1477	/**
1478	* IOMMU Hardware Event Lower Register (MMIO).
1479	* In accordance with the AMD spec.
1480	*/
1481	typedef uint64_t IOMMU_HW_EVT_LO_T;
1482
1483	/**
1484	* IOMMU Hardware Event Status (MMIO).
1485	* In accordance with the AMD spec.
1486	*/
1487	typedef union
1488	{
1489	struct
1490	{
1491	uint32_t u1Valid : 1; /*< Bit 0 - HEV: Hardware Event Valid. /
1492	uint32_t u1Overflow : 1; /*< Bit 1 - HEO: Hardware Event Overflow. /
1493	uint32_t u30Rsvd0 : 30; /*< Bits 31:2 - Reserved. /
1494	uint32_t u32Rsvd0; /*< Bits 63:32 - Reserved. /
1495	} n;
1496	/** The 64-bit unsigned integer view. */
1497	uint64_t u64;
1498	} IOMMU_HW_EVT_STATUS_T;
1499	AssertCompileSize(IOMMU_HW_EVT_STATUS_T, 8);
1500	#define IOMMU_HW_EVT_STATUS_VALID_MASK UINT64_C(0x0000000000000003)
1501
1502	/**
1503	* Guest Virtual-APIC Log Base Address Register (MMIO).
1504	* In accordance with the AMD spec.
1505	*/
1506	typedef union
1507	{
1508	struct
1509	{
1510	RT_GCC_EXTENSION uint64_t u12Rsvd0 : 12; /*< Bit 11:0 - Reserved. /
1511	RT_GCC_EXTENSION uint64_t u40Base : 40; /*< Bits 51:12 - GALogBase: Guest Virtual-APIC Log Base Address. /
1512	RT_GCC_EXTENSION uint64_t u4Rsvd0 : 4; /*< Bits 55:52 - Reserved. /
1513	RT_GCC_EXTENSION uint64_t u4Len : 4; /*< Bits 59:56 - GALogLen: Guest Virtual-APIC Log Length. /
1514	RT_GCC_EXTENSION uint64_t u4Rsvd1 : 4; /*< Bits 63:60 - Reserved. /
1515	} n;
1516	/** The 64-bit unsigned integer view. */
1517	uint64_t u64;
1518	} GALOG_BAR_T;
1519	AssertCompileSize(GALOG_BAR_T, 8);
1520
1521	/**
1522	* Guest Virtual-APIC Log Tail Address Register (MMIO).
1523	* In accordance with the AMD spec.
1524	*/
1525	typedef union
1526	{
1527	struct
1528	{
1529	RT_GCC_EXTENSION uint64_t u3Rsvd0 : 3; /*< Bits 2:0 - Reserved. /
1530	RT_GCC_EXTENSION uint64_t u40GALogTailAddr : 48; /*< Bits 51:3 - GATAddr: Guest Virtual-APIC Tail Log Address. /
1531	RT_GCC_EXTENSION uint64_t u11Rsvd1 : 11; /*< Bits 63:52 - Reserved. /
1532	} n;
1533	/** The 64-bit unsigned integer view. */
1534	uint64_t u64;
1535	} GALOG_TAIL_ADDR_T;
1536	AssertCompileSize(GALOG_TAIL_ADDR_T, 8);
1537
1538	/**
1539	* PPR Log B Base Address Register (MMIO).
1540	* In accordance with the AMD spec.
1541	* Currently identical to PPR_LOG_BAR_T.
1542	*/
1543	typedef PPR_LOG_BAR_T PPR_LOG_B_BAR_T;
1544
1545	/**
1546	* Event Log B Base Address Register (MMIO).
1547	* In accordance with the AMD spec.
1548	* Currently identical to EVT_LOG_BAR_T.
1549	*/
1550	typedef EVT_LOG_BAR_T EVT_LOG_B_BAR_T;
1551
1552	/**
1553	* Device-specific Feature Extension (DSFX) Register (MMIO).
1554	* In accordance with the AMD spec.
1555	*/
1556	typedef union
1557	{
1558	struct
1559	{
1560	uint32_t u24DevSpecFeat : 24; /*< Bits 23:0 - DevSpecificFeatSupp: Implementation specific features. /
1561	uint32_t u4RevMinor : 4; /*< Bits 27:24 - RevMinor: Minor revision identifier. /
1562	uint32_t u4RevMajor : 4; /*< Bits 31:28 - RevMajor: Major revision identifier. /
1563	uint32_t u32Rsvd0; /*< Bits 63:32 - Reserved./
1564	} n;
1565	/** The 64-bit unsigned integer view. */
1566	uint64_t u64;
1567	} DEV_SPECIFIC_FEAT_T;
1568	AssertCompileSize(DEV_SPECIFIC_FEAT_T, 8);
1569
1570	/**
1571	* Device-specific Control Extension (DSCX) Register (MMIO).
1572	* In accordance with the AMD spec.
1573	*/
1574	typedef union
1575	{
1576	struct
1577	{
1578	uint32_t u24DevSpecCtrl : 24; /*< Bits 23:0 - DevSpecificFeatCntrl: Implementation specific control. /
1579	uint32_t u4RevMinor : 4; /*< Bits 27:24 - RevMinor: Minor revision identifier. /
1580	uint32_t u4RevMajor : 4; /*< Bits 31:28 - RevMajor: Major revision identifier. /
1581	uint32_t u32Rsvd0; /*< Bits 63:32 - Reserved./
1582	} n;
1583	/** The 64-bit unsigned integer view. */
1584	uint64_t u64;
1585	} DEV_SPECIFIC_CTRL_T;
1586	AssertCompileSize(DEV_SPECIFIC_CTRL_T, 8);
1587
1588	/**
1589	* Device-specific Status Extension (DSSX) Register (MMIO).
1590	* In accordance with the AMD spec.
1591	*/
1592	typedef union
1593	{
1594	struct
1595	{
1596	uint32_t u24DevSpecStatus : 24; /*< Bits 23:0 - DevSpecificFeatStatus: Implementation specific status. /
1597	uint32_t u4RevMinor : 4; /*< Bits 27:24 - RevMinor: Minor revision identifier. /
1598	uint32_t u4RevMajor : 4; /*< Bits 31:28 - RevMajor: Major revision identifier. /
1599	uint32_t u32Rsvd0; /*< Bits 63:32 - Reserved./
1600	} n;
1601	/** The 64-bit unsigned integer view. */
1602	uint64_t u64;
1603	} DEV_SPECIFIC_STATUS_T;
1604	AssertCompileSize(DEV_SPECIFIC_STATUS_T, 8);
1605
1606	/**
1607	* MSI Information Register 0 and 1 (PCI) / MSI Vector Register 0 and 1 (MMIO).
1608	* In accordance with the AMD spec.
1609	*/
1610	typedef union
1611	{
1612	struct
1613	{
1614	uint32_t u5MsiNumEvtLog : 5; /*< Bits 4:0 - MsiNum: Event Log MSI message number. /
1615	uint32_t u3GstVirtAddrSize: 3; /*< Bits 7:5 - GVAsize: Guest Virtual Address Size. /
1616	uint32_t u7PhysAddrSize : 7; /*< Bits 14:8 - PAsize: Physical Address Size. /
1617	uint32_t u7VirtAddrSize : 7; /*< Bits 21:15 - VAsize: Virtual Address Size. /
1618	uint32_t u1HtAtsResv: 1; /*< Bit 22 - HtAtsResv: HyperTransport ATS Response Address range Reserved. /
1619	uint32_t u4Rsvd0 : 4; /*< Bits 26:23 - Reserved. /
1620	uint32_t u5MsiNumPpr : 5; /*< Bits 31:27 - MsiNumPPR: Peripheral Page Request MSI message number. /
1621	uint32_t u5MsiNumGa : 5; /*< Bits 36:32 - MsiNumGa: MSI message number for guest virtual-APIC log. /
1622	uint32_t u27Rsvd0: 27; /*< Bits 63:37 - Reserved. /
1623	} n;
1624	/** The 32-bit unsigned integer view. */
1625	uint32_t au32[2];
1626	/** The 64-bit unsigned integer view. */
1627	uint64_t u64;
1628	} MSI_MISC_INFO_T;
1629	AssertCompileSize(MSI_MISC_INFO_T, 8);
1630	/** MSI Vector Register 0 and 1 (MMIO). */
1631	typedef MSI_MISC_INFO_T MSI_VECTOR_T;
1632
1633	/**
1634	* MSI Capability Header Register (PCI + MMIO).
1635	* In accordance with the AMD spec.
1636	*/
1637	typedef union
1638	{
1639	struct
1640	{
1641	uint32_t u8MsiCapId : 8; /*< Bits 7:0 - MsiCapId: Capability ID. /
1642	uint32_t u8MsiCapPtr : 8; /*< Bits 15:8 - MsiCapPtr: Pointer (PCI config offset) to the next capability. /
1643	uint32_t u1MsiEnable : 1; /*< Bit 16 - MsiEn: Message Signal Interrupt Enable. /
1644	uint32_t u3MsiMultiMessCap : 3; /*< Bits 19:17 - MsiMultMessCap: MSI Multi-Message Capability. /
1645	uint32_t u3MsiMultiMessEn : 3; /*< Bits 22:20 - MsiMultMessEn: MSI Multi-Message Enable. /
1646	uint32_t u1Msi64BitEn : 1; /*< Bit 23 - Msi64BitEn: MSI 64-bit Enable. /
1647	uint32_t u8Rsvd0 : 8; /*< Bits 31:24 - Reserved. /
1648	} n;
1649	/** The 32-bit unsigned integer view. */
1650	uint32_t u32;
1651	} MSI_CAP_HDR_T;
1652	AssertCompileSize(MSI_CAP_HDR_T, 4);
1653	#define IOMMU_MSI_CAP_HDR_MSI_EN_MASK RT_BIT(16)
1654
1655	/**
1656	* MSI Mapping Capability Header Register (PCI + MMIO).
1657	* In accordance with the AMD spec.
1658	*/
1659	typedef union
1660	{
1661	struct
1662	{
1663	uint32_t u8MsiMapCapId : 8; /*< Bits 7:0 - MsiMapCapId: MSI Map capability ID. /
1664	uint32_t u8Rsvd0 : 8; /*< Bits 15:8 - Reserved. /
1665	uint32_t u1MsiMapEn : 1; /*< Bit 16 - MsiMapEn: MSI Map enable. /
1666	uint32_t u1MsiMapFixed : 1; /*< Bit 17 - MsiMapFixd: MSI Map fixed. /
1667	uint32_t u9Rsvd0 : 9; /*< Bits 26:18 - Reserved. /
1668	uint32_t u5MapCapType : 5; /*< Bits 31:27 - MsiMapCapType: MSI Mapping capability type. /
1669	} n;
1670	/** The 32-bit unsigned integer view. */
1671	uint32_t u32;
1672	} MSI_MAP_CAP_HDR_T;
1673	AssertCompileSize(MSI_MAP_CAP_HDR_T, 4);
1674
1675	/**
1676	* Performance Optimization Control Register (MMIO).
1677	* In accordance with the AMD spec.
1678	*/
1679	typedef union
1680	{
1681	struct
1682	{
1683	uint32_t u13Rsvd0 : 13; /*< Bits 12:0 - Reserved. /
1684	uint32_t u1PerfOptEn : 1; /*< Bit 13 - PerfOptEn: Performance Optimization Enable. /
1685	uint32_t u17Rsvd0 : 18; /*< Bits 31:14 - Reserved. /
1686	} n;
1687	/** The 32-bit unsigned integer view. */
1688	uint32_t u32;
1689	} IOMMU_PERF_OPT_CTRL_T;
1690	AssertCompileSize(IOMMU_PERF_OPT_CTRL_T, 4);
1691
1692	/**
1693	* XT (x2APIC) IOMMU General Interrupt Control Register (MMIO).
1694	* In accordance with the AMD spec.
1695	*/
1696	typedef union
1697	{
1698	struct
1699	{
1700	uint32_t u2Rsvd0 : 2; /*< Bits 1:0 - Reserved./
1701	uint32_t u1X2ApicIntrDstMode : 1; /*< Bit 2 - Destination Mode for general interrupt./
1702	uint32_t u4Rsvd0 : 4; /*< Bits 7:3 - Reserved./
1703	uint32_t u24X2ApicIntrDstLo : 24; /*< Bits 31:8 - Destination for general interrupt (Lo)./
1704	uint32_t u8X2ApicIntrVector : 8; /*< Bits 39:32 - Vector for general interrupt./
1705	uint32_t u1X2ApicIntrDeliveryMode : 1; /*< Bit 40 - Delivery Mode for general interrupt./
1706	uint32_t u15Rsvd0 : 15; /*< Bits 55:41 - Reserved./
1707	uint32_t u7X2ApicIntrDstHi : 7; /*< Bits 63:56 - Destination for general interrupt (Hi) ./
1708	} n;
1709	/** The 64-bit unsigned integer view. */
1710	uint64_t u64;
1711	} IOMMU_XT_GEN_INTR_CTRL_T;
1712	AssertCompileSize(IOMMU_XT_GEN_INTR_CTRL_T, 8);
1713
1714	/**
1715	* XT (x2APIC) IOMMU General Interrupt Control Register (MMIO).
1716	* In accordance with the AMD spec.
1717	*/
1718	typedef union
1719	{
1720	struct
1721	{
1722	uint32_t u2Rsvd0 : 2; /*< Bits 1:0 - Reserved./
1723	uint32_t u1X2ApicIntrDstMode : 1; /*< Bit 2 - Destination Mode for the interrupt./
1724	uint32_t u4Rsvd0 : 4; /*< Bits 7:3 - Reserved./
1725	uint32_t u24X2ApicIntrDstLo : 24; /*< Bits 31:8 - Destination for the interrupt (Lo)./
1726	uint32_t u8X2ApicIntrVector : 8; /*< Bits 39:32 - Vector for the interrupt./
1727	uint32_t u1X2ApicIntrDeliveryMode : 1; /*< Bit 40 - Delivery Mode for the interrupt./
1728	uint32_t u15Rsvd0 : 15; /*< Bits 55:41 - Reserved./
1729	uint32_t u7X2ApicIntrDstHi : 7; /*< Bits 63:56 - Destination for the interrupt (Hi) ./
1730	} n;
1731	/** The 64-bit unsigned integer view. */
1732	uint64_t u64;
1733	} IOMMU_XT_INTR_CTRL_T;
1734	AssertCompileSize(IOMMU_XT_INTR_CTRL_T, 8);
1735
1736	/**
1737	* XT (x2APIC) IOMMU PPR Interrupt Control Register (MMIO).
1738	* In accordance with the AMD spec.
1739	* Currently identical to IOMMU_XT_INTR_CTRL_T.
1740	*/
1741	typedef IOMMU_XT_INTR_CTRL_T IOMMU_XT_PPR_INTR_CTRL_T;
1742
1743	/**
1744	* XT (x2APIC) IOMMU GA (Guest Address) Log Control Register (MMIO).
1745	* In accordance with the AMD spec.
1746	* Currently identical to IOMMU_XT_INTR_CTRL_T.
1747	*/
1748	typedef IOMMU_XT_INTR_CTRL_T IOMMU_XT_GALOG_INTR_CTRL_T;
1749
1750	/**
1751	* Memory Access and Routing Control (MARC) Aperture Base Register (MMIO).
1752	* In accordance with the AMD spec.
1753	*/
1754	typedef union
1755	{
1756	struct
1757	{
1758	RT_GCC_EXTENSION uint64_t u12Rsvd0 : 12; /*< Bits 11:0 - Reserved. /
1759	RT_GCC_EXTENSION uint64_t u40MarcBaseAddr : 40; /*< Bits 51:12 - MarcBaseAddr: MARC Aperture Base Address. /
1760	RT_GCC_EXTENSION uint64_t u12Rsvd1 : 12; /*< Bits 63:52 - Reserved. /
1761	} n;
1762	/** The 64-bit unsigned integer view. */
1763	uint64_t u64;
1764	} MARC_APER_BAR_T;
1765	AssertCompileSize(MARC_APER_BAR_T, 8);
1766
1767	/**
1768	* Memory Access and Routing Control (MARC) Relocation Register (MMIO).
1769	* In accordance with the AMD spec.
1770	*/
1771	typedef union
1772	{
1773	struct
1774	{
1775	RT_GCC_EXTENSION uint64_t u1RelocEn : 1; /*< Bit 0 - RelocEn: Relocation Enabled. /
1776	RT_GCC_EXTENSION uint64_t u1ReadOnly : 1; /*< Bit 1 - ReadOnly: Whether only read-only acceses allowed. /
1777	RT_GCC_EXTENSION uint64_t u10Rsvd0 : 10; /*< Bits 11:2 - Reserved. /
1778	RT_GCC_EXTENSION uint64_t u40MarcRelocAddr : 40; /*< Bits 51:12 - MarcRelocAddr: MARC Aperture Relocation Address. /
1779	RT_GCC_EXTENSION uint64_t u12Rsvd1 : 12; /*< Bits 63:52 - Reserved. /
1780	} n;
1781	/** The 64-bit unsigned integer view. */
1782	uint64_t u64;
1783	} MARC_APER_RELOC_T;
1784	AssertCompileSize(MARC_APER_RELOC_T, 8);
1785
1786	/**
1787	* Memory Access and Routing Control (MARC) Length Register (MMIO).
1788	* In accordance with the AMD spec.
1789	*/
1790	typedef union
1791	{
1792	struct
1793	{
1794	RT_GCC_EXTENSION uint64_t u12Rsvd0 : 12; /*< Bits 11:0 - Reserved. /
1795	RT_GCC_EXTENSION uint64_t u40MarcLength : 40; /*< Bits 51:12 - MarcLength: MARC Aperture Length. /
1796	RT_GCC_EXTENSION uint64_t u12Rsvd1 : 12; /*< Bits 63:52 - Reserved. /
1797	} n;
1798	/** The 64-bit unsigned integer view. */
1799	uint64_t u64;
1800	} MARC_APER_LEN_T;
1801
1802	/**
1803	* Memory Access and Routing Control (MARC) Aperture Register.
1804	* This combines other registers to match the MMIO layout for convenient access.
1805	*/
1806	typedef struct
1807	{
1808	MARC_APER_BAR_T Base;
1809	MARC_APER_RELOC_T Reloc;
1810	MARC_APER_LEN_T Length;
1811	} MARC_APER_T;
1812	AssertCompileSize(MARC_APER_T, 24);
1813
1814	/**
1815	* IOMMU Reserved Register (MMIO).
1816	* In accordance with the AMD spec.
1817	* This register is reserved for hardware use (although RW?).
1818	*/
1819	typedef uint64_t IOMMU_RSVD_REG_T;
1820
1821	/**
1822	* Command Buffer Head Pointer Register (MMIO).
1823	* In accordance with the AMD spec.
1824	*/
1825	typedef union
1826	{
1827	struct
1828	{
1829	uint32_t off; /*< Bits 31:0 - Buffer pointer (offset; 16 byte aligned, 512 KB max). /
1830	uint32_t u32Rsvd0; /*< Bits 63:32 - Reserved. /
1831	} n;
1832	/** The 32-bit unsigned integer view. */
1833	uint32_t au32[2];
1834	/** The 64-bit unsigned integer view. */
1835	uint64_t u64;
1836	} CMD_BUF_HEAD_PTR_T;
1837	AssertCompileSize(CMD_BUF_HEAD_PTR_T, 8);
1838	#define IOMMU_CMD_BUF_HEAD_PTR_VALID_MASK UINT64_C(0x000000000007fff0)
1839
1840	/**
1841	* Command Buffer Tail Pointer Register (MMIO).
1842	* In accordance with the AMD spec.
1843	* Currently identical to CMD_BUF_HEAD_PTR_T.
1844	*/
1845	typedef CMD_BUF_HEAD_PTR_T CMD_BUF_TAIL_PTR_T;
1846	#define IOMMU_CMD_BUF_TAIL_PTR_VALID_MASK IOMMU_CMD_BUF_HEAD_PTR_VALID_MASK
1847
1848	/**
1849	* Event Log Head Pointer Register (MMIO).
1850	* In accordance with the AMD spec.
1851	* Currently identical to CMD_BUF_HEAD_PTR_T.
1852	*/
1853	typedef CMD_BUF_HEAD_PTR_T EVT_LOG_HEAD_PTR_T;
1854	#define IOMMU_EVT_LOG_HEAD_PTR_VALID_MASK IOMMU_CMD_BUF_HEAD_PTR_VALID_MASK
1855
1856	/**
1857	* Event Log Tail Pointer Register (MMIO).
1858	* In accordance with the AMD spec.
1859	* Currently identical to CMD_BUF_HEAD_PTR_T.
1860	*/
1861	typedef CMD_BUF_HEAD_PTR_T EVT_LOG_TAIL_PTR_T;
1862	#define IOMMU_EVT_LOG_TAIL_PTR_VALID_MASK IOMMU_CMD_BUF_HEAD_PTR_VALID_MASK
1863
1864
1865	/**
1866	* IOMMU Status Register (MMIO).
1867	* In accordance with the AMD spec.
1868	*/
1869	typedef union
1870	{
1871	struct
1872	{
1873	uint32_t u1EvtOverflow : 1; /*< Bit 0 - EventOverflow: Event log overflow. /
1874	uint32_t u1EvtLogIntr : 1; /*< Bit 1 - EventLogInt: Event log interrupt. /
1875	uint32_t u1CompWaitIntr : 1; /*< Bit 2 - ComWaitInt: Completion wait interrupt . /
1876	uint32_t u1EvtLogRunning : 1; /*< Bit 3 - EventLogRun: Event logging is running. /
1877	uint32_t u1CmdBufRunning : 1; /*< Bit 4 - CmdBufRun: Command buffer is running. /
1878	uint32_t u1PprOverflow : 1; /*< Bit 5 - PprOverflow: Peripheral Page Request Log (PPR) overflow. /
1879	uint32_t u1PprIntr : 1; /*< Bit 6 - PprInt: PPR interrupt. /
1880	uint32_t u1PprLogRunning : 1; /*< Bit 7 - PprLogRun: PPR logging is running. /
1881	uint32_t u1GstLogRunning : 1; /*< Bit 8 - GALogRun: Guest virtual-APIC logging is running. /
1882	uint32_t u1GstLogOverflow : 1; /*< Bit 9 - GALOverflow: Guest virtual-APIC log overflow. /
1883	uint32_t u1GstLogIntr : 1; /*< Bit 10 - GAInt: Guest virtual-APIC log interrupt. /
1884	uint32_t u1PprOverflowB : 1; /*< Bit 11 - PprOverflowB: PPR log B overflow. /
1885	uint32_t u1PprLogActive : 1; /*< Bit 12 - PprLogActive: PPR log A is active. /
1886	uint32_t u2Rsvd0 : 2; /*< Bits 14:13 - Reserved. /
1887	uint32_t u1EvtOverflowB : 1; /*< Bit 15 - EvtOverflowB: Event log B overflow. /
1888	uint32_t u1EvtLogActive : 1; /*< Bit 16 - EvtLogActive: Event log A active. /
1889	uint32_t u1PprOverflowEarlyB : 1; /*< Bit 17 - PprOverflowEarlyB: PPR log B overflow early warning. /
1890	uint32_t u1PprOverflowEarly : 1; /*< Bit 18 - PprOverflowEarly: PPR log overflow early warning. /
1891	uint32_t u13Rsvd0 : 13; /*< Bits 31:19 - Reserved. /
1892	uint32_t u32Rsvd0; /*< Bits 63:32 - Reserved . /
1893	} n;
1894	/** The 32-bit unsigned integer view. */
1895	uint32_t au32[2];
1896	/** The 64-bit unsigned integer view. */
1897	uint64_t u64;
1898	} IOMMU_STATUS_T;
1899	AssertCompileSize(IOMMU_STATUS_T, 8);
1900	#define IOMMU_STATUS_VALID_MASK UINT64_C(0x0000000000079fff)
1901	#define IOMMU_STATUS_RW1C_MASK UINT64_C(0x0000000000068e67)
1902
1903	/**
1904	* PPR Log Head Pointer Register (MMIO).
1905	* In accordance with the AMD spec.
1906	* Currently identical to CMD_BUF_HEAD_PTR_T.
1907	*/
1908	typedef CMD_BUF_HEAD_PTR_T PPR_LOG_HEAD_PTR_T;
1909
1910	/**
1911	* PPR Log Tail Pointer Register (MMIO).
1912	* In accordance with the AMD spec.
1913	* Currently identical to CMD_BUF_HEAD_PTR_T.
1914	*/
1915	typedef CMD_BUF_HEAD_PTR_T PPR_LOG_TAIL_PTR_T;
1916
1917	/**
1918	* Guest Virtual-APIC Log Head Pointer Register (MMIO).
1919	* In accordance with the AMD spec.
1920	*/
1921	typedef union
1922	{
1923	struct
1924	{
1925	uint32_t u2Rsvd0 : 2; /*< Bits 2:0 - Reserved. /
1926	uint32_t u12GALogPtr : 12; /*< Bits 15:3 - Guest Virtual-APIC Log Head or Tail Pointer. /
1927	uint32_t u16Rsvd0 : 16; /*< Bits 31:16 - Reserved. /
1928	uint32_t u32Rsvd0; /*< Bits 63:32 - Reserved. /
1929	} n;
1930	/** The 32-bit unsigned integer view. */
1931	uint32_t au32[2];
1932	/** The 64-bit unsigned integer view. */
1933	uint64_t u64;
1934	} GALOG_HEAD_PTR_T;
1935	AssertCompileSize(GALOG_HEAD_PTR_T, 8);
1936
1937	/**
1938	* Guest Virtual-APIC Log Tail Pointer Register (MMIO).
1939	* In accordance with the AMD spec.
1940	* Currently identical to GALOG_HEAD_PTR_T.
1941	*/
1942	typedef GALOG_HEAD_PTR_T GALOG_TAIL_PTR_T;
1943
1944	/**
1945	* PPR Log B Head Pointer Register (MMIO).
1946	* In accordance with the AMD spec.
1947	* Currently identical to CMD_BUF_HEAD_PTR_T.
1948	*/
1949	typedef CMD_BUF_HEAD_PTR_T PPR_LOG_B_HEAD_PTR_T;
1950
1951	/**
1952	* PPR Log B Tail Pointer Register (MMIO).
1953	* In accordance with the AMD spec.
1954	* Currently identical to CMD_BUF_HEAD_PTR_T.
1955	*/
1956	typedef CMD_BUF_HEAD_PTR_T PPR_LOG_B_TAIL_PTR_T;
1957
1958	/**
1959	* Event Log B Head Pointer Register (MMIO).
1960	* In accordance with the AMD spec.
1961	* Currently identical to CMD_BUF_HEAD_PTR_T.
1962	*/
1963	typedef CMD_BUF_HEAD_PTR_T EVT_LOG_B_HEAD_PTR_T;
1964
1965	/**
1966	* Event Log B Tail Pointer Register (MMIO).
1967	* In accordance with the AMD spec.
1968	* Currently identical to CMD_BUF_HEAD_PTR_T.
1969	*/
1970	typedef CMD_BUF_HEAD_PTR_T EVT_LOG_B_TAIL_PTR_T;
1971
1972	/**
1973	* PPR Log Auto Response Register (MMIO).
1974	* In accordance with the AMD spec.
1975	*/
1976	typedef union
1977	{
1978	struct
1979	{
1980	uint32_t u4AutoRespCode : 4; /*< Bits 3:0 - PprAutoRespCode: PPR log Auto Response Code. /
1981	uint32_t u1AutoRespMaskGen : 1; /*< Bit 4 - PprAutoRespMaskGn: PPR log Auto Response Mask Gen. /
1982	uint32_t u27Rsvd0 : 27; /*< Bits 31:5 - Reserved. /
1983	uint32_t u32Rsvd0; /*< Bits 63:32 - Reserved./
1984	} n;
1985	/** The 32-bit unsigned integer view. */
1986	uint32_t au32[2];
1987	/** The 64-bit unsigned integer view. */
1988	uint64_t u64;
1989	} PPR_LOG_AUTO_RESP_T;
1990	AssertCompileSize(PPR_LOG_AUTO_RESP_T, 8);
1991
1992	/**
1993	* PPR Log Overflow Early Indicator Register (MMIO).
1994	* In accordance with the AMD spec.
1995	*/
1996	typedef union
1997	{
1998	struct
1999	{
2000	uint32_t u15Threshold : 15; /*< Bits 14:0 - PprOvrflwEarlyThreshold: Overflow early indicator threshold. /
2001	uint32_t u15Rsvd0 : 15; /*< Bits 29:15 - Reserved. /
2002	uint32_t u1IntrEn : 1; /*< Bit 30 - PprOvrflwEarlyIntEn: Overflow early indicator interrupt enable. /
2003	uint32_t u1Enable : 1; /*< Bit 31 - PprOvrflwEarlyEn: Overflow early indicator enable. /
2004	uint32_t u32Rsvd0; /*< Bits 63:32 - Reserved. /
2005	} n;
2006	/** The 32-bit unsigned integer view. */
2007	uint32_t au32[2];
2008	/** The 64-bit unsigned integer view. */
2009	uint64_t u64;
2010	} PPR_LOG_OVERFLOW_EARLY_T;
2011	AssertCompileSize(PPR_LOG_OVERFLOW_EARLY_T, 8);
2012
2013	/**
2014	* PPR Log B Overflow Early Indicator Register (MMIO).
2015	* In accordance with the AMD spec.
2016	* Currently identical to PPR_LOG_OVERFLOW_EARLY_T.
2017	*/
2018	typedef PPR_LOG_OVERFLOW_EARLY_T PPR_LOG_B_OVERFLOW_EARLY_T;
2019
2020	/**
2021	* ILLEGAL_DEV_TABLE_ENTRY Event Types.
2022	* In accordance with the AMD spec.
2023	*/
2024	typedef enum EVT_ILLEGAL_DTE_TYPE_T
2025	{
2026	kIllegalDteType_RsvdNotZero = 0,
2027	kIllegalDteType_RsvdIntTabLen,
2028	kIllegalDteType_RsvdIoCtl,
2029	kIllegalDteType_RsvdIntCtl
2030	} EVT_ILLEGAL_DTE_TYPE_T;
2031
2032	/**
2033	* ILLEGAL_DEV_TABLE_ENTRY Event Types.
2034	* In accordance with the AMD spec.
2035	*/
2036	typedef enum EVT_IO_PAGE_FAULT_TYPE_T
2037	{
2038	/* Memory transaction. */
2039	kIoPageFaultType_DteRsvdPagingMode = 0,
2040	kIoPageFaultType_PteInvalidPageSize,
2041	kIoPageFaultType_PteInvalidLvlEncoding,
2042	kIoPageFaultType_SkippedLevelIovaNotZero,
2043	kIoPageFaultType_PteRsvdNotZero,
2044	kIoPageFaultType_PteValidNotSet,
2045	kIoPageFaultType_DteTranslationDisabled,
2046	kIoPageFaultType_PasidInvalidRange,
2047	kIoPageFaultType_PermDenied,
2048	kIoPageFaultType_UserSupervisor,
2049	/* Interrupt remapping */
2050	kIoPageFaultType_IrteAddrInvalid,
2051	kIoPageFaultType_IrteRsvdNotZero,
2052	kIoPageFaultType_IrteRemapEn,
2053	kIoPageFaultType_IrteRsvdIntType,
2054	kIoPageFaultType_IntrReqAborted,
2055	kIoPageFaultType_IntrWithPasid,
2056	kIoPageFaultType_SmiFilterMismatch,
2057	/* Memory transaction or interrupt remapping. */
2058	kIoPageFaultType_DevId_Invalid
2059	} EVT_IO_PAGE_FAULT_TYPE_T;
2060
2061	/**
2062	* IOTLB_INV_TIMEOUT Event Types.
2063	* In accordance with the AMD spec.
2064	*/
2065	typedef enum EVT_IOTLB_INV_TIMEOUT_TYPE_T
2066	{
2067	InvTimeoutType_NoResponse = 0
2068	} EVT_IOTLB_INV_TIMEOUT_TYPE_T;
2069
2070	/**
2071	* INVALID_DEVICE_REQUEST Event Types.
2072	* In accordance with the AMD spec.
2073	*/
2074	typedef enum EVT_INVALID_DEV_REQ_TYPE_T
2075	{
2076	/* Access. */
2077	kInvalidDevReqType_ReadOrNonPostedWrite = 0,
2078	kInvalidDevReqType_PretranslatedTransaction,
2079	kInvalidDevReqType_PortIo,
2080	kInvalidDevReqType_SysMgt,
2081	kInvalidDevReqType_IntrRange,
2082	kInvalidDevReqType_RsvdIntrRange,
2083	kInvalidDevReqType_SysMgtAddr,
2084	/* Translation Request. */
2085	kInvalidDevReqType_TrAccessInvalid,
2086	kInvalidDevReqType_TrDisabled,
2087	kInvalidDevReqType_DevIdInvalid
2088	} EVT_INVALID_DEV_REQ_TYPE_T;
2089
2090	/**
2091	* INVALID_PPR_REQUEST Event Types.
2092	* In accordance with the AMD spec.
2093	*/
2094	typedef enum EVT_INVALID_PPR_REQ_TYPE_T
2095	{
2096	kInvalidPprReqType_PriNotSupported,
2097	kInvalidPprReqType_GstTranslateDisabled
2098	} EVT_INVALID_PPR_REQ_TYPE_T;
2099
2100
2101	/** @name IVRS format revision field.
2102	* In accordance with the AMD spec.
2103	* @{ */
2104	/** Fixed: Supports only pre-assigned device IDs and type 10h and 11h IVHD
2105	* blocks. */
2106	#define ACPI_IVRS_FMT_REV_FIXED 0x1
2107	/** Mixed: Supports pre-assigned and ACPI HID device naming and all IVHD blocks. */
2108	#define ACPI_IVRS_FMT_REV_MIXED 0x2
2109	/** @} */
2110
2111	/** @name IVHD special device entry variety field.
2112	* In accordance with the AMD spec.
2113	* @{ */
2114	/** I/O APIC. */
2115	#define ACPI_IVHD_VARIETY_IOAPIC 0x1
2116	/** HPET. */
2117	#define ACPI_IVHD_VARIETY_HPET 0x2
2118	/** @} */
2119
2120	/** @name IVHD device entry type codes.
2121	* In accordance with the AMD spec.
2122	* @{ */
2123	/** Reserved. */
2124	#define ACPI_IVHD_DEVENTRY_TYPE_RSVD 0x0
2125	/** All: DTE setting applies to all Device IDs. */
2126	#define ACPI_IVHD_DEVENTRY_TYPE_ALL 0x1
2127	/** Select: DTE setting applies to the device specified in DevId field. */
2128	#define ACPI_IVHD_DEVENTRY_TYPE_SELECT 0x2
2129	/** Start of range: DTE setting applies to all devices from start of range specified
2130	* by the DevId field. */
2131	#define ACPI_IVHD_DEVENTRY_TYPE_START_RANGE 0x3
2132	/** End of range: DTE setting from previous type 3 entry applies to all devices
2133	* incl. DevId specified by this entry. */
2134	#define ACPI_IVHD_DEVENTRY_TYPE_END_RANGE 0x4
2135	/** @} */
2136
2137	/** @name IVHD DTE (Device Table Entry) Settings.
2138	* In accordance with the AMD spec.
2139	* @{ */
2140	/** INITPass: Identifies a device able to assert INIT interrupts. */
2141	#define ACPI_IVHD_DTE_INIT_PASS_SHIFT 0
2142	#define ACPI_IVHD_DTE_INIT_PASS_MASK UINT8_C(0x01)
2143	/** EIntPass: Identifies a device able to assert ExtInt interrupts. */
2144	#define ACPI_IVHD_DTE_EXTINT_PASS_SHIFT 1
2145	#define ACPI_IVHD_DTE_EXTINT_PASS_MASK UINT8_C(0x02)
2146	/** NMIPass: Identifies a device able to assert NMI interrupts. */
2147	#define ACPI_IVHD_DTE_NMI_PASS_SHIFT 2
2148	#define ACPI_IVHD_DTE_NMI_PASS_MASK UINT8_C(0x04)
2149	/** Bit 3 reserved. */
2150	#define ACPI_IVHD_DTE_RSVD_3_SHIFT 3
2151	#define ACPI_IVHD_DTE_RSVD_3_MASK UINT8_C(0x08)
2152	/** SysMgt: Identifies a device able to assert system management messages. */
2153	#define ACPI_IVHD_DTE_SYS_MGT_SHIFT 4
2154	#define ACPI_IVHD_DTE_SYS_MGT_MASK UINT8_C(0x30)
2155	/** Lint0Pass: Identifies a device able to assert LINT0 interrupts. */
2156	#define ACPI_IVHD_DTE_LINT0_PASS_SHIFT 6
2157	#define ACPI_IVHD_DTE_LINT0_PASS_MASK UINT8_C(0x40)
2158	/** Lint0Pass: Identifies a device able to assert LINT1 interrupts. */
2159	#define ACPI_IVHD_DTE_LINT1_PASS_SHIFT 7
2160	#define ACPI_IVHD_DTE_LINT1_PASS_MASK UINT8_C(0x80)
2161	RT_BF_ASSERT_COMPILE_CHECKS(ACPI_IVHD_DTE_, UINT8_C(0), UINT8_MAX,
2162	(INIT_PASS, EXTINT_PASS, NMI_PASS, RSVD_3, SYS_MGT, LINT0_PASS, LINT1_PASS));
2163	/** @} */
2164
2165	/**
2166	* AMD IOMMU: IVHD (I/O Virtualization Hardware Definition) Device Entry (4-byte).
2167	* In accordance with the AMD spec.
2168	*/
2169	#pragma pack(1)
2170	typedef struct ACPIIVHDDEVENTRY4
2171	{
2172	uint8_t u8DevEntryType; /*< Device entry type. /
2173	uint16_t u16DevId; /*< Device ID. /
2174	uint8_t u8DteSetting; /*< DTE (Device Table Entry) setting. /
2175	} ACPIIVHDDEVENTRY4;
2176	#pragma pack()
2177	AssertCompileSize(ACPIIVHDDEVENTRY4, 4);
2178
2179	/**
2180	* AMD IOMMU: IVHD (I/O Virtualization Hardware Definition) Device Entry (8-byte).
2181	* In accordance with the AMD spec.
2182	*/
2183	#pragma pack(1)
2184	typedef struct ACPIIVHDDEVENTRY8
2185	{
2186	uint8_t u8DevEntryType; /*< Device entry type. /
2187	union
2188	{
2189	/** Reserved: When u8DevEntryType is 0x40, 0x41, 0x44 or 0x45 (or 0x49-0x7F). */
2190	struct
2191	{
2192	uint8_t au8Rsvd0[7]; /*< Reserved (MBZ). /
2193	} rsvd;
2194	/** Alias Select: When u8DevEntryType is 0x42 or 0x43. */
2195	struct
2196	{
2197	uint16_t u16DevIdA; /*< Device ID A. /
2198	uint8_t u8DteSetting; /*< DTE (Device Table Entry) setting. /
2199	uint8_t u8Rsvd0; /*< Reserved (MBZ). /
2200	uint16_t u16DevIdB; /*< Device ID B. /
2201	uint8_t u8Rsvd1; /*< Reserved (MBZ). /
2202	} alias;
2203	/** Extended Select: When u8DevEntryType is 0x46 or 0x47. */
2204	struct
2205	{
2206	uint16_t u16DevId; /*< Device ID. /
2207	uint8_t u8DteSetting; /*< DTE (Device Table Entry) setting. /
2208	uint32_t u32ExtDteSetting; /*< Extended DTE setting. /
2209	} ext;
2210	/** Special Device: When u8DevEntryType is 0x48. */
2211	struct
2212	{
2213	uint16_t u16Rsvd0; /*< Reserved (MBZ). /
2214	uint8_t u8DteSetting; /*< DTE (Device Table Entry) setting. /
2215	uint8_t u8Handle; /*< Handle contains I/O APIC ID or HPET number. /
2216	uint16_t u16DevIdB; /*< Device ID B (I/O APIC or HPET). /
2217	uint8_t u8Variety; /*< Whether this is the HPET or I/O APIC. /
2218	} special;
2219	} u;
2220	} ACPIIVHDDEVENTRY8;
2221	#pragma pack()
2222	AssertCompileSize(ACPIIVHDDEVENTRY8, 8);
2223
2224	/** @name IVHD Type 10h Flags.
2225	* In accordance with the AMD spec.
2226	* @{ */
2227	/** Peripheral page request support. */
2228	#define ACPI_IVHD_10H_F_PPR_SUP RT_BIT(7)
2229	/** Prefetch IOMMU pages command support. */
2230	#define ACPI_IVHD_10H_F_PREF_SUP RT_BIT(6)
2231	/** Coherent control. */
2232	#define ACPI_IVHD_10H_F_COHERENT RT_BIT(5)
2233	/** Remote IOTLB support. */
2234	#define ACPI_IVHD_10H_F_IOTLB_SUP RT_BIT(4)
2235	/** Isochronous control. */
2236	#define ACPI_IVHD_10H_F_ISOC RT_BIT(3)
2237	/** Response Pass Posted Write. */
2238	#define ACPI_IVHD_10H_F_RES_PASS_PW RT_BIT(2)
2239	/** Pass Posted Write. */
2240	#define ACPI_IVHD_10H_F_PASS_PW RT_BIT(1)
2241	/** HyperTransport Tunnel. */
2242	#define ACPI_IVHD_10H_F_HT_TUNNEL RT_BIT(0)
2243	/** @} */
2244
2245	/** @name IVRS IVinfo field.
2246	* In accordance with the AMD spec.
2247	* @{ */
2248	/** EFRSup: Extended Feature Support. */
2249	#define ACPI_IVINFO_BF_EFR_SUP_SHIFT 0
2250	#define ACPI_IVINFO_BF_EFR_SUP_MASK UINT32_C(0x00000001)
2251	/** DMA Remap Sup: DMA remapping support (pre-boot DMA protection with
2252	* mandatory remapping of device accessed memory). */
2253	#define ACPI_IVINFO_BF_DMA_REMAP_SUP_SHIFT 1
2254	#define ACPI_IVINFO_BF_DMA_REMAP_SUP_MASK UINT32_C(0x00000002)
2255	/** Bits 4:2 reserved. */
2256	#define ACPI_IVINFO_BF_RSVD_2_4_SHIFT 2
2257	#define ACPI_IVINFO_BF_RSVD_2_4_MASK UINT32_C(0x0000001c)
2258	/** GVASize: Guest virtual-address size. */
2259	#define ACPI_IVINFO_BF_GVA_SIZE_SHIFT 5
2260	#define ACPI_IVINFO_BF_GVA_SIZE_MASK UINT32_C(0x000000e0)
2261	/** PASize: System physical address size. */
2262	#define ACPI_IVINFO_BF_PA_SIZE_SHIFT 8
2263	#define ACPI_IVINFO_BF_PA_SIZE_MASK UINT32_C(0x00007f00)
2264	/** VASize: Virtual address size. */
2265	#define ACPI_IVINFO_BF_VA_SIZE_SHIFT 15
2266	#define ACPI_IVINFO_BF_VA_SIZE_MASK UINT32_C(0x003f8000)
2267	/** HTAtsResv: HyperTransport ATS-response address translation range reserved. */
2268	#define ACPI_IVINFO_BF_HT_ATS_RESV_SHIFT 22
2269	#define ACPI_IVINFO_BF_HT_ATS_RESV_MASK UINT32_C(0x00400000)
2270	/** Bits 31:23 reserved. */
2271	#define ACPI_IVINFO_BF_RSVD_23_31_SHIFT 23
2272	#define ACPI_IVINFO_BF_RSVD_23_31_MASK UINT32_C(0xff800000)
2273	RT_BF_ASSERT_COMPILE_CHECKS(ACPI_IVINFO_BF_, UINT32_C(0), UINT32_MAX,
2274	(EFR_SUP, DMA_REMAP_SUP, RSVD_2_4, GVA_SIZE, PA_SIZE, VA_SIZE, HT_ATS_RESV, RSVD_23_31));
2275	/** @} */
2276
2277	/** @name IVHD IOMMU info flags.
2278	* In accordance with the AMD spec.
2279	* @{ */
2280	/** MSI message number for the event log. */
2281	#define ACPI_IOMMU_INFO_BF_MSI_NUM_SHIFT 0
2282	#define ACPI_IOMMU_INFO_BF_MSI_NUM_MASK UINT16_C(0x001f)
2283	/** Bits 7:5 reserved. */
2284	#define ACPI_IOMMU_INFO_BF_RSVD_5_7_SHIFT 5
2285	#define ACPI_IOMMU_INFO_BF_RSVD_5_7_MASK UINT16_C(0x00e0)
2286	/** IOMMU HyperTransport Unit ID number. */
2287	#define ACPI_IOMMU_INFO_BF_UNIT_ID_SHIFT 8
2288	#define ACPI_IOMMU_INFO_BF_UNIT_ID_MASK UINT16_C(0x1f00)
2289	/** Bits 15:13 reserved. */
2290	#define ACPI_IOMMU_INFO_BF_RSVD_13_15_SHIFT 13
2291	#define ACPI_IOMMU_INFO_BF_RSVD_13_15_MASK UINT16_C(0xe000)
2292	RT_BF_ASSERT_COMPILE_CHECKS(ACPI_IOMMU_INFO_BF_, UINT16_C(0), UINT16_MAX,
2293	(MSI_NUM, RSVD_5_7, UNIT_ID, RSVD_13_15));
2294	/** @} */
2295
2296	/** @name IVHD IOMMU feature reporting field.
2297	* In accordance with the AMD spec.
2298	* @{ */
2299	/** x2APIC supported for peripherals. */
2300	#define ACPI_IOMMU_FEAT_BF_XT_SUP_SHIFT 0
2301	#define ACPI_IOMMU_FEAT_BF_XT_SUP_MASK UINT32_C(0x00000001)
2302	/** NX supported for I/O. */
2303	#define ACPI_IOMMU_FEAT_BF_NX_SUP_SHIFT 1
2304	#define ACPI_IOMMU_FEAT_BF_NX_SUP_MASK UINT32_C(0x00000002)
2305	/** GT (Guest Translation) supported. */
2306	#define ACPI_IOMMU_FEAT_BF_GT_SUP_SHIFT 2
2307	#define ACPI_IOMMU_FEAT_BF_GT_SUP_MASK UINT32_C(0x00000004)
2308	/** GLX (Number of guest CR3 tables) supported. */
2309	#define ACPI_IOMMU_FEAT_BF_GLX_SUP_SHIFT 3
2310	#define ACPI_IOMMU_FEAT_BF_GLX_SUP_MASK UINT32_C(0x00000018)
2311	/** IA (INVALIDATE_IOMMU_ALL) command supported. */
2312	#define ACPI_IOMMU_FEAT_BF_IA_SUP_SHIFT 5
2313	#define ACPI_IOMMU_FEAT_BF_IA_SUP_MASK UINT32_C(0x00000020)
2314	/** GA (Guest virtual APIC) supported. */
2315	#define ACPI_IOMMU_FEAT_BF_GA_SUP_SHIFT 6
2316	#define ACPI_IOMMU_FEAT_BF_GA_SUP_MASK UINT32_C(0x00000040)
2317	/** HE (Hardware error) registers supported. */
2318	#define ACPI_IOMMU_FEAT_BF_HE_SUP_SHIFT 7
2319	#define ACPI_IOMMU_FEAT_BF_HE_SUP_MASK UINT32_C(0x00000080)
2320	/** PASMax (maximum PASID) supported. Ignored if PPRSup=0. */
2321	#define ACPI_IOMMU_FEAT_BF_PAS_MAX_SHIFT 8
2322	#define ACPI_IOMMU_FEAT_BF_PAS_MAX_MASK UINT32_C(0x00001f00)
2323	/** PNCounters (Number of performance counters per counter bank) supported. */
2324	#define ACPI_IOMMU_FEAT_BF_PN_COUNTERS_SHIFT 13
2325	#define ACPI_IOMMU_FEAT_BF_PN_COUNTERS_MASK UINT32_C(0x0001e000)
2326	/** PNBanks (Number of performance counter banks) supported. */
2327	#define ACPI_IOMMU_FEAT_BF_PN_BANKS_SHIFT 17
2328	#define ACPI_IOMMU_FEAT_BF_PN_BANKS_MASK UINT32_C(0x007e0000)
2329	/** MSINumPPR (MSI number for peripheral page requests). */
2330	#define ACPI_IOMMU_FEAT_BF_MSI_NUM_PPR_SHIFT 23
2331	#define ACPI_IOMMU_FEAT_BF_MSI_NUM_PPR_MASK UINT32_C(0x0f800000)
2332	/** GATS (Guest address translation size). MBZ when GTSup=0. */
2333	#define ACPI_IOMMU_FEAT_BF_GATS_SHIFT 28
2334	#define ACPI_IOMMU_FEAT_BF_GATS_MASK UINT32_C(0x30000000)
2335	/** HATS (Host address translation size). */
2336	#define ACPI_IOMMU_FEAT_BF_HATS_SHIFT 30
2337	#define ACPI_IOMMU_FEAT_BF_HATS_MASK UINT32_C(0xc0000000)
2338	RT_BF_ASSERT_COMPILE_CHECKS(ACPI_IOMMU_FEAT_BF_, UINT32_C(0), UINT32_MAX,
2339	(XT_SUP, NX_SUP, GT_SUP, GLX_SUP, IA_SUP, GA_SUP, HE_SUP, PAS_MAX, PN_COUNTERS, PN_BANKS,
2340	MSI_NUM_PPR, GATS, HATS));
2341	/** @} */
2342
2343	/** @name IOMMU Extended Feature Register (PCI/MMIO/ACPI).
2344	* In accordance with the AMD spec.
2345	* @{ */
2346	/** PreFSup: Prefetch support (RO). */
2347	#define IOMMU_EXT_FEAT_BF_PREF_SUP_SHIFT 0
2348	#define IOMMU_EXT_FEAT_BF_PREF_SUP_MASK UINT64_C(0x0000000000000001)
2349	/** PPRSup: Peripheral Page Request (PPR) support (RO). */
2350	#define IOMMU_EXT_FEAT_BF_PPR_SUP_SHIFT 1
2351	#define IOMMU_EXT_FEAT_BF_PPR_SUP_MASK UINT64_C(0x0000000000000002)
2352	/** XTSup: x2APIC support (RO). */
2353	#define IOMMU_EXT_FEAT_BF_X2APIC_SUP_SHIFT 2
2354	#define IOMMU_EXT_FEAT_BF_X2APIC_SUP_MASK UINT64_C(0x0000000000000004)
2355	/** NXSup: No Execute (PMR and PRIV) support (RO). */
2356	#define IOMMU_EXT_FEAT_BF_NO_EXEC_SUP_SHIFT 3
2357	#define IOMMU_EXT_FEAT_BF_NO_EXEC_SUP_MASK UINT64_C(0x0000000000000008)
2358	/** GTSup: Guest Translation support (RO). */
2359	#define IOMMU_EXT_FEAT_BF_GT_SUP_SHIFT 4
2360	#define IOMMU_EXT_FEAT_BF_GT_SUP_MASK UINT64_C(0x0000000000000010)
2361	/** Bit 5 reserved. */
2362	#define IOMMU_EXT_FEAT_BF_RSVD_5_SHIFT 5
2363	#define IOMMU_EXT_FEAT_BF_RSVD_5_MASK UINT64_C(0x0000000000000020)
2364	/** IASup: INVALIDATE_IOMMU_ALL command support (RO). */
2365	#define IOMMU_EXT_FEAT_BF_IA_SUP_SHIFT 6
2366	#define IOMMU_EXT_FEAT_BF_IA_SUP_MASK UINT64_C(0x0000000000000040)
2367	/** GASup: Guest virtual-APIC support (RO). */
2368	#define IOMMU_EXT_FEAT_BF_GA_SUP_SHIFT 7
2369	#define IOMMU_EXT_FEAT_BF_GA_SUP_MASK UINT64_C(0x0000000000000080)
2370	/** HESup: Hardware error registers support (RO). */
2371	#define IOMMU_EXT_FEAT_BF_HE_SUP_SHIFT 8
2372	#define IOMMU_EXT_FEAT_BF_HE_SUP_MASK UINT64_C(0x0000000000000100)
2373	/** PCSup: Performance counters support (RO). */
2374	#define IOMMU_EXT_FEAT_BF_PC_SUP_SHIFT 9
2375	#define IOMMU_EXT_FEAT_BF_PC_SUP_MASK UINT64_C(0x0000000000000200)
2376	/** HATS: Host Address Translation Size (RO). */
2377	#define IOMMU_EXT_FEAT_BF_HATS_SHIFT 10
2378	#define IOMMU_EXT_FEAT_BF_HATS_MASK UINT64_C(0x0000000000000c00)
2379	/** GATS: Guest Address Translation Size (RO). */
2380	#define IOMMU_EXT_FEAT_BF_GATS_SHIFT 12
2381	#define IOMMU_EXT_FEAT_BF_GATS_MASK UINT64_C(0x0000000000003000)
2382	/** GLXSup: Guest CR3 root table level support (RO). */
2383	#define IOMMU_EXT_FEAT_BF_GLX_SUP_SHIFT 14
2384	#define IOMMU_EXT_FEAT_BF_GLX_SUP_MASK UINT64_C(0x000000000000c000)
2385	/** SmiFSup: SMI filter register support (RO). */
2386	#define IOMMU_EXT_FEAT_BF_SMI_FLT_SUP_SHIFT 16
2387	#define IOMMU_EXT_FEAT_BF_SMI_FLT_SUP_MASK UINT64_C(0x0000000000030000)
2388	/** SmiFRC: SMI filter register count (RO). */
2389	#define IOMMU_EXT_FEAT_BF_SMI_FLT_REG_CNT_SHIFT 18
2390	#define IOMMU_EXT_FEAT_BF_SMI_FLT_REG_CNT_MASK UINT64_C(0x00000000001c0000)
2391	/** GAMSup: Guest virtual-APIC modes support (RO). */
2392	#define IOMMU_EXT_FEAT_BF_GAM_SUP_SHIFT 21
2393	#define IOMMU_EXT_FEAT_BF_GAM_SUP_MASK UINT64_C(0x0000000000e00000)
2394	/** DualPprLogSup: Dual PPR Log support (RO). */
2395	#define IOMMU_EXT_FEAT_BF_DUAL_PPR_LOG_SUP_SHIFT 24
2396	#define IOMMU_EXT_FEAT_BF_DUAL_PPR_LOG_SUP_MASK UINT64_C(0x0000000003000000)
2397	/** Bits 27:26 reserved. */
2398	#define IOMMU_EXT_FEAT_BF_RSVD_26_27_SHIFT 26
2399	#define IOMMU_EXT_FEAT_BF_RSVD_26_27_MASK UINT64_C(0x000000000c000000)
2400	/** DualEventLogSup: Dual Event Log support (RO). */
2401	#define IOMMU_EXT_FEAT_BF_DUAL_EVT_LOG_SUP_SHIFT 28
2402	#define IOMMU_EXT_FEAT_BF_DUAL_EVT_LOG_SUP_MASK UINT64_C(0x0000000030000000)
2403	/** Bits 31:30 reserved. */
2404	#define IOMMU_EXT_FEAT_BF_RSVD_30_31_SHIFT 30
2405	#define IOMMU_EXT_FEAT_BF_RSVD_30_31_MASK UINT64_C(0x00000000c0000000)
2406	/** PASMax: Maximum PASID support (RO). */
2407	#define IOMMU_EXT_FEAT_BF_PASID_MAX_SHIFT 32
2408	#define IOMMU_EXT_FEAT_BF_PASID_MAX_MASK UINT64_C(0x0000001f00000000)
2409	/** USSup: User/Supervisor support (RO). */
2410	#define IOMMU_EXT_FEAT_BF_US_SUP_SHIFT 37
2411	#define IOMMU_EXT_FEAT_BF_US_SUP_MASK UINT64_C(0x0000002000000000)
2412	/** DevTblSegSup: Segmented Device Table support (RO). */
2413	#define IOMMU_EXT_FEAT_BF_DEV_TBL_SEG_SUP_SHIFT 38
2414	#define IOMMU_EXT_FEAT_BF_DEV_TBL_SEG_SUP_MASK UINT64_C(0x000000c000000000)
2415	/** PprOverflwEarlySup: PPR Log Overflow Early warning support (RO). */
2416	#define IOMMU_EXT_FEAT_BF_PPR_OVERFLOW_EARLY_SHIFT 40
2417	#define IOMMU_EXT_FEAT_BF_PPR_OVERFLOW_EARLY_MASK UINT64_C(0x0000010000000000)
2418	/** PprAutoRspSup: PPR Automatic Response support (RO). */
2419	#define IOMMU_EXT_FEAT_BF_PPR_AUTO_RES_SUP_SHIFT 41
2420	#define IOMMU_EXT_FEAT_BF_PPR_AUTO_RES_SUP_MASK UINT64_C(0x0000020000000000)
2421	/** MarcSup: Memory Access and Routing (MARC) support (RO). */
2422	#define IOMMU_EXT_FEAT_BF_MARC_SUP_SHIFT 42
2423	#define IOMMU_EXT_FEAT_BF_MARC_SUP_MASK UINT64_C(0x00000c0000000000)
2424	/** BlkStopMrkSup: Block StopMark message support (RO). */
2425	#define IOMMU_EXT_FEAT_BF_BLKSTOP_MARK_SUP_SHIFT 44
2426	#define IOMMU_EXT_FEAT_BF_BLKSTOP_MARK_SUP_MASK UINT64_C(0x0000100000000000)
2427	/** PerfOptSup: IOMMU Performance Optimization support (RO). */
2428	#define IOMMU_EXT_FEAT_BF_PERF_OPT_SUP_SHIFT 45
2429	#define IOMMU_EXT_FEAT_BF_PERF_OPT_SUP_MASK UINT64_C(0x0000200000000000)
2430	/** MsiCapMmioSup: MSI-Capability Register MMIO access support (RO). */
2431	#define IOMMU_EXT_FEAT_BF_MSI_CAP_MMIO_SUP_SHIFT 46
2432	#define IOMMU_EXT_FEAT_BF_MSI_CAP_MMIO_SUP_MASK UINT64_C(0x0000400000000000)
2433	/** Bit 47 reserved. */
2434	#define IOMMU_EXT_FEAT_BF_RSVD_47_SHIFT 47
2435	#define IOMMU_EXT_FEAT_BF_RSVD_47_MASK UINT64_C(0x0000800000000000)
2436	/** GIoSup: Guest I/O Protection support (RO). */
2437	#define IOMMU_EXT_FEAT_BF_GST_IO_PROT_SUP_SHIFT 48
2438	#define IOMMU_EXT_FEAT_BF_GST_IO_PROT_SUP_MASK UINT64_C(0x0001000000000000)
2439	/** HASup: Host Access support (RO). */
2440	#define IOMMU_EXT_FEAT_BF_HST_ACCESS_SUP_SHIFT 49
2441	#define IOMMU_EXT_FEAT_BF_HST_ACCESS_SUP_MASK UINT64_C(0x0002000000000000)
2442	/** EPHSup: Enhandled PPR Handling support (RO). */
2443	#define IOMMU_EXT_FEAT_BF_ENHANCED_PPR_SUP_SHIFT 50
2444	#define IOMMU_EXT_FEAT_BF_ENHANCED_PPR_SUP_MASK UINT64_C(0x0004000000000000)
2445	/** AttrFWSup: Attribute Forward support (RO). */
2446	#define IOMMU_EXT_FEAT_BF_ATTR_FW_SUP_SHIFT 51
2447	#define IOMMU_EXT_FEAT_BF_ATTR_FW_SUP_MASK UINT64_C(0x0008000000000000)
2448	/** HDSup: Host Dirty Support (RO). */
2449	#define IOMMU_EXT_FEAT_BF_HST_DIRTY_SUP_SHIFT 52
2450	#define IOMMU_EXT_FEAT_BF_HST_DIRTY_SUP_MASK UINT64_C(0x0010000000000000)
2451	/** Bit 53 reserved. */
2452	#define IOMMU_EXT_FEAT_BF_RSVD_53_SHIFT 53
2453	#define IOMMU_EXT_FEAT_BF_RSVD_53_MASK UINT64_C(0x0020000000000000)
2454	/** InvIotlbTypeSup: Invalidate IOTLB type support (RO). */
2455	#define IOMMU_EXT_FEAT_BF_INV_IOTLB_TYPE_SUP_SHIFT 54
2456	#define IOMMU_EXT_FEAT_BF_INV_IOTLB_TYPE_SUP_MASK UINT64_C(0x0040000000000000)
2457	/** Bits 60:55 reserved. */
2458	#define IOMMU_EXT_FEAT_BF_RSVD_55_60_SHIFT 55
2459	#define IOMMU_EXT_FEAT_BF_RSVD_55_60_MASK UINT64_C(0x1f80000000000000)
2460	/** GAUpdateDisSup: Support disabling hardware update on guest page table access
2461	* (RO). */
2462	#define IOMMU_EXT_FEAT_BF_GA_UPDATE_DIS_SUP_SHIFT 61
2463	#define IOMMU_EXT_FEAT_BF_GA_UPDATE_DIS_SUP_MASK UINT64_C(0x2000000000000000)
2464	/** ForcePhysDestSup: Force Physical Destination Mode for Remapped Interrupt
2465	* support (RO). */
2466	#define IOMMU_EXT_FEAT_BF_FORCE_PHYS_DST_SUP_SHIFT 62
2467	#define IOMMU_EXT_FEAT_BF_FORCE_PHYS_DST_SUP_MASK UINT64_C(0x4000000000000000)
2468	/** Bit 63 reserved. */
2469	#define IOMMU_EXT_FEAT_BF_RSVD_63_SHIFT 63
2470	#define IOMMU_EXT_FEAT_BF_RSVD_63_MASK UINT64_C(0x8000000000000000)
2471	RT_BF_ASSERT_COMPILE_CHECKS(IOMMU_EXT_FEAT_BF_, UINT64_C(0), UINT64_MAX,
2472	(PREF_SUP, PPR_SUP, X2APIC_SUP, NO_EXEC_SUP, GT_SUP, RSVD_5, IA_SUP, GA_SUP, HE_SUP, PC_SUP,
2473	HATS, GATS, GLX_SUP, SMI_FLT_SUP, SMI_FLT_REG_CNT, GAM_SUP, DUAL_PPR_LOG_SUP, RSVD_26_27,
2474	DUAL_EVT_LOG_SUP, RSVD_30_31, PASID_MAX, US_SUP, DEV_TBL_SEG_SUP, PPR_OVERFLOW_EARLY,
2475	PPR_AUTO_RES_SUP, MARC_SUP, BLKSTOP_MARK_SUP, PERF_OPT_SUP, MSI_CAP_MMIO_SUP, RSVD_47,
2476	GST_IO_PROT_SUP, HST_ACCESS_SUP, ENHANCED_PPR_SUP, ATTR_FW_SUP, HST_DIRTY_SUP, RSVD_53,
2477	INV_IOTLB_TYPE_SUP, RSVD_55_60, GA_UPDATE_DIS_SUP, FORCE_PHYS_DST_SUP, RSVD_63));
2478	/** @} */
2479
2480	/**
2481	* IVHD (I/O Virtualization Hardware Definition) Type 10h.
2482	* In accordance with the AMD spec.
2483	*/
2484	typedef struct ACPIIVHDTYPE10
2485	{
2486	uint8_t u8Type; /*< Type: Must be 0x10. /
2487	uint8_t u8Flags; /*< Flags (see ACPI_IVHD_10H_F_XXX). /
2488	uint16_t u16Length; /*< Length of IVHD including IVHD device entries. /
2489	uint16_t u16DeviceId; /*< Device ID of the IOMMU. /
2490	uint16_t u16CapOffset; /*< Offset in Capability space for control fields of IOMMU. /
2491	uint64_t u64BaseAddress; /*< Base address of IOMMU control registers in MMIO space. /
2492	uint16_t u16PciSegmentGroup; /*< PCI segment group number. /
2493	uint16_t u16IommuInfo; /*< Interrupt number and Unit ID. /
2494	uint32_t u32Features; /*< IOMMU feature reporting. /
2495	/* IVHD device entry block follows. */
2496	} ACPIIVHDTYPE10;
2497	AssertCompileSize(ACPIIVHDTYPE10, 24);
2498
2499	/** @name IVHD Type 11h Flags.
2500	* In accordance with the AMD spec.
2501	* @{ */
2502	/** Coherent control. */
2503	#define ACPI_IVHD_11H_F_COHERENT RT_BIT(5)
2504	/** Remote IOTLB support. */
2505	#define ACPI_IVHD_11H_F_IOTLB_SUP RT_BIT(4)
2506	/** Isochronous control. */
2507	#define ACPI_IVHD_11H_F_ISOC RT_BIT(3)
2508	/** Response Pass Posted Write. */
2509	#define ACPI_IVHD_11H_F_RES_PASS_PW RT_BIT(2)
2510	/** Pass Posted Write. */
2511	#define ACPI_IVHD_11H_F_PASS_PW RT_BIT(1)
2512	/** HyperTransport Tunnel. */
2513	#define ACPI_IVHD_11H_F_HT_TUNNEL RT_BIT(0)
2514	/** @} */
2515
2516	/** @name IVHD IOMMU Type 11 Attributes field.
2517	* In accordance with the AMD spec.
2518	* @{ */
2519	/** Bits 12:0 reserved. */
2520	#define ACPI_IOMMU_ATTR_BF_RSVD_0_12_SHIFT 0
2521	#define ACPI_IOMMU_ATTR_BF_RSVD_0_12_MASK UINT32_C(0x00001fff)
2522	/** PNCounters: Number of performance counters per counter bank. */
2523	#define ACPI_IOMMU_ATTR_BF_PN_COUNTERS_SHIFT 13
2524	#define ACPI_IOMMU_ATTR_BF_PN_COUNTERS_MASK UINT32_C(0x0001e000)
2525	/** PNBanks: Number of performance counter banks. */
2526	#define ACPI_IOMMU_ATTR_BF_PN_BANKS_SHIFT 17
2527	#define ACPI_IOMMU_ATTR_BF_PN_BANKS_MASK UINT32_C(0x007e0000)
2528	/** MSINumPPR: MSI number for peripheral page requests (PPR). */
2529	#define ACPI_IOMMU_ATTR_BF_MSI_NUM_PPR_SHIFT 23
2530	#define ACPI_IOMMU_ATTR_BF_MSI_NUM_PPR_MASK UINT32_C(0x0f800000)
2531	/** Bits 31:28 reserved. */
2532	#define ACPI_IOMMU_ATTR_BF_RSVD_28_31_SHIFT 28
2533	#define ACPI_IOMMU_ATTR_BF_RSVD_28_31_MASK UINT32_C(0xf0000000)
2534	RT_BF_ASSERT_COMPILE_CHECKS(ACPI_IOMMU_ATTR_BF_, UINT32_C(0), UINT32_MAX,
2535	(RSVD_0_12, PN_COUNTERS, PN_BANKS, MSI_NUM_PPR, RSVD_28_31));
2536	/** @} */
2537
2538	/**
2539	* AMD IOMMU: IVHD (I/O Virtualization Hardware Definition) Type 11h.
2540	* In accordance with the AMD spec.
2541	*/
2542	typedef struct ACPIIVHDTYPE11
2543	{
2544	uint8_t u8Type; /*< Type: Must be 0x11. /
2545	uint8_t u8Flags; /*< Flags. /
2546	uint16_t u16Length; /*< Length: Size starting from Type fields incl. IVHD device entries. /
2547	uint16_t u16DeviceId; /*< Device ID of the IOMMU. /
2548	uint16_t u16CapOffset; /*< Offset in Capability space for control fields of IOMMU. /
2549	uint64_t u64BaseAddress; /*< Base address of IOMMU control registers in MMIO space. /
2550	uint16_t u16PciSegmentGroup; /*< PCI segment group number. /
2551	uint16_t u16IommuInfo; /*< Interrupt number and unit ID. /
2552	uint32_t u32IommuAttr; /*< IOMMU info. not reported in EFR. /
2553	uint64_t u64EfrRegister; /*< Extended Feature Register (must be identical to its MMIO shadow). /
2554	uint64_t u64Rsvd0; /*< Reserved for future. /
2555	/* IVHD device entry block follows. */
2556	} ACPIIVHDTYPE11;
2557	AssertCompileSize(ACPIIVHDTYPE11, 40);
2558
2559	/**
2560	* AMD IOMMU: IVHD (I/O Virtualization Hardware Definition) Type 40h.
2561	* In accordance with the AMD spec.
2562	*/
2563	typedef struct ACPIIVHDTYPE11 ACPIIVHDTYPE40;
2564
2565	#endif /* !VBOX_INCLUDED_iommu_amd_h */

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source: vbox/trunk/include/VBox/iommu-amd.h@ 86065

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