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source: vbox/trunk/include/VBox/iommu-intel.h

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1/** @file
2 * IOMMU - Input/Output Memory Management Unit (Intel).
3 */
4
5/*
6 * Copyright (C) 2021-2024 Oracle and/or its affiliates.
7 *
8 * This file is part of VirtualBox base platform packages, as
9 * available from https://www.virtualbox.org.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * as published by the Free Software Foundation, in version 3 of the
14 * License.
15 *
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, see <https://www.gnu.org/licenses>.
23 *
24 * The contents of this file may alternatively be used under the terms
25 * of the Common Development and Distribution License Version 1.0
26 * (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
27 * in the VirtualBox distribution, in which case the provisions of the
28 * CDDL are applicable instead of those of the GPL.
29 *
30 * You may elect to license modified versions of this file under the
31 * terms and conditions of either the GPL or the CDDL or both.
32 *
33 * SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
34 */
35
36#ifndef VBOX_INCLUDED_iommu_intel_h
37#define VBOX_INCLUDED_iommu_intel_h
38#ifndef RT_WITHOUT_PRAGMA_ONCE
39# pragma once
40#endif
41
42#include <iprt/assertcompile.h>
43#include <iprt/types.h>
44
45
46/**
47 * @name MMIO register offsets.
48 * In accordance with the Intel spec.
49 * @{
50 */
51#define VTD_MMIO_OFF_VER_REG 0x000 /**< Version. */
52#define VTD_MMIO_OFF_CAP_REG 0x008 /**< Capability. */
53#define VTD_MMIO_OFF_ECAP_REG 0x010 /**< Extended Capability. */
54#define VTD_MMIO_OFF_GCMD_REG 0x018 /**< Global Command. */
55#define VTD_MMIO_OFF_GSTS_REG 0x01c /**< Global Status. */
56#define VTD_MMIO_OFF_RTADDR_REG 0x020 /**< Root Table Address. */
57#define VTD_MMIO_OFF_CCMD_REG 0x028 /**< Context Command. */
58
59#define VTD_MMIO_OFF_FSTS_REG 0x034 /**< Fault Status.*/
60#define VTD_MMIO_OFF_FECTL_REG 0x038 /**< Fault Event Control.*/
61#define VTD_MMIO_OFF_FEDATA_REG 0x03c /**< Fault Event Data. */
62#define VTD_MMIO_OFF_FEADDR_REG 0x040 /**< Fault Event Address. */
63#define VTD_MMIO_OFF_FEUADDR_REG 0x044 /**< Fault Event Upper Address. */
64
65#define VTD_MMIO_OFF_AFLOG_REG 0x058 /**< Advance Fault Log. */
66
67#define VTD_MMIO_OFF_PMEN_REG 0x064 /**< Protected Memory Enable (PMEN). */
68#define VTD_MMIO_OFF_PLMBASE_REG 0x068 /**< Protected Low Memory Base. */
69#define VTD_MMIO_OFF_PLMLIMIT_REG 0x06c /**< Protected Low Memory Limit. */
70#define VTD_MMIO_OFF_PHMBASE_REG 0x070 /**< Protected High Memory Base. */
71#define VTD_MMIO_OFF_PHMLIMIT_REG 0x078 /**< Protected High Memory Limit. */
72
73#define VTD_MMIO_OFF_IQH_REG 0x080 /**< Invalidation Queue Head. */
74#define VTD_MMIO_OFF_IQT_REG 0x088 /**< Invalidation Queue Tail. */
75#define VTD_MMIO_OFF_IQA_REG 0x090 /**< Invalidation Queue Address. */
76#define VTD_MMIO_OFF_ICS_REG 0x09c /**< Invalidation Completion Status. */
77#define VTD_MMIO_OFF_IECTL_REG 0x0a0 /**< Invalidation Completion Event Control. */
78#define VTD_MMIO_OFF_IEDATA_REG 0x0a4 /**< Invalidation Completion Event Data. */
79#define VTD_MMIO_OFF_IEADDR_REG 0x0a8 /**< Invalidation Completion Event Address. */
80#define VTD_MMIO_OFF_IEUADDR_REG 0x0ac /**< Invalidation Completion Event Upper Address. */
81#define VTD_MMIO_OFF_IQERCD_REG 0x0b0 /**< Invalidation Queue Error Record. */
82
83#define VTD_MMIO_OFF_IRTA_REG 0x0b8 /**< Interrupt Remapping Table Address. */
84
85#define VTD_MMIO_OFF_PQH_REG 0x0c0 /**< Page Request Queue Head. */
86#define VTD_MMIO_OFF_PQT_REG 0x0c8 /**< Page Request Queue Tail. */
87#define VTD_MMIO_OFF_PQA_REG 0x0d0 /**< Page Request Queue Address. */
88#define VTD_MMIO_OFF_PRS_REG 0x0dc /**< Page Request Status. */
89#define VTD_MMIO_OFF_PECTL_REG 0x0e0 /**< Page Request Event Control. */
90#define VTD_MMIO_OFF_PEDATA_REG 0x0e4 /**< Page Request Event Data. */
91#define VTD_MMIO_OFF_PEADDR_REG 0x0e8 /**< Page Request Event Address. */
92#define VTD_MMIO_OFF_PEUADDR_REG 0x0ec /**< Page Request Event Upper Address. */
93
94#define VTD_MMIO_OFF_MTRRCAP_REG 0x100 /**< MTRR Capabliity. */
95#define VTD_MMIO_OFF_MTRRDEF_REG 0x108 /**< MTRR Default Type. */
96
97#define VTD_MMIO_OFF_MTRR_FIX64_00000_REG 0x120 /**< Fixed-range MTRR Register for 64K at 00000. */
98#define VTD_MMIO_OFF_MTRR_FIX16K_80000_REG 0x128 /**< Fixed-range MTRR Register for 16K at 80000. */
99#define VTD_MMIO_OFF_MTRR_FIX16K_A0000_REG 0x130 /**< Fixed-range MTRR Register for 16K at a0000. */
100#define VTD_MMIO_OFF_MTRR_FIX4K_C0000_REG 0x138 /**< Fixed-range MTRR Register for 4K at c0000. */
101#define VTD_MMIO_OFF_MTRR_FIX4K_C8000_REG 0x140 /**< Fixed-range MTRR Register for 4K at c8000. */
102#define VTD_MMIO_OFF_MTRR_FIX4K_D0000_REG 0x148 /**< Fixed-range MTRR Register for 4K at d0000. */
103#define VTD_MMIO_OFF_MTRR_FIX4K_D8000_REG 0x150 /**< Fixed-range MTRR Register for 4K at d8000. */
104#define VTD_MMIO_OFF_MTRR_FIX4K_E0000_REG 0x158 /**< Fixed-range MTRR Register for 4K at e0000. */
105#define VTD_MMIO_OFF_MTRR_FIX4K_E8000_REG 0x160 /**< Fixed-range MTRR Register for 4K at e8000. */
106#define VTD_MMIO_OFF_MTRR_FIX4K_F0000_REG 0x168 /**< Fixed-range MTRR Register for 4K at f0000. */
107#define VTD_MMIO_OFF_MTRR_FIX4K_F8000_REG 0x170 /**< Fixed-range MTRR Register for 4K at f8000. */
108
109#define VTD_MMIO_OFF_MTRR_PHYSBASE0_REG 0x180 /**< Variable-range MTRR Base 0. */
110#define VTD_MMIO_OFF_MTRR_PHYSMASK0_REG 0x188 /**< Variable-range MTRR Mask 0. */
111#define VTD_MMIO_OFF_MTRR_PHYSBASE1_REG 0x190 /**< Variable-range MTRR Base 1. */
112#define VTD_MMIO_OFF_MTRR_PHYSMASK1_REG 0x198 /**< Variable-range MTRR Mask 1. */
113#define VTD_MMIO_OFF_MTRR_PHYSBASE2_REG 0x1a0 /**< Variable-range MTRR Base 2. */
114#define VTD_MMIO_OFF_MTRR_PHYSMASK2_REG 0x1a8 /**< Variable-range MTRR Mask 2. */
115#define VTD_MMIO_OFF_MTRR_PHYSBASE3_REG 0x1b0 /**< Variable-range MTRR Base 3. */
116#define VTD_MMIO_OFF_MTRR_PHYSMASK3_REG 0x1b8 /**< Variable-range MTRR Mask 3. */
117#define VTD_MMIO_OFF_MTRR_PHYSBASE4_REG 0x1c0 /**< Variable-range MTRR Base 4. */
118#define VTD_MMIO_OFF_MTRR_PHYSMASK4_REG 0x1c8 /**< Variable-range MTRR Mask 4. */
119#define VTD_MMIO_OFF_MTRR_PHYSBASE5_REG 0x1d0 /**< Variable-range MTRR Base 5. */
120#define VTD_MMIO_OFF_MTRR_PHYSMASK5_REG 0x1d8 /**< Variable-range MTRR Mask 5. */
121#define VTD_MMIO_OFF_MTRR_PHYSBASE6_REG 0x1e0 /**< Variable-range MTRR Base 6. */
122#define VTD_MMIO_OFF_MTRR_PHYSMASK6_REG 0x1e8 /**< Variable-range MTRR Mask 6. */
123#define VTD_MMIO_OFF_MTRR_PHYSBASE7_REG 0x1f0 /**< Variable-range MTRR Base 7. */
124#define VTD_MMIO_OFF_MTRR_PHYSMASK7_REG 0x1f8 /**< Variable-range MTRR Mask 7. */
125#define VTD_MMIO_OFF_MTRR_PHYSBASE8_REG 0x200 /**< Variable-range MTRR Base 8. */
126#define VTD_MMIO_OFF_MTRR_PHYSMASK8_REG 0x208 /**< Variable-range MTRR Mask 8. */
127#define VTD_MMIO_OFF_MTRR_PHYSBASE9_REG 0x210 /**< Variable-range MTRR Base 9. */
128#define VTD_MMIO_OFF_MTRR_PHYSMASK9_REG 0x218 /**< Variable-range MTRR Mask 9. */
129
130#define VTD_MMIO_OFF_VCCAP_REG 0xe00 /**< Virtual Command Capability. */
131#define VTD_MMIO_OFF_VCMD_REG 0xe10 /**< Virtual Command. */
132#define VTD_MMIO_OFF_VCMDRSVD_REG 0xe18 /**< Reserved for future for Virtual Command. */
133#define VTD_MMIO_OFF_VCRSP_REG 0xe20 /**< Virtual Command Response. */
134#define VTD_MMIO_OFF_VCRSPRSVD_REG 0xe28 /**< Reserved for future for Virtual Command Response. */
135/** @} */
136
137
138/** @name Root Entry.
139 * In accordance with the Intel spec.
140 * @{ */
141/** P: Present. */
142#define VTD_BF_0_ROOT_ENTRY_P_SHIFT 0
143#define VTD_BF_0_ROOT_ENTRY_P_MASK UINT64_C(0x0000000000000001)
144/** R: Reserved (bits 11:1). */
145#define VTD_BF_0_ROOT_ENTRY_RSVD_11_1_SHIFT 1
146#define VTD_BF_0_ROOT_ENTRY_RSVD_11_1_MASK UINT64_C(0x0000000000000ffe)
147/** CTP: Context-Table Pointer. */
148#define VTD_BF_0_ROOT_ENTRY_CTP_SHIFT 12
149#define VTD_BF_0_ROOT_ENTRY_CTP_MASK UINT64_C(0xfffffffffffff000)
150RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_ROOT_ENTRY_, UINT64_C(0), UINT64_MAX,
151 (P, RSVD_11_1, CTP));
152
153/** Root Entry. */
154typedef struct VTD_ROOT_ENTRY_T
155{
156 /** The qwords in the root entry. */
157 uint64_t au64[2];
158} VTD_ROOT_ENTRY_T;
159/** Pointer to a root entry. */
160typedef VTD_ROOT_ENTRY_T *PVTD_ROOT_ENTRY_T;
161/** Pointer to a const root entry. */
162typedef VTD_ROOT_ENTRY_T const *PCVTD_ROOT_ENTRY_T;
163
164/* Root Entry: Qword 0 valid mask. */
165#define VTD_ROOT_ENTRY_0_VALID_MASK (VTD_BF_0_ROOT_ENTRY_P_MASK | VTD_BF_0_ROOT_ENTRY_CTP_MASK)
166/* Root Entry: Qword 1 valid mask. */
167#define VTD_ROOT_ENTRY_1_VALID_MASK UINT64_C(0)
168/** @} */
169
170
171/** @name Scalable-mode Root Entry.
172 * In accordance with the Intel spec.
173 * @{ */
174/** LP: Lower Present. */
175#define VTD_BF_0_SM_ROOT_ENTRY_LP_SHIFT 0
176#define VTD_BF_0_SM_ROOT_ENTRY_LP_MASK UINT64_C(0x0000000000000001)
177/** R: Reserved (bits 11:1). */
178#define VTD_BF_0_SM_ROOT_ENTRY_RSVD_11_1_SHIFT 1
179#define VTD_BF_0_SM_ROOT_ENTRY_RSVD_11_1_MASK UINT64_C(0x0000000000000ffe)
180/** LCTP: Lower Context-Table Pointer */
181#define VTD_BF_0_SM_ROOT_ENTRY_LCTP_SHIFT 12
182#define VTD_BF_0_SM_ROOT_ENTRY_LCTP_MASK UINT64_C(0xfffffffffffff000)
183RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_SM_ROOT_ENTRY_, UINT64_C(0), UINT64_MAX,
184 (LP, RSVD_11_1, LCTP));
185
186/** UP: Upper Present. */
187#define VTD_BF_1_SM_ROOT_ENTRY_UP_SHIFT 0
188#define VTD_BF_1_SM_ROOT_ENTRY_UP_MASK UINT64_C(0x0000000000000001)
189/** R: Reserved (bits 11:1). */
190#define VTD_BF_1_SM_ROOT_ENTRY_RSVD_11_1_SHIFT 1
191#define VTD_BF_1_SM_ROOT_ENTRY_RSVD_11_1_MASK UINT64_C(0x0000000000000ffe)
192/** UCTP: Upper Context-Table Pointer. */
193#define VTD_BF_1_SM_ROOT_ENTRY_UCTP_SHIFT 12
194#define VTD_BF_1_SM_ROOT_ENTRY_UCTP_MASK UINT64_C(0xfffffffffffff000)
195RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_SM_ROOT_ENTRY_, UINT64_C(0), UINT64_MAX,
196 (UP, RSVD_11_1, UCTP));
197
198/** Scalable-mode root entry. */
199typedef struct VTD_SM_ROOT_ENTRY_T
200{
201 /** The lower scalable-mode root entry. */
202 uint64_t uLower;
203 /** The upper scalable-mode root entry. */
204 uint64_t uUpper;
205} VTD_SM_ROOT_ENTRY_T;
206/** Pointer to a scalable-mode root entry. */
207typedef VTD_SM_ROOT_ENTRY_T *PVTD_SM_ROOT_ENTRY_T;
208/** Pointer to a const scalable-mode root entry. */
209typedef VTD_SM_ROOT_ENTRY_T const *PCVTD_SM_ROOT_ENTRY_T;
210/** @} */
211
212
213/** @name Context Entry.
214 * In accordance with the Intel spec.
215 * @{ */
216/** P: Present. */
217#define VTD_BF_0_CONTEXT_ENTRY_P_SHIFT 0
218#define VTD_BF_0_CONTEXT_ENTRY_P_MASK UINT64_C(0x0000000000000001)
219/** FPD: Fault Processing Disable. */
220#define VTD_BF_0_CONTEXT_ENTRY_FPD_SHIFT 1
221#define VTD_BF_0_CONTEXT_ENTRY_FPD_MASK UINT64_C(0x0000000000000002)
222/** TT: Translation Type. */
223#define VTD_BF_0_CONTEXT_ENTRY_TT_SHIFT 2
224#define VTD_BF_0_CONTEXT_ENTRY_TT_MASK UINT64_C(0x000000000000000c)
225/** R: Reserved (bits 11:4). */
226#define VTD_BF_0_CONTEXT_ENTRY_RSVD_11_4_SHIFT 4
227#define VTD_BF_0_CONTEXT_ENTRY_RSVD_11_4_MASK UINT64_C(0x0000000000000ff0)
228/** SLPTPTR: Second Level Page Translation Pointer. */
229#define VTD_BF_0_CONTEXT_ENTRY_SLPTPTR_SHIFT 12
230#define VTD_BF_0_CONTEXT_ENTRY_SLPTPTR_MASK UINT64_C(0xfffffffffffff000)
231RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_CONTEXT_ENTRY_, UINT64_C(0), UINT64_MAX,
232 (P, FPD, TT, RSVD_11_4, SLPTPTR));
233
234/** AW: Address Width. */
235#define VTD_BF_1_CONTEXT_ENTRY_AW_SHIFT 0
236#define VTD_BF_1_CONTEXT_ENTRY_AW_MASK UINT64_C(0x0000000000000007)
237/** IGN: Ignored (bits 6:3). */
238#define VTD_BF_1_CONTEXT_ENTRY_IGN_6_3_SHIFT 3
239#define VTD_BF_1_CONTEXT_ENTRY_IGN_6_3_MASK UINT64_C(0x0000000000000078)
240/** R: Reserved (bit 7). */
241#define VTD_BF_1_CONTEXT_ENTRY_RSVD_7_SHIFT 7
242#define VTD_BF_1_CONTEXT_ENTRY_RSVD_7_MASK UINT64_C(0x0000000000000080)
243/** DID: Domain Identifier. */
244#define VTD_BF_1_CONTEXT_ENTRY_DID_SHIFT 8
245#define VTD_BF_1_CONTEXT_ENTRY_DID_MASK UINT64_C(0x0000000000ffff00)
246/** R: Reserved (bits 63:24). */
247#define VTD_BF_1_CONTEXT_ENTRY_RSVD_63_24_SHIFT 24
248#define VTD_BF_1_CONTEXT_ENTRY_RSVD_63_24_MASK UINT64_C(0xffffffffff000000)
249RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_CONTEXT_ENTRY_, UINT64_C(0), UINT64_MAX,
250 (AW, IGN_6_3, RSVD_7, DID, RSVD_63_24));
251
252/** Context Entry. */
253typedef struct VTD_CONTEXT_ENTRY_T
254{
255 /** The qwords in the context entry. */
256 uint64_t au64[2];
257} VTD_CONTEXT_ENTRY_T;
258/** Pointer to a context entry. */
259typedef VTD_CONTEXT_ENTRY_T *PVTD_CONTEXT_ENTRY_T;
260/** Pointer to a const context entry. */
261typedef VTD_CONTEXT_ENTRY_T const *PCVTD_CONTEXT_ENTRY_T;
262AssertCompileSize(VTD_CONTEXT_ENTRY_T, 16);
263
264/** Context Entry: Qword 0 valid mask. */
265#define VTD_CONTEXT_ENTRY_0_VALID_MASK ( VTD_BF_0_CONTEXT_ENTRY_P_MASK \
266 | VTD_BF_0_CONTEXT_ENTRY_FPD_MASK \
267 | VTD_BF_0_CONTEXT_ENTRY_TT_MASK \
268 | VTD_BF_0_CONTEXT_ENTRY_SLPTPTR_MASK)
269/** Context Entry: Qword 1 valid mask. */
270#define VTD_CONTEXT_ENTRY_1_VALID_MASK ( VTD_BF_1_CONTEXT_ENTRY_AW_MASK \
271 | VTD_BF_1_CONTEXT_ENTRY_IGN_6_3_MASK \
272 | VTD_BF_1_CONTEXT_ENTRY_DID_MASK)
273
274/** Translation Type: Untranslated requests uses second-level paging. */
275#define VTD_TT_UNTRANSLATED_SLP 0
276/** Translation Type: Untranslated requests requires device-TLB support. */
277#define VTD_TT_UNTRANSLATED_DEV_TLB 1
278/** Translation Type: Untranslated requests are pass-through. */
279#define VTD_TT_UNTRANSLATED_PT 2
280/** Translation Type: Reserved. */
281#define VTD_TT_RSVD 3
282/** @} */
283
284
285/** @name Scalable-mode Context Entry.
286 * In accordance with the Intel spec.
287 * @{ */
288/** P: Present. */
289#define VTD_BF_0_SM_CONTEXT_ENTRY_P_SHIFT 0
290#define VTD_BF_0_SM_CONTEXT_ENTRY_P_MASK UINT64_C(0x0000000000000001)
291/** FPD: Fault Processing Disable. */
292#define VTD_BF_0_SM_CONTEXT_ENTRY_FPD_SHIFT 1
293#define VTD_BF_0_SM_CONTEXT_ENTRY_FPD_MASK UINT64_C(0x0000000000000002)
294/** DTE: Device-TLB Enable. */
295#define VTD_BF_0_SM_CONTEXT_ENTRY_DTE_SHIFT 2
296#define VTD_BF_0_SM_CONTEXT_ENTRY_DTE_MASK UINT64_C(0x0000000000000004)
297/** PASIDE: PASID Enable. */
298#define VTD_BF_0_SM_CONTEXT_ENTRY_PASIDE_SHIFT 3
299#define VTD_BF_0_SM_CONTEXT_ENTRY_PASIDE_MASK UINT64_C(0x0000000000000008)
300/** PRE: Page Request Enable. */
301#define VTD_BF_0_SM_CONTEXT_ENTRY_PRE_SHIFT 4
302#define VTD_BF_0_SM_CONTEXT_ENTRY_PRE_MASK UINT64_C(0x0000000000000010)
303/** R: Reserved (bits 8:5). */
304#define VTD_BF_0_SM_CONTEXT_ENTRY_RSVD_8_5_SHIFT 5
305#define VTD_BF_0_SM_CONTEXT_ENTRY_RSVD_8_5_MASK UINT64_C(0x00000000000001e0)
306/** PDTS: PASID Directory Size. */
307#define VTD_BF_0_SM_CONTEXT_ENTRY_PDTS_SHIFT 9
308#define VTD_BF_0_SM_CONTEXT_ENTRY_PDTS_MASK UINT64_C(0x0000000000000e00)
309/** PASIDDIRPTR: PASID Directory Pointer. */
310#define VTD_BF_0_SM_CONTEXT_ENTRY_PASIDDIRPTR_SHIFT 12
311#define VTD_BF_0_SM_CONTEXT_ENTRY_PASIDDIRPTR_MASK UINT64_C(0xfffffffffffff000)
312RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_SM_CONTEXT_ENTRY_, UINT64_C(0), UINT64_MAX,
313 (P, FPD, DTE, PASIDE, PRE, RSVD_8_5, PDTS, PASIDDIRPTR));
314
315/** RID_PASID: Requested Id to PASID assignment. */
316#define VTD_BF_1_SM_CONTEXT_ENTRY_RID_PASID_SHIFT 0
317#define VTD_BF_1_SM_CONTEXT_ENTRY_RID_PASID_MASK UINT64_C(0x00000000000fffff)
318/** RID_PRIV: Requested Id to PrivilegeModeRequested assignment. */
319#define VTD_BF_1_SM_CONTEXT_ENTRY_RID_PRIV_SHIFT 20
320#define VTD_BF_1_SM_CONTEXT_ENTRY_RID_PRIV_MASK UINT64_C(0x0000000000100000)
321/** R: Reserved (bits 63:21). */
322#define VTD_BF_1_SM_CONTEXT_ENTRY_RSVD_63_21_SHIFT 21
323#define VTD_BF_1_SM_CONTEXT_ENTRY_RSVD_63_21_MASK UINT64_C(0xffffffffffe00000)
324RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_SM_CONTEXT_ENTRY_, UINT64_C(0), UINT64_MAX,
325 (RID_PASID, RID_PRIV, RSVD_63_21));
326
327/** Scalable-mode Context Entry. */
328typedef struct VTD_SM_CONTEXT_ENTRY_T
329{
330 /** The qwords in the scalable-mode context entry. */
331 uint64_t au64[4];
332} VTD_SM_CONTEXT_ENTRY_T;
333/** Pointer to a scalable-mode context entry. */
334typedef VTD_SM_CONTEXT_ENTRY_T *PVTD_SM_CONTEXT_ENTRY_T;
335/** Pointer to a const scalable-mode context entry. */
336typedef VTD_SM_CONTEXT_ENTRY_T const *PCVTD_SM_CONTEXT_ENTRY_T;
337/** @} */
338
339
340/** @name Scalable-mode PASID Directory Entry.
341 * In accordance with the Intel spec.
342 * @{ */
343/** P: Present. */
344#define VTD_BF_SM_PASID_DIR_ENTRY_P_SHIFT 0
345#define VTD_BF_SM_PASID_DIR_ENTRY_P_MASK UINT64_C(0x0000000000000001)
346/** FPD: Fault Processing Disable. */
347#define VTD_BF_SM_PASID_DIR_ENTRY_FPD_SHIFT 1
348#define VTD_BF_SM_PASID_DIR_ENTRY_FPD_MASK UINT64_C(0x0000000000000002)
349/** R: Reserved (bits 11:2). */
350#define VTD_BF_SM_PASID_DIR_ENTRY_RSVD_11_2_SHIFT 2
351#define VTD_BF_SM_PASID_DIR_ENTRY_RSVD_11_2_MASK UINT64_C(0x0000000000000ffc)
352/** SMPTBLPTR: Scalable Mode PASID Table Pointer. */
353#define VTD_BF_SM_PASID_DIR_ENTRY_SMPTBLPTR_SHIFT 12
354#define VTD_BF_SM_PASID_DIR_ENTRY_SMPTBLPTR_MASK UINT64_C(0xfffffffffffff000)
355RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_SM_PASID_DIR_ENTRY_, UINT64_C(0), UINT64_MAX,
356 (P, FPD, RSVD_11_2, SMPTBLPTR));
357
358/** Scalable-mode PASID Directory Entry. */
359typedef struct VTD_SM_PASID_DIR_ENTRY_T
360{
361 /** The scalable-mode PASID directory entry. */
362 uint64_t u;
363} VTD_SM_PASID_DIR_ENTRY_T;
364/** Pointer to a scalable-mode PASID directory entry. */
365typedef VTD_SM_PASID_DIR_ENTRY_T *PVTD_SM_PASID_DIR_ENTRY_T;
366/** Pointer to a const scalable-mode PASID directory entry. */
367typedef VTD_SM_PASID_DIR_ENTRY_T const *PCVTD_SM_PASID_DIR_ENTRY_T;
368/** @} */
369
370
371/** @name Scalable-mode PASID Table Entry.
372 * In accordance with the Intel spec.
373 * @{ */
374/** P: Present. */
375#define VTD_BF_0_SM_PASID_TBL_ENTRY_P_SHIFT 0
376#define VTD_BF_0_SM_PASID_TBL_ENTRY_P_MASK UINT64_C(0x0000000000000001)
377/** FPD: Fault Processing Disable. */
378#define VTD_BF_0_SM_PASID_TBL_ENTRY_FPD_SHIFT 1
379#define VTD_BF_0_SM_PASID_TBL_ENTRY_FPD_MASK UINT64_C(0x0000000000000002)
380/** AW: Address Width. */
381#define VTD_BF_0_SM_PASID_TBL_ENTRY_AW_SHIFT 2
382#define VTD_BF_0_SM_PASID_TBL_ENTRY_AW_MASK UINT64_C(0x000000000000001c)
383/** SLEE: Second-Level Execute Enable. */
384#define VTD_BF_0_SM_PASID_TBL_ENTRY_SLEE_SHIFT 5
385#define VTD_BF_0_SM_PASID_TBL_ENTRY_SLEE_MASK UINT64_C(0x0000000000000020)
386/** PGTT: PASID Granular Translation Type. */
387#define VTD_BF_0_SM_PASID_TBL_ENTRY_PGTT_SHIFT 6
388#define VTD_BF_0_SM_PASID_TBL_ENTRY_PGTT_MASK UINT64_C(0x00000000000001c0)
389/** SLADE: Second-Level Address/Dirty Enable. */
390#define VTD_BF_0_SM_PASID_TBL_ENTRY_SLADE_SHIFT 9
391#define VTD_BF_0_SM_PASID_TBL_ENTRY_SLADE_MASK UINT64_C(0x0000000000000200)
392/** R: Reserved (bits 11:10). */
393#define VTD_BF_0_SM_PASID_TBL_ENTRY_RSVD_11_10_SHIFT 10
394#define VTD_BF_0_SM_PASID_TBL_ENTRY_RSVD_11_10_MASK UINT64_C(0x0000000000000c00)
395/** SLPTPTR: Second-Level Page Table Pointer. */
396#define VTD_BF_0_SM_PASID_TBL_ENTRY_SLPTPTR_SHIFT 12
397#define VTD_BF_0_SM_PASID_TBL_ENTRY_SLPTPTR_MASK UINT64_C(0xfffffffffffff000)
398RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_SM_PASID_TBL_ENTRY_, UINT64_C(0), UINT64_MAX,
399 (P, FPD, AW, SLEE, PGTT, SLADE, RSVD_11_10, SLPTPTR));
400
401/** DID: Domain Identifer. */
402#define VTD_BF_1_SM_PASID_TBL_ENTRY_DID_SHIFT 0
403#define VTD_BF_1_SM_PASID_TBL_ENTRY_DID_MASK UINT64_C(0x000000000000ffff)
404/** R: Reserved (bits 22:16). */
405#define VTD_BF_1_SM_PASID_TBL_ENTRY_RSVD_22_16_SHIFT 16
406#define VTD_BF_1_SM_PASID_TBL_ENTRY_RSVD_22_16_MASK UINT64_C(0x00000000007f0000)
407/** PWSNP: Page-Walk Snoop. */
408#define VTD_BF_1_SM_PASID_TBL_ENTRY_PWSNP_SHIFT 23
409#define VTD_BF_1_SM_PASID_TBL_ENTRY_PWSNP_MASK UINT64_C(0x0000000000800000)
410/** PGSNP: Page Snoop. */
411#define VTD_BF_1_SM_PASID_TBL_ENTRY_PGSNP_SHIFT 24
412#define VTD_BF_1_SM_PASID_TBL_ENTRY_PGSNP_MASK UINT64_C(0x0000000001000000)
413/** CD: Cache Disable. */
414#define VTD_BF_1_SM_PASID_TBL_ENTRY_CD_SHIFT 25
415#define VTD_BF_1_SM_PASID_TBL_ENTRY_CD_MASK UINT64_C(0x0000000002000000)
416/** EMTE: Extended Memory Type Enable. */
417#define VTD_BF_1_SM_PASID_TBL_ENTRY_EMTE_SHIFT 26
418#define VTD_BF_1_SM_PASID_TBL_ENTRY_EMTE_MASK UINT64_C(0x0000000004000000)
419/** EMT: Extended Memory Type. */
420#define VTD_BF_1_SM_PASID_TBL_ENTRY_EMT_SHIFT 27
421#define VTD_BF_1_SM_PASID_TBL_ENTRY_EMT_MASK UINT64_C(0x0000000038000000)
422/** PWT: Page-Level Write Through. */
423#define VTD_BF_1_SM_PASID_TBL_ENTRY_PWT_SHIFT 30
424#define VTD_BF_1_SM_PASID_TBL_ENTRY_PWT_MASK UINT64_C(0x0000000040000000)
425/** PCD: Page-Level Cache Disable. */
426#define VTD_BF_1_SM_PASID_TBL_ENTRY_PCD_SHIFT 31
427#define VTD_BF_1_SM_PASID_TBL_ENTRY_PCD_MASK UINT64_C(0x0000000080000000)
428/** PAT: Page Attribute Table. */
429#define VTD_BF_1_SM_PASID_TBL_ENTRY_PAT_SHIFT 32
430#define VTD_BF_1_SM_PASID_TBL_ENTRY_PAT_MASK UINT64_C(0xffffffff00000000)
431RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_SM_PASID_TBL_ENTRY_, UINT64_C(0), UINT64_MAX,
432 (DID, RSVD_22_16, PWSNP, PGSNP, CD, EMTE, EMT, PWT, PCD, PAT));
433
434/** SRE: Supervisor Request Enable. */
435#define VTD_BF_2_SM_PASID_TBL_ENTRY_SRE_SHIFT 0
436#define VTD_BF_2_SM_PASID_TBL_ENTRY_SRE_MASK UINT64_C(0x0000000000000001)
437/** ERE: Execute Request Enable. */
438#define VTD_BF_2_SM_PASID_TBL_ENTRY_ERE_SHIFT 1
439#define VTD_BF_2_SM_PASID_TBL_ENTRY_ERE_MASK UINT64_C(0x0000000000000002)
440/** FLPM: First Level Paging Mode. */
441#define VTD_BF_2_SM_PASID_TBL_ENTRY_FLPM_SHIFT 2
442#define VTD_BF_2_SM_PASID_TBL_ENTRY_FLPM_MASK UINT64_C(0x000000000000000c)
443/** WPE: Write Protect Enable. */
444#define VTD_BF_2_SM_PASID_TBL_ENTRY_WPE_SHIFT 4
445#define VTD_BF_2_SM_PASID_TBL_ENTRY_WPE_MASK UINT64_C(0x0000000000000010)
446/** NXE: No-Execute Enable. */
447#define VTD_BF_2_SM_PASID_TBL_ENTRY_NXE_SHIFT 5
448#define VTD_BF_2_SM_PASID_TBL_ENTRY_NXE_MASK UINT64_C(0x0000000000000020)
449/** SMEP: Supervisor Mode Execute Prevent. */
450#define VTD_BF_2_SM_PASID_TBL_ENTRY_SMPE_SHIFT 6
451#define VTD_BF_2_SM_PASID_TBL_ENTRY_SMPE_MASK UINT64_C(0x0000000000000040)
452/** EAFE: Extended Accessed Flag Enable. */
453#define VTD_BF_2_SM_PASID_TBL_ENTRY_EAFE_SHIFT 7
454#define VTD_BF_2_SM_PASID_TBL_ENTRY_EAFE_MASK UINT64_C(0x0000000000000080)
455/** R: Reserved (bits 11:8). */
456#define VTD_BF_2_SM_PASID_TBL_ENTRY_RSVD_11_8_SHIFT 8
457#define VTD_BF_2_SM_PASID_TBL_ENTRY_RSVD_11_8_MASK UINT64_C(0x0000000000000f00)
458/** FLPTPTR: First Level Page Table Pointer. */
459#define VTD_BF_2_SM_PASID_TBL_ENTRY_FLPTPTR_SHIFT 12
460#define VTD_BF_2_SM_PASID_TBL_ENTRY_FLPTPTR_MASK UINT64_C(0xfffffffffffff000)
461RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_2_SM_PASID_TBL_ENTRY_, UINT64_C(0), UINT64_MAX,
462 (SRE, ERE, FLPM, WPE, NXE, SMPE, EAFE, RSVD_11_8, FLPTPTR));
463
464/** Scalable-mode PASID Table Entry. */
465typedef struct VTD_SM_PASID_TBL_ENTRY_T
466{
467 /** The qwords in the scalable-mode PASID table entry. */
468 uint64_t au64[8];
469} VTD_SM_PASID_TBL_ENTRY_T;
470/** Pointer to a scalable-mode PASID table entry. */
471typedef VTD_SM_PASID_TBL_ENTRY_T *PVTD_SM_PASID_TBL_ENTRY_T;
472/** Pointer to a const scalable-mode PASID table entry. */
473typedef VTD_SM_PASID_TBL_ENTRY_T const *PCVTD_SM_PASID_TBL_ENTRY_T;
474/** @} */
475
476
477/** @name First-Level Paging Entry.
478 * In accordance with the Intel spec.
479 * @{ */
480/** P: Present. */
481#define VTD_BF_FLP_ENTRY_P_SHIFT 0
482#define VTD_BF_FLP_ENTRY_P_MASK UINT64_C(0x0000000000000001)
483/** R/W: Read/Write. */
484#define VTD_BF_FLP_ENTRY_RW_SHIFT 1
485#define VTD_BF_FLP_ENTRY_RW_MASK UINT64_C(0x0000000000000002)
486/** U/S: User/Supervisor. */
487#define VTD_BF_FLP_ENTRY_US_SHIFT 2
488#define VTD_BF_FLP_ENTRY_US_MASK UINT64_C(0x0000000000000004)
489/** PWT: Page-Level Write Through. */
490#define VTD_BF_FLP_ENTRY_PWT_SHIFT 3
491#define VTD_BF_FLP_ENTRY_PWT_MASK UINT64_C(0x0000000000000008)
492/** PC: Page-Level Cache Disable. */
493#define VTD_BF_FLP_ENTRY_PCD_SHIFT 4
494#define VTD_BF_FLP_ENTRY_PCD_MASK UINT64_C(0x0000000000000010)
495/** A: Accessed. */
496#define VTD_BF_FLP_ENTRY_A_SHIFT 5
497#define VTD_BF_FLP_ENTRY_A_MASK UINT64_C(0x0000000000000020)
498/** IGN: Ignored (bit 6). */
499#define VTD_BF_FLP_ENTRY_IGN_6_SHIFT 6
500#define VTD_BF_FLP_ENTRY_IGN_6_MASK UINT64_C(0x0000000000000040)
501/** R: Reserved (bit 7). */
502#define VTD_BF_FLP_ENTRY_RSVD_7_SHIFT 7
503#define VTD_BF_FLP_ENTRY_RSVD_7_MASK UINT64_C(0x0000000000000080)
504/** IGN: Ignored (bits 9:8). */
505#define VTD_BF_FLP_ENTRY_IGN_9_8_SHIFT 8
506#define VTD_BF_FLP_ENTRY_IGN_9_8_MASK UINT64_C(0x0000000000000300)
507/** EA: Extended Accessed. */
508#define VTD_BF_FLP_ENTRY_EA_SHIFT 10
509#define VTD_BF_FLP_ENTRY_EA_MASK UINT64_C(0x0000000000000400)
510/** IGN: Ignored (bit 11). */
511#define VTD_BF_FLP_ENTRY_IGN_11_SHIFT 11
512#define VTD_BF_FLP_ENTRY_IGN_11_MASK UINT64_C(0x0000000000000800)
513/** ADDR: Address. */
514#define VTD_BF_FLP_ENTRY_ADDR_SHIFT 12
515#define VTD_BF_FLP_ENTRY_ADDR_MASK UINT64_C(0x000ffffffffff000)
516/** IGN: Ignored (bits 62:52). */
517#define VTD_BF_FLP_ENTRY_IGN_62_52_SHIFT 52
518#define VTD_BF_FLP_ENTRY_IGN_62_52_MASK UINT64_C(0x7ff0000000000000)
519/** XD: Execute Disabled. */
520#define VTD_BF_FLP_ENTRY_XD_SHIFT 63
521#define VTD_BF_FLP_ENTRY_XD_MASK UINT64_C(0x8000000000000000)
522RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_FLP_ENTRY_, UINT64_C(0), UINT64_MAX,
523 (P, RW, US, PWT, PCD, A, IGN_6, RSVD_7, IGN_9_8, EA, IGN_11, ADDR, IGN_62_52, XD));
524/** @} */
525
526
527/** @name Second-Level PML5E.
528 * In accordance with the Intel spec.
529 * @{ */
530/** R: Read. */
531#define VTD_BF_SL_PML5E_R_SHIFT 0
532#define VTD_BF_SL_PML5E_R_MASK UINT64_C(0x0000000000000001)
533/** W: Write. */
534#define VTD_BF_SL_PML5E_W_SHIFT 1
535#define VTD_BF_SL_PML5E_W_MASK UINT64_C(0x0000000000000002)
536/** X: Execute. */
537#define VTD_BF_SL_PML5E_X_SHIFT 2
538#define VTD_BF_SL_PML5E_X_MASK UINT64_C(0x0000000000000004)
539/** IGN: Ignored (bits 6:3). */
540#define VTD_BF_SL_PML5E_IGN_6_3_SHIFT 3
541#define VTD_BF_SL_PML5E_IGN_6_3_MASK UINT64_C(0x0000000000000078)
542/** R: Reserved (bit 7). */
543#define VTD_BF_SL_PML5E_RSVD_7_SHIFT 7
544#define VTD_BF_SL_PML5E_RSVD_7_MASK UINT64_C(0x0000000000000080)
545/** A: Accessed. */
546#define VTD_BF_SL_PML5E_A_SHIFT 8
547#define VTD_BF_SL_PML5E_A_MASK UINT64_C(0x0000000000000100)
548/** IGN: Ignored (bits 10:9). */
549#define VTD_BF_SL_PML5E_IGN_10_9_SHIFT 9
550#define VTD_BF_SL_PML5E_IGN_10_9_MASK UINT64_C(0x0000000000000600)
551/** R: Reserved (bit 11). */
552#define VTD_BF_SL_PML5E_RSVD_11_SHIFT 11
553#define VTD_BF_SL_PML5E_RSVD_11_MASK UINT64_C(0x0000000000000800)
554/** ADDR: Address. */
555#define VTD_BF_SL_PML5E_ADDR_SHIFT 12
556#define VTD_BF_SL_PML5E_ADDR_MASK UINT64_C(0x000ffffffffff000)
557/** IGN: Ignored (bits 61:52). */
558#define VTD_BF_SL_PML5E_IGN_61_52_SHIFT 52
559#define VTD_BF_SL_PML5E_IGN_61_52_MASK UINT64_C(0x3ff0000000000000)
560/** R: Reserved (bit 62). */
561#define VTD_BF_SL_PML5E_RSVD_62_SHIFT 62
562#define VTD_BF_SL_PML5E_RSVD_62_MASK UINT64_C(0x4000000000000000)
563/** IGN: Ignored (bit 63). */
564#define VTD_BF_SL_PML5E_IGN_63_SHIFT 63
565#define VTD_BF_SL_PML5E_IGN_63_MASK UINT64_C(0x8000000000000000)
566RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_SL_PML5E_, UINT64_C(0), UINT64_MAX,
567 (R, W, X, IGN_6_3, RSVD_7, A, IGN_10_9, RSVD_11, ADDR, IGN_61_52, RSVD_62, IGN_63));
568
569/** Second-level PML5E valid mask. */
570#define VTD_SL_PML5E_VALID_MASK ( VTD_BF_SL_PML5E_R_MASK | VTD_BF_SL_PML5E_W_MASK \
571 | VTD_BF_SL_PML5E_X_MASK | VTD_BF_SL_PML5E_IGN_6_3_MASK \
572 | VTD_BF_SL_PML5E_A_MASK | VTD_BF_SL_PML5E_IGN_10_9_MASK \
573 | VTD_BF_SL_PML5E_ADDR_MASK | VTD_BF_SL_PML5E_IGN_61_52_MASK \
574 | VTD_BF_SL_PML5E_IGN_63_MASK)
575/** @} */
576
577
578/** @name Second-Level PML4E.
579 * In accordance with the Intel spec.
580 * @{ */
581/** R: Read. */
582#define VTD_BF_SL_PML4E_R_SHIFT 0
583#define VTD_BF_SL_PML4E_R_MASK UINT64_C(0x0000000000000001)
584/** W: Write. */
585#define VTD_BF_SL_PML4E_W_SHIFT 1
586#define VTD_BF_SL_PML4E_W_MASK UINT64_C(0x0000000000000002)
587/** X: Execute. */
588#define VTD_BF_SL_PML4E_X_SHIFT 2
589#define VTD_BF_SL_PML4E_X_MASK UINT64_C(0x0000000000000004)
590/** IGN: Ignored (bits 6:3). */
591#define VTD_BF_SL_PML4E_IGN_6_3_SHIFT 3
592#define VTD_BF_SL_PML4E_IGN_6_3_MASK UINT64_C(0x0000000000000078)
593/** R: Reserved (bit 7). */
594#define VTD_BF_SL_PML4E_RSVD_7_SHIFT 7
595#define VTD_BF_SL_PML4E_RSVD_7_MASK UINT64_C(0x0000000000000080)
596/** A: Accessed. */
597#define VTD_BF_SL_PML4E_A_SHIFT 8
598#define VTD_BF_SL_PML4E_A_MASK UINT64_C(0x0000000000000100)
599/** IGN: Ignored (bits 10:9). */
600#define VTD_BF_SL_PML4E_IGN_10_9_SHIFT 9
601#define VTD_BF_SL_PML4E_IGN_10_9_MASK UINT64_C(0x0000000000000600)
602/** R: Reserved (bit 11). */
603#define VTD_BF_SL_PML4E_RSVD_11_SHIFT 11
604#define VTD_BF_SL_PML4E_RSVD_11_MASK UINT64_C(0x0000000000000800)
605/** ADDR: Address. */
606#define VTD_BF_SL_PML4E_ADDR_SHIFT 12
607#define VTD_BF_SL_PML4E_ADDR_MASK UINT64_C(0x000ffffffffff000)
608/** IGN: Ignored (bits 61:52). */
609#define VTD_BF_SL_PML4E_IGN_61_52_SHIFT 52
610#define VTD_BF_SL_PML4E_IGN_61_52_MASK UINT64_C(0x3ff0000000000000)
611/** R: Reserved (bit 62). */
612#define VTD_BF_SL_PML4E_RSVD_62_SHIFT 62
613#define VTD_BF_SL_PML4E_RSVD_62_MASK UINT64_C(0x4000000000000000)
614/** IGN: Ignored (bit 63). */
615#define VTD_BF_SL_PML4E_IGN_63_SHIFT 63
616#define VTD_BF_SL_PML4E_IGN_63_MASK UINT64_C(0x8000000000000000)
617RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_SL_PML4E_, UINT64_C(0), UINT64_MAX,
618 (R, W, X, IGN_6_3, RSVD_7, A, IGN_10_9, RSVD_11, ADDR, IGN_61_52, RSVD_62, IGN_63));
619
620/** Second-level PML4E valid mask. */
621#define VTD_SL_PML4E_VALID_MASK VTD_SL_PML5E_VALID_MASK
622/** @} */
623
624
625/** @name Second-Level PDPE (1GB Page).
626 * In accordance with the Intel spec.
627 * @{ */
628/** R: Read. */
629#define VTD_BF_SL_PDPE1G_R_SHIFT 0
630#define VTD_BF_SL_PDPE1G_R_MASK UINT64_C(0x0000000000000001)
631/** W: Write. */
632#define VTD_BF_SL_PDPE1G_W_SHIFT 1
633#define VTD_BF_SL_PDPE1G_W_MASK UINT64_C(0x0000000000000002)
634/** X: Execute. */
635#define VTD_BF_SL_PDPE1G_X_SHIFT 2
636#define VTD_BF_SL_PDPE1G_X_MASK UINT64_C(0x0000000000000004)
637/** EMT: Extended Memory Type. */
638#define VTD_BF_SL_PDPE1G_EMT_SHIFT 3
639#define VTD_BF_SL_PDPE1G_EMT_MASK UINT64_C(0x0000000000000038)
640/** IPAT: Ignore PAT (Page Attribute Table). */
641#define VTD_BF_SL_PDPE1G_IPAT_SHIFT 6
642#define VTD_BF_SL_PDPE1G_IPAT_MASK UINT64_C(0x0000000000000040)
643/** PS: Page Size (MB1). */
644#define VTD_BF_SL_PDPE1G_PS_SHIFT 7
645#define VTD_BF_SL_PDPE1G_PS_MASK UINT64_C(0x0000000000000080)
646/** A: Accessed. */
647#define VTD_BF_SL_PDPE1G_A_SHIFT 8
648#define VTD_BF_SL_PDPE1G_A_MASK UINT64_C(0x0000000000000100)
649/** D: Dirty. */
650#define VTD_BF_SL_PDPE1G_D_SHIFT 9
651#define VTD_BF_SL_PDPE1G_D_MASK UINT64_C(0x0000000000000200)
652/** IGN: Ignored (bit 10). */
653#define VTD_BF_SL_PDPE1G_IGN_10_SHIFT 10
654#define VTD_BF_SL_PDPE1G_IGN_10_MASK UINT64_C(0x0000000000000400)
655/** R: Reserved (bit 11). */
656#define VTD_BF_SL_PDPE1G_RSVD_11_SHIFT 11
657#define VTD_BF_SL_PDPE1G_RSVD_11_MASK UINT64_C(0x0000000000000800)
658/** R: Reserved (bits 29:12). */
659#define VTD_BF_SL_PDPE1G_RSVD_29_12_SHIFT 12
660#define VTD_BF_SL_PDPE1G_RSVD_29_12_MASK UINT64_C(0x000000003ffff000)
661/** ADDR: Address of 1GB page. */
662#define VTD_BF_SL_PDPE1G_ADDR_SHIFT 30
663#define VTD_BF_SL_PDPE1G_ADDR_MASK UINT64_C(0x000fffffc0000000)
664/** IGN: Ignored (bits 61:52). */
665#define VTD_BF_SL_PDPE1G_IGN_61_52_SHIFT 52
666#define VTD_BF_SL_PDPE1G_IGN_61_52_MASK UINT64_C(0x3ff0000000000000)
667/** R: Reserved (bit 62). */
668#define VTD_BF_SL_PDPE1G_RSVD_62_SHIFT 62
669#define VTD_BF_SL_PDPE1G_RSVD_62_MASK UINT64_C(0x4000000000000000)
670/** IGN: Ignored (bit 63). */
671#define VTD_BF_SL_PDPE1G_IGN_63_SHIFT 63
672#define VTD_BF_SL_PDPE1G_IGN_63_MASK UINT64_C(0x8000000000000000)
673RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_SL_PDPE1G_, UINT64_C(0), UINT64_MAX,
674 (R, W, X, EMT, IPAT, PS, A, D, IGN_10, RSVD_11, RSVD_29_12, ADDR, IGN_61_52, RSVD_62, IGN_63));
675
676/** Second-level PDPE (1GB Page) valid mask. */
677#define VTD_SL_PDPE1G_VALID_MASK ( VTD_BF_SL_PDPE1G_R_MASK | VTD_BF_SL_PDPE1G_W_MASK \
678 | VTD_BF_SL_PDPE1G_X_MASK | VTD_BF_SL_PDPE1G_EMT_MASK \
679 | VTD_BF_SL_PDPE1G_IPAT_MASK | VTD_BF_SL_PDPE1G_PS_MASK \
680 | VTD_BF_SL_PDPE1G_A_MASK | VTD_BF_SL_PDPE1G_D_MASK \
681 | VTD_BF_SL_PDPE1G_IGN_10_MASK | VTD_BF_SL_PDPE1G_ADDR_MASK \
682 | VTD_BF_SL_PDPE1G_IGN_61_52_MASK | VTD_BF_SL_PDPE1G_IGN_63_MASK)
683/** @} */
684
685
686/** @name Second-Level PDPE.
687 * In accordance with the Intel spec.
688 * @{ */
689/** R: Read. */
690#define VTD_BF_SL_PDPE_R_SHIFT 0
691#define VTD_BF_SL_PDPE_R_MASK UINT64_C(0x0000000000000001)
692/** W: Write. */
693#define VTD_BF_SL_PDPE_W_SHIFT 1
694#define VTD_BF_SL_PDPE_W_MASK UINT64_C(0x0000000000000002)
695/** X: Execute. */
696#define VTD_BF_SL_PDPE_X_SHIFT 2
697#define VTD_BF_SL_PDPE_X_MASK UINT64_C(0x0000000000000004)
698/** IGN: Ignored (bits 6:3). */
699#define VTD_BF_SL_PDPE_IGN_6_3_SHIFT 3
700#define VTD_BF_SL_PDPE_IGN_6_3_MASK UINT64_C(0x0000000000000078)
701/** PS: Page Size (MBZ). */
702#define VTD_BF_SL_PDPE_PS_SHIFT 7
703#define VTD_BF_SL_PDPE_PS_MASK UINT64_C(0x0000000000000080)
704/** A: Accessed. */
705#define VTD_BF_SL_PDPE_A_SHIFT 8
706#define VTD_BF_SL_PDPE_A_MASK UINT64_C(0x0000000000000100)
707/** IGN: Ignored (bits 10:9). */
708#define VTD_BF_SL_PDPE_IGN_10_9_SHIFT 9
709#define VTD_BF_SL_PDPE_IGN_10_9_MASK UINT64_C(0x0000000000000600)
710/** R: Reserved (bit 11). */
711#define VTD_BF_SL_PDPE_RSVD_11_SHIFT 11
712#define VTD_BF_SL_PDPE_RSVD_11_MASK UINT64_C(0x0000000000000800)
713/** ADDR: Address of second-level PDT. */
714#define VTD_BF_SL_PDPE_ADDR_SHIFT 12
715#define VTD_BF_SL_PDPE_ADDR_MASK UINT64_C(0x000ffffffffff000)
716/** IGN: Ignored (bits 61:52). */
717#define VTD_BF_SL_PDPE_IGN_61_52_SHIFT 52
718#define VTD_BF_SL_PDPE_IGN_61_52_MASK UINT64_C(0x3ff0000000000000)
719/** R: Reserved (bit 62). */
720#define VTD_BF_SL_PDPE_RSVD_62_SHIFT 62
721#define VTD_BF_SL_PDPE_RSVD_62_MASK UINT64_C(0x4000000000000000)
722/** IGN: Ignored (bit 63). */
723#define VTD_BF_SL_PDPE_IGN_63_SHIFT 63
724#define VTD_BF_SL_PDPE_IGN_63_MASK UINT64_C(0x8000000000000000)
725RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_SL_PDPE_, UINT64_C(0), UINT64_MAX,
726 (R, W, X, IGN_6_3, PS, A, IGN_10_9, RSVD_11, ADDR, IGN_61_52, RSVD_62, IGN_63));
727
728/** Second-level PDPE valid mask. */
729#define VTD_SL_PDPE_VALID_MASK ( VTD_BF_SL_PDPE_R_MASK | VTD_BF_SL_PDPE_W_MASK \
730 | VTD_BF_SL_PDPE_X_MASK | VTD_BF_SL_PDPE_IGN_6_3_MASK \
731 | VTD_BF_SL_PDPE_PS_MASK | VTD_BF_SL_PDPE_A_MASK \
732 | VTD_BF_SL_PDPE_IGN_10_9_MASK | VTD_BF_SL_PDPE_ADDR_MASK \
733 | VTD_BF_SL_PDPE_IGN_61_52_MASK | VTD_BF_SL_PDPE_IGN_63_MASK)
734/** @} */
735
736
737/** @name Second-Level PDE (2MB Page).
738 * In accordance with the Intel spec.
739 * @{ */
740/** R: Read. */
741#define VTD_BF_SL_PDE2M_R_SHIFT 0
742#define VTD_BF_SL_PDE2M_R_MASK UINT64_C(0x0000000000000001)
743/** W: Write. */
744#define VTD_BF_SL_PDE2M_W_SHIFT 1
745#define VTD_BF_SL_PDE2M_W_MASK UINT64_C(0x0000000000000002)
746/** X: Execute. */
747#define VTD_BF_SL_PDE2M_X_SHIFT 2
748#define VTD_BF_SL_PDE2M_X_MASK UINT64_C(0x0000000000000004)
749/** EMT: Extended Memory Type. */
750#define VTD_BF_SL_PDE2M_EMT_SHIFT 3
751#define VTD_BF_SL_PDE2M_EMT_MASK UINT64_C(0x0000000000000038)
752/** IPAT: Ignore PAT (Page Attribute Table). */
753#define VTD_BF_SL_PDE2M_IPAT_SHIFT 6
754#define VTD_BF_SL_PDE2M_IPAT_MASK UINT64_C(0x0000000000000040)
755/** PS: Page Size (MB1). */
756#define VTD_BF_SL_PDE2M_PS_SHIFT 7
757#define VTD_BF_SL_PDE2M_PS_MASK UINT64_C(0x0000000000000080)
758/** A: Accessed. */
759#define VTD_BF_SL_PDE2M_A_SHIFT 8
760#define VTD_BF_SL_PDE2M_A_MASK UINT64_C(0x0000000000000100)
761/** D: Dirty. */
762#define VTD_BF_SL_PDE2M_D_SHIFT 9
763#define VTD_BF_SL_PDE2M_D_MASK UINT64_C(0x0000000000000200)
764/** IGN: Ignored (bit 10). */
765#define VTD_BF_SL_PDE2M_IGN_10_SHIFT 10
766#define VTD_BF_SL_PDE2M_IGN_10_MASK UINT64_C(0x0000000000000400)
767/** R: Reserved (bit 11). */
768#define VTD_BF_SL_PDE2M_RSVD_11_SHIFT 11
769#define VTD_BF_SL_PDE2M_RSVD_11_MASK UINT64_C(0x0000000000000800)
770/** R: Reserved (bits 20:12). */
771#define VTD_BF_SL_PDE2M_RSVD_20_12_SHIFT 12
772#define VTD_BF_SL_PDE2M_RSVD_20_12_MASK UINT64_C(0x00000000001ff000)
773/** ADDR: Address of 2MB page. */
774#define VTD_BF_SL_PDE2M_ADDR_SHIFT 21
775#define VTD_BF_SL_PDE2M_ADDR_MASK UINT64_C(0x000fffffffe00000)
776/** IGN: Ignored (bits 61:52). */
777#define VTD_BF_SL_PDE2M_IGN_61_52_SHIFT 52
778#define VTD_BF_SL_PDE2M_IGN_61_52_MASK UINT64_C(0x3ff0000000000000)
779/** R: Reserved (bit 62). */
780#define VTD_BF_SL_PDE2M_RSVD_62_SHIFT 62
781#define VTD_BF_SL_PDE2M_RSVD_62_MASK UINT64_C(0x4000000000000000)
782/** IGN: Ignored (bit 63). */
783#define VTD_BF_SL_PDE2M_IGN_63_SHIFT 63
784#define VTD_BF_SL_PDE2M_IGN_63_MASK UINT64_C(0x8000000000000000)
785RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_SL_PDE2M_, UINT64_C(0), UINT64_MAX,
786 (R, W, X, EMT, IPAT, PS, A, D, IGN_10, RSVD_11, RSVD_20_12, ADDR, IGN_61_52, RSVD_62, IGN_63));
787
788/** Second-level PDE (2MB page) valid mask. */
789#define VTD_SL_PDE2M_VALID_MASK ( VTD_BF_SL_PDE2M_R_MASK | VTD_BF_SL_PDE2M_W_MASK \
790 | VTD_BF_SL_PDE2M_X_MASK | VTD_BF_SL_PDE2M_EMT_MASK \
791 | VTD_BF_SL_PDE2M_IPAT_MASK | VTD_BF_SL_PDE2M_PS_MASK \
792 | VTD_BF_SL_PDE2M_A_MASK | VTD_BF_SL_PDE2M_D_MASK \
793 | VTD_BF_SL_PDE2M_IGN_10_MASK | VTD_BF_SL_PDE2M_ADDR_MASK \
794 | VTD_BF_SL_PDE2M_IGN_61_52_MASK | VTD_BF_SL_PDE2M_IGN_63_MASK)
795/** @} */
796
797
798/** @name Second-Level PDE.
799 * In accordance with the Intel spec.
800 * @{ */
801/** R: Read. */
802#define VTD_BF_SL_PDE_R_SHIFT 0
803#define VTD_BF_SL_PDE_R_MASK UINT64_C(0x0000000000000001)
804/** W: Write. */
805#define VTD_BF_SL_PDE_W_SHIFT 1
806#define VTD_BF_SL_PDE_W_MASK UINT64_C(0x0000000000000002)
807/** X: Execute. */
808#define VTD_BF_SL_PDE_X_SHIFT 2
809#define VTD_BF_SL_PDE_X_MASK UINT64_C(0x0000000000000004)
810/** IGN: Ignored (bits 6:3). */
811#define VTD_BF_SL_PDE_IGN_6_3_SHIFT 3
812#define VTD_BF_SL_PDE_IGN_6_3_MASK UINT64_C(0x0000000000000078)
813/** PS: Page Size (MBZ). */
814#define VTD_BF_SL_PDE_PS_SHIFT 7
815#define VTD_BF_SL_PDE_PS_MASK UINT64_C(0x0000000000000080)
816/** A: Accessed. */
817#define VTD_BF_SL_PDE_A_SHIFT 8
818#define VTD_BF_SL_PDE_A_MASK UINT64_C(0x0000000000000100)
819/** IGN: Ignored (bits 10:9). */
820#define VTD_BF_SL_PDE_IGN_10_9_SHIFT 9
821#define VTD_BF_SL_PDE_IGN_10_9_MASK UINT64_C(0x0000000000000600)
822/** R: Reserved (bit 11). */
823#define VTD_BF_SL_PDE_RSVD_11_SHIFT 11
824#define VTD_BF_SL_PDE_RSVD_11_MASK UINT64_C(0x0000000000000800)
825/** ADDR: Address of second-level PT. */
826#define VTD_BF_SL_PDE_ADDR_SHIFT 12
827#define VTD_BF_SL_PDE_ADDR_MASK UINT64_C(0x000ffffffffff000)
828/** IGN: Ignored (bits 61:52). */
829#define VTD_BF_SL_PDE_IGN_61_52_SHIFT 52
830#define VTD_BF_SL_PDE_IGN_61_52_MASK UINT64_C(0x3ff0000000000000)
831/** R: Reserved (bit 62). */
832#define VTD_BF_SL_PDE_RSVD_62_SHIFT 62
833#define VTD_BF_SL_PDE_RSVD_62_MASK UINT64_C(0x4000000000000000)
834/** IGN: Ignored (bit 63). */
835#define VTD_BF_SL_PDE_IGN_63_SHIFT 63
836#define VTD_BF_SL_PDE_IGN_63_MASK UINT64_C(0x8000000000000000)
837RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_SL_PDE_, UINT64_C(0), UINT64_MAX,
838 (R, W, X, IGN_6_3, PS, A, IGN_10_9, RSVD_11, ADDR, IGN_61_52, RSVD_62, IGN_63));
839
840/** Second-level PDE valid mask. */
841#define VTD_SL_PDE_VALID_MASK ( VTD_BF_SL_PDE_R_MASK | VTD_BF_SL_PDE_W_MASK \
842 | VTD_BF_SL_PDE_X_MASK | VTD_BF_SL_PDE_IGN_6_3_MASK \
843 | VTD_BF_SL_PDE_PS_MASK | VTD_BF_SL_PDE_A_MASK \
844 | VTD_BF_SL_PDE_IGN_10_9_MASK | VTD_BF_SL_PDE_ADDR_MASK \
845 | VTD_BF_SL_PDE_IGN_61_52_MASK | VTD_BF_SL_PDE_IGN_63_MASK)
846/** @} */
847
848
849/** @name Second-Level PTE.
850 * In accordance with the Intel spec.
851 * @{ */
852/** R: Read. */
853#define VTD_BF_SL_PTE_R_SHIFT 0
854#define VTD_BF_SL_PTE_R_MASK UINT64_C(0x0000000000000001)
855/** W: Write. */
856#define VTD_BF_SL_PTE_W_SHIFT 1
857#define VTD_BF_SL_PTE_W_MASK UINT64_C(0x0000000000000002)
858/** X: Execute. */
859#define VTD_BF_SL_PTE_X_SHIFT 2
860#define VTD_BF_SL_PTE_X_MASK UINT64_C(0x0000000000000004)
861/** EMT: Extended Memory Type. */
862#define VTD_BF_SL_PTE_EMT_SHIFT 3
863#define VTD_BF_SL_PTE_EMT_MASK UINT64_C(0x0000000000000038)
864/** IPAT: Ignore PAT (Page Attribute Table). */
865#define VTD_BF_SL_PTE_IPAT_SHIFT 6
866#define VTD_BF_SL_PTE_IPAT_MASK UINT64_C(0x0000000000000040)
867/** IGN: Ignored (bit 7). */
868#define VTD_BF_SL_PTE_IGN_7_SHIFT 7
869#define VTD_BF_SL_PTE_IGN_7_MASK UINT64_C(0x0000000000000080)
870/** A: Accessed. */
871#define VTD_BF_SL_PTE_A_SHIFT 8
872#define VTD_BF_SL_PTE_A_MASK UINT64_C(0x0000000000000100)
873/** D: Dirty. */
874#define VTD_BF_SL_PTE_D_SHIFT 9
875#define VTD_BF_SL_PTE_D_MASK UINT64_C(0x0000000000000200)
876/** IGN: Ignored (bit 10). */
877#define VTD_BF_SL_PTE_IGN_10_SHIFT 10
878#define VTD_BF_SL_PTE_IGN_10_MASK UINT64_C(0x0000000000000400)
879/** R: Reserved (bit 11). */
880#define VTD_BF_SL_PTE_RSVD_11_SHIFT 11
881#define VTD_BF_SL_PTE_RSVD_11_MASK UINT64_C(0x0000000000000800)
882/** ADDR: Address of 4K page. */
883#define VTD_BF_SL_PTE_ADDR_SHIFT 12
884#define VTD_BF_SL_PTE_ADDR_MASK UINT64_C(0x000ffffffffff000)
885/** IGN: Ignored (bits 61:52). */
886#define VTD_BF_SL_PTE_IGN_61_52_SHIFT 52
887#define VTD_BF_SL_PTE_IGN_61_52_MASK UINT64_C(0x3ff0000000000000)
888/** R: Reserved (bit 62). */
889#define VTD_BF_SL_PTE_RSVD_62_SHIFT 62
890#define VTD_BF_SL_PTE_RSVD_62_MASK UINT64_C(0x4000000000000000)
891/** IGN: Ignored (bit 63). */
892#define VTD_BF_SL_PTE_IGN_63_SHIFT 63
893#define VTD_BF_SL_PTE_IGN_63_MASK UINT64_C(0x8000000000000000)
894RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_SL_PTE_, UINT64_C(0), UINT64_MAX,
895 (R, W, X, EMT, IPAT, IGN_7, A, D, IGN_10, RSVD_11, ADDR, IGN_61_52, RSVD_62, IGN_63));
896
897/** Second-level PTE valid mask. */
898#define VTD_SL_PTE_VALID_MASK ( VTD_BF_SL_PTE_R_MASK | VTD_BF_SL_PTE_W_MASK \
899 | VTD_BF_SL_PTE_X_MASK | VTD_BF_SL_PTE_EMT_MASK \
900 | VTD_BF_SL_PTE_IPAT_MASK | VTD_BF_SL_PTE_IGN_7_MASK \
901 | VTD_BF_SL_PTE_A_MASK | VTD_BF_SL_PTE_D_MASK \
902 | VTD_BF_SL_PTE_IGN_10_MASK | VTD_BF_SL_PTE_ADDR_MASK \
903 | VTD_BF_SL_PTE_IGN_61_52_MASK | VTD_BF_SL_PTE_IGN_63_MASK)
904/** @} */
905
906
907/** @name Fault Record.
908 * In accordance with the Intel spec.
909 * @{ */
910/** R: Reserved (bits 11:0). */
911#define VTD_BF_0_FAULT_RECORD_RSVD_11_0_SHIFT 0
912#define VTD_BF_0_FAULT_RECORD_RSVD_11_0_MASK UINT64_C(0x0000000000000fff)
913/** FI: Fault Information. */
914#define VTD_BF_0_FAULT_RECORD_FI_SHIFT 12
915#define VTD_BF_0_FAULT_RECORD_FI_MASK UINT64_C(0xfffffffffffff000)
916RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_FAULT_RECORD_, UINT64_C(0), UINT64_MAX,
917 (RSVD_11_0, FI));
918
919/** SID: Source identifier. */
920#define VTD_BF_1_FAULT_RECORD_SID_SHIFT 0
921#define VTD_BF_1_FAULT_RECORD_SID_MASK UINT64_C(0x000000000000ffff)
922/** R: Reserved (bits 28:16). */
923#define VTD_BF_1_FAULT_RECORD_RSVD_28_16_SHIFT 16
924#define VTD_BF_1_FAULT_RECORD_RSVD_28_16_MASK UINT64_C(0x000000001fff0000)
925/** PRIV: Privilege Mode Requested. */
926#define VTD_BF_1_FAULT_RECORD_PRIV_SHIFT 29
927#define VTD_BF_1_FAULT_RECORD_PRIV_MASK UINT64_C(0x0000000020000000)
928/** EXE: Execute Permission Requested. */
929#define VTD_BF_1_FAULT_RECORD_EXE_SHIFT 30
930#define VTD_BF_1_FAULT_RECORD_EXE_MASK UINT64_C(0x0000000040000000)
931/** PP: PASID Present. */
932#define VTD_BF_1_FAULT_RECORD_PP_SHIFT 31
933#define VTD_BF_1_FAULT_RECORD_PP_MASK UINT64_C(0x0000000080000000)
934/** FR: Fault Reason. */
935#define VTD_BF_1_FAULT_RECORD_FR_SHIFT 32
936#define VTD_BF_1_FAULT_RECORD_FR_MASK UINT64_C(0x000000ff00000000)
937/** PV: PASID Value. */
938#define VTD_BF_1_FAULT_RECORD_PV_SHIFT 40
939#define VTD_BF_1_FAULT_RECORD_PV_MASK UINT64_C(0x0fffff0000000000)
940/** AT: Address Type. */
941#define VTD_BF_1_FAULT_RECORD_AT_SHIFT 60
942#define VTD_BF_1_FAULT_RECORD_AT_MASK UINT64_C(0x3000000000000000)
943/** T: Type. */
944#define VTD_BF_1_FAULT_RECORD_T_SHIFT 62
945#define VTD_BF_1_FAULT_RECORD_T_MASK UINT64_C(0x4000000000000000)
946/** R: Reserved (bit 127). */
947#define VTD_BF_1_FAULT_RECORD_RSVD_63_SHIFT 63
948#define VTD_BF_1_FAULT_RECORD_RSVD_63_MASK UINT64_C(0x8000000000000000)
949RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_FAULT_RECORD_, UINT64_C(0), UINT64_MAX,
950 (SID, RSVD_28_16, PRIV, EXE, PP, FR, PV, AT, T, RSVD_63));
951
952/** Fault record. */
953typedef struct VTD_FAULT_RECORD_T
954{
955 /** The qwords in the fault record. */
956 uint64_t au64[2];
957} VTD_FAULT_RECORD_T;
958/** Pointer to a fault record. */
959typedef VTD_FAULT_RECORD_T *PVTD_FAULT_RECORD_T;
960/** Pointer to a const fault record. */
961typedef VTD_FAULT_RECORD_T const *PCVTD_FAULT_RECORD_T;
962/** @} */
963
964
965/** @name Interrupt Remapping Table Entry (IRTE) for Remapped Interrupts.
966 * In accordance with the Intel spec.
967 * @{ */
968/** P: Present. */
969#define VTD_BF_0_IRTE_P_SHIFT 0
970#define VTD_BF_0_IRTE_P_MASK UINT64_C(0x0000000000000001)
971/** FPD: Fault Processing Disable. */
972#define VTD_BF_0_IRTE_FPD_SHIFT 1
973#define VTD_BF_0_IRTE_FPD_MASK UINT64_C(0x0000000000000002)
974/** DM: Destination Mode (0=physical, 1=logical). */
975#define VTD_BF_0_IRTE_DM_SHIFT 2
976#define VTD_BF_0_IRTE_DM_MASK UINT64_C(0x0000000000000004)
977/** RH: Redirection Hint. */
978#define VTD_BF_0_IRTE_RH_SHIFT 3
979#define VTD_BF_0_IRTE_RH_MASK UINT64_C(0x0000000000000008)
980/** TM: Trigger Mode. */
981#define VTD_BF_0_IRTE_TM_SHIFT 4
982#define VTD_BF_0_IRTE_TM_MASK UINT64_C(0x0000000000000010)
983/** DLM: Delivery Mode. */
984#define VTD_BF_0_IRTE_DLM_SHIFT 5
985#define VTD_BF_0_IRTE_DLM_MASK UINT64_C(0x00000000000000e0)
986/** AVL: Available. */
987#define VTD_BF_0_IRTE_AVAIL_SHIFT 8
988#define VTD_BF_0_IRTE_AVAIL_MASK UINT64_C(0x0000000000000f00)
989/** R: Reserved (bits 14:12). */
990#define VTD_BF_0_IRTE_RSVD_14_12_SHIFT 12
991#define VTD_BF_0_IRTE_RSVD_14_12_MASK UINT64_C(0x0000000000007000)
992/** IM: IRTE Mode. */
993#define VTD_BF_0_IRTE_IM_SHIFT 15
994#define VTD_BF_0_IRTE_IM_MASK UINT64_C(0x0000000000008000)
995/** V: Vector. */
996#define VTD_BF_0_IRTE_V_SHIFT 16
997#define VTD_BF_0_IRTE_V_MASK UINT64_C(0x0000000000ff0000)
998/** R: Reserved (bits 31:24). */
999#define VTD_BF_0_IRTE_RSVD_31_24_SHIFT 24
1000#define VTD_BF_0_IRTE_RSVD_31_24_MASK UINT64_C(0x00000000ff000000)
1001/** DST: Desination Id. */
1002#define VTD_BF_0_IRTE_DST_SHIFT 32
1003#define VTD_BF_0_IRTE_DST_MASK UINT64_C(0xffffffff00000000)
1004/** R: Reserved (bits 39:32) when EIME=0. */
1005#define VTD_BF_0_IRTE_RSVD_39_32_SHIFT 32
1006#define VTD_BF_0_IRTE_RSVD_39_32_MASK UINT64_C(0x000000ff00000000)
1007/** DST_XAPIC: Destination Id when EIME=0. */
1008#define VTD_BF_0_IRTE_DST_XAPIC_SHIFT 40
1009#define VTD_BF_0_IRTE_DST_XAPIC_MASK UINT64_C(0x0000ff0000000000)
1010/** R: Reserved (bits 63:48) when EIME=0. */
1011#define VTD_BF_0_IRTE_RSVD_63_48_SHIFT 48
1012#define VTD_BF_0_IRTE_RSVD_63_48_MASK UINT64_C(0xffff000000000000)
1013RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_IRTE_, UINT64_C(0), UINT64_MAX,
1014 (P, FPD, DM, RH, TM, DLM, AVAIL, RSVD_14_12, IM, V, RSVD_31_24, DST));
1015RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_IRTE_, UINT64_C(0), UINT64_MAX,
1016 (P, FPD, DM, RH, TM, DLM, AVAIL, RSVD_14_12, IM, V, RSVD_31_24, RSVD_39_32, DST_XAPIC, RSVD_63_48));
1017
1018/** SID: Source Identifier. */
1019#define VTD_BF_1_IRTE_SID_SHIFT 0
1020#define VTD_BF_1_IRTE_SID_MASK UINT64_C(0x000000000000ffff)
1021/** SQ: Source-Id Qualifier. */
1022#define VTD_BF_1_IRTE_SQ_SHIFT 16
1023#define VTD_BF_1_IRTE_SQ_MASK UINT64_C(0x0000000000030000)
1024/** SVT: Source Validation Type. */
1025#define VTD_BF_1_IRTE_SVT_SHIFT 18
1026#define VTD_BF_1_IRTE_SVT_MASK UINT64_C(0x00000000000c0000)
1027/** R: Reserved (bits 127:84). */
1028#define VTD_BF_1_IRTE_RSVD_63_20_SHIFT 20
1029#define VTD_BF_1_IRTE_RSVD_63_20_MASK UINT64_C(0xfffffffffff00000)
1030RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_IRTE_, UINT64_C(0), UINT64_MAX,
1031 (SID, SQ, SVT, RSVD_63_20));
1032
1033/** IRTE: Qword 0 valid mask when EIME=1. */
1034#define VTD_IRTE_0_X2APIC_VALID_MASK ( VTD_BF_0_IRTE_P_MASK | VTD_BF_0_IRTE_FPD_MASK \
1035 | VTD_BF_0_IRTE_DM_MASK | VTD_BF_0_IRTE_RH_MASK \
1036 | VTD_BF_0_IRTE_TM_MASK | VTD_BF_0_IRTE_DLM_MASK \
1037 | VTD_BF_0_IRTE_AVAIL_MASK | VTD_BF_0_IRTE_IM_MASK \
1038 | VTD_BF_0_IRTE_V_MASK | VTD_BF_0_IRTE_DST_MASK)
1039/** IRTE: Qword 0 valid mask when EIME=0. */
1040#define VTD_IRTE_0_XAPIC_VALID_MASK ( VTD_BF_0_IRTE_P_MASK | VTD_BF_0_IRTE_FPD_MASK \
1041 | VTD_BF_0_IRTE_DM_MASK | VTD_BF_0_IRTE_RH_MASK \
1042 | VTD_BF_0_IRTE_TM_MASK | VTD_BF_0_IRTE_DLM_MASK \
1043 | VTD_BF_0_IRTE_AVAIL_MASK | VTD_BF_0_IRTE_IM_MASK \
1044 | VTD_BF_0_IRTE_V_MASK | VTD_BF_0_IRTE_DST_XAPIC_MASK)
1045/** IRTE: Qword 1 valid mask. */
1046#define VTD_IRTE_1_VALID_MASK ( VTD_BF_1_IRTE_SID_MASK | VTD_BF_1_IRTE_SQ_MASK \
1047 | VTD_BF_1_IRTE_SVT_MASK)
1048
1049/** Interrupt Remapping Table Entry (IRTE) for remapped interrupts. */
1050typedef struct VTD_IRTE_T
1051{
1052 /** The qwords in the IRTE. */
1053 uint64_t au64[2];
1054} VTD_IRTE_T;
1055/** Pointer to an IRTE. */
1056typedef VTD_IRTE_T *PVTD_IRTE_T;
1057/** Pointer to a const IRTE. */
1058typedef VTD_IRTE_T const *PCVTD_IRTE_T;
1059
1060/** IRTE SVT: No validation required. */
1061#define VTD_IRTE_SVT_NONE 0
1062/** IRTE SVT: Validate using a mask derived from SID and SQT. */
1063#define VTD_IRTE_SVT_VALIDATE_MASK 1
1064/** IRTE SVT: Validate using Bus range in the SID. */
1065#define VTD_IRTE_SVT_VALIDATE_BUS_RANGE 2
1066/** IRTE SVT: Reserved. */
1067#define VTD_IRTE_SVT_VALIDATE_RSVD 3
1068/** @} */
1069
1070
1071/** @name Version Register (VER_REG).
1072 * In accordance with the Intel spec.
1073 * @{ */
1074/** Min: Minor Version Number. */
1075#define VTD_BF_VER_REG_MIN_SHIFT 0
1076#define VTD_BF_VER_REG_MIN_MASK UINT32_C(0x0000000f)
1077/** Max: Major Version Number. */
1078#define VTD_BF_VER_REG_MAX_SHIFT 4
1079#define VTD_BF_VER_REG_MAX_MASK UINT32_C(0x000000f0)
1080/** R: Reserved (bits 31:8). */
1081#define VTD_BF_VER_REG_RSVD_31_8_SHIFT 8
1082#define VTD_BF_VER_REG_RSVD_31_8_MASK UINT32_C(0xffffff00)
1083RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_VER_REG_, UINT32_C(0), UINT32_MAX,
1084 (MIN, MAX, RSVD_31_8));
1085/** RW: Read/write mask. */
1086#define VTD_VER_REG_RW_MASK UINT32_C(0)
1087/** @} */
1088
1089
1090/** @name Capability Register (CAP_REG).
1091 * In accordance with the Intel spec.
1092 * @{ */
1093/** ND: Number of domains supported. */
1094#define VTD_BF_CAP_REG_ND_SHIFT 0
1095#define VTD_BF_CAP_REG_ND_MASK UINT64_C(0x0000000000000007)
1096/** AFL: Advanced Fault Logging. */
1097#define VTD_BF_CAP_REG_AFL_SHIFT 3
1098#define VTD_BF_CAP_REG_AFL_MASK UINT64_C(0x0000000000000008)
1099/** RWBF: Required Write-Buffer Flushing. */
1100#define VTD_BF_CAP_REG_RWBF_SHIFT 4
1101#define VTD_BF_CAP_REG_RWBF_MASK UINT64_C(0x0000000000000010)
1102/** PLMR: Protected Low-Memory Region. */
1103#define VTD_BF_CAP_REG_PLMR_SHIFT 5
1104#define VTD_BF_CAP_REG_PLMR_MASK UINT64_C(0x0000000000000020)
1105/** PHMR: Protected High-Memory Region. */
1106#define VTD_BF_CAP_REG_PHMR_SHIFT 6
1107#define VTD_BF_CAP_REG_PHMR_MASK UINT64_C(0x0000000000000040)
1108/** CM: Caching Mode. */
1109#define VTD_BF_CAP_REG_CM_SHIFT 7
1110#define VTD_BF_CAP_REG_CM_MASK UINT64_C(0x0000000000000080)
1111/** SAGAW: Supported Adjusted Guest Address Widths. */
1112#define VTD_BF_CAP_REG_SAGAW_SHIFT 8
1113#define VTD_BF_CAP_REG_SAGAW_MASK UINT64_C(0x0000000000001f00)
1114/** R: Reserved (bits 15:13). */
1115#define VTD_BF_CAP_REG_RSVD_15_13_SHIFT 13
1116#define VTD_BF_CAP_REG_RSVD_15_13_MASK UINT64_C(0x000000000000e000)
1117/** MGAW: Maximum Guest Address Width. */
1118#define VTD_BF_CAP_REG_MGAW_SHIFT 16
1119#define VTD_BF_CAP_REG_MGAW_MASK UINT64_C(0x00000000003f0000)
1120/** ZLR: Zero Length Read. */
1121#define VTD_BF_CAP_REG_ZLR_SHIFT 22
1122#define VTD_BF_CAP_REG_ZLR_MASK UINT64_C(0x0000000000400000)
1123/** DEP: Deprecated MBZ. Reserved (bit 23). */
1124#define VTD_BF_CAP_REG_RSVD_23_SHIFT 23
1125#define VTD_BF_CAP_REG_RSVD_23_MASK UINT64_C(0x0000000000800000)
1126/** FRO: Fault-recording Register Offset. */
1127#define VTD_BF_CAP_REG_FRO_SHIFT 24
1128#define VTD_BF_CAP_REG_FRO_MASK UINT64_C(0x00000003ff000000)
1129/** SLLPS: Second Level Large Page Support. */
1130#define VTD_BF_CAP_REG_SLLPS_SHIFT 34
1131#define VTD_BF_CAP_REG_SLLPS_MASK UINT64_C(0x0000003c00000000)
1132/** R: Reserved (bit 38). */
1133#define VTD_BF_CAP_REG_RSVD_38_SHIFT 38
1134#define VTD_BF_CAP_REG_RSVD_38_MASK UINT64_C(0x0000004000000000)
1135/** PSI: Page Selective Invalidation. */
1136#define VTD_BF_CAP_REG_PSI_SHIFT 39
1137#define VTD_BF_CAP_REG_PSI_MASK UINT64_C(0x0000008000000000)
1138/** NFR: Number of Fault-recording Registers. */
1139#define VTD_BF_CAP_REG_NFR_SHIFT 40
1140#define VTD_BF_CAP_REG_NFR_MASK UINT64_C(0x0000ff0000000000)
1141/** MAMV: Maximum Address Mask Value. */
1142#define VTD_BF_CAP_REG_MAMV_SHIFT 48
1143#define VTD_BF_CAP_REG_MAMV_MASK UINT64_C(0x003f000000000000)
1144/** DWD: Write Draining. */
1145#define VTD_BF_CAP_REG_DWD_SHIFT 54
1146#define VTD_BF_CAP_REG_DWD_MASK UINT64_C(0x0040000000000000)
1147/** DRD: Read Draining. */
1148#define VTD_BF_CAP_REG_DRD_SHIFT 55
1149#define VTD_BF_CAP_REG_DRD_MASK UINT64_C(0x0080000000000000)
1150/** FL1GP: First Level 1 GB Page Support. */
1151#define VTD_BF_CAP_REG_FL1GP_SHIFT 56
1152#define VTD_BF_CAP_REG_FL1GP_MASK UINT64_C(0x0100000000000000)
1153/** R: Reserved (bits 58:57). */
1154#define VTD_BF_CAP_REG_RSVD_58_57_SHIFT 57
1155#define VTD_BF_CAP_REG_RSVD_58_57_MASK UINT64_C(0x0600000000000000)
1156/** PI: Posted Interrupt Support. */
1157#define VTD_BF_CAP_REG_PI_SHIFT 59
1158#define VTD_BF_CAP_REG_PI_MASK UINT64_C(0x0800000000000000)
1159/** FL5LP: First Level 5-level Paging Support. */
1160#define VTD_BF_CAP_REG_FL5LP_SHIFT 60
1161#define VTD_BF_CAP_REG_FL5LP_MASK UINT64_C(0x1000000000000000)
1162/** R: Reserved (bit 61). */
1163#define VTD_BF_CAP_REG_RSVD_61_SHIFT 61
1164#define VTD_BF_CAP_REG_RSVD_61_MASK UINT64_C(0x2000000000000000)
1165/** ESIRTPS: Enhanced Set Interrupt Root Table Pointer Support. */
1166#define VTD_BF_CAP_REG_ESIRTPS_SHIFT 62
1167#define VTD_BF_CAP_REG_ESIRTPS_MASK UINT64_C(0x4000000000000000)
1168/** : Enhanced Set Root Table Pointer Support. */
1169#define VTD_BF_CAP_REG_ESRTPS_SHIFT 63
1170#define VTD_BF_CAP_REG_ESRTPS_MASK UINT64_C(0x8000000000000000)
1171RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_CAP_REG_, UINT64_C(0), UINT64_MAX,
1172 (ND, AFL, RWBF, PLMR, PHMR, CM, SAGAW, RSVD_15_13, MGAW, ZLR, RSVD_23, FRO, SLLPS, RSVD_38, PSI, NFR,
1173 MAMV, DWD, DRD, FL1GP, RSVD_58_57, PI, FL5LP, RSVD_61, ESIRTPS, ESRTPS));
1174
1175/** RW: Read/write mask. */
1176#define VTD_CAP_REG_RW_MASK UINT64_C(0)
1177/** @} */
1178
1179
1180/** @name Extended Capability Register (ECAP_REG).
1181 * In accordance with the Intel spec.
1182 * @{ */
1183/** C: Page-walk Coherence. */
1184#define VTD_BF_ECAP_REG_C_SHIFT 0
1185#define VTD_BF_ECAP_REG_C_MASK UINT64_C(0x0000000000000001)
1186/** QI: Queued Invalidation Support. */
1187#define VTD_BF_ECAP_REG_QI_SHIFT 1
1188#define VTD_BF_ECAP_REG_QI_MASK UINT64_C(0x0000000000000002)
1189/** DT: Device-TLB Support. */
1190#define VTD_BF_ECAP_REG_DT_SHIFT 2
1191#define VTD_BF_ECAP_REG_DT_MASK UINT64_C(0x0000000000000004)
1192/** IR: Interrupt Remapping Support. */
1193#define VTD_BF_ECAP_REG_IR_SHIFT 3
1194#define VTD_BF_ECAP_REG_IR_MASK UINT64_C(0x0000000000000008)
1195/** EIM: Extended Interrupt Mode. */
1196#define VTD_BF_ECAP_REG_EIM_SHIFT 4
1197#define VTD_BF_ECAP_REG_EIM_MASK UINT64_C(0x0000000000000010)
1198/** DEP: Deprecated MBZ. Reserved (bit 5). */
1199#define VTD_BF_ECAP_REG_RSVD_5_SHIFT 5
1200#define VTD_BF_ECAP_REG_RSVD_5_MASK UINT64_C(0x0000000000000020)
1201/** PT: Pass Through. */
1202#define VTD_BF_ECAP_REG_PT_SHIFT 6
1203#define VTD_BF_ECAP_REG_PT_MASK UINT64_C(0x0000000000000040)
1204/** SC: Snoop Control. */
1205#define VTD_BF_ECAP_REG_SC_SHIFT 7
1206#define VTD_BF_ECAP_REG_SC_MASK UINT64_C(0x0000000000000080)
1207/** IRO: IOTLB Register Offset. */
1208#define VTD_BF_ECAP_REG_IRO_SHIFT 8
1209#define VTD_BF_ECAP_REG_IRO_MASK UINT64_C(0x000000000003ff00)
1210/** R: Reserved (bits 19:18). */
1211#define VTD_BF_ECAP_REG_RSVD_19_18_SHIFT 18
1212#define VTD_BF_ECAP_REG_RSVD_19_18_MASK UINT64_C(0x00000000000c0000)
1213/** MHMV: Maximum Handle Mask Value. */
1214#define VTD_BF_ECAP_REG_MHMV_SHIFT 20
1215#define VTD_BF_ECAP_REG_MHMV_MASK UINT64_C(0x0000000000f00000)
1216/** DEP: Deprecated MBZ. Reserved (bit 24). */
1217#define VTD_BF_ECAP_REG_RSVD_24_SHIFT 24
1218#define VTD_BF_ECAP_REG_RSVD_24_MASK UINT64_C(0x0000000001000000)
1219/** MTS: Memory Type Support. */
1220#define VTD_BF_ECAP_REG_MTS_SHIFT 25
1221#define VTD_BF_ECAP_REG_MTS_MASK UINT64_C(0x0000000002000000)
1222/** NEST: Nested Translation Support. */
1223#define VTD_BF_ECAP_REG_NEST_SHIFT 26
1224#define VTD_BF_ECAP_REG_NEST_MASK UINT64_C(0x0000000004000000)
1225/** R: Reserved (bit 27). */
1226#define VTD_BF_ECAP_REG_RSVD_27_SHIFT 27
1227#define VTD_BF_ECAP_REG_RSVD_27_MASK UINT64_C(0x0000000008000000)
1228/** DEP: Deprecated MBZ. Reserved (bit 28). */
1229#define VTD_BF_ECAP_REG_RSVD_28_SHIFT 28
1230#define VTD_BF_ECAP_REG_RSVD_28_MASK UINT64_C(0x0000000010000000)
1231/** PRS: Page Request Support. */
1232#define VTD_BF_ECAP_REG_PRS_SHIFT 29
1233#define VTD_BF_ECAP_REG_PRS_MASK UINT64_C(0x0000000020000000)
1234/** ERS: Execute Request Support. */
1235#define VTD_BF_ECAP_REG_ERS_SHIFT 30
1236#define VTD_BF_ECAP_REG_ERS_MASK UINT64_C(0x0000000040000000)
1237/** SRS: Supervisor Request Support. */
1238#define VTD_BF_ECAP_REG_SRS_SHIFT 31
1239#define VTD_BF_ECAP_REG_SRS_MASK UINT64_C(0x0000000080000000)
1240/** R: Reserved (bit 32). */
1241#define VTD_BF_ECAP_REG_RSVD_32_SHIFT 32
1242#define VTD_BF_ECAP_REG_RSVD_32_MASK UINT64_C(0x0000000100000000)
1243/** NWFS: No Write Flag Support. */
1244#define VTD_BF_ECAP_REG_NWFS_SHIFT 33
1245#define VTD_BF_ECAP_REG_NWFS_MASK UINT64_C(0x0000000200000000)
1246/** EAFS: Extended Accessed Flags Support. */
1247#define VTD_BF_ECAP_REG_EAFS_SHIFT 34
1248#define VTD_BF_ECAP_REG_EAFS_MASK UINT64_C(0x0000000400000000)
1249/** PSS: PASID Size Supported. */
1250#define VTD_BF_ECAP_REG_PSS_SHIFT 35
1251#define VTD_BF_ECAP_REG_PSS_MASK UINT64_C(0x000000f800000000)
1252/** PASID: Process Address Space ID Support. */
1253#define VTD_BF_ECAP_REG_PASID_SHIFT 40
1254#define VTD_BF_ECAP_REG_PASID_MASK UINT64_C(0x0000010000000000)
1255/** DIT: Device-TLB Invalidation Throttle. */
1256#define VTD_BF_ECAP_REG_DIT_SHIFT 41
1257#define VTD_BF_ECAP_REG_DIT_MASK UINT64_C(0x0000020000000000)
1258/** PDS: Page-request Drain Support. */
1259#define VTD_BF_ECAP_REG_PDS_SHIFT 42
1260#define VTD_BF_ECAP_REG_PDS_MASK UINT64_C(0x0000040000000000)
1261/** SMTS: Scalable-Mode Translation Support. */
1262#define VTD_BF_ECAP_REG_SMTS_SHIFT 43
1263#define VTD_BF_ECAP_REG_SMTS_MASK UINT64_C(0x0000080000000000)
1264/** VCS: Virtual Command Support. */
1265#define VTD_BF_ECAP_REG_VCS_SHIFT 44
1266#define VTD_BF_ECAP_REG_VCS_MASK UINT64_C(0x0000100000000000)
1267/** SLADS: Second-Level Accessed/Dirty Support. */
1268#define VTD_BF_ECAP_REG_SLADS_SHIFT 45
1269#define VTD_BF_ECAP_REG_SLADS_MASK UINT64_C(0x0000200000000000)
1270/** SLTS: Second-Level Translation Support. */
1271#define VTD_BF_ECAP_REG_SLTS_SHIFT 46
1272#define VTD_BF_ECAP_REG_SLTS_MASK UINT64_C(0x0000400000000000)
1273/** FLTS: First-Level Translation Support. */
1274#define VTD_BF_ECAP_REG_FLTS_SHIFT 47
1275#define VTD_BF_ECAP_REG_FLTS_MASK UINT64_C(0x0000800000000000)
1276/** SMPWCS: Scalable-Mode Page-Walk Coherency Support. */
1277#define VTD_BF_ECAP_REG_SMPWCS_SHIFT 48
1278#define VTD_BF_ECAP_REG_SMPWCS_MASK UINT64_C(0x0001000000000000)
1279/** RPS: RID-PASID Support. */
1280#define VTD_BF_ECAP_REG_RPS_SHIFT 49
1281#define VTD_BF_ECAP_REG_RPS_MASK UINT64_C(0x0002000000000000)
1282/** R: Reserved (bits 51:50). */
1283#define VTD_BF_ECAP_REG_RSVD_51_50_SHIFT 50
1284#define VTD_BF_ECAP_REG_RSVD_51_50_MASK UINT64_C(0x000c000000000000)
1285/** ADMS: Abort DMA Mode Support. */
1286#define VTD_BF_ECAP_REG_ADMS_SHIFT 52
1287#define VTD_BF_ECAP_REG_ADMS_MASK UINT64_C(0x0010000000000000)
1288/** RPRIVS: RID_PRIV Support. */
1289#define VTD_BF_ECAP_REG_RPRIVS_SHIFT 53
1290#define VTD_BF_ECAP_REG_RPRIVS_MASK UINT64_C(0x0020000000000000)
1291/** R: Reserved (bits 63:54). */
1292#define VTD_BF_ECAP_REG_RSVD_63_54_SHIFT 54
1293#define VTD_BF_ECAP_REG_RSVD_63_54_MASK UINT64_C(0xffc0000000000000)
1294RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_ECAP_REG_, UINT64_C(0), UINT64_MAX,
1295 (C, QI, DT, IR, EIM, RSVD_5, PT, SC, IRO, RSVD_19_18, MHMV, RSVD_24, MTS, NEST, RSVD_27, RSVD_28,
1296 PRS, ERS, SRS, RSVD_32, NWFS, EAFS, PSS, PASID, DIT, PDS, SMTS, VCS, SLADS, SLTS, FLTS, SMPWCS, RPS,
1297 RSVD_51_50, ADMS, RPRIVS, RSVD_63_54));
1298
1299/** RW: Read/write mask. */
1300#define VTD_ECAP_REG_RW_MASK UINT64_C(0)
1301/** @} */
1302
1303
1304/** @name Global Command Register (GCMD_REG).
1305 * In accordance with the Intel spec.
1306 * @{ */
1307/** R: Reserved (bits 22:0). */
1308#define VTD_BF_GCMD_REG_RSVD_22_0_SHIFT 0
1309#define VTD_BF_GCMD_REG_RSVD_22_0_MASK UINT32_C(0x007fffff)
1310/** CFI: Compatibility Format Interrupt. */
1311#define VTD_BF_GCMD_REG_CFI_SHIFT 23
1312#define VTD_BF_GCMD_REG_CFI_MASK UINT32_C(0x00800000)
1313/** SIRTP: Set Interrupt Table Remap Pointer. */
1314#define VTD_BF_GCMD_REG_SIRTP_SHIFT 24
1315#define VTD_BF_GCMD_REG_SIRTP_MASK UINT32_C(0x01000000)
1316/** IRE: Interrupt Remap Enable. */
1317#define VTD_BF_GCMD_REG_IRE_SHIFT 25
1318#define VTD_BF_GCMD_REG_IRE_MASK UINT32_C(0x02000000)
1319/** QIE: Queued Invalidation Enable. */
1320#define VTD_BF_GCMD_REG_QIE_SHIFT 26
1321#define VTD_BF_GCMD_REG_QIE_MASK UINT32_C(0x04000000)
1322/** WBF: Write Buffer Flush. */
1323#define VTD_BF_GCMD_REG_WBF_SHIFT 27
1324#define VTD_BF_GCMD_REG_WBF_MASK UINT32_C(0x08000000)
1325/** EAFL: Enable Advance Fault Logging. */
1326#define VTD_BF_GCMD_REG_EAFL_SHIFT 28
1327#define VTD_BF_GCMD_REG_EAFL_MASK UINT32_C(0x10000000)
1328/** SFL: Set Fault Log. */
1329#define VTD_BF_GCMD_REG_SFL_SHIFT 29
1330#define VTD_BF_GCMD_REG_SFL_MASK UINT32_C(0x20000000)
1331/** SRTP: Set Root Table Pointer. */
1332#define VTD_BF_GCMD_REG_SRTP_SHIFT 30
1333#define VTD_BF_GCMD_REG_SRTP_MASK UINT32_C(0x40000000)
1334/** TE: Translation Enable. */
1335#define VTD_BF_GCMD_REG_TE_SHIFT 31
1336#define VTD_BF_GCMD_REG_TE_MASK UINT32_C(0x80000000)
1337RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_GCMD_REG_, UINT32_C(0), UINT32_MAX,
1338 (RSVD_22_0, CFI, SIRTP, IRE, QIE, WBF, EAFL, SFL, SRTP, TE));
1339
1340/** RW: Read/write mask. */
1341#define VTD_GCMD_REG_RW_MASK ( VTD_BF_GCMD_REG_TE_MASK | VTD_BF_GCMD_REG_SRTP_MASK \
1342 | VTD_BF_GCMD_REG_SFL_MASK | VTD_BF_GCMD_REG_EAFL_MASK \
1343 | VTD_BF_GCMD_REG_WBF_MASK | VTD_BF_GCMD_REG_QIE_MASK \
1344 | VTD_BF_GCMD_REG_IRE_MASK | VTD_BF_GCMD_REG_SIRTP_MASK \
1345 | VTD_BF_GCMD_REG_CFI_MASK)
1346/** @} */
1347
1348
1349/** @name Global Status Register (GSTS_REG).
1350 * In accordance with the Intel spec.
1351 * @{ */
1352/** R: Reserved (bits 22:0). */
1353#define VTD_BF_GSTS_REG_RSVD_22_0_SHIFT 0
1354#define VTD_BF_GSTS_REG_RSVD_22_0_MASK UINT32_C(0x007fffff)
1355/** CFIS: Compatibility Format Interrupt Status. */
1356#define VTD_BF_GSTS_REG_CFIS_SHIFT 23
1357#define VTD_BF_GSTS_REG_CFIS_MASK UINT32_C(0x00800000)
1358/** IRTPS: Interrupt Remapping Table Pointer Status. */
1359#define VTD_BF_GSTS_REG_IRTPS_SHIFT 24
1360#define VTD_BF_GSTS_REG_IRTPS_MASK UINT32_C(0x01000000)
1361/** IRES: Interrupt Remapping Enable Status. */
1362#define VTD_BF_GSTS_REG_IRES_SHIFT 25
1363#define VTD_BF_GSTS_REG_IRES_MASK UINT32_C(0x02000000)
1364/** QIES: Queued Invalidation Enable Status. */
1365#define VTD_BF_GSTS_REG_QIES_SHIFT 26
1366#define VTD_BF_GSTS_REG_QIES_MASK UINT32_C(0x04000000)
1367/** WBFS: Write Buffer Flush Status. */
1368#define VTD_BF_GSTS_REG_WBFS_SHIFT 27
1369#define VTD_BF_GSTS_REG_WBFS_MASK UINT32_C(0x08000000)
1370/** AFLS: Advanced Fault Logging Status. */
1371#define VTD_BF_GSTS_REG_AFLS_SHIFT 28
1372#define VTD_BF_GSTS_REG_AFLS_MASK UINT32_C(0x10000000)
1373/** FLS: Fault Log Status. */
1374#define VTD_BF_GSTS_REG_FLS_SHIFT 29
1375#define VTD_BF_GSTS_REG_FLS_MASK UINT32_C(0x20000000)
1376/** RTPS: Root Table Pointer Status. */
1377#define VTD_BF_GSTS_REG_RTPS_SHIFT 30
1378#define VTD_BF_GSTS_REG_RTPS_MASK UINT32_C(0x40000000)
1379/** TES: Translation Enable Status. */
1380#define VTD_BF_GSTS_REG_TES_SHIFT 31
1381#define VTD_BF_GSTS_REG_TES_MASK UINT32_C(0x80000000)
1382RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_GSTS_REG_, UINT32_C(0), UINT32_MAX,
1383 (RSVD_22_0, CFIS, IRTPS, IRES, QIES, WBFS, AFLS, FLS, RTPS, TES));
1384
1385/** RW: Read/write mask. */
1386#define VTD_GSTS_REG_RW_MASK UINT32_C(0)
1387/** @} */
1388
1389
1390/** @name Root Table Address Register (RTADDR_REG).
1391 * In accordance with the Intel spec.
1392 * @{ */
1393/** R: Reserved (bits 9:0). */
1394#define VTD_BF_RTADDR_REG_RSVD_9_0_SHIFT 0
1395#define VTD_BF_RTADDR_REG_RSVD_9_0_MASK UINT64_C(0x00000000000003ff)
1396/** TTM: Translation Table Mode. */
1397#define VTD_BF_RTADDR_REG_TTM_SHIFT 10
1398#define VTD_BF_RTADDR_REG_TTM_MASK UINT64_C(0x0000000000000c00)
1399/** RTA: Root Table Address. */
1400#define VTD_BF_RTADDR_REG_RTA_SHIFT 12
1401#define VTD_BF_RTADDR_REG_RTA_MASK UINT64_C(0xfffffffffffff000)
1402RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_RTADDR_REG_, UINT64_C(0), UINT64_MAX,
1403 (RSVD_9_0, TTM, RTA));
1404
1405/** RW: Read/write mask. */
1406#define VTD_RTADDR_REG_RW_MASK UINT64_C(0xfffffffffffffc00)
1407
1408/** RTADDR_REG.TTM: Legacy mode. */
1409#define VTD_TTM_LEGACY_MODE 0
1410/** RTADDR_REG.TTM: Scalable mode. */
1411#define VTD_TTM_SCALABLE_MODE 1
1412/** RTADDR_REG.TTM: Reserved. */
1413#define VTD_TTM_RSVD 2
1414/** RTADDR_REG.TTM: Abort DMA mode. */
1415#define VTD_TTM_ABORT_DMA_MODE 3
1416/** @} */
1417
1418
1419/** @name Context Command Register (CCMD_REG).
1420 * In accordance with the Intel spec.
1421 * @{ */
1422/** DID: Domain-ID. */
1423#define VTD_BF_CCMD_REG_DID_SHIFT 0
1424#define VTD_BF_CCMD_REG_DID_MASK UINT64_C(0x000000000000ffff)
1425/** SID: Source-ID. */
1426#define VTD_BF_CCMD_REG_SID_SHIFT 16
1427#define VTD_BF_CCMD_REG_SID_MASK UINT64_C(0x00000000ffff0000)
1428/** FM: Function Mask. */
1429#define VTD_BF_CCMD_REG_FM_SHIFT 32
1430#define VTD_BF_CCMD_REG_FM_MASK UINT64_C(0x0000000300000000)
1431/** R: Reserved (bits 58:34). */
1432#define VTD_BF_CCMD_REG_RSVD_58_34_SHIFT 34
1433#define VTD_BF_CCMD_REG_RSVD_58_34_MASK UINT64_C(0x07fffffc00000000)
1434/** CAIG: Context Actual Invalidation Granularity. */
1435#define VTD_BF_CCMD_REG_CAIG_SHIFT 59
1436#define VTD_BF_CCMD_REG_CAIG_MASK UINT64_C(0x1800000000000000)
1437/** CIRG: Context Invalidation Request Granularity. */
1438#define VTD_BF_CCMD_REG_CIRG_SHIFT 61
1439#define VTD_BF_CCMD_REG_CIRG_MASK UINT64_C(0x6000000000000000)
1440/** ICC: Invalidation Context Cache. */
1441#define VTD_BF_CCMD_REG_ICC_SHIFT 63
1442#define VTD_BF_CCMD_REG_ICC_MASK UINT64_C(0x8000000000000000)
1443RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_CCMD_REG_, UINT64_C(0), UINT64_MAX,
1444 (DID, SID, FM, RSVD_58_34, CAIG, CIRG, ICC));
1445
1446/** RW: Read/write mask. */
1447#define VTD_CCMD_REG_RW_MASK ( VTD_BF_CCMD_REG_DID_MASK | VTD_BF_CCMD_REG_SID_MASK \
1448 | VTD_BF_CCMD_REG_FM_MASK | VTD_BF_CCMD_REG_CIRG_MASK \
1449 | VTD_BF_CCMD_REG_ICC_MASK)
1450/** @} */
1451
1452
1453/** @name IOTLB Invalidation Register (IOTLB_REG).
1454 * In accordance with the Intel spec.
1455 * @{ */
1456/** R: Reserved (bits 31:0). */
1457#define VTD_BF_IOTLB_REG_RSVD_31_0_SHIFT 0
1458#define VTD_BF_IOTLB_REG_RSVD_31_0_MASK UINT64_C(0x00000000ffffffff)
1459/** DID: Domain-ID. */
1460#define VTD_BF_IOTLB_REG_DID_SHIFT 32
1461#define VTD_BF_IOTLB_REG_DID_MASK UINT64_C(0x0000ffff00000000)
1462/** DW: Draining Writes. */
1463#define VTD_BF_IOTLB_REG_DW_SHIFT 48
1464#define VTD_BF_IOTLB_REG_DW_MASK UINT64_C(0x0001000000000000)
1465/** DR: Draining Reads. */
1466#define VTD_BF_IOTLB_REG_DR_SHIFT 49
1467#define VTD_BF_IOTLB_REG_DR_MASK UINT64_C(0x0002000000000000)
1468/** R: Reserved (bits 56:50). */
1469#define VTD_BF_IOTLB_REG_RSVD_56_50_SHIFT 50
1470#define VTD_BF_IOTLB_REG_RSVD_56_50_MASK UINT64_C(0x01fc000000000000)
1471/** IAIG: IOTLB Actual Invalidation Granularity. */
1472#define VTD_BF_IOTLB_REG_IAIG_SHIFT 57
1473#define VTD_BF_IOTLB_REG_IAIG_MASK UINT64_C(0x0600000000000000)
1474/** R: Reserved (bit 59). */
1475#define VTD_BF_IOTLB_REG_RSVD_59_SHIFT 59
1476#define VTD_BF_IOTLB_REG_RSVD_59_MASK UINT64_C(0x0800000000000000)
1477/** IIRG: IOTLB Invalidation Request Granularity. */
1478#define VTD_BF_IOTLB_REG_IIRG_SHIFT 60
1479#define VTD_BF_IOTLB_REG_IIRG_MASK UINT64_C(0x3000000000000000)
1480/** R: Reserved (bit 62). */
1481#define VTD_BF_IOTLB_REG_RSVD_62_SHIFT 62
1482#define VTD_BF_IOTLB_REG_RSVD_62_MASK UINT64_C(0x4000000000000000)
1483/** IVT: Invalidate IOTLB. */
1484#define VTD_BF_IOTLB_REG_IVT_SHIFT 63
1485#define VTD_BF_IOTLB_REG_IVT_MASK UINT64_C(0x8000000000000000)
1486RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IOTLB_REG_, UINT64_C(0), UINT64_MAX,
1487 (RSVD_31_0, DID, DW, DR, RSVD_56_50, IAIG, RSVD_59, IIRG, RSVD_62, IVT));
1488
1489/** RW: Read/write mask. */
1490#define VTD_IOTLB_REG_RW_MASK ( VTD_BF_IOTLB_REG_DID_MASK | VTD_BF_IOTLB_REG_DW_MASK \
1491 | VTD_BF_IOTLB_REG_DR_MASK | VTD_BF_IOTLB_REG_IIRG_MASK \
1492 | VTD_BF_IOTLB_REG_IVT_MASK)
1493/** @} */
1494
1495
1496/** @name Invalidate Address Register (IVA_REG).
1497 * In accordance with the Intel spec.
1498 * @{ */
1499/** AM: Address Mask. */
1500#define VTD_BF_IVA_REG_AM_SHIFT 0
1501#define VTD_BF_IVA_REG_AM_MASK UINT64_C(0x000000000000003f)
1502/** IH: Invalidation Hint. */
1503#define VTD_BF_IVA_REG_IH_SHIFT 6
1504#define VTD_BF_IVA_REG_IH_MASK UINT64_C(0x0000000000000040)
1505/** R: Reserved (bits 11:7). */
1506#define VTD_BF_IVA_REG_RSVD_11_7_SHIFT 7
1507#define VTD_BF_IVA_REG_RSVD_11_7_MASK UINT64_C(0x0000000000000f80)
1508/** ADDR: Address. */
1509#define VTD_BF_IVA_REG_ADDR_SHIFT 12
1510#define VTD_BF_IVA_REG_ADDR_MASK UINT64_C(0xfffffffffffff000)
1511RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IVA_REG_, UINT64_C(0), UINT64_MAX,
1512 (AM, IH, RSVD_11_7, ADDR));
1513
1514/** RW: Read/write mask. */
1515#define VTD_IVA_REG_RW_MASK ( VTD_BF_IVA_REG_AM_MASK | VTD_BF_IVA_REG_IH_MASK \
1516 | VTD_BF_IVA_REG_ADDR_MASK)
1517/** @} */
1518
1519
1520/** @name Fault Status Register (FSTS_REG).
1521 * In accordance with the Intel spec.
1522 * @{ */
1523/** PFO: Primary Fault Overflow. */
1524#define VTD_BF_FSTS_REG_PFO_SHIFT 0
1525#define VTD_BF_FSTS_REG_PFO_MASK UINT32_C(0x00000001)
1526/** PPF: Primary Pending Fault. */
1527#define VTD_BF_FSTS_REG_PPF_SHIFT 1
1528#define VTD_BF_FSTS_REG_PPF_MASK UINT32_C(0x00000002)
1529/** AFO: Advanced Fault Overflow. */
1530#define VTD_BF_FSTS_REG_AFO_SHIFT 2
1531#define VTD_BF_FSTS_REG_AFO_MASK UINT32_C(0x00000004)
1532/** APF: Advanced Pending Fault. */
1533#define VTD_BF_FSTS_REG_APF_SHIFT 3
1534#define VTD_BF_FSTS_REG_APF_MASK UINT32_C(0x00000008)
1535/** IQE: Invalidation Queue Error. */
1536#define VTD_BF_FSTS_REG_IQE_SHIFT 4
1537#define VTD_BF_FSTS_REG_IQE_MASK UINT32_C(0x00000010)
1538/** ICE: Invalidation Completion Error. */
1539#define VTD_BF_FSTS_REG_ICE_SHIFT 5
1540#define VTD_BF_FSTS_REG_ICE_MASK UINT32_C(0x00000020)
1541/** ITE: Invalidation Timeout Error. */
1542#define VTD_BF_FSTS_REG_ITE_SHIFT 6
1543#define VTD_BF_FSTS_REG_ITE_MASK UINT32_C(0x00000040)
1544/** DEP: Deprecated MBZ. Reserved (bit 7). */
1545#define VTD_BF_FSTS_REG_RSVD_7_SHIFT 7
1546#define VTD_BF_FSTS_REG_RSVD_7_MASK UINT32_C(0x00000080)
1547/** FRI: Fault Record Index. */
1548#define VTD_BF_FSTS_REG_FRI_SHIFT 8
1549#define VTD_BF_FSTS_REG_FRI_MASK UINT32_C(0x0000ff00)
1550/** R: Reserved (bits 31:16). */
1551#define VTD_BF_FSTS_REG_RSVD_31_16_SHIFT 16
1552#define VTD_BF_FSTS_REG_RSVD_31_16_MASK UINT32_C(0xffff0000)
1553RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_FSTS_REG_, UINT32_C(0), UINT32_MAX,
1554 (PFO, PPF, AFO, APF, IQE, ICE, ITE, RSVD_7, FRI, RSVD_31_16));
1555
1556/** RW: Read/write mask. */
1557#define VTD_FSTS_REG_RW_MASK ( VTD_BF_FSTS_REG_PFO_MASK | VTD_BF_FSTS_REG_AFO_MASK \
1558 | VTD_BF_FSTS_REG_APF_MASK | VTD_BF_FSTS_REG_IQE_MASK \
1559 | VTD_BF_FSTS_REG_ICE_MASK | VTD_BF_FSTS_REG_ITE_MASK)
1560/** RW1C: Read-only-status, Write-1-to-clear status mask. */
1561#define VTD_FSTS_REG_RW1C_MASK ( VTD_BF_FSTS_REG_PFO_MASK | VTD_BF_FSTS_REG_AFO_MASK \
1562 | VTD_BF_FSTS_REG_APF_MASK | VTD_BF_FSTS_REG_IQE_MASK \
1563 | VTD_BF_FSTS_REG_ICE_MASK | VTD_BF_FSTS_REG_ITE_MASK)
1564/** @} */
1565
1566
1567/** @name Fault Event Control Register (FECTL_REG).
1568 * In accordance with the Intel spec.
1569 * @{ */
1570/** R: Reserved (bits 29:0). */
1571#define VTD_BF_FECTL_REG_RSVD_29_0_SHIFT 0
1572#define VTD_BF_FECTL_REG_RSVD_29_0_MASK UINT32_C(0x3fffffff)
1573/** IP: Interrupt Pending. */
1574#define VTD_BF_FECTL_REG_IP_SHIFT 30
1575#define VTD_BF_FECTL_REG_IP_MASK UINT32_C(0x40000000)
1576/** IM: Interrupt Mask. */
1577#define VTD_BF_FECTL_REG_IM_SHIFT 31
1578#define VTD_BF_FECTL_REG_IM_MASK UINT32_C(0x80000000)
1579RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_FECTL_REG_, UINT32_C(0), UINT32_MAX,
1580 (RSVD_29_0, IP, IM));
1581
1582/** RW: Read/write mask. */
1583#define VTD_FECTL_REG_RW_MASK VTD_BF_FECTL_REG_IM_MASK
1584/** @} */
1585
1586
1587/** @name Fault Event Data Register (FEDATA_REG).
1588 * In accordance with the Intel spec.
1589 * @{ */
1590/** IMD: Interrupt Message Data. */
1591#define VTD_BF_FEDATA_REG_IMD_SHIFT 0
1592#define VTD_BF_FEDATA_REG_IMD_MASK UINT32_C(0x0000ffff)
1593/** R: Reserved (bits 31:16). VT-d specs. prior to 2021 had EIMD here. */
1594#define VTD_BF_FEDATA_REG_RSVD_31_16_SHIFT 16
1595#define VTD_BF_FEDATA_REG_RSVD_31_16_MASK UINT32_C(0xffff0000)
1596RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_FEDATA_REG_, UINT32_C(0), UINT32_MAX,
1597 (IMD, RSVD_31_16));
1598
1599/** RW: Read/write mask, see 5.1.6 "Remapping Hardware Event Interrupt
1600 * Programming". */
1601#define VTD_FEDATA_REG_RW_MASK UINT32_C(0x000001ff)
1602/** @} */
1603
1604
1605/** @name Fault Event Address Register (FEADDR_REG).
1606 * In accordance with the Intel spec.
1607 * @{ */
1608/** R: Reserved (bits 1:0). */
1609#define VTD_BF_FEADDR_REG_RSVD_1_0_SHIFT 0
1610#define VTD_BF_FEADDR_REG_RSVD_1_0_MASK UINT32_C(0x00000003)
1611/** MA: Message Address. */
1612#define VTD_BF_FEADDR_REG_MA_SHIFT 2
1613#define VTD_BF_FEADDR_REG_MA_MASK UINT32_C(0xfffffffc)
1614RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_FEADDR_REG_, UINT32_C(0), UINT32_MAX,
1615 (RSVD_1_0, MA));
1616
1617/** RW: Read/write mask. */
1618#define VTD_FEADDR_REG_RW_MASK VTD_BF_FEADDR_REG_MA_MASK
1619/** @} */
1620
1621
1622/** @name Fault Event Upper Address Register (FEUADDR_REG).
1623 * In accordance with the Intel spec.
1624 * @{ */
1625/** MUA: Message Upper Address. */
1626#define VTD_BF_FEUADDR_REG_MA_SHIFT 0
1627#define VTD_BF_FEUADDR_REG_MA_MASK UINT32_C(0xffffffff)
1628
1629/** RW: Read/write mask. */
1630#define VTD_FEUADDR_REG_RW_MASK VTD_BF_FEUADDR_REG_MA_MASK
1631/** @} */
1632
1633
1634/** @name Fault Recording Register (FRCD_REG).
1635 * In accordance with the Intel spec.
1636 * @{ */
1637/** R: Reserved (bits 11:0). */
1638#define VTD_BF_0_FRCD_REG_RSVD_11_0_SHIFT 0
1639#define VTD_BF_0_FRCD_REG_RSVD_11_0_MASK UINT64_C(0x0000000000000fff)
1640/** FI: Fault Info. */
1641#define VTD_BF_0_FRCD_REG_FI_SHIFT 12
1642#define VTD_BF_0_FRCD_REG_FI_MASK UINT64_C(0xfffffffffffff000)
1643RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_FRCD_REG_, UINT64_C(0), UINT64_MAX,
1644 (RSVD_11_0, FI));
1645
1646/** SID: Source Identifier. */
1647#define VTD_BF_1_FRCD_REG_SID_SHIFT 0
1648#define VTD_BF_1_FRCD_REG_SID_MASK UINT64_C(0x000000000000ffff)
1649/** R: Reserved (bits 27:16). */
1650#define VTD_BF_1_FRCD_REG_RSVD_27_16_SHIFT 16
1651#define VTD_BF_1_FRCD_REG_RSVD_27_16_MASK UINT64_C(0x000000000fff0000)
1652/** T2: Type bit 2. */
1653#define VTD_BF_1_FRCD_REG_T2_SHIFT 28
1654#define VTD_BF_1_FRCD_REG_T2_MASK UINT64_C(0x0000000010000000)
1655/** PRIV: Privilege Mode. */
1656#define VTD_BF_1_FRCD_REG_PRIV_SHIFT 29
1657#define VTD_BF_1_FRCD_REG_PRIV_MASK UINT64_C(0x0000000020000000)
1658/** EXE: Execute Permission Requested. */
1659#define VTD_BF_1_FRCD_REG_EXE_SHIFT 30
1660#define VTD_BF_1_FRCD_REG_EXE_MASK UINT64_C(0x0000000040000000)
1661/** PP: PASID Present. */
1662#define VTD_BF_1_FRCD_REG_PP_SHIFT 31
1663#define VTD_BF_1_FRCD_REG_PP_MASK UINT64_C(0x0000000080000000)
1664/** FR: Fault Reason. */
1665#define VTD_BF_1_FRCD_REG_FR_SHIFT 32
1666#define VTD_BF_1_FRCD_REG_FR_MASK UINT64_C(0x000000ff00000000)
1667/** PV: PASID Value. */
1668#define VTD_BF_1_FRCD_REG_PV_SHIFT 40
1669#define VTD_BF_1_FRCD_REG_PV_MASK UINT64_C(0x0fffff0000000000)
1670/** AT: Address Type. */
1671#define VTD_BF_1_FRCD_REG_AT_SHIFT 60
1672#define VTD_BF_1_FRCD_REG_AT_MASK UINT64_C(0x3000000000000000)
1673/** T1: Type bit 1. */
1674#define VTD_BF_1_FRCD_REG_T1_SHIFT 62
1675#define VTD_BF_1_FRCD_REG_T1_MASK UINT64_C(0x4000000000000000)
1676/** F: Fault. */
1677#define VTD_BF_1_FRCD_REG_F_SHIFT 63
1678#define VTD_BF_1_FRCD_REG_F_MASK UINT64_C(0x8000000000000000)
1679RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_FRCD_REG_, UINT64_C(0), UINT64_MAX,
1680 (SID, RSVD_27_16, T2, PRIV, EXE, PP, FR, PV, AT, T1, F));
1681
1682/** RW: Read/write mask. */
1683#define VTD_FRCD_REG_LO_RW_MASK UINT64_C(0)
1684#define VTD_FRCD_REG_HI_RW_MASK VTD_BF_1_FRCD_REG_F_MASK
1685/** RW1C: Read-only-status, Write-1-to-clear status mask. */
1686#define VTD_FRCD_REG_LO_RW1C_MASK UINT64_C(0)
1687#define VTD_FRCD_REG_HI_RW1C_MASK VTD_BF_1_FRCD_REG_F_MASK
1688/** @} */
1689
1690
1691/**
1692 * VT-d faulted address translation request types (FRCD_REG::T2).
1693 * In accordance with the Intel spec.
1694 */
1695typedef enum VTDREQTYPE
1696{
1697 VTDREQTYPE_WRITE = 0, /**< Memory access write request. */
1698 VTDREQTYPE_PAGE, /**< Page translation request. */
1699 VTDREQTYPE_READ, /**< Memory access read request. */
1700 VTDREQTYPE_ATOMIC_OP /**< Memory access atomic operation. */
1701} VTDREQTYPE;
1702/** Pointer to a VTDREQTYPE. */
1703typedef VTDREQTYPE *PVTDREQTYPE;
1704
1705
1706/** @name Advanced Fault Log Register (AFLOG_REG).
1707 * In accordance with the Intel spec.
1708 * @{ */
1709/** R: Reserved (bits 8:0). */
1710#define VTD_BF_0_AFLOG_REG_RSVD_8_0_SHIFT 0
1711#define VTD_BF_0_AFLOG_REG_RSVD_8_0_MASK UINT64_C(0x00000000000001ff)
1712/** FLS: Fault Log Size. */
1713#define VTD_BF_0_AFLOG_REG_FLS_SHIFT 9
1714#define VTD_BF_0_AFLOG_REG_FLS_MASK UINT64_C(0x0000000000000e00)
1715/** FLA: Fault Log Address. */
1716#define VTD_BF_0_AFLOG_REG_FLA_SHIFT 12
1717#define VTD_BF_0_AFLOG_REG_FLA_MASK UINT64_C(0xfffffffffffff000)
1718RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_AFLOG_REG_, UINT64_C(0), UINT64_MAX,
1719 (RSVD_8_0, FLS, FLA));
1720
1721/** RW: Read/write mask. */
1722#define VTD_AFLOG_REG_RW_MASK (VTD_BF_0_AFLOG_REG_FLS_MASK | VTD_BF_0_AFLOG_REG_FLA_MASK)
1723/** @} */
1724
1725
1726/** @name Protected Memory Enable Register (PMEN_REG).
1727 * In accordance with the Intel spec.
1728 * @{ */
1729/** PRS: Protected Region Status. */
1730#define VTD_BF_PMEN_REG_PRS_SHIFT 0
1731#define VTD_BF_PMEN_REG_PRS_MASK UINT32_C(0x00000001)
1732/** R: Reserved (bits 30:1). */
1733#define VTD_BF_PMEN_REG_RSVD_30_1_SHIFT 1
1734#define VTD_BF_PMEN_REG_RSVD_30_1_MASK UINT32_C(0x7ffffffe)
1735/** EPM: Enable Protected Memory. */
1736#define VTD_BF_PMEN_REG_EPM_SHIFT 31
1737#define VTD_BF_PMEN_REG_EPM_MASK UINT32_C(0x80000000)
1738RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_PMEN_REG_, UINT32_C(0), UINT32_MAX,
1739 (PRS, RSVD_30_1, EPM));
1740
1741/** RW: Read/write mask. */
1742#define VTD_PMEN_REG_RW_MASK VTD_BF_PMEN_REG_EPM_MASK
1743/** @} */
1744
1745
1746/** @name Invalidation Queue Head Register (IQH_REG).
1747 * In accordance with the Intel spec.
1748 * @{ */
1749/** R: Reserved (bits 3:0). */
1750#define VTD_BF_IQH_REG_RSVD_3_0_SHIFT 0
1751#define VTD_BF_IQH_REG_RSVD_3_0_MASK UINT64_C(0x000000000000000f)
1752/** QH: Queue Head. */
1753#define VTD_BF_IQH_REG_QH_SHIFT 4
1754#define VTD_BF_IQH_REG_QH_MASK UINT64_C(0x000000000007fff0)
1755/** R: Reserved (bits 63:19). */
1756#define VTD_BF_IQH_REG_RSVD_63_19_SHIFT 19
1757#define VTD_BF_IQH_REG_RSVD_63_19_MASK UINT64_C(0xfffffffffff80000)
1758RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IQH_REG_, UINT64_C(0), UINT64_MAX,
1759 (RSVD_3_0, QH, RSVD_63_19));
1760
1761/** RW: Read/write mask. */
1762#define VTD_IQH_REG_RW_MASK UINT64_C(0x0)
1763/** @} */
1764
1765
1766/** @name Invalidation Queue Tail Register (IQT_REG).
1767 * In accordance with the Intel spec.
1768 * @{ */
1769/** R: Reserved (bits 3:0). */
1770#define VTD_BF_IQT_REG_RSVD_3_0_SHIFT 0
1771#define VTD_BF_IQT_REG_RSVD_3_0_MASK UINT64_C(0x000000000000000f)
1772/** QH: Queue Tail. */
1773#define VTD_BF_IQT_REG_QT_SHIFT 4
1774#define VTD_BF_IQT_REG_QT_MASK UINT64_C(0x000000000007fff0)
1775/** R: Reserved (bits 63:19). */
1776#define VTD_BF_IQT_REG_RSVD_63_19_SHIFT 19
1777#define VTD_BF_IQT_REG_RSVD_63_19_MASK UINT64_C(0xfffffffffff80000)
1778RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IQT_REG_, UINT64_C(0), UINT64_MAX,
1779 (RSVD_3_0, QT, RSVD_63_19));
1780
1781/** RW: Read/write mask. */
1782#define VTD_IQT_REG_RW_MASK VTD_BF_IQT_REG_QT_MASK
1783/** @} */
1784
1785
1786/** @name Invalidation Queue Address Register (IQA_REG).
1787 * In accordance with the Intel spec.
1788 * @{ */
1789/** QS: Queue Size. */
1790#define VTD_BF_IQA_REG_QS_SHIFT 0
1791#define VTD_BF_IQA_REG_QS_MASK UINT64_C(0x0000000000000007)
1792/** R: Reserved (bits 10:3). */
1793#define VTD_BF_IQA_REG_RSVD_10_3_SHIFT 3
1794#define VTD_BF_IQA_REG_RSVD_10_3_MASK UINT64_C(0x00000000000007f8)
1795/** DW: Descriptor Width. */
1796#define VTD_BF_IQA_REG_DW_SHIFT 11
1797#define VTD_BF_IQA_REG_DW_MASK UINT64_C(0x0000000000000800)
1798/** IQA: Invalidation Queue Base Address. */
1799#define VTD_BF_IQA_REG_IQA_SHIFT 12
1800#define VTD_BF_IQA_REG_IQA_MASK UINT64_C(0xfffffffffffff000)
1801RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IQA_REG_, UINT64_C(0), UINT64_MAX,
1802 (QS, RSVD_10_3, DW, IQA));
1803
1804/** RW: Read/write mask. */
1805#define VTD_IQA_REG_RW_MASK ( VTD_BF_IQA_REG_QS_MASK | VTD_BF_IQA_REG_DW_MASK \
1806 | VTD_BF_IQA_REG_IQA_MASK)
1807/** DW: 128-bit descriptor. */
1808#define VTD_IQA_REG_DW_128_BIT 0
1809/** DW: 256-bit descriptor. */
1810#define VTD_IQA_REG_DW_256_BIT 1
1811/** @} */
1812
1813
1814/** @name Invalidation Completion Status Register (ICS_REG).
1815 * In accordance with the Intel spec.
1816 * @{ */
1817/** IWC: Invalidation Wait Descriptor Complete. */
1818#define VTD_BF_ICS_REG_IWC_SHIFT 0
1819#define VTD_BF_ICS_REG_IWC_MASK UINT32_C(0x00000001)
1820/** R: Reserved (bits 31:1). */
1821#define VTD_BF_ICS_REG_RSVD_31_1_SHIFT 1
1822#define VTD_BF_ICS_REG_RSVD_31_1_MASK UINT32_C(0xfffffffe)
1823RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_ICS_REG_, UINT32_C(0), UINT32_MAX,
1824 (IWC, RSVD_31_1));
1825
1826/** RW: Read/write mask. */
1827#define VTD_ICS_REG_RW_MASK VTD_BF_ICS_REG_IWC_MASK
1828/** RW1C: Read-only-status, Write-1-to-clear status mask. */
1829#define VTD_ICS_REG_RW1C_MASK VTD_BF_ICS_REG_IWC_MASK
1830/** @} */
1831
1832
1833/** @name Invalidation Event Control Register (IECTL_REG).
1834 * In accordance with the Intel spec.
1835 * @{ */
1836/** R: Reserved (bits 29:0). */
1837#define VTD_BF_IECTL_REG_RSVD_29_0_SHIFT 0
1838#define VTD_BF_IECTL_REG_RSVD_29_0_MASK UINT32_C(0x3fffffff)
1839/** IP: Interrupt Pending. */
1840#define VTD_BF_IECTL_REG_IP_SHIFT 30
1841#define VTD_BF_IECTL_REG_IP_MASK UINT32_C(0x40000000)
1842/** IM: Interrupt Mask. */
1843#define VTD_BF_IECTL_REG_IM_SHIFT 31
1844#define VTD_BF_IECTL_REG_IM_MASK UINT32_C(0x80000000)
1845RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IECTL_REG_, UINT32_C(0), UINT32_MAX,
1846 (RSVD_29_0, IP, IM));
1847
1848/** RW: Read/write mask. */
1849#define VTD_IECTL_REG_RW_MASK VTD_BF_IECTL_REG_IM_MASK
1850/** @} */
1851
1852
1853/** @name Invalidation Event Data Register (IEDATA_REG).
1854 * In accordance with the Intel spec.
1855 * @{ */
1856/** IMD: Interrupt Message Data. */
1857#define VTD_BF_IEDATA_REG_IMD_SHIFT 0
1858#define VTD_BF_IEDATA_REG_IMD_MASK UINT32_C(0x0000ffff)
1859/** R: Reserved (bits 31:16). VT-d specs. prior to 2021 had EIMD here. */
1860#define VTD_BF_IEDATA_REG_RSVD_31_16_SHIFT 16
1861#define VTD_BF_IEDATA_REG_RSVD_31_16_MASK UINT32_C(0xffff0000)
1862RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IEDATA_REG_, UINT32_C(0), UINT32_MAX,
1863 (IMD, RSVD_31_16));
1864
1865/** RW: Read/write mask, see 5.1.6 "Remapping Hardware Event Interrupt
1866 * Programming". */
1867#define VTD_IEDATA_REG_RW_MASK UINT32_C(0x000001ff)
1868/** @} */
1869
1870
1871/** @name Invalidation Event Address Register (IEADDR_REG).
1872 * In accordance with the Intel spec.
1873 * @{ */
1874/** R: Reserved (bits 1:0). */
1875#define VTD_BF_IEADDR_REG_RSVD_1_0_SHIFT 0
1876#define VTD_BF_IEADDR_REG_RSVD_1_0_MASK UINT32_C(0x00000003)
1877/** MA: Message Address. */
1878#define VTD_BF_IEADDR_REG_MA_SHIFT 2
1879#define VTD_BF_IEADDR_REG_MA_MASK UINT32_C(0xfffffffc)
1880RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IEADDR_REG_, UINT32_C(0), UINT32_MAX,
1881 (RSVD_1_0, MA));
1882
1883/** RW: Read/write mask. */
1884#define VTD_IEADDR_REG_RW_MASK VTD_BF_IEADDR_REG_MA_MASK
1885/** @} */
1886
1887
1888/** @name Invalidation Event Upper Address Register (IEUADDR_REG).
1889 * @{ */
1890/** MUA: Message Upper Address. */
1891#define VTD_BF_IEUADDR_REG_MUA_SHIFT 0
1892#define VTD_BF_IEUADDR_REG_MUA_MASK UINT32_C(0xffffffff)
1893
1894/** RW: Read/write mask. */
1895#define VTD_IEUADDR_REG_RW_MASK VTD_BF_IEUADDR_REG_MUA_MASK
1896/** @} */
1897
1898
1899/** @name Invalidation Queue Error Record Register (IQERCD_REG).
1900 * In accordance with the Intel spec.
1901 * @{ */
1902/** IQEI: Invalidation Queue Error Info. */
1903#define VTD_BF_IQERCD_REG_IQEI_SHIFT 0
1904#define VTD_BF_IQERCD_REG_IQEI_MASK UINT64_C(0x000000000000000f)
1905/** R: Reserved (bits 31:4). */
1906#define VTD_BF_IQERCD_REG_RSVD_31_4_SHIFT 4
1907#define VTD_BF_IQERCD_REG_RSVD_31_4_MASK UINT64_C(0x00000000fffffff0)
1908/** ITESID: Invalidation Timeout Error Source Identifier. */
1909#define VTD_BF_IQERCD_REG_ITESID_SHIFT 32
1910#define VTD_BF_IQERCD_REG_ITESID_MASK UINT64_C(0x0000ffff00000000)
1911/** ICESID: Invalidation Completion Error Source Identifier. */
1912#define VTD_BF_IQERCD_REG_ICESID_SHIFT 48
1913#define VTD_BF_IQERCD_REG_ICESID_MASK UINT64_C(0xffff000000000000)
1914RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IQERCD_REG_, UINT64_C(0), UINT64_MAX,
1915 (IQEI, RSVD_31_4, ITESID, ICESID));
1916
1917/** RW: Read/write mask. */
1918#define VTD_IQERCD_REG_RW_MASK UINT64_C(0)
1919
1920/** Invalidation Queue Error Information. */
1921typedef enum VTDIQEI
1922{
1923 VTDIQEI_INFO_NOT_AVAILABLE,
1924 VTDIQEI_INVALID_TAIL_PTR,
1925 VTDIQEI_FETCH_DESCRIPTOR_ERR,
1926 VTDIQEI_INVALID_DESCRIPTOR_TYPE,
1927 VTDIQEI_RSVD_FIELD_VIOLATION,
1928 VTDIQEI_INVALID_DESCRIPTOR_WIDTH,
1929 VTDIQEI_QUEUE_TAIL_MISALIGNED,
1930 VTDIQEI_INVALID_TTM
1931} VTDIQEI;
1932/** @} */
1933
1934
1935/** @name Interrupt Remapping Table Address Register (IRTA_REG).
1936 * In accordance with the Intel spec.
1937 * @{ */
1938/** S: Size. */
1939#define VTD_BF_IRTA_REG_S_SHIFT 0
1940#define VTD_BF_IRTA_REG_S_MASK UINT64_C(0x000000000000000f)
1941/** R: Reserved (bits 10:4). */
1942#define VTD_BF_IRTA_REG_RSVD_10_4_SHIFT 4
1943#define VTD_BF_IRTA_REG_RSVD_10_4_MASK UINT64_C(0x00000000000007f0)
1944/** EIME: Extended Interrupt Mode Enable. */
1945#define VTD_BF_IRTA_REG_EIME_SHIFT 11
1946#define VTD_BF_IRTA_REG_EIME_MASK UINT64_C(0x0000000000000800)
1947/** IRTA: Interrupt Remapping Table Address. */
1948#define VTD_BF_IRTA_REG_IRTA_SHIFT 12
1949#define VTD_BF_IRTA_REG_IRTA_MASK UINT64_C(0xfffffffffffff000)
1950RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IRTA_REG_, UINT64_C(0), UINT64_MAX,
1951 (S, RSVD_10_4, EIME, IRTA));
1952
1953/** RW: Read/write mask. */
1954#define VTD_IRTA_REG_RW_MASK ( VTD_BF_IRTA_REG_S_MASK | VTD_BF_IRTA_REG_EIME_MASK \
1955 | VTD_BF_IRTA_REG_IRTA_MASK)
1956/** IRTA_REG: Get number of interrupt entries. */
1957#define VTD_IRTA_REG_GET_ENTRY_COUNT(a) (UINT32_C(1) << (1 + ((a) & VTD_BF_IRTA_REG_S_MASK)))
1958/** @} */
1959
1960
1961/** @name Page Request Queue Head Register (PQH_REG).
1962 * In accordance with the Intel spec.
1963 * @{ */
1964/** R: Reserved (bits 4:0). */
1965#define VTD_BF_PQH_REG_RSVD_4_0_SHIFT 0
1966#define VTD_BF_PQH_REG_RSVD_4_0_MASK UINT64_C(0x000000000000001f)
1967/** PQH: Page Queue Head. */
1968#define VTD_BF_PQH_REG_PQH_SHIFT 5
1969#define VTD_BF_PQH_REG_PQH_MASK UINT64_C(0x000000000007ffe0)
1970/** R: Reserved (bits 63:19). */
1971#define VTD_BF_PQH_REG_RSVD_63_19_SHIFT 19
1972#define VTD_BF_PQH_REG_RSVD_63_19_MASK UINT64_C(0xfffffffffff80000)
1973RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_PQH_REG_, UINT64_C(0), UINT64_MAX,
1974 (RSVD_4_0, PQH, RSVD_63_19));
1975
1976/** RW: Read/write mask. */
1977#define VTD_PQH_REG_RW_MASK VTD_BF_PQH_REG_PQH_MASK
1978/** @} */
1979
1980
1981/** @name Page Request Queue Tail Register (PQT_REG).
1982 * In accordance with the Intel spec.
1983 * @{ */
1984/** R: Reserved (bits 4:0). */
1985#define VTD_BF_PQT_REG_RSVD_4_0_SHIFT 0
1986#define VTD_BF_PQT_REG_RSVD_4_0_MASK UINT64_C(0x000000000000001f)
1987/** PQT: Page Queue Tail. */
1988#define VTD_BF_PQT_REG_PQT_SHIFT 5
1989#define VTD_BF_PQT_REG_PQT_MASK UINT64_C(0x000000000007ffe0)
1990/** R: Reserved (bits 63:19). */
1991#define VTD_BF_PQT_REG_RSVD_63_19_SHIFT 19
1992#define VTD_BF_PQT_REG_RSVD_63_19_MASK UINT64_C(0xfffffffffff80000)
1993RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_PQT_REG_, UINT64_C(0), UINT64_MAX,
1994 (RSVD_4_0, PQT, RSVD_63_19));
1995
1996/** RW: Read/write mask. */
1997#define VTD_PQT_REG_RW_MASK VTD_BF_PQT_REG_PQT_MASK
1998/** @} */
1999
2000
2001/** @name Page Request Queue Address Register (PQA_REG).
2002 * In accordance with the Intel spec.
2003 * @{ */
2004/** PQS: Page Queue Size. */
2005#define VTD_BF_PQA_REG_PQS_SHIFT 0
2006#define VTD_BF_PQA_REG_PQS_MASK UINT64_C(0x0000000000000007)
2007/** R: Reserved bits (11:3). */
2008#define VTD_BF_PQA_REG_RSVD_11_3_SHIFT 3
2009#define VTD_BF_PQA_REG_RSVD_11_3_MASK UINT64_C(0x0000000000000ff8)
2010/** PQA: Page Request Queue Base Address. */
2011#define VTD_BF_PQA_REG_PQA_SHIFT 12
2012#define VTD_BF_PQA_REG_PQA_MASK UINT64_C(0xfffffffffffff000)
2013RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_PQA_REG_, UINT64_C(0), UINT64_MAX,
2014 (PQS, RSVD_11_3, PQA));
2015
2016/** RW: Read/write mask. */
2017#define VTD_PQA_REG_RW_MASK (VTD_BF_PQA_REG_PQS_MASK | VTD_BF_PQA_REG_PQA_MASK)
2018/** @} */
2019
2020
2021/** @name Page Request Status Register (PRS_REG).
2022 * In accordance with the Intel spec.
2023 * @{ */
2024/** PPR: Pending Page Request. */
2025#define VTD_BF_PRS_REG_PPR_SHIFT 0
2026#define VTD_BF_PRS_REG_PPR_MASK UINT64_C(0x00000001)
2027/** PRO: Page Request Overflow. */
2028#define VTD_BF_PRS_REG_PRO_SHIFT 1
2029#define VTD_BF_PRS_REG_PRO_MASK UINT64_C(0x00000002)
2030/** R: Reserved (bits 31:2). */
2031#define VTD_BF_PRS_REG_RSVD_31_2_SHIFT 2
2032#define VTD_BF_PRS_REG_RSVD_31_2_MASK UINT64_C(0xfffffffc)
2033RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_PRS_REG_, UINT32_C(0), UINT32_MAX,
2034 (PPR, PRO, RSVD_31_2));
2035
2036/** RW: Read/write mask. */
2037#define VTD_PRS_REG_RW_MASK (VTD_BF_PRS_REG_PPR_MASK | VTD_BF_PRS_REG_PRO_MASK)
2038/** RW1C: Read-only-status, Write-1-to-clear status mask. */
2039#define VTD_PRS_REG_RW1C_MASK (VTD_BF_PRS_REG_PPR_MASK | VTD_BF_PRS_REG_PRO_MASK)
2040/** @} */
2041
2042
2043/** @name Page Request Event Control Register (PECTL_REG).
2044 * In accordance with the Intel spec.
2045 * @{ */
2046/** R: Reserved (bits 29:0). */
2047#define VTD_BF_PECTL_REG_RSVD_29_0_SHIFT 0
2048#define VTD_BF_PECTL_REG_RSVD_29_0_MASK UINT32_C(0x3fffffff)
2049/** IP: Interrupt Pending. */
2050#define VTD_BF_PECTL_REG_IP_SHIFT 30
2051#define VTD_BF_PECTL_REG_IP_MASK UINT32_C(0x40000000)
2052/** IM: Interrupt Mask. */
2053#define VTD_BF_PECTL_REG_IM_SHIFT 31
2054#define VTD_BF_PECTL_REG_IM_MASK UINT32_C(0x80000000)
2055RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_PECTL_REG_, UINT32_C(0), UINT32_MAX,
2056 (RSVD_29_0, IP, IM));
2057
2058/** RW: Read/write mask. */
2059#define VTD_PECTL_REG_RW_MASK VTD_BF_PECTL_REG_IM_MASK
2060/** @} */
2061
2062
2063/** @name Page Request Event Data Register (PEDATA_REG).
2064 * In accordance with the Intel spec.
2065 * @{ */
2066/** IMD: Interrupt Message Data. */
2067#define VTD_BF_PEDATA_REG_IMD_SHIFT 0
2068#define VTD_BF_PEDATA_REG_IMD_MASK UINT32_C(0x0000ffff)
2069/** R: Reserved (bits 31:16). VT-d specs. prior to 2021 had EIMD here. */
2070#define VTD_BF_PEDATA_REG_RSVD_31_16_SHIFT 16
2071#define VTD_BF_PEDATA_REG_RSVD_31_16_MASK UINT32_C(0xffff0000)
2072RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_PEDATA_REG_, UINT32_C(0), UINT32_MAX,
2073 (IMD, RSVD_31_16));
2074
2075/** RW: Read/write mask, see 5.1.6 "Remapping Hardware Event Interrupt
2076 * Programming". */
2077#define VTD_PEDATA_REG_RW_MASK UINT32_C(0x000001ff)
2078/** @} */
2079
2080
2081/** @name Page Request Event Address Register (PEADDR_REG).
2082 * In accordance with the Intel spec.
2083 * @{ */
2084/** R: Reserved (bits 1:0). */
2085#define VTD_BF_PEADDR_REG_RSVD_1_0_SHIFT 0
2086#define VTD_BF_PEADDR_REG_RSVD_1_0_MASK UINT32_C(0x00000003)
2087/** MA: Message Address. */
2088#define VTD_BF_PEADDR_REG_MA_SHIFT 2
2089#define VTD_BF_PEADDR_REG_MA_MASK UINT32_C(0xfffffffc)
2090RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_PEADDR_REG_, UINT32_C(0), UINT32_MAX,
2091 (RSVD_1_0, MA));
2092
2093/** RW: Read/write mask. */
2094#define VTD_PEADDR_REG_RW_MASK VTD_BF_PEADDR_REG_MA_MASK
2095/** @} */
2096
2097
2098
2099/** @name Page Request Event Upper Address Register (PEUADDR_REG).
2100 * In accordance with the Intel spec.
2101 * @{ */
2102/** MA: Message Address. */
2103#define VTD_BF_PEUADDR_REG_MUA_SHIFT 0
2104#define VTD_BF_PEUADDR_REG_MUA_MASK UINT32_C(0xffffffff)
2105
2106/** RW: Read/write mask. */
2107#define VTD_PEUADDR_REG_RW_MASK VTD_BF_PEUADDR_REG_MUA_MASK
2108/** @} */
2109
2110
2111/** @name MTRR Capability Register (MTRRCAP_REG).
2112 * In accordance with the Intel spec.
2113 * @{ */
2114/** VCNT: Variable MTRR Count. */
2115#define VTD_BF_MTRRCAP_REG_VCNT_SHIFT 0
2116#define VTD_BF_MTRRCAP_REG_VCNT_MASK UINT64_C(0x00000000000000ff)
2117/** FIX: Fixed range MTRRs Supported. */
2118#define VTD_BF_MTRRCAP_REG_FIX_SHIFT 8
2119#define VTD_BF_MTRRCAP_REG_FIX_MASK UINT64_C(0x0000000000000100)
2120/** R: Reserved (bit 9). */
2121#define VTD_BF_MTRRCAP_REG_RSVD_9_SHIFT 9
2122#define VTD_BF_MTRRCAP_REG_RSVD_9_MASK UINT64_C(0x0000000000000200)
2123/** WC: Write Combining. */
2124#define VTD_BF_MTRRCAP_REG_WC_SHIFT 10
2125#define VTD_BF_MTRRCAP_REG_WC_MASK UINT64_C(0x0000000000000400)
2126/** R: Reserved (bits 63:11). */
2127#define VTD_BF_MTRRCAP_REG_RSVD_63_11_SHIFT 11
2128#define VTD_BF_MTRRCAP_REG_RSVD_63_11_MASK UINT64_C(0xfffffffffffff800)
2129RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_MTRRCAP_REG_, UINT64_C(0), UINT64_MAX,
2130 (VCNT, FIX, RSVD_9, WC, RSVD_63_11));
2131
2132/** RW: Read/write mask. */
2133#define VTD_MTRRCAP_REG_RW_MASK UINT64_C(0)
2134/** @} */
2135
2136
2137/** @name MTRR Default Type Register (MTRRDEF_REG).
2138 * In accordance with the Intel spec.
2139 * @{ */
2140/** TYPE: Default Memory Type. */
2141#define VTD_BF_MTRRDEF_REG_TYPE_SHIFT 0
2142#define VTD_BF_MTRRDEF_REG_TYPE_MASK UINT64_C(0x00000000000000ff)
2143/** R: Reserved (bits 9:8). */
2144#define VTD_BF_MTRRDEF_REG_RSVD_9_8_SHIFT 8
2145#define VTD_BF_MTRRDEF_REG_RSVD_9_8_MASK UINT64_C(0x0000000000000300)
2146/** FE: Fixed Range MTRR Enable. */
2147#define VTD_BF_MTRRDEF_REG_FE_SHIFT 10
2148#define VTD_BF_MTRRDEF_REG_FE_MASK UINT64_C(0x0000000000000400)
2149/** E: MTRR Enable. */
2150#define VTD_BF_MTRRDEF_REG_E_SHIFT 11
2151#define VTD_BF_MTRRDEF_REG_E_MASK UINT64_C(0x0000000000000800)
2152/** R: Reserved (bits 63:12). */
2153#define VTD_BF_MTRRDEF_REG_RSVD_63_12_SHIFT 12
2154#define VTD_BF_MTRRDEF_REG_RSVD_63_12_MASK UINT64_C(0xfffffffffffff000)
2155RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_MTRRDEF_REG_, UINT64_C(0), UINT64_MAX,
2156 (TYPE, RSVD_9_8, FE, E, RSVD_63_12));
2157
2158/** RW: Read/write mask. */
2159#define VTD_MTRRDEF_REG_RW_MASK ( VTD_BF_MTRRDEF_REG_TYPE_MASK | VTD_BF_MTRRDEF_REG_FE_MASK \
2160 | VTD_BF_MTRRDEF_REG_E_MASK)
2161/** @} */
2162
2163
2164/** @name Virtual Command Capability Register (VCCAP_REG).
2165 * In accordance with the Intel spec.
2166 * @{ */
2167/** PAS: PASID Support. */
2168#define VTD_BF_VCCAP_REG_PAS_SHIFT 0
2169#define VTD_BF_VCCAP_REG_PAS_MASK UINT64_C(0x0000000000000001)
2170/** R: Reserved (bits 63:1). */
2171#define VTD_BF_VCCAP_REG_RSVD_63_1_SHIFT 1
2172#define VTD_BF_VCCAP_REG_RSVD_63_1_MASK UINT64_C(0xfffffffffffffffe)
2173RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_VCCAP_REG_, UINT64_C(0), UINT64_MAX,
2174 (PAS, RSVD_63_1));
2175
2176/** RW: Read/write mask. */
2177#define VTD_VCCAP_REG_RW_MASK UINT64_C(0)
2178/** @} */
2179
2180
2181/** @name Virtual Command Extended Operand Register (VCMD_EO_REG).
2182 * In accordance with the Intel spec.
2183 * @{ */
2184/** OB: Operand B. */
2185#define VTD_BF_VCMD_EO_REG_OB_SHIFT 0
2186#define VTD_BF_VCMD_EO_REG_OB_MASK UINT32_C(0xffffffffffffffff)
2187
2188/** RW: Read/write mask. */
2189#define VTD_VCMD_EO_REG_RW_MASK VTD_BF_VCMD_EO_REG_OB_MASK
2190/** @} */
2191
2192
2193/** @name Virtual Command Register (VCMD_REG).
2194 * In accordance with the Intel spec.
2195 * @{ */
2196/** CMD: Command. */
2197#define VTD_BF_VCMD_REG_CMD_SHIFT 0
2198#define VTD_BF_VCMD_REG_CMD_MASK UINT64_C(0x00000000000000ff)
2199/** OP: Operand. */
2200#define VTD_BF_VCMD_REG_OP_SHIFT 8
2201#define VTD_BF_VCMD_REG_OP_MASK UINT64_C(0xffffffffffffff00)
2202RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_VCMD_REG_, UINT64_C(0), UINT64_MAX,
2203 (CMD, OP));
2204
2205/** RW: Read/write mask. */
2206#define VTD_VCMD_REG_RW_MASK (VTD_BF_VCMD_REG_CMD_MASK | VTD_BF_VCMD_REG_OP_MASK)
2207/** @} */
2208
2209
2210/** @name Virtual Command Response Register (VCRSP_REG).
2211 * In accordance with the Intel spec.
2212 * @{ */
2213/** IP: In Progress. */
2214#define VTD_BF_VCRSP_REG_IP_SHIFT 0
2215#define VTD_BF_VCRSP_REG_IP_MASK UINT64_C(0x0000000000000001)
2216/** SC: Status Code. */
2217#define VTD_BF_VCRSP_REG_SC_SHIFT 1
2218#define VTD_BF_VCRSP_REG_SC_MASK UINT64_C(0x0000000000000006)
2219/** R: Reserved (bits 7:3). */
2220#define VTD_BF_VCRSP_REG_RSVD_7_3_SHIFT 3
2221#define VTD_BF_VCRSP_REG_RSVD_7_3_MASK UINT64_C(0x00000000000000f8)
2222/** RSLT: Result. */
2223#define VTD_BF_VCRSP_REG_RSLT_SHIFT 8
2224#define VTD_BF_VCRSP_REG_RSLT_MASK UINT64_C(0xffffffffffffff00)
2225RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_VCRSP_REG_, UINT64_C(0), UINT64_MAX,
2226 (IP, SC, RSVD_7_3, RSLT));
2227
2228/** RW: Read/write mask. */
2229#define VTD_VCRSP_REG_RW_MASK UINT64_C(0)
2230/** @} */
2231
2232
2233/** @name Generic Invalidation Descriptor.
2234 * In accordance with the Intel spec.
2235 * Non-reserved fields here are common to all invalidation descriptors.
2236 * @{ */
2237/** Type (Lo). */
2238#define VTD_BF_0_GENERIC_INV_DSC_TYPE_LO_SHIFT 0
2239#define VTD_BF_0_GENERIC_INV_DSC_TYPE_LO_MASK UINT64_C(0x000000000000000f)
2240/** R: Reserved (bits 8:4). */
2241#define VTD_BF_0_GENERIC_INV_DSC_RSVD_8_4_SHIFT 4
2242#define VTD_BF_0_GENERIC_INV_DSC_RSVD_8_4_MASK UINT64_C(0x00000000000001f0)
2243/** Type (Hi). */
2244#define VTD_BF_0_GENERIC_INV_DSC_TYPE_HI_SHIFT 9
2245#define VTD_BF_0_GENERIC_INV_DSC_TYPE_HI_MASK UINT64_C(0x0000000000000e00)
2246/** R: Reserved (bits 63:12). */
2247#define VTD_BF_0_GENERIC_INV_DSC_RSVD_63_12_SHIFT 12
2248#define VTD_BF_0_GENERIC_INV_DSC_RSVD_63_12_MASK UINT64_C(0xfffffffffffff000)
2249RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_GENERIC_INV_DSC_, UINT64_C(0), UINT64_MAX,
2250 (TYPE_LO, RSVD_8_4, TYPE_HI, RSVD_63_12));
2251
2252/** GENERIC_INV_DSC: Type. */
2253#define VTD_GENERIC_INV_DSC_GET_TYPE(a) ((((a) & VTD_BF_0_GENERIC_INV_DSC_TYPE_HI_MASK) >> 5) \
2254 | ((a) & VTD_BF_0_GENERIC_INV_DSC_TYPE_LO_MASK))
2255/** @} */
2256
2257
2258/** @name Context-Cache Invalidation Descriptor (cc_inv_dsc).
2259 * In accordance with the Intel spec.
2260 * @{ */
2261/** Type (Lo). */
2262#define VTD_BF_0_CC_INV_DSC_TYPE_LO_SHIFT 0
2263#define VTD_BF_0_CC_INV_DSC_TYPE_LO_MASK UINT64_C(0x000000000000000f)
2264/** G: Granularity. */
2265#define VTD_BF_0_CC_INV_DSC_G_SHIFT 4
2266#define VTD_BF_0_CC_INV_DSC_G_MASK UINT64_C(0x0000000000000030)
2267/** R: Reserved (bits 8:6). */
2268#define VTD_BF_0_CC_INV_DSC_RSVD_8_6_SHIFT 6
2269#define VTD_BF_0_CC_INV_DSC_RSVD_8_6_MASK UINT64_C(0x00000000000001c0)
2270/** Type (Hi). */
2271#define VTD_BF_0_CC_INV_DSC_TYPE_HI_SHIFT 9
2272#define VTD_BF_0_CC_INV_DSC_TYPE_HI_MASK UINT64_C(0x0000000000000e00)
2273/** R: Reserved (bits 15:12). */
2274#define VTD_BF_0_CC_INV_DSC_RSVD_15_12_SHIFT 12
2275#define VTD_BF_0_CC_INV_DSC_RSVD_15_12_MASK UINT64_C(0x000000000000f000)
2276/** DID: Domain Id. */
2277#define VTD_BF_0_CC_INV_DSC_DID_SHIFT 16
2278#define VTD_BF_0_CC_INV_DSC_DID_MASK UINT64_C(0x00000000ffff0000)
2279/** SID: Source Id. */
2280#define VTD_BF_0_CC_INV_DSC_SID_SHIFT 32
2281#define VTD_BF_0_CC_INV_DSC_SID_MASK UINT64_C(0x0000ffff00000000)
2282/** FM: Function Mask. */
2283#define VTD_BF_0_CC_INV_DSC_FM_SHIFT 48
2284#define VTD_BF_0_CC_INV_DSC_FM_MASK UINT64_C(0x0003000000000000)
2285/** R: Reserved (bits 63:50). */
2286#define VTD_BF_0_CC_INV_DSC_RSVD_63_50_SHIFT 50
2287#define VTD_BF_0_CC_INV_DSC_RSVD_63_50_MASK UINT64_C(0xfffc000000000000)
2288RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_CC_INV_DSC_, UINT64_C(0), UINT64_MAX,
2289 (TYPE_LO, G, RSVD_8_6, TYPE_HI, RSVD_15_12, DID, SID, FM, RSVD_63_50));
2290/** @} */
2291
2292
2293/** @name PASID-Cache Invalidation Descriptor (pc_inv_dsc).
2294 * In accordance with the Intel spec.
2295 * @{ */
2296/** Type (Lo). */
2297#define VTD_BF_0_PC_INV_DSC_TYPE_LO_SHIFT 0
2298#define VTD_BF_0_PC_INV_DSC_TYPE_LO_MASK UINT64_C(0x000000000000000f)
2299/** G: Granularity. */
2300#define VTD_BF_0_PC_INV_DSC_G_SHIFT 4
2301#define VTD_BF_0_PC_INV_DSC_G_MASK UINT64_C(0x0000000000000030)
2302/** R: Reserved (bits 8:6). */
2303#define VTD_BF_0_PC_INV_DSC_RSVD_8_6_SHIFT 6
2304#define VTD_BF_0_PC_INV_DSC_RSVD_8_6_MASK UINT64_C(0x00000000000001c0)
2305/** Type (Hi). */
2306#define VTD_BF_0_PC_INV_DSC_TYPE_HI_SHIFT 9
2307#define VTD_BF_0_PC_INV_DSC_TYPE_HI_MASK UINT64_C(0x0000000000000e00)
2308/** R: Reserved (bits 15:12). */
2309#define VTD_BF_0_PC_INV_DSC_RSVD_15_12_SHIFT 12
2310#define VTD_BF_0_PC_INV_DSC_RSVD_15_12_MASK UINT64_C(0x000000000000f000)
2311/** DID: Domain Id. */
2312#define VTD_BF_0_PC_INV_DSC_DID_SHIFT 16
2313#define VTD_BF_0_PC_INV_DSC_DID_MASK UINT64_C(0x00000000ffff0000)
2314/** PASID: Process Address-Space Id. */
2315#define VTD_BF_0_PC_INV_DSC_PASID_SHIFT 32
2316#define VTD_BF_0_PC_INV_DSC_PASID_MASK UINT64_C(0x000fffff00000000)
2317/** R: Reserved (bits 63:52). */
2318#define VTD_BF_0_PC_INV_DSC_RSVD_63_52_SHIFT 52
2319#define VTD_BF_0_PC_INV_DSC_RSVD_63_52_MASK UINT64_C(0xfff0000000000000)
2320
2321RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_PC_INV_DSC_, UINT64_C(0), UINT64_MAX,
2322 (TYPE_LO, G, RSVD_8_6, TYPE_HI, RSVD_15_12, DID, PASID, RSVD_63_52));
2323/** @} */
2324
2325
2326/** @name IOTLB Invalidate Descriptor (iotlb_inv_dsc).
2327 * In accordance with the Intel spec.
2328 * @{ */
2329/** Type (Lo). */
2330#define VTD_BF_0_IOTLB_INV_DSC_TYPE_LO_SHIFT 0
2331#define VTD_BF_0_IOTLB_INV_DSC_TYPE_LO_MASK UINT64_C(0x000000000000000f)
2332/** G: Granularity. */
2333#define VTD_BF_0_IOTLB_INV_DSC_G_SHIFT 4
2334#define VTD_BF_0_IOTLB_INV_DSC_G_MASK UINT64_C(0x0000000000000030)
2335/** DW: Drain Writes. */
2336#define VTD_BF_0_IOTLB_INV_DSC_DW_SHIFT 6
2337#define VTD_BF_0_IOTLB_INV_DSC_DW_MASK UINT64_C(0x0000000000000040)
2338/** DR: Drain Reads. */
2339#define VTD_BF_0_IOTLB_INV_DSC_DR_SHIFT 7
2340#define VTD_BF_0_IOTLB_INV_DSC_DR_MASK UINT64_C(0x0000000000000080)
2341/** R: Reserved (bit 8). */
2342#define VTD_BF_0_IOTLB_INV_DSC_RSVD_8_SHIFT 8
2343#define VTD_BF_0_IOTLB_INV_DSC_RSVD_8_MASK UINT64_C(0x0000000000000100)
2344/** Type (Hi). */
2345#define VTD_BF_0_IOTLB_INV_DSC_TYPE_HI_SHIFT 9
2346#define VTD_BF_0_IOTLB_INV_DSC_TYPE_HI_MASK UINT64_C(0x0000000000000e00)
2347/** R: Reserved (bits 15:12). */
2348#define VTD_BF_0_IOTLB_INV_DSC_RSVD_15_12_SHIFT 12
2349#define VTD_BF_0_IOTLB_INV_DSC_RSVD_15_12_MASK UINT64_C(0x000000000000f000)
2350/** DID: Domain Id. */
2351#define VTD_BF_0_IOTLB_INV_DSC_DID_SHIFT 16
2352#define VTD_BF_0_IOTLB_INV_DSC_DID_MASK UINT64_C(0x00000000ffff0000)
2353/** R: Reserved (bits 63:32). */
2354#define VTD_BF_0_IOTLB_INV_DSC_RSVD_63_32_SHIFT 32
2355#define VTD_BF_0_IOTLB_INV_DSC_RSVD_63_32_MASK UINT64_C(0xffffffff00000000)
2356RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_IOTLB_INV_DSC_, UINT64_C(0), UINT64_MAX,
2357 (TYPE_LO, G, DW, DR, RSVD_8, TYPE_HI, RSVD_15_12, DID, RSVD_63_32));
2358
2359/** AM: Address Mask. */
2360#define VTD_BF_1_IOTLB_INV_DSC_AM_SHIFT 0
2361#define VTD_BF_1_IOTLB_INV_DSC_AM_MASK UINT64_C(0x000000000000003f)
2362/** IH: Invalidation Hint. */
2363#define VTD_BF_1_IOTLB_INV_DSC_IH_SHIFT 6
2364#define VTD_BF_1_IOTLB_INV_DSC_IH_MASK UINT64_C(0x0000000000000040)
2365/** R: Reserved (bits 11:7). */
2366#define VTD_BF_1_IOTLB_INV_DSC_RSVD_11_7_SHIFT 7
2367#define VTD_BF_1_IOTLB_INV_DSC_RSVD_11_7_MASK UINT64_C(0x0000000000000f80)
2368/** ADDR: Address. */
2369#define VTD_BF_1_IOTLB_INV_DSC_ADDR_SHIFT 12
2370#define VTD_BF_1_IOTLB_INV_DSC_ADDR_MASK UINT64_C(0xfffffffffffff000)
2371RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_IOTLB_INV_DSC_, UINT64_C(0), UINT64_MAX,
2372 (AM, IH, RSVD_11_7, ADDR));
2373/** @} */
2374
2375
2376/** @name PASID-based IOTLB Invalidate Descriptor (p_iotlb_inv_dsc).
2377 * In accordance with the Intel spec.
2378 * @{ */
2379/** Type (Lo). */
2380#define VTD_BF_0_P_IOTLB_INV_DSC_TYPE_LO_SHIFT 0
2381#define VTD_BF_0_P_IOTLB_INV_DSC_TYPE_LO_MASK UINT64_C(0x000000000000000f)
2382/** G: Granularity. */
2383#define VTD_BF_0_P_IOTLB_INV_DSC_G_SHIFT 4
2384#define VTD_BF_0_P_IOTLB_INV_DSC_G_MASK UINT64_C(0x0000000000000030)
2385/** R: Reserved (bits 8:6). */
2386#define VTD_BF_0_P_IOTLB_INV_DSC_RSVD_8_6_SHIFT 6
2387#define VTD_BF_0_P_IOTLB_INV_DSC_RSVD_8_6_MASK UINT64_C(0x00000000000001c0)
2388/** Type (Hi). */
2389#define VTD_BF_0_P_IOTLB_INV_DSC_TYPE_HI_SHIFT 9
2390#define VTD_BF_0_P_IOTLB_INV_DSC_TYPE_HI_MASK UINT64_C(0x0000000000000e00)
2391/** R: Reserved (bits 15:12). */
2392#define VTD_BF_0_P_IOTLB_INV_DSC_RSVD_15_12_SHIFT 12
2393#define VTD_BF_0_P_IOTLB_INV_DSC_RSVD_15_12_MASK UINT64_C(0x000000000000f000)
2394/** DID: Domain Id. */
2395#define VTD_BF_0_P_IOTLB_INV_DSC_DID_SHIFT 16
2396#define VTD_BF_0_P_IOTLB_INV_DSC_DID_MASK UINT64_C(0x00000000ffff0000)
2397/** PASID: Process Address-Space Id. */
2398#define VTD_BF_0_P_IOTLB_INV_DSC_PASID_SHIFT 32
2399#define VTD_BF_0_P_IOTLB_INV_DSC_PASID_MASK UINT64_C(0x000fffff00000000)
2400/** R: Reserved (bits 63:52). */
2401#define VTD_BF_0_P_IOTLB_INV_DSC_RSVD_63_52_SHIFT 52
2402#define VTD_BF_0_P_IOTLB_INV_DSC_RSVD_63_52_MASK UINT64_C(0xfff0000000000000)
2403RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_P_IOTLB_INV_DSC_, UINT64_C(0), UINT64_MAX,
2404 (TYPE_LO, G, RSVD_8_6, TYPE_HI, RSVD_15_12, DID, PASID, RSVD_63_52));
2405
2406
2407/** AM: Address Mask. */
2408#define VTD_BF_1_P_IOTLB_INV_DSC_AM_SHIFT 0
2409#define VTD_BF_1_P_IOTLB_INV_DSC_AM_MASK UINT64_C(0x000000000000003f)
2410/** IH: Invalidation Hint. */
2411#define VTD_BF_1_P_IOTLB_INV_DSC_IH_SHIFT 6
2412#define VTD_BF_1_P_IOTLB_INV_DSC_IH_MASK UINT64_C(0x0000000000000040)
2413/** R: Reserved (bits 11:7). */
2414#define VTD_BF_1_P_IOTLB_INV_DSC_RSVD_11_7_SHIFT 7
2415#define VTD_BF_1_P_IOTLB_INV_DSC_RSVD_11_7_MASK UINT64_C(0x0000000000000f80)
2416/** ADDR: Address. */
2417#define VTD_BF_1_P_IOTLB_INV_DSC_ADDR_SHIFT 12
2418#define VTD_BF_1_P_IOTLB_INV_DSC_ADDR_MASK UINT64_C(0xfffffffffffff000)
2419RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_P_IOTLB_INV_DSC_, UINT64_C(0), UINT64_MAX,
2420 (AM, IH, RSVD_11_7, ADDR));
2421/** @} */
2422
2423
2424/** @name Device-TLB Invalidate Descriptor (dev_tlb_inv_dsc).
2425 * In accordance with the Intel spec.
2426 * @{ */
2427/** Type (Lo). */
2428#define VTD_BF_0_DEV_TLB_INV_DSC_TYPE_LO_SHIFT 0
2429#define VTD_BF_0_DEV_TLB_INV_DSC_TYPE_LO_MASK UINT64_C(0x000000000000000f)
2430/** R: Reserved (bits 8:4). */
2431#define VTD_BF_0_DEV_TLB_INV_DSC_RSVD_8_4_SHIFT 4
2432#define VTD_BF_0_DEV_TLB_INV_DSC_RSVD_8_4_MASK UINT64_C(0x00000000000001f0)
2433/** Type (Hi). */
2434#define VTD_BF_0_DEV_TLB_INV_DSC_TYPE_HI_SHIFT 9
2435#define VTD_BF_0_DEV_TLB_INV_DSC_TYPE_HI_MASK UINT64_C(0x0000000000000e00)
2436/** PFSID: Physical-Function Source Id (Lo). */
2437#define VTD_BF_0_DEV_TLB_INV_DSC_PFSID_LO_SHIFT 12
2438#define VTD_BF_0_DEV_TLB_INV_DSC_PFSID_LO_MASK UINT64_C(0x000000000000f000)
2439/** MIP: Max Invalidations Pending. */
2440#define VTD_BF_0_DEV_TLB_INV_DSC_MIP_SHIFT 16
2441#define VTD_BF_0_DEV_TLB_INV_DSC_MIP_MASK UINT64_C(0x00000000001f0000)
2442/** R: Reserved (bits 31:21). */
2443#define VTD_BF_0_DEV_TLB_INV_DSC_RSVD_31_21_SHIFT 21
2444#define VTD_BF_0_DEV_TLB_INV_DSC_RSVD_31_21_MASK UINT64_C(0x00000000ffe00000)
2445/** SID: Source Id. */
2446#define VTD_BF_0_DEV_TLB_INV_DSC_SID_SHIFT 32
2447#define VTD_BF_0_DEV_TLB_INV_DSC_SID_MASK UINT64_C(0x0000ffff00000000)
2448/** R: Reserved (bits 51:48). */
2449#define VTD_BF_0_DEV_TLB_INV_DSC_RSVD_51_48_SHIFT 48
2450#define VTD_BF_0_DEV_TLB_INV_DSC_RSVD_51_48_MASK UINT64_C(0x000f000000000000)
2451/** PFSID: Physical-Function Source Id (Hi). */
2452#define VTD_BF_0_DEV_TLB_INV_DSC_PFSID_HI_SHIFT 52
2453#define VTD_BF_0_DEV_TLB_INV_DSC_PFSID_HI_MASK UINT64_C(0xfff0000000000000)
2454RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_DEV_TLB_INV_DSC_, UINT64_C(0), UINT64_MAX,
2455 (TYPE_LO, RSVD_8_4, TYPE_HI, PFSID_LO, MIP, RSVD_31_21, SID, RSVD_51_48, PFSID_HI));
2456
2457/** S: Size. */
2458#define VTD_BF_1_DEV_TLB_INV_DSC_S_SHIFT 0
2459#define VTD_BF_1_DEV_TLB_INV_DSC_S_MASK UINT64_C(0x0000000000000001)
2460/** R: Reserved (bits 11:1). */
2461#define VTD_BF_1_DEV_TLB_INV_DSC_RSVD_11_1_SHIFT 1
2462#define VTD_BF_1_DEV_TLB_INV_DSC_RSVD_11_1_MASK UINT64_C(0x0000000000000ffe)
2463/** ADDR: Address. */
2464#define VTD_BF_1_DEV_TLB_INV_DSC_ADDR_SHIFT 12
2465#define VTD_BF_1_DEV_TLB_INV_DSC_ADDR_MASK UINT64_C(0xfffffffffffff000)
2466RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_DEV_TLB_INV_DSC_, UINT64_C(0), UINT64_MAX,
2467 (S, RSVD_11_1, ADDR));
2468/** @} */
2469
2470
2471/** @name PASID-based-device-TLB Invalidate Descriptor (p_dev_tlb_inv_dsc).
2472 * In accordance with the Intel spec.
2473 * @{ */
2474/** Type (Lo). */
2475#define VTD_BF_0_P_DEV_TLB_INV_DSC_TYPE_LO_SHIFT 0
2476#define VTD_BF_0_P_DEV_TLB_INV_DSC_TYPE_LO_MASK UINT64_C(0x000000000000000f)
2477/** MIP: Max Invalidations Pending. */
2478#define VTD_BF_0_P_DEV_TLB_INV_DSC_MIP_SHIFT 4
2479#define VTD_BF_0_P_DEV_TLB_INV_DSC_MIP_MASK UINT64_C(0x00000000000001f0)
2480/** Type (Hi). */
2481#define VTD_BF_0_P_DEV_TLB_INV_DSC_TYPE_HI_SHIFT 9
2482#define VTD_BF_0_P_DEV_TLB_INV_DSC_TYPE_HI_MASK UINT64_C(0x0000000000000e00)
2483/** PFSID: Physical-Function Source Id (Lo). */
2484#define VTD_BF_0_P_DEV_TLB_INV_DSC_PFSID_LO_SHIFT 12
2485#define VTD_BF_0_P_DEV_TLB_INV_DSC_PFSID_LO_MASK UINT64_C(0x000000000000f000)
2486/** SID: Source Id. */
2487#define VTD_BF_0_P_DEV_TLB_INV_DSC_SID_SHIFT 16
2488#define VTD_BF_0_P_DEV_TLB_INV_DSC_SID_MASK UINT64_C(0x00000000ffff0000)
2489/** PASID: Process Address-Space Id. */
2490#define VTD_BF_0_P_DEV_TLB_INV_DSC_PASID_SHIFT 32
2491#define VTD_BF_0_P_DEV_TLB_INV_DSC_PASID_MASK UINT64_C(0x000fffff00000000)
2492/** PFSID: Physical-Function Source Id (Hi). */
2493#define VTD_BF_0_P_DEV_TLB_INV_DSC_PFSID_HI_SHIFT 52
2494#define VTD_BF_0_P_DEV_TLB_INV_DSC_PFSID_HI_MASK UINT64_C(0xfff0000000000000)
2495RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_P_DEV_TLB_INV_DSC_, UINT64_C(0), UINT64_MAX,
2496 (TYPE_LO, MIP, TYPE_HI, PFSID_LO, SID, PASID, PFSID_HI));
2497
2498/** G: Granularity. */
2499#define VTD_BF_1_P_DEV_TLB_INV_DSC_G_SHIFT 0
2500#define VTD_BF_1_P_DEV_TLB_INV_DSC_G_MASK UINT64_C(0x0000000000000001)
2501/** R: Reserved (bits 10:1). */
2502#define VTD_BF_1_P_DEV_TLB_INV_DSC_RSVD_10_1_SHIFT 1
2503#define VTD_BF_1_P_DEV_TLB_INV_DSC_RSVD_10_1_MASK UINT64_C(0x00000000000007fe)
2504/** S: Size. */
2505#define VTD_BF_1_P_DEV_TLB_INV_DSC_S_SHIFT 11
2506#define VTD_BF_1_P_DEV_TLB_INV_DSC_S_MASK UINT64_C(0x0000000000000800)
2507/** ADDR: Address. */
2508#define VTD_BF_1_P_DEV_TLB_INV_DSC_ADDR_SHIFT 12
2509#define VTD_BF_1_P_DEV_TLB_INV_DSC_ADDR_MASK UINT64_C(0xfffffffffffff000)
2510RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_P_DEV_TLB_INV_DSC_, UINT64_C(0), UINT64_MAX,
2511 (G, RSVD_10_1, S, ADDR));
2512/** @} */
2513
2514
2515/** @name Interrupt Entry Cache Invalidate Descriptor (iec_inv_dsc).
2516 * In accordance with the Intel spec.
2517 * @{ */
2518/** Type (Lo). */
2519#define VTD_BF_0_IEC_INV_DSC_TYPE_LO_SHIFT 0
2520#define VTD_BF_0_IEC_INV_DSC_TYPE_LO_MASK UINT64_C(0x000000000000000f)
2521/** G: Granularity. */
2522#define VTD_BF_0_IEC_INV_DSC_G_SHIFT 4
2523#define VTD_BF_0_IEC_INV_DSC_G_MASK UINT64_C(0x0000000000000010)
2524/** R: Reserved (bits 8:5). */
2525#define VTD_BF_0_IEC_INV_DSC_RSVD_8_5_SHIFT 5
2526#define VTD_BF_0_IEC_INV_DSC_RSVD_8_5_MASK UINT64_C(0x00000000000001e0)
2527/** Type (Hi). */
2528#define VTD_BF_0_IEC_INV_DSC_TYPE_HI_SHIFT 9
2529#define VTD_BF_0_IEC_INV_DSC_TYPE_HI_MASK UINT64_C(0x0000000000000e00)
2530/** R: Reserved (bits 26:12). */
2531#define VTD_BF_0_IEC_INV_DSC_RSVD_26_12_SHIFT 12
2532#define VTD_BF_0_IEC_INV_DSC_RSVD_26_12_MASK UINT64_C(0x0000000007fff000)
2533/** IM: Index Mask. */
2534#define VTD_BF_0_IEC_INV_DSC_IM_SHIFT 27
2535#define VTD_BF_0_IEC_INV_DSC_IM_MASK UINT64_C(0x00000000f8000000)
2536/** IIDX: Interrupt Index. */
2537#define VTD_BF_0_IEC_INV_DSC_IIDX_SHIFT 32
2538#define VTD_BF_0_IEC_INV_DSC_IIDX_MASK UINT64_C(0x0000ffff00000000)
2539/** R: Reserved (bits 63:48). */
2540#define VTD_BF_0_IEC_INV_DSC_RSVD_63_48_SHIFT 48
2541#define VTD_BF_0_IEC_INV_DSC_RSVD_63_48_MASK UINT64_C(0xffff000000000000)
2542RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_IEC_INV_DSC_, UINT64_C(0), UINT64_MAX,
2543 (TYPE_LO, G, RSVD_8_5, TYPE_HI, RSVD_26_12, IM, IIDX, RSVD_63_48));
2544/** @} */
2545
2546
2547/** @name Invalidation Wait Descriptor (inv_wait_dsc).
2548 * In accordance with the Intel spec.
2549 * @{ */
2550/** Type (Lo). */
2551#define VTD_BF_0_INV_WAIT_DSC_TYPE_LO_SHIFT 0
2552#define VTD_BF_0_INV_WAIT_DSC_TYPE_LO_MASK UINT64_C(0x000000000000000f)
2553/** IF: Interrupt Flag. */
2554#define VTD_BF_0_INV_WAIT_DSC_IF_SHIFT 4
2555#define VTD_BF_0_INV_WAIT_DSC_IF_MASK UINT64_C(0x0000000000000010)
2556/** SW: Status Write. */
2557#define VTD_BF_0_INV_WAIT_DSC_SW_SHIFT 5
2558#define VTD_BF_0_INV_WAIT_DSC_SW_MASK UINT64_C(0x0000000000000020)
2559/** FN: Fence Flag. */
2560#define VTD_BF_0_INV_WAIT_DSC_FN_SHIFT 6
2561#define VTD_BF_0_INV_WAIT_DSC_FN_MASK UINT64_C(0x0000000000000040)
2562/** PD: Page-Request Drain. */
2563#define VTD_BF_0_INV_WAIT_DSC_PD_SHIFT 7
2564#define VTD_BF_0_INV_WAIT_DSC_PD_MASK UINT64_C(0x0000000000000080)
2565/** R: Reserved (bit 8). */
2566#define VTD_BF_0_INV_WAIT_DSC_RSVD_8_SHIFT 8
2567#define VTD_BF_0_INV_WAIT_DSC_RSVD_8_MASK UINT64_C(0x0000000000000100)
2568/** Type (Hi). */
2569#define VTD_BF_0_INV_WAIT_DSC_TYPE_HI_SHIFT 9
2570#define VTD_BF_0_INV_WAIT_DSC_TYPE_HI_MASK UINT64_C(0x0000000000000e00)
2571/** R: Reserved (bits 31:12). */
2572#define VTD_BF_0_INV_WAIT_DSC_RSVD_31_12_SHIFT 12
2573#define VTD_BF_0_INV_WAIT_DSC_RSVD_31_12_MASK UINT64_C(0x00000000fffff000)
2574/** STDATA: Status Data. */
2575#define VTD_BF_0_INV_WAIT_DSC_STDATA_SHIFT 32
2576#define VTD_BF_0_INV_WAIT_DSC_STDATA_MASK UINT64_C(0xffffffff00000000)
2577RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_INV_WAIT_DSC_, UINT64_C(0), UINT64_MAX,
2578 (TYPE_LO, IF, SW, FN, PD, RSVD_8, TYPE_HI, RSVD_31_12, STDATA));
2579
2580/** R: Reserved (bits 1:0). */
2581#define VTD_BF_1_INV_WAIT_DSC_RSVD_1_0_SHIFT 0
2582#define VTD_BF_1_INV_WAIT_DSC_RSVD_1_0_MASK UINT64_C(0x0000000000000003)
2583/** STADDR: Status Address. */
2584#define VTD_BF_1_INV_WAIT_DSC_STADDR_SHIFT 2
2585#define VTD_BF_1_INV_WAIT_DSC_STADDR_MASK UINT64_C(0xfffffffffffffffc)
2586RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_INV_WAIT_DSC_, UINT64_C(0), UINT64_MAX,
2587 (RSVD_1_0, STADDR));
2588
2589/* INV_WAIT_DSC: Qword 0 valid mask. */
2590#define VTD_INV_WAIT_DSC_0_VALID_MASK ( VTD_BF_0_INV_WAIT_DSC_TYPE_LO_MASK \
2591 | VTD_BF_0_INV_WAIT_DSC_IF_MASK \
2592 | VTD_BF_0_INV_WAIT_DSC_SW_MASK \
2593 | VTD_BF_0_INV_WAIT_DSC_FN_MASK \
2594 | VTD_BF_0_INV_WAIT_DSC_PD_MASK \
2595 | VTD_BF_0_INV_WAIT_DSC_TYPE_HI_MASK \
2596 | VTD_BF_0_INV_WAIT_DSC_STDATA_MASK)
2597/* INV_WAIT_DSC: Qword 1 valid mask. */
2598#define VTD_INV_WAIT_DSC_1_VALID_MASK VTD_BF_1_INV_WAIT_DSC_STADDR_MASK
2599/** @} */
2600
2601
2602/** @name Invalidation descriptor types.
2603 * In accordance with the Intel spec.
2604 * @{ */
2605#define VTD_CC_INV_DSC_TYPE 1
2606#define VTD_IOTLB_INV_DSC_TYPE 2
2607#define VTD_DEV_TLB_INV_DSC_TYPE 3
2608#define VTD_IEC_INV_DSC_TYPE 4
2609#define VTD_INV_WAIT_DSC_TYPE 5
2610#define VTD_P_IOTLB_INV_DSC_TYPE 6
2611#define VTD_PC_INV_DSC_TYPE 7
2612#define VTD_P_DEV_TLB_INV_DSC_TYPE 8
2613/** @} */
2614
2615
2616/** @name Remappable Format Interrupt Request.
2617 * In accordance with the Intel spec.
2618 * @{ */
2619/** IGN: Ignored (bits 1:0). */
2620#define VTD_BF_REMAPPABLE_MSI_ADDR_IGN_1_0_SHIFT 0
2621#define VTD_BF_REMAPPABLE_MSI_ADDR_IGN_1_0_MASK UINT32_C(0x00000003)
2622/** Handle (Hi). */
2623#define VTD_BF_REMAPPABLE_MSI_ADDR_HANDLE_HI_SHIFT 2
2624#define VTD_BF_REMAPPABLE_MSI_ADDR_HANDLE_HI_MASK UINT32_C(0x00000004)
2625/** SHV: Subhandle Valid. */
2626#define VTD_BF_REMAPPABLE_MSI_ADDR_SHV_SHIFT 3
2627#define VTD_BF_REMAPPABLE_MSI_ADDR_SHV_MASK UINT32_C(0x00000008)
2628/** Interrupt format. */
2629#define VTD_BF_REMAPPABLE_MSI_ADDR_INTR_FMT_SHIFT 4
2630#define VTD_BF_REMAPPABLE_MSI_ADDR_INTR_FMT_MASK UINT32_C(0x00000010)
2631/** Handle (Lo). */
2632#define VTD_BF_REMAPPABLE_MSI_ADDR_HANDLE_LO_SHIFT 5
2633#define VTD_BF_REMAPPABLE_MSI_ADDR_HANDLE_LO_MASK UINT32_C(0x000fffe0)
2634/** Address. */
2635#define VTD_BF_REMAPPABLE_MSI_ADDR_ADDR_SHIFT 20
2636#define VTD_BF_REMAPPABLE_MSI_ADDR_ADDR_MASK UINT32_C(0xfff00000)
2637RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_REMAPPABLE_MSI_ADDR_, UINT32_C(0), UINT32_MAX,
2638 (IGN_1_0, HANDLE_HI, SHV, INTR_FMT, HANDLE_LO, ADDR));
2639
2640/** Subhandle. */
2641#define VTD_BF_REMAPPABLE_MSI_DATA_SUBHANDLE_SHIFT 0
2642#define VTD_BF_REMAPPABLE_MSI_DATA_SUBHANDLE_MASK UINT32_C(0x0000ffff)
2643/** R: Reserved (bits 31:16). */
2644#define VTD_BF_REMAPPABLE_MSI_DATA_RSVD_31_16_SHIFT 16
2645#define VTD_BF_REMAPPABLE_MSI_DATA_RSVD_31_16_MASK UINT32_C(0xffff0000)
2646RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_REMAPPABLE_MSI_DATA_, UINT32_C(0), UINT32_MAX,
2647 (SUBHANDLE, RSVD_31_16));
2648
2649/** Remappable MSI Address: Valid mask. */
2650#define VTD_REMAPPABLE_MSI_ADDR_VALID_MASK UINT32_MAX
2651/** Remappable MSI Data: Valid mask. */
2652#define VTD_REMAPPABLE_MSI_DATA_VALID_MASK VTD_BF_REMAPPABLE_MSI_DATA_SUBHANDLE_MASK
2653
2654/** Interrupt format: Compatibility. */
2655#define VTD_INTR_FORMAT_COMPAT 0
2656/** Interrupt format: Remappable. */
2657#define VTD_INTR_FORMAT_REMAPPABLE 1
2658/** @} */
2659
2660
2661/** @name Interrupt Remapping Fault Conditions.
2662 * In accordance with the Intel spec.
2663 * @{ */
2664typedef enum VTDIRFAULT
2665{
2666 /** Reserved bits invalid in remappable interrupt. */
2667 VTDIRFAULT_REMAPPABLE_INTR_RSVD = 0x20,
2668
2669 /** Interrupt index for remappable interrupt exceeds table size or referenced
2670 * address above host address width (HAW) */
2671 VTDIRFAULT_INTR_INDEX_INVALID = 0x21,
2672
2673 /** The IRTE is not present. */
2674 VTDIRFAULT_IRTE_NOT_PRESENT = 0x22,
2675 /** Reading IRTE from memory failed. */
2676 VTDIRFAULT_IRTE_READ_FAILED = 0x23,
2677 /** IRTE reserved bits invalid for an IRTE with Present bit set. */
2678 VTDIRFAULT_IRTE_PRESENT_RSVD = 0x24,
2679
2680 /** Compatibility format interrupt (CFI) blocked due to EIME being enabled or CFIs
2681 * were disabled. */
2682 VTDIRFAULT_CFI_BLOCKED = 0x25,
2683
2684 /** IRTE SID, SVT, SQ bits invalid for an IRTE with Present bit set. */
2685 VTDIRFAULT_IRTE_PRESENT_INVALID = 0x26,
2686
2687 /** Reading posted interrupt descriptor (PID) failed. */
2688 VTDIRFAULT_PID_READ_FAILED = 0x27,
2689 /** PID reserved bits invalid. */
2690 VTDIRFAULT_PID_RSVD = 0x28,
2691
2692 /** Untranslated interrupt requested (without PASID) is invalid. */
2693 VTDIRFAULT_IR_WITHOUT_PASID_INVALID = 0x29
2694} VTDIRFAULT;
2695AssertCompileSize(VTDIRFAULT, 4);
2696/** @} */
2697
2698
2699/** @name Address Translation Fault Conditions.
2700 * In accordance with the Intel spec.
2701 * @{ */
2702typedef enum VTDATFAULT
2703{
2704 /* Legacy root table faults (LRT). */
2705 VTDATFAULT_LRT_1 = 0x8,
2706 VTDATFAULT_LRT_2 = 0x1,
2707 VTDATFAULT_LRT_3 = 0xa,
2708
2709 /* Legacy Context-Table Faults (LCT). */
2710 VTDATFAULT_LCT_1 = 0x9,
2711 VTDATFAULT_LCT_2 = 0x2,
2712 VTDATFAULT_LCT_3 = 0xb,
2713 VTDATFAULT_LCT_4_1 = 0x3,
2714 VTDATFAULT_LCT_4_2 = 0x3,
2715 VTDATFAULT_LCT_4_3 = 0x3,
2716 VTDATFAULT_LCT_5 = 0xd,
2717
2718 /* Legacy Second-Level Table Faults (LSL). */
2719 VTDATFAULT_LSL_1 = 0x7,
2720 VTDATFAULT_LSL_2 = 0xc,
2721
2722 /* Legacy General Faults (LGN). */
2723 VTDATFAULT_LGN_1_1 = 0x4,
2724 VTDATFAULT_LGN_1_2 = 0x4,
2725 VTDATFAULT_LGN_1_3 = 0x4,
2726 VTDATFAULT_LGN_2 = 0x5,
2727 VTDATFAULT_LGN_3 = 0x6,
2728 VTDATFAULT_LGN_4 = 0xe,
2729
2730 /* Root-Table Address Register Faults (RTA). */
2731 VTDATFAULT_RTA_1_1 = 0x30,
2732 VTDATFAULT_RTA_1_2 = 0x30,
2733 VTDATFAULT_RTA_1_3 = 0x30,
2734 VTDATFAULT_RTA_2 = 0x31,
2735 VTDATFAULT_RTA_3 = 0x32,
2736 VTDATFAULT_RTA_4 = 0x33,
2737
2738 /* Scalable-Mode Root-Table Faults (SRT). */
2739 VTDATFAULT_SRT_1 = 0x38,
2740 VTDATFAULT_SRT_2 = 0x39,
2741 VTDATFAULT_SRT_3 = 0x3a,
2742
2743 /* Scalable-Mode Context-Table Faults (SCT). */
2744 VTDATFAULT_SCT_1 = 0x40,
2745 VTDATFAULT_SCT_2 = 0x41,
2746 VTDATFAULT_SCT_3 = 0x42,
2747 VTDATFAULT_SCT_4_1 = 0x43,
2748 VTDATFAULT_SCT_4_2 = 0x43,
2749 VTDATFAULT_SCT_5 = 0x44,
2750 VTDATFAULT_SCT_6 = 0x45,
2751 VTDATFAULT_SCT_7 = 0x46,
2752 VTDATFAULT_SCT_8 = 0x47,
2753 VTDATFAULT_SCT_9 = 0x48,
2754
2755 /* Scalable-Mode PASID-Directory Faults (SPD). */
2756 VTDATFAULT_SPD_1 = 0x50,
2757 VTDATFAULT_SPD_2 = 0x51,
2758 VTDATFAULT_SPD_3 = 0x52,
2759
2760 /* Scalable-Mode PASID-Table Faults (SPT). */
2761 VTDATFAULT_SPT_1 = 0x58,
2762 VTDATFAULT_SPT_2 = 0x59,
2763 VTDATFAULT_SPT_3 = 0x5a,
2764 VTDATFAULT_SPT_4_1 = 0x5b,
2765 VTDATFAULT_SPT_4_2 = 0x5b,
2766 VTDATFAULT_SPT_4_3 = 0x5b,
2767 VTDATFAULT_SPT_4_4 = 0x5b,
2768 VTDATFAULT_SPT_5 = 0x5c,
2769 VTDATFAULT_SPT_6 = 0x5d,
2770
2771 /* Scalable-Mode First-Level Table Faults (SFL). */
2772 VTDATFAULT_SFL_1 = 0x70,
2773 VTDATFAULT_SFL_2 = 0x71,
2774 VTDATFAULT_SFL_3 = 0x72,
2775 VTDATFAULT_SFL_4 = 0x73,
2776 VTDATFAULT_SFL_5 = 0x74,
2777 VTDATFAULT_SFL_6 = 0x75,
2778 VTDATFAULT_SFL_7 = 0x76,
2779 VTDATFAULT_SFL_8 = 0x77,
2780 VTDATFAULT_SFL_9 = 0x90,
2781 VTDATFAULT_SFL_10 = 0x91,
2782
2783 /* Scalable-Mode Second-Level Table Faults (SSL). */
2784 VTDATFAULT_SSL_1 = 0x78,
2785 VTDATFAULT_SSL_2 = 0x79,
2786 VTDATFAULT_SSL_3 = 0x7a,
2787 VTDATFAULT_SSL_4 = 0x7b,
2788 VTDATFAULT_SSL_5 = 0x7c,
2789 VTDATFAULT_SSL_6 = 0x7d,
2790
2791 /* Scalable-Mode General Faults (SGN). */
2792 VTDATFAULT_SGN_1 = 0x80,
2793 VTDATFAULT_SGN_2 = 0x81,
2794 VTDATFAULT_SGN_3 = 0x82,
2795 VTDATFAULT_SGN_4_1 = 0x83,
2796 VTDATFAULT_SGN_4_2 = 0x83,
2797 VTDATFAULT_SGN_5 = 0x84,
2798 VTDATFAULT_SGN_6 = 0x85,
2799 VTDATFAULT_SGN_7 = 0x86,
2800 VTDATFAULT_SGN_8 = 0x87,
2801 VTDATFAULT_SGN_9 = 0x88,
2802 VTDATFAULT_SGN_10 = 0x89
2803} VTDATFAULT;
2804AssertCompileSize(VTDATFAULT, 4);
2805/** @} */
2806
2807
2808/** @name ACPI_DMAR_F_XXX: DMA Remapping Reporting Structure Flags.
2809 * In accordance with the Intel spec.
2810 * @{ */
2811/** INTR_REMAP: Interrupt remapping supported. */
2812#define ACPI_DMAR_F_INTR_REMAP RT_BIT(0)
2813/** X2APIC_OPT_OUT: Request system software to opt-out of enabling x2APIC. */
2814#define ACPI_DMAR_F_X2APIC_OPT_OUT RT_BIT(1)
2815/** DMA_CTRL_PLATFORM_OPT_IN_FLAG: Firmware initiated DMA restricted to reserved
2816 * memory regions (RMRR). */
2817#define ACPI_DMAR_F_DMA_CTRL_PLATFORM_OPT_IN RT_BIT(2)
2818/** @} */
2819
2820
2821/** @name ACPI_DRHD_F_XXX: DMA-Remapping Hardware Unit Definition Flags.
2822 * In accordance with the Intel spec.
2823 * @{ */
2824/** INCLUDE_PCI_ALL: All PCI devices under scope. */
2825#define ACPI_DRHD_F_INCLUDE_PCI_ALL RT_BIT(0)
2826/** @} */
2827
2828
2829/**
2830 * DRHD: DMA-Remapping Hardware Unit Definition.
2831 * In accordance with the Intel spec.
2832 */
2833#pragma pack(1)
2834typedef struct ACPIDRHD
2835{
2836 /** Type (must be 0=DRHD). */
2837 uint16_t uType;
2838 /** Length (must be 16 + size of device scope structure). */
2839 uint16_t cbLength;
2840 /** Flags, see ACPI_DRHD_F_XXX. */
2841 uint8_t fFlags;
2842 /** Reserved (MBZ). */
2843 uint8_t bRsvd;
2844 /** PCI segment number. */
2845 uint16_t uPciSegment;
2846 /** Register Base Address (MMIO). */
2847 uint64_t uRegBaseAddr;
2848 /* Device Scope[] Structures follow. */
2849} ACPIDRHD;
2850#pragma pack()
2851AssertCompileSize(ACPIDRHD, 16);
2852AssertCompileMemberOffset(ACPIDRHD, cbLength, 2);
2853AssertCompileMemberOffset(ACPIDRHD, fFlags, 4);
2854AssertCompileMemberOffset(ACPIDRHD, uPciSegment, 6);
2855AssertCompileMemberOffset(ACPIDRHD, uRegBaseAddr, 8);
2856
2857
2858/** @name ACPIDMARDEVSCOPE_TYPE_XXX: Device Type.
2859 * In accordance with the Intel spec.
2860 * @{ */
2861#define ACPIDMARDEVSCOPE_TYPE_PCI_ENDPOINT 1
2862#define ACPIDMARDEVSCOPE_TYPE_PCI_SUB_HIERARCHY 2
2863#define ACPIDMARDEVSCOPE_TYPE_IOAPIC 3
2864#define ACPIDMARDEVSCOPE_TYPE_MSI_CAP_HPET 4
2865#define ACPIDMARDEVSCOPE_TYPE_ACPI_NAMESPACE_DEV 5
2866/** @} */
2867
2868
2869/**
2870 * ACPI Device Scope Structure - PCI device path.
2871 * In accordance with the Intel spec.
2872 */
2873typedef struct ACPIDEVSCOPEPATH
2874{
2875 /** PCI device number. */
2876 uint8_t uDevice;
2877 /** PCI function number. */
2878 uint8_t uFunction;
2879} ACPIDEVSCOPEPATH;
2880AssertCompileSize(ACPIDEVSCOPEPATH, 2);
2881
2882
2883/**
2884 * Device Scope Structure.
2885 * In accordance with the Intel spec.
2886 */
2887#pragma pack(1)
2888typedef struct ACPIDMARDEVSCOPE
2889{
2890 /** Type, see ACPIDMARDEVSCOPE_TYPE_XXX. */
2891 uint8_t uType;
2892 /** Length (must be 6 + size of auPath field). */
2893 uint8_t cbLength;
2894 /** Reserved (MBZ). */
2895 uint8_t abRsvd[2];
2896 /** Enumeration ID (for I/O APIC, HPET and ACPI namespace devices). */
2897 uint8_t idEnum;
2898 /** First bus number for this device. */
2899 uint8_t uStartBusNum;
2900 /** Hierarchical path from the Host Bridge to the device. */
2901 ACPIDEVSCOPEPATH Path;
2902} ACPIDMARDEVSCOPE;
2903#pragma pack()
2904AssertCompileMemberOffset(ACPIDMARDEVSCOPE, cbLength, 1);
2905AssertCompileMemberOffset(ACPIDMARDEVSCOPE, idEnum, 4);
2906AssertCompileMemberOffset(ACPIDMARDEVSCOPE, uStartBusNum, 5);
2907AssertCompileMemberOffset(ACPIDMARDEVSCOPE, Path, 6);
2908
2909/** ACPI DMAR revision (not the OEM revision field).
2910 * In accordance with the Intel spec. */
2911#define ACPI_DMAR_REVISION 1
2912
2913
2914#endif /* !VBOX_INCLUDED_iommu_intel_h */
2915
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