VirtualBox

source: vbox/trunk/include/VBox/iommu-intel.h@ 88174

Last change on this file since 88174 was 88174, checked in by vboxsync, 4 years ago

Intel IOMMU: bugref:9967 Fix const declaration.
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1/** @file
2 * IOMMU - Input/Output Memory Management Unit (Intel).
3 */
4
5/*
6 * Copyright (C) 2021 Oracle Corporation
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * The contents of this file may alternatively be used under the terms
17 * of the Common Development and Distribution License Version 1.0
18 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19 * VirtualBox OSE distribution, in which case the provisions of the
20 * CDDL are applicable instead of those of the GPL.
21 *
22 * You may elect to license modified versions of this file under the
23 * terms and conditions of either the GPL or the CDDL or both.
24 */
25
26#ifndef VBOX_INCLUDED_iommu_intel_h
27#define VBOX_INCLUDED_iommu_intel_h
28#ifndef RT_WITHOUT_PRAGMA_ONCE
29# pragma once
30#endif
31
32#include <iprt/types.h>
33#include <iprt/assertcompile.h>
34
35
36/**
37 * @name MMIO register offsets.
38 * In accordance with the AMD spec.
39 * @{
40 */
41#define VTD_MMIO_OFF_VERSION 0x000 /**< Version. */
42#define VTD_MMIO_OFF_CAP 0x008 /**< Capability. */
43#define VTD_MMIO_OFF_EXT_CAP 0x010 /**< Extended Capability. */
44#define VTD_MMIO_OFF_GLOBAL_CMD 0x018 /**< Global Command. */
45#define VTD_MMIO_OFF_GLOBAL_STATUS 0x01c /**< Global Status. */
46#define VTD_MMIO_OFF_ROOT_TBL_ADDR 0x020 /**< Root Table Address. */
47#define VTD_MMIO_OFF_CTX_CMD 0x028 /**< Context Command. */
48
49#define VTD_MMIO_OFF_FAULT_STATUS 0x034 /**< Fault Status.*/
50#define VTD_MMIO_OFF_FAULT_EVT_CTRL 0x038 /**< Fault Event Control.*/
51#define VTD_MMIO_OFF_FAULT_EVT_DATA 0x03c /**< Fault Event Data. */
52#define VTD_MMIO_OFF_FAULT_EVT_ADDR 0x040 /**< Fault Event Address. */
53#define VTD_MMIO_OFF_FAULT_EVT_UP_ADDR 0x044 /**< Fault Event Upper Address. */
54
55#define VTD_MMIO_OFF_ADV_FAULT_LOG 0x058 /**< Advance Fault Log. */
56
57#define VTD_MMIO_OFF_PROT_MEM_EN 0x064 /**< Protected Memory Enable (PMEN). */
58#define VTD_MMIO_OFF_PROT_LO_MEM_BASE 0x064 /**< Protected Low Memory Base. */
59#define VTD_MMIO_OFF_PROT_LO_MEM_LIMIT 0x068 /**< Protected Low Memory Limit. */
60#define VTD_MMIO_OFF_PROT_HI_MEM_BASE 0x070 /**< Protected High Memory Base. */
61#define VTD_MMIO_OFF_PROT_HI_MEM_LIMIT 0x078 /**< Protected High Memory Limit. */
62
63#define VTD_MMIO_OFF_INV_QUEUE_HEAD 0x080 /**< Invalidation Queue Head. */
64#define VTD_MMIO_OFF_INV_QUEUE_TAIL 0x088 /**< Invalidation Queue Tail. */
65#define VTD_MMIO_OFF_INV_QUEUE_ADDR 0x090 /**< Invalidation Queue Address. */
66#define VTD_MMIO_OFF_INV_COMP_STATUS 0x09c /**< Invalidation Completion Status. */
67#define VTD_MMIO_OFF_INV_COMP_EVT_CTRL 0x0a0 /**< Invalidation Completion Event Control. */
68#define VTD_MMIO_OFF_INV_COMP_EVT_DATA 0x0a4 /**< Invalidation Completion Event Data. */
69#define VTD_MMIO_OFF_INV_COMP_EVT_ADDR 0x0a8 /**< Invalidation Completion Event Address. */
70#define VTD_MMIO_OFF_INV_COMP_EVT_UP_ADDR 0x0ac /**< Invalidation Completion Event Upper Address. */
71#define VTD_MMIO_OFF_INV_QUEUE_ERR_RECORD 0x0b0 /**< Invalidation Completion Queue Error Record. */
72
73#define VTD_MMIO_OFF_IRT_ADDR 0x0b8 /**< Interrupt Remapping Table Address. */
74
75#define VTD_MMIO_OFF_PAGE_REQ_QUEUE_HEAD 0x0c0 /**< Page Request Queue Head. */
76#define VTD_MMIO_OFF_PAGE_REQ_QUEUE_TAIL 0x0c8 /**< Page Request Queue Tail. */
77#define VTD_MMIO_OFF_PAGE_REQ_STATUS 0x0dc /**< Page Request Status. */
78#define VTD_MMIO_OFF_PAGE_REQ_EVT_CTRL 0x0e0 /**< Page Request Event Control. */
79#define VTD_MMIO_OFF_PAGE_REQ_EVT_DATA 0x0e4 /**< Page Request Event Data. */
80#define VTD_MMIO_OFF_PAGE_REQ_EVT_ADDR 0x0e8 /**< Page Request Event Address. */
81#define VTD_MMIO_OFF_PAGE_REQ_EVT_UP_ADDR 0x0ec /**< Page Request Event Upper Address. */
82
83#define VTD_MMIO_OFF_MTRR_CAP 0x100 /**< MTRR Capabliity. */
84#define VTD_MMIO_OFF_MTRR_DEF_TYPE 0x108 /**< MTRR Default Type. */
85
86#define VTD_MMIO_OFF_MTRR_FIXED_00000 0x120 /**< Fixed-range MTRR Register for 64K at 00000. */
87#define VTD_MMIO_OFF_MTRR_FIXED_80000 0x128 /**< Fixed-range MTRR Register for 16K at 80000. */
88#define VTD_MMIO_OFF_MTRR_FIXED_A0000 0x130 /**< Fixed-range MTRR Register for 16K at a0000. */
89#define VTD_MMIO_OFF_MTRR_FIXED_C0000 0x138 /**< Fixed-range MTRR Register for 4K at c0000. */
90#define VTD_MMIO_OFF_MTRR_FIXED_C8000 0x140 /**< Fixed-range MTRR Register for 4K at c8000. */
91#define VTD_MMIO_OFF_MTRR_FIXED_D0000 0x148 /**< Fixed-range MTRR Register for 4K at d0000. */
92#define VTD_MMIO_OFF_MTRR_FIXED_D8000 0x150 /**< Fixed-range MTRR Register for 4K at d8000. */
93#define VTD_MMIO_OFF_MTRR_FIXED_E0000 0x158 /**< Fixed-range MTRR Register for 4K at e0000. */
94#define VTD_MMIO_OFF_MTRR_FIXED_E8000 0x160 /**< Fixed-range MTRR Register for 4K at e8000. */
95#define VTD_MMIO_OFF_MTRR_FIXED_F0000 0x168 /**< Fixed-range MTRR Register for 4K at f0000. */
96#define VTD_MMIO_OFF_MTRR_FIXED_F8000 0x170 /**< Fixed-range MTRR Register for 4K at f8000. */
97
98#define VTD_MMIO_OFF_MTRR_VAR_BASE_0 0x180 /**< Variable-range MTRR Base 0. */
99#define VTD_MMIO_OFF_MTRR_VAR_MASK_0 0x188 /**< Variable-range MTRR Mask 0. */
100#define VTD_MMIO_OFF_MTRR_VAR_BASE_1 0x190 /**< Variable-range MTRR Base 1. */
101#define VTD_MMIO_OFF_MTRR_VAR_MASK_1 0x198 /**< Variable-range MTRR Mask 1. */
102#define VTD_MMIO_OFF_MTRR_VAR_BASE_2 0x1a0 /**< Variable-range MTRR Base 2. */
103#define VTD_MMIO_OFF_MTRR_VAR_MASK_2 0x1a8 /**< Variable-range MTRR Mask 2. */
104#define VTD_MMIO_OFF_MTRR_VAR_BASE_3 0x1b0 /**< Variable-range MTRR Base 3. */
105#define VTD_MMIO_OFF_MTRR_VAR_MASK_3 0x1b8 /**< Variable-range MTRR Mask 3. */
106#define VTD_MMIO_OFF_MTRR_VAR_BASE_4 0x1c0 /**< Variable-range MTRR Base 4. */
107#define VTD_MMIO_OFF_MTRR_VAR_MASK_4 0x1c8 /**< Variable-range MTRR Mask 4. */
108#define VTD_MMIO_OFF_MTRR_VAR_BASE_5 0x1d0 /**< Variable-range MTRR Base 5. */
109#define VTD_MMIO_OFF_MTRR_VAR_MASK_5 0x1d8 /**< Variable-range MTRR Mask 5. */
110#define VTD_MMIO_OFF_MTRR_VAR_BASE_6 0x1e0 /**< Variable-range MTRR Base 6. */
111#define VTD_MMIO_OFF_MTRR_VAR_MASK_6 0x1e8 /**< Variable-range MTRR Mask 6. */
112#define VTD_MMIO_OFF_MTRR_VAR_BASE_7 0x1f0 /**< Variable-range MTRR Base 7. */
113#define VTD_MMIO_OFF_MTRR_VAR_MASK_7 0x1f8 /**< Variable-range MTRR Mask 7. */
114#define VTD_MMIO_OFF_MTRR_VAR_BASE_8 0x200 /**< Variable-range MTRR Base 8. */
115#define VTD_MMIO_OFF_MTRR_VAR_MASK_8 0x208 /**< Variable-range MTRR Mask 8. */
116#define VTD_MMIO_OFF_MTRR_VAR_BASE_9 0x210 /**< Variable-range MTRR Base 9. */
117#define VTD_MMIO_OFF_MTRR_VAR_MASK_9 0x218 /**< Variable-range MTRR Mask 9. */
118
119#define VTD_MMIO_OFF_VIRT_CMD_CAP 0xe00 /**< Virtual Command Capability. */
120#define VTD_MMIO_OFF_VIRT_CMD 0xe10 /**< Virtual Command. */
121#define VTD_MMIO_OFF_VIRT_CMD_RESP 0xe20 /**< Virtual Command Response. */
122/** @} */
123
124
125/** @name Root Entry.
126 * In accordance with the Intel spec.
127 * @{ */
128/** P: Present. */
129#define VTD_BF_0_ROOT_ENTRY_P_SHIFT 0
130#define VTD_BF_0_ROOT_ENTRY_P_MASK UINT64_C(0x0000000000000001)
131/** R: Reserved (bits 11:1). */
132#define VTD_BF_0_ROOT_ENTRY_RSVD_11_1_SHIFT 1
133#define VTD_BF_0_ROOT_ENTRY_RSVD_11_1_MASK UINT64_C(0x0000000000000ffe)
134/** CTP: Context-Table Pointer. */
135#define VTD_BF_0_ROOT_ENTRY_CTP_SHIFT 12
136#define VTD_BF_0_ROOT_ENTRY_CTP_MASK UINT64_C(0xfffffffffffff000)
137RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_ROOT_ENTRY_, UINT64_C(0), UINT64_MAX,
138 (P, RSVD_11_1, CTP));
139
140/** Root Entry. */
141typedef struct VTD_ROOT_ENTRY_T
142{
143 /** The qwords in the root entry. */
144 uint64_t au64[2];
145} VTD_ROOT_ENTRY_T;
146/** Pointer to a root entry. */
147typedef VTD_ROOT_ENTRY_T *PVTD_ROOT_ENTRY_T;
148/** Pointer to a const root entry. */
149typedef VTD_ROOT_ENTRY_T const *PCVTD_ROOT_ENTRY_T;
150/** @} */
151
152
153/** @name Scalable-mode Root Entry.
154 * In accordance with the Intel spec.
155 * @{ */
156/** LP: Lower Present. */
157#define VTD_BF_0_SM_ROOT_ENTRY_LP_SHIFT 0
158#define VTD_BF_0_SM_ROOT_ENTRY_LP_MASK UINT64_C(0x0000000000000001)
159/** R: Reserved (bits 11:1). */
160#define VTD_BF_0_SM_ROOT_ENTRY_RSVD_11_1_SHIFT 1
161#define VTD_BF_0_SM_ROOT_ENTRY_RSVD_11_1_MASK UINT64_C(0x0000000000000ffe)
162/** LCTP: Lower Context-Table Pointer */
163#define VTD_BF_0_SM_ROOT_ENTRY_LCTP_SHIFT 12
164#define VTD_BF_0_SM_ROOT_ENTRY_LCTP_MASK UINT64_C(0xfffffffffffff000)
165RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_SM_ROOT_ENTRY_, UINT64_C(0), UINT64_MAX,
166 (LP, RSVD_11_1, LCTP));
167
168/** UP: Upper Present. */
169#define VTD_BF_1_SM_ROOT_ENTRY_UP_SHIFT 0
170#define VTD_BF_1_SM_ROOT_ENTRY_UP_MASK UINT64_C(0x0000000000000001)
171/** R: Reserved (bits 11:1). */
172#define VTD_BF_1_SM_ROOT_ENTRY_RSVD_11_1_SHIFT 1
173#define VTD_BF_1_SM_ROOT_ENTRY_RSVD_11_1_MASK UINT64_C(0x0000000000000ffe)
174/** UCTP: Upper Context-Table Pointer. */
175#define VTD_BF_1_SM_ROOT_ENTRY_UCTP_SHIFT 12
176#define VTD_BF_1_SM_ROOT_ENTRY_UCTP_MASK UINT64_C(0xfffffffffffff000)
177RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_SM_ROOT_ENTRY_, UINT64_C(0), UINT64_MAX,
178 (UP, RSVD_11_1, UCTP));
179
180/** Scalable-mode root entry. */
181typedef struct VTD_SM_ROOT_ENTRY_T
182{
183 /** The lower scalable-mode root entry. */
184 uint64_t uLower;
185 /** The upper scalable-mode root entry. */
186 uint64_t uUpper;
187} VTD_SM_ROOT_ENTRY_T;
188/** Pointer to a scalable-mode root entry. */
189typedef VTD_SM_ROOT_ENTRY_T *PVTD_SM_ROOT_ENTRY_T;
190/** Pointer to a const scalable-mode root entry. */
191typedef VTD_SM_ROOT_ENTRY_T const *PCVTD_SM_ROOT_ENTRY_T;
192/** @} */
193
194
195/** @name Context Entry.
196 * In accordance with the Intel spec.
197 * @{ */
198/** P: Present. */
199#define VTD_BF_0_CONTEXT_ENTRY_P_SHIFT 0
200#define VTD_BF_0_CONTEXT_ENTRY_P_MASK UINT64_C(0x0000000000000001)
201/** FPD: Fault Processing Disable. */
202#define VTD_BF_0_CONTEXT_ENTRY_FPD_SHIFT 1
203#define VTD_BF_0_CONTEXT_ENTRY_FPD_MASK UINT64_C(0x0000000000000002)
204/** TT: Translation Type. */
205#define VTD_BF_0_CONTEXT_ENTRY_TT_SHIFT 2
206#define VTD_BF_0_CONTEXT_ENTRY_TT_MASK UINT64_C(0x000000000000000c)
207/** R: Reserved (bits 11:4). */
208#define VTD_BF_0_CONTEXT_ENTRY_RSVD_11_4_SHIFT 4
209#define VTD_BF_0_CONTEXT_ENTRY_RSVD_11_4_MASK UINT64_C(0x0000000000000ff0)
210/** SLPTPTR: Second Level Page Translation Pointer. */
211#define VTD_BF_0_CONTEXT_ENTRY_SLPTPTR_SHIFT 12
212#define VTD_BF_0_CONTEXT_ENTRY_SLPTPTR_MASK UINT64_C(0xfffffffffffff000)
213RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_CONTEXT_ENTRY_, UINT64_C(0), UINT64_MAX,
214 (P, FPD, TT, RSVD_11_4, SLPTPTR));
215
216/** AW: Address Width. */
217#define VTD_BF_1_CONTEXT_ENTRY_AW_SHIFT 0
218#define VTD_BF_1_CONTEXT_ENTRY_AW_MASK UINT64_C(0x0000000000000007)
219/** IGN: Ignored (bits 6:3). */
220#define VTD_BF_1_CONTEXT_ENTRY_IGN_6_3_SHIFT 3
221#define VTD_BF_1_CONTEXT_ENTRY_IGN_6_3_MASK UINT64_C(0x0000000000000078)
222/** R: Reserved (bit 7). */
223#define VTD_BF_1_CONTEXT_ENTRY_RSVD_7_SHIFT 7
224#define VTD_BF_1_CONTEXT_ENTRY_RSVD_7_MASK UINT64_C(0x0000000000000080)
225/** DID: Domain Identifier. */
226#define VTD_BF_1_CONTEXT_ENTRY_DID_SHIFT 8
227#define VTD_BF_1_CONTEXT_ENTRY_DID_MASK UINT64_C(0x0000000000ffff00)
228/** R: Reserved (bits 63:24). */
229#define VTD_BF_1_CONTEXT_ENTRY_RSVD_63_24_SHIFT 24
230#define VTD_BF_1_CONTEXT_ENTRY_RSVD_63_24_MASK UINT64_C(0xffffffffff000000)
231RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_CONTEXT_ENTRY_, UINT64_C(0), UINT64_MAX,
232 (AW, IGN_6_3, RSVD_7, DID, RSVD_63_24));
233
234/** Context Entry. */
235typedef struct VTD_CONTEXT_ENTRY_T
236{
237 /** The qwords in the context entry. */
238 uint64_t au64[2];
239} VTD_CONTEXT_ENTRY_T;
240/** Pointer to a context entry. */
241typedef VTD_CONTEXT_ENTRY_T *PVTD_CONTEXT_ENTRY_T;
242/** Pointer to a const context entry. */
243typedef VTD_CONTEXT_ENTRY_T const *PCVTD_CONTEXT_ENTRY_T;
244/** @} */
245
246
247/** @name Scalable-mode Context Entry.
248 * In accordance with the Intel spec.
249 * @{ */
250/** P: Present. */
251#define VTD_BF_0_SM_CONTEXT_ENTRY_P_SHIFT 0
252#define VTD_BF_0_SM_CONTEXT_ENTRY_P_MASK UINT64_C(0x0000000000000001)
253/** FPD: Fault Processing Disable. */
254#define VTD_BF_0_SM_CONTEXT_ENTRY_FPD_SHIFT 1
255#define VTD_BF_0_SM_CONTEXT_ENTRY_FPD_MASK UINT64_C(0x0000000000000002)
256/** DTE: Device-TLB Enable. */
257#define VTD_BF_0_SM_CONTEXT_ENTRY_DTE_SHIFT 2
258#define VTD_BF_0_SM_CONTEXT_ENTRY_DTE_MASK UINT64_C(0x0000000000000004)
259/** PASIDE: PASID Enable. */
260#define VTD_BF_0_SM_CONTEXT_ENTRY_PASIDE_SHIFT 3
261#define VTD_BF_0_SM_CONTEXT_ENTRY_PASIDE_MASK UINT64_C(0x0000000000000008)
262/** PRE: Page Request Enable. */
263#define VTD_BF_0_SM_CONTEXT_ENTRY_PRE_SHIFT 4
264#define VTD_BF_0_SM_CONTEXT_ENTRY_PRE_MASK UINT64_C(0x0000000000000010)
265/** R: Reserved (bits 8:5). */
266#define VTD_BF_0_SM_CONTEXT_ENTRY_RSVD_8_5_SHIFT 5
267#define VTD_BF_0_SM_CONTEXT_ENTRY_RSVD_8_5_MASK UINT64_C(0x00000000000001e0)
268/** PDTS: PASID Directory Size. */
269#define VTD_BF_0_SM_CONTEXT_ENTRY_PDTS_SHIFT 9
270#define VTD_BF_0_SM_CONTEXT_ENTRY_PDTS_MASK UINT64_C(0x0000000000000e00)
271/** PASIDDIRPTR: PASID Directory Pointer. */
272#define VTD_BF_0_SM_CONTEXT_ENTRY_PASIDDIRPTR_SHIFT 12
273#define VTD_BF_0_SM_CONTEXT_ENTRY_PASIDDIRPTR_MASK UINT64_C(0xfffffffffffff000)
274RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_SM_CONTEXT_ENTRY_, UINT64_C(0), UINT64_MAX,
275 (P, FPD, DTE, PASIDE, PRE, RSVD_8_5, PDTS, PASIDDIRPTR));
276
277/** RID_PASID: Requested Id to PASID assignment. */
278#define VTD_BF_1_SM_CONTEXT_ENTRY_RID_PASID_SHIFT 0
279#define VTD_BF_1_SM_CONTEXT_ENTRY_RID_PASID_MASK UINT64_C(0x00000000000fffff)
280/** RID_PRIV: Requested Id to PrivilegeModeRequested assignment. */
281#define VTD_BF_1_SM_CONTEXT_ENTRY_RID_PRIV_SHIFT 20
282#define VTD_BF_1_SM_CONTEXT_ENTRY_RID_PRIV_MASK UINT64_C(0x0000000000100000)
283/** R: Reserved (bits 63:21). */
284#define VTD_BF_1_SM_CONTEXT_ENTRY_RSVD_63_21_SHIFT 21
285#define VTD_BF_1_SM_CONTEXT_ENTRY_RSVD_63_21_MASK UINT64_C(0xffffffffffe00000)
286RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_SM_CONTEXT_ENTRY_, UINT64_C(0), UINT64_MAX,
287 (RID_PASID, RID_PRIV, RSVD_63_21));
288
289/** Context Entry. */
290typedef struct VTD_SM_CONTEXT_ENTRY_T
291{
292 /** The qwords in the scalable-mode context entry. */
293 uint64_t au64[4];
294} VTD_SM_CONTEXT_ENTRY_T;
295/** Pointer to a scalable-mode context entry. */
296typedef VTD_SM_CONTEXT_ENTRY_T *PVTD_SM_CONTEXT_ENTRY_T;
297/** Pointer to a const scalable-mode context entry. */
298typedef VTD_SM_CONTEXT_ENTRY_T const *PCVTD_SM_CONTEXT_ENTRY_T;
299/** @} */
300
301
302/** @name Scalable-mode PASID Directory Entry.
303 * In accordance with the Intel spec.
304 * @{ */
305/** P: Present. */
306#define VTD_BF_SM_PASID_DIR_ENTRY_P_SHIFT 0
307#define VTD_BF_SM_PASID_DIR_ENTRY_P_MASK UINT64_C(0x0000000000000001)
308/** FPD: Fault Processing Disable. */
309#define VTD_BF_SM_PASID_DIR_ENTRY_FPD_SHIFT 1
310#define VTD_BF_SM_PASID_DIR_ENTRY_FPD_MASK UINT64_C(0x0000000000000002)
311/** R: Reserved (bits 11:2). */
312#define VTD_BF_SM_PASID_DIR_ENTRY_RSVD_11_2_SHIFT 2
313#define VTD_BF_SM_PASID_DIR_ENTRY_RSVD_11_2_MASK UINT64_C(0x0000000000000ffc)
314/** SMPTBLPTR: Scalable Mode PASID Table Pointer. */
315#define VTD_BF_SM_PASID_DIR_ENTRY_SMPTBLPTR_SHIFT 12
316#define VTD_BF_SM_PASID_DIR_ENTRY_SMPTBLPTR_MASK UINT64_C(0xfffffffffffff000)
317RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_SM_PASID_DIR_ENTRY_, UINT64_C(0), UINT64_MAX,
318 (P, FPD, RSVD_11_2, SMPTBLPTR));
319
320/** Scalable-mode PASID Directory Entry. */
321typedef struct VTD_SM_PASID_DIR_ENTRY_T
322{
323 /** The scalable-mode PASID directory entry. */
324 uint64_t u;
325} VTD_SM_PASID_DIR_ENTRY_T;
326/** Pointer to a scalable-mode PASID directory entry. */
327typedef VTD_SM_PASID_DIR_ENTRY_T *PVTD_SM_PASID_DIR_ENTRY_T;
328/** Pointer to a const scalable-mode PASID directory entry. */
329typedef VTD_SM_PASID_DIR_ENTRY_T const *PCVTD_SM_PASID_DIR_ENTRY_T;
330/** @} */
331
332
333/** @name Scalable-mode PASID Table Entry.
334 * In accordance with the Intel spec.
335 * @{ */
336/** P: Present. */
337#define VTD_BF_0_SM_PASID_TBL_ENTRY_P_SHIFT 0
338#define VTD_BF_0_SM_PASID_TBL_ENTRY_P_MASK UINT64_C(0x0000000000000001)
339/** FPD: Fault Processing Disable. */
340#define VTD_BF_0_SM_PASID_TBL_ENTRY_FPD_SHIFT 1
341#define VTD_BF_0_SM_PASID_TBL_ENTRY_FPD_MASK UINT64_C(0x0000000000000002)
342/** AW: Address Width. */
343#define VTD_BF_0_SM_PASID_TBL_ENTRY_AW_SHIFT 2
344#define VTD_BF_0_SM_PASID_TBL_ENTRY_AW_MASK UINT64_C(0x000000000000001c)
345/** SLEE: Second-Level Execute Enable. */
346#define VTD_BF_0_SM_PASID_TBL_ENTRY_SLEE_SHIFT 5
347#define VTD_BF_0_SM_PASID_TBL_ENTRY_SLEE_MASK UINT64_C(0x0000000000000020)
348/** PGTT: PASID Granular Translation Type. */
349#define VTD_BF_0_SM_PASID_TBL_ENTRY_PGTT_SHIFT 6
350#define VTD_BF_0_SM_PASID_TBL_ENTRY_PGTT_MASK UINT64_C(0x00000000000001c0)
351/** SLADE: Second-Level Address/Dirty Enable. */
352#define VTD_BF_0_SM_PASID_TBL_ENTRY_SLADE_SHIFT 9
353#define VTD_BF_0_SM_PASID_TBL_ENTRY_SLADE_MASK UINT64_C(0x0000000000000200)
354/** R: Reserved (bits 11:10). */
355#define VTD_BF_0_SM_PASID_TBL_ENTRY_RSVD_11_10_SHIFT 10
356#define VTD_BF_0_SM_PASID_TBL_ENTRY_RSVD_11_10_MASK UINT64_C(0x0000000000000c00)
357/** SLPTPTR: Second-Level Page Table Pointer. */
358#define VTD_BF_0_SM_PASID_TBL_ENTRY_SLPTPTR_SHIFT 12
359#define VTD_BF_0_SM_PASID_TBL_ENTRY_SLPTPTR_MASK UINT64_C(0xfffffffffffff000)
360RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_SM_PASID_TBL_ENTRY_, UINT64_C(0), UINT64_MAX,
361 (P, FPD, AW, SLEE, PGTT, SLADE, RSVD_11_10, SLPTPTR));
362
363/** DID: Domain Identifer. */
364#define VTD_BF_1_SM_PASID_TBL_ENTRY_DID_SHIFT 0
365#define VTD_BF_1_SM_PASID_TBL_ENTRY_DID_MASK UINT64_C(0x000000000000ffff)
366/** R: Reserved (bits 22:16). */
367#define VTD_BF_1_SM_PASID_TBL_ENTRY_RSVD_22_16_SHIFT 16
368#define VTD_BF_1_SM_PASID_TBL_ENTRY_RSVD_22_16_MASK UINT64_C(0x00000000007f0000)
369/** PWSNP: Page-Walk Snoop. */
370#define VTD_BF_1_SM_PASID_TBL_ENTRY_PWSNP_SHIFT 23
371#define VTD_BF_1_SM_PASID_TBL_ENTRY_PWSNP_MASK UINT64_C(0x0000000000800000)
372/** PGSNP: Page Snoop. */
373#define VTD_BF_1_SM_PASID_TBL_ENTRY_PGSNP_SHIFT 24
374#define VTD_BF_1_SM_PASID_TBL_ENTRY_PGSNP_MASK UINT64_C(0x0000000001000000)
375/** CD: Cache Disable. */
376#define VTD_BF_1_SM_PASID_TBL_ENTRY_CD_SHIFT 25
377#define VTD_BF_1_SM_PASID_TBL_ENTRY_CD_MASK UINT64_C(0x0000000002000000)
378/** EMTE: Extended Memory Type Enable. */
379#define VTD_BF_1_SM_PASID_TBL_ENTRY_EMTE_SHIFT 26
380#define VTD_BF_1_SM_PASID_TBL_ENTRY_EMTE_MASK UINT64_C(0x0000000004000000)
381/** EMT: Extended Memory Type. */
382#define VTD_BF_1_SM_PASID_TBL_ENTRY_EMT_SHIFT 27
383#define VTD_BF_1_SM_PASID_TBL_ENTRY_EMT_MASK UINT64_C(0x0000000038000000)
384/** PWT: Page-Level Write Through. */
385#define VTD_BF_1_SM_PASID_TBL_ENTRY_PWT_SHIFT 30
386#define VTD_BF_1_SM_PASID_TBL_ENTRY_PWT_MASK UINT64_C(0x0000000040000000)
387/** PCD: Page-Level Cache Disable. */
388#define VTD_BF_1_SM_PASID_TBL_ENTRY_PCD_SHIFT 31
389#define VTD_BF_1_SM_PASID_TBL_ENTRY_PCD_MASK UINT64_C(0x0000000080000000)
390/** PAT: Page Attribute Table. */
391#define VTD_BF_1_SM_PASID_TBL_ENTRY_PAT_SHIFT 32
392#define VTD_BF_1_SM_PASID_TBL_ENTRY_PAT_MASK UINT64_C(0xffffffff00000000)
393RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_SM_PASID_TBL_ENTRY_, UINT64_C(0), UINT64_MAX,
394 (DID, RSVD_22_16, PWSNP, PGSNP, CD, EMTE, EMT, PWT, PCD, PAT));
395
396/** SRE: Supervisor Request Enable. */
397#define VTD_BF_2_SM_PASID_TBL_ENTRY_SRE_SHIFT 0
398#define VTD_BF_2_SM_PASID_TBL_ENTRY_SRE_MASK UINT64_C(0x0000000000000001)
399/** ERE: Execute Request Enable. */
400#define VTD_BF_2_SM_PASID_TBL_ENTRY_ERE_SHIFT 1
401#define VTD_BF_2_SM_PASID_TBL_ENTRY_ERE_MASK UINT64_C(0x0000000000000002)
402/** FLPM: First Level Paging Mode. */
403#define VTD_BF_2_SM_PASID_TBL_ENTRY_FLPM_SHIFT 2
404#define VTD_BF_2_SM_PASID_TBL_ENTRY_FLPM_MASK UINT64_C(0x000000000000000c)
405/** WPE: Write Protect Enable. */
406#define VTD_BF_2_SM_PASID_TBL_ENTRY_WPE_SHIFT 4
407#define VTD_BF_2_SM_PASID_TBL_ENTRY_WPE_MASK UINT64_C(0x0000000000000010)
408/** NXE: No-Execute Enable. */
409#define VTD_BF_2_SM_PASID_TBL_ENTRY_NXE_SHIFT 5
410#define VTD_BF_2_SM_PASID_TBL_ENTRY_NXE_MASK UINT64_C(0x0000000000000020)
411/** SMEP: Supervisor Mode Execute Prevent. */
412#define VTD_BF_2_SM_PASID_TBL_ENTRY_SMPE_SHIFT 6
413#define VTD_BF_2_SM_PASID_TBL_ENTRY_SMPE_MASK UINT64_C(0x0000000000000040)
414/** EAFE: Extended Accessed Flag Enable. */
415#define VTD_BF_2_SM_PASID_TBL_ENTRY_EAFE_SHIFT 7
416#define VTD_BF_2_SM_PASID_TBL_ENTRY_EAFE_MASK UINT64_C(0x0000000000000080)
417/** R: Reserved (bits 11:8). */
418#define VTD_BF_2_SM_PASID_TBL_ENTRY_RSVD_11_8_SHIFT 8
419#define VTD_BF_2_SM_PASID_TBL_ENTRY_RSVD_11_8_MASK UINT64_C(0x0000000000000f00)
420/** FLPTPTR: First Level Page Table Pointer. */
421#define VTD_BF_2_SM_PASID_TBL_ENTRY_FLPTPTR_SHIFT 12
422#define VTD_BF_2_SM_PASID_TBL_ENTRY_FLPTPTR_MASK UINT64_C(0xfffffffffffff000)
423RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_2_SM_PASID_TBL_ENTRY_, UINT64_C(0), UINT64_MAX,
424 (SRE, ERE, FLPM, WPE, NXE, SMPE, EAFE, RSVD_11_8, FLPTPTR));
425
426/** Scalable-mode PASID Table Entry. */
427typedef struct VTD_SM_PASID_TBL_ENTRY_T
428{
429 /** The qwords in the scalable-mode PASID table entry. */
430 uint64_t au64[8];
431} VTD_SM_PASID_TBL_ENTRY_T;
432/** Pointer to a scalable-mode PASID table entry. */
433typedef VTD_SM_PASID_TBL_ENTRY_T *PVTD_SM_PASID_TBL_ENTRY_T;
434/** Pointer to a const scalable-mode PASID table entry. */
435typedef VTD_SM_PASID_TBL_ENTRY_T const *PCVTD_SM_PASID_TBL_ENTRY_T;
436/** @} */
437
438
439/** @name First-Level Paging Entry.
440 * In accordance with the Intel spec.
441 * @{ */
442/** P: Present. */
443#define VTD_BF_FLP_ENTRY_P_SHIFT 0
444#define VTD_BF_FLP_ENTRY_P_MASK UINT64_C(0x0000000000000001)
445/** R/W: Read/Write. */
446#define VTD_BF_FLP_ENTRY_RW_SHIFT 1
447#define VTD_BF_FLP_ENTRY_RW_MASK UINT64_C(0x0000000000000002)
448/** U/S: User/Supervisor. */
449#define VTD_BF_FLP_ENTRY_US_SHIFT 2
450#define VTD_BF_FLP_ENTRY_US_MASK UINT64_C(0x0000000000000004)
451/** PWT: Page-Level Write Through. */
452#define VTD_BF_FLP_ENTRY_PWT_SHIFT 3
453#define VTD_BF_FLP_ENTRY_PWT_MASK UINT64_C(0x0000000000000008)
454/** PC: Page-Level Cache Disable. */
455#define VTD_BF_FLP_ENTRY_PCD_SHIFT 4
456#define VTD_BF_FLP_ENTRY_PCD_MASK UINT64_C(0x0000000000000010)
457/** A: Accessed. */
458#define VTD_BF_FLP_ENTRY_A_SHIFT 5
459#define VTD_BF_FLP_ENTRY_A_MASK UINT64_C(0x0000000000000020)
460/** IGN: Ignored (bit 6). */
461#define VTD_BF_FLP_ENTRY_IGN_6_SHIFT 6
462#define VTD_BF_FLP_ENTRY_IGN_6_MASK UINT64_C(0x0000000000000040)
463/** R: Reserved (bit 7). */
464#define VTD_BF_FLP_ENTRY_RSVD_7_SHIFT 7
465#define VTD_BF_FLP_ENTRY_RSVD_7_MASK UINT64_C(0x0000000000000080)
466/** IGN: Ignored (bits 9:8). */
467#define VTD_BF_FLP_ENTRY_IGN_9_8_SHIFT 8
468#define VTD_BF_FLP_ENTRY_IGN_9_8_MASK UINT64_C(0x0000000000000300)
469/** EA: Extended Accessed. */
470#define VTD_BF_FLP_ENTRY_EA_SHIFT 10
471#define VTD_BF_FLP_ENTRY_EA_MASK UINT64_C(0x0000000000000400)
472/** IGN: Ignored (bit 11). */
473#define VTD_BF_FLP_ENTRY_IGN_11_SHIFT 11
474#define VTD_BF_FLP_ENTRY_IGN_11_MASK UINT64_C(0x0000000000000800)
475/** ADDR: Address. */
476#define VTD_BF_FLP_ENTRY_ADDR_SHIFT 12
477#define VTD_BF_FLP_ENTRY_ADDR_MASK UINT64_C(0x000ffffffffff000)
478/** IGN: Ignored (bits 62:52). */
479#define VTD_BF_FLP_ENTRY_IGN_62_52_SHIFT 52
480#define VTD_BF_FLP_ENTRY_IGN_62_52_MASK UINT64_C(0x7ff0000000000000)
481/** XD: Execute Disabled. */
482#define VTD_BF_FLP_ENTRY_XD_SHIFT 63
483#define VTD_BF_FLP_ENTRY_XD_MASK UINT64_C(0x8000000000000000)
484RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_FLP_ENTRY_, UINT64_C(0), UINT64_MAX,
485 (P, RW, US, PWT, PCD, A, IGN_6, RSVD_7, IGN_9_8, EA, IGN_11, ADDR, IGN_62_52, XD));
486
487/** First-Level Paging Entry. */
488typedef struct VTD_FLP_ENTRY_T
489{
490 /** The first-level paging entry. */
491 uint64_t u;
492} VTD_FLP_ENTRY_T;
493/** Pointer to a first-level paging entry. */
494typedef VTD_FLP_ENTRY_T *PVTD_FLP_ENTRY_T;
495/** Pointer to a const first-level paging entry. */
496typedef VTD_FLP_ENTRY_T const *PCVTD_FLP_ENTRY_T;
497/** @} */
498
499
500/** @name Second-Level Paging Entry.
501 * In accordance with the Intel spec.
502 * @{ */
503/** R: Read. */
504#define VTD_BF_SLP_ENTRY_R_SHIFT 0
505#define VTD_BF_SLP_ENTRY_R_MASK UINT64_C(0x0000000000000001)
506/** W: Write. */
507#define VTD_BF_SLP_ENTRY_W_SHIFT 1
508#define VTD_BF_SLP_ENTRY_W_MASK UINT64_C(0x0000000000000002)
509/** X: Execute. */
510#define VTD_BF_SLP_ENTRY_X_SHIFT 2
511#define VTD_BF_SLP_ENTRY_X_MASK UINT64_C(0x0000000000000004)
512/** IGN: Ignored (bits 6:3). */
513#define VTD_BF_SLP_ENTRY_IGN_6_3_SHIFT 3
514#define VTD_BF_SLP_ENTRY_IGN_6_3_MASK UINT64_C(0x0000000000000078)
515/** R: Reserved (bit 7). */
516#define VTD_BF_SLP_ENTRY_RSVD_7_SHIFT 7
517#define VTD_BF_SLP_ENTRY_RSVD_7_MASK UINT64_C(0x0000000000000080)
518/** A: Accessed. */
519#define VTD_BF_SLP_ENTRY_A_SHIFT 8
520#define VTD_BF_SLP_ENTRY_A_MASK UINT64_C(0x0000000000000100)
521/** IGN: Ignored (bits 10:9). */
522#define VTD_BF_SLP_ENTRY_IGN_10_9_SHIFT 9
523#define VTD_BF_SLP_ENTRY_IGN_10_9_MASK UINT64_C(0x0000000000000600)
524/** R: Reserved (bit 11). */
525#define VTD_BF_SLP_ENTRY_RSVD_11_SHIFT 11
526#define VTD_BF_SLP_ENTRY_RSVD_11_MASK UINT64_C(0x0000000000000800)
527/** ADDR: Address. */
528#define VTD_BF_SLP_ENTRY_ADDR_SHIFT 12
529#define VTD_BF_SLP_ENTRY_ADDR_MASK UINT64_C(0x000ffffffffff000)
530/** IGN: Ignored (bits 61:52). */
531#define VTD_BF_SLP_ENTRY_IGN_61_52_SHIFT 52
532#define VTD_BF_SLP_ENTRY_IGN_61_52_MASK UINT64_C(0x3ff0000000000000)
533/** R: Reserved (bit 62). */
534#define VTD_BF_SLP_ENTRY_RSVD_62_SHIFT 62
535#define VTD_BF_SLP_ENTRY_RSVD_62_MASK UINT64_C(0x4000000000000000)
536/** IGN: Ignored (bit 63). */
537#define VTD_BF_SLP_ENTRY_IGN_63_SHIFT 63
538#define VTD_BF_SLP_ENTRY_IGN_63_MASK UINT64_C(0x8000000000000000)
539RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_SLP_ENTRY_, UINT64_C(0), UINT64_MAX,
540 (R, W, X, IGN_6_3, RSVD_7, A, IGN_10_9, RSVD_11, ADDR, IGN_61_52, RSVD_62, IGN_63));
541
542/** Second-Level Paging Entry. */
543typedef struct VTD_SLP_ENTRY_T
544{
545 /** The second-level paging entry. */
546 uint64_t u;
547} VTD_SLP_ENTRY_T;
548/** Pointer to a second-level paging entry. */
549typedef VTD_SLP_ENTRY_T *PVTD_SLP_ENTRY_T;
550/** Pointer to a const second-level paging entry. */
551typedef VTD_SLP_ENTRY_T const *PCVTD_SLP_ENTRY_T;
552/** @} */
553
554
555/** @name Fault Record.
556 * In accordance with the Intel spec.
557 * @{ */
558/** R: Reserved (bits 11:0). */
559#define VTD_BF_0_FAULT_RECORD_RSVD_11_0_SHIFT 0
560#define VTD_BF_0_FAULT_RECORD_RSVD_11_0_MASK UINT64_C(0x0000000000000fff)
561/** FI: Fault Information. */
562#define VTD_BF_0_FAULT_RECORD_FI_SHIFT 12
563#define VTD_BF_0_FAULT_RECORD_FI_MASK UINT64_C(0xfffffffffffff000)
564RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_FAULT_RECORD_, UINT64_C(0), UINT64_MAX,
565 (RSVD_11_0, FI));
566
567/** SID: Source identifier. */
568#define VTD_BF_1_FAULT_RECORD_SID_SHIFT 0
569#define VTD_BF_1_FAULT_RECORD_SID_MASK UINT64_C(0x000000000000ffff)
570/** R: Reserved (bits 28:16). */
571#define VTD_BF_1_FAULT_RECORD_RSVD_28_16_SHIFT 16
572#define VTD_BF_1_FAULT_RECORD_RSVD_28_16_MASK UINT64_C(0x000000001fff0000)
573/** PRIV: Privilege Mode Requested. */
574#define VTD_BF_1_FAULT_RECORD_PRIV_SHIFT 29
575#define VTD_BF_1_FAULT_RECORD_PRIV_MASK UINT64_C(0x0000000020000000)
576/** EXE: Execute Permission Requested. */
577#define VTD_BF_1_FAULT_RECORD_EXE_SHIFT 30
578#define VTD_BF_1_FAULT_RECORD_EXE_MASK UINT64_C(0x0000000040000000)
579/** PP: PASID Present. */
580#define VTD_BF_1_FAULT_RECORD_PP_SHIFT 31
581#define VTD_BF_1_FAULT_RECORD_PP_MASK UINT64_C(0x0000000080000000)
582/** FR: Fault Reason. */
583#define VTD_BF_1_FAULT_RECORD_FR_SHIFT 32
584#define VTD_BF_1_FAULT_RECORD_FR_MASK UINT64_C(0x000000ff00000000)
585/** PV: PASID Value. */
586#define VTD_BF_1_FAULT_RECORD_PV_SHIFT 40
587#define VTD_BF_1_FAULT_RECORD_PV_MASK UINT64_C(0x0fffff0000000000)
588/** AT: Address Type. */
589#define VTD_BF_1_FAULT_RECORD_AT_SHIFT 60
590#define VTD_BF_1_FAULT_RECORD_AT_MASK UINT64_C(0x3000000000000000)
591/** T: Type. */
592#define VTD_BF_1_FAULT_RECORD_T_SHIFT 62
593#define VTD_BF_1_FAULT_RECORD_T_MASK UINT64_C(0x4000000000000000)
594/** R: Reserved (bit 127). */
595#define VTD_BF_1_FAULT_RECORD_RSVD_63_SHIFT 63
596#define VTD_BF_1_FAULT_RECORD_RSVD_63_MASK UINT64_C(0x8000000000000000)
597RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_FAULT_RECORD_, UINT64_C(0), UINT64_MAX,
598 (SID, RSVD_28_16, PRIV, EXE, PP, FR, PV, AT, T, RSVD_63));
599
600/** Fault record. */
601typedef struct VTD_FAULT_RECORD_T
602{
603 /** The qwords in the fault record. */
604 uint64_t au64[2];
605} VTD_FAULT_RECORD_T;
606/** Pointer to a fault record. */
607typedef VTD_FAULT_RECORD_T *PVTD_FAULT_RECORD_T;
608/** Pointer to a const fault record. */
609typedef VTD_FAULT_RECORD_T const *PCVTD_FAULT_RECORD_T;
610/** @} */
611
612
613/** @name Interrupt Remapping Table Entry (IRTE) for Remapped Interrupts.
614 * In accordance with the Intel spec.
615 * @{ */
616/** P: Present. */
617#define VTD_BF_0_IRTE_P_SHIFT 0
618#define VTD_BF_0_IRTE_P_MASK UINT64_C(0x0000000000000001)
619/** FPD: Fault Processing Disable. */
620#define VTD_BF_0_IRTE_FPD_SHIFT 1
621#define VTD_BF_0_IRTE_FPD_MASK UINT64_C(0x0000000000000002)
622/** DM: Destination Mode (0=physical, 1=logical). */
623#define VTD_BF_0_IRTE_DM_SHIFT 2
624#define VTD_BF_0_IRTE_DM_MASK UINT64_C(0x0000000000000004)
625/** RH: Redirection Hint. */
626#define VTD_BF_0_IRTE_RH_SHIFT 3
627#define VTD_BF_0_IRTE_RH_MASK UINT64_C(0x0000000000000008)
628/** TM: Trigger Mode. */
629#define VTD_BF_0_IRTE_TM_SHIFT 4
630#define VTD_BF_0_IRTE_TM_MASK UINT64_C(0x0000000000000010)
631/** DLM: Delivery Mode. */
632#define VTD_BF_0_IRTE_DLM_SHIFT 5
633#define VTD_BF_0_IRTE_DLM_MASK UINT64_C(0x00000000000000e0)
634/** AVL: Available. */
635#define VTD_BF_0_IRTE_AVAIL_SHIFT 8
636#define VTD_BF_0_IRTE_AVAIL_MASK UINT64_C(0x0000000000000f00)
637/** R: Reserved (bits 14:12). */
638#define VTD_BF_0_IRTE_RSVD_14_12_SHIFT 12
639#define VTD_BF_0_IRTE_RSVD_14_12_MASK UINT64_C(0x0000000000007000)
640/** IM: IRTE Mode. */
641#define VTD_BF_0_IRTE_IM_SHIFT 15
642#define VTD_BF_0_IRTE_IM_MASK UINT64_C(0x0000000000008000)
643/** V: Vector. */
644#define VTD_BF_0_IRTE_V_SHIFT 16
645#define VTD_BF_0_IRTE_V_MASK UINT64_C(0x0000000000ff0000)
646/** R: Reserved (bits 31:24). */
647#define VTD_BF_0_IRTE_RSVD_31_24_SHIFT 24
648#define VTD_BF_0_IRTE_RSVD_31_24_MASK UINT64_C(0x00000000ff000000)
649/** DST: Desination Id. */
650#define VTD_BF_0_IRTE_DST_SHIFT 32
651#define VTD_BF_0_IRTE_DST_MASK UINT64_C(0xffffffff00000000)
652RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_IRTE_, UINT64_C(0), UINT64_MAX,
653 (P, FPD, DM, RH, TM, DLM, AVAIL, RSVD_14_12, IM, V, RSVD_31_24, DST));
654
655/** SID: Source Identifier. */
656#define VTD_BF_1_IRTE_SID_SHIFT 0
657#define VTD_BF_1_IRTE_SID_MASK UINT64_C(0x000000000000ffff)
658/** SQ: Source-Id Qualifier. */
659#define VTD_BF_1_IRTE_SQ_SHIFT 16
660#define VTD_BF_1_IRTE_SQ_MASK UINT64_C(0x0000000000030000)
661/** SVT: Source Validation Type. */
662#define VTD_BF_1_IRTE_SVT_SHIFT 18
663#define VTD_BF_1_IRTE_SVT_MASK UINT64_C(0x00000000000c0000)
664/** R: Reserved (bits 127:84). */
665#define VTD_BF_1_IRTE_RSVD_63_20_SHIFT 20
666#define VTD_BF_1_IRTE_RSVD_63_20_MASK UINT64_C(0xfffffffffff00000)
667RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_IRTE_, UINT64_C(0), UINT64_MAX,
668 (SID, SQ, SVT, RSVD_63_20));
669
670/** Interrupt Remapping Table Entry (IRTE) for remapped interrupts. */
671typedef struct VTD_IRTE_T
672{
673 /** The qwords in the IRTE. */
674 uint64_t au64[2];
675} VTD_IRTE_T;
676/** Pointer to an IRTE. */
677typedef VTD_IRTE_T *PVTD_IRTE_T;
678/** Pointer to a const IRTE. */
679typedef VTD_IRTE_T const *PCVTD_IRTE_T;
680/** @} */
681
682
683/** @name Version Register (VER_REG).
684 * @{ */
685/** Min: Minor Version Number. */
686#define VTX_BF_VER_REG_MIN_SHIFT 0
687#define VTX_BF_VER_REG_MIN_MASK UINT32_C(0x0000000f)
688/** Max: Major Version Number. */
689#define VTX_BF_VER_REG_MAX_SHIFT 4
690#define VTX_BF_VER_REG_MAX_MASK UINT32_C(0x000000f0)
691/** R: Reserved (bits 31:8). */
692#define VTX_BF_VER_REG_RSVD_31_8_SHIFT 8
693#define VTX_BF_VER_REG_RSVD_31_8_MASK UINT32_C(0xffffff00)
694RT_BF_ASSERT_COMPILE_CHECKS(VTX_BF_VER_REG_, UINT32_C(0), UINT32_MAX,
695 (MIN, MAX, RSVD_31_8));
696/** @} */
697
698
699/** @name Capability Register (CAP_REG).
700 * @{ */
701/** ND: Number of domains supported. */
702#define VTD_BF_CAP_REG_ND_SHIFT 0
703#define VTD_BF_CAP_REG_ND_MASK UINT64_C(0x0000000000000007)
704/** AFL: Advanced Fault Logging. */
705#define VTD_BF_CAP_REG_AFL_SHIFT 3
706#define VTD_BF_CAP_REG_AFL_MASK UINT64_C(0x0000000000000008)
707/** RWBF: Required Write-Buffer Flushing. */
708#define VTD_BF_CAP_REG_RWBF_SHIFT 4
709#define VTD_BF_CAP_REG_RWBF_MASK UINT64_C(0x0000000000000010)
710/** PLMR: Protected Low-Memory Region. */
711#define VTD_BF_CAP_REG_PLMR_SHIFT 5
712#define VTD_BF_CAP_REG_PLMR_MASK UINT64_C(0x0000000000000020)
713/** PHMR: Protected High-Memory Region. */
714#define VTD_BF_CAP_REG_PHMR_SHIFT 6
715#define VTD_BF_CAP_REG_PHMR_MASK UINT64_C(0x0000000000000040)
716/** CM: Caching Mode. */
717#define VTD_BF_CAP_REG_CM_SHIFT 7
718#define VTD_BF_CAP_REG_CM_MASK UINT64_C(0x0000000000000080)
719/** SAGAW: Supported Adjusted Guest Address Widths. */
720#define VTD_BF_CAP_REG_SAGAW_SHIFT 8
721#define VTD_BF_CAP_REG_SAGAW_MASK UINT64_C(0x0000000000001f00)
722/** R: Reserved (bits 15:13). */
723#define VTD_BF_CAP_REG_RSVD_15_13_SHIFT 13
724#define VTD_BF_CAP_REG_RSVD_15_13_MASK UINT64_C(0x000000000000e000)
725/** MGAW: Maximum Guest Address Width. */
726#define VTD_BF_CAP_REG_MGAW_SHIFT 16
727#define VTD_BF_CAP_REG_MGAW_MASK UINT64_C(0x00000000003f0000)
728/** ZLR: Zero Length Read. */
729#define VTD_BF_CAP_REG_ZLR_SHIFT 22
730#define VTD_BF_CAP_REG_ZLR_MASK UINT64_C(0x0000000000400000)
731/** DEP: Deprecated MBZ. Reserved (bit 23). */
732#define VTD_BF_CAP_REG_RSVD_23_SHIFT 23
733#define VTD_BF_CAP_REG_RSVD_23_MASK UINT64_C(0x0000000000800000)
734/** FRO: Fault-recording Register Offset. */
735#define VTD_BF_CAP_REG_FRO_SHIFT 24
736#define VTD_BF_CAP_REG_FRO_MASK UINT64_C(0x00000003ff000000)
737/** SLLPS: Second Level Large Page Support. */
738#define VTD_BF_CAP_REG_SLLPS_SHIFT 34
739#define VTD_BF_CAP_REG_SLLPS_MASK UINT64_C(0x0000003c00000000)
740/** R: Reserved (bit 38). */
741#define VTD_BF_CAP_REG_RSVD_38_SHIFT 38
742#define VTD_BF_CAP_REG_RSVD_38_MASK UINT64_C(0x0000004000000000)
743/** PSI: Page Selective Invalidation. */
744#define VTD_BF_CAP_REG_PSI_SHIFT 39
745#define VTD_BF_CAP_REG_PSI_MASK UINT64_C(0x0000008000000000)
746/** NFR: Number of Fault-recording Registers. */
747#define VTD_BF_CAP_REG_NFR_SHIFT 40
748#define VTD_BF_CAP_REG_NFR_MASK UINT64_C(0x0000ff0000000000)
749/** MAMV: Maximum Address Mask Value. */
750#define VTD_BF_CAP_REG_MAMV_SHIFT 48
751#define VTD_BF_CAP_REG_MAMV_MASK UINT64_C(0x003f000000000000)
752/** DWD: Write Draining. */
753#define VTD_BF_CAP_REG_DWD_SHIFT 54
754#define VTD_BF_CAP_REG_DWD_MASK UINT64_C(0x0040000000000000)
755/** DRD: Read Draining. */
756#define VTD_BF_CAP_REG_DRD_SHIFT 55
757#define VTD_BF_CAP_REG_DRD_MASK UINT64_C(0x0080000000000000)
758/** FL1GP: First Level 1 GB Page Support. */
759#define VTD_BF_CAP_REG_FL1GP_SHIFT 56
760#define VTD_BF_CAP_REG_FL1GP_MASK UINT64_C(0x0100000000000000)
761/** R: Reserved (bits 58:57). */
762#define VTD_BF_CAP_REG_RSVD_58_57_SHIFT 57
763#define VTD_BF_CAP_REG_RSVD_58_57_MASK UINT64_C(0x0600000000000000)
764/** PI: Posted Interrupt Support. */
765#define VTD_BF_CAP_REG_PI_SHIFT 59
766#define VTD_BF_CAP_REG_PI_MASK UINT64_C(0x0800000000000000)
767/** FL5LP: First Level 5-level Paging Support. */
768#define VTD_BF_CAP_REG_FL5LP_SHIFT 60
769#define VTD_BF_CAP_REG_FL5LP_MASK UINT64_C(0x1000000000000000)
770/** R: Reserved (bits 63:61). */
771#define VTD_BF_CAP_REG_RSVD_63_61_SHIFT 61
772#define VTD_BF_CAP_REG_RSVD_63_61_MASK UINT64_C(0xe000000000000000)
773RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_CAP_REG_, UINT64_C(0), UINT64_MAX,
774 (ND, AFL, RWBF, PLMR, PHMR, CM, SAGAW, RSVD_15_13, MGAW, ZLR, RSVD_23, FRO, SLLPS, RSVD_38, PSI, NFR,
775 MAMV, DWD, DRD, FL1GP, RSVD_58_57, PI, FL5LP, RSVD_63_61));
776/** @} */
777
778
779/** @name Extended Capability Register (ECAP_REG).
780 * @{ */
781/** C: Page-walk Coherence. */
782#define VTD_BF_ECAP_REG_C_SHIFT 0
783#define VTD_BF_ECAP_REG_C_MASK UINT64_C(0x0000000000000001)
784/** QI: Queued Invalidation Support. */
785#define VTD_BF_ECAP_REG_QI_SHIFT 1
786#define VTD_BF_ECAP_REG_QI_MASK UINT64_C(0x0000000000000002)
787/** DT: Device-TLB Support. */
788#define VTD_BF_ECAP_REG_DT_SHIFT 2
789#define VTD_BF_ECAP_REG_DT_MASK UINT64_C(0x0000000000000004)
790/** IR: Interrupt Remapping Support. */
791#define VTD_BF_ECAP_REG_IR_SHIFT 3
792#define VTD_BF_ECAP_REG_IR_MASK UINT64_C(0x0000000000000008)
793/** EIM: Extended Interrupt Mode. */
794#define VTD_BF_ECAP_REG_EIM_SHIFT 4
795#define VTD_BF_ECAP_REG_EIM_MASK UINT64_C(0x0000000000000010)
796/** DEP: Deprecated MBZ. Reserved (bit 5). */
797#define VTD_BF_ECAP_REG_RSVD_5_SHIFT 5
798#define VTD_BF_ECAP_REG_RSVD_5_MASK UINT64_C(0x0000000000000020)
799/** PT: Pass Through. */
800#define VTD_BF_ECAP_REG_PT_SHIFT 6
801#define VTD_BF_ECAP_REG_PT_MASK UINT64_C(0x0000000000000040)
802/** SC: Snoop Control. */
803#define VTD_BF_ECAP_REG_SC_SHIFT 7
804#define VTD_BF_ECAP_REG_SC_MASK UINT64_C(0x0000000000000080)
805/** IRO: IOTLB Register Offset. */
806#define VTD_BF_ECAP_REG_IRO_SHIFT 8
807#define VTD_BF_ECAP_REG_IRO_MASK UINT64_C(0x000000000003ff00)
808/** R: Reserved (bits 19:18). */
809#define VTD_BF_ECAP_REG_RSVD_19_18_SHIFT 18
810#define VTD_BF_ECAP_REG_RSVD_19_18_MASK UINT64_C(0x00000000000c0000)
811/** MHMV: Maximum Handle Mask Value. */
812#define VTD_BF_ECAP_REG_MHMV_SHIFT 20
813#define VTD_BF_ECAP_REG_MHMV_MASK UINT64_C(0x0000000000f00000)
814/** DEP: Deprecated MBZ. Reserved (bit 24). */
815#define VTD_BF_ECAP_REG_RSVD_24_SHIFT 24
816#define VTD_BF_ECAP_REG_RSVD_24_MASK UINT64_C(0x0000000001000000)
817/** MTS: Memory Type Support. */
818#define VTD_BF_ECAP_REG_MTS_SHIFT 25
819#define VTD_BF_ECAP_REG_MTS_MASK UINT64_C(0x0000000002000000)
820/** NEST: Nested Translation Support. */
821#define VTD_BF_ECAP_REG_NEST_SHIFT 26
822#define VTD_BF_ECAP_REG_NEST_MASK UINT64_C(0x0000000004000000)
823/** R: Reserved (bit 27). */
824#define VTD_BF_ECAP_REG_RSVD_27_SHIFT 27
825#define VTD_BF_ECAP_REG_RSVD_27_MASK UINT64_C(0x0000000008000000)
826/** DEP: Deprecated MBZ. Reserved (bit 28). */
827#define VTD_BF_ECAP_REG_RSVD_28_SHIFT 28
828#define VTD_BF_ECAP_REG_RSVD_28_MASK UINT64_C(0x0000000010000000)
829/** PRS: Page Request Support. */
830#define VTD_BF_ECAP_REG_PRS_SHIFT 29
831#define VTD_BF_ECAP_REG_PRS_MASK UINT64_C(0x0000000020000000)
832/** ERS: Execute Request Support. */
833#define VTD_BF_ECAP_REG_ERS_SHIFT 30
834#define VTD_BF_ECAP_REG_ERS_MASK UINT64_C(0x0000000040000000)
835/** SRS: Supervisor Request Support. */
836#define VTD_BF_ECAP_REG_SRS_SHIFT 31
837#define VTD_BF_ECAP_REG_SRS_MASK UINT64_C(0x0000000080000000)
838/** R: Reserved (bit 32). */
839#define VTD_BF_ECAP_REG_RSVD_32_SHIFT 32
840#define VTD_BF_ECAP_REG_RSVD_32_MASK UINT64_C(0x0000000100000000)
841/** NWFS: No Write Flag Support. */
842#define VTD_BF_ECAP_REG_NWFS_SHIFT 33
843#define VTD_BF_ECAP_REG_NWFS_MASK UINT64_C(0x0000000200000000)
844/** EAFS: Extended Accessed Flags Support. */
845#define VTD_BF_ECAP_REG_EAFS_SHIFT 34
846#define VTD_BF_ECAP_REG_EAFS_MASK UINT64_C(0x0000000400000000)
847/** PSS: PASID Size Supported. */
848#define VTD_BF_ECAP_REG_PSS_SHIFT 35
849#define VTD_BF_ECAP_REG_PSS_MASK UINT64_C(0x000000f800000000)
850/** PASID: Process Address Space ID Support. */
851#define VTD_BF_ECAP_REG_PASID_SHIFT 40
852#define VTD_BF_ECAP_REG_PASID_MASK UINT64_C(0x0000010000000000)
853/** DIT: Device-TLB Invalidation Throttle. */
854#define VTD_BF_ECAP_REG_DIT_SHIFT 41
855#define VTD_BF_ECAP_REG_DIT_MASK UINT64_C(0x0000020000000000)
856/** PDS: Page-request Drain Support. */
857#define VTD_BF_ECAP_REG_PDS_SHIFT 42
858#define VTD_BF_ECAP_REG_PDS_MASK UINT64_C(0x0000040000000000)
859/** SMTS: Scalable-Mode Translation Support. */
860#define VTD_BF_ECAP_REG_SMTS_SHIFT 43
861#define VTD_BF_ECAP_REG_SMTS_MASK UINT64_C(0x0000080000000000)
862/** VCS: Virtual Command Support. */
863#define VTD_BF_ECAP_REG_VCS_SHIFT 44
864#define VTD_BF_ECAP_REG_VCS_MASK UINT64_C(0x0000100000000000)
865/** SLADS: Second-Level Accessed/Dirty Support. */
866#define VTD_BF_ECAP_REG_SLADS_SHIFT 45
867#define VTD_BF_ECAP_REG_SLADS_MASK UINT64_C(0x0000200000000000)
868/** SLTS: Second-Level Translation Support. */
869#define VTD_BF_ECAP_REG_SLTS_SHIFT 46
870#define VTD_BF_ECAP_REG_SLTS_MASK UINT64_C(0x0000400000000000)
871/** FLTS: First-Level Translation Support. */
872#define VTD_BF_ECAP_REG_FLTS_SHIFT 47
873#define VTD_BF_ECAP_REG_FLTS_MASK UINT64_C(0x0000800000000000)
874/** SMPWCS: Scalable-Mode Page-Walk Coherency Support. */
875#define VTD_BF_ECAP_REG_SMPWCS_SHIFT 48
876#define VTD_BF_ECAP_REG_SMPWCS_MASK UINT64_C(0x0001000000000000)
877/** RPS: RID-PASID Support. */
878#define VTD_BF_ECAP_REG_RPS_SHIFT 49
879#define VTD_BF_ECAP_REG_RPS_MASK UINT64_C(0x0002000000000000)
880/** R: Reserved (bits 63:50). */
881#define VTD_BF_ECAP_REG_RSVD_63_50_SHIFT 50
882#define VTD_BF_ECAP_REG_RSVD_63_50_MASK UINT64_C(0xfffc000000000000)
883RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_ECAP_REG_, UINT64_C(0), UINT64_MAX,
884 (C, QI, DT, IR, EIM, RSVD_5, PT, SC, IRO, RSVD_19_18, MHMV, RSVD_24, MTS, NEST, RSVD_27, RSVD_28,
885 PRS, ERS, SRS, RSVD_32, NWFS, EAFS, PSS, PASID, DIT, PDS, SMTS, VCS, SLADS, SLTS, FLTS, SMPWCS, RPS,
886 RSVD_63_50));
887/** @} */
888
889
890/** @name Global Command Register (GCMD_REG).
891 * @{ */
892/** R: Reserved (bits 22:0). */
893#define VTD_BF_GCMD_REG_RSVD_22_0_SHIFT 0
894#define VTD_BF_GCMD_REG_RSVD_22_0_MASK UINT32_C(0x007fffff)
895/** CFI: Compatibility Format Interrupt. */
896#define VTD_BF_GCMD_REG_CFI_SHIFT 23
897#define VTD_BF_GCMD_REG_CFI_MASK UINT32_C(0x00800000)
898/** SIRTP: Set Interrupt Table Remap Pointer. */
899#define VTD_BF_GCMD_REG_SIRTP_SHIFT 24
900#define VTD_BF_GCMD_REG_SIRTP_MASK UINT32_C(0x01000000)
901/** IRE: Interrupt Remap Enable. */
902#define VTD_BF_GCMD_REG_IRE_SHIFT 25
903#define VTD_BF_GCMD_REG_IRE_MASK UINT32_C(0x02000000)
904/** QIE: Queued Invalidation Enable. */
905#define VTD_BF_GCMD_REG_QIE_SHIFT 26
906#define VTD_BF_GCMD_REG_QIE_MASK UINT32_C(0x04000000)
907/** WBF: Write Buffer Flush. */
908#define VTD_BF_GCMD_REG_WBF_SHIFT 27
909#define VTD_BF_GCMD_REG_WBF_MASK UINT32_C(0x08000000)
910/** EAFL: Enable Advance Fault Logging. */
911#define VTD_BF_GCMD_REG_EAFL_SHIFT 28
912#define VTD_BF_GCMD_REG_EAFL_MASK UINT32_C(0x10000000)
913/** SFL: Set Fault Log. */
914#define VTD_BF_GCMD_REG_SFL_SHIFT 29
915#define VTD_BF_GCMD_REG_SFL_MASK UINT32_C(0x20000000)
916/** SRTP: Set Root Table Pointer. */
917#define VTD_BF_GCMD_REG_SRTP_SHIFT 30
918#define VTD_BF_GCMD_REG_SRTP_MASK UINT32_C(0x40000000)
919/** TE: Translation Enable. */
920#define VTD_BF_GCMD_REG_TE_SHIFT 31
921#define VTD_BF_GCMD_REG_TE_MASK UINT32_C(0x80000000)
922RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_GCMD_REG_, UINT32_C(0), UINT32_MAX,
923 (RSVD_22_0, CFI, SIRTP, IRE, QIE, WBF, EAFL, SFL, SRTP, TE));
924/** @} */
925
926
927/** @name Global Status Register (GSTS_REG).
928 * @{ */
929/** R: Reserved (bits 22:0). */
930#define VTD_BF_GSTS_REG_RSVD_22_0_SHIFT 0
931#define VTD_BF_GSTS_REG_RSVD_22_0_MASK UINT32_C(0x007fffff)
932/** CFIS: Compatibility Format Interrupt Status. */
933#define VTD_BF_GSTS_REG_CFIS_SHIFT 23
934#define VTD_BF_GSTS_REG_CFIS_MASK UINT32_C(0x00800000)
935/** IRTPS: Interrupt Remapping Table Pointer Status. */
936#define VTD_BF_GSTS_REG_IRTPS_SHIFT 24
937#define VTD_BF_GSTS_REG_IRTPS_MASK UINT32_C(0x01000000)
938/** IRES: Interrupt Remapping Enable Status. */
939#define VTD_BF_GSTS_REG_IRES_SHIFT 25
940#define VTD_BF_GSTS_REG_IRES_MASK UINT32_C(0x02000000)
941/** QIES: Queued Invalidation Enable Status. */
942#define VTD_BF_GSTS_REG_QIES_SHIFT 26
943#define VTD_BF_GSTS_REG_QIES_MASK UINT32_C(0x04000000)
944/** WBFS: Write Buffer Flush Status. */
945#define VTD_BF_GSTS_REG_WBFS_SHIFT 27
946#define VTD_BF_GSTS_REG_WBFS_MASK UINT32_C(0x08000000)
947/** AFLS: Advanced Fault Logging Status. */
948#define VTD_BF_GSTS_REG_AFLS_SHIFT 28
949#define VTD_BF_GSTS_REG_AFLS_MASK UINT32_C(0x10000000)
950/** FLS: Fault Log Status. */
951#define VTD_BF_GSTS_REG_FLS_SHIFT 29
952#define VTD_BF_GSTS_REG_FLS_MASK UINT32_C(0x20000000)
953/** RTPS: Root Table Pointer Status. */
954#define VTD_BF_GSTS_REG_RTPS_SHIFT 30
955#define VTD_BF_GSTS_REG_RTPS_MASK UINT32_C(0x40000000)
956/** TES: Translation Enable Status. */
957#define VTD_BF_GSTS_REG_TES_SHIFT 31
958#define VTD_BF_GSTS_REG_TES_MASK UINT32_C(0x80000000)
959RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_GSTS_REG_, UINT32_C(0), UINT32_MAX,
960 (RSVD_22_0, CFIS, IRTPS, IRES, QIES, WBFS, AFLS, FLS, RTPS, TES));
961/** @} */
962
963
964/** @name Root Table Address Register (RTADDR_REG).
965 * @{ */
966/** R: Reserved (bits 9:0). */
967#define VTD_BF_RTADDR_REG_RSVD_9_0_SHIFT 0
968#define VTD_BF_RTADDR_REG_RSVD_9_0_MASK UINT64_C(0x00000000000003ff)
969/** TTM: Translation Table Mode. */
970#define VTD_BF_RTADDR_REG_TTM_SHIFT 10
971#define VTD_BF_RTADDR_REG_TTM_MASK UINT64_C(0x0000000000000c00)
972/** RTA: Root Table Address. */
973#define VTD_BF_RTADDR_REG_RTA_SHIFT 12
974#define VTD_BF_RTADDR_REG_RTA_MASK UINT64_C(0xfffffffffffff000)
975RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_RTADDR_REG_, UINT64_C(0), UINT64_MAX,
976 (RSVD_9_0, TTM, RTA));
977/** @} */
978
979
980/** @name Context Command Register (CCMD_REG).
981 * @{ */
982/** DID: Domain-ID. */
983#define VTD_BF_CCMD_REG_DID_SHIFT 0
984#define VTD_BF_CCMD_REG_DID_MASK UINT64_C(0x000000000000ffff)
985/** SID: Source-ID. */
986#define VTD_BF_CCMD_REG_SID_SHIFT 16
987#define VTD_BF_CCMD_REG_SID_MASK UINT64_C(0x00000000ffff0000)
988/** FM: Function Mask. */
989#define VTD_BF_CCMD_REG_FM_SHIFT 32
990#define VTD_BF_CCMD_REG_FM_MASK UINT64_C(0x0000000300000000)
991/** R: Reserved (bits 58:34). */
992#define VTD_BF_CCMD_REG_RSVD_58_34_SHIFT 34
993#define VTD_BF_CCMD_REG_RSVD_58_34_MASK UINT64_C(0x07fffffc00000000)
994/** CAIG: Context Actual Invalidation Granularity. */
995#define VTD_BF_CCMD_REG_CAIG_SHIFT 59
996#define VTD_BF_CCMD_REG_CAIG_MASK UINT64_C(0x1800000000000000)
997/** CIRG: Context Invalidation Request Granularity. */
998#define VTD_BF_CCMD_REG_CIRG_SHIFT 61
999#define VTD_BF_CCMD_REG_CIRG_MASK UINT64_C(0x6000000000000000)
1000/** ICC: Invalidation Context Cache. */
1001#define VTD_BF_CCMD_REG_ICC_SHIFT 63
1002#define VTD_BF_CCMD_REG_ICC_MASK UINT64_C(0x8000000000000000)
1003RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_CCMD_REG_, UINT64_C(0), UINT64_MAX,
1004 (DID, SID, FM, RSVD_58_34, CAIG, CIRG, ICC));
1005/** @} */
1006
1007
1008/** @name IOTLB Invalidation Register (IOTLB_REG).
1009 * @{ */
1010/** R: Reserved (bits 31:0). */
1011#define VTD_BF_IOTLB_REG_RSVD_31_0_SHIFT 0
1012#define VTD_BF_IOTLB_REG_RSVD_31_0_MASK UINT64_C(0x00000000ffffffff)
1013/** DID: Domain-ID. */
1014#define VTD_BF_IOTLB_REG_DID_SHIFT 32
1015#define VTD_BF_IOTLB_REG_DID_MASK UINT64_C(0x0000ffff00000000)
1016/** DW: Draining Writes. */
1017#define VTD_BF_IOTLB_REG_DW_SHIFT 48
1018#define VTD_BF_IOTLB_REG_DW_MASK UINT64_C(0x0001000000000000)
1019/** DR: Draining Reads. */
1020#define VTD_BF_IOTLB_REG_DR_SHIFT 49
1021#define VTD_BF_IOTLB_REG_DR_MASK UINT64_C(0x0002000000000000)
1022/** R: Reserved (bits 56:50). */
1023#define VTD_BF_IOTLB_REG_RSVD_56_50_SHIFT 50
1024#define VTD_BF_IOTLB_REG_RSVD_56_50_MASK UINT64_C(0x01fc000000000000)
1025/** IAIG: IOTLB Actual Invalidation Granularity. */
1026#define VTD_BF_IOTLB_REG_IAIG_SHIFT 57
1027#define VTD_BF_IOTLB_REG_IAIG_MASK UINT64_C(0x0600000000000000)
1028/** R: Reserved (bit 59). */
1029#define VTD_BF_IOTLB_REG_RSVD_59_SHIFT 59
1030#define VTD_BF_IOTLB_REG_RSVD_59_MASK UINT64_C(0x0800000000000000)
1031/** IIRG: IOTLB Invalidation Request Granularity. */
1032#define VTD_BF_IOTLB_REG_IIRG_SHIFT 60
1033#define VTD_BF_IOTLB_REG_IIRG_MASK UINT64_C(0x3000000000000000)
1034/** R: Reserved (bit 62). */
1035#define VTD_BF_IOTLB_REG_RSVD_62_SHIFT 62
1036#define VTD_BF_IOTLB_REG_RSVD_62_MASK UINT64_C(0x4000000000000000)
1037/** IVT: Invalidate IOTLB. */
1038#define VTD_BF_IOTLB_REG_IVT_SHIFT 63
1039#define VTD_BF_IOTLB_REG_IVT_MASK UINT64_C(0x8000000000000000)
1040RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IOTLB_REG_, UINT64_C(0), UINT64_MAX,
1041 (RSVD_31_0, DID, DW, DR, RSVD_56_50, IAIG, RSVD_59, IIRG, RSVD_62, IVT));
1042/** @} */
1043
1044
1045/** @name Invalidate Address Register (IVA_REG).
1046 * @{ */
1047/** AM: Address Mask. */
1048#define VTD_BF_IVA_REG_AM_SHIFT 0
1049#define VTD_BF_IVA_REG_AM_MASK UINT64_C(0x000000000000003f)
1050/** IH: Invalidation Hint. */
1051#define VTD_BF_IVA_REG_IH_SHIFT 6
1052#define VTD_BF_IVA_REG_IH_MASK UINT64_C(0x0000000000000040)
1053/** R: Reserved (bits 11:7). */
1054#define VTD_BF_IVA_REG_RSVD_11_7_SHIFT 7
1055#define VTD_BF_IVA_REG_RSVD_11_7_MASK UINT64_C(0x0000000000000f80)
1056/** ADDR: Address. */
1057#define VTD_BF_IVA_REG_ADDR_SHIFT 12
1058#define VTD_BF_IVA_REG_ADDR_MASK UINT64_C(0xfffffffffffff000)
1059RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IVA_REG_, UINT64_C(0), UINT64_MAX,
1060 (AM, IH, RSVD_11_7, ADDR));
1061/** @} */
1062
1063
1064/** @name Fault Status Register (FSTS_REG).
1065 * @{ */
1066/** PFO: Primary Fault Overflow. */
1067#define VTD_BF_FSTS_REG_PFO_SHIFT 0
1068#define VTD_BF_FSTS_REG_PFO_MASK UINT32_C(0x00000001)
1069/** PPF: Primary Pending Fault. */
1070#define VTD_BF_FSTS_REG_PPF_SHIFT 1
1071#define VTD_BF_FSTS_REG_PPF_MASK UINT32_C(0x00000002)
1072/** AFO: Advanced Fault Overflow. */
1073#define VTD_BF_FSTS_REG_AFO_SHIFT 2
1074#define VTD_BF_FSTS_REG_AFO_MASK UINT32_C(0x00000004)
1075/** APF: Advanced Pending Fault. */
1076#define VTD_BF_FSTS_REG_APF_SHIFT 3
1077#define VTD_BF_FSTS_REG_APF_MASK UINT32_C(0x00000008)
1078/** IQE: Invalidation Queue Error. */
1079#define VTD_BF_FSTS_REG_IQE_SHIFT 4
1080#define VTD_BF_FSTS_REG_IQE_MASK UINT32_C(0x00000010)
1081/** ICE: Invalidation Completion Error. */
1082#define VTD_BF_FSTS_REG_ICE_SHIFT 5
1083#define VTD_BF_FSTS_REG_ICE_MASK UINT32_C(0x00000020)
1084/** ITE: Invalidation Timeout Error. */
1085#define VTD_BF_FSTS_REG_ITE_SHIFT 6
1086#define VTD_BF_FSTS_REG_ITE_MASK UINT32_C(0x00000040)
1087/** DEP: Deprecated MBZ. Reserved (bit 7). */
1088#define VTD_BF_FSTS_REG_RSVD_7_SHIFT 7
1089#define VTD_BF_FSTS_REG_RSVD_7_MASK UINT32_C(0x00000080)
1090/** FRI: Fault Record Index. */
1091#define VTD_BF_FSTS_REG_FRI_SHIFT 8
1092#define VTD_BF_FSTS_REG_FRI_MASK UINT32_C(0x0000ff00)
1093/** R: Reserved (bits 31:16). */
1094#define VTD_BF_FSTS_REG_RSVD_31_16_SHIFT 16
1095#define VTD_BF_FSTS_REG_RSVD_31_16_MASK UINT32_C(0xffff0000)
1096RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_FSTS_REG_, UINT32_C(0), UINT32_MAX,
1097 (PFO, PPF, AFO, APF, IQE, ICE, ITE, RSVD_7, FRI, RSVD_31_16));
1098/** @} */
1099
1100
1101/** @name Fault Event Control Register (FECTL_REG).
1102 * @{ */
1103/** R: Reserved (bits 29:0). */
1104#define VTD_BF_FECTL_REG_RSVD_29_0_SHIFT 0
1105#define VTD_BF_FECTL_REG_RSVD_29_0_MASK UINT32_C(0x3fffffff)
1106/** IP: Interrupt Pending. */
1107#define VTD_BF_FECTL_REG_IP_SHIFT 30
1108#define VTD_BF_FECTL_REG_IP_MASK UINT32_C(0x40000000)
1109/** IM: Interrupt Mask. */
1110#define VTD_BF_FECTL_REG_IM_SHIFT 31
1111#define VTD_BF_FECTL_REG_IM_MASK UINT32_C(0x80000000)
1112RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_FECTL_REG_, UINT32_C(0), UINT32_MAX,
1113 (RSVD_29_0, IP, IM));
1114/** @} */
1115
1116
1117/** @name Fault Event Data Register (FEDATA_REG).
1118 * @{ */
1119/** IMD: Interrupt Message Data. */
1120#define VTD_BF_FEDATA_REG_IMD_SHIFT 0
1121#define VTD_BF_FEDATA_REG_IMD_MASK UINT32_C(0x0000ffff)
1122/** EIMD: Extended Interrupt Message Data. */
1123#define VTD_BF_FEDATA_REG_EIMD_SHIFT 16
1124#define VTD_BF_FEDATA_REG_EIMD_MASK UINT32_C(0xffff0000)
1125RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_FEDATA_REG_, UINT32_C(0), UINT32_MAX,
1126 (IMD, EIMD));
1127/** @} */
1128
1129
1130/** @name Fault Event Address Register (FEADDR_REG).
1131 * @{ */
1132/** R: Reserved (bits 1:0). */
1133#define VTD_BF_FEADDR_REG_RSVD_1_0_SHIFT 0
1134#define VTD_BF_FEADDR_REG_RSVD_1_0_MASK UINT32_C(0x00000003)
1135/** MA: Message Address. */
1136#define VTD_BF_FEADDR_REG_MA_SHIFT 2
1137#define VTD_BF_FEADDR_REG_MA_MASK UINT32_C(0xfffffffc)
1138RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_FEADDR_REG_, UINT32_C(0), UINT32_MAX,
1139 (RSVD_1_0, MA));
1140/** @} */
1141
1142
1143/** @name Fault Recording Register (FRCD_REG).
1144 * @{ */
1145/** R: Reserved (bits 11:0). */
1146#define VTD_BF_0_FRCD_REG_RSVD_11_0_SHIFT 0
1147#define VTD_BF_0_FRCD_REG_RSVD_11_0_MASK UINT64_C(0x0000000000000fff)
1148/** FI: Fault Info. */
1149#define VTD_BF_0_FRCD_REG_FI_SHIFT 12
1150#define VTD_BF_0_FRCD_REG_FI_MASK UINT64_C(0xfffffffffffff000)
1151RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_FRCD_REG_, UINT64_C(0), UINT64_MAX,
1152 (RSVD_11_0, FI));
1153
1154/** SID: Source Identifier. */
1155#define VTD_BF_1_FRCD_REG_SID_SHIFT 0
1156#define VTD_BF_1_FRCD_REG_SID_MASK UINT64_C(0x000000000000ffff)
1157/** R: Reserved (bits 27:16). */
1158#define VTD_BF_1_FRCD_REG_RSVD_27_16_SHIFT 16
1159#define VTD_BF_1_FRCD_REG_RSVD_27_16_MASK UINT64_C(0x000000000fff0000)
1160/** T2: Type bit 2. */
1161#define VTD_BF_1_FRCD_REG_T2_SHIFT 28
1162#define VTD_BF_1_FRCD_REG_T2_MASK UINT64_C(0x0000000010000000)
1163/** PRIV: Privilege Mode. */
1164#define VTD_BF_1_FRCD_REG_PRIV_SHIFT 29
1165#define VTD_BF_1_FRCD_REG_PRIV_MASK UINT64_C(0x0000000020000000)
1166/** EXE: Execute Permission Requested. */
1167#define VTD_BF_1_FRCD_REG_EXE_SHIFT 30
1168#define VTD_BF_1_FRCD_REG_EXE_MASK UINT64_C(0x0000000040000000)
1169/** PP: PASID Present. */
1170#define VTD_BF_1_FRCD_REG_PP_SHIFT 31
1171#define VTD_BF_1_FRCD_REG_PP_MASK UINT64_C(0x0000000080000000)
1172/** FR: Fault Reason. */
1173#define VTD_BF_1_FRCD_REG_FR_SHIFT 32
1174#define VTD_BF_1_FRCD_REG_FR_MASK UINT64_C(0x000000ff00000000)
1175/** PV: PASID Value. */
1176#define VTD_BF_1_FRCD_REG_PV_SHIFT 40
1177#define VTD_BF_1_FRCD_REG_PV_MASK UINT64_C(0x0fffff0000000000)
1178/** AT: Address Type. */
1179#define VTD_BF_1_FRCD_REG_AT_SHIFT 60
1180#define VTD_BF_1_FRCD_REG_AT_MASK UINT64_C(0x3000000000000000)
1181/** T1: Type bit 1. */
1182#define VTD_BF_1_FRCD_REG_T1_SHIFT 62
1183#define VTD_BF_1_FRCD_REG_T1_MASK UINT64_C(0x4000000000000000)
1184/** F: Fault. */
1185#define VTD_BF_1_FRCD_REG_F_SHIFT 63
1186#define VTD_BF_1_FRCD_REG_F_MASK UINT64_C(0x8000000000000000)
1187RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_FRCD_REG_, UINT64_C(0), UINT64_MAX,
1188 (SID, RSVD_27_16, T2, PRIV, EXE, PP, FR, PV, AT, T1, F));
1189/** @} */
1190
1191
1192/** @name Advanced Fault Log Register (AFLOG_REG).
1193 * @{ */
1194/** R: Reserved (bits 8:0). */
1195#define VTD_BF_0_AFLOG_REG_RSVD_8_0_SHIFT 0
1196#define VTD_BF_0_AFLOG_REG_RSVD_8_0_MASK UINT64_C(0x00000000000001ff)
1197/** FLS: Fault Log Size. */
1198#define VTD_BF_0_AFLOG_REG_FLS_SHIFT 9
1199#define VTD_BF_0_AFLOG_REG_FLS_MASK UINT64_C(0x0000000000000e00)
1200/** FLA: Fault Log Address. */
1201#define VTD_BF_0_AFLOG_REG_FLA_SHIFT 12
1202#define VTD_BF_0_AFLOG_REG_FLA_MASK UINT64_C(0xfffffffffffff000)
1203RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_AFLOG_REG_, UINT64_C(0), UINT64_MAX,
1204 (RSVD_8_0, FLS, FLA));
1205/** @} */
1206
1207
1208/** @name Protected Memory Enable Register (PMEN_REG).
1209 * @{ */
1210/** PRS: Protected Region Status. */
1211#define VTD_BF_PMEN_REG_PRS_SHIFT 0
1212#define VTD_BF_PMEN_REG_PRS_MASK UINT32_C(0x00000001)
1213/** R: Reserved (bits 30:1). */
1214#define VTD_BF_PMEN_REG_RSVD_30_1_SHIFT 1
1215#define VTD_BF_PMEN_REG_RSVD_30_1_MASK UINT32_C(0x7ffffffe)
1216/** EPM: Enable Protected Memory. */
1217#define VTD_BF_PMEN_REG_EPM_SHIFT 31
1218#define VTD_BF_PMEN_REG_EPM_MASK UINT32_C(0x80000000)
1219RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_PMEN_REG_, UINT32_C(0), UINT32_MAX,
1220 (PRS, RSVD_30_1, EPM));
1221/** @} */
1222
1223
1224/** @name Invalidation Queue Head Register (IQH_REG).
1225 * @{ */
1226/** R: Reserved (bits 3:0). */
1227#define VTD_BF_IQH_REG_RSVD_3_0_SHIFT 0
1228#define VTD_BF_IQH_REG_RSVD_3_0_MASK UINT64_C(0x000000000000000f)
1229/** QH: Queue Head. */
1230#define VTD_BF_IQH_REG_QH_SHIFT 4
1231#define VTD_BF_IQH_REG_QH_MASK UINT64_C(0x000000000007fff0)
1232/** R: Reserved (bits 63:19). */
1233#define VTD_BF_IQH_REG_RSVD_63_19_SHIFT 19
1234#define VTD_BF_IQH_REG_RSVD_63_19_MASK UINT64_C(0xfffffffffff80000)
1235RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IQH_REG_, UINT64_C(0), UINT64_MAX,
1236 (RSVD_3_0, QH, RSVD_63_19));
1237/** @} */
1238
1239
1240/** @name Invalidation Queue Tail Register (IQT_REG).
1241 * @{ */
1242/** R: Reserved (bits 3:0). */
1243#define VTD_BF_IQT_REG_RSVD_3_0_SHIFT 0
1244#define VTD_BF_IQT_REG_RSVD_3_0_MASK UINT64_C(0x000000000000000f)
1245/** QH: Queue Tail. */
1246#define VTD_BF_IQT_REG_QT_SHIFT 4
1247#define VTD_BF_IQT_REG_QT_MASK UINT64_C(0x000000000007fff0)
1248/** R: Reserved (bits 63:19). */
1249#define VTD_BF_IQT_REG_RSVD_63_19_SHIFT 19
1250#define VTD_BF_IQT_REG_RSVD_63_19_MASK UINT64_C(0xfffffffffff80000)
1251RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IQT_REG_, UINT64_C(0), UINT64_MAX,
1252 (RSVD_3_0, QT, RSVD_63_19));
1253/** @} */
1254
1255/** @name Invalidation Queue Address Register (IQA_REG).
1256 * @{ */
1257/** QS: Queue Size. */
1258#define VTD_BF_IQA_REG_QS_SHIFT 0
1259#define VTD_BF_IQA_REG_QS_MASK UINT64_C(0x0000000000000007)
1260/** R: Reserved (bits 10:3). */
1261#define VTD_BF_IQA_REG_RSVD_10_3_SHIFT 3
1262#define VTD_BF_IQA_REG_RSVD_10_3_MASK UINT64_C(0x00000000000007f8)
1263/** DW: Descriptor Width. */
1264#define VTD_BF_IQA_REG_DW_SHIFT 11
1265#define VTD_BF_IQA_REG_DW_MASK UINT64_C(0x0000000000000800)
1266/** IQA: Invalidation Queue Base Address. */
1267#define VTD_BF_IQA_REG_IQA_SHIFT 12
1268#define VTD_BF_IQA_REG_IQA_MASK UINT64_C(0xfffffffffffff000)
1269RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IQA_REG_, UINT64_C(0), UINT64_MAX,
1270 (QS, RSVD_10_3, DW, IQA));
1271/** @} */
1272
1273
1274/** @name Invalidation Completion Status Register (ICS_REG).
1275 * @{ */
1276/** IWC: Invalidation Wait Descriptor Complete. */
1277#define VTD_BF_ICS_REG_IWC_SHIFT 0
1278#define VTD_BF_ICS_REG_IWC_MASK UINT32_C(0x00000001)
1279/** R: Reserved (bits 31:1). */
1280#define VTD_BF_ICS_REG_RSVD_31_1_SHIFT 1
1281#define VTD_BF_ICS_REG_RSVD_31_1_MASK UINT32_C(0xfffffffe)
1282RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_ICS_REG_, UINT32_C(0), UINT32_MAX,
1283 (IWC, RSVD_31_1));
1284/** @} */
1285
1286
1287/** @name Invalidation Event Control Register (IECTL_REG).
1288 * @{ */
1289/** R: Reserved (bits 29:0). */
1290#define VTD_BF_IECTL_REG_RSVD_29_0_SHIFT 0
1291#define VTD_BF_IECTL_REG_RSVD_29_0_MASK UINT32_C(0x3fffffff)
1292/** IP: Interrupt Pending. */
1293#define VTD_BF_IECTL_REG_IP_SHIFT 30
1294#define VTD_BF_IECTL_REG_IP_MASK UINT32_C(0x40000000)
1295/** IM: Interrupt Mask. */
1296#define VTD_BF_IECTL_REG_IM_SHIFT 31
1297#define VTD_BF_IECTL_REG_IM_MASK UINT32_C(0x80000000)
1298RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IECTL_REG_, UINT32_C(0), UINT32_MAX,
1299 (RSVD_29_0, IP, IM));
1300/** @} */
1301
1302
1303/** @name Invalidation Event Data Register (IEDATA_REG).
1304 * @{ */
1305/** IMD: Interrupt Message Data. */
1306#define VTD_BF_IEDATA_REG_IMD_SHIFT 0
1307#define VTD_BF_IEDATA_REG_IMD_MASK UINT32_C(0x0000ffff)
1308/** EIMD: Extended Interrupt Message Data. */
1309#define VTD_BF_IEDATA_REG_EIMD_SHIFT 16
1310#define VTD_BF_IEDATA_REG_EIMD_MASK UINT32_C(0xffff0000)
1311RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IEDATA_REG_, UINT32_C(0), UINT32_MAX,
1312 (IMD, EIMD));
1313/** @} */
1314
1315
1316/** @name Invalidation Event Address Register (IEADDR_REG).
1317 * @{ */
1318/** R: Reserved (bits 1:0). */
1319#define VTD_BF_IEADDR_REG_RSVD_1_0_SHIFT 0
1320#define VTD_BF_IEADDR_REG_RSVD_1_0_MASK UINT32_C(0x00000003)
1321/** MA: Message Address. */
1322#define VTD_BF_IEADDR_REG_MA_SHIFT 2
1323#define VTD_BF_IEADDR_REG_MA_MASK UINT32_C(0xfffffffc)
1324RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IEADDR_REG_, UINT32_C(0), UINT32_MAX,
1325 (RSVD_1_0, MA));
1326/** @} */
1327
1328
1329/** @name Invalidation Queue Error Record Register (IQERCD_REG).
1330 * @{ */
1331/** IQEI: Invalidation Queue Error Info. */
1332#define VTD_BF_IQERCD_REG_IQEI_SHIFT 0
1333#define VTD_BF_IQERCD_REG_IQEI_MASK UINT64_C(0x000000000000000f)
1334/** R: Reserved (bits 31:4). */
1335#define VTD_BF_IQERCD_REG_RSVD_31_4_SHIFT 4
1336#define VTD_BF_IQERCD_REG_RSVD_31_4_MASK UINT64_C(0x00000000fffffff0)
1337/** ITESID: Invalidation Timeout Error Source Identifier. */
1338#define VTD_BF_IQERCD_REG_ITESID_SHIFT 32
1339#define VTD_BF_IQERCD_REG_ITESID_MASK UINT64_C(0x0000ffff00000000)
1340/** ICESID: Invalidation Completion Error Source Identifier. */
1341#define VTD_BF_IQERCD_REG_ICESID_SHIFT 48
1342#define VTD_BF_IQERCD_REG_ICESID_MASK UINT64_C(0xffff000000000000)
1343RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IQERCD_REG_, UINT64_C(0), UINT64_MAX,
1344 (IQEI, RSVD_31_4, ITESID, ICESID));
1345/** @} */
1346
1347
1348/** @name Interrupt Remapping Table Address Register (IRTA_REG).
1349 * @{ */
1350/** S: Size. */
1351#define VTD_BF_IRTA_REG_S_SHIFT 0
1352#define VTD_BF_IRTA_REG_S_MASK UINT64_C(0x000000000000000f)
1353/** R: Reserved (bits 10:4). */
1354#define VTD_BF_IRTA_REG_RSVD_10_4_SHIFT 4
1355#define VTD_BF_IRTA_REG_RSVD_10_4_MASK UINT64_C(0x00000000000007f0)
1356/** EIME: Extended Interrupt Mode Enable. */
1357#define VTD_BF_IRTA_REG_EIME_SHIFT 11
1358#define VTD_BF_IRTA_REG_EIME_MASK UINT64_C(0x0000000000000800)
1359/** IRTA: Interrupt Remapping Table Address. */
1360#define VTD_BF_IRTA_REG_IRTA_SHIFT 12
1361#define VTD_BF_IRTA_REG_IRTA_MASK UINT64_C(0xfffffffffffff000)
1362RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IRTA_REG_, UINT64_C(0), UINT64_MAX,
1363 (S, RSVD_10_4, EIME, IRTA));
1364/** @} */
1365
1366
1367/** @name Page Request Queue Head Register (PQH_REG).
1368 * @{ */
1369/** R: Reserved (bits 4:0). */
1370#define VTD_BF_PQH_REG_RSVD_4_0_SHIFT 0
1371#define VTD_BF_PQH_REG_RSVD_4_0_MASK UINT64_C(0x000000000000001f)
1372/** PQH: Page Queue Head. */
1373#define VTD_BF_PQH_REG_PQH_SHIFT 5
1374#define VTD_BF_PQH_REG_PQH_MASK UINT64_C(0x000000000007ffe0)
1375/** R: Reserved (bits 63:19). */
1376#define VTD_BF_PQH_REG_RSVD_63_19_SHIFT 19
1377#define VTD_BF_PQH_REG_RSVD_63_19_MASK UINT64_C(0xfffffffffff80000)
1378RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_PQH_REG_, UINT64_C(0), UINT64_MAX,
1379 (RSVD_4_0, PQH, RSVD_63_19));
1380/** @} */
1381
1382
1383/** @name Page Request Queue Tail Register (PQT_REG).
1384 * @{ */
1385/** R: Reserved (bits 4:0). */
1386#define VTD_BF_PQT_REG_RSVD_4_0_SHIFT 0
1387#define VTD_BF_PQT_REG_RSVD_4_0_MASK UINT64_C(0x000000000000001f)
1388/** PQT: Page Queue Tail. */
1389#define VTD_BF_PQT_REG_PQT_SHIFT 5
1390#define VTD_BF_PQT_REG_PQT_MASK UINT64_C(0x000000000007ffe0)
1391/** R: Reserved (bits 63:19). */
1392#define VTD_BF_PQT_REG_RSVD_63_19_SHIFT 19
1393#define VTD_BF_PQT_REG_RSVD_63_19_MASK UINT64_C(0xfffffffffff80000)
1394RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_PQT_REG_, UINT64_C(0), UINT64_MAX,
1395 (RSVD_4_0, PQT, RSVD_63_19));
1396/** @} */
1397
1398
1399/** @name Page Request Queue Address Register (PQA_REG).
1400 * @{ */
1401/** PQS: Page Queue Size. */
1402#define VTD_BF_PQA_REG_PQS_SHIFT 0
1403#define VTD_BF_PQA_REG_PQS_MASK UINT64_C(0x0000000000000007)
1404/** R: Reserved bits (11:3). */
1405#define VTD_BF_PQA_REG_RSVD_11_3_SHIFT 3
1406#define VTD_BF_PQA_REG_RSVD_11_3_MASK UINT64_C(0x0000000000000ff8)
1407/** PQA: Page Request Queue Base Address. */
1408#define VTD_BF_PQA_REG_PQA_SHIFT 12
1409#define VTD_BF_PQA_REG_PQA_MASK UINT64_C(0xfffffffffffff000)
1410RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_PQA_REG_, UINT64_C(0), UINT64_MAX,
1411 (PQS, RSVD_11_3, PQA));
1412/** @} */
1413
1414
1415/** @name Page Request Status Register (PRS_REG).
1416 * @{ */
1417/** PPR: Pending Page Request. */
1418#define VTD_BF_PRS_REG_PPR_SHIFT 0
1419#define VTD_BF_PRS_REG_PPR_MASK UINT64_C(0x00000001)
1420/** PRO: Page Request Overflow. */
1421#define VTD_BF_PRS_REG_PRO_SHIFT 1
1422#define VTD_BF_PRS_REG_PRO_MASK UINT64_C(0x00000002)
1423/** R: Reserved (bits 31:2). */
1424#define VTD_BF_PRS_REG_RSVD_31_2_SHIFT 2
1425#define VTD_BF_PRS_REG_RSVD_31_2_MASK UINT64_C(0xfffffffc)
1426RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_PRS_REG_, UINT32_C(0), UINT32_MAX,
1427 (PPR, PRO, RSVD_31_2));
1428/** @} */
1429
1430
1431/** @name Page Request Event Control Register (PECTL_REG).
1432 * @{ */
1433/** R: Reserved (bits 29:0). */
1434#define VTD_BF_PECTL_REG_RSVD_29_0_SHIFT 0
1435#define VTD_BF_PECTL_REG_RSVD_29_0_MASK UINT32_C(0x3fffffff)
1436/** IP: Interrupt Pending. */
1437#define VTD_BF_PECTL_REG_IP_SHIFT 30
1438#define VTD_BF_PECTL_REG_IP_MASK UINT32_C(0x40000000)
1439/** IM: Interrupt Mask. */
1440#define VTD_BF_PECTL_REG_IM_SHIFT 31
1441#define VTD_BF_PECTL_REG_IM_MASK UINT32_C(0x80000000)
1442RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_PECTL_REG_, UINT32_C(0), UINT32_MAX,
1443 (RSVD_29_0, IP, IM));
1444/** @} */
1445
1446
1447/** @name Page Request Event Data Register (PEDATA_REG).
1448 * @{ */
1449/** IMD: Interrupt Message Data. */
1450#define VTD_BF_PEDATA_REG_IMD_SHIFT 0
1451#define VTD_BF_PEDATA_REG_IMD_MASK UINT32_C(0x0000ffff)
1452/** EIMD: Extended Interrupt Message Data. */
1453#define VTD_BF_PEDATA_REG_EIMD_SHIFT 16
1454#define VTD_BF_PEDATA_REG_EIMD_MASK UINT32_C(0xffff0000)
1455RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_PEDATA_REG_, UINT32_C(0), UINT32_MAX,
1456 (IMD, EIMD));
1457/** @} */
1458
1459
1460/** @name Page Request Event Address Register (PEADDR_REG).
1461 * @{ */
1462/** R: Reserved (bits 1:0). */
1463#define VTD_BF_PEADDR_REG_RSVD_1_0_SHIFT 0
1464#define VTD_BF_PEADDR_REG_RSVD_1_0_MASK UINT32_C(0x00000003)
1465/** MA: Message Address. */
1466#define VTD_BF_PEADDR_REG_MA_SHIFT 2
1467#define VTD_BF_PEADDR_REG_MA_MASK UINT32_C(0xfffffffc)
1468RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_PEADDR_REG_, UINT32_C(0), UINT32_MAX,
1469 (RSVD_1_0, MA));
1470/** @} */
1471
1472
1473/** @name MTRR Default Type Register (MTRRDEF_REG).
1474 * @{ */
1475/** TYPE: Default Memory Type. */
1476#define VTD_BF_MTRRDEF_REG_TYPE_SHIFT 0
1477#define VTD_BF_MTRRDEF_REG_TYPE_MASK UINT64_C(0x00000000000000ff)
1478/** R: Reserved (bits 9:8). */
1479#define VTD_BF_MTRRDEF_REG_RSVD_9_8_SHIFT 8
1480#define VTD_BF_MTRRDEF_REG_RSVD_9_8_MASK UINT64_C(0x0000000000000300)
1481/** FE: Fixed Range MTRR Enable. */
1482#define VTD_BF_MTRRDEF_REG_FE_SHIFT 10
1483#define VTD_BF_MTRRDEF_REG_FE_MASK UINT64_C(0x0000000000000400)
1484/** E: MTRR Enable. */
1485#define VTD_BF_MTRRDEF_REG_E_SHIFT 11
1486#define VTD_BF_MTRRDEF_REG_E_MASK UINT64_C(0x0000000000000800)
1487/** R: Reserved (bits 63:12). */
1488#define VTD_BF_MTRRDEF_REG_RSVD_63_12_SHIFT 12
1489#define VTD_BF_MTRRDEF_REG_RSVD_63_12_MASK UINT64_C(0xfffffffffffff000)
1490RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_MTRRDEF_REG_, UINT64_C(0), UINT64_MAX,
1491 (TYPE, RSVD_9_8, FE, E, RSVD_63_12));
1492/** @} */
1493
1494
1495/** @name Virtual Command Capability Register (VCCAP_REG).
1496 * @{ */
1497/** PAS: PASID Support. */
1498#define VTD_BF_VCCAP_REG_PAS_SHIFT 0
1499#define VTD_BF_VCCAP_REG_PAS_MASK UINT64_C(0x0000000000000001)
1500/** R: Reserved (bits 63:1). */
1501#define VTD_BF_VCCAP_REG_RSVD_63_1_SHIFT 1
1502#define VTD_BF_VCCAP_REG_RSVD_63_1_MASK UINT64_C(0xfffffffffffffffe)
1503RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_VCCAP_REG_, UINT64_C(0), UINT64_MAX,
1504 (PAS, RSVD_63_1));
1505/** @} */
1506
1507
1508/** @name Virtual Command Register (VCMD_REG).
1509 * @{ */
1510/** CMD: Command. */
1511#define VTD_BF_VCMD_REG_CMD_SHIFT 0
1512#define VTD_BF_VCMD_REG_CMD_MASK UINT64_C(0x00000000000000ff)
1513/** OP: Operand. */
1514#define VTD_BF_VCMD_REG_OP_SHIFT 8
1515#define VTD_BF_VCMD_REG_OP_MASK UINT64_C(0xffffffffffffff00)
1516RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_VCMD_REG_, UINT64_C(0), UINT64_MAX,
1517 (CMD, OP));
1518/** @} */
1519
1520
1521/** @name Virtual Command Register (VCMD_REG).
1522 * @{ */
1523/** IP: In Progress. */
1524#define VTD_BF_VCRSP_REG_IP_SHIFT 0
1525#define VTD_BF_VCRSP_REG_IP_MASK UINT64_C(0x0000000000000001)
1526/** SC: Status Code. */
1527#define VTD_BF_VCRSP_REG_SC_SHIFT 1
1528#define VTD_BF_VCRSP_REG_SC_MASK UINT64_C(0x0000000000000006)
1529/** R: Reserved (bits 7:3). */
1530#define VTD_BF_VCRSP_REG_RSVD_7_3_SHIFT 3
1531#define VTD_BF_VCRSP_REG_RSVD_7_3_MASK UINT64_C(0x00000000000000f8)
1532/** RSLT: Result. */
1533#define VTD_BF_VCRSP_REG_RSLT_SHIFT 8
1534#define VTD_BF_VCRSP_REG_RSLT_MASK UINT64_C(0xffffffffffffff00)
1535RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_VCRSP_REG_, UINT64_C(0), UINT64_MAX,
1536 (IP, SC, RSVD_7_3, RSLT));
1537/** @} */
1538
1539
1540#endif /* !VBOX_INCLUDED_iommu_intel_h */
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