VirtualBox

source: vbox/trunk/include/VBox/iommu-intel.h@ 88201

Last change on this file since 88201 was 88201, checked in by vboxsync, 4 years ago

Intel IOMMU: bugref:9967 WIP.
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File size: 90.8 KB
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1/** @file
2 * IOMMU - Input/Output Memory Management Unit (Intel).
3 */
4
5/*
6 * Copyright (C) 2021 Oracle Corporation
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * The contents of this file may alternatively be used under the terms
17 * of the Common Development and Distribution License Version 1.0
18 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19 * VirtualBox OSE distribution, in which case the provisions of the
20 * CDDL are applicable instead of those of the GPL.
21 *
22 * You may elect to license modified versions of this file under the
23 * terms and conditions of either the GPL or the CDDL or both.
24 */
25
26#ifndef VBOX_INCLUDED_iommu_intel_h
27#define VBOX_INCLUDED_iommu_intel_h
28#ifndef RT_WITHOUT_PRAGMA_ONCE
29# pragma once
30#endif
31
32#include <iprt/types.h>
33
34
35/**
36 * @name MMIO register offsets.
37 * In accordance with the AMD spec.
38 * @{
39 */
40#define VTD_MMIO_GROUP_0_OFF_FIRST 0x000
41#define VTD_MMIO_OFF_VER_REG VTD_MMIO_GROUP_0_OFF_FIRST /**< Version. */
42#define VTD_MMIO_OFF_CAP_REG 0x008 /**< Capability. */
43#define VTD_MMIO_OFF_ECAP_REG 0x010 /**< Extended Capability. */
44#define VTD_MMIO_OFF_GCMD_REG 0x018 /**< Global Command. */
45#define VTD_MMIO_OFF_GSTS_REG 0x01c /**< Global Status. */
46#define VTD_MMIO_OFF_RTADDR_REG 0x020 /**< Root Table Address. */
47#define VTD_MMIO_OFF_CCMD_REG 0x028 /**< Context Command. */
48
49#define VTD_MMIO_OFF_FSTS_REG 0x034 /**< Fault Status.*/
50#define VTD_MMIO_OFF_FECTL_REG 0x038 /**< Fault Event Control.*/
51#define VTD_MMIO_OFF_FEDATA_REG 0x03c /**< Fault Event Data. */
52#define VTD_MMIO_OFF_FEADDR_REG 0x040 /**< Fault Event Address. */
53#define VTD_MMIO_OFF_FEUADDR_REG 0x044 /**< Fault Event Upper Address. */
54
55#define VTD_MMIO_OFF_AFLOG_REG 0x058 /**< Advance Fault Log. */
56
57#define VTD_MMIO_OFF_PMEN_REG 0x064 /**< Protected Memory Enable (PMEN). */
58#define VTD_MMIO_OFF_PLMBASE_REG 0x068 /**< Protected Low Memory Base. */
59#define VTD_MMIO_OFF_PLMLIMIT_REG 0x06c /**< Protected Low Memory Limit. */
60#define VTD_MMIO_OFF_PHMBASE_REG 0x070 /**< Protected High Memory Base. */
61#define VTD_MMIO_OFF_PHMLIMIT_REG 0x078 /**< Protected High Memory Limit. */
62
63#define VTD_MMIO_OFF_IQH_REG 0x080 /**< Invalidation Queue Head. */
64#define VTD_MMIO_OFF_IQT_REG 0x088 /**< Invalidation Queue Tail. */
65#define VTD_MMIO_OFF_IQA_REG 0x090 /**< Invalidation Queue Address. */
66#define VTD_MMIO_OFF_ICS_REG 0x09c /**< Invalidation Completion Status. */
67#define VTD_MMIO_OFF_IECTL_REG 0x0a0 /**< Invalidation Completion Event Control. */
68#define VTD_MMIO_OFF_IEDATA_REG 0x0a4 /**< Invalidation Completion Event Data. */
69#define VTD_MMIO_OFF_IEADDR_REG 0x0a8 /**< Invalidation Completion Event Address. */
70#define VTD_MMIO_OFF_IEUADDR_REG 0x0ac /**< Invalidation Completion Event Upper Address. */
71#define VTD_MMIO_OFF_IQERCD_REG 0x0b0 /**< Invalidation Queue Error Record. */
72
73#define VTD_MMIO_OFF_IRTA_REG 0x0b8 /**< Interrupt Remapping Table Address. */
74
75#define VTD_MMIO_OFF_PQH_REG 0x0c0 /**< Page Request Queue Head. */
76#define VTD_MMIO_OFF_PQT_REG 0x0c8 /**< Page Request Queue Tail. */
77#define VTD_MMIO_OFF_PQA_REG 0x0d0 /**< Page Request Queue Address. */
78#define VTD_MMIO_OFF_PRS_REG 0x0dc /**< Page Request Status. */
79#define VTD_MMIO_OFF_PECTL_REG 0x0e0 /**< Page Request Event Control. */
80#define VTD_MMIO_OFF_PEDATA_REG 0x0e4 /**< Page Request Event Data. */
81#define VTD_MMIO_OFF_PEADDR_REG 0x0e8 /**< Page Request Event Address. */
82#define VTD_MMIO_OFF_PEUADDR_REG 0x0ec /**< Page Request Event Upper Address. */
83
84#define VTD_MMIO_OFF_MTRRCAP_REG 0x100 /**< MTRR Capabliity. */
85#define VTD_MMIO_OFF_MTRRDEF_REG 0x108 /**< MTRR Default Type. */
86
87#define VTD_MMIO_OFF_MTRR_FIX64_00000_REG 0x120 /**< Fixed-range MTRR Register for 64K at 00000. */
88#define VTD_MMIO_OFF_MTRR_FIX16K_80000_REG 0x128 /**< Fixed-range MTRR Register for 16K at 80000. */
89#define VTD_MMIO_OFF_MTRR_FIX16K_A0000_REG 0x130 /**< Fixed-range MTRR Register for 16K at a0000. */
90#define VTD_MMIO_OFF_MTRR_FIX4K_C0000_REG 0x138 /**< Fixed-range MTRR Register for 4K at c0000. */
91#define VTD_MMIO_OFF_MTRR_FIX4K_C8000_REG 0x140 /**< Fixed-range MTRR Register for 4K at c8000. */
92#define VTD_MMIO_OFF_MTRR_FIX4K_D0000_REG 0x148 /**< Fixed-range MTRR Register for 4K at d0000. */
93#define VTD_MMIO_OFF_MTRR_FIX4K_D8000_REG 0x150 /**< Fixed-range MTRR Register for 4K at d8000. */
94#define VTD_MMIO_OFF_MTRR_FIX4K_E0000_REG 0x158 /**< Fixed-range MTRR Register for 4K at e0000. */
95#define VTD_MMIO_OFF_MTRR_FIX4K_E8000_REG 0x160 /**< Fixed-range MTRR Register for 4K at e8000. */
96#define VTD_MMIO_OFF_MTRR_FIX4K_F0000_REG 0x168 /**< Fixed-range MTRR Register for 4K at f0000. */
97#define VTD_MMIO_OFF_MTRR_FIX4K_F8000_REG 0x170 /**< Fixed-range MTRR Register for 4K at f8000. */
98
99#define VTD_MMIO_OFF_MTRR_PHYSBASE0_REG 0x180 /**< Variable-range MTRR Base 0. */
100#define VTD_MMIO_OFF_MTRR_PHYSMASK0_REG 0x188 /**< Variable-range MTRR Mask 0. */
101#define VTD_MMIO_OFF_MTRR_PHYSBASE1_REG 0x190 /**< Variable-range MTRR Base 1. */
102#define VTD_MMIO_OFF_MTRR_PHYSMASK1_REG 0x198 /**< Variable-range MTRR Mask 1. */
103#define VTD_MMIO_OFF_MTRR_PHYSBASE2_REG 0x1a0 /**< Variable-range MTRR Base 2. */
104#define VTD_MMIO_OFF_MTRR_PHYSMASK2_REG 0x1a8 /**< Variable-range MTRR Mask 2. */
105#define VTD_MMIO_OFF_MTRR_PHYSBASE3_REG 0x1b0 /**< Variable-range MTRR Base 3. */
106#define VTD_MMIO_OFF_MTRR_PHYSMASK3_REG 0x1b8 /**< Variable-range MTRR Mask 3. */
107#define VTD_MMIO_OFF_MTRR_PHYSBASE4_REG 0x1c0 /**< Variable-range MTRR Base 4. */
108#define VTD_MMIO_OFF_MTRR_PHYSMASK4_REG 0x1c8 /**< Variable-range MTRR Mask 4. */
109#define VTD_MMIO_OFF_MTRR_PHYSBASE5_REG 0x1d0 /**< Variable-range MTRR Base 5. */
110#define VTD_MMIO_OFF_MTRR_PHYSMASK5_REG 0x1d8 /**< Variable-range MTRR Mask 5. */
111#define VTD_MMIO_OFF_MTRR_PHYSBASE6_REG 0x1e0 /**< Variable-range MTRR Base 6. */
112#define VTD_MMIO_OFF_MTRR_PHYSMASK6_REG 0x1e8 /**< Variable-range MTRR Mask 6. */
113#define VTD_MMIO_OFF_MTRR_PHYSBASE7_REG 0x1f0 /**< Variable-range MTRR Base 7. */
114#define VTD_MMIO_OFF_MTRR_PHYSMASK7_REG 0x1f8 /**< Variable-range MTRR Mask 7. */
115#define VTD_MMIO_OFF_MTRR_PHYSBASE8_REG 0x200 /**< Variable-range MTRR Base 8. */
116#define VTD_MMIO_OFF_MTRR_PHYSMASK8_REG 0x208 /**< Variable-range MTRR Mask 8. */
117#define VTD_MMIO_OFF_MTRR_PHYSBASE9_REG 0x210 /**< Variable-range MTRR Base 9. */
118#define VTD_MMIO_OFF_MTRR_PHYSMASK9_REG 0x218 /**< Variable-range MTRR Mask 9. */
119#define VTD_MMIO_GROUP_0_OFF_LAST VTD_MMIO_OFF_MTRR_PHYSMASK9_REG
120#define VTD_MMIO_GROUP_0_OFF_END (VTD_MMIO_GROUP_0_OFF_LAST + 8 /* sizeof MTRR_PHYSMASK9_REG */)
121
122#define VTD_MMIO_GROUP_1_OFF_FIRST 0xe00
123#define VTD_MMIO_OFF_VCCAP_REG VTD_MMIO_GROUP_1_OFF_FIRST /**< Virtual Command Capability. */
124#define VTD_MMIO_OFF_VCMD_REG 0xe10 /**< Virtual Command. */
125#define VTD_MMIO_OFF_VCRSP_REG 0xe20 /**< Virtual Command Response. */
126#define VTD_MMIO_GROUP_1_OFF_LAST VTD_MMIO_OFF_VCRSP_REG
127#define VTD_MMIO_GROUP_1_OFF_END (VTD_MMIO_GROUP_1_OFF_LAST + 8 /* sizeof VCRSP_REG */)
128
129#define VTD_MMIO_GROUP_0_SIZE (VTD_MMIO_GROUP_0_OFF_END - VTD_MMIO_GROUP_0_OFF_FIRST) /*bytes*/
130#define VTD_MMIO_GROUP_1_SIZE (VTD_MMIO_GROUP_1_OFF_END - VTD_MMIO_GROUP_1_OFF_FIRST) /*bytes*/
131/** @} */
132
133
134/** @name Root Entry.
135 * In accordance with the Intel spec.
136 * @{ */
137/** P: Present. */
138#define VTD_BF_0_ROOT_ENTRY_P_SHIFT 0
139#define VTD_BF_0_ROOT_ENTRY_P_MASK UINT64_C(0x0000000000000001)
140/** R: Reserved (bits 11:1). */
141#define VTD_BF_0_ROOT_ENTRY_RSVD_11_1_SHIFT 1
142#define VTD_BF_0_ROOT_ENTRY_RSVD_11_1_MASK UINT64_C(0x0000000000000ffe)
143/** CTP: Context-Table Pointer. */
144#define VTD_BF_0_ROOT_ENTRY_CTP_SHIFT 12
145#define VTD_BF_0_ROOT_ENTRY_CTP_MASK UINT64_C(0xfffffffffffff000)
146RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_ROOT_ENTRY_, UINT64_C(0), UINT64_MAX,
147 (P, RSVD_11_1, CTP));
148
149/** Root Entry. */
150typedef struct VTD_ROOT_ENTRY_T
151{
152 /** The qwords in the root entry. */
153 uint64_t au64[2];
154} VTD_ROOT_ENTRY_T;
155/** Pointer to a root entry. */
156typedef VTD_ROOT_ENTRY_T *PVTD_ROOT_ENTRY_T;
157/** Pointer to a const root entry. */
158typedef VTD_ROOT_ENTRY_T const *PCVTD_ROOT_ENTRY_T;
159/** @} */
160
161
162/** @name Scalable-mode Root Entry.
163 * In accordance with the Intel spec.
164 * @{ */
165/** LP: Lower Present. */
166#define VTD_BF_0_SM_ROOT_ENTRY_LP_SHIFT 0
167#define VTD_BF_0_SM_ROOT_ENTRY_LP_MASK UINT64_C(0x0000000000000001)
168/** R: Reserved (bits 11:1). */
169#define VTD_BF_0_SM_ROOT_ENTRY_RSVD_11_1_SHIFT 1
170#define VTD_BF_0_SM_ROOT_ENTRY_RSVD_11_1_MASK UINT64_C(0x0000000000000ffe)
171/** LCTP: Lower Context-Table Pointer */
172#define VTD_BF_0_SM_ROOT_ENTRY_LCTP_SHIFT 12
173#define VTD_BF_0_SM_ROOT_ENTRY_LCTP_MASK UINT64_C(0xfffffffffffff000)
174RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_SM_ROOT_ENTRY_, UINT64_C(0), UINT64_MAX,
175 (LP, RSVD_11_1, LCTP));
176
177/** UP: Upper Present. */
178#define VTD_BF_1_SM_ROOT_ENTRY_UP_SHIFT 0
179#define VTD_BF_1_SM_ROOT_ENTRY_UP_MASK UINT64_C(0x0000000000000001)
180/** R: Reserved (bits 11:1). */
181#define VTD_BF_1_SM_ROOT_ENTRY_RSVD_11_1_SHIFT 1
182#define VTD_BF_1_SM_ROOT_ENTRY_RSVD_11_1_MASK UINT64_C(0x0000000000000ffe)
183/** UCTP: Upper Context-Table Pointer. */
184#define VTD_BF_1_SM_ROOT_ENTRY_UCTP_SHIFT 12
185#define VTD_BF_1_SM_ROOT_ENTRY_UCTP_MASK UINT64_C(0xfffffffffffff000)
186RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_SM_ROOT_ENTRY_, UINT64_C(0), UINT64_MAX,
187 (UP, RSVD_11_1, UCTP));
188
189/** Scalable-mode root entry. */
190typedef struct VTD_SM_ROOT_ENTRY_T
191{
192 /** The lower scalable-mode root entry. */
193 uint64_t uLower;
194 /** The upper scalable-mode root entry. */
195 uint64_t uUpper;
196} VTD_SM_ROOT_ENTRY_T;
197/** Pointer to a scalable-mode root entry. */
198typedef VTD_SM_ROOT_ENTRY_T *PVTD_SM_ROOT_ENTRY_T;
199/** Pointer to a const scalable-mode root entry. */
200typedef VTD_SM_ROOT_ENTRY_T const *PCVTD_SM_ROOT_ENTRY_T;
201/** @} */
202
203
204/** @name Context Entry.
205 * In accordance with the Intel spec.
206 * @{ */
207/** P: Present. */
208#define VTD_BF_0_CONTEXT_ENTRY_P_SHIFT 0
209#define VTD_BF_0_CONTEXT_ENTRY_P_MASK UINT64_C(0x0000000000000001)
210/** FPD: Fault Processing Disable. */
211#define VTD_BF_0_CONTEXT_ENTRY_FPD_SHIFT 1
212#define VTD_BF_0_CONTEXT_ENTRY_FPD_MASK UINT64_C(0x0000000000000002)
213/** TT: Translation Type. */
214#define VTD_BF_0_CONTEXT_ENTRY_TT_SHIFT 2
215#define VTD_BF_0_CONTEXT_ENTRY_TT_MASK UINT64_C(0x000000000000000c)
216/** R: Reserved (bits 11:4). */
217#define VTD_BF_0_CONTEXT_ENTRY_RSVD_11_4_SHIFT 4
218#define VTD_BF_0_CONTEXT_ENTRY_RSVD_11_4_MASK UINT64_C(0x0000000000000ff0)
219/** SLPTPTR: Second Level Page Translation Pointer. */
220#define VTD_BF_0_CONTEXT_ENTRY_SLPTPTR_SHIFT 12
221#define VTD_BF_0_CONTEXT_ENTRY_SLPTPTR_MASK UINT64_C(0xfffffffffffff000)
222RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_CONTEXT_ENTRY_, UINT64_C(0), UINT64_MAX,
223 (P, FPD, TT, RSVD_11_4, SLPTPTR));
224
225/** AW: Address Width. */
226#define VTD_BF_1_CONTEXT_ENTRY_AW_SHIFT 0
227#define VTD_BF_1_CONTEXT_ENTRY_AW_MASK UINT64_C(0x0000000000000007)
228/** IGN: Ignored (bits 6:3). */
229#define VTD_BF_1_CONTEXT_ENTRY_IGN_6_3_SHIFT 3
230#define VTD_BF_1_CONTEXT_ENTRY_IGN_6_3_MASK UINT64_C(0x0000000000000078)
231/** R: Reserved (bit 7). */
232#define VTD_BF_1_CONTEXT_ENTRY_RSVD_7_SHIFT 7
233#define VTD_BF_1_CONTEXT_ENTRY_RSVD_7_MASK UINT64_C(0x0000000000000080)
234/** DID: Domain Identifier. */
235#define VTD_BF_1_CONTEXT_ENTRY_DID_SHIFT 8
236#define VTD_BF_1_CONTEXT_ENTRY_DID_MASK UINT64_C(0x0000000000ffff00)
237/** R: Reserved (bits 63:24). */
238#define VTD_BF_1_CONTEXT_ENTRY_RSVD_63_24_SHIFT 24
239#define VTD_BF_1_CONTEXT_ENTRY_RSVD_63_24_MASK UINT64_C(0xffffffffff000000)
240RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_CONTEXT_ENTRY_, UINT64_C(0), UINT64_MAX,
241 (AW, IGN_6_3, RSVD_7, DID, RSVD_63_24));
242
243/** Context Entry. */
244typedef struct VTD_CONTEXT_ENTRY_T
245{
246 /** The qwords in the context entry. */
247 uint64_t au64[2];
248} VTD_CONTEXT_ENTRY_T;
249/** Pointer to a context entry. */
250typedef VTD_CONTEXT_ENTRY_T *PVTD_CONTEXT_ENTRY_T;
251/** Pointer to a const context entry. */
252typedef VTD_CONTEXT_ENTRY_T const *PCVTD_CONTEXT_ENTRY_T;
253/** @} */
254
255
256/** @name Scalable-mode Context Entry.
257 * In accordance with the Intel spec.
258 * @{ */
259/** P: Present. */
260#define VTD_BF_0_SM_CONTEXT_ENTRY_P_SHIFT 0
261#define VTD_BF_0_SM_CONTEXT_ENTRY_P_MASK UINT64_C(0x0000000000000001)
262/** FPD: Fault Processing Disable. */
263#define VTD_BF_0_SM_CONTEXT_ENTRY_FPD_SHIFT 1
264#define VTD_BF_0_SM_CONTEXT_ENTRY_FPD_MASK UINT64_C(0x0000000000000002)
265/** DTE: Device-TLB Enable. */
266#define VTD_BF_0_SM_CONTEXT_ENTRY_DTE_SHIFT 2
267#define VTD_BF_0_SM_CONTEXT_ENTRY_DTE_MASK UINT64_C(0x0000000000000004)
268/** PASIDE: PASID Enable. */
269#define VTD_BF_0_SM_CONTEXT_ENTRY_PASIDE_SHIFT 3
270#define VTD_BF_0_SM_CONTEXT_ENTRY_PASIDE_MASK UINT64_C(0x0000000000000008)
271/** PRE: Page Request Enable. */
272#define VTD_BF_0_SM_CONTEXT_ENTRY_PRE_SHIFT 4
273#define VTD_BF_0_SM_CONTEXT_ENTRY_PRE_MASK UINT64_C(0x0000000000000010)
274/** R: Reserved (bits 8:5). */
275#define VTD_BF_0_SM_CONTEXT_ENTRY_RSVD_8_5_SHIFT 5
276#define VTD_BF_0_SM_CONTEXT_ENTRY_RSVD_8_5_MASK UINT64_C(0x00000000000001e0)
277/** PDTS: PASID Directory Size. */
278#define VTD_BF_0_SM_CONTEXT_ENTRY_PDTS_SHIFT 9
279#define VTD_BF_0_SM_CONTEXT_ENTRY_PDTS_MASK UINT64_C(0x0000000000000e00)
280/** PASIDDIRPTR: PASID Directory Pointer. */
281#define VTD_BF_0_SM_CONTEXT_ENTRY_PASIDDIRPTR_SHIFT 12
282#define VTD_BF_0_SM_CONTEXT_ENTRY_PASIDDIRPTR_MASK UINT64_C(0xfffffffffffff000)
283RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_SM_CONTEXT_ENTRY_, UINT64_C(0), UINT64_MAX,
284 (P, FPD, DTE, PASIDE, PRE, RSVD_8_5, PDTS, PASIDDIRPTR));
285
286/** RID_PASID: Requested Id to PASID assignment. */
287#define VTD_BF_1_SM_CONTEXT_ENTRY_RID_PASID_SHIFT 0
288#define VTD_BF_1_SM_CONTEXT_ENTRY_RID_PASID_MASK UINT64_C(0x00000000000fffff)
289/** RID_PRIV: Requested Id to PrivilegeModeRequested assignment. */
290#define VTD_BF_1_SM_CONTEXT_ENTRY_RID_PRIV_SHIFT 20
291#define VTD_BF_1_SM_CONTEXT_ENTRY_RID_PRIV_MASK UINT64_C(0x0000000000100000)
292/** R: Reserved (bits 63:21). */
293#define VTD_BF_1_SM_CONTEXT_ENTRY_RSVD_63_21_SHIFT 21
294#define VTD_BF_1_SM_CONTEXT_ENTRY_RSVD_63_21_MASK UINT64_C(0xffffffffffe00000)
295RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_SM_CONTEXT_ENTRY_, UINT64_C(0), UINT64_MAX,
296 (RID_PASID, RID_PRIV, RSVD_63_21));
297
298/** Context Entry. */
299typedef struct VTD_SM_CONTEXT_ENTRY_T
300{
301 /** The qwords in the scalable-mode context entry. */
302 uint64_t au64[4];
303} VTD_SM_CONTEXT_ENTRY_T;
304/** Pointer to a scalable-mode context entry. */
305typedef VTD_SM_CONTEXT_ENTRY_T *PVTD_SM_CONTEXT_ENTRY_T;
306/** Pointer to a const scalable-mode context entry. */
307typedef VTD_SM_CONTEXT_ENTRY_T const *PCVTD_SM_CONTEXT_ENTRY_T;
308/** @} */
309
310
311/** @name Scalable-mode PASID Directory Entry.
312 * In accordance with the Intel spec.
313 * @{ */
314/** P: Present. */
315#define VTD_BF_SM_PASID_DIR_ENTRY_P_SHIFT 0
316#define VTD_BF_SM_PASID_DIR_ENTRY_P_MASK UINT64_C(0x0000000000000001)
317/** FPD: Fault Processing Disable. */
318#define VTD_BF_SM_PASID_DIR_ENTRY_FPD_SHIFT 1
319#define VTD_BF_SM_PASID_DIR_ENTRY_FPD_MASK UINT64_C(0x0000000000000002)
320/** R: Reserved (bits 11:2). */
321#define VTD_BF_SM_PASID_DIR_ENTRY_RSVD_11_2_SHIFT 2
322#define VTD_BF_SM_PASID_DIR_ENTRY_RSVD_11_2_MASK UINT64_C(0x0000000000000ffc)
323/** SMPTBLPTR: Scalable Mode PASID Table Pointer. */
324#define VTD_BF_SM_PASID_DIR_ENTRY_SMPTBLPTR_SHIFT 12
325#define VTD_BF_SM_PASID_DIR_ENTRY_SMPTBLPTR_MASK UINT64_C(0xfffffffffffff000)
326RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_SM_PASID_DIR_ENTRY_, UINT64_C(0), UINT64_MAX,
327 (P, FPD, RSVD_11_2, SMPTBLPTR));
328
329/** Scalable-mode PASID Directory Entry. */
330typedef struct VTD_SM_PASID_DIR_ENTRY_T
331{
332 /** The scalable-mode PASID directory entry. */
333 uint64_t u;
334} VTD_SM_PASID_DIR_ENTRY_T;
335/** Pointer to a scalable-mode PASID directory entry. */
336typedef VTD_SM_PASID_DIR_ENTRY_T *PVTD_SM_PASID_DIR_ENTRY_T;
337/** Pointer to a const scalable-mode PASID directory entry. */
338typedef VTD_SM_PASID_DIR_ENTRY_T const *PCVTD_SM_PASID_DIR_ENTRY_T;
339/** @} */
340
341
342/** @name Scalable-mode PASID Table Entry.
343 * In accordance with the Intel spec.
344 * @{ */
345/** P: Present. */
346#define VTD_BF_0_SM_PASID_TBL_ENTRY_P_SHIFT 0
347#define VTD_BF_0_SM_PASID_TBL_ENTRY_P_MASK UINT64_C(0x0000000000000001)
348/** FPD: Fault Processing Disable. */
349#define VTD_BF_0_SM_PASID_TBL_ENTRY_FPD_SHIFT 1
350#define VTD_BF_0_SM_PASID_TBL_ENTRY_FPD_MASK UINT64_C(0x0000000000000002)
351/** AW: Address Width. */
352#define VTD_BF_0_SM_PASID_TBL_ENTRY_AW_SHIFT 2
353#define VTD_BF_0_SM_PASID_TBL_ENTRY_AW_MASK UINT64_C(0x000000000000001c)
354/** SLEE: Second-Level Execute Enable. */
355#define VTD_BF_0_SM_PASID_TBL_ENTRY_SLEE_SHIFT 5
356#define VTD_BF_0_SM_PASID_TBL_ENTRY_SLEE_MASK UINT64_C(0x0000000000000020)
357/** PGTT: PASID Granular Translation Type. */
358#define VTD_BF_0_SM_PASID_TBL_ENTRY_PGTT_SHIFT 6
359#define VTD_BF_0_SM_PASID_TBL_ENTRY_PGTT_MASK UINT64_C(0x00000000000001c0)
360/** SLADE: Second-Level Address/Dirty Enable. */
361#define VTD_BF_0_SM_PASID_TBL_ENTRY_SLADE_SHIFT 9
362#define VTD_BF_0_SM_PASID_TBL_ENTRY_SLADE_MASK UINT64_C(0x0000000000000200)
363/** R: Reserved (bits 11:10). */
364#define VTD_BF_0_SM_PASID_TBL_ENTRY_RSVD_11_10_SHIFT 10
365#define VTD_BF_0_SM_PASID_TBL_ENTRY_RSVD_11_10_MASK UINT64_C(0x0000000000000c00)
366/** SLPTPTR: Second-Level Page Table Pointer. */
367#define VTD_BF_0_SM_PASID_TBL_ENTRY_SLPTPTR_SHIFT 12
368#define VTD_BF_0_SM_PASID_TBL_ENTRY_SLPTPTR_MASK UINT64_C(0xfffffffffffff000)
369RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_SM_PASID_TBL_ENTRY_, UINT64_C(0), UINT64_MAX,
370 (P, FPD, AW, SLEE, PGTT, SLADE, RSVD_11_10, SLPTPTR));
371
372/** DID: Domain Identifer. */
373#define VTD_BF_1_SM_PASID_TBL_ENTRY_DID_SHIFT 0
374#define VTD_BF_1_SM_PASID_TBL_ENTRY_DID_MASK UINT64_C(0x000000000000ffff)
375/** R: Reserved (bits 22:16). */
376#define VTD_BF_1_SM_PASID_TBL_ENTRY_RSVD_22_16_SHIFT 16
377#define VTD_BF_1_SM_PASID_TBL_ENTRY_RSVD_22_16_MASK UINT64_C(0x00000000007f0000)
378/** PWSNP: Page-Walk Snoop. */
379#define VTD_BF_1_SM_PASID_TBL_ENTRY_PWSNP_SHIFT 23
380#define VTD_BF_1_SM_PASID_TBL_ENTRY_PWSNP_MASK UINT64_C(0x0000000000800000)
381/** PGSNP: Page Snoop. */
382#define VTD_BF_1_SM_PASID_TBL_ENTRY_PGSNP_SHIFT 24
383#define VTD_BF_1_SM_PASID_TBL_ENTRY_PGSNP_MASK UINT64_C(0x0000000001000000)
384/** CD: Cache Disable. */
385#define VTD_BF_1_SM_PASID_TBL_ENTRY_CD_SHIFT 25
386#define VTD_BF_1_SM_PASID_TBL_ENTRY_CD_MASK UINT64_C(0x0000000002000000)
387/** EMTE: Extended Memory Type Enable. */
388#define VTD_BF_1_SM_PASID_TBL_ENTRY_EMTE_SHIFT 26
389#define VTD_BF_1_SM_PASID_TBL_ENTRY_EMTE_MASK UINT64_C(0x0000000004000000)
390/** EMT: Extended Memory Type. */
391#define VTD_BF_1_SM_PASID_TBL_ENTRY_EMT_SHIFT 27
392#define VTD_BF_1_SM_PASID_TBL_ENTRY_EMT_MASK UINT64_C(0x0000000038000000)
393/** PWT: Page-Level Write Through. */
394#define VTD_BF_1_SM_PASID_TBL_ENTRY_PWT_SHIFT 30
395#define VTD_BF_1_SM_PASID_TBL_ENTRY_PWT_MASK UINT64_C(0x0000000040000000)
396/** PCD: Page-Level Cache Disable. */
397#define VTD_BF_1_SM_PASID_TBL_ENTRY_PCD_SHIFT 31
398#define VTD_BF_1_SM_PASID_TBL_ENTRY_PCD_MASK UINT64_C(0x0000000080000000)
399/** PAT: Page Attribute Table. */
400#define VTD_BF_1_SM_PASID_TBL_ENTRY_PAT_SHIFT 32
401#define VTD_BF_1_SM_PASID_TBL_ENTRY_PAT_MASK UINT64_C(0xffffffff00000000)
402RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_SM_PASID_TBL_ENTRY_, UINT64_C(0), UINT64_MAX,
403 (DID, RSVD_22_16, PWSNP, PGSNP, CD, EMTE, EMT, PWT, PCD, PAT));
404
405/** SRE: Supervisor Request Enable. */
406#define VTD_BF_2_SM_PASID_TBL_ENTRY_SRE_SHIFT 0
407#define VTD_BF_2_SM_PASID_TBL_ENTRY_SRE_MASK UINT64_C(0x0000000000000001)
408/** ERE: Execute Request Enable. */
409#define VTD_BF_2_SM_PASID_TBL_ENTRY_ERE_SHIFT 1
410#define VTD_BF_2_SM_PASID_TBL_ENTRY_ERE_MASK UINT64_C(0x0000000000000002)
411/** FLPM: First Level Paging Mode. */
412#define VTD_BF_2_SM_PASID_TBL_ENTRY_FLPM_SHIFT 2
413#define VTD_BF_2_SM_PASID_TBL_ENTRY_FLPM_MASK UINT64_C(0x000000000000000c)
414/** WPE: Write Protect Enable. */
415#define VTD_BF_2_SM_PASID_TBL_ENTRY_WPE_SHIFT 4
416#define VTD_BF_2_SM_PASID_TBL_ENTRY_WPE_MASK UINT64_C(0x0000000000000010)
417/** NXE: No-Execute Enable. */
418#define VTD_BF_2_SM_PASID_TBL_ENTRY_NXE_SHIFT 5
419#define VTD_BF_2_SM_PASID_TBL_ENTRY_NXE_MASK UINT64_C(0x0000000000000020)
420/** SMEP: Supervisor Mode Execute Prevent. */
421#define VTD_BF_2_SM_PASID_TBL_ENTRY_SMPE_SHIFT 6
422#define VTD_BF_2_SM_PASID_TBL_ENTRY_SMPE_MASK UINT64_C(0x0000000000000040)
423/** EAFE: Extended Accessed Flag Enable. */
424#define VTD_BF_2_SM_PASID_TBL_ENTRY_EAFE_SHIFT 7
425#define VTD_BF_2_SM_PASID_TBL_ENTRY_EAFE_MASK UINT64_C(0x0000000000000080)
426/** R: Reserved (bits 11:8). */
427#define VTD_BF_2_SM_PASID_TBL_ENTRY_RSVD_11_8_SHIFT 8
428#define VTD_BF_2_SM_PASID_TBL_ENTRY_RSVD_11_8_MASK UINT64_C(0x0000000000000f00)
429/** FLPTPTR: First Level Page Table Pointer. */
430#define VTD_BF_2_SM_PASID_TBL_ENTRY_FLPTPTR_SHIFT 12
431#define VTD_BF_2_SM_PASID_TBL_ENTRY_FLPTPTR_MASK UINT64_C(0xfffffffffffff000)
432RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_2_SM_PASID_TBL_ENTRY_, UINT64_C(0), UINT64_MAX,
433 (SRE, ERE, FLPM, WPE, NXE, SMPE, EAFE, RSVD_11_8, FLPTPTR));
434
435/** Scalable-mode PASID Table Entry. */
436typedef struct VTD_SM_PASID_TBL_ENTRY_T
437{
438 /** The qwords in the scalable-mode PASID table entry. */
439 uint64_t au64[8];
440} VTD_SM_PASID_TBL_ENTRY_T;
441/** Pointer to a scalable-mode PASID table entry. */
442typedef VTD_SM_PASID_TBL_ENTRY_T *PVTD_SM_PASID_TBL_ENTRY_T;
443/** Pointer to a const scalable-mode PASID table entry. */
444typedef VTD_SM_PASID_TBL_ENTRY_T const *PCVTD_SM_PASID_TBL_ENTRY_T;
445/** @} */
446
447
448/** @name First-Level Paging Entry.
449 * In accordance with the Intel spec.
450 * @{ */
451/** P: Present. */
452#define VTD_BF_FLP_ENTRY_P_SHIFT 0
453#define VTD_BF_FLP_ENTRY_P_MASK UINT64_C(0x0000000000000001)
454/** R/W: Read/Write. */
455#define VTD_BF_FLP_ENTRY_RW_SHIFT 1
456#define VTD_BF_FLP_ENTRY_RW_MASK UINT64_C(0x0000000000000002)
457/** U/S: User/Supervisor. */
458#define VTD_BF_FLP_ENTRY_US_SHIFT 2
459#define VTD_BF_FLP_ENTRY_US_MASK UINT64_C(0x0000000000000004)
460/** PWT: Page-Level Write Through. */
461#define VTD_BF_FLP_ENTRY_PWT_SHIFT 3
462#define VTD_BF_FLP_ENTRY_PWT_MASK UINT64_C(0x0000000000000008)
463/** PC: Page-Level Cache Disable. */
464#define VTD_BF_FLP_ENTRY_PCD_SHIFT 4
465#define VTD_BF_FLP_ENTRY_PCD_MASK UINT64_C(0x0000000000000010)
466/** A: Accessed. */
467#define VTD_BF_FLP_ENTRY_A_SHIFT 5
468#define VTD_BF_FLP_ENTRY_A_MASK UINT64_C(0x0000000000000020)
469/** IGN: Ignored (bit 6). */
470#define VTD_BF_FLP_ENTRY_IGN_6_SHIFT 6
471#define VTD_BF_FLP_ENTRY_IGN_6_MASK UINT64_C(0x0000000000000040)
472/** R: Reserved (bit 7). */
473#define VTD_BF_FLP_ENTRY_RSVD_7_SHIFT 7
474#define VTD_BF_FLP_ENTRY_RSVD_7_MASK UINT64_C(0x0000000000000080)
475/** IGN: Ignored (bits 9:8). */
476#define VTD_BF_FLP_ENTRY_IGN_9_8_SHIFT 8
477#define VTD_BF_FLP_ENTRY_IGN_9_8_MASK UINT64_C(0x0000000000000300)
478/** EA: Extended Accessed. */
479#define VTD_BF_FLP_ENTRY_EA_SHIFT 10
480#define VTD_BF_FLP_ENTRY_EA_MASK UINT64_C(0x0000000000000400)
481/** IGN: Ignored (bit 11). */
482#define VTD_BF_FLP_ENTRY_IGN_11_SHIFT 11
483#define VTD_BF_FLP_ENTRY_IGN_11_MASK UINT64_C(0x0000000000000800)
484/** ADDR: Address. */
485#define VTD_BF_FLP_ENTRY_ADDR_SHIFT 12
486#define VTD_BF_FLP_ENTRY_ADDR_MASK UINT64_C(0x000ffffffffff000)
487/** IGN: Ignored (bits 62:52). */
488#define VTD_BF_FLP_ENTRY_IGN_62_52_SHIFT 52
489#define VTD_BF_FLP_ENTRY_IGN_62_52_MASK UINT64_C(0x7ff0000000000000)
490/** XD: Execute Disabled. */
491#define VTD_BF_FLP_ENTRY_XD_SHIFT 63
492#define VTD_BF_FLP_ENTRY_XD_MASK UINT64_C(0x8000000000000000)
493RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_FLP_ENTRY_, UINT64_C(0), UINT64_MAX,
494 (P, RW, US, PWT, PCD, A, IGN_6, RSVD_7, IGN_9_8, EA, IGN_11, ADDR, IGN_62_52, XD));
495
496/** First-Level Paging Entry. */
497typedef struct VTD_FLP_ENTRY_T
498{
499 /** The first-level paging entry. */
500 uint64_t u;
501} VTD_FLP_ENTRY_T;
502/** Pointer to a first-level paging entry. */
503typedef VTD_FLP_ENTRY_T *PVTD_FLP_ENTRY_T;
504/** Pointer to a const first-level paging entry. */
505typedef VTD_FLP_ENTRY_T const *PCVTD_FLP_ENTRY_T;
506/** @} */
507
508
509/** @name Second-Level Paging Entry.
510 * In accordance with the Intel spec.
511 * @{ */
512/** R: Read. */
513#define VTD_BF_SLP_ENTRY_R_SHIFT 0
514#define VTD_BF_SLP_ENTRY_R_MASK UINT64_C(0x0000000000000001)
515/** W: Write. */
516#define VTD_BF_SLP_ENTRY_W_SHIFT 1
517#define VTD_BF_SLP_ENTRY_W_MASK UINT64_C(0x0000000000000002)
518/** X: Execute. */
519#define VTD_BF_SLP_ENTRY_X_SHIFT 2
520#define VTD_BF_SLP_ENTRY_X_MASK UINT64_C(0x0000000000000004)
521/** IGN: Ignored (bits 6:3). */
522#define VTD_BF_SLP_ENTRY_IGN_6_3_SHIFT 3
523#define VTD_BF_SLP_ENTRY_IGN_6_3_MASK UINT64_C(0x0000000000000078)
524/** R: Reserved (bit 7). */
525#define VTD_BF_SLP_ENTRY_RSVD_7_SHIFT 7
526#define VTD_BF_SLP_ENTRY_RSVD_7_MASK UINT64_C(0x0000000000000080)
527/** A: Accessed. */
528#define VTD_BF_SLP_ENTRY_A_SHIFT 8
529#define VTD_BF_SLP_ENTRY_A_MASK UINT64_C(0x0000000000000100)
530/** IGN: Ignored (bits 10:9). */
531#define VTD_BF_SLP_ENTRY_IGN_10_9_SHIFT 9
532#define VTD_BF_SLP_ENTRY_IGN_10_9_MASK UINT64_C(0x0000000000000600)
533/** R: Reserved (bit 11). */
534#define VTD_BF_SLP_ENTRY_RSVD_11_SHIFT 11
535#define VTD_BF_SLP_ENTRY_RSVD_11_MASK UINT64_C(0x0000000000000800)
536/** ADDR: Address. */
537#define VTD_BF_SLP_ENTRY_ADDR_SHIFT 12
538#define VTD_BF_SLP_ENTRY_ADDR_MASK UINT64_C(0x000ffffffffff000)
539/** IGN: Ignored (bits 61:52). */
540#define VTD_BF_SLP_ENTRY_IGN_61_52_SHIFT 52
541#define VTD_BF_SLP_ENTRY_IGN_61_52_MASK UINT64_C(0x3ff0000000000000)
542/** R: Reserved (bit 62). */
543#define VTD_BF_SLP_ENTRY_RSVD_62_SHIFT 62
544#define VTD_BF_SLP_ENTRY_RSVD_62_MASK UINT64_C(0x4000000000000000)
545/** IGN: Ignored (bit 63). */
546#define VTD_BF_SLP_ENTRY_IGN_63_SHIFT 63
547#define VTD_BF_SLP_ENTRY_IGN_63_MASK UINT64_C(0x8000000000000000)
548RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_SLP_ENTRY_, UINT64_C(0), UINT64_MAX,
549 (R, W, X, IGN_6_3, RSVD_7, A, IGN_10_9, RSVD_11, ADDR, IGN_61_52, RSVD_62, IGN_63));
550
551/** Second-Level Paging Entry. */
552typedef struct VTD_SLP_ENTRY_T
553{
554 /** The second-level paging entry. */
555 uint64_t u;
556} VTD_SLP_ENTRY_T;
557/** Pointer to a second-level paging entry. */
558typedef VTD_SLP_ENTRY_T *PVTD_SLP_ENTRY_T;
559/** Pointer to a const second-level paging entry. */
560typedef VTD_SLP_ENTRY_T const *PCVTD_SLP_ENTRY_T;
561/** @} */
562
563
564/** @name Fault Record.
565 * In accordance with the Intel spec.
566 * @{ */
567/** R: Reserved (bits 11:0). */
568#define VTD_BF_0_FAULT_RECORD_RSVD_11_0_SHIFT 0
569#define VTD_BF_0_FAULT_RECORD_RSVD_11_0_MASK UINT64_C(0x0000000000000fff)
570/** FI: Fault Information. */
571#define VTD_BF_0_FAULT_RECORD_FI_SHIFT 12
572#define VTD_BF_0_FAULT_RECORD_FI_MASK UINT64_C(0xfffffffffffff000)
573RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_FAULT_RECORD_, UINT64_C(0), UINT64_MAX,
574 (RSVD_11_0, FI));
575
576/** SID: Source identifier. */
577#define VTD_BF_1_FAULT_RECORD_SID_SHIFT 0
578#define VTD_BF_1_FAULT_RECORD_SID_MASK UINT64_C(0x000000000000ffff)
579/** R: Reserved (bits 28:16). */
580#define VTD_BF_1_FAULT_RECORD_RSVD_28_16_SHIFT 16
581#define VTD_BF_1_FAULT_RECORD_RSVD_28_16_MASK UINT64_C(0x000000001fff0000)
582/** PRIV: Privilege Mode Requested. */
583#define VTD_BF_1_FAULT_RECORD_PRIV_SHIFT 29
584#define VTD_BF_1_FAULT_RECORD_PRIV_MASK UINT64_C(0x0000000020000000)
585/** EXE: Execute Permission Requested. */
586#define VTD_BF_1_FAULT_RECORD_EXE_SHIFT 30
587#define VTD_BF_1_FAULT_RECORD_EXE_MASK UINT64_C(0x0000000040000000)
588/** PP: PASID Present. */
589#define VTD_BF_1_FAULT_RECORD_PP_SHIFT 31
590#define VTD_BF_1_FAULT_RECORD_PP_MASK UINT64_C(0x0000000080000000)
591/** FR: Fault Reason. */
592#define VTD_BF_1_FAULT_RECORD_FR_SHIFT 32
593#define VTD_BF_1_FAULT_RECORD_FR_MASK UINT64_C(0x000000ff00000000)
594/** PV: PASID Value. */
595#define VTD_BF_1_FAULT_RECORD_PV_SHIFT 40
596#define VTD_BF_1_FAULT_RECORD_PV_MASK UINT64_C(0x0fffff0000000000)
597/** AT: Address Type. */
598#define VTD_BF_1_FAULT_RECORD_AT_SHIFT 60
599#define VTD_BF_1_FAULT_RECORD_AT_MASK UINT64_C(0x3000000000000000)
600/** T: Type. */
601#define VTD_BF_1_FAULT_RECORD_T_SHIFT 62
602#define VTD_BF_1_FAULT_RECORD_T_MASK UINT64_C(0x4000000000000000)
603/** R: Reserved (bit 127). */
604#define VTD_BF_1_FAULT_RECORD_RSVD_63_SHIFT 63
605#define VTD_BF_1_FAULT_RECORD_RSVD_63_MASK UINT64_C(0x8000000000000000)
606RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_FAULT_RECORD_, UINT64_C(0), UINT64_MAX,
607 (SID, RSVD_28_16, PRIV, EXE, PP, FR, PV, AT, T, RSVD_63));
608
609/** Fault record. */
610typedef struct VTD_FAULT_RECORD_T
611{
612 /** The qwords in the fault record. */
613 uint64_t au64[2];
614} VTD_FAULT_RECORD_T;
615/** Pointer to a fault record. */
616typedef VTD_FAULT_RECORD_T *PVTD_FAULT_RECORD_T;
617/** Pointer to a const fault record. */
618typedef VTD_FAULT_RECORD_T const *PCVTD_FAULT_RECORD_T;
619/** @} */
620
621
622/** @name Interrupt Remapping Table Entry (IRTE) for Remapped Interrupts.
623 * In accordance with the Intel spec.
624 * @{ */
625/** P: Present. */
626#define VTD_BF_0_IRTE_P_SHIFT 0
627#define VTD_BF_0_IRTE_P_MASK UINT64_C(0x0000000000000001)
628/** FPD: Fault Processing Disable. */
629#define VTD_BF_0_IRTE_FPD_SHIFT 1
630#define VTD_BF_0_IRTE_FPD_MASK UINT64_C(0x0000000000000002)
631/** DM: Destination Mode (0=physical, 1=logical). */
632#define VTD_BF_0_IRTE_DM_SHIFT 2
633#define VTD_BF_0_IRTE_DM_MASK UINT64_C(0x0000000000000004)
634/** RH: Redirection Hint. */
635#define VTD_BF_0_IRTE_RH_SHIFT 3
636#define VTD_BF_0_IRTE_RH_MASK UINT64_C(0x0000000000000008)
637/** TM: Trigger Mode. */
638#define VTD_BF_0_IRTE_TM_SHIFT 4
639#define VTD_BF_0_IRTE_TM_MASK UINT64_C(0x0000000000000010)
640/** DLM: Delivery Mode. */
641#define VTD_BF_0_IRTE_DLM_SHIFT 5
642#define VTD_BF_0_IRTE_DLM_MASK UINT64_C(0x00000000000000e0)
643/** AVL: Available. */
644#define VTD_BF_0_IRTE_AVAIL_SHIFT 8
645#define VTD_BF_0_IRTE_AVAIL_MASK UINT64_C(0x0000000000000f00)
646/** R: Reserved (bits 14:12). */
647#define VTD_BF_0_IRTE_RSVD_14_12_SHIFT 12
648#define VTD_BF_0_IRTE_RSVD_14_12_MASK UINT64_C(0x0000000000007000)
649/** IM: IRTE Mode. */
650#define VTD_BF_0_IRTE_IM_SHIFT 15
651#define VTD_BF_0_IRTE_IM_MASK UINT64_C(0x0000000000008000)
652/** V: Vector. */
653#define VTD_BF_0_IRTE_V_SHIFT 16
654#define VTD_BF_0_IRTE_V_MASK UINT64_C(0x0000000000ff0000)
655/** R: Reserved (bits 31:24). */
656#define VTD_BF_0_IRTE_RSVD_31_24_SHIFT 24
657#define VTD_BF_0_IRTE_RSVD_31_24_MASK UINT64_C(0x00000000ff000000)
658/** DST: Desination Id. */
659#define VTD_BF_0_IRTE_DST_SHIFT 32
660#define VTD_BF_0_IRTE_DST_MASK UINT64_C(0xffffffff00000000)
661RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_IRTE_, UINT64_C(0), UINT64_MAX,
662 (P, FPD, DM, RH, TM, DLM, AVAIL, RSVD_14_12, IM, V, RSVD_31_24, DST));
663
664/** SID: Source Identifier. */
665#define VTD_BF_1_IRTE_SID_SHIFT 0
666#define VTD_BF_1_IRTE_SID_MASK UINT64_C(0x000000000000ffff)
667/** SQ: Source-Id Qualifier. */
668#define VTD_BF_1_IRTE_SQ_SHIFT 16
669#define VTD_BF_1_IRTE_SQ_MASK UINT64_C(0x0000000000030000)
670/** SVT: Source Validation Type. */
671#define VTD_BF_1_IRTE_SVT_SHIFT 18
672#define VTD_BF_1_IRTE_SVT_MASK UINT64_C(0x00000000000c0000)
673/** R: Reserved (bits 127:84). */
674#define VTD_BF_1_IRTE_RSVD_63_20_SHIFT 20
675#define VTD_BF_1_IRTE_RSVD_63_20_MASK UINT64_C(0xfffffffffff00000)
676RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_IRTE_, UINT64_C(0), UINT64_MAX,
677 (SID, SQ, SVT, RSVD_63_20));
678
679/** Interrupt Remapping Table Entry (IRTE) for remapped interrupts. */
680typedef struct VTD_IRTE_T
681{
682 /** The qwords in the IRTE. */
683 uint64_t au64[2];
684} VTD_IRTE_T;
685/** Pointer to an IRTE. */
686typedef VTD_IRTE_T *PVTD_IRTE_T;
687/** Pointer to a const IRTE. */
688typedef VTD_IRTE_T const *PCVTD_IRTE_T;
689/** @} */
690
691
692/** @name Version Register (VER_REG).
693 * @{ */
694/** Min: Minor Version Number. */
695#define VTX_BF_VER_REG_MIN_SHIFT 0
696#define VTX_BF_VER_REG_MIN_MASK UINT32_C(0x0000000f)
697/** Max: Major Version Number. */
698#define VTX_BF_VER_REG_MAX_SHIFT 4
699#define VTX_BF_VER_REG_MAX_MASK UINT32_C(0x000000f0)
700/** R: Reserved (bits 31:8). */
701#define VTX_BF_VER_REG_RSVD_31_8_SHIFT 8
702#define VTX_BF_VER_REG_RSVD_31_8_MASK UINT32_C(0xffffff00)
703RT_BF_ASSERT_COMPILE_CHECKS(VTX_BF_VER_REG_, UINT32_C(0), UINT32_MAX,
704 (MIN, MAX, RSVD_31_8));
705/** RW: Read/write mask. */
706#define VTD_VER_REG_RW_MASK UINT32_C(0)
707/** @} */
708
709
710/** @name Capability Register (CAP_REG).
711 * @{ */
712/** ND: Number of domains supported. */
713#define VTD_BF_CAP_REG_ND_SHIFT 0
714#define VTD_BF_CAP_REG_ND_MASK UINT64_C(0x0000000000000007)
715/** AFL: Advanced Fault Logging. */
716#define VTD_BF_CAP_REG_AFL_SHIFT 3
717#define VTD_BF_CAP_REG_AFL_MASK UINT64_C(0x0000000000000008)
718/** RWBF: Required Write-Buffer Flushing. */
719#define VTD_BF_CAP_REG_RWBF_SHIFT 4
720#define VTD_BF_CAP_REG_RWBF_MASK UINT64_C(0x0000000000000010)
721/** PLMR: Protected Low-Memory Region. */
722#define VTD_BF_CAP_REG_PLMR_SHIFT 5
723#define VTD_BF_CAP_REG_PLMR_MASK UINT64_C(0x0000000000000020)
724/** PHMR: Protected High-Memory Region. */
725#define VTD_BF_CAP_REG_PHMR_SHIFT 6
726#define VTD_BF_CAP_REG_PHMR_MASK UINT64_C(0x0000000000000040)
727/** CM: Caching Mode. */
728#define VTD_BF_CAP_REG_CM_SHIFT 7
729#define VTD_BF_CAP_REG_CM_MASK UINT64_C(0x0000000000000080)
730/** SAGAW: Supported Adjusted Guest Address Widths. */
731#define VTD_BF_CAP_REG_SAGAW_SHIFT 8
732#define VTD_BF_CAP_REG_SAGAW_MASK UINT64_C(0x0000000000001f00)
733/** R: Reserved (bits 15:13). */
734#define VTD_BF_CAP_REG_RSVD_15_13_SHIFT 13
735#define VTD_BF_CAP_REG_RSVD_15_13_MASK UINT64_C(0x000000000000e000)
736/** MGAW: Maximum Guest Address Width. */
737#define VTD_BF_CAP_REG_MGAW_SHIFT 16
738#define VTD_BF_CAP_REG_MGAW_MASK UINT64_C(0x00000000003f0000)
739/** ZLR: Zero Length Read. */
740#define VTD_BF_CAP_REG_ZLR_SHIFT 22
741#define VTD_BF_CAP_REG_ZLR_MASK UINT64_C(0x0000000000400000)
742/** DEP: Deprecated MBZ. Reserved (bit 23). */
743#define VTD_BF_CAP_REG_RSVD_23_SHIFT 23
744#define VTD_BF_CAP_REG_RSVD_23_MASK UINT64_C(0x0000000000800000)
745/** FRO: Fault-recording Register Offset. */
746#define VTD_BF_CAP_REG_FRO_SHIFT 24
747#define VTD_BF_CAP_REG_FRO_MASK UINT64_C(0x00000003ff000000)
748/** SLLPS: Second Level Large Page Support. */
749#define VTD_BF_CAP_REG_SLLPS_SHIFT 34
750#define VTD_BF_CAP_REG_SLLPS_MASK UINT64_C(0x0000003c00000000)
751/** R: Reserved (bit 38). */
752#define VTD_BF_CAP_REG_RSVD_38_SHIFT 38
753#define VTD_BF_CAP_REG_RSVD_38_MASK UINT64_C(0x0000004000000000)
754/** PSI: Page Selective Invalidation. */
755#define VTD_BF_CAP_REG_PSI_SHIFT 39
756#define VTD_BF_CAP_REG_PSI_MASK UINT64_C(0x0000008000000000)
757/** NFR: Number of Fault-recording Registers. */
758#define VTD_BF_CAP_REG_NFR_SHIFT 40
759#define VTD_BF_CAP_REG_NFR_MASK UINT64_C(0x0000ff0000000000)
760/** MAMV: Maximum Address Mask Value. */
761#define VTD_BF_CAP_REG_MAMV_SHIFT 48
762#define VTD_BF_CAP_REG_MAMV_MASK UINT64_C(0x003f000000000000)
763/** DWD: Write Draining. */
764#define VTD_BF_CAP_REG_DWD_SHIFT 54
765#define VTD_BF_CAP_REG_DWD_MASK UINT64_C(0x0040000000000000)
766/** DRD: Read Draining. */
767#define VTD_BF_CAP_REG_DRD_SHIFT 55
768#define VTD_BF_CAP_REG_DRD_MASK UINT64_C(0x0080000000000000)
769/** FL1GP: First Level 1 GB Page Support. */
770#define VTD_BF_CAP_REG_FL1GP_SHIFT 56
771#define VTD_BF_CAP_REG_FL1GP_MASK UINT64_C(0x0100000000000000)
772/** R: Reserved (bits 58:57). */
773#define VTD_BF_CAP_REG_RSVD_58_57_SHIFT 57
774#define VTD_BF_CAP_REG_RSVD_58_57_MASK UINT64_C(0x0600000000000000)
775/** PI: Posted Interrupt Support. */
776#define VTD_BF_CAP_REG_PI_SHIFT 59
777#define VTD_BF_CAP_REG_PI_MASK UINT64_C(0x0800000000000000)
778/** FL5LP: First Level 5-level Paging Support. */
779#define VTD_BF_CAP_REG_FL5LP_SHIFT 60
780#define VTD_BF_CAP_REG_FL5LP_MASK UINT64_C(0x1000000000000000)
781/** R: Reserved (bits 63:61). */
782#define VTD_BF_CAP_REG_RSVD_63_61_SHIFT 61
783#define VTD_BF_CAP_REG_RSVD_63_61_MASK UINT64_C(0xe000000000000000)
784RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_CAP_REG_, UINT64_C(0), UINT64_MAX,
785 (ND, AFL, RWBF, PLMR, PHMR, CM, SAGAW, RSVD_15_13, MGAW, ZLR, RSVD_23, FRO, SLLPS, RSVD_38, PSI, NFR,
786 MAMV, DWD, DRD, FL1GP, RSVD_58_57, PI, FL5LP, RSVD_63_61));
787
788/** RW: Read/write mask. */
789#define VTD_CAP_REG_RW_MASK UINT64_C(0x0000000000000000)
790/** @} */
791
792
793/** @name Extended Capability Register (ECAP_REG).
794 * @{ */
795/** C: Page-walk Coherence. */
796#define VTD_BF_ECAP_REG_C_SHIFT 0
797#define VTD_BF_ECAP_REG_C_MASK UINT64_C(0x0000000000000001)
798/** QI: Queued Invalidation Support. */
799#define VTD_BF_ECAP_REG_QI_SHIFT 1
800#define VTD_BF_ECAP_REG_QI_MASK UINT64_C(0x0000000000000002)
801/** DT: Device-TLB Support. */
802#define VTD_BF_ECAP_REG_DT_SHIFT 2
803#define VTD_BF_ECAP_REG_DT_MASK UINT64_C(0x0000000000000004)
804/** IR: Interrupt Remapping Support. */
805#define VTD_BF_ECAP_REG_IR_SHIFT 3
806#define VTD_BF_ECAP_REG_IR_MASK UINT64_C(0x0000000000000008)
807/** EIM: Extended Interrupt Mode. */
808#define VTD_BF_ECAP_REG_EIM_SHIFT 4
809#define VTD_BF_ECAP_REG_EIM_MASK UINT64_C(0x0000000000000010)
810/** DEP: Deprecated MBZ. Reserved (bit 5). */
811#define VTD_BF_ECAP_REG_RSVD_5_SHIFT 5
812#define VTD_BF_ECAP_REG_RSVD_5_MASK UINT64_C(0x0000000000000020)
813/** PT: Pass Through. */
814#define VTD_BF_ECAP_REG_PT_SHIFT 6
815#define VTD_BF_ECAP_REG_PT_MASK UINT64_C(0x0000000000000040)
816/** SC: Snoop Control. */
817#define VTD_BF_ECAP_REG_SC_SHIFT 7
818#define VTD_BF_ECAP_REG_SC_MASK UINT64_C(0x0000000000000080)
819/** IRO: IOTLB Register Offset. */
820#define VTD_BF_ECAP_REG_IRO_SHIFT 8
821#define VTD_BF_ECAP_REG_IRO_MASK UINT64_C(0x000000000003ff00)
822/** R: Reserved (bits 19:18). */
823#define VTD_BF_ECAP_REG_RSVD_19_18_SHIFT 18
824#define VTD_BF_ECAP_REG_RSVD_19_18_MASK UINT64_C(0x00000000000c0000)
825/** MHMV: Maximum Handle Mask Value. */
826#define VTD_BF_ECAP_REG_MHMV_SHIFT 20
827#define VTD_BF_ECAP_REG_MHMV_MASK UINT64_C(0x0000000000f00000)
828/** DEP: Deprecated MBZ. Reserved (bit 24). */
829#define VTD_BF_ECAP_REG_RSVD_24_SHIFT 24
830#define VTD_BF_ECAP_REG_RSVD_24_MASK UINT64_C(0x0000000001000000)
831/** MTS: Memory Type Support. */
832#define VTD_BF_ECAP_REG_MTS_SHIFT 25
833#define VTD_BF_ECAP_REG_MTS_MASK UINT64_C(0x0000000002000000)
834/** NEST: Nested Translation Support. */
835#define VTD_BF_ECAP_REG_NEST_SHIFT 26
836#define VTD_BF_ECAP_REG_NEST_MASK UINT64_C(0x0000000004000000)
837/** R: Reserved (bit 27). */
838#define VTD_BF_ECAP_REG_RSVD_27_SHIFT 27
839#define VTD_BF_ECAP_REG_RSVD_27_MASK UINT64_C(0x0000000008000000)
840/** DEP: Deprecated MBZ. Reserved (bit 28). */
841#define VTD_BF_ECAP_REG_RSVD_28_SHIFT 28
842#define VTD_BF_ECAP_REG_RSVD_28_MASK UINT64_C(0x0000000010000000)
843/** PRS: Page Request Support. */
844#define VTD_BF_ECAP_REG_PRS_SHIFT 29
845#define VTD_BF_ECAP_REG_PRS_MASK UINT64_C(0x0000000020000000)
846/** ERS: Execute Request Support. */
847#define VTD_BF_ECAP_REG_ERS_SHIFT 30
848#define VTD_BF_ECAP_REG_ERS_MASK UINT64_C(0x0000000040000000)
849/** SRS: Supervisor Request Support. */
850#define VTD_BF_ECAP_REG_SRS_SHIFT 31
851#define VTD_BF_ECAP_REG_SRS_MASK UINT64_C(0x0000000080000000)
852/** R: Reserved (bit 32). */
853#define VTD_BF_ECAP_REG_RSVD_32_SHIFT 32
854#define VTD_BF_ECAP_REG_RSVD_32_MASK UINT64_C(0x0000000100000000)
855/** NWFS: No Write Flag Support. */
856#define VTD_BF_ECAP_REG_NWFS_SHIFT 33
857#define VTD_BF_ECAP_REG_NWFS_MASK UINT64_C(0x0000000200000000)
858/** EAFS: Extended Accessed Flags Support. */
859#define VTD_BF_ECAP_REG_EAFS_SHIFT 34
860#define VTD_BF_ECAP_REG_EAFS_MASK UINT64_C(0x0000000400000000)
861/** PSS: PASID Size Supported. */
862#define VTD_BF_ECAP_REG_PSS_SHIFT 35
863#define VTD_BF_ECAP_REG_PSS_MASK UINT64_C(0x000000f800000000)
864/** PASID: Process Address Space ID Support. */
865#define VTD_BF_ECAP_REG_PASID_SHIFT 40
866#define VTD_BF_ECAP_REG_PASID_MASK UINT64_C(0x0000010000000000)
867/** DIT: Device-TLB Invalidation Throttle. */
868#define VTD_BF_ECAP_REG_DIT_SHIFT 41
869#define VTD_BF_ECAP_REG_DIT_MASK UINT64_C(0x0000020000000000)
870/** PDS: Page-request Drain Support. */
871#define VTD_BF_ECAP_REG_PDS_SHIFT 42
872#define VTD_BF_ECAP_REG_PDS_MASK UINT64_C(0x0000040000000000)
873/** SMTS: Scalable-Mode Translation Support. */
874#define VTD_BF_ECAP_REG_SMTS_SHIFT 43
875#define VTD_BF_ECAP_REG_SMTS_MASK UINT64_C(0x0000080000000000)
876/** VCS: Virtual Command Support. */
877#define VTD_BF_ECAP_REG_VCS_SHIFT 44
878#define VTD_BF_ECAP_REG_VCS_MASK UINT64_C(0x0000100000000000)
879/** SLADS: Second-Level Accessed/Dirty Support. */
880#define VTD_BF_ECAP_REG_SLADS_SHIFT 45
881#define VTD_BF_ECAP_REG_SLADS_MASK UINT64_C(0x0000200000000000)
882/** SLTS: Second-Level Translation Support. */
883#define VTD_BF_ECAP_REG_SLTS_SHIFT 46
884#define VTD_BF_ECAP_REG_SLTS_MASK UINT64_C(0x0000400000000000)
885/** FLTS: First-Level Translation Support. */
886#define VTD_BF_ECAP_REG_FLTS_SHIFT 47
887#define VTD_BF_ECAP_REG_FLTS_MASK UINT64_C(0x0000800000000000)
888/** SMPWCS: Scalable-Mode Page-Walk Coherency Support. */
889#define VTD_BF_ECAP_REG_SMPWCS_SHIFT 48
890#define VTD_BF_ECAP_REG_SMPWCS_MASK UINT64_C(0x0001000000000000)
891/** RPS: RID-PASID Support. */
892#define VTD_BF_ECAP_REG_RPS_SHIFT 49
893#define VTD_BF_ECAP_REG_RPS_MASK UINT64_C(0x0002000000000000)
894/** R: Reserved (bits 63:50). */
895#define VTD_BF_ECAP_REG_RSVD_63_50_SHIFT 50
896#define VTD_BF_ECAP_REG_RSVD_63_50_MASK UINT64_C(0xfffc000000000000)
897RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_ECAP_REG_, UINT64_C(0), UINT64_MAX,
898 (C, QI, DT, IR, EIM, RSVD_5, PT, SC, IRO, RSVD_19_18, MHMV, RSVD_24, MTS, NEST, RSVD_27, RSVD_28,
899 PRS, ERS, SRS, RSVD_32, NWFS, EAFS, PSS, PASID, DIT, PDS, SMTS, VCS, SLADS, SLTS, FLTS, SMPWCS, RPS,
900 RSVD_63_50));
901
902/** RW: Read/write mask. */
903#define VTD_ECAP_REG_RW_MASK UINT64_C(0x0000000000000000)
904/** @} */
905
906
907/** @name Global Command Register (GCMD_REG).
908 * @{ */
909/** R: Reserved (bits 22:0). */
910#define VTD_BF_GCMD_REG_RSVD_22_0_SHIFT 0
911#define VTD_BF_GCMD_REG_RSVD_22_0_MASK UINT32_C(0x007fffff)
912/** CFI: Compatibility Format Interrupt. */
913#define VTD_BF_GCMD_REG_CFI_SHIFT 23
914#define VTD_BF_GCMD_REG_CFI_MASK UINT32_C(0x00800000)
915/** SIRTP: Set Interrupt Table Remap Pointer. */
916#define VTD_BF_GCMD_REG_SIRTP_SHIFT 24
917#define VTD_BF_GCMD_REG_SIRTP_MASK UINT32_C(0x01000000)
918/** IRE: Interrupt Remap Enable. */
919#define VTD_BF_GCMD_REG_IRE_SHIFT 25
920#define VTD_BF_GCMD_REG_IRE_MASK UINT32_C(0x02000000)
921/** QIE: Queued Invalidation Enable. */
922#define VTD_BF_GCMD_REG_QIE_SHIFT 26
923#define VTD_BF_GCMD_REG_QIE_MASK UINT32_C(0x04000000)
924/** WBF: Write Buffer Flush. */
925#define VTD_BF_GCMD_REG_WBF_SHIFT 27
926#define VTD_BF_GCMD_REG_WBF_MASK UINT32_C(0x08000000)
927/** EAFL: Enable Advance Fault Logging. */
928#define VTD_BF_GCMD_REG_EAFL_SHIFT 28
929#define VTD_BF_GCMD_REG_EAFL_MASK UINT32_C(0x10000000)
930/** SFL: Set Fault Log. */
931#define VTD_BF_GCMD_REG_SFL_SHIFT 29
932#define VTD_BF_GCMD_REG_SFL_MASK UINT32_C(0x20000000)
933/** SRTP: Set Root Table Pointer. */
934#define VTD_BF_GCMD_REG_SRTP_SHIFT 30
935#define VTD_BF_GCMD_REG_SRTP_MASK UINT32_C(0x40000000)
936/** TE: Translation Enable. */
937#define VTD_BF_GCMD_REG_TE_SHIFT 31
938#define VTD_BF_GCMD_REG_TE_MASK UINT32_C(0x80000000)
939RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_GCMD_REG_, UINT32_C(0), UINT32_MAX,
940 (RSVD_22_0, CFI, SIRTP, IRE, QIE, WBF, EAFL, SFL, SRTP, TE));
941
942/** RW: Read/write mask. */
943#define VTD_GCMD_REG_RW_MASK UINT32_C(0xff800000)
944/** @} */
945
946
947/** @name Global Status Register (GSTS_REG).
948 * @{ */
949/** R: Reserved (bits 22:0). */
950#define VTD_BF_GSTS_REG_RSVD_22_0_SHIFT 0
951#define VTD_BF_GSTS_REG_RSVD_22_0_MASK UINT32_C(0x007fffff)
952/** CFIS: Compatibility Format Interrupt Status. */
953#define VTD_BF_GSTS_REG_CFIS_SHIFT 23
954#define VTD_BF_GSTS_REG_CFIS_MASK UINT32_C(0x00800000)
955/** IRTPS: Interrupt Remapping Table Pointer Status. */
956#define VTD_BF_GSTS_REG_IRTPS_SHIFT 24
957#define VTD_BF_GSTS_REG_IRTPS_MASK UINT32_C(0x01000000)
958/** IRES: Interrupt Remapping Enable Status. */
959#define VTD_BF_GSTS_REG_IRES_SHIFT 25
960#define VTD_BF_GSTS_REG_IRES_MASK UINT32_C(0x02000000)
961/** QIES: Queued Invalidation Enable Status. */
962#define VTD_BF_GSTS_REG_QIES_SHIFT 26
963#define VTD_BF_GSTS_REG_QIES_MASK UINT32_C(0x04000000)
964/** WBFS: Write Buffer Flush Status. */
965#define VTD_BF_GSTS_REG_WBFS_SHIFT 27
966#define VTD_BF_GSTS_REG_WBFS_MASK UINT32_C(0x08000000)
967/** AFLS: Advanced Fault Logging Status. */
968#define VTD_BF_GSTS_REG_AFLS_SHIFT 28
969#define VTD_BF_GSTS_REG_AFLS_MASK UINT32_C(0x10000000)
970/** FLS: Fault Log Status. */
971#define VTD_BF_GSTS_REG_FLS_SHIFT 29
972#define VTD_BF_GSTS_REG_FLS_MASK UINT32_C(0x20000000)
973/** RTPS: Root Table Pointer Status. */
974#define VTD_BF_GSTS_REG_RTPS_SHIFT 30
975#define VTD_BF_GSTS_REG_RTPS_MASK UINT32_C(0x40000000)
976/** TES: Translation Enable Status. */
977#define VTD_BF_GSTS_REG_TES_SHIFT 31
978#define VTD_BF_GSTS_REG_TES_MASK UINT32_C(0x80000000)
979RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_GSTS_REG_, UINT32_C(0), UINT32_MAX,
980 (RSVD_22_0, CFIS, IRTPS, IRES, QIES, WBFS, AFLS, FLS, RTPS, TES));
981
982/** RW: Read/write mask. */
983#define VTD_GSTS_REG_RW_MASK UINT32_C(0)
984/** @} */
985
986
987/** @name Root Table Address Register (RTADDR_REG).
988 * @{ */
989/** R: Reserved (bits 9:0). */
990#define VTD_BF_RTADDR_REG_RSVD_9_0_SHIFT 0
991#define VTD_BF_RTADDR_REG_RSVD_9_0_MASK UINT64_C(0x00000000000003ff)
992/** TTM: Translation Table Mode. */
993#define VTD_BF_RTADDR_REG_TTM_SHIFT 10
994#define VTD_BF_RTADDR_REG_TTM_MASK UINT64_C(0x0000000000000c00)
995/** RTA: Root Table Address. */
996#define VTD_BF_RTADDR_REG_RTA_SHIFT 12
997#define VTD_BF_RTADDR_REG_RTA_MASK UINT64_C(0xfffffffffffff000)
998RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_RTADDR_REG_, UINT64_C(0), UINT64_MAX,
999 (RSVD_9_0, TTM, RTA));
1000
1001/** RW: Read/write mask. */
1002#define VTD_RTADDR_REG_RW_MASK UINT64_C(0xfffffffffffffc00)
1003/** @} */
1004
1005
1006/** @name Context Command Register (CCMD_REG).
1007 * @{ */
1008/** DID: Domain-ID. */
1009#define VTD_BF_CCMD_REG_DID_SHIFT 0
1010#define VTD_BF_CCMD_REG_DID_MASK UINT64_C(0x000000000000ffff)
1011/** SID: Source-ID. */
1012#define VTD_BF_CCMD_REG_SID_SHIFT 16
1013#define VTD_BF_CCMD_REG_SID_MASK UINT64_C(0x00000000ffff0000)
1014/** FM: Function Mask. */
1015#define VTD_BF_CCMD_REG_FM_SHIFT 32
1016#define VTD_BF_CCMD_REG_FM_MASK UINT64_C(0x0000000300000000)
1017/** R: Reserved (bits 58:34). */
1018#define VTD_BF_CCMD_REG_RSVD_58_34_SHIFT 34
1019#define VTD_BF_CCMD_REG_RSVD_58_34_MASK UINT64_C(0x07fffffc00000000)
1020/** CAIG: Context Actual Invalidation Granularity. */
1021#define VTD_BF_CCMD_REG_CAIG_SHIFT 59
1022#define VTD_BF_CCMD_REG_CAIG_MASK UINT64_C(0x1800000000000000)
1023/** CIRG: Context Invalidation Request Granularity. */
1024#define VTD_BF_CCMD_REG_CIRG_SHIFT 61
1025#define VTD_BF_CCMD_REG_CIRG_MASK UINT64_C(0x6000000000000000)
1026/** ICC: Invalidation Context Cache. */
1027#define VTD_BF_CCMD_REG_ICC_SHIFT 63
1028#define VTD_BF_CCMD_REG_ICC_MASK UINT64_C(0x8000000000000000)
1029RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_CCMD_REG_, UINT64_C(0), UINT64_MAX,
1030 (DID, SID, FM, RSVD_58_34, CAIG, CIRG, ICC));
1031
1032/** RW: Read/write mask. */
1033#define VTD_CCMD_REG_RW_MASK ( VTD_BF_CCMD_REG_DID_MASK | VTD_BF_CCMD_REG_SID_MASK \
1034 | VTD_BF_CCMD_REG_FM_MASK | VTD_BF_CCMD_REG_CIRG_MASK \
1035 | VTD_BF_CCMD_REG_ICC_MASK)
1036/** @} */
1037
1038
1039/** @name IOTLB Invalidation Register (IOTLB_REG).
1040 * @{ */
1041/** R: Reserved (bits 31:0). */
1042#define VTD_BF_IOTLB_REG_RSVD_31_0_SHIFT 0
1043#define VTD_BF_IOTLB_REG_RSVD_31_0_MASK UINT64_C(0x00000000ffffffff)
1044/** DID: Domain-ID. */
1045#define VTD_BF_IOTLB_REG_DID_SHIFT 32
1046#define VTD_BF_IOTLB_REG_DID_MASK UINT64_C(0x0000ffff00000000)
1047/** DW: Draining Writes. */
1048#define VTD_BF_IOTLB_REG_DW_SHIFT 48
1049#define VTD_BF_IOTLB_REG_DW_MASK UINT64_C(0x0001000000000000)
1050/** DR: Draining Reads. */
1051#define VTD_BF_IOTLB_REG_DR_SHIFT 49
1052#define VTD_BF_IOTLB_REG_DR_MASK UINT64_C(0x0002000000000000)
1053/** R: Reserved (bits 56:50). */
1054#define VTD_BF_IOTLB_REG_RSVD_56_50_SHIFT 50
1055#define VTD_BF_IOTLB_REG_RSVD_56_50_MASK UINT64_C(0x01fc000000000000)
1056/** IAIG: IOTLB Actual Invalidation Granularity. */
1057#define VTD_BF_IOTLB_REG_IAIG_SHIFT 57
1058#define VTD_BF_IOTLB_REG_IAIG_MASK UINT64_C(0x0600000000000000)
1059/** R: Reserved (bit 59). */
1060#define VTD_BF_IOTLB_REG_RSVD_59_SHIFT 59
1061#define VTD_BF_IOTLB_REG_RSVD_59_MASK UINT64_C(0x0800000000000000)
1062/** IIRG: IOTLB Invalidation Request Granularity. */
1063#define VTD_BF_IOTLB_REG_IIRG_SHIFT 60
1064#define VTD_BF_IOTLB_REG_IIRG_MASK UINT64_C(0x3000000000000000)
1065/** R: Reserved (bit 62). */
1066#define VTD_BF_IOTLB_REG_RSVD_62_SHIFT 62
1067#define VTD_BF_IOTLB_REG_RSVD_62_MASK UINT64_C(0x4000000000000000)
1068/** IVT: Invalidate IOTLB. */
1069#define VTD_BF_IOTLB_REG_IVT_SHIFT 63
1070#define VTD_BF_IOTLB_REG_IVT_MASK UINT64_C(0x8000000000000000)
1071RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IOTLB_REG_, UINT64_C(0), UINT64_MAX,
1072 (RSVD_31_0, DID, DW, DR, RSVD_56_50, IAIG, RSVD_59, IIRG, RSVD_62, IVT));
1073/** @} */
1074
1075
1076/** @name Invalidate Address Register (IVA_REG).
1077 * @{ */
1078/** AM: Address Mask. */
1079#define VTD_BF_IVA_REG_AM_SHIFT 0
1080#define VTD_BF_IVA_REG_AM_MASK UINT64_C(0x000000000000003f)
1081/** IH: Invalidation Hint. */
1082#define VTD_BF_IVA_REG_IH_SHIFT 6
1083#define VTD_BF_IVA_REG_IH_MASK UINT64_C(0x0000000000000040)
1084/** R: Reserved (bits 11:7). */
1085#define VTD_BF_IVA_REG_RSVD_11_7_SHIFT 7
1086#define VTD_BF_IVA_REG_RSVD_11_7_MASK UINT64_C(0x0000000000000f80)
1087/** ADDR: Address. */
1088#define VTD_BF_IVA_REG_ADDR_SHIFT 12
1089#define VTD_BF_IVA_REG_ADDR_MASK UINT64_C(0xfffffffffffff000)
1090RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IVA_REG_, UINT64_C(0), UINT64_MAX,
1091 (AM, IH, RSVD_11_7, ADDR));
1092/** @} */
1093
1094
1095/** @name Fault Status Register (FSTS_REG).
1096 * @{ */
1097/** PFO: Primary Fault Overflow. */
1098#define VTD_BF_FSTS_REG_PFO_SHIFT 0
1099#define VTD_BF_FSTS_REG_PFO_MASK UINT32_C(0x00000001)
1100/** PPF: Primary Pending Fault. */
1101#define VTD_BF_FSTS_REG_PPF_SHIFT 1
1102#define VTD_BF_FSTS_REG_PPF_MASK UINT32_C(0x00000002)
1103/** AFO: Advanced Fault Overflow. */
1104#define VTD_BF_FSTS_REG_AFO_SHIFT 2
1105#define VTD_BF_FSTS_REG_AFO_MASK UINT32_C(0x00000004)
1106/** APF: Advanced Pending Fault. */
1107#define VTD_BF_FSTS_REG_APF_SHIFT 3
1108#define VTD_BF_FSTS_REG_APF_MASK UINT32_C(0x00000008)
1109/** IQE: Invalidation Queue Error. */
1110#define VTD_BF_FSTS_REG_IQE_SHIFT 4
1111#define VTD_BF_FSTS_REG_IQE_MASK UINT32_C(0x00000010)
1112/** ICE: Invalidation Completion Error. */
1113#define VTD_BF_FSTS_REG_ICE_SHIFT 5
1114#define VTD_BF_FSTS_REG_ICE_MASK UINT32_C(0x00000020)
1115/** ITE: Invalidation Timeout Error. */
1116#define VTD_BF_FSTS_REG_ITE_SHIFT 6
1117#define VTD_BF_FSTS_REG_ITE_MASK UINT32_C(0x00000040)
1118/** DEP: Deprecated MBZ. Reserved (bit 7). */
1119#define VTD_BF_FSTS_REG_RSVD_7_SHIFT 7
1120#define VTD_BF_FSTS_REG_RSVD_7_MASK UINT32_C(0x00000080)
1121/** FRI: Fault Record Index. */
1122#define VTD_BF_FSTS_REG_FRI_SHIFT 8
1123#define VTD_BF_FSTS_REG_FRI_MASK UINT32_C(0x0000ff00)
1124/** R: Reserved (bits 31:16). */
1125#define VTD_BF_FSTS_REG_RSVD_31_16_SHIFT 16
1126#define VTD_BF_FSTS_REG_RSVD_31_16_MASK UINT32_C(0xffff0000)
1127RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_FSTS_REG_, UINT32_C(0), UINT32_MAX,
1128 (PFO, PPF, AFO, APF, IQE, ICE, ITE, RSVD_7, FRI, RSVD_31_16));
1129
1130/** RW: Read/write mask. */
1131#define VTD_FSTS_REG_RW_MASK ( VTD_BF_FSTS_REG_PFO_MASK | VTD_BF_FSTS_REG_AFO_MASK \
1132 | VTD_BF_FSTS_REG_APF_MASK | VTD_BF_FSTS_REG_IQE_MASK \
1133 | VTD_BF_FSTS_REG_ICE_MASK | VTD_BF_FSTS_REG_ITE_MASK)
1134/** @} */
1135
1136
1137/** @name Fault Event Control Register (FECTL_REG).
1138 * @{ */
1139/** R: Reserved (bits 29:0). */
1140#define VTD_BF_FECTL_REG_RSVD_29_0_SHIFT 0
1141#define VTD_BF_FECTL_REG_RSVD_29_0_MASK UINT32_C(0x3fffffff)
1142/** IP: Interrupt Pending. */
1143#define VTD_BF_FECTL_REG_IP_SHIFT 30
1144#define VTD_BF_FECTL_REG_IP_MASK UINT32_C(0x40000000)
1145/** IM: Interrupt Mask. */
1146#define VTD_BF_FECTL_REG_IM_SHIFT 31
1147#define VTD_BF_FECTL_REG_IM_MASK UINT32_C(0x80000000)
1148RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_FECTL_REG_, UINT32_C(0), UINT32_MAX,
1149 (RSVD_29_0, IP, IM));
1150
1151/** RW: Read/write mask. */
1152#define VTD_FECTL_REG_RW_MASK VTD_BF_FECTL_REG_IM_MASK
1153/** @} */
1154
1155
1156/** @name Fault Event Data Register (FEDATA_REG).
1157 * @{ */
1158/** IMD: Interrupt Message Data. */
1159#define VTD_BF_FEDATA_REG_IMD_SHIFT 0
1160#define VTD_BF_FEDATA_REG_IMD_MASK UINT32_C(0x0000ffff)
1161/** EIMD: Extended Interrupt Message Data. */
1162#define VTD_BF_FEDATA_REG_EIMD_SHIFT 16
1163#define VTD_BF_FEDATA_REG_EIMD_MASK UINT32_C(0xffff0000)
1164RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_FEDATA_REG_, UINT32_C(0), UINT32_MAX,
1165 (IMD, EIMD));
1166
1167/** RW: Read/write mask. */
1168#define VTD_FEDATA_REG_RW_MASK (VTD_BF_FEDATA_REG_IMD_MASK | VTD_BF_FEDATA_REG_EIMD_MASK)
1169/** @} */
1170
1171
1172/** @name Fault Event Address Register (FEADDR_REG).
1173 * @{ */
1174/** R: Reserved (bits 1:0). */
1175#define VTD_BF_FEADDR_REG_RSVD_1_0_SHIFT 0
1176#define VTD_BF_FEADDR_REG_RSVD_1_0_MASK UINT32_C(0x00000003)
1177/** MA: Message Address. */
1178#define VTD_BF_FEADDR_REG_MA_SHIFT 2
1179#define VTD_BF_FEADDR_REG_MA_MASK UINT32_C(0xfffffffc)
1180RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_FEADDR_REG_, UINT32_C(0), UINT32_MAX,
1181 (RSVD_1_0, MA));
1182
1183/** RW: Read/write mask. */
1184#define VTD_FEADDR_REG_RW_MASK VTD_BF_FEADDR_REG_MA_MASK
1185/** @} */
1186
1187
1188/** @name Fault Event Upper Address Register (FEUADDR_REG).
1189 * @{ */
1190/** MUA: Message Upper Address. */
1191#define VTD_BF_FEUADDR_REG_MA_SHIFT 0
1192#define VTD_BF_FEUADDR_REG_MA_MASK UINT32_C(0xffffffff)
1193
1194/** RW: Read/write mask. */
1195#define VTD_FEUADDR_REG_RW_MASK VTD_BF_FEUADDR_REG_MA_MASK
1196/** @} */
1197
1198
1199/** @name Fault Recording Register (FRCD_REG).
1200 * @{ */
1201/** R: Reserved (bits 11:0). */
1202#define VTD_BF_0_FRCD_REG_RSVD_11_0_SHIFT 0
1203#define VTD_BF_0_FRCD_REG_RSVD_11_0_MASK UINT64_C(0x0000000000000fff)
1204/** FI: Fault Info. */
1205#define VTD_BF_0_FRCD_REG_FI_SHIFT 12
1206#define VTD_BF_0_FRCD_REG_FI_MASK UINT64_C(0xfffffffffffff000)
1207RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_FRCD_REG_, UINT64_C(0), UINT64_MAX,
1208 (RSVD_11_0, FI));
1209
1210/** SID: Source Identifier. */
1211#define VTD_BF_1_FRCD_REG_SID_SHIFT 0
1212#define VTD_BF_1_FRCD_REG_SID_MASK UINT64_C(0x000000000000ffff)
1213/** R: Reserved (bits 27:16). */
1214#define VTD_BF_1_FRCD_REG_RSVD_27_16_SHIFT 16
1215#define VTD_BF_1_FRCD_REG_RSVD_27_16_MASK UINT64_C(0x000000000fff0000)
1216/** T2: Type bit 2. */
1217#define VTD_BF_1_FRCD_REG_T2_SHIFT 28
1218#define VTD_BF_1_FRCD_REG_T2_MASK UINT64_C(0x0000000010000000)
1219/** PRIV: Privilege Mode. */
1220#define VTD_BF_1_FRCD_REG_PRIV_SHIFT 29
1221#define VTD_BF_1_FRCD_REG_PRIV_MASK UINT64_C(0x0000000020000000)
1222/** EXE: Execute Permission Requested. */
1223#define VTD_BF_1_FRCD_REG_EXE_SHIFT 30
1224#define VTD_BF_1_FRCD_REG_EXE_MASK UINT64_C(0x0000000040000000)
1225/** PP: PASID Present. */
1226#define VTD_BF_1_FRCD_REG_PP_SHIFT 31
1227#define VTD_BF_1_FRCD_REG_PP_MASK UINT64_C(0x0000000080000000)
1228/** FR: Fault Reason. */
1229#define VTD_BF_1_FRCD_REG_FR_SHIFT 32
1230#define VTD_BF_1_FRCD_REG_FR_MASK UINT64_C(0x000000ff00000000)
1231/** PV: PASID Value. */
1232#define VTD_BF_1_FRCD_REG_PV_SHIFT 40
1233#define VTD_BF_1_FRCD_REG_PV_MASK UINT64_C(0x0fffff0000000000)
1234/** AT: Address Type. */
1235#define VTD_BF_1_FRCD_REG_AT_SHIFT 60
1236#define VTD_BF_1_FRCD_REG_AT_MASK UINT64_C(0x3000000000000000)
1237/** T1: Type bit 1. */
1238#define VTD_BF_1_FRCD_REG_T1_SHIFT 62
1239#define VTD_BF_1_FRCD_REG_T1_MASK UINT64_C(0x4000000000000000)
1240/** F: Fault. */
1241#define VTD_BF_1_FRCD_REG_F_SHIFT 63
1242#define VTD_BF_1_FRCD_REG_F_MASK UINT64_C(0x8000000000000000)
1243RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_FRCD_REG_, UINT64_C(0), UINT64_MAX,
1244 (SID, RSVD_27_16, T2, PRIV, EXE, PP, FR, PV, AT, T1, F));
1245/** @} */
1246
1247
1248/** @name Advanced Fault Log Register (AFLOG_REG).
1249 * @{ */
1250/** R: Reserved (bits 8:0). */
1251#define VTD_BF_0_AFLOG_REG_RSVD_8_0_SHIFT 0
1252#define VTD_BF_0_AFLOG_REG_RSVD_8_0_MASK UINT64_C(0x00000000000001ff)
1253/** FLS: Fault Log Size. */
1254#define VTD_BF_0_AFLOG_REG_FLS_SHIFT 9
1255#define VTD_BF_0_AFLOG_REG_FLS_MASK UINT64_C(0x0000000000000e00)
1256/** FLA: Fault Log Address. */
1257#define VTD_BF_0_AFLOG_REG_FLA_SHIFT 12
1258#define VTD_BF_0_AFLOG_REG_FLA_MASK UINT64_C(0xfffffffffffff000)
1259RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_AFLOG_REG_, UINT64_C(0), UINT64_MAX,
1260 (RSVD_8_0, FLS, FLA));
1261
1262/** RW: Read/write mask. */
1263#define VTD_AFLOG_REG_RW_MASK (VTD_BF_0_AFLOG_REG_FLS_MASK | VTD_BF_0_AFLOG_REG_FLA_MASK)
1264/** @} */
1265
1266
1267/** @name Protected Memory Enable Register (PMEN_REG).
1268 * @{ */
1269/** PRS: Protected Region Status. */
1270#define VTD_BF_PMEN_REG_PRS_SHIFT 0
1271#define VTD_BF_PMEN_REG_PRS_MASK UINT32_C(0x00000001)
1272/** R: Reserved (bits 30:1). */
1273#define VTD_BF_PMEN_REG_RSVD_30_1_SHIFT 1
1274#define VTD_BF_PMEN_REG_RSVD_30_1_MASK UINT32_C(0x7ffffffe)
1275/** EPM: Enable Protected Memory. */
1276#define VTD_BF_PMEN_REG_EPM_SHIFT 31
1277#define VTD_BF_PMEN_REG_EPM_MASK UINT32_C(0x80000000)
1278RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_PMEN_REG_, UINT32_C(0), UINT32_MAX,
1279 (PRS, RSVD_30_1, EPM));
1280
1281/** RW: Read/write mask. */
1282#define VTD_PMEN_REG_RW_MASK VTD_BF_PMEN_REG_EPM_MASK
1283/** @} */
1284
1285
1286/** @name Invalidation Queue Head Register (IQH_REG).
1287 * @{ */
1288/** R: Reserved (bits 3:0). */
1289#define VTD_BF_IQH_REG_RSVD_3_0_SHIFT 0
1290#define VTD_BF_IQH_REG_RSVD_3_0_MASK UINT64_C(0x000000000000000f)
1291/** QH: Queue Head. */
1292#define VTD_BF_IQH_REG_QH_SHIFT 4
1293#define VTD_BF_IQH_REG_QH_MASK UINT64_C(0x000000000007fff0)
1294/** R: Reserved (bits 63:19). */
1295#define VTD_BF_IQH_REG_RSVD_63_19_SHIFT 19
1296#define VTD_BF_IQH_REG_RSVD_63_19_MASK UINT64_C(0xfffffffffff80000)
1297RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IQH_REG_, UINT64_C(0), UINT64_MAX,
1298 (RSVD_3_0, QH, RSVD_63_19));
1299
1300/** RW: Read/write mask. */
1301#define VTD_IQH_REG_RW_MASK UINT64_C(0x0)
1302/** @} */
1303
1304
1305/** @name Invalidation Queue Tail Register (IQT_REG).
1306 * @{ */
1307/** R: Reserved (bits 3:0). */
1308#define VTD_BF_IQT_REG_RSVD_3_0_SHIFT 0
1309#define VTD_BF_IQT_REG_RSVD_3_0_MASK UINT64_C(0x000000000000000f)
1310/** QH: Queue Tail. */
1311#define VTD_BF_IQT_REG_QT_SHIFT 4
1312#define VTD_BF_IQT_REG_QT_MASK UINT64_C(0x000000000007fff0)
1313/** R: Reserved (bits 63:19). */
1314#define VTD_BF_IQT_REG_RSVD_63_19_SHIFT 19
1315#define VTD_BF_IQT_REG_RSVD_63_19_MASK UINT64_C(0xfffffffffff80000)
1316RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IQT_REG_, UINT64_C(0), UINT64_MAX,
1317 (RSVD_3_0, QT, RSVD_63_19));
1318
1319/** RW: Read/write mask. */
1320#define VTD_IQT_REG_RW_MASK VTD_BF_IQT_REG_QT_MASK
1321/** @} */
1322
1323
1324/** @name Invalidation Queue Address Register (IQA_REG).
1325 * @{ */
1326/** QS: Queue Size. */
1327#define VTD_BF_IQA_REG_QS_SHIFT 0
1328#define VTD_BF_IQA_REG_QS_MASK UINT64_C(0x0000000000000007)
1329/** R: Reserved (bits 10:3). */
1330#define VTD_BF_IQA_REG_RSVD_10_3_SHIFT 3
1331#define VTD_BF_IQA_REG_RSVD_10_3_MASK UINT64_C(0x00000000000007f8)
1332/** DW: Descriptor Width. */
1333#define VTD_BF_IQA_REG_DW_SHIFT 11
1334#define VTD_BF_IQA_REG_DW_MASK UINT64_C(0x0000000000000800)
1335/** IQA: Invalidation Queue Base Address. */
1336#define VTD_BF_IQA_REG_IQA_SHIFT 12
1337#define VTD_BF_IQA_REG_IQA_MASK UINT64_C(0xfffffffffffff000)
1338RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IQA_REG_, UINT64_C(0), UINT64_MAX,
1339 (QS, RSVD_10_3, DW, IQA));
1340
1341/** RW: Read/write mask. */
1342#define VTD_IQA_REG_RW_MASK ( VTD_BF_IQA_REG_QS_MASK | VTD_BF_IQA_REG_DW_MASK \
1343 | VTD_BF_IQA_REG_IQA_MASK)
1344/** @} */
1345
1346
1347/** @name Invalidation Completion Status Register (ICS_REG).
1348 * @{ */
1349/** IWC: Invalidation Wait Descriptor Complete. */
1350#define VTD_BF_ICS_REG_IWC_SHIFT 0
1351#define VTD_BF_ICS_REG_IWC_MASK UINT32_C(0x00000001)
1352/** R: Reserved (bits 31:1). */
1353#define VTD_BF_ICS_REG_RSVD_31_1_SHIFT 1
1354#define VTD_BF_ICS_REG_RSVD_31_1_MASK UINT32_C(0xfffffffe)
1355RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_ICS_REG_, UINT32_C(0), UINT32_MAX,
1356 (IWC, RSVD_31_1));
1357
1358/** RW: Read/write mask. */
1359#define VTD_ICS_REG_RW_MASK VTD_BF_ICS_REG_IWC_MASK
1360/** @} */
1361
1362
1363/** @name Invalidation Event Control Register (IECTL_REG).
1364 * @{ */
1365/** R: Reserved (bits 29:0). */
1366#define VTD_BF_IECTL_REG_RSVD_29_0_SHIFT 0
1367#define VTD_BF_IECTL_REG_RSVD_29_0_MASK UINT32_C(0x3fffffff)
1368/** IP: Interrupt Pending. */
1369#define VTD_BF_IECTL_REG_IP_SHIFT 30
1370#define VTD_BF_IECTL_REG_IP_MASK UINT32_C(0x40000000)
1371/** IM: Interrupt Mask. */
1372#define VTD_BF_IECTL_REG_IM_SHIFT 31
1373#define VTD_BF_IECTL_REG_IM_MASK UINT32_C(0x80000000)
1374RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IECTL_REG_, UINT32_C(0), UINT32_MAX,
1375 (RSVD_29_0, IP, IM));
1376
1377/** RW: Read/write mask. */
1378#define VTD_IECTL_REG_RW_MASK VTD_BF_IECTL_REG_IM_MASK
1379/** @} */
1380
1381
1382/** @name Invalidation Event Data Register (IEDATA_REG).
1383 * @{ */
1384/** IMD: Interrupt Message Data. */
1385#define VTD_BF_IEDATA_REG_IMD_SHIFT 0
1386#define VTD_BF_IEDATA_REG_IMD_MASK UINT32_C(0x0000ffff)
1387/** EIMD: Extended Interrupt Message Data. */
1388#define VTD_BF_IEDATA_REG_EIMD_SHIFT 16
1389#define VTD_BF_IEDATA_REG_EIMD_MASK UINT32_C(0xffff0000)
1390RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IEDATA_REG_, UINT32_C(0), UINT32_MAX,
1391 (IMD, EIMD));
1392
1393/** RW: Read/write mask. */
1394#define VTD_IEDATA_REG_RW_MASK (VTD_BF_IEDATA_REG_IMD_MASK | VTD_BF_IEDATA_REG_EIMD_MASK)
1395/** @} */
1396
1397
1398/** @name Invalidation Event Address Register (IEADDR_REG).
1399 * @{ */
1400/** R: Reserved (bits 1:0). */
1401#define VTD_BF_IEADDR_REG_RSVD_1_0_SHIFT 0
1402#define VTD_BF_IEADDR_REG_RSVD_1_0_MASK UINT32_C(0x00000003)
1403/** MA: Message Address. */
1404#define VTD_BF_IEADDR_REG_MA_SHIFT 2
1405#define VTD_BF_IEADDR_REG_MA_MASK UINT32_C(0xfffffffc)
1406RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IEADDR_REG_, UINT32_C(0), UINT32_MAX,
1407 (RSVD_1_0, MA));
1408
1409/** RW: Read/write mask. */
1410#define VTD_IEADDR_REG_RW_MASK VTD_BF_IEADDR_REG_MA_MASK
1411/** @} */
1412
1413
1414/** @name Invalidation Event Upper Address Register (IEUADDR_REG).
1415 * @{ */
1416/** MUA: Message Upper Address. */
1417#define VTD_BF_IEUADDR_REG_MUA_SHIFT 0
1418#define VTD_BF_IEUADDR_REG_MUA_MASK UINT32_C(0xffffffff)
1419
1420/** RW: Read/write mask. */
1421#define VTD_IEUADDR_REG_RW_MASK VTD_BF_IEUADDR_REG_MUA_MASK
1422/** @} */
1423
1424
1425/** @name Invalidation Queue Error Record Register (IQERCD_REG).
1426 * @{ */
1427/** IQEI: Invalidation Queue Error Info. */
1428#define VTD_BF_IQERCD_REG_IQEI_SHIFT 0
1429#define VTD_BF_IQERCD_REG_IQEI_MASK UINT64_C(0x000000000000000f)
1430/** R: Reserved (bits 31:4). */
1431#define VTD_BF_IQERCD_REG_RSVD_31_4_SHIFT 4
1432#define VTD_BF_IQERCD_REG_RSVD_31_4_MASK UINT64_C(0x00000000fffffff0)
1433/** ITESID: Invalidation Timeout Error Source Identifier. */
1434#define VTD_BF_IQERCD_REG_ITESID_SHIFT 32
1435#define VTD_BF_IQERCD_REG_ITESID_MASK UINT64_C(0x0000ffff00000000)
1436/** ICESID: Invalidation Completion Error Source Identifier. */
1437#define VTD_BF_IQERCD_REG_ICESID_SHIFT 48
1438#define VTD_BF_IQERCD_REG_ICESID_MASK UINT64_C(0xffff000000000000)
1439RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IQERCD_REG_, UINT64_C(0), UINT64_MAX,
1440 (IQEI, RSVD_31_4, ITESID, ICESID));
1441
1442/** RW: Read/write mask. */
1443#define VTD_IQERCD_REG_RW_MASK UINT64_C(0)
1444/** @} */
1445
1446
1447/** @name Interrupt Remapping Table Address Register (IRTA_REG).
1448 * @{ */
1449/** S: Size. */
1450#define VTD_BF_IRTA_REG_S_SHIFT 0
1451#define VTD_BF_IRTA_REG_S_MASK UINT64_C(0x000000000000000f)
1452/** R: Reserved (bits 10:4). */
1453#define VTD_BF_IRTA_REG_RSVD_10_4_SHIFT 4
1454#define VTD_BF_IRTA_REG_RSVD_10_4_MASK UINT64_C(0x00000000000007f0)
1455/** EIME: Extended Interrupt Mode Enable. */
1456#define VTD_BF_IRTA_REG_EIME_SHIFT 11
1457#define VTD_BF_IRTA_REG_EIME_MASK UINT64_C(0x0000000000000800)
1458/** IRTA: Interrupt Remapping Table Address. */
1459#define VTD_BF_IRTA_REG_IRTA_SHIFT 12
1460#define VTD_BF_IRTA_REG_IRTA_MASK UINT64_C(0xfffffffffffff000)
1461RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IRTA_REG_, UINT64_C(0), UINT64_MAX,
1462 (S, RSVD_10_4, EIME, IRTA));
1463
1464/** RW: Read/write mask. */
1465#define VTD_IRTA_REG_RW_MASK ( VTD_BF_IRTA_REG_S_MASK | VTD_BF_IRTA_REG_EIME_MASK \
1466 | VTD_BF_IRTA_REG_IRTA_MASK)
1467/** @} */
1468
1469
1470/** @name Page Request Queue Head Register (PQH_REG).
1471 * @{ */
1472/** R: Reserved (bits 4:0). */
1473#define VTD_BF_PQH_REG_RSVD_4_0_SHIFT 0
1474#define VTD_BF_PQH_REG_RSVD_4_0_MASK UINT64_C(0x000000000000001f)
1475/** PQH: Page Queue Head. */
1476#define VTD_BF_PQH_REG_PQH_SHIFT 5
1477#define VTD_BF_PQH_REG_PQH_MASK UINT64_C(0x000000000007ffe0)
1478/** R: Reserved (bits 63:19). */
1479#define VTD_BF_PQH_REG_RSVD_63_19_SHIFT 19
1480#define VTD_BF_PQH_REG_RSVD_63_19_MASK UINT64_C(0xfffffffffff80000)
1481RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_PQH_REG_, UINT64_C(0), UINT64_MAX,
1482 (RSVD_4_0, PQH, RSVD_63_19));
1483
1484/** RW: Read/write mask. */
1485#define VTD_PQH_REG_RW_MASK VTD_BF_PQH_REG_PQH_MASK
1486/** @} */
1487
1488
1489/** @name Page Request Queue Tail Register (PQT_REG).
1490 * @{ */
1491/** R: Reserved (bits 4:0). */
1492#define VTD_BF_PQT_REG_RSVD_4_0_SHIFT 0
1493#define VTD_BF_PQT_REG_RSVD_4_0_MASK UINT64_C(0x000000000000001f)
1494/** PQT: Page Queue Tail. */
1495#define VTD_BF_PQT_REG_PQT_SHIFT 5
1496#define VTD_BF_PQT_REG_PQT_MASK UINT64_C(0x000000000007ffe0)
1497/** R: Reserved (bits 63:19). */
1498#define VTD_BF_PQT_REG_RSVD_63_19_SHIFT 19
1499#define VTD_BF_PQT_REG_RSVD_63_19_MASK UINT64_C(0xfffffffffff80000)
1500RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_PQT_REG_, UINT64_C(0), UINT64_MAX,
1501 (RSVD_4_0, PQT, RSVD_63_19));
1502
1503/** RW: Read/write mask. */
1504#define VTD_PQT_REG_RW_MASK VTD_BF_PQT_REG_PQT_MASK
1505/** @} */
1506
1507
1508/** @name Page Request Queue Address Register (PQA_REG).
1509 * @{ */
1510/** PQS: Page Queue Size. */
1511#define VTD_BF_PQA_REG_PQS_SHIFT 0
1512#define VTD_BF_PQA_REG_PQS_MASK UINT64_C(0x0000000000000007)
1513/** R: Reserved bits (11:3). */
1514#define VTD_BF_PQA_REG_RSVD_11_3_SHIFT 3
1515#define VTD_BF_PQA_REG_RSVD_11_3_MASK UINT64_C(0x0000000000000ff8)
1516/** PQA: Page Request Queue Base Address. */
1517#define VTD_BF_PQA_REG_PQA_SHIFT 12
1518#define VTD_BF_PQA_REG_PQA_MASK UINT64_C(0xfffffffffffff000)
1519RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_PQA_REG_, UINT64_C(0), UINT64_MAX,
1520 (PQS, RSVD_11_3, PQA));
1521
1522/** RW: Read/write mask. */
1523#define VTD_PQA_REG_RW_MASK (VTD_BF_PQA_REG_PQS_MASK | VTD_BF_PQA_REG_PQA_MASK)
1524/** @} */
1525
1526
1527/** @name Page Request Status Register (PRS_REG).
1528 * @{ */
1529/** PPR: Pending Page Request. */
1530#define VTD_BF_PRS_REG_PPR_SHIFT 0
1531#define VTD_BF_PRS_REG_PPR_MASK UINT64_C(0x00000001)
1532/** PRO: Page Request Overflow. */
1533#define VTD_BF_PRS_REG_PRO_SHIFT 1
1534#define VTD_BF_PRS_REG_PRO_MASK UINT64_C(0x00000002)
1535/** R: Reserved (bits 31:2). */
1536#define VTD_BF_PRS_REG_RSVD_31_2_SHIFT 2
1537#define VTD_BF_PRS_REG_RSVD_31_2_MASK UINT64_C(0xfffffffc)
1538RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_PRS_REG_, UINT32_C(0), UINT32_MAX,
1539 (PPR, PRO, RSVD_31_2));
1540
1541/** RW: Read/write mask. */
1542#define VTD_PRS_REG_RW_MASK (VTD_BF_PRS_REG_PPR_MASK | VTD_BF_PRS_REG_PRO_MASK)
1543/** @} */
1544
1545
1546/** @name Page Request Event Control Register (PECTL_REG).
1547 * @{ */
1548/** R: Reserved (bits 29:0). */
1549#define VTD_BF_PECTL_REG_RSVD_29_0_SHIFT 0
1550#define VTD_BF_PECTL_REG_RSVD_29_0_MASK UINT32_C(0x3fffffff)
1551/** IP: Interrupt Pending. */
1552#define VTD_BF_PECTL_REG_IP_SHIFT 30
1553#define VTD_BF_PECTL_REG_IP_MASK UINT32_C(0x40000000)
1554/** IM: Interrupt Mask. */
1555#define VTD_BF_PECTL_REG_IM_SHIFT 31
1556#define VTD_BF_PECTL_REG_IM_MASK UINT32_C(0x80000000)
1557RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_PECTL_REG_, UINT32_C(0), UINT32_MAX,
1558 (RSVD_29_0, IP, IM));
1559
1560/** RW: Read/write mask. */
1561#define VTD_PECTL_REG_RW_MASK VTD_BF_PECTL_REG_IM_MASK
1562/** @} */
1563
1564
1565/** @name Page Request Event Data Register (PEDATA_REG).
1566 * @{ */
1567/** IMD: Interrupt Message Data. */
1568#define VTD_BF_PEDATA_REG_IMD_SHIFT 0
1569#define VTD_BF_PEDATA_REG_IMD_MASK UINT32_C(0x0000ffff)
1570/** EIMD: Extended Interrupt Message Data. */
1571#define VTD_BF_PEDATA_REG_EIMD_SHIFT 16
1572#define VTD_BF_PEDATA_REG_EIMD_MASK UINT32_C(0xffff0000)
1573RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_PEDATA_REG_, UINT32_C(0), UINT32_MAX,
1574 (IMD, EIMD));
1575
1576/** RW: Read/write mask. */
1577#define VTD_PEDATA_REG_RW_MASK (VTD_BF_PEDATA_REG_IMD_MASK | VTD_BF_PEDATA_REG_EIMD_MASK)
1578/** @} */
1579
1580
1581/** @name Page Request Event Address Register (PEADDR_REG).
1582 * @{ */
1583/** R: Reserved (bits 1:0). */
1584#define VTD_BF_PEADDR_REG_RSVD_1_0_SHIFT 0
1585#define VTD_BF_PEADDR_REG_RSVD_1_0_MASK UINT32_C(0x00000003)
1586/** MA: Message Address. */
1587#define VTD_BF_PEADDR_REG_MA_SHIFT 2
1588#define VTD_BF_PEADDR_REG_MA_MASK UINT32_C(0xfffffffc)
1589RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_PEADDR_REG_, UINT32_C(0), UINT32_MAX,
1590 (RSVD_1_0, MA));
1591
1592/** RW: Read/write mask. */
1593#define VTD_PEADDR_REG_RW_MASK VTD_BF_PEADDR_REG_MA_MASK
1594/** @} */
1595
1596
1597
1598/** @name Page Request Event Upper Address Register (PEUADDR_REG).
1599 * @{ */
1600/** MA: Message Address. */
1601#define VTD_BF_PEUADDR_REG_MUA_SHIFT 0
1602#define VTD_BF_PEUADDR_REG_MUA_MASK UINT32_C(0xffffffff)
1603
1604/** RW: Read/write mask. */
1605#define VTD_PEUADDR_REG_RW_MASK VTD_BF_PEUADDR_REG_MUA_MASK
1606/** @} */
1607
1608
1609/** @name MTRR Capability Register (MTRRCAP_REG).
1610 * @{ */
1611/** VCNT: Variable MTRR Count. */
1612#define VTD_BF_MTRRCAP_REG_VCNT_SHIFT 0
1613#define VTD_BF_MTRRCAP_REG_VCNT_MASK UINT64_C(0x00000000000000ff)
1614/** FIX: Fixed range MTRRs Supported. */
1615#define VTD_BF_MTRRCAP_REG_FIX_SHIFT 8
1616#define VTD_BF_MTRRCAP_REG_FIX_MASK UINT64_C(0x0000000000000100)
1617/** R: Reserved (bit 9). */
1618#define VTD_BF_MTRRCAP_REG_RSVD_9_SHIFT 9
1619#define VTD_BF_MTRRCAP_REG_RSVD_9_MASK UINT64_C(0x0000000000000200)
1620/** WC: Write Combining. */
1621#define VTD_BF_MTRRCAP_REG_WC_SHIFT 10
1622#define VTD_BF_MTRRCAP_REG_WC_MASK UINT64_C(0x0000000000000400)
1623/** R: Reserved (bits 63:11). */
1624#define VTD_BF_MTRRCAP_REG_RSVD_63_11_SHIFT 11
1625#define VTD_BF_MTRRCAP_REG_RSVD_63_11_MASK UINT64_C(0xfffffffffffff800)
1626RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_MTRRCAP_REG_, UINT64_C(0), UINT64_MAX,
1627 (VCNT, FIX, RSVD_9, WC, RSVD_63_11));
1628
1629/** RW: Read/write mask. */
1630#define VTD_MTRRCAP_REG_RW_MASK UINT64_C(0)
1631/** @} */
1632
1633
1634/** @name MTRR Default Type Register (MTRRDEF_REG).
1635 * @{ */
1636/** TYPE: Default Memory Type. */
1637#define VTD_BF_MTRRDEF_REG_TYPE_SHIFT 0
1638#define VTD_BF_MTRRDEF_REG_TYPE_MASK UINT64_C(0x00000000000000ff)
1639/** R: Reserved (bits 9:8). */
1640#define VTD_BF_MTRRDEF_REG_RSVD_9_8_SHIFT 8
1641#define VTD_BF_MTRRDEF_REG_RSVD_9_8_MASK UINT64_C(0x0000000000000300)
1642/** FE: Fixed Range MTRR Enable. */
1643#define VTD_BF_MTRRDEF_REG_FE_SHIFT 10
1644#define VTD_BF_MTRRDEF_REG_FE_MASK UINT64_C(0x0000000000000400)
1645/** E: MTRR Enable. */
1646#define VTD_BF_MTRRDEF_REG_E_SHIFT 11
1647#define VTD_BF_MTRRDEF_REG_E_MASK UINT64_C(0x0000000000000800)
1648/** R: Reserved (bits 63:12). */
1649#define VTD_BF_MTRRDEF_REG_RSVD_63_12_SHIFT 12
1650#define VTD_BF_MTRRDEF_REG_RSVD_63_12_MASK UINT64_C(0xfffffffffffff000)
1651RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_MTRRDEF_REG_, UINT64_C(0), UINT64_MAX,
1652 (TYPE, RSVD_9_8, FE, E, RSVD_63_12));
1653
1654/** RW: Read/write mask. */
1655#define VTD_MTRRDEF_REG_RW_MASK ( VTD_BF_MTRRDEF_REG_TYPE_MASK | VTD_BF_MTRRDEF_REG_FE_MASK \
1656 | VTD_BF_MTRRDEF_REG_E_MASK)
1657/** @} */
1658
1659
1660/** @name Virtual Command Capability Register (VCCAP_REG).
1661 * @{ */
1662/** PAS: PASID Support. */
1663#define VTD_BF_VCCAP_REG_PAS_SHIFT 0
1664#define VTD_BF_VCCAP_REG_PAS_MASK UINT64_C(0x0000000000000001)
1665/** R: Reserved (bits 63:1). */
1666#define VTD_BF_VCCAP_REG_RSVD_63_1_SHIFT 1
1667#define VTD_BF_VCCAP_REG_RSVD_63_1_MASK UINT64_C(0xfffffffffffffffe)
1668RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_VCCAP_REG_, UINT64_C(0), UINT64_MAX,
1669 (PAS, RSVD_63_1));
1670
1671/** RW: Read/write mask. */
1672#define VTD_VCCAP_REG_RW_MASK UINT64_C(0)
1673/** @} */
1674
1675
1676/** @name Virtual Command Register (VCMD_REG).
1677 * @{ */
1678/** CMD: Command. */
1679#define VTD_BF_VCMD_REG_CMD_SHIFT 0
1680#define VTD_BF_VCMD_REG_CMD_MASK UINT64_C(0x00000000000000ff)
1681/** OP: Operand. */
1682#define VTD_BF_VCMD_REG_OP_SHIFT 8
1683#define VTD_BF_VCMD_REG_OP_MASK UINT64_C(0xffffffffffffff00)
1684RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_VCMD_REG_, UINT64_C(0), UINT64_MAX,
1685 (CMD, OP));
1686
1687/** RW: Read/write mask. */
1688#define VTD_VCMD_REG_RW_MASK (VTD_BF_VCMD_REG_CMD_MASK | VTD_BF_VCMD_REG_OP_MASK)
1689/** @} */
1690
1691
1692/** @name Virtual Command Response Register (VCRSP_REG).
1693 * @{ */
1694/** IP: In Progress. */
1695#define VTD_BF_VCRSP_REG_IP_SHIFT 0
1696#define VTD_BF_VCRSP_REG_IP_MASK UINT64_C(0x0000000000000001)
1697/** SC: Status Code. */
1698#define VTD_BF_VCRSP_REG_SC_SHIFT 1
1699#define VTD_BF_VCRSP_REG_SC_MASK UINT64_C(0x0000000000000006)
1700/** R: Reserved (bits 7:3). */
1701#define VTD_BF_VCRSP_REG_RSVD_7_3_SHIFT 3
1702#define VTD_BF_VCRSP_REG_RSVD_7_3_MASK UINT64_C(0x00000000000000f8)
1703/** RSLT: Result. */
1704#define VTD_BF_VCRSP_REG_RSLT_SHIFT 8
1705#define VTD_BF_VCRSP_REG_RSLT_MASK UINT64_C(0xffffffffffffff00)
1706RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_VCRSP_REG_, UINT64_C(0), UINT64_MAX,
1707 (IP, SC, RSVD_7_3, RSLT));
1708
1709/** RW: Read/write mask. */
1710#define VTD_VCRSP_REG_RW_MASK UINT64_C(0)
1711/** @} */
1712
1713
1714#endif /* !VBOX_INCLUDED_iommu_intel_h */
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