VirtualBox

source: vbox/trunk/include/VBox/iommu-intel.h@ 88202

Last change on this file since 88202 was 88202, checked in by vboxsync, 4 years ago

Intel IOMMU: bugref:9967 WIP, build fix.
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File size: 90.9 KB
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1/** @file
2 * IOMMU - Input/Output Memory Management Unit (Intel).
3 */
4
5/*
6 * Copyright (C) 2021 Oracle Corporation
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * The contents of this file may alternatively be used under the terms
17 * of the Common Development and Distribution License Version 1.0
18 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19 * VirtualBox OSE distribution, in which case the provisions of the
20 * CDDL are applicable instead of those of the GPL.
21 *
22 * You may elect to license modified versions of this file under the
23 * terms and conditions of either the GPL or the CDDL or both.
24 */
25
26#ifndef VBOX_INCLUDED_iommu_intel_h
27#define VBOX_INCLUDED_iommu_intel_h
28#ifndef RT_WITHOUT_PRAGMA_ONCE
29# pragma once
30#endif
31
32#include <iprt/assertcompile.h>
33#include <iprt/types.h>
34
35
36/**
37 * @name MMIO register offsets.
38 * In accordance with the AMD spec.
39 * @{
40 */
41#define VTD_MMIO_GROUP_0_OFF_FIRST 0x000
42#define VTD_MMIO_OFF_VER_REG VTD_MMIO_GROUP_0_OFF_FIRST /**< Version. */
43#define VTD_MMIO_OFF_CAP_REG 0x008 /**< Capability. */
44#define VTD_MMIO_OFF_ECAP_REG 0x010 /**< Extended Capability. */
45#define VTD_MMIO_OFF_GCMD_REG 0x018 /**< Global Command. */
46#define VTD_MMIO_OFF_GSTS_REG 0x01c /**< Global Status. */
47#define VTD_MMIO_OFF_RTADDR_REG 0x020 /**< Root Table Address. */
48#define VTD_MMIO_OFF_CCMD_REG 0x028 /**< Context Command. */
49
50#define VTD_MMIO_OFF_FSTS_REG 0x034 /**< Fault Status.*/
51#define VTD_MMIO_OFF_FECTL_REG 0x038 /**< Fault Event Control.*/
52#define VTD_MMIO_OFF_FEDATA_REG 0x03c /**< Fault Event Data. */
53#define VTD_MMIO_OFF_FEADDR_REG 0x040 /**< Fault Event Address. */
54#define VTD_MMIO_OFF_FEUADDR_REG 0x044 /**< Fault Event Upper Address. */
55
56#define VTD_MMIO_OFF_AFLOG_REG 0x058 /**< Advance Fault Log. */
57
58#define VTD_MMIO_OFF_PMEN_REG 0x064 /**< Protected Memory Enable (PMEN). */
59#define VTD_MMIO_OFF_PLMBASE_REG 0x068 /**< Protected Low Memory Base. */
60#define VTD_MMIO_OFF_PLMLIMIT_REG 0x06c /**< Protected Low Memory Limit. */
61#define VTD_MMIO_OFF_PHMBASE_REG 0x070 /**< Protected High Memory Base. */
62#define VTD_MMIO_OFF_PHMLIMIT_REG 0x078 /**< Protected High Memory Limit. */
63
64#define VTD_MMIO_OFF_IQH_REG 0x080 /**< Invalidation Queue Head. */
65#define VTD_MMIO_OFF_IQT_REG 0x088 /**< Invalidation Queue Tail. */
66#define VTD_MMIO_OFF_IQA_REG 0x090 /**< Invalidation Queue Address. */
67#define VTD_MMIO_OFF_ICS_REG 0x09c /**< Invalidation Completion Status. */
68#define VTD_MMIO_OFF_IECTL_REG 0x0a0 /**< Invalidation Completion Event Control. */
69#define VTD_MMIO_OFF_IEDATA_REG 0x0a4 /**< Invalidation Completion Event Data. */
70#define VTD_MMIO_OFF_IEADDR_REG 0x0a8 /**< Invalidation Completion Event Address. */
71#define VTD_MMIO_OFF_IEUADDR_REG 0x0ac /**< Invalidation Completion Event Upper Address. */
72#define VTD_MMIO_OFF_IQERCD_REG 0x0b0 /**< Invalidation Queue Error Record. */
73
74#define VTD_MMIO_OFF_IRTA_REG 0x0b8 /**< Interrupt Remapping Table Address. */
75
76#define VTD_MMIO_OFF_PQH_REG 0x0c0 /**< Page Request Queue Head. */
77#define VTD_MMIO_OFF_PQT_REG 0x0c8 /**< Page Request Queue Tail. */
78#define VTD_MMIO_OFF_PQA_REG 0x0d0 /**< Page Request Queue Address. */
79#define VTD_MMIO_OFF_PRS_REG 0x0dc /**< Page Request Status. */
80#define VTD_MMIO_OFF_PECTL_REG 0x0e0 /**< Page Request Event Control. */
81#define VTD_MMIO_OFF_PEDATA_REG 0x0e4 /**< Page Request Event Data. */
82#define VTD_MMIO_OFF_PEADDR_REG 0x0e8 /**< Page Request Event Address. */
83#define VTD_MMIO_OFF_PEUADDR_REG 0x0ec /**< Page Request Event Upper Address. */
84
85#define VTD_MMIO_OFF_MTRRCAP_REG 0x100 /**< MTRR Capabliity. */
86#define VTD_MMIO_OFF_MTRRDEF_REG 0x108 /**< MTRR Default Type. */
87
88#define VTD_MMIO_OFF_MTRR_FIX64_00000_REG 0x120 /**< Fixed-range MTRR Register for 64K at 00000. */
89#define VTD_MMIO_OFF_MTRR_FIX16K_80000_REG 0x128 /**< Fixed-range MTRR Register for 16K at 80000. */
90#define VTD_MMIO_OFF_MTRR_FIX16K_A0000_REG 0x130 /**< Fixed-range MTRR Register for 16K at a0000. */
91#define VTD_MMIO_OFF_MTRR_FIX4K_C0000_REG 0x138 /**< Fixed-range MTRR Register for 4K at c0000. */
92#define VTD_MMIO_OFF_MTRR_FIX4K_C8000_REG 0x140 /**< Fixed-range MTRR Register for 4K at c8000. */
93#define VTD_MMIO_OFF_MTRR_FIX4K_D0000_REG 0x148 /**< Fixed-range MTRR Register for 4K at d0000. */
94#define VTD_MMIO_OFF_MTRR_FIX4K_D8000_REG 0x150 /**< Fixed-range MTRR Register for 4K at d8000. */
95#define VTD_MMIO_OFF_MTRR_FIX4K_E0000_REG 0x158 /**< Fixed-range MTRR Register for 4K at e0000. */
96#define VTD_MMIO_OFF_MTRR_FIX4K_E8000_REG 0x160 /**< Fixed-range MTRR Register for 4K at e8000. */
97#define VTD_MMIO_OFF_MTRR_FIX4K_F0000_REG 0x168 /**< Fixed-range MTRR Register for 4K at f0000. */
98#define VTD_MMIO_OFF_MTRR_FIX4K_F8000_REG 0x170 /**< Fixed-range MTRR Register for 4K at f8000. */
99
100#define VTD_MMIO_OFF_MTRR_PHYSBASE0_REG 0x180 /**< Variable-range MTRR Base 0. */
101#define VTD_MMIO_OFF_MTRR_PHYSMASK0_REG 0x188 /**< Variable-range MTRR Mask 0. */
102#define VTD_MMIO_OFF_MTRR_PHYSBASE1_REG 0x190 /**< Variable-range MTRR Base 1. */
103#define VTD_MMIO_OFF_MTRR_PHYSMASK1_REG 0x198 /**< Variable-range MTRR Mask 1. */
104#define VTD_MMIO_OFF_MTRR_PHYSBASE2_REG 0x1a0 /**< Variable-range MTRR Base 2. */
105#define VTD_MMIO_OFF_MTRR_PHYSMASK2_REG 0x1a8 /**< Variable-range MTRR Mask 2. */
106#define VTD_MMIO_OFF_MTRR_PHYSBASE3_REG 0x1b0 /**< Variable-range MTRR Base 3. */
107#define VTD_MMIO_OFF_MTRR_PHYSMASK3_REG 0x1b8 /**< Variable-range MTRR Mask 3. */
108#define VTD_MMIO_OFF_MTRR_PHYSBASE4_REG 0x1c0 /**< Variable-range MTRR Base 4. */
109#define VTD_MMIO_OFF_MTRR_PHYSMASK4_REG 0x1c8 /**< Variable-range MTRR Mask 4. */
110#define VTD_MMIO_OFF_MTRR_PHYSBASE5_REG 0x1d0 /**< Variable-range MTRR Base 5. */
111#define VTD_MMIO_OFF_MTRR_PHYSMASK5_REG 0x1d8 /**< Variable-range MTRR Mask 5. */
112#define VTD_MMIO_OFF_MTRR_PHYSBASE6_REG 0x1e0 /**< Variable-range MTRR Base 6. */
113#define VTD_MMIO_OFF_MTRR_PHYSMASK6_REG 0x1e8 /**< Variable-range MTRR Mask 6. */
114#define VTD_MMIO_OFF_MTRR_PHYSBASE7_REG 0x1f0 /**< Variable-range MTRR Base 7. */
115#define VTD_MMIO_OFF_MTRR_PHYSMASK7_REG 0x1f8 /**< Variable-range MTRR Mask 7. */
116#define VTD_MMIO_OFF_MTRR_PHYSBASE8_REG 0x200 /**< Variable-range MTRR Base 8. */
117#define VTD_MMIO_OFF_MTRR_PHYSMASK8_REG 0x208 /**< Variable-range MTRR Mask 8. */
118#define VTD_MMIO_OFF_MTRR_PHYSBASE9_REG 0x210 /**< Variable-range MTRR Base 9. */
119#define VTD_MMIO_OFF_MTRR_PHYSMASK9_REG 0x218 /**< Variable-range MTRR Mask 9. */
120#define VTD_MMIO_GROUP_0_OFF_LAST VTD_MMIO_OFF_MTRR_PHYSMASK9_REG
121#define VTD_MMIO_GROUP_0_OFF_END (VTD_MMIO_GROUP_0_OFF_LAST + 8 /* sizeof MTRR_PHYSMASK9_REG */)
122
123#define VTD_MMIO_GROUP_1_OFF_FIRST 0xe00
124#define VTD_MMIO_OFF_VCCAP_REG VTD_MMIO_GROUP_1_OFF_FIRST /**< Virtual Command Capability. */
125#define VTD_MMIO_OFF_VCMD_REG 0xe10 /**< Virtual Command. */
126#define VTD_MMIO_OFF_VCRSP_REG 0xe20 /**< Virtual Command Response. */
127#define VTD_MMIO_GROUP_1_OFF_LAST VTD_MMIO_OFF_VCRSP_REG
128#define VTD_MMIO_GROUP_1_OFF_END (VTD_MMIO_GROUP_1_OFF_LAST + 8 /* sizeof VCRSP_REG */)
129
130#define VTD_MMIO_GROUP_0_SIZE (VTD_MMIO_GROUP_0_OFF_END - VTD_MMIO_GROUP_0_OFF_FIRST) /*bytes*/
131#define VTD_MMIO_GROUP_1_SIZE (VTD_MMIO_GROUP_1_OFF_END - VTD_MMIO_GROUP_1_OFF_FIRST) /*bytes*/
132/** @} */
133
134
135/** @name Root Entry.
136 * In accordance with the Intel spec.
137 * @{ */
138/** P: Present. */
139#define VTD_BF_0_ROOT_ENTRY_P_SHIFT 0
140#define VTD_BF_0_ROOT_ENTRY_P_MASK UINT64_C(0x0000000000000001)
141/** R: Reserved (bits 11:1). */
142#define VTD_BF_0_ROOT_ENTRY_RSVD_11_1_SHIFT 1
143#define VTD_BF_0_ROOT_ENTRY_RSVD_11_1_MASK UINT64_C(0x0000000000000ffe)
144/** CTP: Context-Table Pointer. */
145#define VTD_BF_0_ROOT_ENTRY_CTP_SHIFT 12
146#define VTD_BF_0_ROOT_ENTRY_CTP_MASK UINT64_C(0xfffffffffffff000)
147RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_ROOT_ENTRY_, UINT64_C(0), UINT64_MAX,
148 (P, RSVD_11_1, CTP));
149
150/** Root Entry. */
151typedef struct VTD_ROOT_ENTRY_T
152{
153 /** The qwords in the root entry. */
154 uint64_t au64[2];
155} VTD_ROOT_ENTRY_T;
156/** Pointer to a root entry. */
157typedef VTD_ROOT_ENTRY_T *PVTD_ROOT_ENTRY_T;
158/** Pointer to a const root entry. */
159typedef VTD_ROOT_ENTRY_T const *PCVTD_ROOT_ENTRY_T;
160/** @} */
161
162
163/** @name Scalable-mode Root Entry.
164 * In accordance with the Intel spec.
165 * @{ */
166/** LP: Lower Present. */
167#define VTD_BF_0_SM_ROOT_ENTRY_LP_SHIFT 0
168#define VTD_BF_0_SM_ROOT_ENTRY_LP_MASK UINT64_C(0x0000000000000001)
169/** R: Reserved (bits 11:1). */
170#define VTD_BF_0_SM_ROOT_ENTRY_RSVD_11_1_SHIFT 1
171#define VTD_BF_0_SM_ROOT_ENTRY_RSVD_11_1_MASK UINT64_C(0x0000000000000ffe)
172/** LCTP: Lower Context-Table Pointer */
173#define VTD_BF_0_SM_ROOT_ENTRY_LCTP_SHIFT 12
174#define VTD_BF_0_SM_ROOT_ENTRY_LCTP_MASK UINT64_C(0xfffffffffffff000)
175RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_SM_ROOT_ENTRY_, UINT64_C(0), UINT64_MAX,
176 (LP, RSVD_11_1, LCTP));
177
178/** UP: Upper Present. */
179#define VTD_BF_1_SM_ROOT_ENTRY_UP_SHIFT 0
180#define VTD_BF_1_SM_ROOT_ENTRY_UP_MASK UINT64_C(0x0000000000000001)
181/** R: Reserved (bits 11:1). */
182#define VTD_BF_1_SM_ROOT_ENTRY_RSVD_11_1_SHIFT 1
183#define VTD_BF_1_SM_ROOT_ENTRY_RSVD_11_1_MASK UINT64_C(0x0000000000000ffe)
184/** UCTP: Upper Context-Table Pointer. */
185#define VTD_BF_1_SM_ROOT_ENTRY_UCTP_SHIFT 12
186#define VTD_BF_1_SM_ROOT_ENTRY_UCTP_MASK UINT64_C(0xfffffffffffff000)
187RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_SM_ROOT_ENTRY_, UINT64_C(0), UINT64_MAX,
188 (UP, RSVD_11_1, UCTP));
189
190/** Scalable-mode root entry. */
191typedef struct VTD_SM_ROOT_ENTRY_T
192{
193 /** The lower scalable-mode root entry. */
194 uint64_t uLower;
195 /** The upper scalable-mode root entry. */
196 uint64_t uUpper;
197} VTD_SM_ROOT_ENTRY_T;
198/** Pointer to a scalable-mode root entry. */
199typedef VTD_SM_ROOT_ENTRY_T *PVTD_SM_ROOT_ENTRY_T;
200/** Pointer to a const scalable-mode root entry. */
201typedef VTD_SM_ROOT_ENTRY_T const *PCVTD_SM_ROOT_ENTRY_T;
202/** @} */
203
204
205/** @name Context Entry.
206 * In accordance with the Intel spec.
207 * @{ */
208/** P: Present. */
209#define VTD_BF_0_CONTEXT_ENTRY_P_SHIFT 0
210#define VTD_BF_0_CONTEXT_ENTRY_P_MASK UINT64_C(0x0000000000000001)
211/** FPD: Fault Processing Disable. */
212#define VTD_BF_0_CONTEXT_ENTRY_FPD_SHIFT 1
213#define VTD_BF_0_CONTEXT_ENTRY_FPD_MASK UINT64_C(0x0000000000000002)
214/** TT: Translation Type. */
215#define VTD_BF_0_CONTEXT_ENTRY_TT_SHIFT 2
216#define VTD_BF_0_CONTEXT_ENTRY_TT_MASK UINT64_C(0x000000000000000c)
217/** R: Reserved (bits 11:4). */
218#define VTD_BF_0_CONTEXT_ENTRY_RSVD_11_4_SHIFT 4
219#define VTD_BF_0_CONTEXT_ENTRY_RSVD_11_4_MASK UINT64_C(0x0000000000000ff0)
220/** SLPTPTR: Second Level Page Translation Pointer. */
221#define VTD_BF_0_CONTEXT_ENTRY_SLPTPTR_SHIFT 12
222#define VTD_BF_0_CONTEXT_ENTRY_SLPTPTR_MASK UINT64_C(0xfffffffffffff000)
223RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_CONTEXT_ENTRY_, UINT64_C(0), UINT64_MAX,
224 (P, FPD, TT, RSVD_11_4, SLPTPTR));
225
226/** AW: Address Width. */
227#define VTD_BF_1_CONTEXT_ENTRY_AW_SHIFT 0
228#define VTD_BF_1_CONTEXT_ENTRY_AW_MASK UINT64_C(0x0000000000000007)
229/** IGN: Ignored (bits 6:3). */
230#define VTD_BF_1_CONTEXT_ENTRY_IGN_6_3_SHIFT 3
231#define VTD_BF_1_CONTEXT_ENTRY_IGN_6_3_MASK UINT64_C(0x0000000000000078)
232/** R: Reserved (bit 7). */
233#define VTD_BF_1_CONTEXT_ENTRY_RSVD_7_SHIFT 7
234#define VTD_BF_1_CONTEXT_ENTRY_RSVD_7_MASK UINT64_C(0x0000000000000080)
235/** DID: Domain Identifier. */
236#define VTD_BF_1_CONTEXT_ENTRY_DID_SHIFT 8
237#define VTD_BF_1_CONTEXT_ENTRY_DID_MASK UINT64_C(0x0000000000ffff00)
238/** R: Reserved (bits 63:24). */
239#define VTD_BF_1_CONTEXT_ENTRY_RSVD_63_24_SHIFT 24
240#define VTD_BF_1_CONTEXT_ENTRY_RSVD_63_24_MASK UINT64_C(0xffffffffff000000)
241RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_CONTEXT_ENTRY_, UINT64_C(0), UINT64_MAX,
242 (AW, IGN_6_3, RSVD_7, DID, RSVD_63_24));
243
244/** Context Entry. */
245typedef struct VTD_CONTEXT_ENTRY_T
246{
247 /** The qwords in the context entry. */
248 uint64_t au64[2];
249} VTD_CONTEXT_ENTRY_T;
250/** Pointer to a context entry. */
251typedef VTD_CONTEXT_ENTRY_T *PVTD_CONTEXT_ENTRY_T;
252/** Pointer to a const context entry. */
253typedef VTD_CONTEXT_ENTRY_T const *PCVTD_CONTEXT_ENTRY_T;
254/** @} */
255
256
257/** @name Scalable-mode Context Entry.
258 * In accordance with the Intel spec.
259 * @{ */
260/** P: Present. */
261#define VTD_BF_0_SM_CONTEXT_ENTRY_P_SHIFT 0
262#define VTD_BF_0_SM_CONTEXT_ENTRY_P_MASK UINT64_C(0x0000000000000001)
263/** FPD: Fault Processing Disable. */
264#define VTD_BF_0_SM_CONTEXT_ENTRY_FPD_SHIFT 1
265#define VTD_BF_0_SM_CONTEXT_ENTRY_FPD_MASK UINT64_C(0x0000000000000002)
266/** DTE: Device-TLB Enable. */
267#define VTD_BF_0_SM_CONTEXT_ENTRY_DTE_SHIFT 2
268#define VTD_BF_0_SM_CONTEXT_ENTRY_DTE_MASK UINT64_C(0x0000000000000004)
269/** PASIDE: PASID Enable. */
270#define VTD_BF_0_SM_CONTEXT_ENTRY_PASIDE_SHIFT 3
271#define VTD_BF_0_SM_CONTEXT_ENTRY_PASIDE_MASK UINT64_C(0x0000000000000008)
272/** PRE: Page Request Enable. */
273#define VTD_BF_0_SM_CONTEXT_ENTRY_PRE_SHIFT 4
274#define VTD_BF_0_SM_CONTEXT_ENTRY_PRE_MASK UINT64_C(0x0000000000000010)
275/** R: Reserved (bits 8:5). */
276#define VTD_BF_0_SM_CONTEXT_ENTRY_RSVD_8_5_SHIFT 5
277#define VTD_BF_0_SM_CONTEXT_ENTRY_RSVD_8_5_MASK UINT64_C(0x00000000000001e0)
278/** PDTS: PASID Directory Size. */
279#define VTD_BF_0_SM_CONTEXT_ENTRY_PDTS_SHIFT 9
280#define VTD_BF_0_SM_CONTEXT_ENTRY_PDTS_MASK UINT64_C(0x0000000000000e00)
281/** PASIDDIRPTR: PASID Directory Pointer. */
282#define VTD_BF_0_SM_CONTEXT_ENTRY_PASIDDIRPTR_SHIFT 12
283#define VTD_BF_0_SM_CONTEXT_ENTRY_PASIDDIRPTR_MASK UINT64_C(0xfffffffffffff000)
284RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_SM_CONTEXT_ENTRY_, UINT64_C(0), UINT64_MAX,
285 (P, FPD, DTE, PASIDE, PRE, RSVD_8_5, PDTS, PASIDDIRPTR));
286
287/** RID_PASID: Requested Id to PASID assignment. */
288#define VTD_BF_1_SM_CONTEXT_ENTRY_RID_PASID_SHIFT 0
289#define VTD_BF_1_SM_CONTEXT_ENTRY_RID_PASID_MASK UINT64_C(0x00000000000fffff)
290/** RID_PRIV: Requested Id to PrivilegeModeRequested assignment. */
291#define VTD_BF_1_SM_CONTEXT_ENTRY_RID_PRIV_SHIFT 20
292#define VTD_BF_1_SM_CONTEXT_ENTRY_RID_PRIV_MASK UINT64_C(0x0000000000100000)
293/** R: Reserved (bits 63:21). */
294#define VTD_BF_1_SM_CONTEXT_ENTRY_RSVD_63_21_SHIFT 21
295#define VTD_BF_1_SM_CONTEXT_ENTRY_RSVD_63_21_MASK UINT64_C(0xffffffffffe00000)
296RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_SM_CONTEXT_ENTRY_, UINT64_C(0), UINT64_MAX,
297 (RID_PASID, RID_PRIV, RSVD_63_21));
298
299/** Context Entry. */
300typedef struct VTD_SM_CONTEXT_ENTRY_T
301{
302 /** The qwords in the scalable-mode context entry. */
303 uint64_t au64[4];
304} VTD_SM_CONTEXT_ENTRY_T;
305/** Pointer to a scalable-mode context entry. */
306typedef VTD_SM_CONTEXT_ENTRY_T *PVTD_SM_CONTEXT_ENTRY_T;
307/** Pointer to a const scalable-mode context entry. */
308typedef VTD_SM_CONTEXT_ENTRY_T const *PCVTD_SM_CONTEXT_ENTRY_T;
309/** @} */
310
311
312/** @name Scalable-mode PASID Directory Entry.
313 * In accordance with the Intel spec.
314 * @{ */
315/** P: Present. */
316#define VTD_BF_SM_PASID_DIR_ENTRY_P_SHIFT 0
317#define VTD_BF_SM_PASID_DIR_ENTRY_P_MASK UINT64_C(0x0000000000000001)
318/** FPD: Fault Processing Disable. */
319#define VTD_BF_SM_PASID_DIR_ENTRY_FPD_SHIFT 1
320#define VTD_BF_SM_PASID_DIR_ENTRY_FPD_MASK UINT64_C(0x0000000000000002)
321/** R: Reserved (bits 11:2). */
322#define VTD_BF_SM_PASID_DIR_ENTRY_RSVD_11_2_SHIFT 2
323#define VTD_BF_SM_PASID_DIR_ENTRY_RSVD_11_2_MASK UINT64_C(0x0000000000000ffc)
324/** SMPTBLPTR: Scalable Mode PASID Table Pointer. */
325#define VTD_BF_SM_PASID_DIR_ENTRY_SMPTBLPTR_SHIFT 12
326#define VTD_BF_SM_PASID_DIR_ENTRY_SMPTBLPTR_MASK UINT64_C(0xfffffffffffff000)
327RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_SM_PASID_DIR_ENTRY_, UINT64_C(0), UINT64_MAX,
328 (P, FPD, RSVD_11_2, SMPTBLPTR));
329
330/** Scalable-mode PASID Directory Entry. */
331typedef struct VTD_SM_PASID_DIR_ENTRY_T
332{
333 /** The scalable-mode PASID directory entry. */
334 uint64_t u;
335} VTD_SM_PASID_DIR_ENTRY_T;
336/** Pointer to a scalable-mode PASID directory entry. */
337typedef VTD_SM_PASID_DIR_ENTRY_T *PVTD_SM_PASID_DIR_ENTRY_T;
338/** Pointer to a const scalable-mode PASID directory entry. */
339typedef VTD_SM_PASID_DIR_ENTRY_T const *PCVTD_SM_PASID_DIR_ENTRY_T;
340/** @} */
341
342
343/** @name Scalable-mode PASID Table Entry.
344 * In accordance with the Intel spec.
345 * @{ */
346/** P: Present. */
347#define VTD_BF_0_SM_PASID_TBL_ENTRY_P_SHIFT 0
348#define VTD_BF_0_SM_PASID_TBL_ENTRY_P_MASK UINT64_C(0x0000000000000001)
349/** FPD: Fault Processing Disable. */
350#define VTD_BF_0_SM_PASID_TBL_ENTRY_FPD_SHIFT 1
351#define VTD_BF_0_SM_PASID_TBL_ENTRY_FPD_MASK UINT64_C(0x0000000000000002)
352/** AW: Address Width. */
353#define VTD_BF_0_SM_PASID_TBL_ENTRY_AW_SHIFT 2
354#define VTD_BF_0_SM_PASID_TBL_ENTRY_AW_MASK UINT64_C(0x000000000000001c)
355/** SLEE: Second-Level Execute Enable. */
356#define VTD_BF_0_SM_PASID_TBL_ENTRY_SLEE_SHIFT 5
357#define VTD_BF_0_SM_PASID_TBL_ENTRY_SLEE_MASK UINT64_C(0x0000000000000020)
358/** PGTT: PASID Granular Translation Type. */
359#define VTD_BF_0_SM_PASID_TBL_ENTRY_PGTT_SHIFT 6
360#define VTD_BF_0_SM_PASID_TBL_ENTRY_PGTT_MASK UINT64_C(0x00000000000001c0)
361/** SLADE: Second-Level Address/Dirty Enable. */
362#define VTD_BF_0_SM_PASID_TBL_ENTRY_SLADE_SHIFT 9
363#define VTD_BF_0_SM_PASID_TBL_ENTRY_SLADE_MASK UINT64_C(0x0000000000000200)
364/** R: Reserved (bits 11:10). */
365#define VTD_BF_0_SM_PASID_TBL_ENTRY_RSVD_11_10_SHIFT 10
366#define VTD_BF_0_SM_PASID_TBL_ENTRY_RSVD_11_10_MASK UINT64_C(0x0000000000000c00)
367/** SLPTPTR: Second-Level Page Table Pointer. */
368#define VTD_BF_0_SM_PASID_TBL_ENTRY_SLPTPTR_SHIFT 12
369#define VTD_BF_0_SM_PASID_TBL_ENTRY_SLPTPTR_MASK UINT64_C(0xfffffffffffff000)
370RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_SM_PASID_TBL_ENTRY_, UINT64_C(0), UINT64_MAX,
371 (P, FPD, AW, SLEE, PGTT, SLADE, RSVD_11_10, SLPTPTR));
372
373/** DID: Domain Identifer. */
374#define VTD_BF_1_SM_PASID_TBL_ENTRY_DID_SHIFT 0
375#define VTD_BF_1_SM_PASID_TBL_ENTRY_DID_MASK UINT64_C(0x000000000000ffff)
376/** R: Reserved (bits 22:16). */
377#define VTD_BF_1_SM_PASID_TBL_ENTRY_RSVD_22_16_SHIFT 16
378#define VTD_BF_1_SM_PASID_TBL_ENTRY_RSVD_22_16_MASK UINT64_C(0x00000000007f0000)
379/** PWSNP: Page-Walk Snoop. */
380#define VTD_BF_1_SM_PASID_TBL_ENTRY_PWSNP_SHIFT 23
381#define VTD_BF_1_SM_PASID_TBL_ENTRY_PWSNP_MASK UINT64_C(0x0000000000800000)
382/** PGSNP: Page Snoop. */
383#define VTD_BF_1_SM_PASID_TBL_ENTRY_PGSNP_SHIFT 24
384#define VTD_BF_1_SM_PASID_TBL_ENTRY_PGSNP_MASK UINT64_C(0x0000000001000000)
385/** CD: Cache Disable. */
386#define VTD_BF_1_SM_PASID_TBL_ENTRY_CD_SHIFT 25
387#define VTD_BF_1_SM_PASID_TBL_ENTRY_CD_MASK UINT64_C(0x0000000002000000)
388/** EMTE: Extended Memory Type Enable. */
389#define VTD_BF_1_SM_PASID_TBL_ENTRY_EMTE_SHIFT 26
390#define VTD_BF_1_SM_PASID_TBL_ENTRY_EMTE_MASK UINT64_C(0x0000000004000000)
391/** EMT: Extended Memory Type. */
392#define VTD_BF_1_SM_PASID_TBL_ENTRY_EMT_SHIFT 27
393#define VTD_BF_1_SM_PASID_TBL_ENTRY_EMT_MASK UINT64_C(0x0000000038000000)
394/** PWT: Page-Level Write Through. */
395#define VTD_BF_1_SM_PASID_TBL_ENTRY_PWT_SHIFT 30
396#define VTD_BF_1_SM_PASID_TBL_ENTRY_PWT_MASK UINT64_C(0x0000000040000000)
397/** PCD: Page-Level Cache Disable. */
398#define VTD_BF_1_SM_PASID_TBL_ENTRY_PCD_SHIFT 31
399#define VTD_BF_1_SM_PASID_TBL_ENTRY_PCD_MASK UINT64_C(0x0000000080000000)
400/** PAT: Page Attribute Table. */
401#define VTD_BF_1_SM_PASID_TBL_ENTRY_PAT_SHIFT 32
402#define VTD_BF_1_SM_PASID_TBL_ENTRY_PAT_MASK UINT64_C(0xffffffff00000000)
403RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_SM_PASID_TBL_ENTRY_, UINT64_C(0), UINT64_MAX,
404 (DID, RSVD_22_16, PWSNP, PGSNP, CD, EMTE, EMT, PWT, PCD, PAT));
405
406/** SRE: Supervisor Request Enable. */
407#define VTD_BF_2_SM_PASID_TBL_ENTRY_SRE_SHIFT 0
408#define VTD_BF_2_SM_PASID_TBL_ENTRY_SRE_MASK UINT64_C(0x0000000000000001)
409/** ERE: Execute Request Enable. */
410#define VTD_BF_2_SM_PASID_TBL_ENTRY_ERE_SHIFT 1
411#define VTD_BF_2_SM_PASID_TBL_ENTRY_ERE_MASK UINT64_C(0x0000000000000002)
412/** FLPM: First Level Paging Mode. */
413#define VTD_BF_2_SM_PASID_TBL_ENTRY_FLPM_SHIFT 2
414#define VTD_BF_2_SM_PASID_TBL_ENTRY_FLPM_MASK UINT64_C(0x000000000000000c)
415/** WPE: Write Protect Enable. */
416#define VTD_BF_2_SM_PASID_TBL_ENTRY_WPE_SHIFT 4
417#define VTD_BF_2_SM_PASID_TBL_ENTRY_WPE_MASK UINT64_C(0x0000000000000010)
418/** NXE: No-Execute Enable. */
419#define VTD_BF_2_SM_PASID_TBL_ENTRY_NXE_SHIFT 5
420#define VTD_BF_2_SM_PASID_TBL_ENTRY_NXE_MASK UINT64_C(0x0000000000000020)
421/** SMEP: Supervisor Mode Execute Prevent. */
422#define VTD_BF_2_SM_PASID_TBL_ENTRY_SMPE_SHIFT 6
423#define VTD_BF_2_SM_PASID_TBL_ENTRY_SMPE_MASK UINT64_C(0x0000000000000040)
424/** EAFE: Extended Accessed Flag Enable. */
425#define VTD_BF_2_SM_PASID_TBL_ENTRY_EAFE_SHIFT 7
426#define VTD_BF_2_SM_PASID_TBL_ENTRY_EAFE_MASK UINT64_C(0x0000000000000080)
427/** R: Reserved (bits 11:8). */
428#define VTD_BF_2_SM_PASID_TBL_ENTRY_RSVD_11_8_SHIFT 8
429#define VTD_BF_2_SM_PASID_TBL_ENTRY_RSVD_11_8_MASK UINT64_C(0x0000000000000f00)
430/** FLPTPTR: First Level Page Table Pointer. */
431#define VTD_BF_2_SM_PASID_TBL_ENTRY_FLPTPTR_SHIFT 12
432#define VTD_BF_2_SM_PASID_TBL_ENTRY_FLPTPTR_MASK UINT64_C(0xfffffffffffff000)
433RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_2_SM_PASID_TBL_ENTRY_, UINT64_C(0), UINT64_MAX,
434 (SRE, ERE, FLPM, WPE, NXE, SMPE, EAFE, RSVD_11_8, FLPTPTR));
435
436/** Scalable-mode PASID Table Entry. */
437typedef struct VTD_SM_PASID_TBL_ENTRY_T
438{
439 /** The qwords in the scalable-mode PASID table entry. */
440 uint64_t au64[8];
441} VTD_SM_PASID_TBL_ENTRY_T;
442/** Pointer to a scalable-mode PASID table entry. */
443typedef VTD_SM_PASID_TBL_ENTRY_T *PVTD_SM_PASID_TBL_ENTRY_T;
444/** Pointer to a const scalable-mode PASID table entry. */
445typedef VTD_SM_PASID_TBL_ENTRY_T const *PCVTD_SM_PASID_TBL_ENTRY_T;
446/** @} */
447
448
449/** @name First-Level Paging Entry.
450 * In accordance with the Intel spec.
451 * @{ */
452/** P: Present. */
453#define VTD_BF_FLP_ENTRY_P_SHIFT 0
454#define VTD_BF_FLP_ENTRY_P_MASK UINT64_C(0x0000000000000001)
455/** R/W: Read/Write. */
456#define VTD_BF_FLP_ENTRY_RW_SHIFT 1
457#define VTD_BF_FLP_ENTRY_RW_MASK UINT64_C(0x0000000000000002)
458/** U/S: User/Supervisor. */
459#define VTD_BF_FLP_ENTRY_US_SHIFT 2
460#define VTD_BF_FLP_ENTRY_US_MASK UINT64_C(0x0000000000000004)
461/** PWT: Page-Level Write Through. */
462#define VTD_BF_FLP_ENTRY_PWT_SHIFT 3
463#define VTD_BF_FLP_ENTRY_PWT_MASK UINT64_C(0x0000000000000008)
464/** PC: Page-Level Cache Disable. */
465#define VTD_BF_FLP_ENTRY_PCD_SHIFT 4
466#define VTD_BF_FLP_ENTRY_PCD_MASK UINT64_C(0x0000000000000010)
467/** A: Accessed. */
468#define VTD_BF_FLP_ENTRY_A_SHIFT 5
469#define VTD_BF_FLP_ENTRY_A_MASK UINT64_C(0x0000000000000020)
470/** IGN: Ignored (bit 6). */
471#define VTD_BF_FLP_ENTRY_IGN_6_SHIFT 6
472#define VTD_BF_FLP_ENTRY_IGN_6_MASK UINT64_C(0x0000000000000040)
473/** R: Reserved (bit 7). */
474#define VTD_BF_FLP_ENTRY_RSVD_7_SHIFT 7
475#define VTD_BF_FLP_ENTRY_RSVD_7_MASK UINT64_C(0x0000000000000080)
476/** IGN: Ignored (bits 9:8). */
477#define VTD_BF_FLP_ENTRY_IGN_9_8_SHIFT 8
478#define VTD_BF_FLP_ENTRY_IGN_9_8_MASK UINT64_C(0x0000000000000300)
479/** EA: Extended Accessed. */
480#define VTD_BF_FLP_ENTRY_EA_SHIFT 10
481#define VTD_BF_FLP_ENTRY_EA_MASK UINT64_C(0x0000000000000400)
482/** IGN: Ignored (bit 11). */
483#define VTD_BF_FLP_ENTRY_IGN_11_SHIFT 11
484#define VTD_BF_FLP_ENTRY_IGN_11_MASK UINT64_C(0x0000000000000800)
485/** ADDR: Address. */
486#define VTD_BF_FLP_ENTRY_ADDR_SHIFT 12
487#define VTD_BF_FLP_ENTRY_ADDR_MASK UINT64_C(0x000ffffffffff000)
488/** IGN: Ignored (bits 62:52). */
489#define VTD_BF_FLP_ENTRY_IGN_62_52_SHIFT 52
490#define VTD_BF_FLP_ENTRY_IGN_62_52_MASK UINT64_C(0x7ff0000000000000)
491/** XD: Execute Disabled. */
492#define VTD_BF_FLP_ENTRY_XD_SHIFT 63
493#define VTD_BF_FLP_ENTRY_XD_MASK UINT64_C(0x8000000000000000)
494RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_FLP_ENTRY_, UINT64_C(0), UINT64_MAX,
495 (P, RW, US, PWT, PCD, A, IGN_6, RSVD_7, IGN_9_8, EA, IGN_11, ADDR, IGN_62_52, XD));
496
497/** First-Level Paging Entry. */
498typedef struct VTD_FLP_ENTRY_T
499{
500 /** The first-level paging entry. */
501 uint64_t u;
502} VTD_FLP_ENTRY_T;
503/** Pointer to a first-level paging entry. */
504typedef VTD_FLP_ENTRY_T *PVTD_FLP_ENTRY_T;
505/** Pointer to a const first-level paging entry. */
506typedef VTD_FLP_ENTRY_T const *PCVTD_FLP_ENTRY_T;
507/** @} */
508
509
510/** @name Second-Level Paging Entry.
511 * In accordance with the Intel spec.
512 * @{ */
513/** R: Read. */
514#define VTD_BF_SLP_ENTRY_R_SHIFT 0
515#define VTD_BF_SLP_ENTRY_R_MASK UINT64_C(0x0000000000000001)
516/** W: Write. */
517#define VTD_BF_SLP_ENTRY_W_SHIFT 1
518#define VTD_BF_SLP_ENTRY_W_MASK UINT64_C(0x0000000000000002)
519/** X: Execute. */
520#define VTD_BF_SLP_ENTRY_X_SHIFT 2
521#define VTD_BF_SLP_ENTRY_X_MASK UINT64_C(0x0000000000000004)
522/** IGN: Ignored (bits 6:3). */
523#define VTD_BF_SLP_ENTRY_IGN_6_3_SHIFT 3
524#define VTD_BF_SLP_ENTRY_IGN_6_3_MASK UINT64_C(0x0000000000000078)
525/** R: Reserved (bit 7). */
526#define VTD_BF_SLP_ENTRY_RSVD_7_SHIFT 7
527#define VTD_BF_SLP_ENTRY_RSVD_7_MASK UINT64_C(0x0000000000000080)
528/** A: Accessed. */
529#define VTD_BF_SLP_ENTRY_A_SHIFT 8
530#define VTD_BF_SLP_ENTRY_A_MASK UINT64_C(0x0000000000000100)
531/** IGN: Ignored (bits 10:9). */
532#define VTD_BF_SLP_ENTRY_IGN_10_9_SHIFT 9
533#define VTD_BF_SLP_ENTRY_IGN_10_9_MASK UINT64_C(0x0000000000000600)
534/** R: Reserved (bit 11). */
535#define VTD_BF_SLP_ENTRY_RSVD_11_SHIFT 11
536#define VTD_BF_SLP_ENTRY_RSVD_11_MASK UINT64_C(0x0000000000000800)
537/** ADDR: Address. */
538#define VTD_BF_SLP_ENTRY_ADDR_SHIFT 12
539#define VTD_BF_SLP_ENTRY_ADDR_MASK UINT64_C(0x000ffffffffff000)
540/** IGN: Ignored (bits 61:52). */
541#define VTD_BF_SLP_ENTRY_IGN_61_52_SHIFT 52
542#define VTD_BF_SLP_ENTRY_IGN_61_52_MASK UINT64_C(0x3ff0000000000000)
543/** R: Reserved (bit 62). */
544#define VTD_BF_SLP_ENTRY_RSVD_62_SHIFT 62
545#define VTD_BF_SLP_ENTRY_RSVD_62_MASK UINT64_C(0x4000000000000000)
546/** IGN: Ignored (bit 63). */
547#define VTD_BF_SLP_ENTRY_IGN_63_SHIFT 63
548#define VTD_BF_SLP_ENTRY_IGN_63_MASK UINT64_C(0x8000000000000000)
549RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_SLP_ENTRY_, UINT64_C(0), UINT64_MAX,
550 (R, W, X, IGN_6_3, RSVD_7, A, IGN_10_9, RSVD_11, ADDR, IGN_61_52, RSVD_62, IGN_63));
551
552/** Second-Level Paging Entry. */
553typedef struct VTD_SLP_ENTRY_T
554{
555 /** The second-level paging entry. */
556 uint64_t u;
557} VTD_SLP_ENTRY_T;
558/** Pointer to a second-level paging entry. */
559typedef VTD_SLP_ENTRY_T *PVTD_SLP_ENTRY_T;
560/** Pointer to a const second-level paging entry. */
561typedef VTD_SLP_ENTRY_T const *PCVTD_SLP_ENTRY_T;
562/** @} */
563
564
565/** @name Fault Record.
566 * In accordance with the Intel spec.
567 * @{ */
568/** R: Reserved (bits 11:0). */
569#define VTD_BF_0_FAULT_RECORD_RSVD_11_0_SHIFT 0
570#define VTD_BF_0_FAULT_RECORD_RSVD_11_0_MASK UINT64_C(0x0000000000000fff)
571/** FI: Fault Information. */
572#define VTD_BF_0_FAULT_RECORD_FI_SHIFT 12
573#define VTD_BF_0_FAULT_RECORD_FI_MASK UINT64_C(0xfffffffffffff000)
574RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_FAULT_RECORD_, UINT64_C(0), UINT64_MAX,
575 (RSVD_11_0, FI));
576
577/** SID: Source identifier. */
578#define VTD_BF_1_FAULT_RECORD_SID_SHIFT 0
579#define VTD_BF_1_FAULT_RECORD_SID_MASK UINT64_C(0x000000000000ffff)
580/** R: Reserved (bits 28:16). */
581#define VTD_BF_1_FAULT_RECORD_RSVD_28_16_SHIFT 16
582#define VTD_BF_1_FAULT_RECORD_RSVD_28_16_MASK UINT64_C(0x000000001fff0000)
583/** PRIV: Privilege Mode Requested. */
584#define VTD_BF_1_FAULT_RECORD_PRIV_SHIFT 29
585#define VTD_BF_1_FAULT_RECORD_PRIV_MASK UINT64_C(0x0000000020000000)
586/** EXE: Execute Permission Requested. */
587#define VTD_BF_1_FAULT_RECORD_EXE_SHIFT 30
588#define VTD_BF_1_FAULT_RECORD_EXE_MASK UINT64_C(0x0000000040000000)
589/** PP: PASID Present. */
590#define VTD_BF_1_FAULT_RECORD_PP_SHIFT 31
591#define VTD_BF_1_FAULT_RECORD_PP_MASK UINT64_C(0x0000000080000000)
592/** FR: Fault Reason. */
593#define VTD_BF_1_FAULT_RECORD_FR_SHIFT 32
594#define VTD_BF_1_FAULT_RECORD_FR_MASK UINT64_C(0x000000ff00000000)
595/** PV: PASID Value. */
596#define VTD_BF_1_FAULT_RECORD_PV_SHIFT 40
597#define VTD_BF_1_FAULT_RECORD_PV_MASK UINT64_C(0x0fffff0000000000)
598/** AT: Address Type. */
599#define VTD_BF_1_FAULT_RECORD_AT_SHIFT 60
600#define VTD_BF_1_FAULT_RECORD_AT_MASK UINT64_C(0x3000000000000000)
601/** T: Type. */
602#define VTD_BF_1_FAULT_RECORD_T_SHIFT 62
603#define VTD_BF_1_FAULT_RECORD_T_MASK UINT64_C(0x4000000000000000)
604/** R: Reserved (bit 127). */
605#define VTD_BF_1_FAULT_RECORD_RSVD_63_SHIFT 63
606#define VTD_BF_1_FAULT_RECORD_RSVD_63_MASK UINT64_C(0x8000000000000000)
607RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_FAULT_RECORD_, UINT64_C(0), UINT64_MAX,
608 (SID, RSVD_28_16, PRIV, EXE, PP, FR, PV, AT, T, RSVD_63));
609
610/** Fault record. */
611typedef struct VTD_FAULT_RECORD_T
612{
613 /** The qwords in the fault record. */
614 uint64_t au64[2];
615} VTD_FAULT_RECORD_T;
616/** Pointer to a fault record. */
617typedef VTD_FAULT_RECORD_T *PVTD_FAULT_RECORD_T;
618/** Pointer to a const fault record. */
619typedef VTD_FAULT_RECORD_T const *PCVTD_FAULT_RECORD_T;
620/** @} */
621
622
623/** @name Interrupt Remapping Table Entry (IRTE) for Remapped Interrupts.
624 * In accordance with the Intel spec.
625 * @{ */
626/** P: Present. */
627#define VTD_BF_0_IRTE_P_SHIFT 0
628#define VTD_BF_0_IRTE_P_MASK UINT64_C(0x0000000000000001)
629/** FPD: Fault Processing Disable. */
630#define VTD_BF_0_IRTE_FPD_SHIFT 1
631#define VTD_BF_0_IRTE_FPD_MASK UINT64_C(0x0000000000000002)
632/** DM: Destination Mode (0=physical, 1=logical). */
633#define VTD_BF_0_IRTE_DM_SHIFT 2
634#define VTD_BF_0_IRTE_DM_MASK UINT64_C(0x0000000000000004)
635/** RH: Redirection Hint. */
636#define VTD_BF_0_IRTE_RH_SHIFT 3
637#define VTD_BF_0_IRTE_RH_MASK UINT64_C(0x0000000000000008)
638/** TM: Trigger Mode. */
639#define VTD_BF_0_IRTE_TM_SHIFT 4
640#define VTD_BF_0_IRTE_TM_MASK UINT64_C(0x0000000000000010)
641/** DLM: Delivery Mode. */
642#define VTD_BF_0_IRTE_DLM_SHIFT 5
643#define VTD_BF_0_IRTE_DLM_MASK UINT64_C(0x00000000000000e0)
644/** AVL: Available. */
645#define VTD_BF_0_IRTE_AVAIL_SHIFT 8
646#define VTD_BF_0_IRTE_AVAIL_MASK UINT64_C(0x0000000000000f00)
647/** R: Reserved (bits 14:12). */
648#define VTD_BF_0_IRTE_RSVD_14_12_SHIFT 12
649#define VTD_BF_0_IRTE_RSVD_14_12_MASK UINT64_C(0x0000000000007000)
650/** IM: IRTE Mode. */
651#define VTD_BF_0_IRTE_IM_SHIFT 15
652#define VTD_BF_0_IRTE_IM_MASK UINT64_C(0x0000000000008000)
653/** V: Vector. */
654#define VTD_BF_0_IRTE_V_SHIFT 16
655#define VTD_BF_0_IRTE_V_MASK UINT64_C(0x0000000000ff0000)
656/** R: Reserved (bits 31:24). */
657#define VTD_BF_0_IRTE_RSVD_31_24_SHIFT 24
658#define VTD_BF_0_IRTE_RSVD_31_24_MASK UINT64_C(0x00000000ff000000)
659/** DST: Desination Id. */
660#define VTD_BF_0_IRTE_DST_SHIFT 32
661#define VTD_BF_0_IRTE_DST_MASK UINT64_C(0xffffffff00000000)
662RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_IRTE_, UINT64_C(0), UINT64_MAX,
663 (P, FPD, DM, RH, TM, DLM, AVAIL, RSVD_14_12, IM, V, RSVD_31_24, DST));
664
665/** SID: Source Identifier. */
666#define VTD_BF_1_IRTE_SID_SHIFT 0
667#define VTD_BF_1_IRTE_SID_MASK UINT64_C(0x000000000000ffff)
668/** SQ: Source-Id Qualifier. */
669#define VTD_BF_1_IRTE_SQ_SHIFT 16
670#define VTD_BF_1_IRTE_SQ_MASK UINT64_C(0x0000000000030000)
671/** SVT: Source Validation Type. */
672#define VTD_BF_1_IRTE_SVT_SHIFT 18
673#define VTD_BF_1_IRTE_SVT_MASK UINT64_C(0x00000000000c0000)
674/** R: Reserved (bits 127:84). */
675#define VTD_BF_1_IRTE_RSVD_63_20_SHIFT 20
676#define VTD_BF_1_IRTE_RSVD_63_20_MASK UINT64_C(0xfffffffffff00000)
677RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_IRTE_, UINT64_C(0), UINT64_MAX,
678 (SID, SQ, SVT, RSVD_63_20));
679
680/** Interrupt Remapping Table Entry (IRTE) for remapped interrupts. */
681typedef struct VTD_IRTE_T
682{
683 /** The qwords in the IRTE. */
684 uint64_t au64[2];
685} VTD_IRTE_T;
686/** Pointer to an IRTE. */
687typedef VTD_IRTE_T *PVTD_IRTE_T;
688/** Pointer to a const IRTE. */
689typedef VTD_IRTE_T const *PCVTD_IRTE_T;
690/** @} */
691
692
693/** @name Version Register (VER_REG).
694 * @{ */
695/** Min: Minor Version Number. */
696#define VTX_BF_VER_REG_MIN_SHIFT 0
697#define VTX_BF_VER_REG_MIN_MASK UINT32_C(0x0000000f)
698/** Max: Major Version Number. */
699#define VTX_BF_VER_REG_MAX_SHIFT 4
700#define VTX_BF_VER_REG_MAX_MASK UINT32_C(0x000000f0)
701/** R: Reserved (bits 31:8). */
702#define VTX_BF_VER_REG_RSVD_31_8_SHIFT 8
703#define VTX_BF_VER_REG_RSVD_31_8_MASK UINT32_C(0xffffff00)
704RT_BF_ASSERT_COMPILE_CHECKS(VTX_BF_VER_REG_, UINT32_C(0), UINT32_MAX,
705 (MIN, MAX, RSVD_31_8));
706/** RW: Read/write mask. */
707#define VTD_VER_REG_RW_MASK UINT32_C(0)
708/** @} */
709
710
711/** @name Capability Register (CAP_REG).
712 * @{ */
713/** ND: Number of domains supported. */
714#define VTD_BF_CAP_REG_ND_SHIFT 0
715#define VTD_BF_CAP_REG_ND_MASK UINT64_C(0x0000000000000007)
716/** AFL: Advanced Fault Logging. */
717#define VTD_BF_CAP_REG_AFL_SHIFT 3
718#define VTD_BF_CAP_REG_AFL_MASK UINT64_C(0x0000000000000008)
719/** RWBF: Required Write-Buffer Flushing. */
720#define VTD_BF_CAP_REG_RWBF_SHIFT 4
721#define VTD_BF_CAP_REG_RWBF_MASK UINT64_C(0x0000000000000010)
722/** PLMR: Protected Low-Memory Region. */
723#define VTD_BF_CAP_REG_PLMR_SHIFT 5
724#define VTD_BF_CAP_REG_PLMR_MASK UINT64_C(0x0000000000000020)
725/** PHMR: Protected High-Memory Region. */
726#define VTD_BF_CAP_REG_PHMR_SHIFT 6
727#define VTD_BF_CAP_REG_PHMR_MASK UINT64_C(0x0000000000000040)
728/** CM: Caching Mode. */
729#define VTD_BF_CAP_REG_CM_SHIFT 7
730#define VTD_BF_CAP_REG_CM_MASK UINT64_C(0x0000000000000080)
731/** SAGAW: Supported Adjusted Guest Address Widths. */
732#define VTD_BF_CAP_REG_SAGAW_SHIFT 8
733#define VTD_BF_CAP_REG_SAGAW_MASK UINT64_C(0x0000000000001f00)
734/** R: Reserved (bits 15:13). */
735#define VTD_BF_CAP_REG_RSVD_15_13_SHIFT 13
736#define VTD_BF_CAP_REG_RSVD_15_13_MASK UINT64_C(0x000000000000e000)
737/** MGAW: Maximum Guest Address Width. */
738#define VTD_BF_CAP_REG_MGAW_SHIFT 16
739#define VTD_BF_CAP_REG_MGAW_MASK UINT64_C(0x00000000003f0000)
740/** ZLR: Zero Length Read. */
741#define VTD_BF_CAP_REG_ZLR_SHIFT 22
742#define VTD_BF_CAP_REG_ZLR_MASK UINT64_C(0x0000000000400000)
743/** DEP: Deprecated MBZ. Reserved (bit 23). */
744#define VTD_BF_CAP_REG_RSVD_23_SHIFT 23
745#define VTD_BF_CAP_REG_RSVD_23_MASK UINT64_C(0x0000000000800000)
746/** FRO: Fault-recording Register Offset. */
747#define VTD_BF_CAP_REG_FRO_SHIFT 24
748#define VTD_BF_CAP_REG_FRO_MASK UINT64_C(0x00000003ff000000)
749/** SLLPS: Second Level Large Page Support. */
750#define VTD_BF_CAP_REG_SLLPS_SHIFT 34
751#define VTD_BF_CAP_REG_SLLPS_MASK UINT64_C(0x0000003c00000000)
752/** R: Reserved (bit 38). */
753#define VTD_BF_CAP_REG_RSVD_38_SHIFT 38
754#define VTD_BF_CAP_REG_RSVD_38_MASK UINT64_C(0x0000004000000000)
755/** PSI: Page Selective Invalidation. */
756#define VTD_BF_CAP_REG_PSI_SHIFT 39
757#define VTD_BF_CAP_REG_PSI_MASK UINT64_C(0x0000008000000000)
758/** NFR: Number of Fault-recording Registers. */
759#define VTD_BF_CAP_REG_NFR_SHIFT 40
760#define VTD_BF_CAP_REG_NFR_MASK UINT64_C(0x0000ff0000000000)
761/** MAMV: Maximum Address Mask Value. */
762#define VTD_BF_CAP_REG_MAMV_SHIFT 48
763#define VTD_BF_CAP_REG_MAMV_MASK UINT64_C(0x003f000000000000)
764/** DWD: Write Draining. */
765#define VTD_BF_CAP_REG_DWD_SHIFT 54
766#define VTD_BF_CAP_REG_DWD_MASK UINT64_C(0x0040000000000000)
767/** DRD: Read Draining. */
768#define VTD_BF_CAP_REG_DRD_SHIFT 55
769#define VTD_BF_CAP_REG_DRD_MASK UINT64_C(0x0080000000000000)
770/** FL1GP: First Level 1 GB Page Support. */
771#define VTD_BF_CAP_REG_FL1GP_SHIFT 56
772#define VTD_BF_CAP_REG_FL1GP_MASK UINT64_C(0x0100000000000000)
773/** R: Reserved (bits 58:57). */
774#define VTD_BF_CAP_REG_RSVD_58_57_SHIFT 57
775#define VTD_BF_CAP_REG_RSVD_58_57_MASK UINT64_C(0x0600000000000000)
776/** PI: Posted Interrupt Support. */
777#define VTD_BF_CAP_REG_PI_SHIFT 59
778#define VTD_BF_CAP_REG_PI_MASK UINT64_C(0x0800000000000000)
779/** FL5LP: First Level 5-level Paging Support. */
780#define VTD_BF_CAP_REG_FL5LP_SHIFT 60
781#define VTD_BF_CAP_REG_FL5LP_MASK UINT64_C(0x1000000000000000)
782/** R: Reserved (bits 63:61). */
783#define VTD_BF_CAP_REG_RSVD_63_61_SHIFT 61
784#define VTD_BF_CAP_REG_RSVD_63_61_MASK UINT64_C(0xe000000000000000)
785RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_CAP_REG_, UINT64_C(0), UINT64_MAX,
786 (ND, AFL, RWBF, PLMR, PHMR, CM, SAGAW, RSVD_15_13, MGAW, ZLR, RSVD_23, FRO, SLLPS, RSVD_38, PSI, NFR,
787 MAMV, DWD, DRD, FL1GP, RSVD_58_57, PI, FL5LP, RSVD_63_61));
788
789/** RW: Read/write mask. */
790#define VTD_CAP_REG_RW_MASK UINT64_C(0x0000000000000000)
791/** @} */
792
793
794/** @name Extended Capability Register (ECAP_REG).
795 * @{ */
796/** C: Page-walk Coherence. */
797#define VTD_BF_ECAP_REG_C_SHIFT 0
798#define VTD_BF_ECAP_REG_C_MASK UINT64_C(0x0000000000000001)
799/** QI: Queued Invalidation Support. */
800#define VTD_BF_ECAP_REG_QI_SHIFT 1
801#define VTD_BF_ECAP_REG_QI_MASK UINT64_C(0x0000000000000002)
802/** DT: Device-TLB Support. */
803#define VTD_BF_ECAP_REG_DT_SHIFT 2
804#define VTD_BF_ECAP_REG_DT_MASK UINT64_C(0x0000000000000004)
805/** IR: Interrupt Remapping Support. */
806#define VTD_BF_ECAP_REG_IR_SHIFT 3
807#define VTD_BF_ECAP_REG_IR_MASK UINT64_C(0x0000000000000008)
808/** EIM: Extended Interrupt Mode. */
809#define VTD_BF_ECAP_REG_EIM_SHIFT 4
810#define VTD_BF_ECAP_REG_EIM_MASK UINT64_C(0x0000000000000010)
811/** DEP: Deprecated MBZ. Reserved (bit 5). */
812#define VTD_BF_ECAP_REG_RSVD_5_SHIFT 5
813#define VTD_BF_ECAP_REG_RSVD_5_MASK UINT64_C(0x0000000000000020)
814/** PT: Pass Through. */
815#define VTD_BF_ECAP_REG_PT_SHIFT 6
816#define VTD_BF_ECAP_REG_PT_MASK UINT64_C(0x0000000000000040)
817/** SC: Snoop Control. */
818#define VTD_BF_ECAP_REG_SC_SHIFT 7
819#define VTD_BF_ECAP_REG_SC_MASK UINT64_C(0x0000000000000080)
820/** IRO: IOTLB Register Offset. */
821#define VTD_BF_ECAP_REG_IRO_SHIFT 8
822#define VTD_BF_ECAP_REG_IRO_MASK UINT64_C(0x000000000003ff00)
823/** R: Reserved (bits 19:18). */
824#define VTD_BF_ECAP_REG_RSVD_19_18_SHIFT 18
825#define VTD_BF_ECAP_REG_RSVD_19_18_MASK UINT64_C(0x00000000000c0000)
826/** MHMV: Maximum Handle Mask Value. */
827#define VTD_BF_ECAP_REG_MHMV_SHIFT 20
828#define VTD_BF_ECAP_REG_MHMV_MASK UINT64_C(0x0000000000f00000)
829/** DEP: Deprecated MBZ. Reserved (bit 24). */
830#define VTD_BF_ECAP_REG_RSVD_24_SHIFT 24
831#define VTD_BF_ECAP_REG_RSVD_24_MASK UINT64_C(0x0000000001000000)
832/** MTS: Memory Type Support. */
833#define VTD_BF_ECAP_REG_MTS_SHIFT 25
834#define VTD_BF_ECAP_REG_MTS_MASK UINT64_C(0x0000000002000000)
835/** NEST: Nested Translation Support. */
836#define VTD_BF_ECAP_REG_NEST_SHIFT 26
837#define VTD_BF_ECAP_REG_NEST_MASK UINT64_C(0x0000000004000000)
838/** R: Reserved (bit 27). */
839#define VTD_BF_ECAP_REG_RSVD_27_SHIFT 27
840#define VTD_BF_ECAP_REG_RSVD_27_MASK UINT64_C(0x0000000008000000)
841/** DEP: Deprecated MBZ. Reserved (bit 28). */
842#define VTD_BF_ECAP_REG_RSVD_28_SHIFT 28
843#define VTD_BF_ECAP_REG_RSVD_28_MASK UINT64_C(0x0000000010000000)
844/** PRS: Page Request Support. */
845#define VTD_BF_ECAP_REG_PRS_SHIFT 29
846#define VTD_BF_ECAP_REG_PRS_MASK UINT64_C(0x0000000020000000)
847/** ERS: Execute Request Support. */
848#define VTD_BF_ECAP_REG_ERS_SHIFT 30
849#define VTD_BF_ECAP_REG_ERS_MASK UINT64_C(0x0000000040000000)
850/** SRS: Supervisor Request Support. */
851#define VTD_BF_ECAP_REG_SRS_SHIFT 31
852#define VTD_BF_ECAP_REG_SRS_MASK UINT64_C(0x0000000080000000)
853/** R: Reserved (bit 32). */
854#define VTD_BF_ECAP_REG_RSVD_32_SHIFT 32
855#define VTD_BF_ECAP_REG_RSVD_32_MASK UINT64_C(0x0000000100000000)
856/** NWFS: No Write Flag Support. */
857#define VTD_BF_ECAP_REG_NWFS_SHIFT 33
858#define VTD_BF_ECAP_REG_NWFS_MASK UINT64_C(0x0000000200000000)
859/** EAFS: Extended Accessed Flags Support. */
860#define VTD_BF_ECAP_REG_EAFS_SHIFT 34
861#define VTD_BF_ECAP_REG_EAFS_MASK UINT64_C(0x0000000400000000)
862/** PSS: PASID Size Supported. */
863#define VTD_BF_ECAP_REG_PSS_SHIFT 35
864#define VTD_BF_ECAP_REG_PSS_MASK UINT64_C(0x000000f800000000)
865/** PASID: Process Address Space ID Support. */
866#define VTD_BF_ECAP_REG_PASID_SHIFT 40
867#define VTD_BF_ECAP_REG_PASID_MASK UINT64_C(0x0000010000000000)
868/** DIT: Device-TLB Invalidation Throttle. */
869#define VTD_BF_ECAP_REG_DIT_SHIFT 41
870#define VTD_BF_ECAP_REG_DIT_MASK UINT64_C(0x0000020000000000)
871/** PDS: Page-request Drain Support. */
872#define VTD_BF_ECAP_REG_PDS_SHIFT 42
873#define VTD_BF_ECAP_REG_PDS_MASK UINT64_C(0x0000040000000000)
874/** SMTS: Scalable-Mode Translation Support. */
875#define VTD_BF_ECAP_REG_SMTS_SHIFT 43
876#define VTD_BF_ECAP_REG_SMTS_MASK UINT64_C(0x0000080000000000)
877/** VCS: Virtual Command Support. */
878#define VTD_BF_ECAP_REG_VCS_SHIFT 44
879#define VTD_BF_ECAP_REG_VCS_MASK UINT64_C(0x0000100000000000)
880/** SLADS: Second-Level Accessed/Dirty Support. */
881#define VTD_BF_ECAP_REG_SLADS_SHIFT 45
882#define VTD_BF_ECAP_REG_SLADS_MASK UINT64_C(0x0000200000000000)
883/** SLTS: Second-Level Translation Support. */
884#define VTD_BF_ECAP_REG_SLTS_SHIFT 46
885#define VTD_BF_ECAP_REG_SLTS_MASK UINT64_C(0x0000400000000000)
886/** FLTS: First-Level Translation Support. */
887#define VTD_BF_ECAP_REG_FLTS_SHIFT 47
888#define VTD_BF_ECAP_REG_FLTS_MASK UINT64_C(0x0000800000000000)
889/** SMPWCS: Scalable-Mode Page-Walk Coherency Support. */
890#define VTD_BF_ECAP_REG_SMPWCS_SHIFT 48
891#define VTD_BF_ECAP_REG_SMPWCS_MASK UINT64_C(0x0001000000000000)
892/** RPS: RID-PASID Support. */
893#define VTD_BF_ECAP_REG_RPS_SHIFT 49
894#define VTD_BF_ECAP_REG_RPS_MASK UINT64_C(0x0002000000000000)
895/** R: Reserved (bits 63:50). */
896#define VTD_BF_ECAP_REG_RSVD_63_50_SHIFT 50
897#define VTD_BF_ECAP_REG_RSVD_63_50_MASK UINT64_C(0xfffc000000000000)
898RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_ECAP_REG_, UINT64_C(0), UINT64_MAX,
899 (C, QI, DT, IR, EIM, RSVD_5, PT, SC, IRO, RSVD_19_18, MHMV, RSVD_24, MTS, NEST, RSVD_27, RSVD_28,
900 PRS, ERS, SRS, RSVD_32, NWFS, EAFS, PSS, PASID, DIT, PDS, SMTS, VCS, SLADS, SLTS, FLTS, SMPWCS, RPS,
901 RSVD_63_50));
902
903/** RW: Read/write mask. */
904#define VTD_ECAP_REG_RW_MASK UINT64_C(0x0000000000000000)
905/** @} */
906
907
908/** @name Global Command Register (GCMD_REG).
909 * @{ */
910/** R: Reserved (bits 22:0). */
911#define VTD_BF_GCMD_REG_RSVD_22_0_SHIFT 0
912#define VTD_BF_GCMD_REG_RSVD_22_0_MASK UINT32_C(0x007fffff)
913/** CFI: Compatibility Format Interrupt. */
914#define VTD_BF_GCMD_REG_CFI_SHIFT 23
915#define VTD_BF_GCMD_REG_CFI_MASK UINT32_C(0x00800000)
916/** SIRTP: Set Interrupt Table Remap Pointer. */
917#define VTD_BF_GCMD_REG_SIRTP_SHIFT 24
918#define VTD_BF_GCMD_REG_SIRTP_MASK UINT32_C(0x01000000)
919/** IRE: Interrupt Remap Enable. */
920#define VTD_BF_GCMD_REG_IRE_SHIFT 25
921#define VTD_BF_GCMD_REG_IRE_MASK UINT32_C(0x02000000)
922/** QIE: Queued Invalidation Enable. */
923#define VTD_BF_GCMD_REG_QIE_SHIFT 26
924#define VTD_BF_GCMD_REG_QIE_MASK UINT32_C(0x04000000)
925/** WBF: Write Buffer Flush. */
926#define VTD_BF_GCMD_REG_WBF_SHIFT 27
927#define VTD_BF_GCMD_REG_WBF_MASK UINT32_C(0x08000000)
928/** EAFL: Enable Advance Fault Logging. */
929#define VTD_BF_GCMD_REG_EAFL_SHIFT 28
930#define VTD_BF_GCMD_REG_EAFL_MASK UINT32_C(0x10000000)
931/** SFL: Set Fault Log. */
932#define VTD_BF_GCMD_REG_SFL_SHIFT 29
933#define VTD_BF_GCMD_REG_SFL_MASK UINT32_C(0x20000000)
934/** SRTP: Set Root Table Pointer. */
935#define VTD_BF_GCMD_REG_SRTP_SHIFT 30
936#define VTD_BF_GCMD_REG_SRTP_MASK UINT32_C(0x40000000)
937/** TE: Translation Enable. */
938#define VTD_BF_GCMD_REG_TE_SHIFT 31
939#define VTD_BF_GCMD_REG_TE_MASK UINT32_C(0x80000000)
940RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_GCMD_REG_, UINT32_C(0), UINT32_MAX,
941 (RSVD_22_0, CFI, SIRTP, IRE, QIE, WBF, EAFL, SFL, SRTP, TE));
942
943/** RW: Read/write mask. */
944#define VTD_GCMD_REG_RW_MASK UINT32_C(0xff800000)
945/** @} */
946
947
948/** @name Global Status Register (GSTS_REG).
949 * @{ */
950/** R: Reserved (bits 22:0). */
951#define VTD_BF_GSTS_REG_RSVD_22_0_SHIFT 0
952#define VTD_BF_GSTS_REG_RSVD_22_0_MASK UINT32_C(0x007fffff)
953/** CFIS: Compatibility Format Interrupt Status. */
954#define VTD_BF_GSTS_REG_CFIS_SHIFT 23
955#define VTD_BF_GSTS_REG_CFIS_MASK UINT32_C(0x00800000)
956/** IRTPS: Interrupt Remapping Table Pointer Status. */
957#define VTD_BF_GSTS_REG_IRTPS_SHIFT 24
958#define VTD_BF_GSTS_REG_IRTPS_MASK UINT32_C(0x01000000)
959/** IRES: Interrupt Remapping Enable Status. */
960#define VTD_BF_GSTS_REG_IRES_SHIFT 25
961#define VTD_BF_GSTS_REG_IRES_MASK UINT32_C(0x02000000)
962/** QIES: Queued Invalidation Enable Status. */
963#define VTD_BF_GSTS_REG_QIES_SHIFT 26
964#define VTD_BF_GSTS_REG_QIES_MASK UINT32_C(0x04000000)
965/** WBFS: Write Buffer Flush Status. */
966#define VTD_BF_GSTS_REG_WBFS_SHIFT 27
967#define VTD_BF_GSTS_REG_WBFS_MASK UINT32_C(0x08000000)
968/** AFLS: Advanced Fault Logging Status. */
969#define VTD_BF_GSTS_REG_AFLS_SHIFT 28
970#define VTD_BF_GSTS_REG_AFLS_MASK UINT32_C(0x10000000)
971/** FLS: Fault Log Status. */
972#define VTD_BF_GSTS_REG_FLS_SHIFT 29
973#define VTD_BF_GSTS_REG_FLS_MASK UINT32_C(0x20000000)
974/** RTPS: Root Table Pointer Status. */
975#define VTD_BF_GSTS_REG_RTPS_SHIFT 30
976#define VTD_BF_GSTS_REG_RTPS_MASK UINT32_C(0x40000000)
977/** TES: Translation Enable Status. */
978#define VTD_BF_GSTS_REG_TES_SHIFT 31
979#define VTD_BF_GSTS_REG_TES_MASK UINT32_C(0x80000000)
980RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_GSTS_REG_, UINT32_C(0), UINT32_MAX,
981 (RSVD_22_0, CFIS, IRTPS, IRES, QIES, WBFS, AFLS, FLS, RTPS, TES));
982
983/** RW: Read/write mask. */
984#define VTD_GSTS_REG_RW_MASK UINT32_C(0)
985/** @} */
986
987
988/** @name Root Table Address Register (RTADDR_REG).
989 * @{ */
990/** R: Reserved (bits 9:0). */
991#define VTD_BF_RTADDR_REG_RSVD_9_0_SHIFT 0
992#define VTD_BF_RTADDR_REG_RSVD_9_0_MASK UINT64_C(0x00000000000003ff)
993/** TTM: Translation Table Mode. */
994#define VTD_BF_RTADDR_REG_TTM_SHIFT 10
995#define VTD_BF_RTADDR_REG_TTM_MASK UINT64_C(0x0000000000000c00)
996/** RTA: Root Table Address. */
997#define VTD_BF_RTADDR_REG_RTA_SHIFT 12
998#define VTD_BF_RTADDR_REG_RTA_MASK UINT64_C(0xfffffffffffff000)
999RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_RTADDR_REG_, UINT64_C(0), UINT64_MAX,
1000 (RSVD_9_0, TTM, RTA));
1001
1002/** RW: Read/write mask. */
1003#define VTD_RTADDR_REG_RW_MASK UINT64_C(0xfffffffffffffc00)
1004/** @} */
1005
1006
1007/** @name Context Command Register (CCMD_REG).
1008 * @{ */
1009/** DID: Domain-ID. */
1010#define VTD_BF_CCMD_REG_DID_SHIFT 0
1011#define VTD_BF_CCMD_REG_DID_MASK UINT64_C(0x000000000000ffff)
1012/** SID: Source-ID. */
1013#define VTD_BF_CCMD_REG_SID_SHIFT 16
1014#define VTD_BF_CCMD_REG_SID_MASK UINT64_C(0x00000000ffff0000)
1015/** FM: Function Mask. */
1016#define VTD_BF_CCMD_REG_FM_SHIFT 32
1017#define VTD_BF_CCMD_REG_FM_MASK UINT64_C(0x0000000300000000)
1018/** R: Reserved (bits 58:34). */
1019#define VTD_BF_CCMD_REG_RSVD_58_34_SHIFT 34
1020#define VTD_BF_CCMD_REG_RSVD_58_34_MASK UINT64_C(0x07fffffc00000000)
1021/** CAIG: Context Actual Invalidation Granularity. */
1022#define VTD_BF_CCMD_REG_CAIG_SHIFT 59
1023#define VTD_BF_CCMD_REG_CAIG_MASK UINT64_C(0x1800000000000000)
1024/** CIRG: Context Invalidation Request Granularity. */
1025#define VTD_BF_CCMD_REG_CIRG_SHIFT 61
1026#define VTD_BF_CCMD_REG_CIRG_MASK UINT64_C(0x6000000000000000)
1027/** ICC: Invalidation Context Cache. */
1028#define VTD_BF_CCMD_REG_ICC_SHIFT 63
1029#define VTD_BF_CCMD_REG_ICC_MASK UINT64_C(0x8000000000000000)
1030RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_CCMD_REG_, UINT64_C(0), UINT64_MAX,
1031 (DID, SID, FM, RSVD_58_34, CAIG, CIRG, ICC));
1032
1033/** RW: Read/write mask. */
1034#define VTD_CCMD_REG_RW_MASK ( VTD_BF_CCMD_REG_DID_MASK | VTD_BF_CCMD_REG_SID_MASK \
1035 | VTD_BF_CCMD_REG_FM_MASK | VTD_BF_CCMD_REG_CIRG_MASK \
1036 | VTD_BF_CCMD_REG_ICC_MASK)
1037/** @} */
1038
1039
1040/** @name IOTLB Invalidation Register (IOTLB_REG).
1041 * @{ */
1042/** R: Reserved (bits 31:0). */
1043#define VTD_BF_IOTLB_REG_RSVD_31_0_SHIFT 0
1044#define VTD_BF_IOTLB_REG_RSVD_31_0_MASK UINT64_C(0x00000000ffffffff)
1045/** DID: Domain-ID. */
1046#define VTD_BF_IOTLB_REG_DID_SHIFT 32
1047#define VTD_BF_IOTLB_REG_DID_MASK UINT64_C(0x0000ffff00000000)
1048/** DW: Draining Writes. */
1049#define VTD_BF_IOTLB_REG_DW_SHIFT 48
1050#define VTD_BF_IOTLB_REG_DW_MASK UINT64_C(0x0001000000000000)
1051/** DR: Draining Reads. */
1052#define VTD_BF_IOTLB_REG_DR_SHIFT 49
1053#define VTD_BF_IOTLB_REG_DR_MASK UINT64_C(0x0002000000000000)
1054/** R: Reserved (bits 56:50). */
1055#define VTD_BF_IOTLB_REG_RSVD_56_50_SHIFT 50
1056#define VTD_BF_IOTLB_REG_RSVD_56_50_MASK UINT64_C(0x01fc000000000000)
1057/** IAIG: IOTLB Actual Invalidation Granularity. */
1058#define VTD_BF_IOTLB_REG_IAIG_SHIFT 57
1059#define VTD_BF_IOTLB_REG_IAIG_MASK UINT64_C(0x0600000000000000)
1060/** R: Reserved (bit 59). */
1061#define VTD_BF_IOTLB_REG_RSVD_59_SHIFT 59
1062#define VTD_BF_IOTLB_REG_RSVD_59_MASK UINT64_C(0x0800000000000000)
1063/** IIRG: IOTLB Invalidation Request Granularity. */
1064#define VTD_BF_IOTLB_REG_IIRG_SHIFT 60
1065#define VTD_BF_IOTLB_REG_IIRG_MASK UINT64_C(0x3000000000000000)
1066/** R: Reserved (bit 62). */
1067#define VTD_BF_IOTLB_REG_RSVD_62_SHIFT 62
1068#define VTD_BF_IOTLB_REG_RSVD_62_MASK UINT64_C(0x4000000000000000)
1069/** IVT: Invalidate IOTLB. */
1070#define VTD_BF_IOTLB_REG_IVT_SHIFT 63
1071#define VTD_BF_IOTLB_REG_IVT_MASK UINT64_C(0x8000000000000000)
1072RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IOTLB_REG_, UINT64_C(0), UINT64_MAX,
1073 (RSVD_31_0, DID, DW, DR, RSVD_56_50, IAIG, RSVD_59, IIRG, RSVD_62, IVT));
1074/** @} */
1075
1076
1077/** @name Invalidate Address Register (IVA_REG).
1078 * @{ */
1079/** AM: Address Mask. */
1080#define VTD_BF_IVA_REG_AM_SHIFT 0
1081#define VTD_BF_IVA_REG_AM_MASK UINT64_C(0x000000000000003f)
1082/** IH: Invalidation Hint. */
1083#define VTD_BF_IVA_REG_IH_SHIFT 6
1084#define VTD_BF_IVA_REG_IH_MASK UINT64_C(0x0000000000000040)
1085/** R: Reserved (bits 11:7). */
1086#define VTD_BF_IVA_REG_RSVD_11_7_SHIFT 7
1087#define VTD_BF_IVA_REG_RSVD_11_7_MASK UINT64_C(0x0000000000000f80)
1088/** ADDR: Address. */
1089#define VTD_BF_IVA_REG_ADDR_SHIFT 12
1090#define VTD_BF_IVA_REG_ADDR_MASK UINT64_C(0xfffffffffffff000)
1091RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IVA_REG_, UINT64_C(0), UINT64_MAX,
1092 (AM, IH, RSVD_11_7, ADDR));
1093/** @} */
1094
1095
1096/** @name Fault Status Register (FSTS_REG).
1097 * @{ */
1098/** PFO: Primary Fault Overflow. */
1099#define VTD_BF_FSTS_REG_PFO_SHIFT 0
1100#define VTD_BF_FSTS_REG_PFO_MASK UINT32_C(0x00000001)
1101/** PPF: Primary Pending Fault. */
1102#define VTD_BF_FSTS_REG_PPF_SHIFT 1
1103#define VTD_BF_FSTS_REG_PPF_MASK UINT32_C(0x00000002)
1104/** AFO: Advanced Fault Overflow. */
1105#define VTD_BF_FSTS_REG_AFO_SHIFT 2
1106#define VTD_BF_FSTS_REG_AFO_MASK UINT32_C(0x00000004)
1107/** APF: Advanced Pending Fault. */
1108#define VTD_BF_FSTS_REG_APF_SHIFT 3
1109#define VTD_BF_FSTS_REG_APF_MASK UINT32_C(0x00000008)
1110/** IQE: Invalidation Queue Error. */
1111#define VTD_BF_FSTS_REG_IQE_SHIFT 4
1112#define VTD_BF_FSTS_REG_IQE_MASK UINT32_C(0x00000010)
1113/** ICE: Invalidation Completion Error. */
1114#define VTD_BF_FSTS_REG_ICE_SHIFT 5
1115#define VTD_BF_FSTS_REG_ICE_MASK UINT32_C(0x00000020)
1116/** ITE: Invalidation Timeout Error. */
1117#define VTD_BF_FSTS_REG_ITE_SHIFT 6
1118#define VTD_BF_FSTS_REG_ITE_MASK UINT32_C(0x00000040)
1119/** DEP: Deprecated MBZ. Reserved (bit 7). */
1120#define VTD_BF_FSTS_REG_RSVD_7_SHIFT 7
1121#define VTD_BF_FSTS_REG_RSVD_7_MASK UINT32_C(0x00000080)
1122/** FRI: Fault Record Index. */
1123#define VTD_BF_FSTS_REG_FRI_SHIFT 8
1124#define VTD_BF_FSTS_REG_FRI_MASK UINT32_C(0x0000ff00)
1125/** R: Reserved (bits 31:16). */
1126#define VTD_BF_FSTS_REG_RSVD_31_16_SHIFT 16
1127#define VTD_BF_FSTS_REG_RSVD_31_16_MASK UINT32_C(0xffff0000)
1128RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_FSTS_REG_, UINT32_C(0), UINT32_MAX,
1129 (PFO, PPF, AFO, APF, IQE, ICE, ITE, RSVD_7, FRI, RSVD_31_16));
1130
1131/** RW: Read/write mask. */
1132#define VTD_FSTS_REG_RW_MASK ( VTD_BF_FSTS_REG_PFO_MASK | VTD_BF_FSTS_REG_AFO_MASK \
1133 | VTD_BF_FSTS_REG_APF_MASK | VTD_BF_FSTS_REG_IQE_MASK \
1134 | VTD_BF_FSTS_REG_ICE_MASK | VTD_BF_FSTS_REG_ITE_MASK)
1135/** @} */
1136
1137
1138/** @name Fault Event Control Register (FECTL_REG).
1139 * @{ */
1140/** R: Reserved (bits 29:0). */
1141#define VTD_BF_FECTL_REG_RSVD_29_0_SHIFT 0
1142#define VTD_BF_FECTL_REG_RSVD_29_0_MASK UINT32_C(0x3fffffff)
1143/** IP: Interrupt Pending. */
1144#define VTD_BF_FECTL_REG_IP_SHIFT 30
1145#define VTD_BF_FECTL_REG_IP_MASK UINT32_C(0x40000000)
1146/** IM: Interrupt Mask. */
1147#define VTD_BF_FECTL_REG_IM_SHIFT 31
1148#define VTD_BF_FECTL_REG_IM_MASK UINT32_C(0x80000000)
1149RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_FECTL_REG_, UINT32_C(0), UINT32_MAX,
1150 (RSVD_29_0, IP, IM));
1151
1152/** RW: Read/write mask. */
1153#define VTD_FECTL_REG_RW_MASK VTD_BF_FECTL_REG_IM_MASK
1154/** @} */
1155
1156
1157/** @name Fault Event Data Register (FEDATA_REG).
1158 * @{ */
1159/** IMD: Interrupt Message Data. */
1160#define VTD_BF_FEDATA_REG_IMD_SHIFT 0
1161#define VTD_BF_FEDATA_REG_IMD_MASK UINT32_C(0x0000ffff)
1162/** EIMD: Extended Interrupt Message Data. */
1163#define VTD_BF_FEDATA_REG_EIMD_SHIFT 16
1164#define VTD_BF_FEDATA_REG_EIMD_MASK UINT32_C(0xffff0000)
1165RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_FEDATA_REG_, UINT32_C(0), UINT32_MAX,
1166 (IMD, EIMD));
1167
1168/** RW: Read/write mask. */
1169#define VTD_FEDATA_REG_RW_MASK (VTD_BF_FEDATA_REG_IMD_MASK | VTD_BF_FEDATA_REG_EIMD_MASK)
1170/** @} */
1171
1172
1173/** @name Fault Event Address Register (FEADDR_REG).
1174 * @{ */
1175/** R: Reserved (bits 1:0). */
1176#define VTD_BF_FEADDR_REG_RSVD_1_0_SHIFT 0
1177#define VTD_BF_FEADDR_REG_RSVD_1_0_MASK UINT32_C(0x00000003)
1178/** MA: Message Address. */
1179#define VTD_BF_FEADDR_REG_MA_SHIFT 2
1180#define VTD_BF_FEADDR_REG_MA_MASK UINT32_C(0xfffffffc)
1181RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_FEADDR_REG_, UINT32_C(0), UINT32_MAX,
1182 (RSVD_1_0, MA));
1183
1184/** RW: Read/write mask. */
1185#define VTD_FEADDR_REG_RW_MASK VTD_BF_FEADDR_REG_MA_MASK
1186/** @} */
1187
1188
1189/** @name Fault Event Upper Address Register (FEUADDR_REG).
1190 * @{ */
1191/** MUA: Message Upper Address. */
1192#define VTD_BF_FEUADDR_REG_MA_SHIFT 0
1193#define VTD_BF_FEUADDR_REG_MA_MASK UINT32_C(0xffffffff)
1194
1195/** RW: Read/write mask. */
1196#define VTD_FEUADDR_REG_RW_MASK VTD_BF_FEUADDR_REG_MA_MASK
1197/** @} */
1198
1199
1200/** @name Fault Recording Register (FRCD_REG).
1201 * @{ */
1202/** R: Reserved (bits 11:0). */
1203#define VTD_BF_0_FRCD_REG_RSVD_11_0_SHIFT 0
1204#define VTD_BF_0_FRCD_REG_RSVD_11_0_MASK UINT64_C(0x0000000000000fff)
1205/** FI: Fault Info. */
1206#define VTD_BF_0_FRCD_REG_FI_SHIFT 12
1207#define VTD_BF_0_FRCD_REG_FI_MASK UINT64_C(0xfffffffffffff000)
1208RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_FRCD_REG_, UINT64_C(0), UINT64_MAX,
1209 (RSVD_11_0, FI));
1210
1211/** SID: Source Identifier. */
1212#define VTD_BF_1_FRCD_REG_SID_SHIFT 0
1213#define VTD_BF_1_FRCD_REG_SID_MASK UINT64_C(0x000000000000ffff)
1214/** R: Reserved (bits 27:16). */
1215#define VTD_BF_1_FRCD_REG_RSVD_27_16_SHIFT 16
1216#define VTD_BF_1_FRCD_REG_RSVD_27_16_MASK UINT64_C(0x000000000fff0000)
1217/** T2: Type bit 2. */
1218#define VTD_BF_1_FRCD_REG_T2_SHIFT 28
1219#define VTD_BF_1_FRCD_REG_T2_MASK UINT64_C(0x0000000010000000)
1220/** PRIV: Privilege Mode. */
1221#define VTD_BF_1_FRCD_REG_PRIV_SHIFT 29
1222#define VTD_BF_1_FRCD_REG_PRIV_MASK UINT64_C(0x0000000020000000)
1223/** EXE: Execute Permission Requested. */
1224#define VTD_BF_1_FRCD_REG_EXE_SHIFT 30
1225#define VTD_BF_1_FRCD_REG_EXE_MASK UINT64_C(0x0000000040000000)
1226/** PP: PASID Present. */
1227#define VTD_BF_1_FRCD_REG_PP_SHIFT 31
1228#define VTD_BF_1_FRCD_REG_PP_MASK UINT64_C(0x0000000080000000)
1229/** FR: Fault Reason. */
1230#define VTD_BF_1_FRCD_REG_FR_SHIFT 32
1231#define VTD_BF_1_FRCD_REG_FR_MASK UINT64_C(0x000000ff00000000)
1232/** PV: PASID Value. */
1233#define VTD_BF_1_FRCD_REG_PV_SHIFT 40
1234#define VTD_BF_1_FRCD_REG_PV_MASK UINT64_C(0x0fffff0000000000)
1235/** AT: Address Type. */
1236#define VTD_BF_1_FRCD_REG_AT_SHIFT 60
1237#define VTD_BF_1_FRCD_REG_AT_MASK UINT64_C(0x3000000000000000)
1238/** T1: Type bit 1. */
1239#define VTD_BF_1_FRCD_REG_T1_SHIFT 62
1240#define VTD_BF_1_FRCD_REG_T1_MASK UINT64_C(0x4000000000000000)
1241/** F: Fault. */
1242#define VTD_BF_1_FRCD_REG_F_SHIFT 63
1243#define VTD_BF_1_FRCD_REG_F_MASK UINT64_C(0x8000000000000000)
1244RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_FRCD_REG_, UINT64_C(0), UINT64_MAX,
1245 (SID, RSVD_27_16, T2, PRIV, EXE, PP, FR, PV, AT, T1, F));
1246/** @} */
1247
1248
1249/** @name Advanced Fault Log Register (AFLOG_REG).
1250 * @{ */
1251/** R: Reserved (bits 8:0). */
1252#define VTD_BF_0_AFLOG_REG_RSVD_8_0_SHIFT 0
1253#define VTD_BF_0_AFLOG_REG_RSVD_8_0_MASK UINT64_C(0x00000000000001ff)
1254/** FLS: Fault Log Size. */
1255#define VTD_BF_0_AFLOG_REG_FLS_SHIFT 9
1256#define VTD_BF_0_AFLOG_REG_FLS_MASK UINT64_C(0x0000000000000e00)
1257/** FLA: Fault Log Address. */
1258#define VTD_BF_0_AFLOG_REG_FLA_SHIFT 12
1259#define VTD_BF_0_AFLOG_REG_FLA_MASK UINT64_C(0xfffffffffffff000)
1260RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_AFLOG_REG_, UINT64_C(0), UINT64_MAX,
1261 (RSVD_8_0, FLS, FLA));
1262
1263/** RW: Read/write mask. */
1264#define VTD_AFLOG_REG_RW_MASK (VTD_BF_0_AFLOG_REG_FLS_MASK | VTD_BF_0_AFLOG_REG_FLA_MASK)
1265/** @} */
1266
1267
1268/** @name Protected Memory Enable Register (PMEN_REG).
1269 * @{ */
1270/** PRS: Protected Region Status. */
1271#define VTD_BF_PMEN_REG_PRS_SHIFT 0
1272#define VTD_BF_PMEN_REG_PRS_MASK UINT32_C(0x00000001)
1273/** R: Reserved (bits 30:1). */
1274#define VTD_BF_PMEN_REG_RSVD_30_1_SHIFT 1
1275#define VTD_BF_PMEN_REG_RSVD_30_1_MASK UINT32_C(0x7ffffffe)
1276/** EPM: Enable Protected Memory. */
1277#define VTD_BF_PMEN_REG_EPM_SHIFT 31
1278#define VTD_BF_PMEN_REG_EPM_MASK UINT32_C(0x80000000)
1279RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_PMEN_REG_, UINT32_C(0), UINT32_MAX,
1280 (PRS, RSVD_30_1, EPM));
1281
1282/** RW: Read/write mask. */
1283#define VTD_PMEN_REG_RW_MASK VTD_BF_PMEN_REG_EPM_MASK
1284/** @} */
1285
1286
1287/** @name Invalidation Queue Head Register (IQH_REG).
1288 * @{ */
1289/** R: Reserved (bits 3:0). */
1290#define VTD_BF_IQH_REG_RSVD_3_0_SHIFT 0
1291#define VTD_BF_IQH_REG_RSVD_3_0_MASK UINT64_C(0x000000000000000f)
1292/** QH: Queue Head. */
1293#define VTD_BF_IQH_REG_QH_SHIFT 4
1294#define VTD_BF_IQH_REG_QH_MASK UINT64_C(0x000000000007fff0)
1295/** R: Reserved (bits 63:19). */
1296#define VTD_BF_IQH_REG_RSVD_63_19_SHIFT 19
1297#define VTD_BF_IQH_REG_RSVD_63_19_MASK UINT64_C(0xfffffffffff80000)
1298RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IQH_REG_, UINT64_C(0), UINT64_MAX,
1299 (RSVD_3_0, QH, RSVD_63_19));
1300
1301/** RW: Read/write mask. */
1302#define VTD_IQH_REG_RW_MASK UINT64_C(0x0)
1303/** @} */
1304
1305
1306/** @name Invalidation Queue Tail Register (IQT_REG).
1307 * @{ */
1308/** R: Reserved (bits 3:0). */
1309#define VTD_BF_IQT_REG_RSVD_3_0_SHIFT 0
1310#define VTD_BF_IQT_REG_RSVD_3_0_MASK UINT64_C(0x000000000000000f)
1311/** QH: Queue Tail. */
1312#define VTD_BF_IQT_REG_QT_SHIFT 4
1313#define VTD_BF_IQT_REG_QT_MASK UINT64_C(0x000000000007fff0)
1314/** R: Reserved (bits 63:19). */
1315#define VTD_BF_IQT_REG_RSVD_63_19_SHIFT 19
1316#define VTD_BF_IQT_REG_RSVD_63_19_MASK UINT64_C(0xfffffffffff80000)
1317RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IQT_REG_, UINT64_C(0), UINT64_MAX,
1318 (RSVD_3_0, QT, RSVD_63_19));
1319
1320/** RW: Read/write mask. */
1321#define VTD_IQT_REG_RW_MASK VTD_BF_IQT_REG_QT_MASK
1322/** @} */
1323
1324
1325/** @name Invalidation Queue Address Register (IQA_REG).
1326 * @{ */
1327/** QS: Queue Size. */
1328#define VTD_BF_IQA_REG_QS_SHIFT 0
1329#define VTD_BF_IQA_REG_QS_MASK UINT64_C(0x0000000000000007)
1330/** R: Reserved (bits 10:3). */
1331#define VTD_BF_IQA_REG_RSVD_10_3_SHIFT 3
1332#define VTD_BF_IQA_REG_RSVD_10_3_MASK UINT64_C(0x00000000000007f8)
1333/** DW: Descriptor Width. */
1334#define VTD_BF_IQA_REG_DW_SHIFT 11
1335#define VTD_BF_IQA_REG_DW_MASK UINT64_C(0x0000000000000800)
1336/** IQA: Invalidation Queue Base Address. */
1337#define VTD_BF_IQA_REG_IQA_SHIFT 12
1338#define VTD_BF_IQA_REG_IQA_MASK UINT64_C(0xfffffffffffff000)
1339RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IQA_REG_, UINT64_C(0), UINT64_MAX,
1340 (QS, RSVD_10_3, DW, IQA));
1341
1342/** RW: Read/write mask. */
1343#define VTD_IQA_REG_RW_MASK ( VTD_BF_IQA_REG_QS_MASK | VTD_BF_IQA_REG_DW_MASK \
1344 | VTD_BF_IQA_REG_IQA_MASK)
1345/** @} */
1346
1347
1348/** @name Invalidation Completion Status Register (ICS_REG).
1349 * @{ */
1350/** IWC: Invalidation Wait Descriptor Complete. */
1351#define VTD_BF_ICS_REG_IWC_SHIFT 0
1352#define VTD_BF_ICS_REG_IWC_MASK UINT32_C(0x00000001)
1353/** R: Reserved (bits 31:1). */
1354#define VTD_BF_ICS_REG_RSVD_31_1_SHIFT 1
1355#define VTD_BF_ICS_REG_RSVD_31_1_MASK UINT32_C(0xfffffffe)
1356RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_ICS_REG_, UINT32_C(0), UINT32_MAX,
1357 (IWC, RSVD_31_1));
1358
1359/** RW: Read/write mask. */
1360#define VTD_ICS_REG_RW_MASK VTD_BF_ICS_REG_IWC_MASK
1361/** @} */
1362
1363
1364/** @name Invalidation Event Control Register (IECTL_REG).
1365 * @{ */
1366/** R: Reserved (bits 29:0). */
1367#define VTD_BF_IECTL_REG_RSVD_29_0_SHIFT 0
1368#define VTD_BF_IECTL_REG_RSVD_29_0_MASK UINT32_C(0x3fffffff)
1369/** IP: Interrupt Pending. */
1370#define VTD_BF_IECTL_REG_IP_SHIFT 30
1371#define VTD_BF_IECTL_REG_IP_MASK UINT32_C(0x40000000)
1372/** IM: Interrupt Mask. */
1373#define VTD_BF_IECTL_REG_IM_SHIFT 31
1374#define VTD_BF_IECTL_REG_IM_MASK UINT32_C(0x80000000)
1375RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IECTL_REG_, UINT32_C(0), UINT32_MAX,
1376 (RSVD_29_0, IP, IM));
1377
1378/** RW: Read/write mask. */
1379#define VTD_IECTL_REG_RW_MASK VTD_BF_IECTL_REG_IM_MASK
1380/** @} */
1381
1382
1383/** @name Invalidation Event Data Register (IEDATA_REG).
1384 * @{ */
1385/** IMD: Interrupt Message Data. */
1386#define VTD_BF_IEDATA_REG_IMD_SHIFT 0
1387#define VTD_BF_IEDATA_REG_IMD_MASK UINT32_C(0x0000ffff)
1388/** EIMD: Extended Interrupt Message Data. */
1389#define VTD_BF_IEDATA_REG_EIMD_SHIFT 16
1390#define VTD_BF_IEDATA_REG_EIMD_MASK UINT32_C(0xffff0000)
1391RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IEDATA_REG_, UINT32_C(0), UINT32_MAX,
1392 (IMD, EIMD));
1393
1394/** RW: Read/write mask. */
1395#define VTD_IEDATA_REG_RW_MASK (VTD_BF_IEDATA_REG_IMD_MASK | VTD_BF_IEDATA_REG_EIMD_MASK)
1396/** @} */
1397
1398
1399/** @name Invalidation Event Address Register (IEADDR_REG).
1400 * @{ */
1401/** R: Reserved (bits 1:0). */
1402#define VTD_BF_IEADDR_REG_RSVD_1_0_SHIFT 0
1403#define VTD_BF_IEADDR_REG_RSVD_1_0_MASK UINT32_C(0x00000003)
1404/** MA: Message Address. */
1405#define VTD_BF_IEADDR_REG_MA_SHIFT 2
1406#define VTD_BF_IEADDR_REG_MA_MASK UINT32_C(0xfffffffc)
1407RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IEADDR_REG_, UINT32_C(0), UINT32_MAX,
1408 (RSVD_1_0, MA));
1409
1410/** RW: Read/write mask. */
1411#define VTD_IEADDR_REG_RW_MASK VTD_BF_IEADDR_REG_MA_MASK
1412/** @} */
1413
1414
1415/** @name Invalidation Event Upper Address Register (IEUADDR_REG).
1416 * @{ */
1417/** MUA: Message Upper Address. */
1418#define VTD_BF_IEUADDR_REG_MUA_SHIFT 0
1419#define VTD_BF_IEUADDR_REG_MUA_MASK UINT32_C(0xffffffff)
1420
1421/** RW: Read/write mask. */
1422#define VTD_IEUADDR_REG_RW_MASK VTD_BF_IEUADDR_REG_MUA_MASK
1423/** @} */
1424
1425
1426/** @name Invalidation Queue Error Record Register (IQERCD_REG).
1427 * @{ */
1428/** IQEI: Invalidation Queue Error Info. */
1429#define VTD_BF_IQERCD_REG_IQEI_SHIFT 0
1430#define VTD_BF_IQERCD_REG_IQEI_MASK UINT64_C(0x000000000000000f)
1431/** R: Reserved (bits 31:4). */
1432#define VTD_BF_IQERCD_REG_RSVD_31_4_SHIFT 4
1433#define VTD_BF_IQERCD_REG_RSVD_31_4_MASK UINT64_C(0x00000000fffffff0)
1434/** ITESID: Invalidation Timeout Error Source Identifier. */
1435#define VTD_BF_IQERCD_REG_ITESID_SHIFT 32
1436#define VTD_BF_IQERCD_REG_ITESID_MASK UINT64_C(0x0000ffff00000000)
1437/** ICESID: Invalidation Completion Error Source Identifier. */
1438#define VTD_BF_IQERCD_REG_ICESID_SHIFT 48
1439#define VTD_BF_IQERCD_REG_ICESID_MASK UINT64_C(0xffff000000000000)
1440RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IQERCD_REG_, UINT64_C(0), UINT64_MAX,
1441 (IQEI, RSVD_31_4, ITESID, ICESID));
1442
1443/** RW: Read/write mask. */
1444#define VTD_IQERCD_REG_RW_MASK UINT64_C(0)
1445/** @} */
1446
1447
1448/** @name Interrupt Remapping Table Address Register (IRTA_REG).
1449 * @{ */
1450/** S: Size. */
1451#define VTD_BF_IRTA_REG_S_SHIFT 0
1452#define VTD_BF_IRTA_REG_S_MASK UINT64_C(0x000000000000000f)
1453/** R: Reserved (bits 10:4). */
1454#define VTD_BF_IRTA_REG_RSVD_10_4_SHIFT 4
1455#define VTD_BF_IRTA_REG_RSVD_10_4_MASK UINT64_C(0x00000000000007f0)
1456/** EIME: Extended Interrupt Mode Enable. */
1457#define VTD_BF_IRTA_REG_EIME_SHIFT 11
1458#define VTD_BF_IRTA_REG_EIME_MASK UINT64_C(0x0000000000000800)
1459/** IRTA: Interrupt Remapping Table Address. */
1460#define VTD_BF_IRTA_REG_IRTA_SHIFT 12
1461#define VTD_BF_IRTA_REG_IRTA_MASK UINT64_C(0xfffffffffffff000)
1462RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IRTA_REG_, UINT64_C(0), UINT64_MAX,
1463 (S, RSVD_10_4, EIME, IRTA));
1464
1465/** RW: Read/write mask. */
1466#define VTD_IRTA_REG_RW_MASK ( VTD_BF_IRTA_REG_S_MASK | VTD_BF_IRTA_REG_EIME_MASK \
1467 | VTD_BF_IRTA_REG_IRTA_MASK)
1468/** @} */
1469
1470
1471/** @name Page Request Queue Head Register (PQH_REG).
1472 * @{ */
1473/** R: Reserved (bits 4:0). */
1474#define VTD_BF_PQH_REG_RSVD_4_0_SHIFT 0
1475#define VTD_BF_PQH_REG_RSVD_4_0_MASK UINT64_C(0x000000000000001f)
1476/** PQH: Page Queue Head. */
1477#define VTD_BF_PQH_REG_PQH_SHIFT 5
1478#define VTD_BF_PQH_REG_PQH_MASK UINT64_C(0x000000000007ffe0)
1479/** R: Reserved (bits 63:19). */
1480#define VTD_BF_PQH_REG_RSVD_63_19_SHIFT 19
1481#define VTD_BF_PQH_REG_RSVD_63_19_MASK UINT64_C(0xfffffffffff80000)
1482RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_PQH_REG_, UINT64_C(0), UINT64_MAX,
1483 (RSVD_4_0, PQH, RSVD_63_19));
1484
1485/** RW: Read/write mask. */
1486#define VTD_PQH_REG_RW_MASK VTD_BF_PQH_REG_PQH_MASK
1487/** @} */
1488
1489
1490/** @name Page Request Queue Tail Register (PQT_REG).
1491 * @{ */
1492/** R: Reserved (bits 4:0). */
1493#define VTD_BF_PQT_REG_RSVD_4_0_SHIFT 0
1494#define VTD_BF_PQT_REG_RSVD_4_0_MASK UINT64_C(0x000000000000001f)
1495/** PQT: Page Queue Tail. */
1496#define VTD_BF_PQT_REG_PQT_SHIFT 5
1497#define VTD_BF_PQT_REG_PQT_MASK UINT64_C(0x000000000007ffe0)
1498/** R: Reserved (bits 63:19). */
1499#define VTD_BF_PQT_REG_RSVD_63_19_SHIFT 19
1500#define VTD_BF_PQT_REG_RSVD_63_19_MASK UINT64_C(0xfffffffffff80000)
1501RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_PQT_REG_, UINT64_C(0), UINT64_MAX,
1502 (RSVD_4_0, PQT, RSVD_63_19));
1503
1504/** RW: Read/write mask. */
1505#define VTD_PQT_REG_RW_MASK VTD_BF_PQT_REG_PQT_MASK
1506/** @} */
1507
1508
1509/** @name Page Request Queue Address Register (PQA_REG).
1510 * @{ */
1511/** PQS: Page Queue Size. */
1512#define VTD_BF_PQA_REG_PQS_SHIFT 0
1513#define VTD_BF_PQA_REG_PQS_MASK UINT64_C(0x0000000000000007)
1514/** R: Reserved bits (11:3). */
1515#define VTD_BF_PQA_REG_RSVD_11_3_SHIFT 3
1516#define VTD_BF_PQA_REG_RSVD_11_3_MASK UINT64_C(0x0000000000000ff8)
1517/** PQA: Page Request Queue Base Address. */
1518#define VTD_BF_PQA_REG_PQA_SHIFT 12
1519#define VTD_BF_PQA_REG_PQA_MASK UINT64_C(0xfffffffffffff000)
1520RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_PQA_REG_, UINT64_C(0), UINT64_MAX,
1521 (PQS, RSVD_11_3, PQA));
1522
1523/** RW: Read/write mask. */
1524#define VTD_PQA_REG_RW_MASK (VTD_BF_PQA_REG_PQS_MASK | VTD_BF_PQA_REG_PQA_MASK)
1525/** @} */
1526
1527
1528/** @name Page Request Status Register (PRS_REG).
1529 * @{ */
1530/** PPR: Pending Page Request. */
1531#define VTD_BF_PRS_REG_PPR_SHIFT 0
1532#define VTD_BF_PRS_REG_PPR_MASK UINT64_C(0x00000001)
1533/** PRO: Page Request Overflow. */
1534#define VTD_BF_PRS_REG_PRO_SHIFT 1
1535#define VTD_BF_PRS_REG_PRO_MASK UINT64_C(0x00000002)
1536/** R: Reserved (bits 31:2). */
1537#define VTD_BF_PRS_REG_RSVD_31_2_SHIFT 2
1538#define VTD_BF_PRS_REG_RSVD_31_2_MASK UINT64_C(0xfffffffc)
1539RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_PRS_REG_, UINT32_C(0), UINT32_MAX,
1540 (PPR, PRO, RSVD_31_2));
1541
1542/** RW: Read/write mask. */
1543#define VTD_PRS_REG_RW_MASK (VTD_BF_PRS_REG_PPR_MASK | VTD_BF_PRS_REG_PRO_MASK)
1544/** @} */
1545
1546
1547/** @name Page Request Event Control Register (PECTL_REG).
1548 * @{ */
1549/** R: Reserved (bits 29:0). */
1550#define VTD_BF_PECTL_REG_RSVD_29_0_SHIFT 0
1551#define VTD_BF_PECTL_REG_RSVD_29_0_MASK UINT32_C(0x3fffffff)
1552/** IP: Interrupt Pending. */
1553#define VTD_BF_PECTL_REG_IP_SHIFT 30
1554#define VTD_BF_PECTL_REG_IP_MASK UINT32_C(0x40000000)
1555/** IM: Interrupt Mask. */
1556#define VTD_BF_PECTL_REG_IM_SHIFT 31
1557#define VTD_BF_PECTL_REG_IM_MASK UINT32_C(0x80000000)
1558RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_PECTL_REG_, UINT32_C(0), UINT32_MAX,
1559 (RSVD_29_0, IP, IM));
1560
1561/** RW: Read/write mask. */
1562#define VTD_PECTL_REG_RW_MASK VTD_BF_PECTL_REG_IM_MASK
1563/** @} */
1564
1565
1566/** @name Page Request Event Data Register (PEDATA_REG).
1567 * @{ */
1568/** IMD: Interrupt Message Data. */
1569#define VTD_BF_PEDATA_REG_IMD_SHIFT 0
1570#define VTD_BF_PEDATA_REG_IMD_MASK UINT32_C(0x0000ffff)
1571/** EIMD: Extended Interrupt Message Data. */
1572#define VTD_BF_PEDATA_REG_EIMD_SHIFT 16
1573#define VTD_BF_PEDATA_REG_EIMD_MASK UINT32_C(0xffff0000)
1574RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_PEDATA_REG_, UINT32_C(0), UINT32_MAX,
1575 (IMD, EIMD));
1576
1577/** RW: Read/write mask. */
1578#define VTD_PEDATA_REG_RW_MASK (VTD_BF_PEDATA_REG_IMD_MASK | VTD_BF_PEDATA_REG_EIMD_MASK)
1579/** @} */
1580
1581
1582/** @name Page Request Event Address Register (PEADDR_REG).
1583 * @{ */
1584/** R: Reserved (bits 1:0). */
1585#define VTD_BF_PEADDR_REG_RSVD_1_0_SHIFT 0
1586#define VTD_BF_PEADDR_REG_RSVD_1_0_MASK UINT32_C(0x00000003)
1587/** MA: Message Address. */
1588#define VTD_BF_PEADDR_REG_MA_SHIFT 2
1589#define VTD_BF_PEADDR_REG_MA_MASK UINT32_C(0xfffffffc)
1590RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_PEADDR_REG_, UINT32_C(0), UINT32_MAX,
1591 (RSVD_1_0, MA));
1592
1593/** RW: Read/write mask. */
1594#define VTD_PEADDR_REG_RW_MASK VTD_BF_PEADDR_REG_MA_MASK
1595/** @} */
1596
1597
1598
1599/** @name Page Request Event Upper Address Register (PEUADDR_REG).
1600 * @{ */
1601/** MA: Message Address. */
1602#define VTD_BF_PEUADDR_REG_MUA_SHIFT 0
1603#define VTD_BF_PEUADDR_REG_MUA_MASK UINT32_C(0xffffffff)
1604
1605/** RW: Read/write mask. */
1606#define VTD_PEUADDR_REG_RW_MASK VTD_BF_PEUADDR_REG_MUA_MASK
1607/** @} */
1608
1609
1610/** @name MTRR Capability Register (MTRRCAP_REG).
1611 * @{ */
1612/** VCNT: Variable MTRR Count. */
1613#define VTD_BF_MTRRCAP_REG_VCNT_SHIFT 0
1614#define VTD_BF_MTRRCAP_REG_VCNT_MASK UINT64_C(0x00000000000000ff)
1615/** FIX: Fixed range MTRRs Supported. */
1616#define VTD_BF_MTRRCAP_REG_FIX_SHIFT 8
1617#define VTD_BF_MTRRCAP_REG_FIX_MASK UINT64_C(0x0000000000000100)
1618/** R: Reserved (bit 9). */
1619#define VTD_BF_MTRRCAP_REG_RSVD_9_SHIFT 9
1620#define VTD_BF_MTRRCAP_REG_RSVD_9_MASK UINT64_C(0x0000000000000200)
1621/** WC: Write Combining. */
1622#define VTD_BF_MTRRCAP_REG_WC_SHIFT 10
1623#define VTD_BF_MTRRCAP_REG_WC_MASK UINT64_C(0x0000000000000400)
1624/** R: Reserved (bits 63:11). */
1625#define VTD_BF_MTRRCAP_REG_RSVD_63_11_SHIFT 11
1626#define VTD_BF_MTRRCAP_REG_RSVD_63_11_MASK UINT64_C(0xfffffffffffff800)
1627RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_MTRRCAP_REG_, UINT64_C(0), UINT64_MAX,
1628 (VCNT, FIX, RSVD_9, WC, RSVD_63_11));
1629
1630/** RW: Read/write mask. */
1631#define VTD_MTRRCAP_REG_RW_MASK UINT64_C(0)
1632/** @} */
1633
1634
1635/** @name MTRR Default Type Register (MTRRDEF_REG).
1636 * @{ */
1637/** TYPE: Default Memory Type. */
1638#define VTD_BF_MTRRDEF_REG_TYPE_SHIFT 0
1639#define VTD_BF_MTRRDEF_REG_TYPE_MASK UINT64_C(0x00000000000000ff)
1640/** R: Reserved (bits 9:8). */
1641#define VTD_BF_MTRRDEF_REG_RSVD_9_8_SHIFT 8
1642#define VTD_BF_MTRRDEF_REG_RSVD_9_8_MASK UINT64_C(0x0000000000000300)
1643/** FE: Fixed Range MTRR Enable. */
1644#define VTD_BF_MTRRDEF_REG_FE_SHIFT 10
1645#define VTD_BF_MTRRDEF_REG_FE_MASK UINT64_C(0x0000000000000400)
1646/** E: MTRR Enable. */
1647#define VTD_BF_MTRRDEF_REG_E_SHIFT 11
1648#define VTD_BF_MTRRDEF_REG_E_MASK UINT64_C(0x0000000000000800)
1649/** R: Reserved (bits 63:12). */
1650#define VTD_BF_MTRRDEF_REG_RSVD_63_12_SHIFT 12
1651#define VTD_BF_MTRRDEF_REG_RSVD_63_12_MASK UINT64_C(0xfffffffffffff000)
1652RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_MTRRDEF_REG_, UINT64_C(0), UINT64_MAX,
1653 (TYPE, RSVD_9_8, FE, E, RSVD_63_12));
1654
1655/** RW: Read/write mask. */
1656#define VTD_MTRRDEF_REG_RW_MASK ( VTD_BF_MTRRDEF_REG_TYPE_MASK | VTD_BF_MTRRDEF_REG_FE_MASK \
1657 | VTD_BF_MTRRDEF_REG_E_MASK)
1658/** @} */
1659
1660
1661/** @name Virtual Command Capability Register (VCCAP_REG).
1662 * @{ */
1663/** PAS: PASID Support. */
1664#define VTD_BF_VCCAP_REG_PAS_SHIFT 0
1665#define VTD_BF_VCCAP_REG_PAS_MASK UINT64_C(0x0000000000000001)
1666/** R: Reserved (bits 63:1). */
1667#define VTD_BF_VCCAP_REG_RSVD_63_1_SHIFT 1
1668#define VTD_BF_VCCAP_REG_RSVD_63_1_MASK UINT64_C(0xfffffffffffffffe)
1669RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_VCCAP_REG_, UINT64_C(0), UINT64_MAX,
1670 (PAS, RSVD_63_1));
1671
1672/** RW: Read/write mask. */
1673#define VTD_VCCAP_REG_RW_MASK UINT64_C(0)
1674/** @} */
1675
1676
1677/** @name Virtual Command Register (VCMD_REG).
1678 * @{ */
1679/** CMD: Command. */
1680#define VTD_BF_VCMD_REG_CMD_SHIFT 0
1681#define VTD_BF_VCMD_REG_CMD_MASK UINT64_C(0x00000000000000ff)
1682/** OP: Operand. */
1683#define VTD_BF_VCMD_REG_OP_SHIFT 8
1684#define VTD_BF_VCMD_REG_OP_MASK UINT64_C(0xffffffffffffff00)
1685RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_VCMD_REG_, UINT64_C(0), UINT64_MAX,
1686 (CMD, OP));
1687
1688/** RW: Read/write mask. */
1689#define VTD_VCMD_REG_RW_MASK (VTD_BF_VCMD_REG_CMD_MASK | VTD_BF_VCMD_REG_OP_MASK)
1690/** @} */
1691
1692
1693/** @name Virtual Command Response Register (VCRSP_REG).
1694 * @{ */
1695/** IP: In Progress. */
1696#define VTD_BF_VCRSP_REG_IP_SHIFT 0
1697#define VTD_BF_VCRSP_REG_IP_MASK UINT64_C(0x0000000000000001)
1698/** SC: Status Code. */
1699#define VTD_BF_VCRSP_REG_SC_SHIFT 1
1700#define VTD_BF_VCRSP_REG_SC_MASK UINT64_C(0x0000000000000006)
1701/** R: Reserved (bits 7:3). */
1702#define VTD_BF_VCRSP_REG_RSVD_7_3_SHIFT 3
1703#define VTD_BF_VCRSP_REG_RSVD_7_3_MASK UINT64_C(0x00000000000000f8)
1704/** RSLT: Result. */
1705#define VTD_BF_VCRSP_REG_RSLT_SHIFT 8
1706#define VTD_BF_VCRSP_REG_RSLT_MASK UINT64_C(0xffffffffffffff00)
1707RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_VCRSP_REG_, UINT64_C(0), UINT64_MAX,
1708 (IP, SC, RSVD_7_3, RSLT));
1709
1710/** RW: Read/write mask. */
1711#define VTD_VCRSP_REG_RW_MASK UINT64_C(0)
1712/** @} */
1713
1714
1715#endif /* !VBOX_INCLUDED_iommu_intel_h */
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