VirtualBox

source: vbox/trunk/include/VBox/iommu-intel.h@ 88518

Last change on this file since 88518 was 88518, checked in by vboxsync, 4 years ago

Intel IOMMU: bugref:9967 WIP.
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1/** @file
2 * IOMMU - Input/Output Memory Management Unit (Intel).
3 */
4
5/*
6 * Copyright (C) 2021 Oracle Corporation
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * The contents of this file may alternatively be used under the terms
17 * of the Common Development and Distribution License Version 1.0
18 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19 * VirtualBox OSE distribution, in which case the provisions of the
20 * CDDL are applicable instead of those of the GPL.
21 *
22 * You may elect to license modified versions of this file under the
23 * terms and conditions of either the GPL or the CDDL or both.
24 */
25
26#ifndef VBOX_INCLUDED_iommu_intel_h
27#define VBOX_INCLUDED_iommu_intel_h
28#ifndef RT_WITHOUT_PRAGMA_ONCE
29# pragma once
30#endif
31
32#include <iprt/assertcompile.h>
33#include <iprt/types.h>
34
35
36/**
37 * @name MMIO register offsets.
38 * In accordance with the Intel spec.
39 * @{
40 */
41#define VTD_MMIO_OFF_VER_REG 0x000 /**< Version. */
42#define VTD_MMIO_OFF_CAP_REG 0x008 /**< Capability. */
43#define VTD_MMIO_OFF_ECAP_REG 0x010 /**< Extended Capability. */
44#define VTD_MMIO_OFF_GCMD_REG 0x018 /**< Global Command. */
45#define VTD_MMIO_OFF_GSTS_REG 0x01c /**< Global Status. */
46#define VTD_MMIO_OFF_RTADDR_REG 0x020 /**< Root Table Address. */
47#define VTD_MMIO_OFF_CCMD_REG 0x028 /**< Context Command. */
48
49#define VTD_MMIO_OFF_FSTS_REG 0x034 /**< Fault Status.*/
50#define VTD_MMIO_OFF_FECTL_REG 0x038 /**< Fault Event Control.*/
51#define VTD_MMIO_OFF_FEDATA_REG 0x03c /**< Fault Event Data. */
52#define VTD_MMIO_OFF_FEADDR_REG 0x040 /**< Fault Event Address. */
53#define VTD_MMIO_OFF_FEUADDR_REG 0x044 /**< Fault Event Upper Address. */
54
55#define VTD_MMIO_OFF_AFLOG_REG 0x058 /**< Advance Fault Log. */
56
57#define VTD_MMIO_OFF_PMEN_REG 0x064 /**< Protected Memory Enable (PMEN). */
58#define VTD_MMIO_OFF_PLMBASE_REG 0x068 /**< Protected Low Memory Base. */
59#define VTD_MMIO_OFF_PLMLIMIT_REG 0x06c /**< Protected Low Memory Limit. */
60#define VTD_MMIO_OFF_PHMBASE_REG 0x070 /**< Protected High Memory Base. */
61#define VTD_MMIO_OFF_PHMLIMIT_REG 0x078 /**< Protected High Memory Limit. */
62
63#define VTD_MMIO_OFF_IQH_REG 0x080 /**< Invalidation Queue Head. */
64#define VTD_MMIO_OFF_IQT_REG 0x088 /**< Invalidation Queue Tail. */
65#define VTD_MMIO_OFF_IQA_REG 0x090 /**< Invalidation Queue Address. */
66#define VTD_MMIO_OFF_ICS_REG 0x09c /**< Invalidation Completion Status. */
67#define VTD_MMIO_OFF_IECTL_REG 0x0a0 /**< Invalidation Completion Event Control. */
68#define VTD_MMIO_OFF_IEDATA_REG 0x0a4 /**< Invalidation Completion Event Data. */
69#define VTD_MMIO_OFF_IEADDR_REG 0x0a8 /**< Invalidation Completion Event Address. */
70#define VTD_MMIO_OFF_IEUADDR_REG 0x0ac /**< Invalidation Completion Event Upper Address. */
71#define VTD_MMIO_OFF_IQERCD_REG 0x0b0 /**< Invalidation Queue Error Record. */
72
73#define VTD_MMIO_OFF_IRTA_REG 0x0b8 /**< Interrupt Remapping Table Address. */
74
75#define VTD_MMIO_OFF_PQH_REG 0x0c0 /**< Page Request Queue Head. */
76#define VTD_MMIO_OFF_PQT_REG 0x0c8 /**< Page Request Queue Tail. */
77#define VTD_MMIO_OFF_PQA_REG 0x0d0 /**< Page Request Queue Address. */
78#define VTD_MMIO_OFF_PRS_REG 0x0dc /**< Page Request Status. */
79#define VTD_MMIO_OFF_PECTL_REG 0x0e0 /**< Page Request Event Control. */
80#define VTD_MMIO_OFF_PEDATA_REG 0x0e4 /**< Page Request Event Data. */
81#define VTD_MMIO_OFF_PEADDR_REG 0x0e8 /**< Page Request Event Address. */
82#define VTD_MMIO_OFF_PEUADDR_REG 0x0ec /**< Page Request Event Upper Address. */
83
84#define VTD_MMIO_OFF_MTRRCAP_REG 0x100 /**< MTRR Capabliity. */
85#define VTD_MMIO_OFF_MTRRDEF_REG 0x108 /**< MTRR Default Type. */
86
87#define VTD_MMIO_OFF_MTRR_FIX64_00000_REG 0x120 /**< Fixed-range MTRR Register for 64K at 00000. */
88#define VTD_MMIO_OFF_MTRR_FIX16K_80000_REG 0x128 /**< Fixed-range MTRR Register for 16K at 80000. */
89#define VTD_MMIO_OFF_MTRR_FIX16K_A0000_REG 0x130 /**< Fixed-range MTRR Register for 16K at a0000. */
90#define VTD_MMIO_OFF_MTRR_FIX4K_C0000_REG 0x138 /**< Fixed-range MTRR Register for 4K at c0000. */
91#define VTD_MMIO_OFF_MTRR_FIX4K_C8000_REG 0x140 /**< Fixed-range MTRR Register for 4K at c8000. */
92#define VTD_MMIO_OFF_MTRR_FIX4K_D0000_REG 0x148 /**< Fixed-range MTRR Register for 4K at d0000. */
93#define VTD_MMIO_OFF_MTRR_FIX4K_D8000_REG 0x150 /**< Fixed-range MTRR Register for 4K at d8000. */
94#define VTD_MMIO_OFF_MTRR_FIX4K_E0000_REG 0x158 /**< Fixed-range MTRR Register for 4K at e0000. */
95#define VTD_MMIO_OFF_MTRR_FIX4K_E8000_REG 0x160 /**< Fixed-range MTRR Register for 4K at e8000. */
96#define VTD_MMIO_OFF_MTRR_FIX4K_F0000_REG 0x168 /**< Fixed-range MTRR Register for 4K at f0000. */
97#define VTD_MMIO_OFF_MTRR_FIX4K_F8000_REG 0x170 /**< Fixed-range MTRR Register for 4K at f8000. */
98
99#define VTD_MMIO_OFF_MTRR_PHYSBASE0_REG 0x180 /**< Variable-range MTRR Base 0. */
100#define VTD_MMIO_OFF_MTRR_PHYSMASK0_REG 0x188 /**< Variable-range MTRR Mask 0. */
101#define VTD_MMIO_OFF_MTRR_PHYSBASE1_REG 0x190 /**< Variable-range MTRR Base 1. */
102#define VTD_MMIO_OFF_MTRR_PHYSMASK1_REG 0x198 /**< Variable-range MTRR Mask 1. */
103#define VTD_MMIO_OFF_MTRR_PHYSBASE2_REG 0x1a0 /**< Variable-range MTRR Base 2. */
104#define VTD_MMIO_OFF_MTRR_PHYSMASK2_REG 0x1a8 /**< Variable-range MTRR Mask 2. */
105#define VTD_MMIO_OFF_MTRR_PHYSBASE3_REG 0x1b0 /**< Variable-range MTRR Base 3. */
106#define VTD_MMIO_OFF_MTRR_PHYSMASK3_REG 0x1b8 /**< Variable-range MTRR Mask 3. */
107#define VTD_MMIO_OFF_MTRR_PHYSBASE4_REG 0x1c0 /**< Variable-range MTRR Base 4. */
108#define VTD_MMIO_OFF_MTRR_PHYSMASK4_REG 0x1c8 /**< Variable-range MTRR Mask 4. */
109#define VTD_MMIO_OFF_MTRR_PHYSBASE5_REG 0x1d0 /**< Variable-range MTRR Base 5. */
110#define VTD_MMIO_OFF_MTRR_PHYSMASK5_REG 0x1d8 /**< Variable-range MTRR Mask 5. */
111#define VTD_MMIO_OFF_MTRR_PHYSBASE6_REG 0x1e0 /**< Variable-range MTRR Base 6. */
112#define VTD_MMIO_OFF_MTRR_PHYSMASK6_REG 0x1e8 /**< Variable-range MTRR Mask 6. */
113#define VTD_MMIO_OFF_MTRR_PHYSBASE7_REG 0x1f0 /**< Variable-range MTRR Base 7. */
114#define VTD_MMIO_OFF_MTRR_PHYSMASK7_REG 0x1f8 /**< Variable-range MTRR Mask 7. */
115#define VTD_MMIO_OFF_MTRR_PHYSBASE8_REG 0x200 /**< Variable-range MTRR Base 8. */
116#define VTD_MMIO_OFF_MTRR_PHYSMASK8_REG 0x208 /**< Variable-range MTRR Mask 8. */
117#define VTD_MMIO_OFF_MTRR_PHYSBASE9_REG 0x210 /**< Variable-range MTRR Base 9. */
118#define VTD_MMIO_OFF_MTRR_PHYSMASK9_REG 0x218 /**< Variable-range MTRR Mask 9. */
119
120#define VTD_MMIO_OFF_VCCAP_REG 0xe00 /**< Virtual Command Capability. */
121#define VTD_MMIO_OFF_VCMD_REG 0xe10 /**< Virtual Command. */
122#define VTD_MMIO_OFF_VCMDRSVD_REG 0xe18 /**< Reserved for future for Virtual Command. */
123#define VTD_MMIO_OFF_VCRSP_REG 0xe20 /**< Virtual Command Response. */
124#define VTD_MMIO_OFF_VCRSPRSVD_REG 0xe28 /**< Reserved for future for Virtual Command Response. */
125/** @} */
126
127
128/** @name Root Entry.
129 * In accordance with the Intel spec.
130 * @{ */
131/** P: Present. */
132#define VTD_BF_0_ROOT_ENTRY_P_SHIFT 0
133#define VTD_BF_0_ROOT_ENTRY_P_MASK UINT64_C(0x0000000000000001)
134/** R: Reserved (bits 11:1). */
135#define VTD_BF_0_ROOT_ENTRY_RSVD_11_1_SHIFT 1
136#define VTD_BF_0_ROOT_ENTRY_RSVD_11_1_MASK UINT64_C(0x0000000000000ffe)
137/** CTP: Context-Table Pointer. */
138#define VTD_BF_0_ROOT_ENTRY_CTP_SHIFT 12
139#define VTD_BF_0_ROOT_ENTRY_CTP_MASK UINT64_C(0xfffffffffffff000)
140RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_ROOT_ENTRY_, UINT64_C(0), UINT64_MAX,
141 (P, RSVD_11_1, CTP));
142
143/** Root Entry. */
144typedef struct VTD_ROOT_ENTRY_T
145{
146 /** The qwords in the root entry. */
147 uint64_t au64[2];
148} VTD_ROOT_ENTRY_T;
149/** Pointer to a root entry. */
150typedef VTD_ROOT_ENTRY_T *PVTD_ROOT_ENTRY_T;
151/** Pointer to a const root entry. */
152typedef VTD_ROOT_ENTRY_T const *PCVTD_ROOT_ENTRY_T;
153/** @} */
154
155
156/** @name Scalable-mode Root Entry.
157 * In accordance with the Intel spec.
158 * @{ */
159/** LP: Lower Present. */
160#define VTD_BF_0_SM_ROOT_ENTRY_LP_SHIFT 0
161#define VTD_BF_0_SM_ROOT_ENTRY_LP_MASK UINT64_C(0x0000000000000001)
162/** R: Reserved (bits 11:1). */
163#define VTD_BF_0_SM_ROOT_ENTRY_RSVD_11_1_SHIFT 1
164#define VTD_BF_0_SM_ROOT_ENTRY_RSVD_11_1_MASK UINT64_C(0x0000000000000ffe)
165/** LCTP: Lower Context-Table Pointer */
166#define VTD_BF_0_SM_ROOT_ENTRY_LCTP_SHIFT 12
167#define VTD_BF_0_SM_ROOT_ENTRY_LCTP_MASK UINT64_C(0xfffffffffffff000)
168RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_SM_ROOT_ENTRY_, UINT64_C(0), UINT64_MAX,
169 (LP, RSVD_11_1, LCTP));
170
171/** UP: Upper Present. */
172#define VTD_BF_1_SM_ROOT_ENTRY_UP_SHIFT 0
173#define VTD_BF_1_SM_ROOT_ENTRY_UP_MASK UINT64_C(0x0000000000000001)
174/** R: Reserved (bits 11:1). */
175#define VTD_BF_1_SM_ROOT_ENTRY_RSVD_11_1_SHIFT 1
176#define VTD_BF_1_SM_ROOT_ENTRY_RSVD_11_1_MASK UINT64_C(0x0000000000000ffe)
177/** UCTP: Upper Context-Table Pointer. */
178#define VTD_BF_1_SM_ROOT_ENTRY_UCTP_SHIFT 12
179#define VTD_BF_1_SM_ROOT_ENTRY_UCTP_MASK UINT64_C(0xfffffffffffff000)
180RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_SM_ROOT_ENTRY_, UINT64_C(0), UINT64_MAX,
181 (UP, RSVD_11_1, UCTP));
182
183/** Scalable-mode root entry. */
184typedef struct VTD_SM_ROOT_ENTRY_T
185{
186 /** The lower scalable-mode root entry. */
187 uint64_t uLower;
188 /** The upper scalable-mode root entry. */
189 uint64_t uUpper;
190} VTD_SM_ROOT_ENTRY_T;
191/** Pointer to a scalable-mode root entry. */
192typedef VTD_SM_ROOT_ENTRY_T *PVTD_SM_ROOT_ENTRY_T;
193/** Pointer to a const scalable-mode root entry. */
194typedef VTD_SM_ROOT_ENTRY_T const *PCVTD_SM_ROOT_ENTRY_T;
195/** @} */
196
197
198/** @name Context Entry.
199 * In accordance with the Intel spec.
200 * @{ */
201/** P: Present. */
202#define VTD_BF_0_CONTEXT_ENTRY_P_SHIFT 0
203#define VTD_BF_0_CONTEXT_ENTRY_P_MASK UINT64_C(0x0000000000000001)
204/** FPD: Fault Processing Disable. */
205#define VTD_BF_0_CONTEXT_ENTRY_FPD_SHIFT 1
206#define VTD_BF_0_CONTEXT_ENTRY_FPD_MASK UINT64_C(0x0000000000000002)
207/** TT: Translation Type. */
208#define VTD_BF_0_CONTEXT_ENTRY_TT_SHIFT 2
209#define VTD_BF_0_CONTEXT_ENTRY_TT_MASK UINT64_C(0x000000000000000c)
210/** R: Reserved (bits 11:4). */
211#define VTD_BF_0_CONTEXT_ENTRY_RSVD_11_4_SHIFT 4
212#define VTD_BF_0_CONTEXT_ENTRY_RSVD_11_4_MASK UINT64_C(0x0000000000000ff0)
213/** SLPTPTR: Second Level Page Translation Pointer. */
214#define VTD_BF_0_CONTEXT_ENTRY_SLPTPTR_SHIFT 12
215#define VTD_BF_0_CONTEXT_ENTRY_SLPTPTR_MASK UINT64_C(0xfffffffffffff000)
216RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_CONTEXT_ENTRY_, UINT64_C(0), UINT64_MAX,
217 (P, FPD, TT, RSVD_11_4, SLPTPTR));
218
219/** AW: Address Width. */
220#define VTD_BF_1_CONTEXT_ENTRY_AW_SHIFT 0
221#define VTD_BF_1_CONTEXT_ENTRY_AW_MASK UINT64_C(0x0000000000000007)
222/** IGN: Ignored (bits 6:3). */
223#define VTD_BF_1_CONTEXT_ENTRY_IGN_6_3_SHIFT 3
224#define VTD_BF_1_CONTEXT_ENTRY_IGN_6_3_MASK UINT64_C(0x0000000000000078)
225/** R: Reserved (bit 7). */
226#define VTD_BF_1_CONTEXT_ENTRY_RSVD_7_SHIFT 7
227#define VTD_BF_1_CONTEXT_ENTRY_RSVD_7_MASK UINT64_C(0x0000000000000080)
228/** DID: Domain Identifier. */
229#define VTD_BF_1_CONTEXT_ENTRY_DID_SHIFT 8
230#define VTD_BF_1_CONTEXT_ENTRY_DID_MASK UINT64_C(0x0000000000ffff00)
231/** R: Reserved (bits 63:24). */
232#define VTD_BF_1_CONTEXT_ENTRY_RSVD_63_24_SHIFT 24
233#define VTD_BF_1_CONTEXT_ENTRY_RSVD_63_24_MASK UINT64_C(0xffffffffff000000)
234RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_CONTEXT_ENTRY_, UINT64_C(0), UINT64_MAX,
235 (AW, IGN_6_3, RSVD_7, DID, RSVD_63_24));
236
237/** Context Entry. */
238typedef struct VTD_CONTEXT_ENTRY_T
239{
240 /** The qwords in the context entry. */
241 uint64_t au64[2];
242} VTD_CONTEXT_ENTRY_T;
243/** Pointer to a context entry. */
244typedef VTD_CONTEXT_ENTRY_T *PVTD_CONTEXT_ENTRY_T;
245/** Pointer to a const context entry. */
246typedef VTD_CONTEXT_ENTRY_T const *PCVTD_CONTEXT_ENTRY_T;
247/** @} */
248
249
250/** @name Scalable-mode Context Entry.
251 * In accordance with the Intel spec.
252 * @{ */
253/** P: Present. */
254#define VTD_BF_0_SM_CONTEXT_ENTRY_P_SHIFT 0
255#define VTD_BF_0_SM_CONTEXT_ENTRY_P_MASK UINT64_C(0x0000000000000001)
256/** FPD: Fault Processing Disable. */
257#define VTD_BF_0_SM_CONTEXT_ENTRY_FPD_SHIFT 1
258#define VTD_BF_0_SM_CONTEXT_ENTRY_FPD_MASK UINT64_C(0x0000000000000002)
259/** DTE: Device-TLB Enable. */
260#define VTD_BF_0_SM_CONTEXT_ENTRY_DTE_SHIFT 2
261#define VTD_BF_0_SM_CONTEXT_ENTRY_DTE_MASK UINT64_C(0x0000000000000004)
262/** PASIDE: PASID Enable. */
263#define VTD_BF_0_SM_CONTEXT_ENTRY_PASIDE_SHIFT 3
264#define VTD_BF_0_SM_CONTEXT_ENTRY_PASIDE_MASK UINT64_C(0x0000000000000008)
265/** PRE: Page Request Enable. */
266#define VTD_BF_0_SM_CONTEXT_ENTRY_PRE_SHIFT 4
267#define VTD_BF_0_SM_CONTEXT_ENTRY_PRE_MASK UINT64_C(0x0000000000000010)
268/** R: Reserved (bits 8:5). */
269#define VTD_BF_0_SM_CONTEXT_ENTRY_RSVD_8_5_SHIFT 5
270#define VTD_BF_0_SM_CONTEXT_ENTRY_RSVD_8_5_MASK UINT64_C(0x00000000000001e0)
271/** PDTS: PASID Directory Size. */
272#define VTD_BF_0_SM_CONTEXT_ENTRY_PDTS_SHIFT 9
273#define VTD_BF_0_SM_CONTEXT_ENTRY_PDTS_MASK UINT64_C(0x0000000000000e00)
274/** PASIDDIRPTR: PASID Directory Pointer. */
275#define VTD_BF_0_SM_CONTEXT_ENTRY_PASIDDIRPTR_SHIFT 12
276#define VTD_BF_0_SM_CONTEXT_ENTRY_PASIDDIRPTR_MASK UINT64_C(0xfffffffffffff000)
277RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_SM_CONTEXT_ENTRY_, UINT64_C(0), UINT64_MAX,
278 (P, FPD, DTE, PASIDE, PRE, RSVD_8_5, PDTS, PASIDDIRPTR));
279
280/** RID_PASID: Requested Id to PASID assignment. */
281#define VTD_BF_1_SM_CONTEXT_ENTRY_RID_PASID_SHIFT 0
282#define VTD_BF_1_SM_CONTEXT_ENTRY_RID_PASID_MASK UINT64_C(0x00000000000fffff)
283/** RID_PRIV: Requested Id to PrivilegeModeRequested assignment. */
284#define VTD_BF_1_SM_CONTEXT_ENTRY_RID_PRIV_SHIFT 20
285#define VTD_BF_1_SM_CONTEXT_ENTRY_RID_PRIV_MASK UINT64_C(0x0000000000100000)
286/** R: Reserved (bits 63:21). */
287#define VTD_BF_1_SM_CONTEXT_ENTRY_RSVD_63_21_SHIFT 21
288#define VTD_BF_1_SM_CONTEXT_ENTRY_RSVD_63_21_MASK UINT64_C(0xffffffffffe00000)
289RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_SM_CONTEXT_ENTRY_, UINT64_C(0), UINT64_MAX,
290 (RID_PASID, RID_PRIV, RSVD_63_21));
291
292/** Context Entry. */
293typedef struct VTD_SM_CONTEXT_ENTRY_T
294{
295 /** The qwords in the scalable-mode context entry. */
296 uint64_t au64[4];
297} VTD_SM_CONTEXT_ENTRY_T;
298/** Pointer to a scalable-mode context entry. */
299typedef VTD_SM_CONTEXT_ENTRY_T *PVTD_SM_CONTEXT_ENTRY_T;
300/** Pointer to a const scalable-mode context entry. */
301typedef VTD_SM_CONTEXT_ENTRY_T const *PCVTD_SM_CONTEXT_ENTRY_T;
302/** @} */
303
304
305/** @name Scalable-mode PASID Directory Entry.
306 * In accordance with the Intel spec.
307 * @{ */
308/** P: Present. */
309#define VTD_BF_SM_PASID_DIR_ENTRY_P_SHIFT 0
310#define VTD_BF_SM_PASID_DIR_ENTRY_P_MASK UINT64_C(0x0000000000000001)
311/** FPD: Fault Processing Disable. */
312#define VTD_BF_SM_PASID_DIR_ENTRY_FPD_SHIFT 1
313#define VTD_BF_SM_PASID_DIR_ENTRY_FPD_MASK UINT64_C(0x0000000000000002)
314/** R: Reserved (bits 11:2). */
315#define VTD_BF_SM_PASID_DIR_ENTRY_RSVD_11_2_SHIFT 2
316#define VTD_BF_SM_PASID_DIR_ENTRY_RSVD_11_2_MASK UINT64_C(0x0000000000000ffc)
317/** SMPTBLPTR: Scalable Mode PASID Table Pointer. */
318#define VTD_BF_SM_PASID_DIR_ENTRY_SMPTBLPTR_SHIFT 12
319#define VTD_BF_SM_PASID_DIR_ENTRY_SMPTBLPTR_MASK UINT64_C(0xfffffffffffff000)
320RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_SM_PASID_DIR_ENTRY_, UINT64_C(0), UINT64_MAX,
321 (P, FPD, RSVD_11_2, SMPTBLPTR));
322
323/** Scalable-mode PASID Directory Entry. */
324typedef struct VTD_SM_PASID_DIR_ENTRY_T
325{
326 /** The scalable-mode PASID directory entry. */
327 uint64_t u;
328} VTD_SM_PASID_DIR_ENTRY_T;
329/** Pointer to a scalable-mode PASID directory entry. */
330typedef VTD_SM_PASID_DIR_ENTRY_T *PVTD_SM_PASID_DIR_ENTRY_T;
331/** Pointer to a const scalable-mode PASID directory entry. */
332typedef VTD_SM_PASID_DIR_ENTRY_T const *PCVTD_SM_PASID_DIR_ENTRY_T;
333/** @} */
334
335
336/** @name Scalable-mode PASID Table Entry.
337 * In accordance with the Intel spec.
338 * @{ */
339/** P: Present. */
340#define VTD_BF_0_SM_PASID_TBL_ENTRY_P_SHIFT 0
341#define VTD_BF_0_SM_PASID_TBL_ENTRY_P_MASK UINT64_C(0x0000000000000001)
342/** FPD: Fault Processing Disable. */
343#define VTD_BF_0_SM_PASID_TBL_ENTRY_FPD_SHIFT 1
344#define VTD_BF_0_SM_PASID_TBL_ENTRY_FPD_MASK UINT64_C(0x0000000000000002)
345/** AW: Address Width. */
346#define VTD_BF_0_SM_PASID_TBL_ENTRY_AW_SHIFT 2
347#define VTD_BF_0_SM_PASID_TBL_ENTRY_AW_MASK UINT64_C(0x000000000000001c)
348/** SLEE: Second-Level Execute Enable. */
349#define VTD_BF_0_SM_PASID_TBL_ENTRY_SLEE_SHIFT 5
350#define VTD_BF_0_SM_PASID_TBL_ENTRY_SLEE_MASK UINT64_C(0x0000000000000020)
351/** PGTT: PASID Granular Translation Type. */
352#define VTD_BF_0_SM_PASID_TBL_ENTRY_PGTT_SHIFT 6
353#define VTD_BF_0_SM_PASID_TBL_ENTRY_PGTT_MASK UINT64_C(0x00000000000001c0)
354/** SLADE: Second-Level Address/Dirty Enable. */
355#define VTD_BF_0_SM_PASID_TBL_ENTRY_SLADE_SHIFT 9
356#define VTD_BF_0_SM_PASID_TBL_ENTRY_SLADE_MASK UINT64_C(0x0000000000000200)
357/** R: Reserved (bits 11:10). */
358#define VTD_BF_0_SM_PASID_TBL_ENTRY_RSVD_11_10_SHIFT 10
359#define VTD_BF_0_SM_PASID_TBL_ENTRY_RSVD_11_10_MASK UINT64_C(0x0000000000000c00)
360/** SLPTPTR: Second-Level Page Table Pointer. */
361#define VTD_BF_0_SM_PASID_TBL_ENTRY_SLPTPTR_SHIFT 12
362#define VTD_BF_0_SM_PASID_TBL_ENTRY_SLPTPTR_MASK UINT64_C(0xfffffffffffff000)
363RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_SM_PASID_TBL_ENTRY_, UINT64_C(0), UINT64_MAX,
364 (P, FPD, AW, SLEE, PGTT, SLADE, RSVD_11_10, SLPTPTR));
365
366/** DID: Domain Identifer. */
367#define VTD_BF_1_SM_PASID_TBL_ENTRY_DID_SHIFT 0
368#define VTD_BF_1_SM_PASID_TBL_ENTRY_DID_MASK UINT64_C(0x000000000000ffff)
369/** R: Reserved (bits 22:16). */
370#define VTD_BF_1_SM_PASID_TBL_ENTRY_RSVD_22_16_SHIFT 16
371#define VTD_BF_1_SM_PASID_TBL_ENTRY_RSVD_22_16_MASK UINT64_C(0x00000000007f0000)
372/** PWSNP: Page-Walk Snoop. */
373#define VTD_BF_1_SM_PASID_TBL_ENTRY_PWSNP_SHIFT 23
374#define VTD_BF_1_SM_PASID_TBL_ENTRY_PWSNP_MASK UINT64_C(0x0000000000800000)
375/** PGSNP: Page Snoop. */
376#define VTD_BF_1_SM_PASID_TBL_ENTRY_PGSNP_SHIFT 24
377#define VTD_BF_1_SM_PASID_TBL_ENTRY_PGSNP_MASK UINT64_C(0x0000000001000000)
378/** CD: Cache Disable. */
379#define VTD_BF_1_SM_PASID_TBL_ENTRY_CD_SHIFT 25
380#define VTD_BF_1_SM_PASID_TBL_ENTRY_CD_MASK UINT64_C(0x0000000002000000)
381/** EMTE: Extended Memory Type Enable. */
382#define VTD_BF_1_SM_PASID_TBL_ENTRY_EMTE_SHIFT 26
383#define VTD_BF_1_SM_PASID_TBL_ENTRY_EMTE_MASK UINT64_C(0x0000000004000000)
384/** EMT: Extended Memory Type. */
385#define VTD_BF_1_SM_PASID_TBL_ENTRY_EMT_SHIFT 27
386#define VTD_BF_1_SM_PASID_TBL_ENTRY_EMT_MASK UINT64_C(0x0000000038000000)
387/** PWT: Page-Level Write Through. */
388#define VTD_BF_1_SM_PASID_TBL_ENTRY_PWT_SHIFT 30
389#define VTD_BF_1_SM_PASID_TBL_ENTRY_PWT_MASK UINT64_C(0x0000000040000000)
390/** PCD: Page-Level Cache Disable. */
391#define VTD_BF_1_SM_PASID_TBL_ENTRY_PCD_SHIFT 31
392#define VTD_BF_1_SM_PASID_TBL_ENTRY_PCD_MASK UINT64_C(0x0000000080000000)
393/** PAT: Page Attribute Table. */
394#define VTD_BF_1_SM_PASID_TBL_ENTRY_PAT_SHIFT 32
395#define VTD_BF_1_SM_PASID_TBL_ENTRY_PAT_MASK UINT64_C(0xffffffff00000000)
396RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_SM_PASID_TBL_ENTRY_, UINT64_C(0), UINT64_MAX,
397 (DID, RSVD_22_16, PWSNP, PGSNP, CD, EMTE, EMT, PWT, PCD, PAT));
398
399/** SRE: Supervisor Request Enable. */
400#define VTD_BF_2_SM_PASID_TBL_ENTRY_SRE_SHIFT 0
401#define VTD_BF_2_SM_PASID_TBL_ENTRY_SRE_MASK UINT64_C(0x0000000000000001)
402/** ERE: Execute Request Enable. */
403#define VTD_BF_2_SM_PASID_TBL_ENTRY_ERE_SHIFT 1
404#define VTD_BF_2_SM_PASID_TBL_ENTRY_ERE_MASK UINT64_C(0x0000000000000002)
405/** FLPM: First Level Paging Mode. */
406#define VTD_BF_2_SM_PASID_TBL_ENTRY_FLPM_SHIFT 2
407#define VTD_BF_2_SM_PASID_TBL_ENTRY_FLPM_MASK UINT64_C(0x000000000000000c)
408/** WPE: Write Protect Enable. */
409#define VTD_BF_2_SM_PASID_TBL_ENTRY_WPE_SHIFT 4
410#define VTD_BF_2_SM_PASID_TBL_ENTRY_WPE_MASK UINT64_C(0x0000000000000010)
411/** NXE: No-Execute Enable. */
412#define VTD_BF_2_SM_PASID_TBL_ENTRY_NXE_SHIFT 5
413#define VTD_BF_2_SM_PASID_TBL_ENTRY_NXE_MASK UINT64_C(0x0000000000000020)
414/** SMEP: Supervisor Mode Execute Prevent. */
415#define VTD_BF_2_SM_PASID_TBL_ENTRY_SMPE_SHIFT 6
416#define VTD_BF_2_SM_PASID_TBL_ENTRY_SMPE_MASK UINT64_C(0x0000000000000040)
417/** EAFE: Extended Accessed Flag Enable. */
418#define VTD_BF_2_SM_PASID_TBL_ENTRY_EAFE_SHIFT 7
419#define VTD_BF_2_SM_PASID_TBL_ENTRY_EAFE_MASK UINT64_C(0x0000000000000080)
420/** R: Reserved (bits 11:8). */
421#define VTD_BF_2_SM_PASID_TBL_ENTRY_RSVD_11_8_SHIFT 8
422#define VTD_BF_2_SM_PASID_TBL_ENTRY_RSVD_11_8_MASK UINT64_C(0x0000000000000f00)
423/** FLPTPTR: First Level Page Table Pointer. */
424#define VTD_BF_2_SM_PASID_TBL_ENTRY_FLPTPTR_SHIFT 12
425#define VTD_BF_2_SM_PASID_TBL_ENTRY_FLPTPTR_MASK UINT64_C(0xfffffffffffff000)
426RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_2_SM_PASID_TBL_ENTRY_, UINT64_C(0), UINT64_MAX,
427 (SRE, ERE, FLPM, WPE, NXE, SMPE, EAFE, RSVD_11_8, FLPTPTR));
428
429/** Scalable-mode PASID Table Entry. */
430typedef struct VTD_SM_PASID_TBL_ENTRY_T
431{
432 /** The qwords in the scalable-mode PASID table entry. */
433 uint64_t au64[8];
434} VTD_SM_PASID_TBL_ENTRY_T;
435/** Pointer to a scalable-mode PASID table entry. */
436typedef VTD_SM_PASID_TBL_ENTRY_T *PVTD_SM_PASID_TBL_ENTRY_T;
437/** Pointer to a const scalable-mode PASID table entry. */
438typedef VTD_SM_PASID_TBL_ENTRY_T const *PCVTD_SM_PASID_TBL_ENTRY_T;
439/** @} */
440
441
442/** @name First-Level Paging Entry.
443 * In accordance with the Intel spec.
444 * @{ */
445/** P: Present. */
446#define VTD_BF_FLP_ENTRY_P_SHIFT 0
447#define VTD_BF_FLP_ENTRY_P_MASK UINT64_C(0x0000000000000001)
448/** R/W: Read/Write. */
449#define VTD_BF_FLP_ENTRY_RW_SHIFT 1
450#define VTD_BF_FLP_ENTRY_RW_MASK UINT64_C(0x0000000000000002)
451/** U/S: User/Supervisor. */
452#define VTD_BF_FLP_ENTRY_US_SHIFT 2
453#define VTD_BF_FLP_ENTRY_US_MASK UINT64_C(0x0000000000000004)
454/** PWT: Page-Level Write Through. */
455#define VTD_BF_FLP_ENTRY_PWT_SHIFT 3
456#define VTD_BF_FLP_ENTRY_PWT_MASK UINT64_C(0x0000000000000008)
457/** PC: Page-Level Cache Disable. */
458#define VTD_BF_FLP_ENTRY_PCD_SHIFT 4
459#define VTD_BF_FLP_ENTRY_PCD_MASK UINT64_C(0x0000000000000010)
460/** A: Accessed. */
461#define VTD_BF_FLP_ENTRY_A_SHIFT 5
462#define VTD_BF_FLP_ENTRY_A_MASK UINT64_C(0x0000000000000020)
463/** IGN: Ignored (bit 6). */
464#define VTD_BF_FLP_ENTRY_IGN_6_SHIFT 6
465#define VTD_BF_FLP_ENTRY_IGN_6_MASK UINT64_C(0x0000000000000040)
466/** R: Reserved (bit 7). */
467#define VTD_BF_FLP_ENTRY_RSVD_7_SHIFT 7
468#define VTD_BF_FLP_ENTRY_RSVD_7_MASK UINT64_C(0x0000000000000080)
469/** IGN: Ignored (bits 9:8). */
470#define VTD_BF_FLP_ENTRY_IGN_9_8_SHIFT 8
471#define VTD_BF_FLP_ENTRY_IGN_9_8_MASK UINT64_C(0x0000000000000300)
472/** EA: Extended Accessed. */
473#define VTD_BF_FLP_ENTRY_EA_SHIFT 10
474#define VTD_BF_FLP_ENTRY_EA_MASK UINT64_C(0x0000000000000400)
475/** IGN: Ignored (bit 11). */
476#define VTD_BF_FLP_ENTRY_IGN_11_SHIFT 11
477#define VTD_BF_FLP_ENTRY_IGN_11_MASK UINT64_C(0x0000000000000800)
478/** ADDR: Address. */
479#define VTD_BF_FLP_ENTRY_ADDR_SHIFT 12
480#define VTD_BF_FLP_ENTRY_ADDR_MASK UINT64_C(0x000ffffffffff000)
481/** IGN: Ignored (bits 62:52). */
482#define VTD_BF_FLP_ENTRY_IGN_62_52_SHIFT 52
483#define VTD_BF_FLP_ENTRY_IGN_62_52_MASK UINT64_C(0x7ff0000000000000)
484/** XD: Execute Disabled. */
485#define VTD_BF_FLP_ENTRY_XD_SHIFT 63
486#define VTD_BF_FLP_ENTRY_XD_MASK UINT64_C(0x8000000000000000)
487RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_FLP_ENTRY_, UINT64_C(0), UINT64_MAX,
488 (P, RW, US, PWT, PCD, A, IGN_6, RSVD_7, IGN_9_8, EA, IGN_11, ADDR, IGN_62_52, XD));
489
490/** First-Level Paging Entry. */
491typedef struct VTD_FLP_ENTRY_T
492{
493 /** The first-level paging entry. */
494 uint64_t u;
495} VTD_FLP_ENTRY_T;
496/** Pointer to a first-level paging entry. */
497typedef VTD_FLP_ENTRY_T *PVTD_FLP_ENTRY_T;
498/** Pointer to a const first-level paging entry. */
499typedef VTD_FLP_ENTRY_T const *PCVTD_FLP_ENTRY_T;
500/** @} */
501
502
503/** @name Second-Level Paging Entry.
504 * In accordance with the Intel spec.
505 * @{ */
506/** R: Read. */
507#define VTD_BF_SLP_ENTRY_R_SHIFT 0
508#define VTD_BF_SLP_ENTRY_R_MASK UINT64_C(0x0000000000000001)
509/** W: Write. */
510#define VTD_BF_SLP_ENTRY_W_SHIFT 1
511#define VTD_BF_SLP_ENTRY_W_MASK UINT64_C(0x0000000000000002)
512/** X: Execute. */
513#define VTD_BF_SLP_ENTRY_X_SHIFT 2
514#define VTD_BF_SLP_ENTRY_X_MASK UINT64_C(0x0000000000000004)
515/** IGN: Ignored (bits 6:3). */
516#define VTD_BF_SLP_ENTRY_IGN_6_3_SHIFT 3
517#define VTD_BF_SLP_ENTRY_IGN_6_3_MASK UINT64_C(0x0000000000000078)
518/** R: Reserved (bit 7). */
519#define VTD_BF_SLP_ENTRY_RSVD_7_SHIFT 7
520#define VTD_BF_SLP_ENTRY_RSVD_7_MASK UINT64_C(0x0000000000000080)
521/** A: Accessed. */
522#define VTD_BF_SLP_ENTRY_A_SHIFT 8
523#define VTD_BF_SLP_ENTRY_A_MASK UINT64_C(0x0000000000000100)
524/** IGN: Ignored (bits 10:9). */
525#define VTD_BF_SLP_ENTRY_IGN_10_9_SHIFT 9
526#define VTD_BF_SLP_ENTRY_IGN_10_9_MASK UINT64_C(0x0000000000000600)
527/** R: Reserved (bit 11). */
528#define VTD_BF_SLP_ENTRY_RSVD_11_SHIFT 11
529#define VTD_BF_SLP_ENTRY_RSVD_11_MASK UINT64_C(0x0000000000000800)
530/** ADDR: Address. */
531#define VTD_BF_SLP_ENTRY_ADDR_SHIFT 12
532#define VTD_BF_SLP_ENTRY_ADDR_MASK UINT64_C(0x000ffffffffff000)
533/** IGN: Ignored (bits 61:52). */
534#define VTD_BF_SLP_ENTRY_IGN_61_52_SHIFT 52
535#define VTD_BF_SLP_ENTRY_IGN_61_52_MASK UINT64_C(0x3ff0000000000000)
536/** R: Reserved (bit 62). */
537#define VTD_BF_SLP_ENTRY_RSVD_62_SHIFT 62
538#define VTD_BF_SLP_ENTRY_RSVD_62_MASK UINT64_C(0x4000000000000000)
539/** IGN: Ignored (bit 63). */
540#define VTD_BF_SLP_ENTRY_IGN_63_SHIFT 63
541#define VTD_BF_SLP_ENTRY_IGN_63_MASK UINT64_C(0x8000000000000000)
542RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_SLP_ENTRY_, UINT64_C(0), UINT64_MAX,
543 (R, W, X, IGN_6_3, RSVD_7, A, IGN_10_9, RSVD_11, ADDR, IGN_61_52, RSVD_62, IGN_63));
544
545/** Second-Level Paging Entry. */
546typedef struct VTD_SLP_ENTRY_T
547{
548 /** The second-level paging entry. */
549 uint64_t u;
550} VTD_SLP_ENTRY_T;
551/** Pointer to a second-level paging entry. */
552typedef VTD_SLP_ENTRY_T *PVTD_SLP_ENTRY_T;
553/** Pointer to a const second-level paging entry. */
554typedef VTD_SLP_ENTRY_T const *PCVTD_SLP_ENTRY_T;
555/** @} */
556
557
558/** @name Fault Record.
559 * In accordance with the Intel spec.
560 * @{ */
561/** R: Reserved (bits 11:0). */
562#define VTD_BF_0_FAULT_RECORD_RSVD_11_0_SHIFT 0
563#define VTD_BF_0_FAULT_RECORD_RSVD_11_0_MASK UINT64_C(0x0000000000000fff)
564/** FI: Fault Information. */
565#define VTD_BF_0_FAULT_RECORD_FI_SHIFT 12
566#define VTD_BF_0_FAULT_RECORD_FI_MASK UINT64_C(0xfffffffffffff000)
567RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_FAULT_RECORD_, UINT64_C(0), UINT64_MAX,
568 (RSVD_11_0, FI));
569
570/** SID: Source identifier. */
571#define VTD_BF_1_FAULT_RECORD_SID_SHIFT 0
572#define VTD_BF_1_FAULT_RECORD_SID_MASK UINT64_C(0x000000000000ffff)
573/** R: Reserved (bits 28:16). */
574#define VTD_BF_1_FAULT_RECORD_RSVD_28_16_SHIFT 16
575#define VTD_BF_1_FAULT_RECORD_RSVD_28_16_MASK UINT64_C(0x000000001fff0000)
576/** PRIV: Privilege Mode Requested. */
577#define VTD_BF_1_FAULT_RECORD_PRIV_SHIFT 29
578#define VTD_BF_1_FAULT_RECORD_PRIV_MASK UINT64_C(0x0000000020000000)
579/** EXE: Execute Permission Requested. */
580#define VTD_BF_1_FAULT_RECORD_EXE_SHIFT 30
581#define VTD_BF_1_FAULT_RECORD_EXE_MASK UINT64_C(0x0000000040000000)
582/** PP: PASID Present. */
583#define VTD_BF_1_FAULT_RECORD_PP_SHIFT 31
584#define VTD_BF_1_FAULT_RECORD_PP_MASK UINT64_C(0x0000000080000000)
585/** FR: Fault Reason. */
586#define VTD_BF_1_FAULT_RECORD_FR_SHIFT 32
587#define VTD_BF_1_FAULT_RECORD_FR_MASK UINT64_C(0x000000ff00000000)
588/** PV: PASID Value. */
589#define VTD_BF_1_FAULT_RECORD_PV_SHIFT 40
590#define VTD_BF_1_FAULT_RECORD_PV_MASK UINT64_C(0x0fffff0000000000)
591/** AT: Address Type. */
592#define VTD_BF_1_FAULT_RECORD_AT_SHIFT 60
593#define VTD_BF_1_FAULT_RECORD_AT_MASK UINT64_C(0x3000000000000000)
594/** T: Type. */
595#define VTD_BF_1_FAULT_RECORD_T_SHIFT 62
596#define VTD_BF_1_FAULT_RECORD_T_MASK UINT64_C(0x4000000000000000)
597/** R: Reserved (bit 127). */
598#define VTD_BF_1_FAULT_RECORD_RSVD_63_SHIFT 63
599#define VTD_BF_1_FAULT_RECORD_RSVD_63_MASK UINT64_C(0x8000000000000000)
600RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_FAULT_RECORD_, UINT64_C(0), UINT64_MAX,
601 (SID, RSVD_28_16, PRIV, EXE, PP, FR, PV, AT, T, RSVD_63));
602
603/** Fault record. */
604typedef struct VTD_FAULT_RECORD_T
605{
606 /** The qwords in the fault record. */
607 uint64_t au64[2];
608} VTD_FAULT_RECORD_T;
609/** Pointer to a fault record. */
610typedef VTD_FAULT_RECORD_T *PVTD_FAULT_RECORD_T;
611/** Pointer to a const fault record. */
612typedef VTD_FAULT_RECORD_T const *PCVTD_FAULT_RECORD_T;
613/** @} */
614
615
616/** @name Interrupt Remapping Table Entry (IRTE) for Remapped Interrupts.
617 * In accordance with the Intel spec.
618 * @{ */
619/** P: Present. */
620#define VTD_BF_0_IRTE_P_SHIFT 0
621#define VTD_BF_0_IRTE_P_MASK UINT64_C(0x0000000000000001)
622/** FPD: Fault Processing Disable. */
623#define VTD_BF_0_IRTE_FPD_SHIFT 1
624#define VTD_BF_0_IRTE_FPD_MASK UINT64_C(0x0000000000000002)
625/** DM: Destination Mode (0=physical, 1=logical). */
626#define VTD_BF_0_IRTE_DM_SHIFT 2
627#define VTD_BF_0_IRTE_DM_MASK UINT64_C(0x0000000000000004)
628/** RH: Redirection Hint. */
629#define VTD_BF_0_IRTE_RH_SHIFT 3
630#define VTD_BF_0_IRTE_RH_MASK UINT64_C(0x0000000000000008)
631/** TM: Trigger Mode. */
632#define VTD_BF_0_IRTE_TM_SHIFT 4
633#define VTD_BF_0_IRTE_TM_MASK UINT64_C(0x0000000000000010)
634/** DLM: Delivery Mode. */
635#define VTD_BF_0_IRTE_DLM_SHIFT 5
636#define VTD_BF_0_IRTE_DLM_MASK UINT64_C(0x00000000000000e0)
637/** AVL: Available. */
638#define VTD_BF_0_IRTE_AVAIL_SHIFT 8
639#define VTD_BF_0_IRTE_AVAIL_MASK UINT64_C(0x0000000000000f00)
640/** R: Reserved (bits 14:12). */
641#define VTD_BF_0_IRTE_RSVD_14_12_SHIFT 12
642#define VTD_BF_0_IRTE_RSVD_14_12_MASK UINT64_C(0x0000000000007000)
643/** IM: IRTE Mode. */
644#define VTD_BF_0_IRTE_IM_SHIFT 15
645#define VTD_BF_0_IRTE_IM_MASK UINT64_C(0x0000000000008000)
646/** V: Vector. */
647#define VTD_BF_0_IRTE_V_SHIFT 16
648#define VTD_BF_0_IRTE_V_MASK UINT64_C(0x0000000000ff0000)
649/** R: Reserved (bits 31:24). */
650#define VTD_BF_0_IRTE_RSVD_31_24_SHIFT 24
651#define VTD_BF_0_IRTE_RSVD_31_24_MASK UINT64_C(0x00000000ff000000)
652/** DST: Desination Id. */
653#define VTD_BF_0_IRTE_DST_SHIFT 32
654#define VTD_BF_0_IRTE_DST_MASK UINT64_C(0xffffffff00000000)
655RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_IRTE_, UINT64_C(0), UINT64_MAX,
656 (P, FPD, DM, RH, TM, DLM, AVAIL, RSVD_14_12, IM, V, RSVD_31_24, DST));
657
658/** SID: Source Identifier. */
659#define VTD_BF_1_IRTE_SID_SHIFT 0
660#define VTD_BF_1_IRTE_SID_MASK UINT64_C(0x000000000000ffff)
661/** SQ: Source-Id Qualifier. */
662#define VTD_BF_1_IRTE_SQ_SHIFT 16
663#define VTD_BF_1_IRTE_SQ_MASK UINT64_C(0x0000000000030000)
664/** SVT: Source Validation Type. */
665#define VTD_BF_1_IRTE_SVT_SHIFT 18
666#define VTD_BF_1_IRTE_SVT_MASK UINT64_C(0x00000000000c0000)
667/** R: Reserved (bits 127:84). */
668#define VTD_BF_1_IRTE_RSVD_63_20_SHIFT 20
669#define VTD_BF_1_IRTE_RSVD_63_20_MASK UINT64_C(0xfffffffffff00000)
670RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_IRTE_, UINT64_C(0), UINT64_MAX,
671 (SID, SQ, SVT, RSVD_63_20));
672
673/** Interrupt Remapping Table Entry (IRTE) for remapped interrupts. */
674typedef struct VTD_IRTE_T
675{
676 /** The qwords in the IRTE. */
677 uint64_t au64[2];
678} VTD_IRTE_T;
679/** Pointer to an IRTE. */
680typedef VTD_IRTE_T *PVTD_IRTE_T;
681/** Pointer to a const IRTE. */
682typedef VTD_IRTE_T const *PCVTD_IRTE_T;
683/** @} */
684
685
686/** @name Version Register (VER_REG).
687 * In accordance with the Intel spec.
688 * @{ */
689/** Min: Minor Version Number. */
690#define VTD_BF_VER_REG_MIN_SHIFT 0
691#define VTD_BF_VER_REG_MIN_MASK UINT32_C(0x0000000f)
692/** Max: Major Version Number. */
693#define VTD_BF_VER_REG_MAX_SHIFT 4
694#define VTD_BF_VER_REG_MAX_MASK UINT32_C(0x000000f0)
695/** R: Reserved (bits 31:8). */
696#define VTD_BF_VER_REG_RSVD_31_8_SHIFT 8
697#define VTD_BF_VER_REG_RSVD_31_8_MASK UINT32_C(0xffffff00)
698RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_VER_REG_, UINT32_C(0), UINT32_MAX,
699 (MIN, MAX, RSVD_31_8));
700/** RW: Read/write mask. */
701#define VTD_VER_REG_RW_MASK UINT32_C(0)
702/** @} */
703
704
705/** @name Capability Register (CAP_REG).
706 * In accordance with the Intel spec.
707 * @{ */
708/** ND: Number of domains supported. */
709#define VTD_BF_CAP_REG_ND_SHIFT 0
710#define VTD_BF_CAP_REG_ND_MASK UINT64_C(0x0000000000000007)
711/** AFL: Advanced Fault Logging. */
712#define VTD_BF_CAP_REG_AFL_SHIFT 3
713#define VTD_BF_CAP_REG_AFL_MASK UINT64_C(0x0000000000000008)
714/** RWBF: Required Write-Buffer Flushing. */
715#define VTD_BF_CAP_REG_RWBF_SHIFT 4
716#define VTD_BF_CAP_REG_RWBF_MASK UINT64_C(0x0000000000000010)
717/** PLMR: Protected Low-Memory Region. */
718#define VTD_BF_CAP_REG_PLMR_SHIFT 5
719#define VTD_BF_CAP_REG_PLMR_MASK UINT64_C(0x0000000000000020)
720/** PHMR: Protected High-Memory Region. */
721#define VTD_BF_CAP_REG_PHMR_SHIFT 6
722#define VTD_BF_CAP_REG_PHMR_MASK UINT64_C(0x0000000000000040)
723/** CM: Caching Mode. */
724#define VTD_BF_CAP_REG_CM_SHIFT 7
725#define VTD_BF_CAP_REG_CM_MASK UINT64_C(0x0000000000000080)
726/** SAGAW: Supported Adjusted Guest Address Widths. */
727#define VTD_BF_CAP_REG_SAGAW_SHIFT 8
728#define VTD_BF_CAP_REG_SAGAW_MASK UINT64_C(0x0000000000001f00)
729/** R: Reserved (bits 15:13). */
730#define VTD_BF_CAP_REG_RSVD_15_13_SHIFT 13
731#define VTD_BF_CAP_REG_RSVD_15_13_MASK UINT64_C(0x000000000000e000)
732/** MGAW: Maximum Guest Address Width. */
733#define VTD_BF_CAP_REG_MGAW_SHIFT 16
734#define VTD_BF_CAP_REG_MGAW_MASK UINT64_C(0x00000000003f0000)
735/** ZLR: Zero Length Read. */
736#define VTD_BF_CAP_REG_ZLR_SHIFT 22
737#define VTD_BF_CAP_REG_ZLR_MASK UINT64_C(0x0000000000400000)
738/** DEP: Deprecated MBZ. Reserved (bit 23). */
739#define VTD_BF_CAP_REG_RSVD_23_SHIFT 23
740#define VTD_BF_CAP_REG_RSVD_23_MASK UINT64_C(0x0000000000800000)
741/** FRO: Fault-recording Register Offset. */
742#define VTD_BF_CAP_REG_FRO_SHIFT 24
743#define VTD_BF_CAP_REG_FRO_MASK UINT64_C(0x00000003ff000000)
744/** SLLPS: Second Level Large Page Support. */
745#define VTD_BF_CAP_REG_SLLPS_SHIFT 34
746#define VTD_BF_CAP_REG_SLLPS_MASK UINT64_C(0x0000003c00000000)
747/** R: Reserved (bit 38). */
748#define VTD_BF_CAP_REG_RSVD_38_SHIFT 38
749#define VTD_BF_CAP_REG_RSVD_38_MASK UINT64_C(0x0000004000000000)
750/** PSI: Page Selective Invalidation. */
751#define VTD_BF_CAP_REG_PSI_SHIFT 39
752#define VTD_BF_CAP_REG_PSI_MASK UINT64_C(0x0000008000000000)
753/** NFR: Number of Fault-recording Registers. */
754#define VTD_BF_CAP_REG_NFR_SHIFT 40
755#define VTD_BF_CAP_REG_NFR_MASK UINT64_C(0x0000ff0000000000)
756/** MAMV: Maximum Address Mask Value. */
757#define VTD_BF_CAP_REG_MAMV_SHIFT 48
758#define VTD_BF_CAP_REG_MAMV_MASK UINT64_C(0x003f000000000000)
759/** DWD: Write Draining. */
760#define VTD_BF_CAP_REG_DWD_SHIFT 54
761#define VTD_BF_CAP_REG_DWD_MASK UINT64_C(0x0040000000000000)
762/** DRD: Read Draining. */
763#define VTD_BF_CAP_REG_DRD_SHIFT 55
764#define VTD_BF_CAP_REG_DRD_MASK UINT64_C(0x0080000000000000)
765/** FL1GP: First Level 1 GB Page Support. */
766#define VTD_BF_CAP_REG_FL1GP_SHIFT 56
767#define VTD_BF_CAP_REG_FL1GP_MASK UINT64_C(0x0100000000000000)
768/** R: Reserved (bits 58:57). */
769#define VTD_BF_CAP_REG_RSVD_58_57_SHIFT 57
770#define VTD_BF_CAP_REG_RSVD_58_57_MASK UINT64_C(0x0600000000000000)
771/** PI: Posted Interrupt Support. */
772#define VTD_BF_CAP_REG_PI_SHIFT 59
773#define VTD_BF_CAP_REG_PI_MASK UINT64_C(0x0800000000000000)
774/** FL5LP: First Level 5-level Paging Support. */
775#define VTD_BF_CAP_REG_FL5LP_SHIFT 60
776#define VTD_BF_CAP_REG_FL5LP_MASK UINT64_C(0x1000000000000000)
777/** R: Reserved (bits 63:61). */
778#define VTD_BF_CAP_REG_RSVD_63_61_SHIFT 61
779#define VTD_BF_CAP_REG_RSVD_63_61_MASK UINT64_C(0xe000000000000000)
780RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_CAP_REG_, UINT64_C(0), UINT64_MAX,
781 (ND, AFL, RWBF, PLMR, PHMR, CM, SAGAW, RSVD_15_13, MGAW, ZLR, RSVD_23, FRO, SLLPS, RSVD_38, PSI, NFR,
782 MAMV, DWD, DRD, FL1GP, RSVD_58_57, PI, FL5LP, RSVD_63_61));
783
784/** RW: Read/write mask. */
785#define VTD_CAP_REG_RW_MASK UINT64_C(0)
786/** @} */
787
788
789/** @name Extended Capability Register (ECAP_REG).
790 * In accordance with the Intel spec.
791 * @{ */
792/** C: Page-walk Coherence. */
793#define VTD_BF_ECAP_REG_C_SHIFT 0
794#define VTD_BF_ECAP_REG_C_MASK UINT64_C(0x0000000000000001)
795/** QI: Queued Invalidation Support. */
796#define VTD_BF_ECAP_REG_QI_SHIFT 1
797#define VTD_BF_ECAP_REG_QI_MASK UINT64_C(0x0000000000000002)
798/** DT: Device-TLB Support. */
799#define VTD_BF_ECAP_REG_DT_SHIFT 2
800#define VTD_BF_ECAP_REG_DT_MASK UINT64_C(0x0000000000000004)
801/** IR: Interrupt Remapping Support. */
802#define VTD_BF_ECAP_REG_IR_SHIFT 3
803#define VTD_BF_ECAP_REG_IR_MASK UINT64_C(0x0000000000000008)
804/** EIM: Extended Interrupt Mode. */
805#define VTD_BF_ECAP_REG_EIM_SHIFT 4
806#define VTD_BF_ECAP_REG_EIM_MASK UINT64_C(0x0000000000000010)
807/** DEP: Deprecated MBZ. Reserved (bit 5). */
808#define VTD_BF_ECAP_REG_RSVD_5_SHIFT 5
809#define VTD_BF_ECAP_REG_RSVD_5_MASK UINT64_C(0x0000000000000020)
810/** PT: Pass Through. */
811#define VTD_BF_ECAP_REG_PT_SHIFT 6
812#define VTD_BF_ECAP_REG_PT_MASK UINT64_C(0x0000000000000040)
813/** SC: Snoop Control. */
814#define VTD_BF_ECAP_REG_SC_SHIFT 7
815#define VTD_BF_ECAP_REG_SC_MASK UINT64_C(0x0000000000000080)
816/** IRO: IOTLB Register Offset. */
817#define VTD_BF_ECAP_REG_IRO_SHIFT 8
818#define VTD_BF_ECAP_REG_IRO_MASK UINT64_C(0x000000000003ff00)
819/** R: Reserved (bits 19:18). */
820#define VTD_BF_ECAP_REG_RSVD_19_18_SHIFT 18
821#define VTD_BF_ECAP_REG_RSVD_19_18_MASK UINT64_C(0x00000000000c0000)
822/** MHMV: Maximum Handle Mask Value. */
823#define VTD_BF_ECAP_REG_MHMV_SHIFT 20
824#define VTD_BF_ECAP_REG_MHMV_MASK UINT64_C(0x0000000000f00000)
825/** DEP: Deprecated MBZ. Reserved (bit 24). */
826#define VTD_BF_ECAP_REG_RSVD_24_SHIFT 24
827#define VTD_BF_ECAP_REG_RSVD_24_MASK UINT64_C(0x0000000001000000)
828/** MTS: Memory Type Support. */
829#define VTD_BF_ECAP_REG_MTS_SHIFT 25
830#define VTD_BF_ECAP_REG_MTS_MASK UINT64_C(0x0000000002000000)
831/** NEST: Nested Translation Support. */
832#define VTD_BF_ECAP_REG_NEST_SHIFT 26
833#define VTD_BF_ECAP_REG_NEST_MASK UINT64_C(0x0000000004000000)
834/** R: Reserved (bit 27). */
835#define VTD_BF_ECAP_REG_RSVD_27_SHIFT 27
836#define VTD_BF_ECAP_REG_RSVD_27_MASK UINT64_C(0x0000000008000000)
837/** DEP: Deprecated MBZ. Reserved (bit 28). */
838#define VTD_BF_ECAP_REG_RSVD_28_SHIFT 28
839#define VTD_BF_ECAP_REG_RSVD_28_MASK UINT64_C(0x0000000010000000)
840/** PRS: Page Request Support. */
841#define VTD_BF_ECAP_REG_PRS_SHIFT 29
842#define VTD_BF_ECAP_REG_PRS_MASK UINT64_C(0x0000000020000000)
843/** ERS: Execute Request Support. */
844#define VTD_BF_ECAP_REG_ERS_SHIFT 30
845#define VTD_BF_ECAP_REG_ERS_MASK UINT64_C(0x0000000040000000)
846/** SRS: Supervisor Request Support. */
847#define VTD_BF_ECAP_REG_SRS_SHIFT 31
848#define VTD_BF_ECAP_REG_SRS_MASK UINT64_C(0x0000000080000000)
849/** R: Reserved (bit 32). */
850#define VTD_BF_ECAP_REG_RSVD_32_SHIFT 32
851#define VTD_BF_ECAP_REG_RSVD_32_MASK UINT64_C(0x0000000100000000)
852/** NWFS: No Write Flag Support. */
853#define VTD_BF_ECAP_REG_NWFS_SHIFT 33
854#define VTD_BF_ECAP_REG_NWFS_MASK UINT64_C(0x0000000200000000)
855/** EAFS: Extended Accessed Flags Support. */
856#define VTD_BF_ECAP_REG_EAFS_SHIFT 34
857#define VTD_BF_ECAP_REG_EAFS_MASK UINT64_C(0x0000000400000000)
858/** PSS: PASID Size Supported. */
859#define VTD_BF_ECAP_REG_PSS_SHIFT 35
860#define VTD_BF_ECAP_REG_PSS_MASK UINT64_C(0x000000f800000000)
861/** PASID: Process Address Space ID Support. */
862#define VTD_BF_ECAP_REG_PASID_SHIFT 40
863#define VTD_BF_ECAP_REG_PASID_MASK UINT64_C(0x0000010000000000)
864/** DIT: Device-TLB Invalidation Throttle. */
865#define VTD_BF_ECAP_REG_DIT_SHIFT 41
866#define VTD_BF_ECAP_REG_DIT_MASK UINT64_C(0x0000020000000000)
867/** PDS: Page-request Drain Support. */
868#define VTD_BF_ECAP_REG_PDS_SHIFT 42
869#define VTD_BF_ECAP_REG_PDS_MASK UINT64_C(0x0000040000000000)
870/** SMTS: Scalable-Mode Translation Support. */
871#define VTD_BF_ECAP_REG_SMTS_SHIFT 43
872#define VTD_BF_ECAP_REG_SMTS_MASK UINT64_C(0x0000080000000000)
873/** VCS: Virtual Command Support. */
874#define VTD_BF_ECAP_REG_VCS_SHIFT 44
875#define VTD_BF_ECAP_REG_VCS_MASK UINT64_C(0x0000100000000000)
876/** SLADS: Second-Level Accessed/Dirty Support. */
877#define VTD_BF_ECAP_REG_SLADS_SHIFT 45
878#define VTD_BF_ECAP_REG_SLADS_MASK UINT64_C(0x0000200000000000)
879/** SLTS: Second-Level Translation Support. */
880#define VTD_BF_ECAP_REG_SLTS_SHIFT 46
881#define VTD_BF_ECAP_REG_SLTS_MASK UINT64_C(0x0000400000000000)
882/** FLTS: First-Level Translation Support. */
883#define VTD_BF_ECAP_REG_FLTS_SHIFT 47
884#define VTD_BF_ECAP_REG_FLTS_MASK UINT64_C(0x0000800000000000)
885/** SMPWCS: Scalable-Mode Page-Walk Coherency Support. */
886#define VTD_BF_ECAP_REG_SMPWCS_SHIFT 48
887#define VTD_BF_ECAP_REG_SMPWCS_MASK UINT64_C(0x0001000000000000)
888/** RPS: RID-PASID Support. */
889#define VTD_BF_ECAP_REG_RPS_SHIFT 49
890#define VTD_BF_ECAP_REG_RPS_MASK UINT64_C(0x0002000000000000)
891/** R: Reserved (bits 63:50). */
892#define VTD_BF_ECAP_REG_RSVD_63_50_SHIFT 50
893#define VTD_BF_ECAP_REG_RSVD_63_50_MASK UINT64_C(0xfffc000000000000)
894RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_ECAP_REG_, UINT64_C(0), UINT64_MAX,
895 (C, QI, DT, IR, EIM, RSVD_5, PT, SC, IRO, RSVD_19_18, MHMV, RSVD_24, MTS, NEST, RSVD_27, RSVD_28,
896 PRS, ERS, SRS, RSVD_32, NWFS, EAFS, PSS, PASID, DIT, PDS, SMTS, VCS, SLADS, SLTS, FLTS, SMPWCS, RPS,
897 RSVD_63_50));
898
899/** RW: Read/write mask. */
900#define VTD_ECAP_REG_RW_MASK UINT64_C(0)
901/** @} */
902
903
904/** @name Global Command Register (GCMD_REG).
905 * In accordance with the Intel spec.
906 * @{ */
907/** R: Reserved (bits 22:0). */
908#define VTD_BF_GCMD_REG_RSVD_22_0_SHIFT 0
909#define VTD_BF_GCMD_REG_RSVD_22_0_MASK UINT32_C(0x007fffff)
910/** CFI: Compatibility Format Interrupt. */
911#define VTD_BF_GCMD_REG_CFI_SHIFT 23
912#define VTD_BF_GCMD_REG_CFI_MASK UINT32_C(0x00800000)
913/** SIRTP: Set Interrupt Table Remap Pointer. */
914#define VTD_BF_GCMD_REG_SIRTP_SHIFT 24
915#define VTD_BF_GCMD_REG_SIRTP_MASK UINT32_C(0x01000000)
916/** IRE: Interrupt Remap Enable. */
917#define VTD_BF_GCMD_REG_IRE_SHIFT 25
918#define VTD_BF_GCMD_REG_IRE_MASK UINT32_C(0x02000000)
919/** QIE: Queued Invalidation Enable. */
920#define VTD_BF_GCMD_REG_QIE_SHIFT 26
921#define VTD_BF_GCMD_REG_QIE_MASK UINT32_C(0x04000000)
922/** WBF: Write Buffer Flush. */
923#define VTD_BF_GCMD_REG_WBF_SHIFT 27
924#define VTD_BF_GCMD_REG_WBF_MASK UINT32_C(0x08000000)
925/** EAFL: Enable Advance Fault Logging. */
926#define VTD_BF_GCMD_REG_EAFL_SHIFT 28
927#define VTD_BF_GCMD_REG_EAFL_MASK UINT32_C(0x10000000)
928/** SFL: Set Fault Log. */
929#define VTD_BF_GCMD_REG_SFL_SHIFT 29
930#define VTD_BF_GCMD_REG_SFL_MASK UINT32_C(0x20000000)
931/** SRTP: Set Root Table Pointer. */
932#define VTD_BF_GCMD_REG_SRTP_SHIFT 30
933#define VTD_BF_GCMD_REG_SRTP_MASK UINT32_C(0x40000000)
934/** TE: Translation Enable. */
935#define VTD_BF_GCMD_REG_TE_SHIFT 31
936#define VTD_BF_GCMD_REG_TE_MASK UINT32_C(0x80000000)
937RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_GCMD_REG_, UINT32_C(0), UINT32_MAX,
938 (RSVD_22_0, CFI, SIRTP, IRE, QIE, WBF, EAFL, SFL, SRTP, TE));
939
940/** RW: Read/write mask. */
941#define VTD_GCMD_REG_RW_MASK UINT32_C(0xff800000)
942/** @} */
943
944
945/** @name Global Status Register (GSTS_REG).
946 * In accordance with the Intel spec.
947 * @{ */
948/** R: Reserved (bits 22:0). */
949#define VTD_BF_GSTS_REG_RSVD_22_0_SHIFT 0
950#define VTD_BF_GSTS_REG_RSVD_22_0_MASK UINT32_C(0x007fffff)
951/** CFIS: Compatibility Format Interrupt Status. */
952#define VTD_BF_GSTS_REG_CFIS_SHIFT 23
953#define VTD_BF_GSTS_REG_CFIS_MASK UINT32_C(0x00800000)
954/** IRTPS: Interrupt Remapping Table Pointer Status. */
955#define VTD_BF_GSTS_REG_IRTPS_SHIFT 24
956#define VTD_BF_GSTS_REG_IRTPS_MASK UINT32_C(0x01000000)
957/** IRES: Interrupt Remapping Enable Status. */
958#define VTD_BF_GSTS_REG_IRES_SHIFT 25
959#define VTD_BF_GSTS_REG_IRES_MASK UINT32_C(0x02000000)
960/** QIES: Queued Invalidation Enable Status. */
961#define VTD_BF_GSTS_REG_QIES_SHIFT 26
962#define VTD_BF_GSTS_REG_QIES_MASK UINT32_C(0x04000000)
963/** WBFS: Write Buffer Flush Status. */
964#define VTD_BF_GSTS_REG_WBFS_SHIFT 27
965#define VTD_BF_GSTS_REG_WBFS_MASK UINT32_C(0x08000000)
966/** AFLS: Advanced Fault Logging Status. */
967#define VTD_BF_GSTS_REG_AFLS_SHIFT 28
968#define VTD_BF_GSTS_REG_AFLS_MASK UINT32_C(0x10000000)
969/** FLS: Fault Log Status. */
970#define VTD_BF_GSTS_REG_FLS_SHIFT 29
971#define VTD_BF_GSTS_REG_FLS_MASK UINT32_C(0x20000000)
972/** RTPS: Root Table Pointer Status. */
973#define VTD_BF_GSTS_REG_RTPS_SHIFT 30
974#define VTD_BF_GSTS_REG_RTPS_MASK UINT32_C(0x40000000)
975/** TES: Translation Enable Status. */
976#define VTD_BF_GSTS_REG_TES_SHIFT 31
977#define VTD_BF_GSTS_REG_TES_MASK UINT32_C(0x80000000)
978RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_GSTS_REG_, UINT32_C(0), UINT32_MAX,
979 (RSVD_22_0, CFIS, IRTPS, IRES, QIES, WBFS, AFLS, FLS, RTPS, TES));
980
981/** RW: Read/write mask. */
982#define VTD_GSTS_REG_RW_MASK UINT32_C(0)
983/** @} */
984
985
986/** @name Root Table Address Register (RTADDR_REG).
987 * In accordance with the Intel spec.
988 * @{ */
989/** R: Reserved (bits 9:0). */
990#define VTD_BF_RTADDR_REG_RSVD_9_0_SHIFT 0
991#define VTD_BF_RTADDR_REG_RSVD_9_0_MASK UINT64_C(0x00000000000003ff)
992/** TTM: Translation Table Mode. */
993#define VTD_BF_RTADDR_REG_TTM_SHIFT 10
994#define VTD_BF_RTADDR_REG_TTM_MASK UINT64_C(0x0000000000000c00)
995/** RTA: Root Table Address. */
996#define VTD_BF_RTADDR_REG_RTA_SHIFT 12
997#define VTD_BF_RTADDR_REG_RTA_MASK UINT64_C(0xfffffffffffff000)
998RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_RTADDR_REG_, UINT64_C(0), UINT64_MAX,
999 (RSVD_9_0, TTM, RTA));
1000
1001/** RW: Read/write mask. */
1002#define VTD_RTADDR_REG_RW_MASK UINT64_C(0xfffffffffffffc00)
1003/** @} */
1004
1005
1006/** @name Context Command Register (CCMD_REG).
1007 * In accordance with the Intel spec.
1008 * @{ */
1009/** DID: Domain-ID. */
1010#define VTD_BF_CCMD_REG_DID_SHIFT 0
1011#define VTD_BF_CCMD_REG_DID_MASK UINT64_C(0x000000000000ffff)
1012/** SID: Source-ID. */
1013#define VTD_BF_CCMD_REG_SID_SHIFT 16
1014#define VTD_BF_CCMD_REG_SID_MASK UINT64_C(0x00000000ffff0000)
1015/** FM: Function Mask. */
1016#define VTD_BF_CCMD_REG_FM_SHIFT 32
1017#define VTD_BF_CCMD_REG_FM_MASK UINT64_C(0x0000000300000000)
1018/** R: Reserved (bits 58:34). */
1019#define VTD_BF_CCMD_REG_RSVD_58_34_SHIFT 34
1020#define VTD_BF_CCMD_REG_RSVD_58_34_MASK UINT64_C(0x07fffffc00000000)
1021/** CAIG: Context Actual Invalidation Granularity. */
1022#define VTD_BF_CCMD_REG_CAIG_SHIFT 59
1023#define VTD_BF_CCMD_REG_CAIG_MASK UINT64_C(0x1800000000000000)
1024/** CIRG: Context Invalidation Request Granularity. */
1025#define VTD_BF_CCMD_REG_CIRG_SHIFT 61
1026#define VTD_BF_CCMD_REG_CIRG_MASK UINT64_C(0x6000000000000000)
1027/** ICC: Invalidation Context Cache. */
1028#define VTD_BF_CCMD_REG_ICC_SHIFT 63
1029#define VTD_BF_CCMD_REG_ICC_MASK UINT64_C(0x8000000000000000)
1030RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_CCMD_REG_, UINT64_C(0), UINT64_MAX,
1031 (DID, SID, FM, RSVD_58_34, CAIG, CIRG, ICC));
1032
1033/** RW: Read/write mask. */
1034#define VTD_CCMD_REG_RW_MASK ( VTD_BF_CCMD_REG_DID_MASK | VTD_BF_CCMD_REG_SID_MASK \
1035 | VTD_BF_CCMD_REG_FM_MASK | VTD_BF_CCMD_REG_CIRG_MASK \
1036 | VTD_BF_CCMD_REG_ICC_MASK)
1037/** @} */
1038
1039
1040/** @name IOTLB Invalidation Register (IOTLB_REG).
1041 * In accordance with the Intel spec.
1042 * @{ */
1043/** R: Reserved (bits 31:0). */
1044#define VTD_BF_IOTLB_REG_RSVD_31_0_SHIFT 0
1045#define VTD_BF_IOTLB_REG_RSVD_31_0_MASK UINT64_C(0x00000000ffffffff)
1046/** DID: Domain-ID. */
1047#define VTD_BF_IOTLB_REG_DID_SHIFT 32
1048#define VTD_BF_IOTLB_REG_DID_MASK UINT64_C(0x0000ffff00000000)
1049/** DW: Draining Writes. */
1050#define VTD_BF_IOTLB_REG_DW_SHIFT 48
1051#define VTD_BF_IOTLB_REG_DW_MASK UINT64_C(0x0001000000000000)
1052/** DR: Draining Reads. */
1053#define VTD_BF_IOTLB_REG_DR_SHIFT 49
1054#define VTD_BF_IOTLB_REG_DR_MASK UINT64_C(0x0002000000000000)
1055/** R: Reserved (bits 56:50). */
1056#define VTD_BF_IOTLB_REG_RSVD_56_50_SHIFT 50
1057#define VTD_BF_IOTLB_REG_RSVD_56_50_MASK UINT64_C(0x01fc000000000000)
1058/** IAIG: IOTLB Actual Invalidation Granularity. */
1059#define VTD_BF_IOTLB_REG_IAIG_SHIFT 57
1060#define VTD_BF_IOTLB_REG_IAIG_MASK UINT64_C(0x0600000000000000)
1061/** R: Reserved (bit 59). */
1062#define VTD_BF_IOTLB_REG_RSVD_59_SHIFT 59
1063#define VTD_BF_IOTLB_REG_RSVD_59_MASK UINT64_C(0x0800000000000000)
1064/** IIRG: IOTLB Invalidation Request Granularity. */
1065#define VTD_BF_IOTLB_REG_IIRG_SHIFT 60
1066#define VTD_BF_IOTLB_REG_IIRG_MASK UINT64_C(0x3000000000000000)
1067/** R: Reserved (bit 62). */
1068#define VTD_BF_IOTLB_REG_RSVD_62_SHIFT 62
1069#define VTD_BF_IOTLB_REG_RSVD_62_MASK UINT64_C(0x4000000000000000)
1070/** IVT: Invalidate IOTLB. */
1071#define VTD_BF_IOTLB_REG_IVT_SHIFT 63
1072#define VTD_BF_IOTLB_REG_IVT_MASK UINT64_C(0x8000000000000000)
1073RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IOTLB_REG_, UINT64_C(0), UINT64_MAX,
1074 (RSVD_31_0, DID, DW, DR, RSVD_56_50, IAIG, RSVD_59, IIRG, RSVD_62, IVT));
1075
1076/** RW: Read/write mask. */
1077#define VTD_IOTLB_REG_RW_MASK ( VTD_BF_IOTLB_REG_DID_MASK | VTD_BF_IOTLB_REG_DW_MASK \
1078 | VTD_BF_IOTLB_REG_DR_MASK | VTD_BF_IOTLB_REG_IIRG_MASK \
1079 | VTD_BF_IOTLB_REG_IVT_MASK)
1080/** @} */
1081
1082
1083/** @name Invalidate Address Register (IVA_REG).
1084 * In accordance with the Intel spec.
1085 * @{ */
1086/** AM: Address Mask. */
1087#define VTD_BF_IVA_REG_AM_SHIFT 0
1088#define VTD_BF_IVA_REG_AM_MASK UINT64_C(0x000000000000003f)
1089/** IH: Invalidation Hint. */
1090#define VTD_BF_IVA_REG_IH_SHIFT 6
1091#define VTD_BF_IVA_REG_IH_MASK UINT64_C(0x0000000000000040)
1092/** R: Reserved (bits 11:7). */
1093#define VTD_BF_IVA_REG_RSVD_11_7_SHIFT 7
1094#define VTD_BF_IVA_REG_RSVD_11_7_MASK UINT64_C(0x0000000000000f80)
1095/** ADDR: Address. */
1096#define VTD_BF_IVA_REG_ADDR_SHIFT 12
1097#define VTD_BF_IVA_REG_ADDR_MASK UINT64_C(0xfffffffffffff000)
1098RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IVA_REG_, UINT64_C(0), UINT64_MAX,
1099 (AM, IH, RSVD_11_7, ADDR));
1100
1101/** RW: Read/write mask. */
1102#define VTD_IVA_REG_RW_MASK ( VTD_BF_IVA_REG_AM_MASK | VTD_BF_IVA_REG_IH_MASK \
1103 | VTD_BF_IVA_REG_ADDR_MASK)
1104/** @} */
1105
1106
1107/** @name Fault Status Register (FSTS_REG).
1108 * In accordance with the Intel spec.
1109 * @{ */
1110/** PFO: Primary Fault Overflow. */
1111#define VTD_BF_FSTS_REG_PFO_SHIFT 0
1112#define VTD_BF_FSTS_REG_PFO_MASK UINT32_C(0x00000001)
1113/** PPF: Primary Pending Fault. */
1114#define VTD_BF_FSTS_REG_PPF_SHIFT 1
1115#define VTD_BF_FSTS_REG_PPF_MASK UINT32_C(0x00000002)
1116/** AFO: Advanced Fault Overflow. */
1117#define VTD_BF_FSTS_REG_AFO_SHIFT 2
1118#define VTD_BF_FSTS_REG_AFO_MASK UINT32_C(0x00000004)
1119/** APF: Advanced Pending Fault. */
1120#define VTD_BF_FSTS_REG_APF_SHIFT 3
1121#define VTD_BF_FSTS_REG_APF_MASK UINT32_C(0x00000008)
1122/** IQE: Invalidation Queue Error. */
1123#define VTD_BF_FSTS_REG_IQE_SHIFT 4
1124#define VTD_BF_FSTS_REG_IQE_MASK UINT32_C(0x00000010)
1125/** ICE: Invalidation Completion Error. */
1126#define VTD_BF_FSTS_REG_ICE_SHIFT 5
1127#define VTD_BF_FSTS_REG_ICE_MASK UINT32_C(0x00000020)
1128/** ITE: Invalidation Timeout Error. */
1129#define VTD_BF_FSTS_REG_ITE_SHIFT 6
1130#define VTD_BF_FSTS_REG_ITE_MASK UINT32_C(0x00000040)
1131/** DEP: Deprecated MBZ. Reserved (bit 7). */
1132#define VTD_BF_FSTS_REG_RSVD_7_SHIFT 7
1133#define VTD_BF_FSTS_REG_RSVD_7_MASK UINT32_C(0x00000080)
1134/** FRI: Fault Record Index. */
1135#define VTD_BF_FSTS_REG_FRI_SHIFT 8
1136#define VTD_BF_FSTS_REG_FRI_MASK UINT32_C(0x0000ff00)
1137/** R: Reserved (bits 31:16). */
1138#define VTD_BF_FSTS_REG_RSVD_31_16_SHIFT 16
1139#define VTD_BF_FSTS_REG_RSVD_31_16_MASK UINT32_C(0xffff0000)
1140RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_FSTS_REG_, UINT32_C(0), UINT32_MAX,
1141 (PFO, PPF, AFO, APF, IQE, ICE, ITE, RSVD_7, FRI, RSVD_31_16));
1142
1143/** RW: Read/write mask. */
1144#define VTD_FSTS_REG_RW_MASK ( VTD_BF_FSTS_REG_PFO_MASK | VTD_BF_FSTS_REG_AFO_MASK \
1145 | VTD_BF_FSTS_REG_APF_MASK | VTD_BF_FSTS_REG_IQE_MASK \
1146 | VTD_BF_FSTS_REG_ICE_MASK | VTD_BF_FSTS_REG_ITE_MASK)
1147/** RW1C: Read-only-status, Write-1-to-clear status mask. */
1148#define VTD_FSTS_REG_RW1C_MASK ( VTD_BF_FSTS_REG_PFO_MASK | VTD_BF_FSTS_REG_AFO_MASK \
1149 | VTD_BF_FSTS_REG_APF_MASK | VTD_BF_FSTS_REG_IQE_MASK \
1150 | VTD_BF_FSTS_REG_ICE_MASK | VTD_BF_FSTS_REG_ITE_MASK)
1151/** @} */
1152
1153
1154/** @name Fault Event Control Register (FECTL_REG).
1155 * In accordance with the Intel spec.
1156 * @{ */
1157/** R: Reserved (bits 29:0). */
1158#define VTD_BF_FECTL_REG_RSVD_29_0_SHIFT 0
1159#define VTD_BF_FECTL_REG_RSVD_29_0_MASK UINT32_C(0x3fffffff)
1160/** IP: Interrupt Pending. */
1161#define VTD_BF_FECTL_REG_IP_SHIFT 30
1162#define VTD_BF_FECTL_REG_IP_MASK UINT32_C(0x40000000)
1163/** IM: Interrupt Mask. */
1164#define VTD_BF_FECTL_REG_IM_SHIFT 31
1165#define VTD_BF_FECTL_REG_IM_MASK UINT32_C(0x80000000)
1166RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_FECTL_REG_, UINT32_C(0), UINT32_MAX,
1167 (RSVD_29_0, IP, IM));
1168
1169/** RW: Read/write mask. */
1170#define VTD_FECTL_REG_RW_MASK VTD_BF_FECTL_REG_IM_MASK
1171/** @} */
1172
1173
1174/** @name Fault Event Data Register (FEDATA_REG).
1175 * In accordance with the Intel spec.
1176 * @{ */
1177/** IMD: Interrupt Message Data. */
1178#define VTD_BF_FEDATA_REG_IMD_SHIFT 0
1179#define VTD_BF_FEDATA_REG_IMD_MASK UINT32_C(0x0000ffff)
1180/** R: Reserved (bits 31:16). VT-d specs. prior to 2021 had EIMD here. */
1181#define VTD_BF_FEDATA_REG_RSVD_31_16_SHIFT 16
1182#define VTD_BF_FEDATA_REG_RSVD_31_16_MASK UINT32_C(0xffff0000)
1183RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_FEDATA_REG_, UINT32_C(0), UINT32_MAX,
1184 (IMD, RSVD_31_16));
1185
1186/** RW: Read/write mask. */
1187#define VTD_FEDATA_REG_RW_MASK VTD_BF_FEDATA_REG_IMD_MASK
1188/** @} */
1189
1190
1191/** @name Fault Event Address Register (FEADDR_REG).
1192 * In accordance with the Intel spec.
1193 * @{ */
1194/** R: Reserved (bits 1:0). */
1195#define VTD_BF_FEADDR_REG_RSVD_1_0_SHIFT 0
1196#define VTD_BF_FEADDR_REG_RSVD_1_0_MASK UINT32_C(0x00000003)
1197/** MA: Message Address. */
1198#define VTD_BF_FEADDR_REG_MA_SHIFT 2
1199#define VTD_BF_FEADDR_REG_MA_MASK UINT32_C(0xfffffffc)
1200RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_FEADDR_REG_, UINT32_C(0), UINT32_MAX,
1201 (RSVD_1_0, MA));
1202
1203/** RW: Read/write mask. */
1204#define VTD_FEADDR_REG_RW_MASK VTD_BF_FEADDR_REG_MA_MASK
1205/** @} */
1206
1207
1208/** @name Fault Event Upper Address Register (FEUADDR_REG).
1209 * In accordance with the Intel spec.
1210 * @{ */
1211/** MUA: Message Upper Address. */
1212#define VTD_BF_FEUADDR_REG_MA_SHIFT 0
1213#define VTD_BF_FEUADDR_REG_MA_MASK UINT32_C(0xffffffff)
1214
1215/** RW: Read/write mask. */
1216#define VTD_FEUADDR_REG_RW_MASK VTD_BF_FEUADDR_REG_MA_MASK
1217/** @} */
1218
1219
1220/** @name Fault Recording Register (FRCD_REG).
1221 * In accordance with the Intel spec.
1222 * @{ */
1223/** R: Reserved (bits 11:0). */
1224#define VTD_BF_0_FRCD_REG_RSVD_11_0_SHIFT 0
1225#define VTD_BF_0_FRCD_REG_RSVD_11_0_MASK UINT64_C(0x0000000000000fff)
1226/** FI: Fault Info. */
1227#define VTD_BF_0_FRCD_REG_FI_SHIFT 12
1228#define VTD_BF_0_FRCD_REG_FI_MASK UINT64_C(0xfffffffffffff000)
1229RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_FRCD_REG_, UINT64_C(0), UINT64_MAX,
1230 (RSVD_11_0, FI));
1231
1232/** SID: Source Identifier. */
1233#define VTD_BF_1_FRCD_REG_SID_SHIFT 0
1234#define VTD_BF_1_FRCD_REG_SID_MASK UINT64_C(0x000000000000ffff)
1235/** R: Reserved (bits 27:16). */
1236#define VTD_BF_1_FRCD_REG_RSVD_27_16_SHIFT 16
1237#define VTD_BF_1_FRCD_REG_RSVD_27_16_MASK UINT64_C(0x000000000fff0000)
1238/** T2: Type bit 2. */
1239#define VTD_BF_1_FRCD_REG_T2_SHIFT 28
1240#define VTD_BF_1_FRCD_REG_T2_MASK UINT64_C(0x0000000010000000)
1241/** PRIV: Privilege Mode. */
1242#define VTD_BF_1_FRCD_REG_PRIV_SHIFT 29
1243#define VTD_BF_1_FRCD_REG_PRIV_MASK UINT64_C(0x0000000020000000)
1244/** EXE: Execute Permission Requested. */
1245#define VTD_BF_1_FRCD_REG_EXE_SHIFT 30
1246#define VTD_BF_1_FRCD_REG_EXE_MASK UINT64_C(0x0000000040000000)
1247/** PP: PASID Present. */
1248#define VTD_BF_1_FRCD_REG_PP_SHIFT 31
1249#define VTD_BF_1_FRCD_REG_PP_MASK UINT64_C(0x0000000080000000)
1250/** FR: Fault Reason. */
1251#define VTD_BF_1_FRCD_REG_FR_SHIFT 32
1252#define VTD_BF_1_FRCD_REG_FR_MASK UINT64_C(0x000000ff00000000)
1253/** PV: PASID Value. */
1254#define VTD_BF_1_FRCD_REG_PV_SHIFT 40
1255#define VTD_BF_1_FRCD_REG_PV_MASK UINT64_C(0x0fffff0000000000)
1256/** AT: Address Type. */
1257#define VTD_BF_1_FRCD_REG_AT_SHIFT 60
1258#define VTD_BF_1_FRCD_REG_AT_MASK UINT64_C(0x3000000000000000)
1259/** T1: Type bit 1. */
1260#define VTD_BF_1_FRCD_REG_T1_SHIFT 62
1261#define VTD_BF_1_FRCD_REG_T1_MASK UINT64_C(0x4000000000000000)
1262/** F: Fault. */
1263#define VTD_BF_1_FRCD_REG_F_SHIFT 63
1264#define VTD_BF_1_FRCD_REG_F_MASK UINT64_C(0x8000000000000000)
1265RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_FRCD_REG_, UINT64_C(0), UINT64_MAX,
1266 (SID, RSVD_27_16, T2, PRIV, EXE, PP, FR, PV, AT, T1, F));
1267
1268/** RW: Read/write mask. */
1269#define VTD_FRCD_REG_LO_RW_MASK UINT64_C(0)
1270#define VTD_FRCD_REG_HI_RW_MASK VTD_BF_1_FRCD_REG_F_MASK
1271/** RW1C: Read-only-status, Write-1-to-clear status mask. */
1272#define VTD_FRCD_REG_LO_RW1C_MASK UINT64_C(0)
1273#define VTD_FRCD_REG_HI_RW1C_MASK VTD_BF_1_FRCD_REG_F_MASK
1274/** @} */
1275
1276
1277/** @name Advanced Fault Log Register (AFLOG_REG).
1278 * In accordance with the Intel spec.
1279 * @{ */
1280/** R: Reserved (bits 8:0). */
1281#define VTD_BF_0_AFLOG_REG_RSVD_8_0_SHIFT 0
1282#define VTD_BF_0_AFLOG_REG_RSVD_8_0_MASK UINT64_C(0x00000000000001ff)
1283/** FLS: Fault Log Size. */
1284#define VTD_BF_0_AFLOG_REG_FLS_SHIFT 9
1285#define VTD_BF_0_AFLOG_REG_FLS_MASK UINT64_C(0x0000000000000e00)
1286/** FLA: Fault Log Address. */
1287#define VTD_BF_0_AFLOG_REG_FLA_SHIFT 12
1288#define VTD_BF_0_AFLOG_REG_FLA_MASK UINT64_C(0xfffffffffffff000)
1289RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_AFLOG_REG_, UINT64_C(0), UINT64_MAX,
1290 (RSVD_8_0, FLS, FLA));
1291
1292/** RW: Read/write mask. */
1293#define VTD_AFLOG_REG_RW_MASK (VTD_BF_0_AFLOG_REG_FLS_MASK | VTD_BF_0_AFLOG_REG_FLA_MASK)
1294/** @} */
1295
1296
1297/** @name Protected Memory Enable Register (PMEN_REG).
1298 * In accordance with the Intel spec.
1299 * @{ */
1300/** PRS: Protected Region Status. */
1301#define VTD_BF_PMEN_REG_PRS_SHIFT 0
1302#define VTD_BF_PMEN_REG_PRS_MASK UINT32_C(0x00000001)
1303/** R: Reserved (bits 30:1). */
1304#define VTD_BF_PMEN_REG_RSVD_30_1_SHIFT 1
1305#define VTD_BF_PMEN_REG_RSVD_30_1_MASK UINT32_C(0x7ffffffe)
1306/** EPM: Enable Protected Memory. */
1307#define VTD_BF_PMEN_REG_EPM_SHIFT 31
1308#define VTD_BF_PMEN_REG_EPM_MASK UINT32_C(0x80000000)
1309RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_PMEN_REG_, UINT32_C(0), UINT32_MAX,
1310 (PRS, RSVD_30_1, EPM));
1311
1312/** RW: Read/write mask. */
1313#define VTD_PMEN_REG_RW_MASK VTD_BF_PMEN_REG_EPM_MASK
1314/** @} */
1315
1316
1317/** @name Invalidation Queue Head Register (IQH_REG).
1318 * In accordance with the Intel spec.
1319 * @{ */
1320/** R: Reserved (bits 3:0). */
1321#define VTD_BF_IQH_REG_RSVD_3_0_SHIFT 0
1322#define VTD_BF_IQH_REG_RSVD_3_0_MASK UINT64_C(0x000000000000000f)
1323/** QH: Queue Head. */
1324#define VTD_BF_IQH_REG_QH_SHIFT 4
1325#define VTD_BF_IQH_REG_QH_MASK UINT64_C(0x000000000007fff0)
1326/** R: Reserved (bits 63:19). */
1327#define VTD_BF_IQH_REG_RSVD_63_19_SHIFT 19
1328#define VTD_BF_IQH_REG_RSVD_63_19_MASK UINT64_C(0xfffffffffff80000)
1329RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IQH_REG_, UINT64_C(0), UINT64_MAX,
1330 (RSVD_3_0, QH, RSVD_63_19));
1331
1332/** RW: Read/write mask. */
1333#define VTD_IQH_REG_RW_MASK UINT64_C(0x0)
1334/** @} */
1335
1336
1337/** @name Invalidation Queue Tail Register (IQT_REG).
1338 * In accordance with the Intel spec.
1339 * @{ */
1340/** R: Reserved (bits 3:0). */
1341#define VTD_BF_IQT_REG_RSVD_3_0_SHIFT 0
1342#define VTD_BF_IQT_REG_RSVD_3_0_MASK UINT64_C(0x000000000000000f)
1343/** QH: Queue Tail. */
1344#define VTD_BF_IQT_REG_QT_SHIFT 4
1345#define VTD_BF_IQT_REG_QT_MASK UINT64_C(0x000000000007fff0)
1346/** R: Reserved (bits 63:19). */
1347#define VTD_BF_IQT_REG_RSVD_63_19_SHIFT 19
1348#define VTD_BF_IQT_REG_RSVD_63_19_MASK UINT64_C(0xfffffffffff80000)
1349RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IQT_REG_, UINT64_C(0), UINT64_MAX,
1350 (RSVD_3_0, QT, RSVD_63_19));
1351
1352/** RW: Read/write mask. */
1353#define VTD_IQT_REG_RW_MASK VTD_BF_IQT_REG_QT_MASK
1354
1355/** IQT_REG.QT: Gets the queue tail. */
1356#define VTD_IQT_REG_GET_QT(a) ((a) & (VTD_BF_IQT_REG_QT_MASK | VTD_BF_IQT_REG_RSVD_3_0_MASK))
1357/** @} */
1358
1359
1360/** @name Invalidation Queue Address Register (IQA_REG).
1361 * In accordance with the Intel spec.
1362 * @{ */
1363/** QS: Queue Size. */
1364#define VTD_BF_IQA_REG_QS_SHIFT 0
1365#define VTD_BF_IQA_REG_QS_MASK UINT64_C(0x0000000000000007)
1366/** R: Reserved (bits 10:3). */
1367#define VTD_BF_IQA_REG_RSVD_10_3_SHIFT 3
1368#define VTD_BF_IQA_REG_RSVD_10_3_MASK UINT64_C(0x00000000000007f8)
1369/** DW: Descriptor Width. */
1370#define VTD_BF_IQA_REG_DW_SHIFT 11
1371#define VTD_BF_IQA_REG_DW_MASK UINT64_C(0x0000000000000800)
1372/** IQA: Invalidation Queue Base Address. */
1373#define VTD_BF_IQA_REG_IQA_SHIFT 12
1374#define VTD_BF_IQA_REG_IQA_MASK UINT64_C(0xfffffffffffff000)
1375RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IQA_REG_, UINT64_C(0), UINT64_MAX,
1376 (QS, RSVD_10_3, DW, IQA));
1377
1378/** RW: Read/write mask. */
1379#define VTD_IQA_REG_RW_MASK ( VTD_BF_IQA_REG_QS_MASK | VTD_BF_IQA_REG_DW_MASK \
1380 | VTD_BF_IQA_REG_IQA_MASK)
1381/** DW: 128-bit descriptor. */
1382#define VTD_IQA_REG_DW_128_BIT 0
1383/** DW: 256-bit descriptor. */
1384#define VTD_IQA_REG_DW_256_BIT 1
1385/** @} */
1386
1387
1388/** @name Invalidation Completion Status Register (ICS_REG).
1389 * In accordance with the Intel spec.
1390 * @{ */
1391/** IWC: Invalidation Wait Descriptor Complete. */
1392#define VTD_BF_ICS_REG_IWC_SHIFT 0
1393#define VTD_BF_ICS_REG_IWC_MASK UINT32_C(0x00000001)
1394/** R: Reserved (bits 31:1). */
1395#define VTD_BF_ICS_REG_RSVD_31_1_SHIFT 1
1396#define VTD_BF_ICS_REG_RSVD_31_1_MASK UINT32_C(0xfffffffe)
1397RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_ICS_REG_, UINT32_C(0), UINT32_MAX,
1398 (IWC, RSVD_31_1));
1399
1400/** RW: Read/write mask. */
1401#define VTD_ICS_REG_RW_MASK VTD_BF_ICS_REG_IWC_MASK
1402/** RW1C: Read-only-status, Write-1-to-clear status mask. */
1403#define VTD_ICS_REG_RW1C_MASK VTD_BF_ICS_REG_IWC_MASK
1404/** @} */
1405
1406
1407/** @name Invalidation Event Control Register (IECTL_REG).
1408 * In accordance with the Intel spec.
1409 * @{ */
1410/** R: Reserved (bits 29:0). */
1411#define VTD_BF_IECTL_REG_RSVD_29_0_SHIFT 0
1412#define VTD_BF_IECTL_REG_RSVD_29_0_MASK UINT32_C(0x3fffffff)
1413/** IP: Interrupt Pending. */
1414#define VTD_BF_IECTL_REG_IP_SHIFT 30
1415#define VTD_BF_IECTL_REG_IP_MASK UINT32_C(0x40000000)
1416/** IM: Interrupt Mask. */
1417#define VTD_BF_IECTL_REG_IM_SHIFT 31
1418#define VTD_BF_IECTL_REG_IM_MASK UINT32_C(0x80000000)
1419RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IECTL_REG_, UINT32_C(0), UINT32_MAX,
1420 (RSVD_29_0, IP, IM));
1421
1422/** RW: Read/write mask. */
1423#define VTD_IECTL_REG_RW_MASK VTD_BF_IECTL_REG_IM_MASK
1424/** @} */
1425
1426
1427/** @name Invalidation Event Data Register (IEDATA_REG).
1428 * In accordance with the Intel spec.
1429 * @{ */
1430/** IMD: Interrupt Message Data. */
1431#define VTD_BF_IEDATA_REG_IMD_SHIFT 0
1432#define VTD_BF_IEDATA_REG_IMD_MASK UINT32_C(0x0000ffff)
1433/** R: Reserved (bits 31:16). VT-d specs. prior to 2021 had EIMD here. */
1434#define VTD_BF_IEDATA_REG_RSVD_31_16_SHIFT 16
1435#define VTD_BF_IEDATA_REG_RSVD_31_16_MASK UINT32_C(0xffff0000)
1436RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IEDATA_REG_, UINT32_C(0), UINT32_MAX,
1437 (IMD, RSVD_31_16));
1438
1439/** RW: Read/write mask. */
1440#define VTD_IEDATA_REG_RW_MASK VTD_BF_IEDATA_REG_IMD_MASK
1441/** @} */
1442
1443
1444/** @name Invalidation Event Address Register (IEADDR_REG).
1445 * In accordance with the Intel spec.
1446 * @{ */
1447/** R: Reserved (bits 1:0). */
1448#define VTD_BF_IEADDR_REG_RSVD_1_0_SHIFT 0
1449#define VTD_BF_IEADDR_REG_RSVD_1_0_MASK UINT32_C(0x00000003)
1450/** MA: Message Address. */
1451#define VTD_BF_IEADDR_REG_MA_SHIFT 2
1452#define VTD_BF_IEADDR_REG_MA_MASK UINT32_C(0xfffffffc)
1453RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IEADDR_REG_, UINT32_C(0), UINT32_MAX,
1454 (RSVD_1_0, MA));
1455
1456/** RW: Read/write mask. */
1457#define VTD_IEADDR_REG_RW_MASK VTD_BF_IEADDR_REG_MA_MASK
1458/** @} */
1459
1460
1461/** @name Invalidation Event Upper Address Register (IEUADDR_REG).
1462 * @{ */
1463/** MUA: Message Upper Address. */
1464#define VTD_BF_IEUADDR_REG_MUA_SHIFT 0
1465#define VTD_BF_IEUADDR_REG_MUA_MASK UINT32_C(0xffffffff)
1466
1467/** RW: Read/write mask. */
1468#define VTD_IEUADDR_REG_RW_MASK VTD_BF_IEUADDR_REG_MUA_MASK
1469/** @} */
1470
1471
1472/** @name Invalidation Queue Error Record Register (IQERCD_REG).
1473 * In accordance with the Intel spec.
1474 * @{ */
1475/** IQEI: Invalidation Queue Error Info. */
1476#define VTD_BF_IQERCD_REG_IQEI_SHIFT 0
1477#define VTD_BF_IQERCD_REG_IQEI_MASK UINT64_C(0x000000000000000f)
1478/** R: Reserved (bits 31:4). */
1479#define VTD_BF_IQERCD_REG_RSVD_31_4_SHIFT 4
1480#define VTD_BF_IQERCD_REG_RSVD_31_4_MASK UINT64_C(0x00000000fffffff0)
1481/** ITESID: Invalidation Timeout Error Source Identifier. */
1482#define VTD_BF_IQERCD_REG_ITESID_SHIFT 32
1483#define VTD_BF_IQERCD_REG_ITESID_MASK UINT64_C(0x0000ffff00000000)
1484/** ICESID: Invalidation Completion Error Source Identifier. */
1485#define VTD_BF_IQERCD_REG_ICESID_SHIFT 48
1486#define VTD_BF_IQERCD_REG_ICESID_MASK UINT64_C(0xffff000000000000)
1487RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IQERCD_REG_, UINT64_C(0), UINT64_MAX,
1488 (IQEI, RSVD_31_4, ITESID, ICESID));
1489
1490/** RW: Read/write mask. */
1491#define VTD_IQERCD_REG_RW_MASK UINT64_C(0)
1492/** @} */
1493
1494
1495/** @name Interrupt Remapping Table Address Register (IRTA_REG).
1496 * In accordance with the Intel spec.
1497 * @{ */
1498/** S: Size. */
1499#define VTD_BF_IRTA_REG_S_SHIFT 0
1500#define VTD_BF_IRTA_REG_S_MASK UINT64_C(0x000000000000000f)
1501/** R: Reserved (bits 10:4). */
1502#define VTD_BF_IRTA_REG_RSVD_10_4_SHIFT 4
1503#define VTD_BF_IRTA_REG_RSVD_10_4_MASK UINT64_C(0x00000000000007f0)
1504/** EIME: Extended Interrupt Mode Enable. */
1505#define VTD_BF_IRTA_REG_EIME_SHIFT 11
1506#define VTD_BF_IRTA_REG_EIME_MASK UINT64_C(0x0000000000000800)
1507/** IRTA: Interrupt Remapping Table Address. */
1508#define VTD_BF_IRTA_REG_IRTA_SHIFT 12
1509#define VTD_BF_IRTA_REG_IRTA_MASK UINT64_C(0xfffffffffffff000)
1510RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IRTA_REG_, UINT64_C(0), UINT64_MAX,
1511 (S, RSVD_10_4, EIME, IRTA));
1512
1513/** RW: Read/write mask. */
1514#define VTD_IRTA_REG_RW_MASK ( VTD_BF_IRTA_REG_S_MASK | VTD_BF_IRTA_REG_EIME_MASK \
1515 | VTD_BF_IRTA_REG_IRTA_MASK)
1516/** @} */
1517
1518
1519/** @name Page Request Queue Head Register (PQH_REG).
1520 * In accordance with the Intel spec.
1521 * @{ */
1522/** R: Reserved (bits 4:0). */
1523#define VTD_BF_PQH_REG_RSVD_4_0_SHIFT 0
1524#define VTD_BF_PQH_REG_RSVD_4_0_MASK UINT64_C(0x000000000000001f)
1525/** PQH: Page Queue Head. */
1526#define VTD_BF_PQH_REG_PQH_SHIFT 5
1527#define VTD_BF_PQH_REG_PQH_MASK UINT64_C(0x000000000007ffe0)
1528/** R: Reserved (bits 63:19). */
1529#define VTD_BF_PQH_REG_RSVD_63_19_SHIFT 19
1530#define VTD_BF_PQH_REG_RSVD_63_19_MASK UINT64_C(0xfffffffffff80000)
1531RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_PQH_REG_, UINT64_C(0), UINT64_MAX,
1532 (RSVD_4_0, PQH, RSVD_63_19));
1533
1534/** RW: Read/write mask. */
1535#define VTD_PQH_REG_RW_MASK VTD_BF_PQH_REG_PQH_MASK
1536/** @} */
1537
1538
1539/** @name Page Request Queue Tail Register (PQT_REG).
1540 * In accordance with the Intel spec.
1541 * @{ */
1542/** R: Reserved (bits 4:0). */
1543#define VTD_BF_PQT_REG_RSVD_4_0_SHIFT 0
1544#define VTD_BF_PQT_REG_RSVD_4_0_MASK UINT64_C(0x000000000000001f)
1545/** PQT: Page Queue Tail. */
1546#define VTD_BF_PQT_REG_PQT_SHIFT 5
1547#define VTD_BF_PQT_REG_PQT_MASK UINT64_C(0x000000000007ffe0)
1548/** R: Reserved (bits 63:19). */
1549#define VTD_BF_PQT_REG_RSVD_63_19_SHIFT 19
1550#define VTD_BF_PQT_REG_RSVD_63_19_MASK UINT64_C(0xfffffffffff80000)
1551RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_PQT_REG_, UINT64_C(0), UINT64_MAX,
1552 (RSVD_4_0, PQT, RSVD_63_19));
1553
1554/** RW: Read/write mask. */
1555#define VTD_PQT_REG_RW_MASK VTD_BF_PQT_REG_PQT_MASK
1556/** @} */
1557
1558
1559/** @name Page Request Queue Address Register (PQA_REG).
1560 * In accordance with the Intel spec.
1561 * @{ */
1562/** PQS: Page Queue Size. */
1563#define VTD_BF_PQA_REG_PQS_SHIFT 0
1564#define VTD_BF_PQA_REG_PQS_MASK UINT64_C(0x0000000000000007)
1565/** R: Reserved bits (11:3). */
1566#define VTD_BF_PQA_REG_RSVD_11_3_SHIFT 3
1567#define VTD_BF_PQA_REG_RSVD_11_3_MASK UINT64_C(0x0000000000000ff8)
1568/** PQA: Page Request Queue Base Address. */
1569#define VTD_BF_PQA_REG_PQA_SHIFT 12
1570#define VTD_BF_PQA_REG_PQA_MASK UINT64_C(0xfffffffffffff000)
1571RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_PQA_REG_, UINT64_C(0), UINT64_MAX,
1572 (PQS, RSVD_11_3, PQA));
1573
1574/** RW: Read/write mask. */
1575#define VTD_PQA_REG_RW_MASK (VTD_BF_PQA_REG_PQS_MASK | VTD_BF_PQA_REG_PQA_MASK)
1576/** @} */
1577
1578
1579/** @name Page Request Status Register (PRS_REG).
1580 * In accordance with the Intel spec.
1581 * @{ */
1582/** PPR: Pending Page Request. */
1583#define VTD_BF_PRS_REG_PPR_SHIFT 0
1584#define VTD_BF_PRS_REG_PPR_MASK UINT64_C(0x00000001)
1585/** PRO: Page Request Overflow. */
1586#define VTD_BF_PRS_REG_PRO_SHIFT 1
1587#define VTD_BF_PRS_REG_PRO_MASK UINT64_C(0x00000002)
1588/** R: Reserved (bits 31:2). */
1589#define VTD_BF_PRS_REG_RSVD_31_2_SHIFT 2
1590#define VTD_BF_PRS_REG_RSVD_31_2_MASK UINT64_C(0xfffffffc)
1591RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_PRS_REG_, UINT32_C(0), UINT32_MAX,
1592 (PPR, PRO, RSVD_31_2));
1593
1594/** RW: Read/write mask. */
1595#define VTD_PRS_REG_RW_MASK (VTD_BF_PRS_REG_PPR_MASK | VTD_BF_PRS_REG_PRO_MASK)
1596/** RW1C: Read-only-status, Write-1-to-clear status mask. */
1597#define VTD_PRS_REG_RW1C_MASK (VTD_BF_PRS_REG_PPR_MASK | VTD_BF_PRS_REG_PRO_MASK)
1598/** @} */
1599
1600
1601/** @name Page Request Event Control Register (PECTL_REG).
1602 * In accordance with the Intel spec.
1603 * @{ */
1604/** R: Reserved (bits 29:0). */
1605#define VTD_BF_PECTL_REG_RSVD_29_0_SHIFT 0
1606#define VTD_BF_PECTL_REG_RSVD_29_0_MASK UINT32_C(0x3fffffff)
1607/** IP: Interrupt Pending. */
1608#define VTD_BF_PECTL_REG_IP_SHIFT 30
1609#define VTD_BF_PECTL_REG_IP_MASK UINT32_C(0x40000000)
1610/** IM: Interrupt Mask. */
1611#define VTD_BF_PECTL_REG_IM_SHIFT 31
1612#define VTD_BF_PECTL_REG_IM_MASK UINT32_C(0x80000000)
1613RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_PECTL_REG_, UINT32_C(0), UINT32_MAX,
1614 (RSVD_29_0, IP, IM));
1615
1616/** RW: Read/write mask. */
1617#define VTD_PECTL_REG_RW_MASK VTD_BF_PECTL_REG_IM_MASK
1618/** @} */
1619
1620
1621/** @name Page Request Event Data Register (PEDATA_REG).
1622 * In accordance with the Intel spec.
1623 * @{ */
1624/** IMD: Interrupt Message Data. */
1625#define VTD_BF_PEDATA_REG_IMD_SHIFT 0
1626#define VTD_BF_PEDATA_REG_IMD_MASK UINT32_C(0x0000ffff)
1627/** R: Reserved (bits 31:16). VT-d specs. prior to 2021 had EIMD here. */
1628#define VTD_BF_PEDATA_REG_RSVD_31_16_SHIFT 16
1629#define VTD_BF_PEDATA_REG_RSVD_31_16_MASK UINT32_C(0xffff0000)
1630RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_PEDATA_REG_, UINT32_C(0), UINT32_MAX,
1631 (IMD, RSVD_31_16));
1632
1633/** RW: Read/write mask. */
1634#define VTD_PEDATA_REG_RW_MASK VTD_BF_PEDATA_REG_IMD_MASK
1635/** @} */
1636
1637
1638/** @name Page Request Event Address Register (PEADDR_REG).
1639 * In accordance with the Intel spec.
1640 * @{ */
1641/** R: Reserved (bits 1:0). */
1642#define VTD_BF_PEADDR_REG_RSVD_1_0_SHIFT 0
1643#define VTD_BF_PEADDR_REG_RSVD_1_0_MASK UINT32_C(0x00000003)
1644/** MA: Message Address. */
1645#define VTD_BF_PEADDR_REG_MA_SHIFT 2
1646#define VTD_BF_PEADDR_REG_MA_MASK UINT32_C(0xfffffffc)
1647RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_PEADDR_REG_, UINT32_C(0), UINT32_MAX,
1648 (RSVD_1_0, MA));
1649
1650/** RW: Read/write mask. */
1651#define VTD_PEADDR_REG_RW_MASK VTD_BF_PEADDR_REG_MA_MASK
1652/** @} */
1653
1654
1655
1656/** @name Page Request Event Upper Address Register (PEUADDR_REG).
1657 * In accordance with the Intel spec.
1658 * @{ */
1659/** MA: Message Address. */
1660#define VTD_BF_PEUADDR_REG_MUA_SHIFT 0
1661#define VTD_BF_PEUADDR_REG_MUA_MASK UINT32_C(0xffffffff)
1662
1663/** RW: Read/write mask. */
1664#define VTD_PEUADDR_REG_RW_MASK VTD_BF_PEUADDR_REG_MUA_MASK
1665/** @} */
1666
1667
1668/** @name MTRR Capability Register (MTRRCAP_REG).
1669 * In accordance with the Intel spec.
1670 * @{ */
1671/** VCNT: Variable MTRR Count. */
1672#define VTD_BF_MTRRCAP_REG_VCNT_SHIFT 0
1673#define VTD_BF_MTRRCAP_REG_VCNT_MASK UINT64_C(0x00000000000000ff)
1674/** FIX: Fixed range MTRRs Supported. */
1675#define VTD_BF_MTRRCAP_REG_FIX_SHIFT 8
1676#define VTD_BF_MTRRCAP_REG_FIX_MASK UINT64_C(0x0000000000000100)
1677/** R: Reserved (bit 9). */
1678#define VTD_BF_MTRRCAP_REG_RSVD_9_SHIFT 9
1679#define VTD_BF_MTRRCAP_REG_RSVD_9_MASK UINT64_C(0x0000000000000200)
1680/** WC: Write Combining. */
1681#define VTD_BF_MTRRCAP_REG_WC_SHIFT 10
1682#define VTD_BF_MTRRCAP_REG_WC_MASK UINT64_C(0x0000000000000400)
1683/** R: Reserved (bits 63:11). */
1684#define VTD_BF_MTRRCAP_REG_RSVD_63_11_SHIFT 11
1685#define VTD_BF_MTRRCAP_REG_RSVD_63_11_MASK UINT64_C(0xfffffffffffff800)
1686RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_MTRRCAP_REG_, UINT64_C(0), UINT64_MAX,
1687 (VCNT, FIX, RSVD_9, WC, RSVD_63_11));
1688
1689/** RW: Read/write mask. */
1690#define VTD_MTRRCAP_REG_RW_MASK UINT64_C(0)
1691/** @} */
1692
1693
1694/** @name MTRR Default Type Register (MTRRDEF_REG).
1695 * In accordance with the Intel spec.
1696 * @{ */
1697/** TYPE: Default Memory Type. */
1698#define VTD_BF_MTRRDEF_REG_TYPE_SHIFT 0
1699#define VTD_BF_MTRRDEF_REG_TYPE_MASK UINT64_C(0x00000000000000ff)
1700/** R: Reserved (bits 9:8). */
1701#define VTD_BF_MTRRDEF_REG_RSVD_9_8_SHIFT 8
1702#define VTD_BF_MTRRDEF_REG_RSVD_9_8_MASK UINT64_C(0x0000000000000300)
1703/** FE: Fixed Range MTRR Enable. */
1704#define VTD_BF_MTRRDEF_REG_FE_SHIFT 10
1705#define VTD_BF_MTRRDEF_REG_FE_MASK UINT64_C(0x0000000000000400)
1706/** E: MTRR Enable. */
1707#define VTD_BF_MTRRDEF_REG_E_SHIFT 11
1708#define VTD_BF_MTRRDEF_REG_E_MASK UINT64_C(0x0000000000000800)
1709/** R: Reserved (bits 63:12). */
1710#define VTD_BF_MTRRDEF_REG_RSVD_63_12_SHIFT 12
1711#define VTD_BF_MTRRDEF_REG_RSVD_63_12_MASK UINT64_C(0xfffffffffffff000)
1712RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_MTRRDEF_REG_, UINT64_C(0), UINT64_MAX,
1713 (TYPE, RSVD_9_8, FE, E, RSVD_63_12));
1714
1715/** RW: Read/write mask. */
1716#define VTD_MTRRDEF_REG_RW_MASK ( VTD_BF_MTRRDEF_REG_TYPE_MASK | VTD_BF_MTRRDEF_REG_FE_MASK \
1717 | VTD_BF_MTRRDEF_REG_E_MASK)
1718/** @} */
1719
1720
1721/** @name Virtual Command Capability Register (VCCAP_REG).
1722 * In accordance with the Intel spec.
1723 * @{ */
1724/** PAS: PASID Support. */
1725#define VTD_BF_VCCAP_REG_PAS_SHIFT 0
1726#define VTD_BF_VCCAP_REG_PAS_MASK UINT64_C(0x0000000000000001)
1727/** R: Reserved (bits 63:1). */
1728#define VTD_BF_VCCAP_REG_RSVD_63_1_SHIFT 1
1729#define VTD_BF_VCCAP_REG_RSVD_63_1_MASK UINT64_C(0xfffffffffffffffe)
1730RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_VCCAP_REG_, UINT64_C(0), UINT64_MAX,
1731 (PAS, RSVD_63_1));
1732
1733/** RW: Read/write mask. */
1734#define VTD_VCCAP_REG_RW_MASK UINT64_C(0)
1735/** @} */
1736
1737
1738/** @name Virtual Command Extended Operand Register (VCMD_EO_REG).
1739 * In accordance with the Intel spec.
1740 * @{ */
1741/** OB: Operand B. */
1742#define VTD_BF_VCMD_EO_REG_OB_SHIFT 0
1743#define VTD_BF_VCMD_EO_REG_OB_MASK UINT32_C(0xffffffffffffffff)
1744
1745/** RW: Read/write mask. */
1746#define VTD_VCMD_EO_REG_RW_MASK VTD_BF_VCMD_EO_REG_OB_MASK
1747/** @} */
1748
1749
1750/** @name Virtual Command Register (VCMD_REG).
1751 * In accordance with the Intel spec.
1752 * @{ */
1753/** CMD: Command. */
1754#define VTD_BF_VCMD_REG_CMD_SHIFT 0
1755#define VTD_BF_VCMD_REG_CMD_MASK UINT64_C(0x00000000000000ff)
1756/** OP: Operand. */
1757#define VTD_BF_VCMD_REG_OP_SHIFT 8
1758#define VTD_BF_VCMD_REG_OP_MASK UINT64_C(0xffffffffffffff00)
1759RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_VCMD_REG_, UINT64_C(0), UINT64_MAX,
1760 (CMD, OP));
1761
1762/** RW: Read/write mask. */
1763#define VTD_VCMD_REG_RW_MASK (VTD_BF_VCMD_REG_CMD_MASK | VTD_BF_VCMD_REG_OP_MASK)
1764/** @} */
1765
1766
1767/** @name Virtual Command Response Register (VCRSP_REG).
1768 * In accordance with the Intel spec.
1769 * @{ */
1770/** IP: In Progress. */
1771#define VTD_BF_VCRSP_REG_IP_SHIFT 0
1772#define VTD_BF_VCRSP_REG_IP_MASK UINT64_C(0x0000000000000001)
1773/** SC: Status Code. */
1774#define VTD_BF_VCRSP_REG_SC_SHIFT 1
1775#define VTD_BF_VCRSP_REG_SC_MASK UINT64_C(0x0000000000000006)
1776/** R: Reserved (bits 7:3). */
1777#define VTD_BF_VCRSP_REG_RSVD_7_3_SHIFT 3
1778#define VTD_BF_VCRSP_REG_RSVD_7_3_MASK UINT64_C(0x00000000000000f8)
1779/** RSLT: Result. */
1780#define VTD_BF_VCRSP_REG_RSLT_SHIFT 8
1781#define VTD_BF_VCRSP_REG_RSLT_MASK UINT64_C(0xffffffffffffff00)
1782RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_VCRSP_REG_, UINT64_C(0), UINT64_MAX,
1783 (IP, SC, RSVD_7_3, RSLT));
1784
1785/** RW: Read/write mask. */
1786#define VTD_VCRSP_REG_RW_MASK UINT64_C(0)
1787/** @} */
1788
1789
1790/** @name ACPI_DMAR_F_XXX: DMA Remapping Reporting Structure Flags.
1791 * In accordance with the Intel spec.
1792 * @{ */
1793/** INTR_REMAP: Interrupt remapping supported. */
1794#define ACPI_DMAR_F_INTR_REMAP RT_BIT(0)
1795/** X2APIC_OPT_OUT: Request system software to opt-out of enabling x2APIC. */
1796#define ACPI_DMAR_F_X2APIC_OPT_OUT RT_BIT(1)
1797/** DMA_CTRL_PLATFORM_OPT_IN_FLAG: Firmware initiated DMA restricted to reserved
1798 * memory regions (RMRR). */
1799#define ACPI_DMAR_F_DMA_CTRL_PLATFORM_OPT_IN RT_BIT(2)
1800/** @} */
1801
1802
1803/** @name ACPI_DRHD_F_XXX: DMA-Remapping Hardware Unit Definition Flags.
1804 * In accordance with the Intel spec.
1805 * @{ */
1806/** INCLUDE_PCI_ALL: All PCI devices under scope. */
1807#define ACPI_DRHD_F_INCLUDE_PCI_ALL RT_BIT(0)
1808/** @} */
1809
1810
1811/**
1812 * DRHD: DMA-Remapping Hardware Unit Definition.
1813 * In accordance with the Intel spec.
1814 */
1815#pragma pack(1)
1816typedef struct ACPIDRHD
1817{
1818 /** Type (must be 0=DRHD). */
1819 uint16_t uType;
1820 /** Length (must be 16 + size of device scope structure). */
1821 uint16_t cbLength;
1822 /** Flags, see ACPI_DRHD_F_XXX. */
1823 uint8_t fFlags;
1824 /** Reserved (MBZ). */
1825 uint8_t bRsvd;
1826 /** PCI segment number. */
1827 uint16_t uPciSegment;
1828 /** Register Base Address (MMIO). */
1829 uint64_t uRegBaseAddr;
1830 /* Device Scope[] Structures follow. */
1831} ACPIDRHD;
1832#pragma pack()
1833AssertCompileSize(ACPIDRHD, 16);
1834AssertCompileMemberOffset(ACPIDRHD, cbLength, 2);
1835AssertCompileMemberOffset(ACPIDRHD, fFlags, 4);
1836AssertCompileMemberOffset(ACPIDRHD, uPciSegment, 6);
1837AssertCompileMemberOffset(ACPIDRHD, uRegBaseAddr, 8);
1838
1839
1840/** @name ACPIDMARDEVSCOPE_TYPE_XXX: Device Type.
1841 * In accordance with the Intel spec.
1842 * @{ */
1843#define ACPIDMARDEVSCOPE_TYPE_PCI_ENDPOINT 1
1844#define ACPIDMARDEVSCOPE_TYPE_PCI_SUB_HIERARCHY 2
1845#define ACPIDMARDEVSCOPE_TYPE_IOAPIC 3
1846#define ACPIDMARDEVSCOPE_TYPE_MSI_CAP_HPET 4
1847#define ACPIDMARDEVSCOPE_TYPE_ACPI_NAMESPACE_DEV 5
1848/** @} */
1849
1850
1851/**
1852 * ACPI Device Scope Structure - PCI device path.
1853 * In accordance with the Intel spec.
1854 */
1855typedef struct ACPIDEVSCOPEPATH
1856{
1857 /** PCI device number. */
1858 uint8_t uDevice;
1859 /** PCI function number. */
1860 uint8_t uFunction;
1861} ACPIDEVSCOPEPATH;
1862AssertCompileSize(ACPIDEVSCOPEPATH, 2);
1863
1864
1865/**
1866 * Device Scope Structure.
1867 * In accordance with the Intel spec.
1868 */
1869#pragma pack(1)
1870typedef struct ACPIDMARDEVSCOPE
1871{
1872 /** Type, see ACPIDMARDEVSCOPE_TYPE_XXX. */
1873 uint8_t uType;
1874 /** Length (must be 6 + size of auPath field). */
1875 uint8_t cbLength;
1876 /** Reserved (MBZ). */
1877 uint8_t abRsvd[2];
1878 /** Enumeration ID (for I/O APIC, HPET and ACPI namespace devices). */
1879 uint8_t idEnum;
1880 /** First bus number for this device. */
1881 uint8_t uStartBusNum;
1882 /** Hierarchical path from the Host Bridge to the device. */
1883 ACPIDEVSCOPEPATH Path;
1884} ACPIDMARDEVSCOPE;
1885#pragma pack()
1886AssertCompileMemberOffset(ACPIDMARDEVSCOPE, cbLength, 1);
1887AssertCompileMemberOffset(ACPIDMARDEVSCOPE, idEnum, 4);
1888AssertCompileMemberOffset(ACPIDMARDEVSCOPE, uStartBusNum, 5);
1889AssertCompileMemberOffset(ACPIDMARDEVSCOPE, Path, 6);
1890
1891/** ACPI DMAR revision (not the OEM revision field).
1892 * In accordance with the Intel spec. */
1893#define ACPI_DMAR_REVISION 1
1894
1895
1896#endif /* !VBOX_INCLUDED_iommu_intel_h */
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