iommu-intel.h@ 88841

Last change on this file since 88841 was 88841, checked in by vboxsync, 4 years ago
Intel IOMMU: bugref:9967 Interrupt remapping WIP.
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 122.4 KB

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1	/** @file
2	* IOMMU - Input/Output Memory Management Unit (Intel).
3	*/
4
5	/*
6	* Copyright (C) 2021 Oracle Corporation
7	*
8	* This file is part of VirtualBox Open Source Edition (OSE), as
9	* available from http://www.virtualbox.org. This file is free software;
10	* you can redistribute it and/or modify it under the terms of the GNU
11	* General Public License (GPL) as published by the Free Software
12	* Foundation, in version 2 as it comes in the "COPYING" file of the
13	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15	*
16	* The contents of this file may alternatively be used under the terms
17	* of the Common Development and Distribution License Version 1.0
18	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19	* VirtualBox OSE distribution, in which case the provisions of the
20	* CDDL are applicable instead of those of the GPL.
21	*
22	* You may elect to license modified versions of this file under the
23	* terms and conditions of either the GPL or the CDDL or both.
24	*/
25
26	#ifndef VBOX_INCLUDED_iommu_intel_h
27	#define VBOX_INCLUDED_iommu_intel_h
28	#ifndef RT_WITHOUT_PRAGMA_ONCE
29	# pragma once
30	#endif
31
32	#include <iprt/assertcompile.h>
33	#include <iprt/types.h>
34
35
36	/**
37	* @name MMIO register offsets.
38	* In accordance with the Intel spec.
39	* @{
40	*/
41	#define VTD_MMIO_OFF_VER_REG 0x000 /*< Version. /
42	#define VTD_MMIO_OFF_CAP_REG 0x008 /*< Capability. /
43	#define VTD_MMIO_OFF_ECAP_REG 0x010 /*< Extended Capability. /
44	#define VTD_MMIO_OFF_GCMD_REG 0x018 /*< Global Command. /
45	#define VTD_MMIO_OFF_GSTS_REG 0x01c /*< Global Status. /
46	#define VTD_MMIO_OFF_RTADDR_REG 0x020 /*< Root Table Address. /
47	#define VTD_MMIO_OFF_CCMD_REG 0x028 /*< Context Command. /
48
49	#define VTD_MMIO_OFF_FSTS_REG 0x034 /*< Fault Status./
50	#define VTD_MMIO_OFF_FECTL_REG 0x038 /*< Fault Event Control./
51	#define VTD_MMIO_OFF_FEDATA_REG 0x03c /*< Fault Event Data. /
52	#define VTD_MMIO_OFF_FEADDR_REG 0x040 /*< Fault Event Address. /
53	#define VTD_MMIO_OFF_FEUADDR_REG 0x044 /*< Fault Event Upper Address. /
54
55	#define VTD_MMIO_OFF_AFLOG_REG 0x058 /*< Advance Fault Log. /
56
57	#define VTD_MMIO_OFF_PMEN_REG 0x064 /*< Protected Memory Enable (PMEN). /
58	#define VTD_MMIO_OFF_PLMBASE_REG 0x068 /*< Protected Low Memory Base. /
59	#define VTD_MMIO_OFF_PLMLIMIT_REG 0x06c /*< Protected Low Memory Limit. /
60	#define VTD_MMIO_OFF_PHMBASE_REG 0x070 /*< Protected High Memory Base. /
61	#define VTD_MMIO_OFF_PHMLIMIT_REG 0x078 /*< Protected High Memory Limit. /
62
63	#define VTD_MMIO_OFF_IQH_REG 0x080 /*< Invalidation Queue Head. /
64	#define VTD_MMIO_OFF_IQT_REG 0x088 /*< Invalidation Queue Tail. /
65	#define VTD_MMIO_OFF_IQA_REG 0x090 /*< Invalidation Queue Address. /
66	#define VTD_MMIO_OFF_ICS_REG 0x09c /*< Invalidation Completion Status. /
67	#define VTD_MMIO_OFF_IECTL_REG 0x0a0 /*< Invalidation Completion Event Control. /
68	#define VTD_MMIO_OFF_IEDATA_REG 0x0a4 /*< Invalidation Completion Event Data. /
69	#define VTD_MMIO_OFF_IEADDR_REG 0x0a8 /*< Invalidation Completion Event Address. /
70	#define VTD_MMIO_OFF_IEUADDR_REG 0x0ac /*< Invalidation Completion Event Upper Address. /
71	#define VTD_MMIO_OFF_IQERCD_REG 0x0b0 /*< Invalidation Queue Error Record. /
72
73	#define VTD_MMIO_OFF_IRTA_REG 0x0b8 /*< Interrupt Remapping Table Address. /
74
75	#define VTD_MMIO_OFF_PQH_REG 0x0c0 /*< Page Request Queue Head. /
76	#define VTD_MMIO_OFF_PQT_REG 0x0c8 /*< Page Request Queue Tail. /
77	#define VTD_MMIO_OFF_PQA_REG 0x0d0 /*< Page Request Queue Address. /
78	#define VTD_MMIO_OFF_PRS_REG 0x0dc /*< Page Request Status. /
79	#define VTD_MMIO_OFF_PECTL_REG 0x0e0 /*< Page Request Event Control. /
80	#define VTD_MMIO_OFF_PEDATA_REG 0x0e4 /*< Page Request Event Data. /
81	#define VTD_MMIO_OFF_PEADDR_REG 0x0e8 /*< Page Request Event Address. /
82	#define VTD_MMIO_OFF_PEUADDR_REG 0x0ec /*< Page Request Event Upper Address. /
83
84	#define VTD_MMIO_OFF_MTRRCAP_REG 0x100 /*< MTRR Capabliity. /
85	#define VTD_MMIO_OFF_MTRRDEF_REG 0x108 /*< MTRR Default Type. /
86
87	#define VTD_MMIO_OFF_MTRR_FIX64_00000_REG 0x120 /*< Fixed-range MTRR Register for 64K at 00000. /
88	#define VTD_MMIO_OFF_MTRR_FIX16K_80000_REG 0x128 /*< Fixed-range MTRR Register for 16K at 80000. /
89	#define VTD_MMIO_OFF_MTRR_FIX16K_A0000_REG 0x130 /*< Fixed-range MTRR Register for 16K at a0000. /
90	#define VTD_MMIO_OFF_MTRR_FIX4K_C0000_REG 0x138 /*< Fixed-range MTRR Register for 4K at c0000. /
91	#define VTD_MMIO_OFF_MTRR_FIX4K_C8000_REG 0x140 /*< Fixed-range MTRR Register for 4K at c8000. /
92	#define VTD_MMIO_OFF_MTRR_FIX4K_D0000_REG 0x148 /*< Fixed-range MTRR Register for 4K at d0000. /
93	#define VTD_MMIO_OFF_MTRR_FIX4K_D8000_REG 0x150 /*< Fixed-range MTRR Register for 4K at d8000. /
94	#define VTD_MMIO_OFF_MTRR_FIX4K_E0000_REG 0x158 /*< Fixed-range MTRR Register for 4K at e0000. /
95	#define VTD_MMIO_OFF_MTRR_FIX4K_E8000_REG 0x160 /*< Fixed-range MTRR Register for 4K at e8000. /
96	#define VTD_MMIO_OFF_MTRR_FIX4K_F0000_REG 0x168 /*< Fixed-range MTRR Register for 4K at f0000. /
97	#define VTD_MMIO_OFF_MTRR_FIX4K_F8000_REG 0x170 /*< Fixed-range MTRR Register for 4K at f8000. /
98
99	#define VTD_MMIO_OFF_MTRR_PHYSBASE0_REG 0x180 /*< Variable-range MTRR Base 0. /
100	#define VTD_MMIO_OFF_MTRR_PHYSMASK0_REG 0x188 /*< Variable-range MTRR Mask 0. /
101	#define VTD_MMIO_OFF_MTRR_PHYSBASE1_REG 0x190 /*< Variable-range MTRR Base 1. /
102	#define VTD_MMIO_OFF_MTRR_PHYSMASK1_REG 0x198 /*< Variable-range MTRR Mask 1. /
103	#define VTD_MMIO_OFF_MTRR_PHYSBASE2_REG 0x1a0 /*< Variable-range MTRR Base 2. /
104	#define VTD_MMIO_OFF_MTRR_PHYSMASK2_REG 0x1a8 /*< Variable-range MTRR Mask 2. /
105	#define VTD_MMIO_OFF_MTRR_PHYSBASE3_REG 0x1b0 /*< Variable-range MTRR Base 3. /
106	#define VTD_MMIO_OFF_MTRR_PHYSMASK3_REG 0x1b8 /*< Variable-range MTRR Mask 3. /
107	#define VTD_MMIO_OFF_MTRR_PHYSBASE4_REG 0x1c0 /*< Variable-range MTRR Base 4. /
108	#define VTD_MMIO_OFF_MTRR_PHYSMASK4_REG 0x1c8 /*< Variable-range MTRR Mask 4. /
109	#define VTD_MMIO_OFF_MTRR_PHYSBASE5_REG 0x1d0 /*< Variable-range MTRR Base 5. /
110	#define VTD_MMIO_OFF_MTRR_PHYSMASK5_REG 0x1d8 /*< Variable-range MTRR Mask 5. /
111	#define VTD_MMIO_OFF_MTRR_PHYSBASE6_REG 0x1e0 /*< Variable-range MTRR Base 6. /
112	#define VTD_MMIO_OFF_MTRR_PHYSMASK6_REG 0x1e8 /*< Variable-range MTRR Mask 6. /
113	#define VTD_MMIO_OFF_MTRR_PHYSBASE7_REG 0x1f0 /*< Variable-range MTRR Base 7. /
114	#define VTD_MMIO_OFF_MTRR_PHYSMASK7_REG 0x1f8 /*< Variable-range MTRR Mask 7. /
115	#define VTD_MMIO_OFF_MTRR_PHYSBASE8_REG 0x200 /*< Variable-range MTRR Base 8. /
116	#define VTD_MMIO_OFF_MTRR_PHYSMASK8_REG 0x208 /*< Variable-range MTRR Mask 8. /
117	#define VTD_MMIO_OFF_MTRR_PHYSBASE9_REG 0x210 /*< Variable-range MTRR Base 9. /
118	#define VTD_MMIO_OFF_MTRR_PHYSMASK9_REG 0x218 /*< Variable-range MTRR Mask 9. /
119
120	#define VTD_MMIO_OFF_VCCAP_REG 0xe00 /*< Virtual Command Capability. /
121	#define VTD_MMIO_OFF_VCMD_REG 0xe10 /*< Virtual Command. /
122	#define VTD_MMIO_OFF_VCMDRSVD_REG 0xe18 /*< Reserved for future for Virtual Command. /
123	#define VTD_MMIO_OFF_VCRSP_REG 0xe20 /*< Virtual Command Response. /
124	#define VTD_MMIO_OFF_VCRSPRSVD_REG 0xe28 /*< Reserved for future for Virtual Command Response. /
125	/** @} */
126
127
128	/** @name Root Entry.
129	* In accordance with the Intel spec.
130	* @{ */
131	/** P: Present. */
132	#define VTD_BF_0_ROOT_ENTRY_P_SHIFT 0
133	#define VTD_BF_0_ROOT_ENTRY_P_MASK UINT64_C(0x0000000000000001)
134	/** R: Reserved (bits 11:1). */
135	#define VTD_BF_0_ROOT_ENTRY_RSVD_11_1_SHIFT 1
136	#define VTD_BF_0_ROOT_ENTRY_RSVD_11_1_MASK UINT64_C(0x0000000000000ffe)
137	/** CTP: Context-Table Pointer. */
138	#define VTD_BF_0_ROOT_ENTRY_CTP_SHIFT 12
139	#define VTD_BF_0_ROOT_ENTRY_CTP_MASK UINT64_C(0xfffffffffffff000)
140	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_ROOT_ENTRY_, UINT64_C(0), UINT64_MAX,
141	(P, RSVD_11_1, CTP));
142
143	/** Root Entry. */
144	typedef struct VTD_ROOT_ENTRY_T
145	{
146	/** The qwords in the root entry. */
147	uint64_t au64[2];
148	} VTD_ROOT_ENTRY_T;
149	/** Pointer to a root entry. */
150	typedef VTD_ROOT_ENTRY_T *PVTD_ROOT_ENTRY_T;
151	/** Pointer to a const root entry. */
152	typedef VTD_ROOT_ENTRY_T const *PCVTD_ROOT_ENTRY_T;
153	/** @} */
154
155
156	/** @name Scalable-mode Root Entry.
157	* In accordance with the Intel spec.
158	* @{ */
159	/** LP: Lower Present. */
160	#define VTD_BF_0_SM_ROOT_ENTRY_LP_SHIFT 0
161	#define VTD_BF_0_SM_ROOT_ENTRY_LP_MASK UINT64_C(0x0000000000000001)
162	/** R: Reserved (bits 11:1). */
163	#define VTD_BF_0_SM_ROOT_ENTRY_RSVD_11_1_SHIFT 1
164	#define VTD_BF_0_SM_ROOT_ENTRY_RSVD_11_1_MASK UINT64_C(0x0000000000000ffe)
165	/** LCTP: Lower Context-Table Pointer */
166	#define VTD_BF_0_SM_ROOT_ENTRY_LCTP_SHIFT 12
167	#define VTD_BF_0_SM_ROOT_ENTRY_LCTP_MASK UINT64_C(0xfffffffffffff000)
168	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_SM_ROOT_ENTRY_, UINT64_C(0), UINT64_MAX,
169	(LP, RSVD_11_1, LCTP));
170
171	/** UP: Upper Present. */
172	#define VTD_BF_1_SM_ROOT_ENTRY_UP_SHIFT 0
173	#define VTD_BF_1_SM_ROOT_ENTRY_UP_MASK UINT64_C(0x0000000000000001)
174	/** R: Reserved (bits 11:1). */
175	#define VTD_BF_1_SM_ROOT_ENTRY_RSVD_11_1_SHIFT 1
176	#define VTD_BF_1_SM_ROOT_ENTRY_RSVD_11_1_MASK UINT64_C(0x0000000000000ffe)
177	/** UCTP: Upper Context-Table Pointer. */
178	#define VTD_BF_1_SM_ROOT_ENTRY_UCTP_SHIFT 12
179	#define VTD_BF_1_SM_ROOT_ENTRY_UCTP_MASK UINT64_C(0xfffffffffffff000)
180	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_SM_ROOT_ENTRY_, UINT64_C(0), UINT64_MAX,
181	(UP, RSVD_11_1, UCTP));
182
183	/** Scalable-mode root entry. */
184	typedef struct VTD_SM_ROOT_ENTRY_T
185	{
186	/** The lower scalable-mode root entry. */
187	uint64_t uLower;
188	/** The upper scalable-mode root entry. */
189	uint64_t uUpper;
190	} VTD_SM_ROOT_ENTRY_T;
191	/** Pointer to a scalable-mode root entry. */
192	typedef VTD_SM_ROOT_ENTRY_T *PVTD_SM_ROOT_ENTRY_T;
193	/** Pointer to a const scalable-mode root entry. */
194	typedef VTD_SM_ROOT_ENTRY_T const *PCVTD_SM_ROOT_ENTRY_T;
195	/** @} */
196
197
198	/** @name Context Entry.
199	* In accordance with the Intel spec.
200	* @{ */
201	/** P: Present. */
202	#define VTD_BF_0_CONTEXT_ENTRY_P_SHIFT 0
203	#define VTD_BF_0_CONTEXT_ENTRY_P_MASK UINT64_C(0x0000000000000001)
204	/** FPD: Fault Processing Disable. */
205	#define VTD_BF_0_CONTEXT_ENTRY_FPD_SHIFT 1
206	#define VTD_BF_0_CONTEXT_ENTRY_FPD_MASK UINT64_C(0x0000000000000002)
207	/** TT: Translation Type. */
208	#define VTD_BF_0_CONTEXT_ENTRY_TT_SHIFT 2
209	#define VTD_BF_0_CONTEXT_ENTRY_TT_MASK UINT64_C(0x000000000000000c)
210	/** R: Reserved (bits 11:4). */
211	#define VTD_BF_0_CONTEXT_ENTRY_RSVD_11_4_SHIFT 4
212	#define VTD_BF_0_CONTEXT_ENTRY_RSVD_11_4_MASK UINT64_C(0x0000000000000ff0)
213	/** SLPTPTR: Second Level Page Translation Pointer. */
214	#define VTD_BF_0_CONTEXT_ENTRY_SLPTPTR_SHIFT 12
215	#define VTD_BF_0_CONTEXT_ENTRY_SLPTPTR_MASK UINT64_C(0xfffffffffffff000)
216	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_CONTEXT_ENTRY_, UINT64_C(0), UINT64_MAX,
217	(P, FPD, TT, RSVD_11_4, SLPTPTR));
218
219	/** AW: Address Width. */
220	#define VTD_BF_1_CONTEXT_ENTRY_AW_SHIFT 0
221	#define VTD_BF_1_CONTEXT_ENTRY_AW_MASK UINT64_C(0x0000000000000007)
222	/** IGN: Ignored (bits 6:3). */
223	#define VTD_BF_1_CONTEXT_ENTRY_IGN_6_3_SHIFT 3
224	#define VTD_BF_1_CONTEXT_ENTRY_IGN_6_3_MASK UINT64_C(0x0000000000000078)
225	/** R: Reserved (bit 7). */
226	#define VTD_BF_1_CONTEXT_ENTRY_RSVD_7_SHIFT 7
227	#define VTD_BF_1_CONTEXT_ENTRY_RSVD_7_MASK UINT64_C(0x0000000000000080)
228	/** DID: Domain Identifier. */
229	#define VTD_BF_1_CONTEXT_ENTRY_DID_SHIFT 8
230	#define VTD_BF_1_CONTEXT_ENTRY_DID_MASK UINT64_C(0x0000000000ffff00)
231	/** R: Reserved (bits 63:24). */
232	#define VTD_BF_1_CONTEXT_ENTRY_RSVD_63_24_SHIFT 24
233	#define VTD_BF_1_CONTEXT_ENTRY_RSVD_63_24_MASK UINT64_C(0xffffffffff000000)
234	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_CONTEXT_ENTRY_, UINT64_C(0), UINT64_MAX,
235	(AW, IGN_6_3, RSVD_7, DID, RSVD_63_24));
236
237	/** Context Entry. */
238	typedef struct VTD_CONTEXT_ENTRY_T
239	{
240	/** The qwords in the context entry. */
241	uint64_t au64[2];
242	} VTD_CONTEXT_ENTRY_T;
243	/** Pointer to a context entry. */
244	typedef VTD_CONTEXT_ENTRY_T *PVTD_CONTEXT_ENTRY_T;
245	/** Pointer to a const context entry. */
246	typedef VTD_CONTEXT_ENTRY_T const *PCVTD_CONTEXT_ENTRY_T;
247	/** @} */
248
249
250	/** @name Scalable-mode Context Entry.
251	* In accordance with the Intel spec.
252	* @{ */
253	/** P: Present. */
254	#define VTD_BF_0_SM_CONTEXT_ENTRY_P_SHIFT 0
255	#define VTD_BF_0_SM_CONTEXT_ENTRY_P_MASK UINT64_C(0x0000000000000001)
256	/** FPD: Fault Processing Disable. */
257	#define VTD_BF_0_SM_CONTEXT_ENTRY_FPD_SHIFT 1
258	#define VTD_BF_0_SM_CONTEXT_ENTRY_FPD_MASK UINT64_C(0x0000000000000002)
259	/** DTE: Device-TLB Enable. */
260	#define VTD_BF_0_SM_CONTEXT_ENTRY_DTE_SHIFT 2
261	#define VTD_BF_0_SM_CONTEXT_ENTRY_DTE_MASK UINT64_C(0x0000000000000004)
262	/** PASIDE: PASID Enable. */
263	#define VTD_BF_0_SM_CONTEXT_ENTRY_PASIDE_SHIFT 3
264	#define VTD_BF_0_SM_CONTEXT_ENTRY_PASIDE_MASK UINT64_C(0x0000000000000008)
265	/** PRE: Page Request Enable. */
266	#define VTD_BF_0_SM_CONTEXT_ENTRY_PRE_SHIFT 4
267	#define VTD_BF_0_SM_CONTEXT_ENTRY_PRE_MASK UINT64_C(0x0000000000000010)
268	/** R: Reserved (bits 8:5). */
269	#define VTD_BF_0_SM_CONTEXT_ENTRY_RSVD_8_5_SHIFT 5
270	#define VTD_BF_0_SM_CONTEXT_ENTRY_RSVD_8_5_MASK UINT64_C(0x00000000000001e0)
271	/** PDTS: PASID Directory Size. */
272	#define VTD_BF_0_SM_CONTEXT_ENTRY_PDTS_SHIFT 9
273	#define VTD_BF_0_SM_CONTEXT_ENTRY_PDTS_MASK UINT64_C(0x0000000000000e00)
274	/** PASIDDIRPTR: PASID Directory Pointer. */
275	#define VTD_BF_0_SM_CONTEXT_ENTRY_PASIDDIRPTR_SHIFT 12
276	#define VTD_BF_0_SM_CONTEXT_ENTRY_PASIDDIRPTR_MASK UINT64_C(0xfffffffffffff000)
277	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_SM_CONTEXT_ENTRY_, UINT64_C(0), UINT64_MAX,
278	(P, FPD, DTE, PASIDE, PRE, RSVD_8_5, PDTS, PASIDDIRPTR));
279
280	/** RID_PASID: Requested Id to PASID assignment. */
281	#define VTD_BF_1_SM_CONTEXT_ENTRY_RID_PASID_SHIFT 0
282	#define VTD_BF_1_SM_CONTEXT_ENTRY_RID_PASID_MASK UINT64_C(0x00000000000fffff)
283	/** RID_PRIV: Requested Id to PrivilegeModeRequested assignment. */
284	#define VTD_BF_1_SM_CONTEXT_ENTRY_RID_PRIV_SHIFT 20
285	#define VTD_BF_1_SM_CONTEXT_ENTRY_RID_PRIV_MASK UINT64_C(0x0000000000100000)
286	/** R: Reserved (bits 63:21). */
287	#define VTD_BF_1_SM_CONTEXT_ENTRY_RSVD_63_21_SHIFT 21
288	#define VTD_BF_1_SM_CONTEXT_ENTRY_RSVD_63_21_MASK UINT64_C(0xffffffffffe00000)
289	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_SM_CONTEXT_ENTRY_, UINT64_C(0), UINT64_MAX,
290	(RID_PASID, RID_PRIV, RSVD_63_21));
291
292	/** Context Entry. */
293	typedef struct VTD_SM_CONTEXT_ENTRY_T
294	{
295	/** The qwords in the scalable-mode context entry. */
296	uint64_t au64[4];
297	} VTD_SM_CONTEXT_ENTRY_T;
298	/** Pointer to a scalable-mode context entry. */
299	typedef VTD_SM_CONTEXT_ENTRY_T *PVTD_SM_CONTEXT_ENTRY_T;
300	/** Pointer to a const scalable-mode context entry. */
301	typedef VTD_SM_CONTEXT_ENTRY_T const *PCVTD_SM_CONTEXT_ENTRY_T;
302	/** @} */
303
304
305	/** @name Scalable-mode PASID Directory Entry.
306	* In accordance with the Intel spec.
307	* @{ */
308	/** P: Present. */
309	#define VTD_BF_SM_PASID_DIR_ENTRY_P_SHIFT 0
310	#define VTD_BF_SM_PASID_DIR_ENTRY_P_MASK UINT64_C(0x0000000000000001)
311	/** FPD: Fault Processing Disable. */
312	#define VTD_BF_SM_PASID_DIR_ENTRY_FPD_SHIFT 1
313	#define VTD_BF_SM_PASID_DIR_ENTRY_FPD_MASK UINT64_C(0x0000000000000002)
314	/** R: Reserved (bits 11:2). */
315	#define VTD_BF_SM_PASID_DIR_ENTRY_RSVD_11_2_SHIFT 2
316	#define VTD_BF_SM_PASID_DIR_ENTRY_RSVD_11_2_MASK UINT64_C(0x0000000000000ffc)
317	/** SMPTBLPTR: Scalable Mode PASID Table Pointer. */
318	#define VTD_BF_SM_PASID_DIR_ENTRY_SMPTBLPTR_SHIFT 12
319	#define VTD_BF_SM_PASID_DIR_ENTRY_SMPTBLPTR_MASK UINT64_C(0xfffffffffffff000)
320	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_SM_PASID_DIR_ENTRY_, UINT64_C(0), UINT64_MAX,
321	(P, FPD, RSVD_11_2, SMPTBLPTR));
322
323	/** Scalable-mode PASID Directory Entry. */
324	typedef struct VTD_SM_PASID_DIR_ENTRY_T
325	{
326	/** The scalable-mode PASID directory entry. */
327	uint64_t u;
328	} VTD_SM_PASID_DIR_ENTRY_T;
329	/** Pointer to a scalable-mode PASID directory entry. */
330	typedef VTD_SM_PASID_DIR_ENTRY_T *PVTD_SM_PASID_DIR_ENTRY_T;
331	/** Pointer to a const scalable-mode PASID directory entry. */
332	typedef VTD_SM_PASID_DIR_ENTRY_T const *PCVTD_SM_PASID_DIR_ENTRY_T;
333	/** @} */
334
335
336	/** @name Scalable-mode PASID Table Entry.
337	* In accordance with the Intel spec.
338	* @{ */
339	/** P: Present. */
340	#define VTD_BF_0_SM_PASID_TBL_ENTRY_P_SHIFT 0
341	#define VTD_BF_0_SM_PASID_TBL_ENTRY_P_MASK UINT64_C(0x0000000000000001)
342	/** FPD: Fault Processing Disable. */
343	#define VTD_BF_0_SM_PASID_TBL_ENTRY_FPD_SHIFT 1
344	#define VTD_BF_0_SM_PASID_TBL_ENTRY_FPD_MASK UINT64_C(0x0000000000000002)
345	/** AW: Address Width. */
346	#define VTD_BF_0_SM_PASID_TBL_ENTRY_AW_SHIFT 2
347	#define VTD_BF_0_SM_PASID_TBL_ENTRY_AW_MASK UINT64_C(0x000000000000001c)
348	/** SLEE: Second-Level Execute Enable. */
349	#define VTD_BF_0_SM_PASID_TBL_ENTRY_SLEE_SHIFT 5
350	#define VTD_BF_0_SM_PASID_TBL_ENTRY_SLEE_MASK UINT64_C(0x0000000000000020)
351	/** PGTT: PASID Granular Translation Type. */
352	#define VTD_BF_0_SM_PASID_TBL_ENTRY_PGTT_SHIFT 6
353	#define VTD_BF_0_SM_PASID_TBL_ENTRY_PGTT_MASK UINT64_C(0x00000000000001c0)
354	/** SLADE: Second-Level Address/Dirty Enable. */
355	#define VTD_BF_0_SM_PASID_TBL_ENTRY_SLADE_SHIFT 9
356	#define VTD_BF_0_SM_PASID_TBL_ENTRY_SLADE_MASK UINT64_C(0x0000000000000200)
357	/** R: Reserved (bits 11:10). */
358	#define VTD_BF_0_SM_PASID_TBL_ENTRY_RSVD_11_10_SHIFT 10
359	#define VTD_BF_0_SM_PASID_TBL_ENTRY_RSVD_11_10_MASK UINT64_C(0x0000000000000c00)
360	/** SLPTPTR: Second-Level Page Table Pointer. */
361	#define VTD_BF_0_SM_PASID_TBL_ENTRY_SLPTPTR_SHIFT 12
362	#define VTD_BF_0_SM_PASID_TBL_ENTRY_SLPTPTR_MASK UINT64_C(0xfffffffffffff000)
363	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_SM_PASID_TBL_ENTRY_, UINT64_C(0), UINT64_MAX,
364	(P, FPD, AW, SLEE, PGTT, SLADE, RSVD_11_10, SLPTPTR));
365
366	/** DID: Domain Identifer. */
367	#define VTD_BF_1_SM_PASID_TBL_ENTRY_DID_SHIFT 0
368	#define VTD_BF_1_SM_PASID_TBL_ENTRY_DID_MASK UINT64_C(0x000000000000ffff)
369	/** R: Reserved (bits 22:16). */
370	#define VTD_BF_1_SM_PASID_TBL_ENTRY_RSVD_22_16_SHIFT 16
371	#define VTD_BF_1_SM_PASID_TBL_ENTRY_RSVD_22_16_MASK UINT64_C(0x00000000007f0000)
372	/** PWSNP: Page-Walk Snoop. */
373	#define VTD_BF_1_SM_PASID_TBL_ENTRY_PWSNP_SHIFT 23
374	#define VTD_BF_1_SM_PASID_TBL_ENTRY_PWSNP_MASK UINT64_C(0x0000000000800000)
375	/** PGSNP: Page Snoop. */
376	#define VTD_BF_1_SM_PASID_TBL_ENTRY_PGSNP_SHIFT 24
377	#define VTD_BF_1_SM_PASID_TBL_ENTRY_PGSNP_MASK UINT64_C(0x0000000001000000)
378	/** CD: Cache Disable. */
379	#define VTD_BF_1_SM_PASID_TBL_ENTRY_CD_SHIFT 25
380	#define VTD_BF_1_SM_PASID_TBL_ENTRY_CD_MASK UINT64_C(0x0000000002000000)
381	/** EMTE: Extended Memory Type Enable. */
382	#define VTD_BF_1_SM_PASID_TBL_ENTRY_EMTE_SHIFT 26
383	#define VTD_BF_1_SM_PASID_TBL_ENTRY_EMTE_MASK UINT64_C(0x0000000004000000)
384	/** EMT: Extended Memory Type. */
385	#define VTD_BF_1_SM_PASID_TBL_ENTRY_EMT_SHIFT 27
386	#define VTD_BF_1_SM_PASID_TBL_ENTRY_EMT_MASK UINT64_C(0x0000000038000000)
387	/** PWT: Page-Level Write Through. */
388	#define VTD_BF_1_SM_PASID_TBL_ENTRY_PWT_SHIFT 30
389	#define VTD_BF_1_SM_PASID_TBL_ENTRY_PWT_MASK UINT64_C(0x0000000040000000)
390	/** PCD: Page-Level Cache Disable. */
391	#define VTD_BF_1_SM_PASID_TBL_ENTRY_PCD_SHIFT 31
392	#define VTD_BF_1_SM_PASID_TBL_ENTRY_PCD_MASK UINT64_C(0x0000000080000000)
393	/** PAT: Page Attribute Table. */
394	#define VTD_BF_1_SM_PASID_TBL_ENTRY_PAT_SHIFT 32
395	#define VTD_BF_1_SM_PASID_TBL_ENTRY_PAT_MASK UINT64_C(0xffffffff00000000)
396	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_SM_PASID_TBL_ENTRY_, UINT64_C(0), UINT64_MAX,
397	(DID, RSVD_22_16, PWSNP, PGSNP, CD, EMTE, EMT, PWT, PCD, PAT));
398
399	/** SRE: Supervisor Request Enable. */
400	#define VTD_BF_2_SM_PASID_TBL_ENTRY_SRE_SHIFT 0
401	#define VTD_BF_2_SM_PASID_TBL_ENTRY_SRE_MASK UINT64_C(0x0000000000000001)
402	/** ERE: Execute Request Enable. */
403	#define VTD_BF_2_SM_PASID_TBL_ENTRY_ERE_SHIFT 1
404	#define VTD_BF_2_SM_PASID_TBL_ENTRY_ERE_MASK UINT64_C(0x0000000000000002)
405	/** FLPM: First Level Paging Mode. */
406	#define VTD_BF_2_SM_PASID_TBL_ENTRY_FLPM_SHIFT 2
407	#define VTD_BF_2_SM_PASID_TBL_ENTRY_FLPM_MASK UINT64_C(0x000000000000000c)
408	/** WPE: Write Protect Enable. */
409	#define VTD_BF_2_SM_PASID_TBL_ENTRY_WPE_SHIFT 4
410	#define VTD_BF_2_SM_PASID_TBL_ENTRY_WPE_MASK UINT64_C(0x0000000000000010)
411	/** NXE: No-Execute Enable. */
412	#define VTD_BF_2_SM_PASID_TBL_ENTRY_NXE_SHIFT 5
413	#define VTD_BF_2_SM_PASID_TBL_ENTRY_NXE_MASK UINT64_C(0x0000000000000020)
414	/** SMEP: Supervisor Mode Execute Prevent. */
415	#define VTD_BF_2_SM_PASID_TBL_ENTRY_SMPE_SHIFT 6
416	#define VTD_BF_2_SM_PASID_TBL_ENTRY_SMPE_MASK UINT64_C(0x0000000000000040)
417	/** EAFE: Extended Accessed Flag Enable. */
418	#define VTD_BF_2_SM_PASID_TBL_ENTRY_EAFE_SHIFT 7
419	#define VTD_BF_2_SM_PASID_TBL_ENTRY_EAFE_MASK UINT64_C(0x0000000000000080)
420	/** R: Reserved (bits 11:8). */
421	#define VTD_BF_2_SM_PASID_TBL_ENTRY_RSVD_11_8_SHIFT 8
422	#define VTD_BF_2_SM_PASID_TBL_ENTRY_RSVD_11_8_MASK UINT64_C(0x0000000000000f00)
423	/** FLPTPTR: First Level Page Table Pointer. */
424	#define VTD_BF_2_SM_PASID_TBL_ENTRY_FLPTPTR_SHIFT 12
425	#define VTD_BF_2_SM_PASID_TBL_ENTRY_FLPTPTR_MASK UINT64_C(0xfffffffffffff000)
426	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_2_SM_PASID_TBL_ENTRY_, UINT64_C(0), UINT64_MAX,
427	(SRE, ERE, FLPM, WPE, NXE, SMPE, EAFE, RSVD_11_8, FLPTPTR));
428
429	/** Scalable-mode PASID Table Entry. */
430	typedef struct VTD_SM_PASID_TBL_ENTRY_T
431	{
432	/** The qwords in the scalable-mode PASID table entry. */
433	uint64_t au64[8];
434	} VTD_SM_PASID_TBL_ENTRY_T;
435	/** Pointer to a scalable-mode PASID table entry. */
436	typedef VTD_SM_PASID_TBL_ENTRY_T *PVTD_SM_PASID_TBL_ENTRY_T;
437	/** Pointer to a const scalable-mode PASID table entry. */
438	typedef VTD_SM_PASID_TBL_ENTRY_T const *PCVTD_SM_PASID_TBL_ENTRY_T;
439	/** @} */
440
441
442	/** @name First-Level Paging Entry.
443	* In accordance with the Intel spec.
444	* @{ */
445	/** P: Present. */
446	#define VTD_BF_FLP_ENTRY_P_SHIFT 0
447	#define VTD_BF_FLP_ENTRY_P_MASK UINT64_C(0x0000000000000001)
448	/** R/W: Read/Write. */
449	#define VTD_BF_FLP_ENTRY_RW_SHIFT 1
450	#define VTD_BF_FLP_ENTRY_RW_MASK UINT64_C(0x0000000000000002)
451	/** U/S: User/Supervisor. */
452	#define VTD_BF_FLP_ENTRY_US_SHIFT 2
453	#define VTD_BF_FLP_ENTRY_US_MASK UINT64_C(0x0000000000000004)
454	/** PWT: Page-Level Write Through. */
455	#define VTD_BF_FLP_ENTRY_PWT_SHIFT 3
456	#define VTD_BF_FLP_ENTRY_PWT_MASK UINT64_C(0x0000000000000008)
457	/** PC: Page-Level Cache Disable. */
458	#define VTD_BF_FLP_ENTRY_PCD_SHIFT 4
459	#define VTD_BF_FLP_ENTRY_PCD_MASK UINT64_C(0x0000000000000010)
460	/** A: Accessed. */
461	#define VTD_BF_FLP_ENTRY_A_SHIFT 5
462	#define VTD_BF_FLP_ENTRY_A_MASK UINT64_C(0x0000000000000020)
463	/** IGN: Ignored (bit 6). */
464	#define VTD_BF_FLP_ENTRY_IGN_6_SHIFT 6
465	#define VTD_BF_FLP_ENTRY_IGN_6_MASK UINT64_C(0x0000000000000040)
466	/** R: Reserved (bit 7). */
467	#define VTD_BF_FLP_ENTRY_RSVD_7_SHIFT 7
468	#define VTD_BF_FLP_ENTRY_RSVD_7_MASK UINT64_C(0x0000000000000080)
469	/** IGN: Ignored (bits 9:8). */
470	#define VTD_BF_FLP_ENTRY_IGN_9_8_SHIFT 8
471	#define VTD_BF_FLP_ENTRY_IGN_9_8_MASK UINT64_C(0x0000000000000300)
472	/** EA: Extended Accessed. */
473	#define VTD_BF_FLP_ENTRY_EA_SHIFT 10
474	#define VTD_BF_FLP_ENTRY_EA_MASK UINT64_C(0x0000000000000400)
475	/** IGN: Ignored (bit 11). */
476	#define VTD_BF_FLP_ENTRY_IGN_11_SHIFT 11
477	#define VTD_BF_FLP_ENTRY_IGN_11_MASK UINT64_C(0x0000000000000800)
478	/** ADDR: Address. */
479	#define VTD_BF_FLP_ENTRY_ADDR_SHIFT 12
480	#define VTD_BF_FLP_ENTRY_ADDR_MASK UINT64_C(0x000ffffffffff000)
481	/** IGN: Ignored (bits 62:52). */
482	#define VTD_BF_FLP_ENTRY_IGN_62_52_SHIFT 52
483	#define VTD_BF_FLP_ENTRY_IGN_62_52_MASK UINT64_C(0x7ff0000000000000)
484	/** XD: Execute Disabled. */
485	#define VTD_BF_FLP_ENTRY_XD_SHIFT 63
486	#define VTD_BF_FLP_ENTRY_XD_MASK UINT64_C(0x8000000000000000)
487	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_FLP_ENTRY_, UINT64_C(0), UINT64_MAX,
488	(P, RW, US, PWT, PCD, A, IGN_6, RSVD_7, IGN_9_8, EA, IGN_11, ADDR, IGN_62_52, XD));
489
490	/** First-Level Paging Entry. */
491	typedef struct VTD_FLP_ENTRY_T
492	{
493	/** The first-level paging entry. */
494	uint64_t u;
495	} VTD_FLP_ENTRY_T;
496	/** Pointer to a first-level paging entry. */
497	typedef VTD_FLP_ENTRY_T *PVTD_FLP_ENTRY_T;
498	/** Pointer to a const first-level paging entry. */
499	typedef VTD_FLP_ENTRY_T const *PCVTD_FLP_ENTRY_T;
500	/** @} */
501
502
503	/** @name Second-Level Paging Entry.
504	* In accordance with the Intel spec.
505	* @{ */
506	/** R: Read. */
507	#define VTD_BF_SLP_ENTRY_R_SHIFT 0
508	#define VTD_BF_SLP_ENTRY_R_MASK UINT64_C(0x0000000000000001)
509	/** W: Write. */
510	#define VTD_BF_SLP_ENTRY_W_SHIFT 1
511	#define VTD_BF_SLP_ENTRY_W_MASK UINT64_C(0x0000000000000002)
512	/** X: Execute. */
513	#define VTD_BF_SLP_ENTRY_X_SHIFT 2
514	#define VTD_BF_SLP_ENTRY_X_MASK UINT64_C(0x0000000000000004)
515	/** IGN: Ignored (bits 6:3). */
516	#define VTD_BF_SLP_ENTRY_IGN_6_3_SHIFT 3
517	#define VTD_BF_SLP_ENTRY_IGN_6_3_MASK UINT64_C(0x0000000000000078)
518	/** R: Reserved (bit 7). */
519	#define VTD_BF_SLP_ENTRY_RSVD_7_SHIFT 7
520	#define VTD_BF_SLP_ENTRY_RSVD_7_MASK UINT64_C(0x0000000000000080)
521	/** A: Accessed. */
522	#define VTD_BF_SLP_ENTRY_A_SHIFT 8
523	#define VTD_BF_SLP_ENTRY_A_MASK UINT64_C(0x0000000000000100)
524	/** IGN: Ignored (bits 10:9). */
525	#define VTD_BF_SLP_ENTRY_IGN_10_9_SHIFT 9
526	#define VTD_BF_SLP_ENTRY_IGN_10_9_MASK UINT64_C(0x0000000000000600)
527	/** R: Reserved (bit 11). */
528	#define VTD_BF_SLP_ENTRY_RSVD_11_SHIFT 11
529	#define VTD_BF_SLP_ENTRY_RSVD_11_MASK UINT64_C(0x0000000000000800)
530	/** ADDR: Address. */
531	#define VTD_BF_SLP_ENTRY_ADDR_SHIFT 12
532	#define VTD_BF_SLP_ENTRY_ADDR_MASK UINT64_C(0x000ffffffffff000)
533	/** IGN: Ignored (bits 61:52). */
534	#define VTD_BF_SLP_ENTRY_IGN_61_52_SHIFT 52
535	#define VTD_BF_SLP_ENTRY_IGN_61_52_MASK UINT64_C(0x3ff0000000000000)
536	/** R: Reserved (bit 62). */
537	#define VTD_BF_SLP_ENTRY_RSVD_62_SHIFT 62
538	#define VTD_BF_SLP_ENTRY_RSVD_62_MASK UINT64_C(0x4000000000000000)
539	/** IGN: Ignored (bit 63). */
540	#define VTD_BF_SLP_ENTRY_IGN_63_SHIFT 63
541	#define VTD_BF_SLP_ENTRY_IGN_63_MASK UINT64_C(0x8000000000000000)
542	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_SLP_ENTRY_, UINT64_C(0), UINT64_MAX,
543	(R, W, X, IGN_6_3, RSVD_7, A, IGN_10_9, RSVD_11, ADDR, IGN_61_52, RSVD_62, IGN_63));
544
545	/** Second-Level Paging Entry. */
546	typedef struct VTD_SLP_ENTRY_T
547	{
548	/** The second-level paging entry. */
549	uint64_t u;
550	} VTD_SLP_ENTRY_T;
551	/** Pointer to a second-level paging entry. */
552	typedef VTD_SLP_ENTRY_T *PVTD_SLP_ENTRY_T;
553	/** Pointer to a const second-level paging entry. */
554	typedef VTD_SLP_ENTRY_T const *PCVTD_SLP_ENTRY_T;
555	/** @} */
556
557
558	/** @name Fault Record.
559	* In accordance with the Intel spec.
560	* @{ */
561	/** R: Reserved (bits 11:0). */
562	#define VTD_BF_0_FAULT_RECORD_RSVD_11_0_SHIFT 0
563	#define VTD_BF_0_FAULT_RECORD_RSVD_11_0_MASK UINT64_C(0x0000000000000fff)
564	/** FI: Fault Information. */
565	#define VTD_BF_0_FAULT_RECORD_FI_SHIFT 12
566	#define VTD_BF_0_FAULT_RECORD_FI_MASK UINT64_C(0xfffffffffffff000)
567	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_FAULT_RECORD_, UINT64_C(0), UINT64_MAX,
568	(RSVD_11_0, FI));
569
570	/** SID: Source identifier. */
571	#define VTD_BF_1_FAULT_RECORD_SID_SHIFT 0
572	#define VTD_BF_1_FAULT_RECORD_SID_MASK UINT64_C(0x000000000000ffff)
573	/** R: Reserved (bits 28:16). */
574	#define VTD_BF_1_FAULT_RECORD_RSVD_28_16_SHIFT 16
575	#define VTD_BF_1_FAULT_RECORD_RSVD_28_16_MASK UINT64_C(0x000000001fff0000)
576	/** PRIV: Privilege Mode Requested. */
577	#define VTD_BF_1_FAULT_RECORD_PRIV_SHIFT 29
578	#define VTD_BF_1_FAULT_RECORD_PRIV_MASK UINT64_C(0x0000000020000000)
579	/** EXE: Execute Permission Requested. */
580	#define VTD_BF_1_FAULT_RECORD_EXE_SHIFT 30
581	#define VTD_BF_1_FAULT_RECORD_EXE_MASK UINT64_C(0x0000000040000000)
582	/** PP: PASID Present. */
583	#define VTD_BF_1_FAULT_RECORD_PP_SHIFT 31
584	#define VTD_BF_1_FAULT_RECORD_PP_MASK UINT64_C(0x0000000080000000)
585	/** FR: Fault Reason. */
586	#define VTD_BF_1_FAULT_RECORD_FR_SHIFT 32
587	#define VTD_BF_1_FAULT_RECORD_FR_MASK UINT64_C(0x000000ff00000000)
588	/** PV: PASID Value. */
589	#define VTD_BF_1_FAULT_RECORD_PV_SHIFT 40
590	#define VTD_BF_1_FAULT_RECORD_PV_MASK UINT64_C(0x0fffff0000000000)
591	/** AT: Address Type. */
592	#define VTD_BF_1_FAULT_RECORD_AT_SHIFT 60
593	#define VTD_BF_1_FAULT_RECORD_AT_MASK UINT64_C(0x3000000000000000)
594	/** T: Type. */
595	#define VTD_BF_1_FAULT_RECORD_T_SHIFT 62
596	#define VTD_BF_1_FAULT_RECORD_T_MASK UINT64_C(0x4000000000000000)
597	/** R: Reserved (bit 127). */
598	#define VTD_BF_1_FAULT_RECORD_RSVD_63_SHIFT 63
599	#define VTD_BF_1_FAULT_RECORD_RSVD_63_MASK UINT64_C(0x8000000000000000)
600	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_FAULT_RECORD_, UINT64_C(0), UINT64_MAX,
601	(SID, RSVD_28_16, PRIV, EXE, PP, FR, PV, AT, T, RSVD_63));
602
603	/** Fault record. */
604	typedef struct VTD_FAULT_RECORD_T
605	{
606	/** The qwords in the fault record. */
607	uint64_t au64[2];
608	} VTD_FAULT_RECORD_T;
609	/** Pointer to a fault record. */
610	typedef VTD_FAULT_RECORD_T *PVTD_FAULT_RECORD_T;
611	/** Pointer to a const fault record. */
612	typedef VTD_FAULT_RECORD_T const *PCVTD_FAULT_RECORD_T;
613	/** @} */
614
615
616	/** @name Interrupt Remapping Table Entry (IRTE) for Remapped Interrupts.
617	* In accordance with the Intel spec.
618	* @{ */
619	/** P: Present. */
620	#define VTD_BF_0_IRTE_P_SHIFT 0
621	#define VTD_BF_0_IRTE_P_MASK UINT64_C(0x0000000000000001)
622	/** FPD: Fault Processing Disable. */
623	#define VTD_BF_0_IRTE_FPD_SHIFT 1
624	#define VTD_BF_0_IRTE_FPD_MASK UINT64_C(0x0000000000000002)
625	/** DM: Destination Mode (0=physical, 1=logical). */
626	#define VTD_BF_0_IRTE_DM_SHIFT 2
627	#define VTD_BF_0_IRTE_DM_MASK UINT64_C(0x0000000000000004)
628	/** RH: Redirection Hint. */
629	#define VTD_BF_0_IRTE_RH_SHIFT 3
630	#define VTD_BF_0_IRTE_RH_MASK UINT64_C(0x0000000000000008)
631	/** TM: Trigger Mode. */
632	#define VTD_BF_0_IRTE_TM_SHIFT 4
633	#define VTD_BF_0_IRTE_TM_MASK UINT64_C(0x0000000000000010)
634	/** DLM: Delivery Mode. */
635	#define VTD_BF_0_IRTE_DLM_SHIFT 5
636	#define VTD_BF_0_IRTE_DLM_MASK UINT64_C(0x00000000000000e0)
637	/** AVL: Available. */
638	#define VTD_BF_0_IRTE_AVAIL_SHIFT 8
639	#define VTD_BF_0_IRTE_AVAIL_MASK UINT64_C(0x0000000000000f00)
640	/** R: Reserved (bits 14:12). */
641	#define VTD_BF_0_IRTE_RSVD_14_12_SHIFT 12
642	#define VTD_BF_0_IRTE_RSVD_14_12_MASK UINT64_C(0x0000000000007000)
643	/** IM: IRTE Mode. */
644	#define VTD_BF_0_IRTE_IM_SHIFT 15
645	#define VTD_BF_0_IRTE_IM_MASK UINT64_C(0x0000000000008000)
646	/** V: Vector. */
647	#define VTD_BF_0_IRTE_V_SHIFT 16
648	#define VTD_BF_0_IRTE_V_MASK UINT64_C(0x0000000000ff0000)
649	/** R: Reserved (bits 31:24). */
650	#define VTD_BF_0_IRTE_RSVD_31_24_SHIFT 24
651	#define VTD_BF_0_IRTE_RSVD_31_24_MASK UINT64_C(0x00000000ff000000)
652	/** DST: Desination Id. */
653	#define VTD_BF_0_IRTE_DST_SHIFT 32
654	#define VTD_BF_0_IRTE_DST_MASK UINT64_C(0xffffffff00000000)
655	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_IRTE_, UINT64_C(0), UINT64_MAX,
656	(P, FPD, DM, RH, TM, DLM, AVAIL, RSVD_14_12, IM, V, RSVD_31_24, DST));
657
658	/** SID: Source Identifier. */
659	#define VTD_BF_1_IRTE_SID_SHIFT 0
660	#define VTD_BF_1_IRTE_SID_MASK UINT64_C(0x000000000000ffff)
661	/** SQ: Source-Id Qualifier. */
662	#define VTD_BF_1_IRTE_SQ_SHIFT 16
663	#define VTD_BF_1_IRTE_SQ_MASK UINT64_C(0x0000000000030000)
664	/** SVT: Source Validation Type. */
665	#define VTD_BF_1_IRTE_SVT_SHIFT 18
666	#define VTD_BF_1_IRTE_SVT_MASK UINT64_C(0x00000000000c0000)
667	/** R: Reserved (bits 127:84). */
668	#define VTD_BF_1_IRTE_RSVD_63_20_SHIFT 20
669	#define VTD_BF_1_IRTE_RSVD_63_20_MASK UINT64_C(0xfffffffffff00000)
670	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_IRTE_, UINT64_C(0), UINT64_MAX,
671	(SID, SQ, SVT, RSVD_63_20));
672
673	/** Interrupt Remapping Table Entry (IRTE) for remapped interrupts. */
674	typedef struct VTD_IRTE_T
675	{
676	/** The qwords in the IRTE. */
677	uint64_t au64[2];
678	} VTD_IRTE_T;
679	/** Pointer to an IRTE. */
680	typedef VTD_IRTE_T *PVTD_IRTE_T;
681	/** Pointer to a const IRTE. */
682	typedef VTD_IRTE_T const *PCVTD_IRTE_T;
683	/** @} */
684
685
686	/** @name Version Register (VER_REG).
687	* In accordance with the Intel spec.
688	* @{ */
689	/** Min: Minor Version Number. */
690	#define VTD_BF_VER_REG_MIN_SHIFT 0
691	#define VTD_BF_VER_REG_MIN_MASK UINT32_C(0x0000000f)
692	/** Max: Major Version Number. */
693	#define VTD_BF_VER_REG_MAX_SHIFT 4
694	#define VTD_BF_VER_REG_MAX_MASK UINT32_C(0x000000f0)
695	/** R: Reserved (bits 31:8). */
696	#define VTD_BF_VER_REG_RSVD_31_8_SHIFT 8
697	#define VTD_BF_VER_REG_RSVD_31_8_MASK UINT32_C(0xffffff00)
698	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_VER_REG_, UINT32_C(0), UINT32_MAX,
699	(MIN, MAX, RSVD_31_8));
700	/** RW: Read/write mask. */
701	#define VTD_VER_REG_RW_MASK UINT32_C(0)
702	/** @} */
703
704
705	/** @name Capability Register (CAP_REG).
706	* In accordance with the Intel spec.
707	* @{ */
708	/** ND: Number of domains supported. */
709	#define VTD_BF_CAP_REG_ND_SHIFT 0
710	#define VTD_BF_CAP_REG_ND_MASK UINT64_C(0x0000000000000007)
711	/** AFL: Advanced Fault Logging. */
712	#define VTD_BF_CAP_REG_AFL_SHIFT 3
713	#define VTD_BF_CAP_REG_AFL_MASK UINT64_C(0x0000000000000008)
714	/** RWBF: Required Write-Buffer Flushing. */
715	#define VTD_BF_CAP_REG_RWBF_SHIFT 4
716	#define VTD_BF_CAP_REG_RWBF_MASK UINT64_C(0x0000000000000010)
717	/** PLMR: Protected Low-Memory Region. */
718	#define VTD_BF_CAP_REG_PLMR_SHIFT 5
719	#define VTD_BF_CAP_REG_PLMR_MASK UINT64_C(0x0000000000000020)
720	/** PHMR: Protected High-Memory Region. */
721	#define VTD_BF_CAP_REG_PHMR_SHIFT 6
722	#define VTD_BF_CAP_REG_PHMR_MASK UINT64_C(0x0000000000000040)
723	/** CM: Caching Mode. */
724	#define VTD_BF_CAP_REG_CM_SHIFT 7
725	#define VTD_BF_CAP_REG_CM_MASK UINT64_C(0x0000000000000080)
726	/** SAGAW: Supported Adjusted Guest Address Widths. */
727	#define VTD_BF_CAP_REG_SAGAW_SHIFT 8
728	#define VTD_BF_CAP_REG_SAGAW_MASK UINT64_C(0x0000000000001f00)
729	/** R: Reserved (bits 15:13). */
730	#define VTD_BF_CAP_REG_RSVD_15_13_SHIFT 13
731	#define VTD_BF_CAP_REG_RSVD_15_13_MASK UINT64_C(0x000000000000e000)
732	/** MGAW: Maximum Guest Address Width. */
733	#define VTD_BF_CAP_REG_MGAW_SHIFT 16
734	#define VTD_BF_CAP_REG_MGAW_MASK UINT64_C(0x00000000003f0000)
735	/** ZLR: Zero Length Read. */
736	#define VTD_BF_CAP_REG_ZLR_SHIFT 22
737	#define VTD_BF_CAP_REG_ZLR_MASK UINT64_C(0x0000000000400000)
738	/** DEP: Deprecated MBZ. Reserved (bit 23). */
739	#define VTD_BF_CAP_REG_RSVD_23_SHIFT 23
740	#define VTD_BF_CAP_REG_RSVD_23_MASK UINT64_C(0x0000000000800000)
741	/** FRO: Fault-recording Register Offset. */
742	#define VTD_BF_CAP_REG_FRO_SHIFT 24
743	#define VTD_BF_CAP_REG_FRO_MASK UINT64_C(0x00000003ff000000)
744	/** SLLPS: Second Level Large Page Support. */
745	#define VTD_BF_CAP_REG_SLLPS_SHIFT 34
746	#define VTD_BF_CAP_REG_SLLPS_MASK UINT64_C(0x0000003c00000000)
747	/** R: Reserved (bit 38). */
748	#define VTD_BF_CAP_REG_RSVD_38_SHIFT 38
749	#define VTD_BF_CAP_REG_RSVD_38_MASK UINT64_C(0x0000004000000000)
750	/** PSI: Page Selective Invalidation. */
751	#define VTD_BF_CAP_REG_PSI_SHIFT 39
752	#define VTD_BF_CAP_REG_PSI_MASK UINT64_C(0x0000008000000000)
753	/** NFR: Number of Fault-recording Registers. */
754	#define VTD_BF_CAP_REG_NFR_SHIFT 40
755	#define VTD_BF_CAP_REG_NFR_MASK UINT64_C(0x0000ff0000000000)
756	/** MAMV: Maximum Address Mask Value. */
757	#define VTD_BF_CAP_REG_MAMV_SHIFT 48
758	#define VTD_BF_CAP_REG_MAMV_MASK UINT64_C(0x003f000000000000)
759	/** DWD: Write Draining. */
760	#define VTD_BF_CAP_REG_DWD_SHIFT 54
761	#define VTD_BF_CAP_REG_DWD_MASK UINT64_C(0x0040000000000000)
762	/** DRD: Read Draining. */
763	#define VTD_BF_CAP_REG_DRD_SHIFT 55
764	#define VTD_BF_CAP_REG_DRD_MASK UINT64_C(0x0080000000000000)
765	/** FL1GP: First Level 1 GB Page Support. */
766	#define VTD_BF_CAP_REG_FL1GP_SHIFT 56
767	#define VTD_BF_CAP_REG_FL1GP_MASK UINT64_C(0x0100000000000000)
768	/** R: Reserved (bits 58:57). */
769	#define VTD_BF_CAP_REG_RSVD_58_57_SHIFT 57
770	#define VTD_BF_CAP_REG_RSVD_58_57_MASK UINT64_C(0x0600000000000000)
771	/** PI: Posted Interrupt Support. */
772	#define VTD_BF_CAP_REG_PI_SHIFT 59
773	#define VTD_BF_CAP_REG_PI_MASK UINT64_C(0x0800000000000000)
774	/** FL5LP: First Level 5-level Paging Support. */
775	#define VTD_BF_CAP_REG_FL5LP_SHIFT 60
776	#define VTD_BF_CAP_REG_FL5LP_MASK UINT64_C(0x1000000000000000)
777	/** R: Reserved (bit 61). */
778	#define VTD_BF_CAP_REG_RSVD_61_SHIFT 61
779	#define VTD_BF_CAP_REG_RSVD_61_MASK UINT64_C(0x2000000000000000)
780	/** ESIRTPS: Enhanced Set Interrupt Root Table Pointer Support. */
781	#define VTD_BF_CAP_REG_ESIRTPS_SHIFT 62
782	#define VTD_BF_CAP_REG_ESIRTPS_MASK UINT64_C(0x4000000000000000)
783	/** : Enhanced Set Root Table Pointer Support. */
784	#define VTD_BF_CAP_REG_ESRTPS_SHIFT 63
785	#define VTD_BF_CAP_REG_ESRTPS_MASK UINT64_C(0x8000000000000000)
786	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_CAP_REG_, UINT64_C(0), UINT64_MAX,
787	(ND, AFL, RWBF, PLMR, PHMR, CM, SAGAW, RSVD_15_13, MGAW, ZLR, RSVD_23, FRO, SLLPS, RSVD_38, PSI, NFR,
788	MAMV, DWD, DRD, FL1GP, RSVD_58_57, PI, FL5LP, RSVD_61, ESIRTPS, ESRTPS));
789
790	/** RW: Read/write mask. */
791	#define VTD_CAP_REG_RW_MASK UINT64_C(0)
792	/** @} */
793
794
795	/** @name Extended Capability Register (ECAP_REG).
796	* In accordance with the Intel spec.
797	* @{ */
798	/** C: Page-walk Coherence. */
799	#define VTD_BF_ECAP_REG_C_SHIFT 0
800	#define VTD_BF_ECAP_REG_C_MASK UINT64_C(0x0000000000000001)
801	/** QI: Queued Invalidation Support. */
802	#define VTD_BF_ECAP_REG_QI_SHIFT 1
803	#define VTD_BF_ECAP_REG_QI_MASK UINT64_C(0x0000000000000002)
804	/** DT: Device-TLB Support. */
805	#define VTD_BF_ECAP_REG_DT_SHIFT 2
806	#define VTD_BF_ECAP_REG_DT_MASK UINT64_C(0x0000000000000004)
807	/** IR: Interrupt Remapping Support. */
808	#define VTD_BF_ECAP_REG_IR_SHIFT 3
809	#define VTD_BF_ECAP_REG_IR_MASK UINT64_C(0x0000000000000008)
810	/** EIM: Extended Interrupt Mode. */
811	#define VTD_BF_ECAP_REG_EIM_SHIFT 4
812	#define VTD_BF_ECAP_REG_EIM_MASK UINT64_C(0x0000000000000010)
813	/** DEP: Deprecated MBZ. Reserved (bit 5). */
814	#define VTD_BF_ECAP_REG_RSVD_5_SHIFT 5
815	#define VTD_BF_ECAP_REG_RSVD_5_MASK UINT64_C(0x0000000000000020)
816	/** PT: Pass Through. */
817	#define VTD_BF_ECAP_REG_PT_SHIFT 6
818	#define VTD_BF_ECAP_REG_PT_MASK UINT64_C(0x0000000000000040)
819	/** SC: Snoop Control. */
820	#define VTD_BF_ECAP_REG_SC_SHIFT 7
821	#define VTD_BF_ECAP_REG_SC_MASK UINT64_C(0x0000000000000080)
822	/** IRO: IOTLB Register Offset. */
823	#define VTD_BF_ECAP_REG_IRO_SHIFT 8
824	#define VTD_BF_ECAP_REG_IRO_MASK UINT64_C(0x000000000003ff00)
825	/** R: Reserved (bits 19:18). */
826	#define VTD_BF_ECAP_REG_RSVD_19_18_SHIFT 18
827	#define VTD_BF_ECAP_REG_RSVD_19_18_MASK UINT64_C(0x00000000000c0000)
828	/** MHMV: Maximum Handle Mask Value. */
829	#define VTD_BF_ECAP_REG_MHMV_SHIFT 20
830	#define VTD_BF_ECAP_REG_MHMV_MASK UINT64_C(0x0000000000f00000)
831	/** DEP: Deprecated MBZ. Reserved (bit 24). */
832	#define VTD_BF_ECAP_REG_RSVD_24_SHIFT 24
833	#define VTD_BF_ECAP_REG_RSVD_24_MASK UINT64_C(0x0000000001000000)
834	/** MTS: Memory Type Support. */
835	#define VTD_BF_ECAP_REG_MTS_SHIFT 25
836	#define VTD_BF_ECAP_REG_MTS_MASK UINT64_C(0x0000000002000000)
837	/** NEST: Nested Translation Support. */
838	#define VTD_BF_ECAP_REG_NEST_SHIFT 26
839	#define VTD_BF_ECAP_REG_NEST_MASK UINT64_C(0x0000000004000000)
840	/** R: Reserved (bit 27). */
841	#define VTD_BF_ECAP_REG_RSVD_27_SHIFT 27
842	#define VTD_BF_ECAP_REG_RSVD_27_MASK UINT64_C(0x0000000008000000)
843	/** DEP: Deprecated MBZ. Reserved (bit 28). */
844	#define VTD_BF_ECAP_REG_RSVD_28_SHIFT 28
845	#define VTD_BF_ECAP_REG_RSVD_28_MASK UINT64_C(0x0000000010000000)
846	/** PRS: Page Request Support. */
847	#define VTD_BF_ECAP_REG_PRS_SHIFT 29
848	#define VTD_BF_ECAP_REG_PRS_MASK UINT64_C(0x0000000020000000)
849	/** ERS: Execute Request Support. */
850	#define VTD_BF_ECAP_REG_ERS_SHIFT 30
851	#define VTD_BF_ECAP_REG_ERS_MASK UINT64_C(0x0000000040000000)
852	/** SRS: Supervisor Request Support. */
853	#define VTD_BF_ECAP_REG_SRS_SHIFT 31
854	#define VTD_BF_ECAP_REG_SRS_MASK UINT64_C(0x0000000080000000)
855	/** R: Reserved (bit 32). */
856	#define VTD_BF_ECAP_REG_RSVD_32_SHIFT 32
857	#define VTD_BF_ECAP_REG_RSVD_32_MASK UINT64_C(0x0000000100000000)
858	/** NWFS: No Write Flag Support. */
859	#define VTD_BF_ECAP_REG_NWFS_SHIFT 33
860	#define VTD_BF_ECAP_REG_NWFS_MASK UINT64_C(0x0000000200000000)
861	/** EAFS: Extended Accessed Flags Support. */
862	#define VTD_BF_ECAP_REG_EAFS_SHIFT 34
863	#define VTD_BF_ECAP_REG_EAFS_MASK UINT64_C(0x0000000400000000)
864	/** PSS: PASID Size Supported. */
865	#define VTD_BF_ECAP_REG_PSS_SHIFT 35
866	#define VTD_BF_ECAP_REG_PSS_MASK UINT64_C(0x000000f800000000)
867	/** PASID: Process Address Space ID Support. */
868	#define VTD_BF_ECAP_REG_PASID_SHIFT 40
869	#define VTD_BF_ECAP_REG_PASID_MASK UINT64_C(0x0000010000000000)
870	/** DIT: Device-TLB Invalidation Throttle. */
871	#define VTD_BF_ECAP_REG_DIT_SHIFT 41
872	#define VTD_BF_ECAP_REG_DIT_MASK UINT64_C(0x0000020000000000)
873	/** PDS: Page-request Drain Support. */
874	#define VTD_BF_ECAP_REG_PDS_SHIFT 42
875	#define VTD_BF_ECAP_REG_PDS_MASK UINT64_C(0x0000040000000000)
876	/** SMTS: Scalable-Mode Translation Support. */
877	#define VTD_BF_ECAP_REG_SMTS_SHIFT 43
878	#define VTD_BF_ECAP_REG_SMTS_MASK UINT64_C(0x0000080000000000)
879	/** VCS: Virtual Command Support. */
880	#define VTD_BF_ECAP_REG_VCS_SHIFT 44
881	#define VTD_BF_ECAP_REG_VCS_MASK UINT64_C(0x0000100000000000)
882	/** SLADS: Second-Level Accessed/Dirty Support. */
883	#define VTD_BF_ECAP_REG_SLADS_SHIFT 45
884	#define VTD_BF_ECAP_REG_SLADS_MASK UINT64_C(0x0000200000000000)
885	/** SLTS: Second-Level Translation Support. */
886	#define VTD_BF_ECAP_REG_SLTS_SHIFT 46
887	#define VTD_BF_ECAP_REG_SLTS_MASK UINT64_C(0x0000400000000000)
888	/** FLTS: First-Level Translation Support. */
889	#define VTD_BF_ECAP_REG_FLTS_SHIFT 47
890	#define VTD_BF_ECAP_REG_FLTS_MASK UINT64_C(0x0000800000000000)
891	/** SMPWCS: Scalable-Mode Page-Walk Coherency Support. */
892	#define VTD_BF_ECAP_REG_SMPWCS_SHIFT 48
893	#define VTD_BF_ECAP_REG_SMPWCS_MASK UINT64_C(0x0001000000000000)
894	/** RPS: RID-PASID Support. */
895	#define VTD_BF_ECAP_REG_RPS_SHIFT 49
896	#define VTD_BF_ECAP_REG_RPS_MASK UINT64_C(0x0002000000000000)
897	/** R: Reserved (bits 51:50). */
898	#define VTD_BF_ECAP_REG_RSVD_51_50_SHIFT 50
899	#define VTD_BF_ECAP_REG_RSVD_51_50_MASK UINT64_C(0x000c000000000000)
900	/** ADMS: Abort DMA Mode Support. */
901	#define VTD_BF_ECAP_REG_ADMS_SHIFT 52
902	#define VTD_BF_ECAP_REG_ADMS_MASK UINT64_C(0x0010000000000000)
903	/** RPRIVS: RID_PRIV Support. */
904	#define VTD_BF_ECAP_REG_RPRIVS_SHIFT 53
905	#define VTD_BF_ECAP_REG_RPRIVS_MASK UINT64_C(0x0020000000000000)
906	/** R: Reserved (bits 63:54). */
907	#define VTD_BF_ECAP_REG_RSVD_63_54_SHIFT 54
908	#define VTD_BF_ECAP_REG_RSVD_63_54_MASK UINT64_C(0xffc0000000000000)
909	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_ECAP_REG_, UINT64_C(0), UINT64_MAX,
910	(C, QI, DT, IR, EIM, RSVD_5, PT, SC, IRO, RSVD_19_18, MHMV, RSVD_24, MTS, NEST, RSVD_27, RSVD_28,
911	PRS, ERS, SRS, RSVD_32, NWFS, EAFS, PSS, PASID, DIT, PDS, SMTS, VCS, SLADS, SLTS, FLTS, SMPWCS, RPS,
912	RSVD_51_50, ADMS, RPRIVS, RSVD_63_54));
913
914	/** RW: Read/write mask. */
915	#define VTD_ECAP_REG_RW_MASK UINT64_C(0)
916	/** @} */
917
918
919	/** @name Global Command Register (GCMD_REG).
920	* In accordance with the Intel spec.
921	* @{ */
922	/** R: Reserved (bits 22:0). */
923	#define VTD_BF_GCMD_REG_RSVD_22_0_SHIFT 0
924	#define VTD_BF_GCMD_REG_RSVD_22_0_MASK UINT32_C(0x007fffff)
925	/** CFI: Compatibility Format Interrupt. */
926	#define VTD_BF_GCMD_REG_CFI_SHIFT 23
927	#define VTD_BF_GCMD_REG_CFI_MASK UINT32_C(0x00800000)
928	/** SIRTP: Set Interrupt Table Remap Pointer. */
929	#define VTD_BF_GCMD_REG_SIRTP_SHIFT 24
930	#define VTD_BF_GCMD_REG_SIRTP_MASK UINT32_C(0x01000000)
931	/** IRE: Interrupt Remap Enable. */
932	#define VTD_BF_GCMD_REG_IRE_SHIFT 25
933	#define VTD_BF_GCMD_REG_IRE_MASK UINT32_C(0x02000000)
934	/** QIE: Queued Invalidation Enable. */
935	#define VTD_BF_GCMD_REG_QIE_SHIFT 26
936	#define VTD_BF_GCMD_REG_QIE_MASK UINT32_C(0x04000000)
937	/** WBF: Write Buffer Flush. */
938	#define VTD_BF_GCMD_REG_WBF_SHIFT 27
939	#define VTD_BF_GCMD_REG_WBF_MASK UINT32_C(0x08000000)
940	/** EAFL: Enable Advance Fault Logging. */
941	#define VTD_BF_GCMD_REG_EAFL_SHIFT 28
942	#define VTD_BF_GCMD_REG_EAFL_MASK UINT32_C(0x10000000)
943	/** SFL: Set Fault Log. */
944	#define VTD_BF_GCMD_REG_SFL_SHIFT 29
945	#define VTD_BF_GCMD_REG_SFL_MASK UINT32_C(0x20000000)
946	/** SRTP: Set Root Table Pointer. */
947	#define VTD_BF_GCMD_REG_SRTP_SHIFT 30
948	#define VTD_BF_GCMD_REG_SRTP_MASK UINT32_C(0x40000000)
949	/** TE: Translation Enable. */
950	#define VTD_BF_GCMD_REG_TE_SHIFT 31
951	#define VTD_BF_GCMD_REG_TE_MASK UINT32_C(0x80000000)
952	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_GCMD_REG_, UINT32_C(0), UINT32_MAX,
953	(RSVD_22_0, CFI, SIRTP, IRE, QIE, WBF, EAFL, SFL, SRTP, TE));
954
955	/** RW: Read/write mask. */
956	#define VTD_GCMD_REG_RW_MASK UINT32_C(0xff800000)
957	/** @} */
958
959
960	/** @name Global Status Register (GSTS_REG).
961	* In accordance with the Intel spec.
962	* @{ */
963	/** R: Reserved (bits 22:0). */
964	#define VTD_BF_GSTS_REG_RSVD_22_0_SHIFT 0
965	#define VTD_BF_GSTS_REG_RSVD_22_0_MASK UINT32_C(0x007fffff)
966	/** CFIS: Compatibility Format Interrupt Status. */
967	#define VTD_BF_GSTS_REG_CFIS_SHIFT 23
968	#define VTD_BF_GSTS_REG_CFIS_MASK UINT32_C(0x00800000)
969	/** IRTPS: Interrupt Remapping Table Pointer Status. */
970	#define VTD_BF_GSTS_REG_IRTPS_SHIFT 24
971	#define VTD_BF_GSTS_REG_IRTPS_MASK UINT32_C(0x01000000)
972	/** IRES: Interrupt Remapping Enable Status. */
973	#define VTD_BF_GSTS_REG_IRES_SHIFT 25
974	#define VTD_BF_GSTS_REG_IRES_MASK UINT32_C(0x02000000)
975	/** QIES: Queued Invalidation Enable Status. */
976	#define VTD_BF_GSTS_REG_QIES_SHIFT 26
977	#define VTD_BF_GSTS_REG_QIES_MASK UINT32_C(0x04000000)
978	/** WBFS: Write Buffer Flush Status. */
979	#define VTD_BF_GSTS_REG_WBFS_SHIFT 27
980	#define VTD_BF_GSTS_REG_WBFS_MASK UINT32_C(0x08000000)
981	/** AFLS: Advanced Fault Logging Status. */
982	#define VTD_BF_GSTS_REG_AFLS_SHIFT 28
983	#define VTD_BF_GSTS_REG_AFLS_MASK UINT32_C(0x10000000)
984	/** FLS: Fault Log Status. */
985	#define VTD_BF_GSTS_REG_FLS_SHIFT 29
986	#define VTD_BF_GSTS_REG_FLS_MASK UINT32_C(0x20000000)
987	/** RTPS: Root Table Pointer Status. */
988	#define VTD_BF_GSTS_REG_RTPS_SHIFT 30
989	#define VTD_BF_GSTS_REG_RTPS_MASK UINT32_C(0x40000000)
990	/** TES: Translation Enable Status. */
991	#define VTD_BF_GSTS_REG_TES_SHIFT 31
992	#define VTD_BF_GSTS_REG_TES_MASK UINT32_C(0x80000000)
993	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_GSTS_REG_, UINT32_C(0), UINT32_MAX,
994	(RSVD_22_0, CFIS, IRTPS, IRES, QIES, WBFS, AFLS, FLS, RTPS, TES));
995
996	/** RW: Read/write mask. */
997	#define VTD_GSTS_REG_RW_MASK UINT32_C(0)
998	/** @} */
999
1000
1001	/** @name Root Table Address Register (RTADDR_REG).
1002	* In accordance with the Intel spec.
1003	* @{ */
1004	/** R: Reserved (bits 9:0). */
1005	#define VTD_BF_RTADDR_REG_RSVD_9_0_SHIFT 0
1006	#define VTD_BF_RTADDR_REG_RSVD_9_0_MASK UINT64_C(0x00000000000003ff)
1007	/** TTM: Translation Table Mode. */
1008	#define VTD_BF_RTADDR_REG_TTM_SHIFT 10
1009	#define VTD_BF_RTADDR_REG_TTM_MASK UINT64_C(0x0000000000000c00)
1010	/** RTA: Root Table Address. */
1011	#define VTD_BF_RTADDR_REG_RTA_SHIFT 12
1012	#define VTD_BF_RTADDR_REG_RTA_MASK UINT64_C(0xfffffffffffff000)
1013	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_RTADDR_REG_, UINT64_C(0), UINT64_MAX,
1014	(RSVD_9_0, TTM, RTA));
1015
1016	/** RW: Read/write mask. */
1017	#define VTD_RTADDR_REG_RW_MASK UINT64_C(0xfffffffffffffc00)
1018
1019	/** RTADDR_REG.TTM: Legacy mode. */
1020	#define VTD_TTM_LEGACY_MODE 0
1021	/** RTADDR_REG.TTM: Scalable mode. */
1022	#define VTD_TTM_SCALABLE_MODE 1
1023	/** RTADDR_REG.TTM: Reserved. */
1024	#define VTD_TTM_RSVD 2
1025	/** RTADDR_REG.TTM: Abort DMA mode. */
1026	#define VTD_TTM_ABORT_DMA_MODE 3
1027	/** @} */
1028
1029
1030	/** @name Context Command Register (CCMD_REG).
1031	* In accordance with the Intel spec.
1032	* @{ */
1033	/** DID: Domain-ID. */
1034	#define VTD_BF_CCMD_REG_DID_SHIFT 0
1035	#define VTD_BF_CCMD_REG_DID_MASK UINT64_C(0x000000000000ffff)
1036	/** SID: Source-ID. */
1037	#define VTD_BF_CCMD_REG_SID_SHIFT 16
1038	#define VTD_BF_CCMD_REG_SID_MASK UINT64_C(0x00000000ffff0000)
1039	/** FM: Function Mask. */
1040	#define VTD_BF_CCMD_REG_FM_SHIFT 32
1041	#define VTD_BF_CCMD_REG_FM_MASK UINT64_C(0x0000000300000000)
1042	/** R: Reserved (bits 58:34). */
1043	#define VTD_BF_CCMD_REG_RSVD_58_34_SHIFT 34
1044	#define VTD_BF_CCMD_REG_RSVD_58_34_MASK UINT64_C(0x07fffffc00000000)
1045	/** CAIG: Context Actual Invalidation Granularity. */
1046	#define VTD_BF_CCMD_REG_CAIG_SHIFT 59
1047	#define VTD_BF_CCMD_REG_CAIG_MASK UINT64_C(0x1800000000000000)
1048	/** CIRG: Context Invalidation Request Granularity. */
1049	#define VTD_BF_CCMD_REG_CIRG_SHIFT 61
1050	#define VTD_BF_CCMD_REG_CIRG_MASK UINT64_C(0x6000000000000000)
1051	/** ICC: Invalidation Context Cache. */
1052	#define VTD_BF_CCMD_REG_ICC_SHIFT 63
1053	#define VTD_BF_CCMD_REG_ICC_MASK UINT64_C(0x8000000000000000)
1054	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_CCMD_REG_, UINT64_C(0), UINT64_MAX,
1055	(DID, SID, FM, RSVD_58_34, CAIG, CIRG, ICC));
1056
1057	/** RW: Read/write mask. */
1058	#define VTD_CCMD_REG_RW_MASK ( VTD_BF_CCMD_REG_DID_MASK \| VTD_BF_CCMD_REG_SID_MASK \
1059	\| VTD_BF_CCMD_REG_FM_MASK \| VTD_BF_CCMD_REG_CIRG_MASK \
1060	\| VTD_BF_CCMD_REG_ICC_MASK)
1061	/** @} */
1062
1063
1064	/** @name IOTLB Invalidation Register (IOTLB_REG).
1065	* In accordance with the Intel spec.
1066	* @{ */
1067	/** R: Reserved (bits 31:0). */
1068	#define VTD_BF_IOTLB_REG_RSVD_31_0_SHIFT 0
1069	#define VTD_BF_IOTLB_REG_RSVD_31_0_MASK UINT64_C(0x00000000ffffffff)
1070	/** DID: Domain-ID. */
1071	#define VTD_BF_IOTLB_REG_DID_SHIFT 32
1072	#define VTD_BF_IOTLB_REG_DID_MASK UINT64_C(0x0000ffff00000000)
1073	/** DW: Draining Writes. */
1074	#define VTD_BF_IOTLB_REG_DW_SHIFT 48
1075	#define VTD_BF_IOTLB_REG_DW_MASK UINT64_C(0x0001000000000000)
1076	/** DR: Draining Reads. */
1077	#define VTD_BF_IOTLB_REG_DR_SHIFT 49
1078	#define VTD_BF_IOTLB_REG_DR_MASK UINT64_C(0x0002000000000000)
1079	/** R: Reserved (bits 56:50). */
1080	#define VTD_BF_IOTLB_REG_RSVD_56_50_SHIFT 50
1081	#define VTD_BF_IOTLB_REG_RSVD_56_50_MASK UINT64_C(0x01fc000000000000)
1082	/** IAIG: IOTLB Actual Invalidation Granularity. */
1083	#define VTD_BF_IOTLB_REG_IAIG_SHIFT 57
1084	#define VTD_BF_IOTLB_REG_IAIG_MASK UINT64_C(0x0600000000000000)
1085	/** R: Reserved (bit 59). */
1086	#define VTD_BF_IOTLB_REG_RSVD_59_SHIFT 59
1087	#define VTD_BF_IOTLB_REG_RSVD_59_MASK UINT64_C(0x0800000000000000)
1088	/** IIRG: IOTLB Invalidation Request Granularity. */
1089	#define VTD_BF_IOTLB_REG_IIRG_SHIFT 60
1090	#define VTD_BF_IOTLB_REG_IIRG_MASK UINT64_C(0x3000000000000000)
1091	/** R: Reserved (bit 62). */
1092	#define VTD_BF_IOTLB_REG_RSVD_62_SHIFT 62
1093	#define VTD_BF_IOTLB_REG_RSVD_62_MASK UINT64_C(0x4000000000000000)
1094	/** IVT: Invalidate IOTLB. */
1095	#define VTD_BF_IOTLB_REG_IVT_SHIFT 63
1096	#define VTD_BF_IOTLB_REG_IVT_MASK UINT64_C(0x8000000000000000)
1097	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IOTLB_REG_, UINT64_C(0), UINT64_MAX,
1098	(RSVD_31_0, DID, DW, DR, RSVD_56_50, IAIG, RSVD_59, IIRG, RSVD_62, IVT));
1099
1100	/** RW: Read/write mask. */
1101	#define VTD_IOTLB_REG_RW_MASK ( VTD_BF_IOTLB_REG_DID_MASK \| VTD_BF_IOTLB_REG_DW_MASK \
1102	\| VTD_BF_IOTLB_REG_DR_MASK \| VTD_BF_IOTLB_REG_IIRG_MASK \
1103	\| VTD_BF_IOTLB_REG_IVT_MASK)
1104	/** @} */
1105
1106
1107	/** @name Invalidate Address Register (IVA_REG).
1108	* In accordance with the Intel spec.
1109	* @{ */
1110	/** AM: Address Mask. */
1111	#define VTD_BF_IVA_REG_AM_SHIFT 0
1112	#define VTD_BF_IVA_REG_AM_MASK UINT64_C(0x000000000000003f)
1113	/** IH: Invalidation Hint. */
1114	#define VTD_BF_IVA_REG_IH_SHIFT 6
1115	#define VTD_BF_IVA_REG_IH_MASK UINT64_C(0x0000000000000040)
1116	/** R: Reserved (bits 11:7). */
1117	#define VTD_BF_IVA_REG_RSVD_11_7_SHIFT 7
1118	#define VTD_BF_IVA_REG_RSVD_11_7_MASK UINT64_C(0x0000000000000f80)
1119	/** ADDR: Address. */
1120	#define VTD_BF_IVA_REG_ADDR_SHIFT 12
1121	#define VTD_BF_IVA_REG_ADDR_MASK UINT64_C(0xfffffffffffff000)
1122	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IVA_REG_, UINT64_C(0), UINT64_MAX,
1123	(AM, IH, RSVD_11_7, ADDR));
1124
1125	/** RW: Read/write mask. */
1126	#define VTD_IVA_REG_RW_MASK ( VTD_BF_IVA_REG_AM_MASK \| VTD_BF_IVA_REG_IH_MASK \
1127	\| VTD_BF_IVA_REG_ADDR_MASK)
1128	/** @} */
1129
1130
1131	/** @name Fault Status Register (FSTS_REG).
1132	* In accordance with the Intel spec.
1133	* @{ */
1134	/** PFO: Primary Fault Overflow. */
1135	#define VTD_BF_FSTS_REG_PFO_SHIFT 0
1136	#define VTD_BF_FSTS_REG_PFO_MASK UINT32_C(0x00000001)
1137	/** PPF: Primary Pending Fault. */
1138	#define VTD_BF_FSTS_REG_PPF_SHIFT 1
1139	#define VTD_BF_FSTS_REG_PPF_MASK UINT32_C(0x00000002)
1140	/** AFO: Advanced Fault Overflow. */
1141	#define VTD_BF_FSTS_REG_AFO_SHIFT 2
1142	#define VTD_BF_FSTS_REG_AFO_MASK UINT32_C(0x00000004)
1143	/** APF: Advanced Pending Fault. */
1144	#define VTD_BF_FSTS_REG_APF_SHIFT 3
1145	#define VTD_BF_FSTS_REG_APF_MASK UINT32_C(0x00000008)
1146	/** IQE: Invalidation Queue Error. */
1147	#define VTD_BF_FSTS_REG_IQE_SHIFT 4
1148	#define VTD_BF_FSTS_REG_IQE_MASK UINT32_C(0x00000010)
1149	/** ICE: Invalidation Completion Error. */
1150	#define VTD_BF_FSTS_REG_ICE_SHIFT 5
1151	#define VTD_BF_FSTS_REG_ICE_MASK UINT32_C(0x00000020)
1152	/** ITE: Invalidation Timeout Error. */
1153	#define VTD_BF_FSTS_REG_ITE_SHIFT 6
1154	#define VTD_BF_FSTS_REG_ITE_MASK UINT32_C(0x00000040)
1155	/** DEP: Deprecated MBZ. Reserved (bit 7). */
1156	#define VTD_BF_FSTS_REG_RSVD_7_SHIFT 7
1157	#define VTD_BF_FSTS_REG_RSVD_7_MASK UINT32_C(0x00000080)
1158	/** FRI: Fault Record Index. */
1159	#define VTD_BF_FSTS_REG_FRI_SHIFT 8
1160	#define VTD_BF_FSTS_REG_FRI_MASK UINT32_C(0x0000ff00)
1161	/** R: Reserved (bits 31:16). */
1162	#define VTD_BF_FSTS_REG_RSVD_31_16_SHIFT 16
1163	#define VTD_BF_FSTS_REG_RSVD_31_16_MASK UINT32_C(0xffff0000)
1164	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_FSTS_REG_, UINT32_C(0), UINT32_MAX,
1165	(PFO, PPF, AFO, APF, IQE, ICE, ITE, RSVD_7, FRI, RSVD_31_16));
1166
1167	/** RW: Read/write mask. */
1168	#define VTD_FSTS_REG_RW_MASK ( VTD_BF_FSTS_REG_PFO_MASK \| VTD_BF_FSTS_REG_AFO_MASK \
1169	\| VTD_BF_FSTS_REG_APF_MASK \| VTD_BF_FSTS_REG_IQE_MASK \
1170	\| VTD_BF_FSTS_REG_ICE_MASK \| VTD_BF_FSTS_REG_ITE_MASK)
1171	/** RW1C: Read-only-status, Write-1-to-clear status mask. */
1172	#define VTD_FSTS_REG_RW1C_MASK ( VTD_BF_FSTS_REG_PFO_MASK \| VTD_BF_FSTS_REG_AFO_MASK \
1173	\| VTD_BF_FSTS_REG_APF_MASK \| VTD_BF_FSTS_REG_IQE_MASK \
1174	\| VTD_BF_FSTS_REG_ICE_MASK \| VTD_BF_FSTS_REG_ITE_MASK)
1175	/** @} */
1176
1177
1178	/** @name Fault Event Control Register (FECTL_REG).
1179	* In accordance with the Intel spec.
1180	* @{ */
1181	/** R: Reserved (bits 29:0). */
1182	#define VTD_BF_FECTL_REG_RSVD_29_0_SHIFT 0
1183	#define VTD_BF_FECTL_REG_RSVD_29_0_MASK UINT32_C(0x3fffffff)
1184	/** IP: Interrupt Pending. */
1185	#define VTD_BF_FECTL_REG_IP_SHIFT 30
1186	#define VTD_BF_FECTL_REG_IP_MASK UINT32_C(0x40000000)
1187	/** IM: Interrupt Mask. */
1188	#define VTD_BF_FECTL_REG_IM_SHIFT 31
1189	#define VTD_BF_FECTL_REG_IM_MASK UINT32_C(0x80000000)
1190	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_FECTL_REG_, UINT32_C(0), UINT32_MAX,
1191	(RSVD_29_0, IP, IM));
1192
1193	/** RW: Read/write mask. */
1194	#define VTD_FECTL_REG_RW_MASK VTD_BF_FECTL_REG_IM_MASK
1195	/** @} */
1196
1197
1198	/** @name Fault Event Data Register (FEDATA_REG).
1199	* In accordance with the Intel spec.
1200	* @{ */
1201	/** IMD: Interrupt Message Data. */
1202	#define VTD_BF_FEDATA_REG_IMD_SHIFT 0
1203	#define VTD_BF_FEDATA_REG_IMD_MASK UINT32_C(0x0000ffff)
1204	/** R: Reserved (bits 31:16). VT-d specs. prior to 2021 had EIMD here. */
1205	#define VTD_BF_FEDATA_REG_RSVD_31_16_SHIFT 16
1206	#define VTD_BF_FEDATA_REG_RSVD_31_16_MASK UINT32_C(0xffff0000)
1207	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_FEDATA_REG_, UINT32_C(0), UINT32_MAX,
1208	(IMD, RSVD_31_16));
1209
1210	/** RW: Read/write mask. */
1211	#define VTD_FEDATA_REG_RW_MASK VTD_BF_FEDATA_REG_IMD_MASK
1212	/** @} */
1213
1214
1215	/** @name Fault Event Address Register (FEADDR_REG).
1216	* In accordance with the Intel spec.
1217	* @{ */
1218	/** R: Reserved (bits 1:0). */
1219	#define VTD_BF_FEADDR_REG_RSVD_1_0_SHIFT 0
1220	#define VTD_BF_FEADDR_REG_RSVD_1_0_MASK UINT32_C(0x00000003)
1221	/** MA: Message Address. */
1222	#define VTD_BF_FEADDR_REG_MA_SHIFT 2
1223	#define VTD_BF_FEADDR_REG_MA_MASK UINT32_C(0xfffffffc)
1224	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_FEADDR_REG_, UINT32_C(0), UINT32_MAX,
1225	(RSVD_1_0, MA));
1226
1227	/** RW: Read/write mask. */
1228	#define VTD_FEADDR_REG_RW_MASK VTD_BF_FEADDR_REG_MA_MASK
1229	/** @} */
1230
1231
1232	/** @name Fault Event Upper Address Register (FEUADDR_REG).
1233	* In accordance with the Intel spec.
1234	* @{ */
1235	/** MUA: Message Upper Address. */
1236	#define VTD_BF_FEUADDR_REG_MA_SHIFT 0
1237	#define VTD_BF_FEUADDR_REG_MA_MASK UINT32_C(0xffffffff)
1238
1239	/** RW: Read/write mask. */
1240	#define VTD_FEUADDR_REG_RW_MASK VTD_BF_FEUADDR_REG_MA_MASK
1241	/** @} */
1242
1243
1244	/** @name Fault Recording Register (FRCD_REG).
1245	* In accordance with the Intel spec.
1246	* @{ */
1247	/** R: Reserved (bits 11:0). */
1248	#define VTD_BF_0_FRCD_REG_RSVD_11_0_SHIFT 0
1249	#define VTD_BF_0_FRCD_REG_RSVD_11_0_MASK UINT64_C(0x0000000000000fff)
1250	/** FI: Fault Info. */
1251	#define VTD_BF_0_FRCD_REG_FI_SHIFT 12
1252	#define VTD_BF_0_FRCD_REG_FI_MASK UINT64_C(0xfffffffffffff000)
1253	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_FRCD_REG_, UINT64_C(0), UINT64_MAX,
1254	(RSVD_11_0, FI));
1255
1256	/** SID: Source Identifier. */
1257	#define VTD_BF_1_FRCD_REG_SID_SHIFT 0
1258	#define VTD_BF_1_FRCD_REG_SID_MASK UINT64_C(0x000000000000ffff)
1259	/** R: Reserved (bits 27:16). */
1260	#define VTD_BF_1_FRCD_REG_RSVD_27_16_SHIFT 16
1261	#define VTD_BF_1_FRCD_REG_RSVD_27_16_MASK UINT64_C(0x000000000fff0000)
1262	/** T2: Type bit 2. */
1263	#define VTD_BF_1_FRCD_REG_T2_SHIFT 28
1264	#define VTD_BF_1_FRCD_REG_T2_MASK UINT64_C(0x0000000010000000)
1265	/** PRIV: Privilege Mode. */
1266	#define VTD_BF_1_FRCD_REG_PRIV_SHIFT 29
1267	#define VTD_BF_1_FRCD_REG_PRIV_MASK UINT64_C(0x0000000020000000)
1268	/** EXE: Execute Permission Requested. */
1269	#define VTD_BF_1_FRCD_REG_EXE_SHIFT 30
1270	#define VTD_BF_1_FRCD_REG_EXE_MASK UINT64_C(0x0000000040000000)
1271	/** PP: PASID Present. */
1272	#define VTD_BF_1_FRCD_REG_PP_SHIFT 31
1273	#define VTD_BF_1_FRCD_REG_PP_MASK UINT64_C(0x0000000080000000)
1274	/** FR: Fault Reason. */
1275	#define VTD_BF_1_FRCD_REG_FR_SHIFT 32
1276	#define VTD_BF_1_FRCD_REG_FR_MASK UINT64_C(0x000000ff00000000)
1277	/** PV: PASID Value. */
1278	#define VTD_BF_1_FRCD_REG_PV_SHIFT 40
1279	#define VTD_BF_1_FRCD_REG_PV_MASK UINT64_C(0x0fffff0000000000)
1280	/** AT: Address Type. */
1281	#define VTD_BF_1_FRCD_REG_AT_SHIFT 60
1282	#define VTD_BF_1_FRCD_REG_AT_MASK UINT64_C(0x3000000000000000)
1283	/** T1: Type bit 1. */
1284	#define VTD_BF_1_FRCD_REG_T1_SHIFT 62
1285	#define VTD_BF_1_FRCD_REG_T1_MASK UINT64_C(0x4000000000000000)
1286	/** F: Fault. */
1287	#define VTD_BF_1_FRCD_REG_F_SHIFT 63
1288	#define VTD_BF_1_FRCD_REG_F_MASK UINT64_C(0x8000000000000000)
1289	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_FRCD_REG_, UINT64_C(0), UINT64_MAX,
1290	(SID, RSVD_27_16, T2, PRIV, EXE, PP, FR, PV, AT, T1, F));
1291
1292	/** RW: Read/write mask. */
1293	#define VTD_FRCD_REG_LO_RW_MASK UINT64_C(0)
1294	#define VTD_FRCD_REG_HI_RW_MASK VTD_BF_1_FRCD_REG_F_MASK
1295	/** RW1C: Read-only-status, Write-1-to-clear status mask. */
1296	#define VTD_FRCD_REG_LO_RW1C_MASK UINT64_C(0)
1297	#define VTD_FRCD_REG_HI_RW1C_MASK VTD_BF_1_FRCD_REG_F_MASK
1298	/** @} */
1299
1300
1301	/** @name Advanced Fault Log Register (AFLOG_REG).
1302	* In accordance with the Intel spec.
1303	* @{ */
1304	/** R: Reserved (bits 8:0). */
1305	#define VTD_BF_0_AFLOG_REG_RSVD_8_0_SHIFT 0
1306	#define VTD_BF_0_AFLOG_REG_RSVD_8_0_MASK UINT64_C(0x00000000000001ff)
1307	/** FLS: Fault Log Size. */
1308	#define VTD_BF_0_AFLOG_REG_FLS_SHIFT 9
1309	#define VTD_BF_0_AFLOG_REG_FLS_MASK UINT64_C(0x0000000000000e00)
1310	/** FLA: Fault Log Address. */
1311	#define VTD_BF_0_AFLOG_REG_FLA_SHIFT 12
1312	#define VTD_BF_0_AFLOG_REG_FLA_MASK UINT64_C(0xfffffffffffff000)
1313	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_AFLOG_REG_, UINT64_C(0), UINT64_MAX,
1314	(RSVD_8_0, FLS, FLA));
1315
1316	/** RW: Read/write mask. */
1317	#define VTD_AFLOG_REG_RW_MASK (VTD_BF_0_AFLOG_REG_FLS_MASK \| VTD_BF_0_AFLOG_REG_FLA_MASK)
1318	/** @} */
1319
1320
1321	/** @name Protected Memory Enable Register (PMEN_REG).
1322	* In accordance with the Intel spec.
1323	* @{ */
1324	/** PRS: Protected Region Status. */
1325	#define VTD_BF_PMEN_REG_PRS_SHIFT 0
1326	#define VTD_BF_PMEN_REG_PRS_MASK UINT32_C(0x00000001)
1327	/** R: Reserved (bits 30:1). */
1328	#define VTD_BF_PMEN_REG_RSVD_30_1_SHIFT 1
1329	#define VTD_BF_PMEN_REG_RSVD_30_1_MASK UINT32_C(0x7ffffffe)
1330	/** EPM: Enable Protected Memory. */
1331	#define VTD_BF_PMEN_REG_EPM_SHIFT 31
1332	#define VTD_BF_PMEN_REG_EPM_MASK UINT32_C(0x80000000)
1333	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_PMEN_REG_, UINT32_C(0), UINT32_MAX,
1334	(PRS, RSVD_30_1, EPM));
1335
1336	/** RW: Read/write mask. */
1337	#define VTD_PMEN_REG_RW_MASK VTD_BF_PMEN_REG_EPM_MASK
1338	/** @} */
1339
1340
1341	/** @name Invalidation Queue Head Register (IQH_REG).
1342	* In accordance with the Intel spec.
1343	* @{ */
1344	/** R: Reserved (bits 3:0). */
1345	#define VTD_BF_IQH_REG_RSVD_3_0_SHIFT 0
1346	#define VTD_BF_IQH_REG_RSVD_3_0_MASK UINT64_C(0x000000000000000f)
1347	/** QH: Queue Head. */
1348	#define VTD_BF_IQH_REG_QH_SHIFT 4
1349	#define VTD_BF_IQH_REG_QH_MASK UINT64_C(0x000000000007fff0)
1350	/** R: Reserved (bits 63:19). */
1351	#define VTD_BF_IQH_REG_RSVD_63_19_SHIFT 19
1352	#define VTD_BF_IQH_REG_RSVD_63_19_MASK UINT64_C(0xfffffffffff80000)
1353	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IQH_REG_, UINT64_C(0), UINT64_MAX,
1354	(RSVD_3_0, QH, RSVD_63_19));
1355
1356	/** RW: Read/write mask. */
1357	#define VTD_IQH_REG_RW_MASK UINT64_C(0x0)
1358	/** @} */
1359
1360
1361	/** @name Invalidation Queue Tail Register (IQT_REG).
1362	* In accordance with the Intel spec.
1363	* @{ */
1364	/** R: Reserved (bits 3:0). */
1365	#define VTD_BF_IQT_REG_RSVD_3_0_SHIFT 0
1366	#define VTD_BF_IQT_REG_RSVD_3_0_MASK UINT64_C(0x000000000000000f)
1367	/** QH: Queue Tail. */
1368	#define VTD_BF_IQT_REG_QT_SHIFT 4
1369	#define VTD_BF_IQT_REG_QT_MASK UINT64_C(0x000000000007fff0)
1370	/** R: Reserved (bits 63:19). */
1371	#define VTD_BF_IQT_REG_RSVD_63_19_SHIFT 19
1372	#define VTD_BF_IQT_REG_RSVD_63_19_MASK UINT64_C(0xfffffffffff80000)
1373	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IQT_REG_, UINT64_C(0), UINT64_MAX,
1374	(RSVD_3_0, QT, RSVD_63_19));
1375
1376	/** RW: Read/write mask. */
1377	#define VTD_IQT_REG_RW_MASK VTD_BF_IQT_REG_QT_MASK
1378	/** @} */
1379
1380
1381	/** @name Invalidation Queue Address Register (IQA_REG).
1382	* In accordance with the Intel spec.
1383	* @{ */
1384	/** QS: Queue Size. */
1385	#define VTD_BF_IQA_REG_QS_SHIFT 0
1386	#define VTD_BF_IQA_REG_QS_MASK UINT64_C(0x0000000000000007)
1387	/** R: Reserved (bits 10:3). */
1388	#define VTD_BF_IQA_REG_RSVD_10_3_SHIFT 3
1389	#define VTD_BF_IQA_REG_RSVD_10_3_MASK UINT64_C(0x00000000000007f8)
1390	/** DW: Descriptor Width. */
1391	#define VTD_BF_IQA_REG_DW_SHIFT 11
1392	#define VTD_BF_IQA_REG_DW_MASK UINT64_C(0x0000000000000800)
1393	/** IQA: Invalidation Queue Base Address. */
1394	#define VTD_BF_IQA_REG_IQA_SHIFT 12
1395	#define VTD_BF_IQA_REG_IQA_MASK UINT64_C(0xfffffffffffff000)
1396	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IQA_REG_, UINT64_C(0), UINT64_MAX,
1397	(QS, RSVD_10_3, DW, IQA));
1398
1399	/** RW: Read/write mask. */
1400	#define VTD_IQA_REG_RW_MASK ( VTD_BF_IQA_REG_QS_MASK \| VTD_BF_IQA_REG_DW_MASK \
1401	\| VTD_BF_IQA_REG_IQA_MASK)
1402	/** DW: 128-bit descriptor. */
1403	#define VTD_IQA_REG_DW_128_BIT 0
1404	/** DW: 256-bit descriptor. */
1405	#define VTD_IQA_REG_DW_256_BIT 1
1406	/** @} */
1407
1408
1409	/** @name Invalidation Completion Status Register (ICS_REG).
1410	* In accordance with the Intel spec.
1411	* @{ */
1412	/** IWC: Invalidation Wait Descriptor Complete. */
1413	#define VTD_BF_ICS_REG_IWC_SHIFT 0
1414	#define VTD_BF_ICS_REG_IWC_MASK UINT32_C(0x00000001)
1415	/** R: Reserved (bits 31:1). */
1416	#define VTD_BF_ICS_REG_RSVD_31_1_SHIFT 1
1417	#define VTD_BF_ICS_REG_RSVD_31_1_MASK UINT32_C(0xfffffffe)
1418	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_ICS_REG_, UINT32_C(0), UINT32_MAX,
1419	(IWC, RSVD_31_1));
1420
1421	/** RW: Read/write mask. */
1422	#define VTD_ICS_REG_RW_MASK VTD_BF_ICS_REG_IWC_MASK
1423	/** RW1C: Read-only-status, Write-1-to-clear status mask. */
1424	#define VTD_ICS_REG_RW1C_MASK VTD_BF_ICS_REG_IWC_MASK
1425	/** @} */
1426
1427
1428	/** @name Invalidation Event Control Register (IECTL_REG).
1429	* In accordance with the Intel spec.
1430	* @{ */
1431	/** R: Reserved (bits 29:0). */
1432	#define VTD_BF_IECTL_REG_RSVD_29_0_SHIFT 0
1433	#define VTD_BF_IECTL_REG_RSVD_29_0_MASK UINT32_C(0x3fffffff)
1434	/** IP: Interrupt Pending. */
1435	#define VTD_BF_IECTL_REG_IP_SHIFT 30
1436	#define VTD_BF_IECTL_REG_IP_MASK UINT32_C(0x40000000)
1437	/** IM: Interrupt Mask. */
1438	#define VTD_BF_IECTL_REG_IM_SHIFT 31
1439	#define VTD_BF_IECTL_REG_IM_MASK UINT32_C(0x80000000)
1440	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IECTL_REG_, UINT32_C(0), UINT32_MAX,
1441	(RSVD_29_0, IP, IM));
1442
1443	/** RW: Read/write mask. */
1444	#define VTD_IECTL_REG_RW_MASK VTD_BF_IECTL_REG_IM_MASK
1445	/** @} */
1446
1447
1448	/** @name Invalidation Event Data Register (IEDATA_REG).
1449	* In accordance with the Intel spec.
1450	* @{ */
1451	/** IMD: Interrupt Message Data. */
1452	#define VTD_BF_IEDATA_REG_IMD_SHIFT 0
1453	#define VTD_BF_IEDATA_REG_IMD_MASK UINT32_C(0x0000ffff)
1454	/** R: Reserved (bits 31:16). VT-d specs. prior to 2021 had EIMD here. */
1455	#define VTD_BF_IEDATA_REG_RSVD_31_16_SHIFT 16
1456	#define VTD_BF_IEDATA_REG_RSVD_31_16_MASK UINT32_C(0xffff0000)
1457	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IEDATA_REG_, UINT32_C(0), UINT32_MAX,
1458	(IMD, RSVD_31_16));
1459
1460	/** RW: Read/write mask. */
1461	#define VTD_IEDATA_REG_RW_MASK VTD_BF_IEDATA_REG_IMD_MASK
1462	/** @} */
1463
1464
1465	/** @name Invalidation Event Address Register (IEADDR_REG).
1466	* In accordance with the Intel spec.
1467	* @{ */
1468	/** R: Reserved (bits 1:0). */
1469	#define VTD_BF_IEADDR_REG_RSVD_1_0_SHIFT 0
1470	#define VTD_BF_IEADDR_REG_RSVD_1_0_MASK UINT32_C(0x00000003)
1471	/** MA: Message Address. */
1472	#define VTD_BF_IEADDR_REG_MA_SHIFT 2
1473	#define VTD_BF_IEADDR_REG_MA_MASK UINT32_C(0xfffffffc)
1474	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IEADDR_REG_, UINT32_C(0), UINT32_MAX,
1475	(RSVD_1_0, MA));
1476
1477	/** RW: Read/write mask. */
1478	#define VTD_IEADDR_REG_RW_MASK VTD_BF_IEADDR_REG_MA_MASK
1479	/** @} */
1480
1481
1482	/** @name Invalidation Event Upper Address Register (IEUADDR_REG).
1483	* @{ */
1484	/** MUA: Message Upper Address. */
1485	#define VTD_BF_IEUADDR_REG_MUA_SHIFT 0
1486	#define VTD_BF_IEUADDR_REG_MUA_MASK UINT32_C(0xffffffff)
1487
1488	/** RW: Read/write mask. */
1489	#define VTD_IEUADDR_REG_RW_MASK VTD_BF_IEUADDR_REG_MUA_MASK
1490	/** @} */
1491
1492
1493	/** @name Invalidation Queue Error Record Register (IQERCD_REG).
1494	* In accordance with the Intel spec.
1495	* @{ */
1496	/** IQEI: Invalidation Queue Error Info. */
1497	#define VTD_BF_IQERCD_REG_IQEI_SHIFT 0
1498	#define VTD_BF_IQERCD_REG_IQEI_MASK UINT64_C(0x000000000000000f)
1499	/** R: Reserved (bits 31:4). */
1500	#define VTD_BF_IQERCD_REG_RSVD_31_4_SHIFT 4
1501	#define VTD_BF_IQERCD_REG_RSVD_31_4_MASK UINT64_C(0x00000000fffffff0)
1502	/** ITESID: Invalidation Timeout Error Source Identifier. */
1503	#define VTD_BF_IQERCD_REG_ITESID_SHIFT 32
1504	#define VTD_BF_IQERCD_REG_ITESID_MASK UINT64_C(0x0000ffff00000000)
1505	/** ICESID: Invalidation Completion Error Source Identifier. */
1506	#define VTD_BF_IQERCD_REG_ICESID_SHIFT 48
1507	#define VTD_BF_IQERCD_REG_ICESID_MASK UINT64_C(0xffff000000000000)
1508	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IQERCD_REG_, UINT64_C(0), UINT64_MAX,
1509	(IQEI, RSVD_31_4, ITESID, ICESID));
1510
1511	/** RW: Read/write mask. */
1512	#define VTD_IQERCD_REG_RW_MASK UINT64_C(0)
1513
1514	/** Invalidation Queue Error Information. */
1515	typedef enum VTD_IQEI_T
1516	{
1517	kIqei_InfoNotAvailable = 0,
1518	kIqei_InvalidTailPointer,
1519	kIqei_FetchDescriptorError,
1520	kIqei_InvalidDescriptorType,
1521	kIqei_RsvdFieldViolation,
1522	kIqei_InvalidDescriptorWidth,
1523	kIqei_QueueTailNotAligned,
1524	kIqei_InvalidTtm
1525	} VTD_IQEI_T;
1526	/** @} */
1527
1528
1529	/** @name Interrupt Remapping Table Address Register (IRTA_REG).
1530	* In accordance with the Intel spec.
1531	* @{ */
1532	/** S: Size. */
1533	#define VTD_BF_IRTA_REG_S_SHIFT 0
1534	#define VTD_BF_IRTA_REG_S_MASK UINT64_C(0x000000000000000f)
1535	/** R: Reserved (bits 10:4). */
1536	#define VTD_BF_IRTA_REG_RSVD_10_4_SHIFT 4
1537	#define VTD_BF_IRTA_REG_RSVD_10_4_MASK UINT64_C(0x00000000000007f0)
1538	/** EIME: Extended Interrupt Mode Enable. */
1539	#define VTD_BF_IRTA_REG_EIME_SHIFT 11
1540	#define VTD_BF_IRTA_REG_EIME_MASK UINT64_C(0x0000000000000800)
1541	/** IRTA: Interrupt Remapping Table Address. */
1542	#define VTD_BF_IRTA_REG_IRTA_SHIFT 12
1543	#define VTD_BF_IRTA_REG_IRTA_MASK UINT64_C(0xfffffffffffff000)
1544	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IRTA_REG_, UINT64_C(0), UINT64_MAX,
1545	(S, RSVD_10_4, EIME, IRTA));
1546
1547	/** RW: Read/write mask. */
1548	#define VTD_IRTA_REG_RW_MASK ( VTD_BF_IRTA_REG_S_MASK \| VTD_BF_IRTA_REG_EIME_MASK \
1549	\| VTD_BF_IRTA_REG_IRTA_MASK)
1550	/** @} */
1551
1552
1553	/** @name Page Request Queue Head Register (PQH_REG).
1554	* In accordance with the Intel spec.
1555	* @{ */
1556	/** R: Reserved (bits 4:0). */
1557	#define VTD_BF_PQH_REG_RSVD_4_0_SHIFT 0
1558	#define VTD_BF_PQH_REG_RSVD_4_0_MASK UINT64_C(0x000000000000001f)
1559	/** PQH: Page Queue Head. */
1560	#define VTD_BF_PQH_REG_PQH_SHIFT 5
1561	#define VTD_BF_PQH_REG_PQH_MASK UINT64_C(0x000000000007ffe0)
1562	/** R: Reserved (bits 63:19). */
1563	#define VTD_BF_PQH_REG_RSVD_63_19_SHIFT 19
1564	#define VTD_BF_PQH_REG_RSVD_63_19_MASK UINT64_C(0xfffffffffff80000)
1565	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_PQH_REG_, UINT64_C(0), UINT64_MAX,
1566	(RSVD_4_0, PQH, RSVD_63_19));
1567
1568	/** RW: Read/write mask. */
1569	#define VTD_PQH_REG_RW_MASK VTD_BF_PQH_REG_PQH_MASK
1570	/** @} */
1571
1572
1573	/** @name Page Request Queue Tail Register (PQT_REG).
1574	* In accordance with the Intel spec.
1575	* @{ */
1576	/** R: Reserved (bits 4:0). */
1577	#define VTD_BF_PQT_REG_RSVD_4_0_SHIFT 0
1578	#define VTD_BF_PQT_REG_RSVD_4_0_MASK UINT64_C(0x000000000000001f)
1579	/** PQT: Page Queue Tail. */
1580	#define VTD_BF_PQT_REG_PQT_SHIFT 5
1581	#define VTD_BF_PQT_REG_PQT_MASK UINT64_C(0x000000000007ffe0)
1582	/** R: Reserved (bits 63:19). */
1583	#define VTD_BF_PQT_REG_RSVD_63_19_SHIFT 19
1584	#define VTD_BF_PQT_REG_RSVD_63_19_MASK UINT64_C(0xfffffffffff80000)
1585	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_PQT_REG_, UINT64_C(0), UINT64_MAX,
1586	(RSVD_4_0, PQT, RSVD_63_19));
1587
1588	/** RW: Read/write mask. */
1589	#define VTD_PQT_REG_RW_MASK VTD_BF_PQT_REG_PQT_MASK
1590	/** @} */
1591
1592
1593	/** @name Page Request Queue Address Register (PQA_REG).
1594	* In accordance with the Intel spec.
1595	* @{ */
1596	/** PQS: Page Queue Size. */
1597	#define VTD_BF_PQA_REG_PQS_SHIFT 0
1598	#define VTD_BF_PQA_REG_PQS_MASK UINT64_C(0x0000000000000007)
1599	/** R: Reserved bits (11:3). */
1600	#define VTD_BF_PQA_REG_RSVD_11_3_SHIFT 3
1601	#define VTD_BF_PQA_REG_RSVD_11_3_MASK UINT64_C(0x0000000000000ff8)
1602	/** PQA: Page Request Queue Base Address. */
1603	#define VTD_BF_PQA_REG_PQA_SHIFT 12
1604	#define VTD_BF_PQA_REG_PQA_MASK UINT64_C(0xfffffffffffff000)
1605	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_PQA_REG_, UINT64_C(0), UINT64_MAX,
1606	(PQS, RSVD_11_3, PQA));
1607
1608	/** RW: Read/write mask. */
1609	#define VTD_PQA_REG_RW_MASK (VTD_BF_PQA_REG_PQS_MASK \| VTD_BF_PQA_REG_PQA_MASK)
1610	/** @} */
1611
1612
1613	/** @name Page Request Status Register (PRS_REG).
1614	* In accordance with the Intel spec.
1615	* @{ */
1616	/** PPR: Pending Page Request. */
1617	#define VTD_BF_PRS_REG_PPR_SHIFT 0
1618	#define VTD_BF_PRS_REG_PPR_MASK UINT64_C(0x00000001)
1619	/** PRO: Page Request Overflow. */
1620	#define VTD_BF_PRS_REG_PRO_SHIFT 1
1621	#define VTD_BF_PRS_REG_PRO_MASK UINT64_C(0x00000002)
1622	/** R: Reserved (bits 31:2). */
1623	#define VTD_BF_PRS_REG_RSVD_31_2_SHIFT 2
1624	#define VTD_BF_PRS_REG_RSVD_31_2_MASK UINT64_C(0xfffffffc)
1625	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_PRS_REG_, UINT32_C(0), UINT32_MAX,
1626	(PPR, PRO, RSVD_31_2));
1627
1628	/** RW: Read/write mask. */
1629	#define VTD_PRS_REG_RW_MASK (VTD_BF_PRS_REG_PPR_MASK \| VTD_BF_PRS_REG_PRO_MASK)
1630	/** RW1C: Read-only-status, Write-1-to-clear status mask. */
1631	#define VTD_PRS_REG_RW1C_MASK (VTD_BF_PRS_REG_PPR_MASK \| VTD_BF_PRS_REG_PRO_MASK)
1632	/** @} */
1633
1634
1635	/** @name Page Request Event Control Register (PECTL_REG).
1636	* In accordance with the Intel spec.
1637	* @{ */
1638	/** R: Reserved (bits 29:0). */
1639	#define VTD_BF_PECTL_REG_RSVD_29_0_SHIFT 0
1640	#define VTD_BF_PECTL_REG_RSVD_29_0_MASK UINT32_C(0x3fffffff)
1641	/** IP: Interrupt Pending. */
1642	#define VTD_BF_PECTL_REG_IP_SHIFT 30
1643	#define VTD_BF_PECTL_REG_IP_MASK UINT32_C(0x40000000)
1644	/** IM: Interrupt Mask. */
1645	#define VTD_BF_PECTL_REG_IM_SHIFT 31
1646	#define VTD_BF_PECTL_REG_IM_MASK UINT32_C(0x80000000)
1647	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_PECTL_REG_, UINT32_C(0), UINT32_MAX,
1648	(RSVD_29_0, IP, IM));
1649
1650	/** RW: Read/write mask. */
1651	#define VTD_PECTL_REG_RW_MASK VTD_BF_PECTL_REG_IM_MASK
1652	/** @} */
1653
1654
1655	/** @name Page Request Event Data Register (PEDATA_REG).
1656	* In accordance with the Intel spec.
1657	* @{ */
1658	/** IMD: Interrupt Message Data. */
1659	#define VTD_BF_PEDATA_REG_IMD_SHIFT 0
1660	#define VTD_BF_PEDATA_REG_IMD_MASK UINT32_C(0x0000ffff)
1661	/** R: Reserved (bits 31:16). VT-d specs. prior to 2021 had EIMD here. */
1662	#define VTD_BF_PEDATA_REG_RSVD_31_16_SHIFT 16
1663	#define VTD_BF_PEDATA_REG_RSVD_31_16_MASK UINT32_C(0xffff0000)
1664	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_PEDATA_REG_, UINT32_C(0), UINT32_MAX,
1665	(IMD, RSVD_31_16));
1666
1667	/** RW: Read/write mask. */
1668	#define VTD_PEDATA_REG_RW_MASK VTD_BF_PEDATA_REG_IMD_MASK
1669	/** @} */
1670
1671
1672	/** @name Page Request Event Address Register (PEADDR_REG).
1673	* In accordance with the Intel spec.
1674	* @{ */
1675	/** R: Reserved (bits 1:0). */
1676	#define VTD_BF_PEADDR_REG_RSVD_1_0_SHIFT 0
1677	#define VTD_BF_PEADDR_REG_RSVD_1_0_MASK UINT32_C(0x00000003)
1678	/** MA: Message Address. */
1679	#define VTD_BF_PEADDR_REG_MA_SHIFT 2
1680	#define VTD_BF_PEADDR_REG_MA_MASK UINT32_C(0xfffffffc)
1681	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_PEADDR_REG_, UINT32_C(0), UINT32_MAX,
1682	(RSVD_1_0, MA));
1683
1684	/** RW: Read/write mask. */
1685	#define VTD_PEADDR_REG_RW_MASK VTD_BF_PEADDR_REG_MA_MASK
1686	/** @} */
1687
1688
1689
1690	/** @name Page Request Event Upper Address Register (PEUADDR_REG).
1691	* In accordance with the Intel spec.
1692	* @{ */
1693	/** MA: Message Address. */
1694	#define VTD_BF_PEUADDR_REG_MUA_SHIFT 0
1695	#define VTD_BF_PEUADDR_REG_MUA_MASK UINT32_C(0xffffffff)
1696
1697	/** RW: Read/write mask. */
1698	#define VTD_PEUADDR_REG_RW_MASK VTD_BF_PEUADDR_REG_MUA_MASK
1699	/** @} */
1700
1701
1702	/** @name MTRR Capability Register (MTRRCAP_REG).
1703	* In accordance with the Intel spec.
1704	* @{ */
1705	/** VCNT: Variable MTRR Count. */
1706	#define VTD_BF_MTRRCAP_REG_VCNT_SHIFT 0
1707	#define VTD_BF_MTRRCAP_REG_VCNT_MASK UINT64_C(0x00000000000000ff)
1708	/** FIX: Fixed range MTRRs Supported. */
1709	#define VTD_BF_MTRRCAP_REG_FIX_SHIFT 8
1710	#define VTD_BF_MTRRCAP_REG_FIX_MASK UINT64_C(0x0000000000000100)
1711	/** R: Reserved (bit 9). */
1712	#define VTD_BF_MTRRCAP_REG_RSVD_9_SHIFT 9
1713	#define VTD_BF_MTRRCAP_REG_RSVD_9_MASK UINT64_C(0x0000000000000200)
1714	/** WC: Write Combining. */
1715	#define VTD_BF_MTRRCAP_REG_WC_SHIFT 10
1716	#define VTD_BF_MTRRCAP_REG_WC_MASK UINT64_C(0x0000000000000400)
1717	/** R: Reserved (bits 63:11). */
1718	#define VTD_BF_MTRRCAP_REG_RSVD_63_11_SHIFT 11
1719	#define VTD_BF_MTRRCAP_REG_RSVD_63_11_MASK UINT64_C(0xfffffffffffff800)
1720	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_MTRRCAP_REG_, UINT64_C(0), UINT64_MAX,
1721	(VCNT, FIX, RSVD_9, WC, RSVD_63_11));
1722
1723	/** RW: Read/write mask. */
1724	#define VTD_MTRRCAP_REG_RW_MASK UINT64_C(0)
1725	/** @} */
1726
1727
1728	/** @name MTRR Default Type Register (MTRRDEF_REG).
1729	* In accordance with the Intel spec.
1730	* @{ */
1731	/** TYPE: Default Memory Type. */
1732	#define VTD_BF_MTRRDEF_REG_TYPE_SHIFT 0
1733	#define VTD_BF_MTRRDEF_REG_TYPE_MASK UINT64_C(0x00000000000000ff)
1734	/** R: Reserved (bits 9:8). */
1735	#define VTD_BF_MTRRDEF_REG_RSVD_9_8_SHIFT 8
1736	#define VTD_BF_MTRRDEF_REG_RSVD_9_8_MASK UINT64_C(0x0000000000000300)
1737	/** FE: Fixed Range MTRR Enable. */
1738	#define VTD_BF_MTRRDEF_REG_FE_SHIFT 10
1739	#define VTD_BF_MTRRDEF_REG_FE_MASK UINT64_C(0x0000000000000400)
1740	/** E: MTRR Enable. */
1741	#define VTD_BF_MTRRDEF_REG_E_SHIFT 11
1742	#define VTD_BF_MTRRDEF_REG_E_MASK UINT64_C(0x0000000000000800)
1743	/** R: Reserved (bits 63:12). */
1744	#define VTD_BF_MTRRDEF_REG_RSVD_63_12_SHIFT 12
1745	#define VTD_BF_MTRRDEF_REG_RSVD_63_12_MASK UINT64_C(0xfffffffffffff000)
1746	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_MTRRDEF_REG_, UINT64_C(0), UINT64_MAX,
1747	(TYPE, RSVD_9_8, FE, E, RSVD_63_12));
1748
1749	/** RW: Read/write mask. */
1750	#define VTD_MTRRDEF_REG_RW_MASK ( VTD_BF_MTRRDEF_REG_TYPE_MASK \| VTD_BF_MTRRDEF_REG_FE_MASK \
1751	\| VTD_BF_MTRRDEF_REG_E_MASK)
1752	/** @} */
1753
1754
1755	/** @name Virtual Command Capability Register (VCCAP_REG).
1756	* In accordance with the Intel spec.
1757	* @{ */
1758	/** PAS: PASID Support. */
1759	#define VTD_BF_VCCAP_REG_PAS_SHIFT 0
1760	#define VTD_BF_VCCAP_REG_PAS_MASK UINT64_C(0x0000000000000001)
1761	/** R: Reserved (bits 63:1). */
1762	#define VTD_BF_VCCAP_REG_RSVD_63_1_SHIFT 1
1763	#define VTD_BF_VCCAP_REG_RSVD_63_1_MASK UINT64_C(0xfffffffffffffffe)
1764	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_VCCAP_REG_, UINT64_C(0), UINT64_MAX,
1765	(PAS, RSVD_63_1));
1766
1767	/** RW: Read/write mask. */
1768	#define VTD_VCCAP_REG_RW_MASK UINT64_C(0)
1769	/** @} */
1770
1771
1772	/** @name Virtual Command Extended Operand Register (VCMD_EO_REG).
1773	* In accordance with the Intel spec.
1774	* @{ */
1775	/** OB: Operand B. */
1776	#define VTD_BF_VCMD_EO_REG_OB_SHIFT 0
1777	#define VTD_BF_VCMD_EO_REG_OB_MASK UINT32_C(0xffffffffffffffff)
1778
1779	/** RW: Read/write mask. */
1780	#define VTD_VCMD_EO_REG_RW_MASK VTD_BF_VCMD_EO_REG_OB_MASK
1781	/** @} */
1782
1783
1784	/** @name Virtual Command Register (VCMD_REG).
1785	* In accordance with the Intel spec.
1786	* @{ */
1787	/** CMD: Command. */
1788	#define VTD_BF_VCMD_REG_CMD_SHIFT 0
1789	#define VTD_BF_VCMD_REG_CMD_MASK UINT64_C(0x00000000000000ff)
1790	/** OP: Operand. */
1791	#define VTD_BF_VCMD_REG_OP_SHIFT 8
1792	#define VTD_BF_VCMD_REG_OP_MASK UINT64_C(0xffffffffffffff00)
1793	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_VCMD_REG_, UINT64_C(0), UINT64_MAX,
1794	(CMD, OP));
1795
1796	/** RW: Read/write mask. */
1797	#define VTD_VCMD_REG_RW_MASK (VTD_BF_VCMD_REG_CMD_MASK \| VTD_BF_VCMD_REG_OP_MASK)
1798	/** @} */
1799
1800
1801	/** @name Virtual Command Response Register (VCRSP_REG).
1802	* In accordance with the Intel spec.
1803	* @{ */
1804	/** IP: In Progress. */
1805	#define VTD_BF_VCRSP_REG_IP_SHIFT 0
1806	#define VTD_BF_VCRSP_REG_IP_MASK UINT64_C(0x0000000000000001)
1807	/** SC: Status Code. */
1808	#define VTD_BF_VCRSP_REG_SC_SHIFT 1
1809	#define VTD_BF_VCRSP_REG_SC_MASK UINT64_C(0x0000000000000006)
1810	/** R: Reserved (bits 7:3). */
1811	#define VTD_BF_VCRSP_REG_RSVD_7_3_SHIFT 3
1812	#define VTD_BF_VCRSP_REG_RSVD_7_3_MASK UINT64_C(0x00000000000000f8)
1813	/** RSLT: Result. */
1814	#define VTD_BF_VCRSP_REG_RSLT_SHIFT 8
1815	#define VTD_BF_VCRSP_REG_RSLT_MASK UINT64_C(0xffffffffffffff00)
1816	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_VCRSP_REG_, UINT64_C(0), UINT64_MAX,
1817	(IP, SC, RSVD_7_3, RSLT));
1818
1819	/** RW: Read/write mask. */
1820	#define VTD_VCRSP_REG_RW_MASK UINT64_C(0)
1821	/** @} */
1822
1823
1824	/** @name Generic Invalidation Descriptor.
1825	* In accordance with the Intel spec.
1826	* Non-reserved fields here are common to all invalidation descriptors.
1827	* @{ */
1828	/** Type (Lo). */
1829	#define VTD_BF_0_GENERIC_INV_DSC_TYPE_LO_SHIFT 0
1830	#define VTD_BF_0_GENERIC_INV_DSC_TYPE_LO_MASK UINT64_C(0x000000000000000f)
1831	/** R: Reserved (bits 8:4). */
1832	#define VTD_BF_0_GENERIC_INV_DSC_RSVD_8_4_SHIFT 4
1833	#define VTD_BF_0_GENERIC_INV_DSC_RSVD_8_4_MASK UINT64_C(0x00000000000001f0)
1834	/** Type (Hi). */
1835	#define VTD_BF_0_GENERIC_INV_DSC_TYPE_HI_SHIFT 9
1836	#define VTD_BF_0_GENERIC_INV_DSC_TYPE_HI_MASK UINT64_C(0x0000000000000e00)
1837	/** R: Reserved (bits 63:12). */
1838	#define VTD_BF_0_GENERIC_INV_DSC_RSVD_63_12_SHIFT 12
1839	#define VTD_BF_0_GENERIC_INV_DSC_RSVD_63_12_MASK UINT64_C(0xfffffffffffff000)
1840	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_GENERIC_INV_DSC_, UINT64_C(0), UINT64_MAX,
1841	(TYPE_LO, RSVD_8_4, TYPE_HI, RSVD_63_12));
1842
1843	/** GENERIC_INV_DSC: Type. */
1844	#define VTD_GENERIC_INV_DSC_GET_TYPE(a) ((((a) & VTD_BF_0_GENERIC_INV_DSC_TYPE_HI_MASK) >> 5) \
1845	\| ((a) & VTD_BF_0_GENERIC_INV_DSC_TYPE_LO_MASK))
1846	/** @} */
1847
1848
1849	/** @name Context-Cache Invalidation Descriptor (cc_inv_dsc).
1850	* In accordance with the Intel spec.
1851	* @{ */
1852	/** Type (Lo). */
1853	#define VTD_BF_0_CC_INV_DSC_TYPE_LO_SHIFT 0
1854	#define VTD_BF_0_CC_INV_DSC_TYPE_LO_MASK UINT64_C(0x000000000000000f)
1855	/** G: Granularity. */
1856	#define VTD_BF_0_CC_INV_DSC_G_SHIFT 4
1857	#define VTD_BF_0_CC_INV_DSC_G_MASK UINT64_C(0x0000000000000030)
1858	/** R: Reserved (bits 8:6). */
1859	#define VTD_BF_0_CC_INV_DSC_RSVD_8_6_SHIFT 6
1860	#define VTD_BF_0_CC_INV_DSC_RSVD_8_6_MASK UINT64_C(0x00000000000001c0)
1861	/** Type (Hi). */
1862	#define VTD_BF_0_CC_INV_DSC_TYPE_HI_SHIFT 9
1863	#define VTD_BF_0_CC_INV_DSC_TYPE_HI_MASK UINT64_C(0x0000000000000e00)
1864	/** R: Reserved (bits 15:12). */
1865	#define VTD_BF_0_CC_INV_DSC_RSVD_15_12_SHIFT 12
1866	#define VTD_BF_0_CC_INV_DSC_RSVD_15_12_MASK UINT64_C(0x000000000000f000)
1867	/** DID: Domain Id. */
1868	#define VTD_BF_0_CC_INV_DSC_DID_SHIFT 16
1869	#define VTD_BF_0_CC_INV_DSC_DID_MASK UINT64_C(0x00000000ffff0000)
1870	/** SID: Source Id. */
1871	#define VTD_BF_0_CC_INV_DSC_SID_SHIFT 32
1872	#define VTD_BF_0_CC_INV_DSC_SID_MASK UINT64_C(0x0000ffff00000000)
1873	/** FM: Function Mask. */
1874	#define VTD_BF_0_CC_INV_DSC_FM_SHIFT 48
1875	#define VTD_BF_0_CC_INV_DSC_FM_MASK UINT64_C(0x0003000000000000)
1876	/** R: Reserved (bits 63:50). */
1877	#define VTD_BF_0_CC_INV_DSC_RSVD_63_50_SHIFT 50
1878	#define VTD_BF_0_CC_INV_DSC_RSVD_63_50_MASK UINT64_C(0xfffc000000000000)
1879	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_CC_INV_DSC_, UINT64_C(0), UINT64_MAX,
1880	(TYPE_LO, G, RSVD_8_6, TYPE_HI, RSVD_15_12, DID, SID, FM, RSVD_63_50));
1881	/** @} */
1882
1883
1884	/** @name PASID-Cache Invalidation Descriptor (pc_inv_dsc).
1885	* In accordance with the Intel spec.
1886	* @{ */
1887	/** Type (Lo). */
1888	#define VTD_BF_0_PC_INV_DSC_TYPE_LO_SHIFT 0
1889	#define VTD_BF_0_PC_INV_DSC_TYPE_LO_MASK UINT64_C(0x000000000000000f)
1890	/** G: Granularity. */
1891	#define VTD_BF_0_PC_INV_DSC_G_SHIFT 4
1892	#define VTD_BF_0_PC_INV_DSC_G_MASK UINT64_C(0x0000000000000030)
1893	/** R: Reserved (bits 8:6). */
1894	#define VTD_BF_0_PC_INV_DSC_RSVD_8_6_SHIFT 6
1895	#define VTD_BF_0_PC_INV_DSC_RSVD_8_6_MASK UINT64_C(0x00000000000001c0)
1896	/** Type (Hi). */
1897	#define VTD_BF_0_PC_INV_DSC_TYPE_HI_SHIFT 9
1898	#define VTD_BF_0_PC_INV_DSC_TYPE_HI_MASK UINT64_C(0x0000000000000e00)
1899	/** R: Reserved (bits 15:12). */
1900	#define VTD_BF_0_PC_INV_DSC_RSVD_15_12_SHIFT 12
1901	#define VTD_BF_0_PC_INV_DSC_RSVD_15_12_MASK UINT64_C(0x000000000000f000)
1902	/** DID: Domain Id. */
1903	#define VTD_BF_0_PC_INV_DSC_DID_SHIFT 16
1904	#define VTD_BF_0_PC_INV_DSC_DID_MASK UINT64_C(0x00000000ffff0000)
1905	/** PASID: Process Address-Space Id. */
1906	#define VTD_BF_0_PC_INV_DSC_PASID_SHIFT 32
1907	#define VTD_BF_0_PC_INV_DSC_PASID_MASK UINT64_C(0x000fffff00000000)
1908	/** R: Reserved (bits 63:52). */
1909	#define VTD_BF_0_PC_INV_DSC_RSVD_63_52_SHIFT 52
1910	#define VTD_BF_0_PC_INV_DSC_RSVD_63_52_MASK UINT64_C(0xfff0000000000000)
1911
1912	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_PC_INV_DSC_, UINT64_C(0), UINT64_MAX,
1913	(TYPE_LO, G, RSVD_8_6, TYPE_HI, RSVD_15_12, DID, PASID, RSVD_63_52));
1914	/** @} */
1915
1916
1917	/** @name IOTLB Invalidate Descriptor (iotlb_inv_dsc).
1918	* In accordance with the Intel spec.
1919	* @{ */
1920	/** Type (Lo). */
1921	#define VTD_BF_0_IOTLB_INV_DSC_TYPE_LO_SHIFT 0
1922	#define VTD_BF_0_IOTLB_INV_DSC_TYPE_LO_MASK UINT64_C(0x000000000000000f)
1923	/** G: Granularity. */
1924	#define VTD_BF_0_IOTLB_INV_DSC_G_SHIFT 4
1925	#define VTD_BF_0_IOTLB_INV_DSC_G_MASK UINT64_C(0x0000000000000030)
1926	/** DW: Drain Writes. */
1927	#define VTD_BF_0_IOTLB_INV_DSC_DW_SHIFT 6
1928	#define VTD_BF_0_IOTLB_INV_DSC_DW_MASK UINT64_C(0x0000000000000040)
1929	/** DR: Drain Reads. */
1930	#define VTD_BF_0_IOTLB_INV_DSC_DR_SHIFT 7
1931	#define VTD_BF_0_IOTLB_INV_DSC_DR_MASK UINT64_C(0x0000000000000080)
1932	/** R: Reserved (bit 8). */
1933	#define VTD_BF_0_IOTLB_INV_DSC_RSVD_8_SHIFT 8
1934	#define VTD_BF_0_IOTLB_INV_DSC_RSVD_8_MASK UINT64_C(0x0000000000000100)
1935	/** Type (Hi). */
1936	#define VTD_BF_0_IOTLB_INV_DSC_TYPE_HI_SHIFT 9
1937	#define VTD_BF_0_IOTLB_INV_DSC_TYPE_HI_MASK UINT64_C(0x0000000000000e00)
1938	/** R: Reserved (bits 15:12). */
1939	#define VTD_BF_0_IOTLB_INV_DSC_RSVD_15_12_SHIFT 12
1940	#define VTD_BF_0_IOTLB_INV_DSC_RSVD_15_12_MASK UINT64_C(0x000000000000f000)
1941	/** DID: Domain Id. */
1942	#define VTD_BF_0_IOTLB_INV_DSC_DID_SHIFT 16
1943	#define VTD_BF_0_IOTLB_INV_DSC_DID_MASK UINT64_C(0x00000000ffff0000)
1944	/** R: Reserved (bits 63:32). */
1945	#define VTD_BF_0_IOTLB_INV_DSC_RSVD_63_32_SHIFT 32
1946	#define VTD_BF_0_IOTLB_INV_DSC_RSVD_63_32_MASK UINT64_C(0xffffffff00000000)
1947	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_IOTLB_INV_DSC_, UINT64_C(0), UINT64_MAX,
1948	(TYPE_LO, G, DW, DR, RSVD_8, TYPE_HI, RSVD_15_12, DID, RSVD_63_32));
1949
1950	/** AM: Address Mask. */
1951	#define VTD_BF_1_IOTLB_INV_DSC_AM_SHIFT 0
1952	#define VTD_BF_1_IOTLB_INV_DSC_AM_MASK UINT64_C(0x000000000000003f)
1953	/** IH: Invalidation Hint. */
1954	#define VTD_BF_1_IOTLB_INV_DSC_IH_SHIFT 6
1955	#define VTD_BF_1_IOTLB_INV_DSC_IH_MASK UINT64_C(0x0000000000000040)
1956	/** R: Reserved (bits 11:7). */
1957	#define VTD_BF_1_IOTLB_INV_DSC_RSVD_11_7_SHIFT 7
1958	#define VTD_BF_1_IOTLB_INV_DSC_RSVD_11_7_MASK UINT64_C(0x0000000000000f80)
1959	/** ADDR: Address. */
1960	#define VTD_BF_1_IOTLB_INV_DSC_ADDR_SHIFT 12
1961	#define VTD_BF_1_IOTLB_INV_DSC_ADDR_MASK UINT64_C(0xfffffffffffff000)
1962	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_IOTLB_INV_DSC_, UINT64_C(0), UINT64_MAX,
1963	(AM, IH, RSVD_11_7, ADDR));
1964	/** @} */
1965
1966
1967	/** @name PASID-based IOTLB Invalidate Descriptor (p_iotlb_inv_dsc).
1968	* In accordance with the Intel spec.
1969	* @{ */
1970	/** Type (Lo). */
1971	#define VTD_BF_0_P_IOTLB_INV_DSC_TYPE_LO_SHIFT 0
1972	#define VTD_BF_0_P_IOTLB_INV_DSC_TYPE_LO_MASK UINT64_C(0x000000000000000f)
1973	/** G: Granularity. */
1974	#define VTD_BF_0_P_IOTLB_INV_DSC_G_SHIFT 4
1975	#define VTD_BF_0_P_IOTLB_INV_DSC_G_MASK UINT64_C(0x0000000000000030)
1976	/** R: Reserved (bits 8:6). */
1977	#define VTD_BF_0_P_IOTLB_INV_DSC_RSVD_8_6_SHIFT 6
1978	#define VTD_BF_0_P_IOTLB_INV_DSC_RSVD_8_6_MASK UINT64_C(0x00000000000001c0)
1979	/** Type (Hi). */
1980	#define VTD_BF_0_P_IOTLB_INV_DSC_TYPE_HI_SHIFT 9
1981	#define VTD_BF_0_P_IOTLB_INV_DSC_TYPE_HI_MASK UINT64_C(0x0000000000000e00)
1982	/** R: Reserved (bits 15:12). */
1983	#define VTD_BF_0_P_IOTLB_INV_DSC_RSVD_15_12_SHIFT 12
1984	#define VTD_BF_0_P_IOTLB_INV_DSC_RSVD_15_12_MASK UINT64_C(0x000000000000f000)
1985	/** DID: Domain Id. */
1986	#define VTD_BF_0_P_IOTLB_INV_DSC_DID_SHIFT 16
1987	#define VTD_BF_0_P_IOTLB_INV_DSC_DID_MASK UINT64_C(0x00000000ffff0000)
1988	/** PASID: Process Address-Space Id. */
1989	#define VTD_BF_0_P_IOTLB_INV_DSC_PASID_SHIFT 32
1990	#define VTD_BF_0_P_IOTLB_INV_DSC_PASID_MASK UINT64_C(0x000fffff00000000)
1991	/** R: Reserved (bits 63:52). */
1992	#define VTD_BF_0_P_IOTLB_INV_DSC_RSVD_63_52_SHIFT 52
1993	#define VTD_BF_0_P_IOTLB_INV_DSC_RSVD_63_52_MASK UINT64_C(0xfff0000000000000)
1994	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_P_IOTLB_INV_DSC_, UINT64_C(0), UINT64_MAX,
1995	(TYPE_LO, G, RSVD_8_6, TYPE_HI, RSVD_15_12, DID, PASID, RSVD_63_52));
1996
1997
1998	/** AM: Address Mask. */
1999	#define VTD_BF_1_P_IOTLB_INV_DSC_AM_SHIFT 0
2000	#define VTD_BF_1_P_IOTLB_INV_DSC_AM_MASK UINT64_C(0x000000000000003f)
2001	/** IH: Invalidation Hint. */
2002	#define VTD_BF_1_P_IOTLB_INV_DSC_IH_SHIFT 6
2003	#define VTD_BF_1_P_IOTLB_INV_DSC_IH_MASK UINT64_C(0x0000000000000040)
2004	/** R: Reserved (bits 11:7). */
2005	#define VTD_BF_1_P_IOTLB_INV_DSC_RSVD_11_7_SHIFT 7
2006	#define VTD_BF_1_P_IOTLB_INV_DSC_RSVD_11_7_MASK UINT64_C(0x0000000000000f80)
2007	/** ADDR: Address. */
2008	#define VTD_BF_1_P_IOTLB_INV_DSC_ADDR_SHIFT 12
2009	#define VTD_BF_1_P_IOTLB_INV_DSC_ADDR_MASK UINT64_C(0xfffffffffffff000)
2010	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_P_IOTLB_INV_DSC_, UINT64_C(0), UINT64_MAX,
2011	(AM, IH, RSVD_11_7, ADDR));
2012	/** @} */
2013
2014
2015	/** @name Device-TLB Invalidate Descriptor (dev_tlb_inv_dsc).
2016	* In accordance with the Intel spec.
2017	* @{ */
2018	/** Type (Lo). */
2019	#define VTD_BF_0_DEV_TLB_INV_DSC_TYPE_LO_SHIFT 0
2020	#define VTD_BF_0_DEV_TLB_INV_DSC_TYPE_LO_MASK UINT64_C(0x000000000000000f)
2021	/** R: Reserved (bits 8:4). */
2022	#define VTD_BF_0_DEV_TLB_INV_DSC_RSVD_8_4_SHIFT 4
2023	#define VTD_BF_0_DEV_TLB_INV_DSC_RSVD_8_4_MASK UINT64_C(0x00000000000001f0)
2024	/** Type (Hi). */
2025	#define VTD_BF_0_DEV_TLB_INV_DSC_TYPE_HI_SHIFT 9
2026	#define VTD_BF_0_DEV_TLB_INV_DSC_TYPE_HI_MASK UINT64_C(0x0000000000000e00)
2027	/** PFSID: Physical-Function Source Id (Lo). */
2028	#define VTD_BF_0_DEV_TLB_INV_DSC_PFSID_LO_SHIFT 12
2029	#define VTD_BF_0_DEV_TLB_INV_DSC_PFSID_LO_MASK UINT64_C(0x000000000000f000)
2030	/** MIP: Max Invalidations Pending. */
2031	#define VTD_BF_0_DEV_TLB_INV_DSC_MIP_SHIFT 16
2032	#define VTD_BF_0_DEV_TLB_INV_DSC_MIP_MASK UINT64_C(0x00000000001f0000)
2033	/** R: Reserved (bits 31:21). */
2034	#define VTD_BF_0_DEV_TLB_INV_DSC_RSVD_31_21_SHIFT 21
2035	#define VTD_BF_0_DEV_TLB_INV_DSC_RSVD_31_21_MASK UINT64_C(0x00000000ffe00000)
2036	/** SID: Source Id. */
2037	#define VTD_BF_0_DEV_TLB_INV_DSC_SID_SHIFT 32
2038	#define VTD_BF_0_DEV_TLB_INV_DSC_SID_MASK UINT64_C(0x0000ffff00000000)
2039	/** R: Reserved (bits 51:48). */
2040	#define VTD_BF_0_DEV_TLB_INV_DSC_RSVD_51_48_SHIFT 48
2041	#define VTD_BF_0_DEV_TLB_INV_DSC_RSVD_51_48_MASK UINT64_C(0x000f000000000000)
2042	/** PFSID: Physical-Function Source Id (Hi). */
2043	#define VTD_BF_0_DEV_TLB_INV_DSC_PFSID_HI_SHIFT 52
2044	#define VTD_BF_0_DEV_TLB_INV_DSC_PFSID_HI_MASK UINT64_C(0xfff0000000000000)
2045	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_DEV_TLB_INV_DSC_, UINT64_C(0), UINT64_MAX,
2046	(TYPE_LO, RSVD_8_4, TYPE_HI, PFSID_LO, MIP, RSVD_31_21, SID, RSVD_51_48, PFSID_HI));
2047
2048	/** S: Size. */
2049	#define VTD_BF_1_DEV_TLB_INV_DSC_S_SHIFT 0
2050	#define VTD_BF_1_DEV_TLB_INV_DSC_S_MASK UINT64_C(0x0000000000000001)
2051	/** R: Reserved (bits 11:1). */
2052	#define VTD_BF_1_DEV_TLB_INV_DSC_RSVD_11_1_SHIFT 1
2053	#define VTD_BF_1_DEV_TLB_INV_DSC_RSVD_11_1_MASK UINT64_C(0x0000000000000ffe)
2054	/** ADDR: Address. */
2055	#define VTD_BF_1_DEV_TLB_INV_DSC_ADDR_SHIFT 12
2056	#define VTD_BF_1_DEV_TLB_INV_DSC_ADDR_MASK UINT64_C(0xfffffffffffff000)
2057	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_DEV_TLB_INV_DSC_, UINT64_C(0), UINT64_MAX,
2058	(S, RSVD_11_1, ADDR));
2059	/** @} */
2060
2061
2062	/** @name PASID-based-device-TLB Invalidate Descriptor (p_dev_tlb_inv_dsc).
2063	* In accordance with the Intel spec.
2064	* @{ */
2065	/** Type (Lo). */
2066	#define VTD_BF_0_P_DEV_TLB_INV_DSC_TYPE_LO_SHIFT 0
2067	#define VTD_BF_0_P_DEV_TLB_INV_DSC_TYPE_LO_MASK UINT64_C(0x000000000000000f)
2068	/** MIP: Max Invalidations Pending. */
2069	#define VTD_BF_0_P_DEV_TLB_INV_DSC_MIP_SHIFT 4
2070	#define VTD_BF_0_P_DEV_TLB_INV_DSC_MIP_MASK UINT64_C(0x00000000000001f0)
2071	/** Type (Hi). */
2072	#define VTD_BF_0_P_DEV_TLB_INV_DSC_TYPE_HI_SHIFT 9
2073	#define VTD_BF_0_P_DEV_TLB_INV_DSC_TYPE_HI_MASK UINT64_C(0x0000000000000e00)
2074	/** PFSID: Physical-Function Source Id (Lo). */
2075	#define VTD_BF_0_P_DEV_TLB_INV_DSC_PFSID_LO_SHIFT 12
2076	#define VTD_BF_0_P_DEV_TLB_INV_DSC_PFSID_LO_MASK UINT64_C(0x000000000000f000)
2077	/** SID: Source Id. */
2078	#define VTD_BF_0_P_DEV_TLB_INV_DSC_SID_SHIFT 16
2079	#define VTD_BF_0_P_DEV_TLB_INV_DSC_SID_MASK UINT64_C(0x00000000ffff0000)
2080	/** PASID: Process Address-Space Id. */
2081	#define VTD_BF_0_P_DEV_TLB_INV_DSC_PASID_SHIFT 32
2082	#define VTD_BF_0_P_DEV_TLB_INV_DSC_PASID_MASK UINT64_C(0x000fffff00000000)
2083	/** PFSID: Physical-Function Source Id (Hi). */
2084	#define VTD_BF_0_P_DEV_TLB_INV_DSC_PFSID_HI_SHIFT 52
2085	#define VTD_BF_0_P_DEV_TLB_INV_DSC_PFSID_HI_MASK UINT64_C(0xfff0000000000000)
2086	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_P_DEV_TLB_INV_DSC_, UINT64_C(0), UINT64_MAX,
2087	(TYPE_LO, MIP, TYPE_HI, PFSID_LO, SID, PASID, PFSID_HI));
2088
2089	/** G: Granularity. */
2090	#define VTD_BF_1_P_DEV_TLB_INV_DSC_G_SHIFT 0
2091	#define VTD_BF_1_P_DEV_TLB_INV_DSC_G_MASK UINT64_C(0x0000000000000001)
2092	/** R: Reserved (bits 10:1). */
2093	#define VTD_BF_1_P_DEV_TLB_INV_DSC_RSVD_10_1_SHIFT 1
2094	#define VTD_BF_1_P_DEV_TLB_INV_DSC_RSVD_10_1_MASK UINT64_C(0x00000000000007fe)
2095	/** S: Size. */
2096	#define VTD_BF_1_P_DEV_TLB_INV_DSC_S_SHIFT 11
2097	#define VTD_BF_1_P_DEV_TLB_INV_DSC_S_MASK UINT64_C(0x0000000000000800)
2098	/** ADDR: Address. */
2099	#define VTD_BF_1_P_DEV_TLB_INV_DSC_ADDR_SHIFT 12
2100	#define VTD_BF_1_P_DEV_TLB_INV_DSC_ADDR_MASK UINT64_C(0xfffffffffffff000)
2101	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_P_DEV_TLB_INV_DSC_, UINT64_C(0), UINT64_MAX,
2102	(G, RSVD_10_1, S, ADDR));
2103	/** @} */
2104
2105
2106	/** @name Interrupt Entry Cache Invalidate Descriptor (iec_inv_dsc).
2107	* In accordance with the Intel spec.
2108	* @{ */
2109	/** Type (Lo). */
2110	#define VTD_BF_0_IEC_INV_DSC_TYPE_LO_SHIFT 0
2111	#define VTD_BF_0_IEC_INV_DSC_TYPE_LO_MASK UINT64_C(0x000000000000000f)
2112	/** G: Granularity. */
2113	#define VTD_BF_0_IEC_INV_DSC_G_SHIFT 4
2114	#define VTD_BF_0_IEC_INV_DSC_G_MASK UINT64_C(0x0000000000000010)
2115	/** R: Reserved (bits 8:5). */
2116	#define VTD_BF_0_IEC_INV_DSC_RSVD_8_5_SHIFT 5
2117	#define VTD_BF_0_IEC_INV_DSC_RSVD_8_5_MASK UINT64_C(0x00000000000001e0)
2118	/** Type (Hi). */
2119	#define VTD_BF_0_IEC_INV_DSC_TYPE_HI_SHIFT 9
2120	#define VTD_BF_0_IEC_INV_DSC_TYPE_HI_MASK UINT64_C(0x0000000000000e00)
2121	/** R: Reserved (bits 26:12). */
2122	#define VTD_BF_0_IEC_INV_DSC_RSVD_26_12_SHIFT 12
2123	#define VTD_BF_0_IEC_INV_DSC_RSVD_26_12_MASK UINT64_C(0x0000000007fff000)
2124	/** IM: Index Mask. */
2125	#define VTD_BF_0_IEC_INV_DSC_IM_SHIFT 27
2126	#define VTD_BF_0_IEC_INV_DSC_IM_MASK UINT64_C(0x00000000f8000000)
2127	/** IIDX: Interrupt Index. */
2128	#define VTD_BF_0_IEC_INV_DSC_IIDX_SHIFT 32
2129	#define VTD_BF_0_IEC_INV_DSC_IIDX_MASK UINT64_C(0x0000ffff00000000)
2130	/** R: Reserved (bits 63:48). */
2131	#define VTD_BF_0_IEC_INV_DSC_RSVD_63_48_SHIFT 48
2132	#define VTD_BF_0_IEC_INV_DSC_RSVD_63_48_MASK UINT64_C(0xffff000000000000)
2133	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_IEC_INV_DSC_, UINT64_C(0), UINT64_MAX,
2134	(TYPE_LO, G, RSVD_8_5, TYPE_HI, RSVD_26_12, IM, IIDX, RSVD_63_48));
2135	/** @} */
2136
2137
2138	/** @name Invalidation Wait Descriptor (inv_wait_dsc).
2139	* In accordance with the Intel spec.
2140	* @{ */
2141	/** Type (Lo). */
2142	#define VTD_BF_0_INV_WAIT_DSC_TYPE_LO_SHIFT 0
2143	#define VTD_BF_0_INV_WAIT_DSC_TYPE_LO_MASK UINT64_C(0x000000000000000f)
2144	/** IF: Interrupt Flag. */
2145	#define VTD_BF_0_INV_WAIT_DSC_IF_SHIFT 4
2146	#define VTD_BF_0_INV_WAIT_DSC_IF_MASK UINT64_C(0x0000000000000010)
2147	/** SW: Status Write. */
2148	#define VTD_BF_0_INV_WAIT_DSC_SW_SHIFT 5
2149	#define VTD_BF_0_INV_WAIT_DSC_SW_MASK UINT64_C(0x0000000000000020)
2150	/** FN: Fence Flag. */
2151	#define VTD_BF_0_INV_WAIT_DSC_FN_SHIFT 6
2152	#define VTD_BF_0_INV_WAIT_DSC_FN_MASK UINT64_C(0x0000000000000040)
2153	/** PD: Page-Request Drain. */
2154	#define VTD_BF_0_INV_WAIT_DSC_PD_SHIFT 7
2155	#define VTD_BF_0_INV_WAIT_DSC_PD_MASK UINT64_C(0x0000000000000080)
2156	/** R: Reserved (bit 8). */
2157	#define VTD_BF_0_INV_WAIT_DSC_RSVD_8_SHIFT 8
2158	#define VTD_BF_0_INV_WAIT_DSC_RSVD_8_MASK UINT64_C(0x0000000000000100)
2159	/** Type (Hi). */
2160	#define VTD_BF_0_INV_WAIT_DSC_TYPE_HI_SHIFT 9
2161	#define VTD_BF_0_INV_WAIT_DSC_TYPE_HI_MASK UINT64_C(0x0000000000000e00)
2162	/** R: Reserved (bits 31:12). */
2163	#define VTD_BF_0_INV_WAIT_DSC_RSVD_31_12_SHIFT 12
2164	#define VTD_BF_0_INV_WAIT_DSC_RSVD_31_12_MASK UINT64_C(0x00000000fffff000)
2165	/** STDATA: Status Data. */
2166	#define VTD_BF_0_INV_WAIT_DSC_STDATA_SHIFT 32
2167	#define VTD_BF_0_INV_WAIT_DSC_STDATA_MASK UINT64_C(0xffffffff00000000)
2168	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_INV_WAIT_DSC_, UINT64_C(0), UINT64_MAX,
2169	(TYPE_LO, IF, SW, FN, PD, RSVD_8, TYPE_HI, RSVD_31_12, STDATA));
2170
2171	/** R: Reserved (bits 1:0). */
2172	#define VTD_BF_1_INV_WAIT_DSC_RSVD_1_0_SHIFT 0
2173	#define VTD_BF_1_INV_WAIT_DSC_RSVD_1_0_MASK UINT64_C(0x0000000000000003)
2174	/** STADDR: Status Address. */
2175	#define VTD_BF_1_INV_WAIT_DSC_STADDR_SHIFT 2
2176	#define VTD_BF_1_INV_WAIT_DSC_STADDR_MASK UINT64_C(0xfffffffffffffffc)
2177	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_INV_WAIT_DSC_, UINT64_C(0), UINT64_MAX,
2178	(RSVD_1_0, STADDR));
2179
2180	/* INV_WAIT_DSC: Qword 0 valid mask. */
2181	#define VTD_INV_WAIT_DSC_0_VALID_MASK ( VTD_BF_0_INV_WAIT_DSC_TYPE_LO_MASK \
2182	\| VTD_BF_0_INV_WAIT_DSC_IF_MASK \
2183	\| VTD_BF_0_INV_WAIT_DSC_SW_MASK \
2184	\| VTD_BF_0_INV_WAIT_DSC_FN_MASK \
2185	\| VTD_BF_0_INV_WAIT_DSC_PD_MASK \
2186	\| VTD_BF_0_INV_WAIT_DSC_TYPE_HI_MASK \
2187	\| VTD_BF_0_INV_WAIT_DSC_STDATA_MASK)
2188	/* INV_WAIT_DSC: Qword 1 valid mask. */
2189	#define VTD_INV_WAIT_DSC_1_VALID_MASK VTD_BF_1_INV_WAIT_DSC_STADDR_MASK
2190	/** @} */
2191
2192
2193	/** @name Invalidation descriptor types.
2194	* In accordance with the Intel spec.
2195	* @{ */
2196	#define VTD_CC_INV_DSC_TYPE 1
2197	#define VTD_IOTLB_INV_DSC_TYPE 2
2198	#define VTD_DEV_TLB_INV_DSC_TYPE 3
2199	#define VTD_IEC_INV_DSC_TYPE 4
2200	#define VTD_INV_WAIT_DSC_TYPE 5
2201	#define VTD_P_IOTLB_INV_DSC_TYPE 6
2202	#define VTD_PC_INV_DSC_TYPE 7
2203	#define VTD_P_DEV_TLB_INV_DSC_TYPE 8
2204	/** @} */
2205
2206
2207	/** Gets the interrupt format from an MSI address. */
2208	#define VTD_MSI_ADDR_GET_INTR_FORMAT(a_uMsiAddr) ((a_uMsiAddr) & RT_BIT_64(4))
2209	/** Interrupt format: Compatibility. */
2210	#define VTD_INTR_FORMAT_COMPAT 0
2211	/** Interrupt format: Remappable. */
2212	#define VTD_INTR_FORMAT_REMAPPABLE 1
2213
2214
2215	/** @name Remappable Format Interrupt Request.
2216	* In accordance with the Intel spec.
2217	* @{ */
2218	/** IGN: Ignored (bits 1:0). */
2219	#define VTD_BF_REMAPPABLE_IR_ADDR_IGN_1_0_SHIFT 0
2220	#define VTD_BF_REMAPPABLE_IR_ADDR_IGN_1_0_MASK UINT32_C(0x00000003)
2221	/** Handle (Hi). */
2222	#define VTD_BF_REMAPPABLE_IR_ADDR_HANDLE_HI_SHIFT 2
2223	#define VTD_BF_REMAPPABLE_IR_ADDR_HANDLE_HI_MASK UINT32_C(0x00000004)
2224	/** SHV: Subhandle Valid. */
2225	#define VTD_BF_REMAPPABLE_IR_ADDR_SHV_SHIFT 3
2226	#define VTD_BF_REMAPPABLE_IR_ADDR_SHV_MASK UINT32_C(0x00000008)
2227	/** Interrupt format. */
2228	#define VTD_BF_REMAPPABLE_IR_ADDR_INTR_FMT_SHIFT 4
2229	#define VTD_BF_REMAPPABLE_IR_ADDR_INTR_FMT_MASK UINT32_C(0x00000010)
2230	/** Handle (Lo). */
2231	#define VTD_BF_REMAPPABLE_IR_ADDR_HANDLE_LO_SHIFT 5
2232	#define VTD_BF_REMAPPABLE_IR_ADDR_HANDLE_LO_MASK UINT32_C(0x000fffe0)
2233	/** Address. */
2234	#define VTD_BF_REMAPPABLE_IR_ADDR_ADDR_SHIFT 20
2235	#define VTD_BF_REMAPPABLE_IR_ADDR_ADDR_MASK UINT32_C(0xfff00000)
2236	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_REMAPPABLE_IR_ADDR_, UINT32_C(0), UINT32_MAX,
2237	(IGN_1_0, HANDLE_HI, SHV, INTR_FMT, HANDLE_LO, ADDR));
2238
2239	/** Subhandle. */
2240	#define VTD_BF_REMAPPABLE_IR_DATA_SUBHANDLE_SHIFT 0
2241	#define VTD_BF_REMAPPABLE_IR_DATA_SUBHANDLE_MASK UINT32_C(0x0000ffff)
2242	/** R: Reserved (bits 31:16). */
2243	#define VTD_BF_REMAPPABLE_IR_DATA_RSVD_31_16_SHIFT 16
2244	#define VTD_BF_REMAPPABLE_IR_DATA_RSVD_31_16_MASK UINT32_C(0xffff0000)
2245	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_REMAPPABLE_IR_DATA_, UINT32_C(0), UINT32_MAX,
2246	(SUBHANDLE, RSVD_31_16));
2247	/** @} */
2248
2249
2250	/** @name ACPI_DMAR_F_XXX: DMA Remapping Reporting Structure Flags.
2251	* In accordance with the Intel spec.
2252	* @{ */
2253	/** INTR_REMAP: Interrupt remapping supported. */
2254	#define ACPI_DMAR_F_INTR_REMAP RT_BIT(0)
2255	/** X2APIC_OPT_OUT: Request system software to opt-out of enabling x2APIC. */
2256	#define ACPI_DMAR_F_X2APIC_OPT_OUT RT_BIT(1)
2257	/** DMA_CTRL_PLATFORM_OPT_IN_FLAG: Firmware initiated DMA restricted to reserved
2258	* memory regions (RMRR). */
2259	#define ACPI_DMAR_F_DMA_CTRL_PLATFORM_OPT_IN RT_BIT(2)
2260	/** @} */
2261
2262
2263	/** @name ACPI_DRHD_F_XXX: DMA-Remapping Hardware Unit Definition Flags.
2264	* In accordance with the Intel spec.
2265	* @{ */
2266	/** INCLUDE_PCI_ALL: All PCI devices under scope. */
2267	#define ACPI_DRHD_F_INCLUDE_PCI_ALL RT_BIT(0)
2268	/** @} */
2269
2270
2271	/**
2272	* DRHD: DMA-Remapping Hardware Unit Definition.
2273	* In accordance with the Intel spec.
2274	*/
2275	#pragma pack(1)
2276	typedef struct ACPIDRHD
2277	{
2278	/** Type (must be 0=DRHD). */
2279	uint16_t uType;
2280	/** Length (must be 16 + size of device scope structure). */
2281	uint16_t cbLength;
2282	/** Flags, see ACPI_DRHD_F_XXX. */
2283	uint8_t fFlags;
2284	/** Reserved (MBZ). */
2285	uint8_t bRsvd;
2286	/** PCI segment number. */
2287	uint16_t uPciSegment;
2288	/** Register Base Address (MMIO). */
2289	uint64_t uRegBaseAddr;
2290	/* Device Scope[] Structures follow. */
2291	} ACPIDRHD;
2292	#pragma pack()
2293	AssertCompileSize(ACPIDRHD, 16);
2294	AssertCompileMemberOffset(ACPIDRHD, cbLength, 2);
2295	AssertCompileMemberOffset(ACPIDRHD, fFlags, 4);
2296	AssertCompileMemberOffset(ACPIDRHD, uPciSegment, 6);
2297	AssertCompileMemberOffset(ACPIDRHD, uRegBaseAddr, 8);
2298
2299
2300	/** @name ACPIDMARDEVSCOPE_TYPE_XXX: Device Type.
2301	* In accordance with the Intel spec.
2302	* @{ */
2303	#define ACPIDMARDEVSCOPE_TYPE_PCI_ENDPOINT 1
2304	#define ACPIDMARDEVSCOPE_TYPE_PCI_SUB_HIERARCHY 2
2305	#define ACPIDMARDEVSCOPE_TYPE_IOAPIC 3
2306	#define ACPIDMARDEVSCOPE_TYPE_MSI_CAP_HPET 4
2307	#define ACPIDMARDEVSCOPE_TYPE_ACPI_NAMESPACE_DEV 5
2308	/** @} */
2309
2310
2311	/**
2312	* ACPI Device Scope Structure - PCI device path.
2313	* In accordance with the Intel spec.
2314	*/
2315	typedef struct ACPIDEVSCOPEPATH
2316	{
2317	/** PCI device number. */
2318	uint8_t uDevice;
2319	/** PCI function number. */
2320	uint8_t uFunction;
2321	} ACPIDEVSCOPEPATH;
2322	AssertCompileSize(ACPIDEVSCOPEPATH, 2);
2323
2324
2325	/**
2326	* Device Scope Structure.
2327	* In accordance with the Intel spec.
2328	*/
2329	#pragma pack(1)
2330	typedef struct ACPIDMARDEVSCOPE
2331	{
2332	/** Type, see ACPIDMARDEVSCOPE_TYPE_XXX. */
2333	uint8_t uType;
2334	/** Length (must be 6 + size of auPath field). */
2335	uint8_t cbLength;
2336	/** Reserved (MBZ). */
2337	uint8_t abRsvd[2];
2338	/** Enumeration ID (for I/O APIC, HPET and ACPI namespace devices). */
2339	uint8_t idEnum;
2340	/** First bus number for this device. */
2341	uint8_t uStartBusNum;
2342	/** Hierarchical path from the Host Bridge to the device. */
2343	ACPIDEVSCOPEPATH Path;
2344	} ACPIDMARDEVSCOPE;
2345	#pragma pack()
2346	AssertCompileMemberOffset(ACPIDMARDEVSCOPE, cbLength, 1);
2347	AssertCompileMemberOffset(ACPIDMARDEVSCOPE, idEnum, 4);
2348	AssertCompileMemberOffset(ACPIDMARDEVSCOPE, uStartBusNum, 5);
2349	AssertCompileMemberOffset(ACPIDMARDEVSCOPE, Path, 6);
2350
2351	/** ACPI DMAR revision (not the OEM revision field).
2352	* In accordance with the Intel spec. */
2353	#define ACPI_DMAR_REVISION 1
2354
2355
2356	#endif /* !VBOX_INCLUDED_iommu_intel_h */
2357

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source: vbox/trunk/include/VBox/iommu-intel.h@ 88841

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