iommu-intel.h@ 88893

Last change on this file since 88893 was 88893, checked in by vboxsync, 4 years ago
Intel IOMMU: bugref:9967 Interrupt remapping, work-in-progress. Also include reserved bits in the destination ID when xAPIC mode is used when validating reserved bits.
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 126.7 KB

Line
1	/** @file
2	* IOMMU - Input/Output Memory Management Unit (Intel).
3	*/
4
5	/*
6	* Copyright (C) 2021 Oracle Corporation
7	*
8	* This file is part of VirtualBox Open Source Edition (OSE), as
9	* available from http://www.virtualbox.org. This file is free software;
10	* you can redistribute it and/or modify it under the terms of the GNU
11	* General Public License (GPL) as published by the Free Software
12	* Foundation, in version 2 as it comes in the "COPYING" file of the
13	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15	*
16	* The contents of this file may alternatively be used under the terms
17	* of the Common Development and Distribution License Version 1.0
18	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19	* VirtualBox OSE distribution, in which case the provisions of the
20	* CDDL are applicable instead of those of the GPL.
21	*
22	* You may elect to license modified versions of this file under the
23	* terms and conditions of either the GPL or the CDDL or both.
24	*/
25
26	#ifndef VBOX_INCLUDED_iommu_intel_h
27	#define VBOX_INCLUDED_iommu_intel_h
28	#ifndef RT_WITHOUT_PRAGMA_ONCE
29	# pragma once
30	#endif
31
32	#include <iprt/assertcompile.h>
33	#include <iprt/types.h>
34
35
36	/**
37	* @name MMIO register offsets.
38	* In accordance with the Intel spec.
39	* @{
40	*/
41	#define VTD_MMIO_OFF_VER_REG 0x000 /*< Version. /
42	#define VTD_MMIO_OFF_CAP_REG 0x008 /*< Capability. /
43	#define VTD_MMIO_OFF_ECAP_REG 0x010 /*< Extended Capability. /
44	#define VTD_MMIO_OFF_GCMD_REG 0x018 /*< Global Command. /
45	#define VTD_MMIO_OFF_GSTS_REG 0x01c /*< Global Status. /
46	#define VTD_MMIO_OFF_RTADDR_REG 0x020 /*< Root Table Address. /
47	#define VTD_MMIO_OFF_CCMD_REG 0x028 /*< Context Command. /
48
49	#define VTD_MMIO_OFF_FSTS_REG 0x034 /*< Fault Status./
50	#define VTD_MMIO_OFF_FECTL_REG 0x038 /*< Fault Event Control./
51	#define VTD_MMIO_OFF_FEDATA_REG 0x03c /*< Fault Event Data. /
52	#define VTD_MMIO_OFF_FEADDR_REG 0x040 /*< Fault Event Address. /
53	#define VTD_MMIO_OFF_FEUADDR_REG 0x044 /*< Fault Event Upper Address. /
54
55	#define VTD_MMIO_OFF_AFLOG_REG 0x058 /*< Advance Fault Log. /
56
57	#define VTD_MMIO_OFF_PMEN_REG 0x064 /*< Protected Memory Enable (PMEN). /
58	#define VTD_MMIO_OFF_PLMBASE_REG 0x068 /*< Protected Low Memory Base. /
59	#define VTD_MMIO_OFF_PLMLIMIT_REG 0x06c /*< Protected Low Memory Limit. /
60	#define VTD_MMIO_OFF_PHMBASE_REG 0x070 /*< Protected High Memory Base. /
61	#define VTD_MMIO_OFF_PHMLIMIT_REG 0x078 /*< Protected High Memory Limit. /
62
63	#define VTD_MMIO_OFF_IQH_REG 0x080 /*< Invalidation Queue Head. /
64	#define VTD_MMIO_OFF_IQT_REG 0x088 /*< Invalidation Queue Tail. /
65	#define VTD_MMIO_OFF_IQA_REG 0x090 /*< Invalidation Queue Address. /
66	#define VTD_MMIO_OFF_ICS_REG 0x09c /*< Invalidation Completion Status. /
67	#define VTD_MMIO_OFF_IECTL_REG 0x0a0 /*< Invalidation Completion Event Control. /
68	#define VTD_MMIO_OFF_IEDATA_REG 0x0a4 /*< Invalidation Completion Event Data. /
69	#define VTD_MMIO_OFF_IEADDR_REG 0x0a8 /*< Invalidation Completion Event Address. /
70	#define VTD_MMIO_OFF_IEUADDR_REG 0x0ac /*< Invalidation Completion Event Upper Address. /
71	#define VTD_MMIO_OFF_IQERCD_REG 0x0b0 /*< Invalidation Queue Error Record. /
72
73	#define VTD_MMIO_OFF_IRTA_REG 0x0b8 /*< Interrupt Remapping Table Address. /
74
75	#define VTD_MMIO_OFF_PQH_REG 0x0c0 /*< Page Request Queue Head. /
76	#define VTD_MMIO_OFF_PQT_REG 0x0c8 /*< Page Request Queue Tail. /
77	#define VTD_MMIO_OFF_PQA_REG 0x0d0 /*< Page Request Queue Address. /
78	#define VTD_MMIO_OFF_PRS_REG 0x0dc /*< Page Request Status. /
79	#define VTD_MMIO_OFF_PECTL_REG 0x0e0 /*< Page Request Event Control. /
80	#define VTD_MMIO_OFF_PEDATA_REG 0x0e4 /*< Page Request Event Data. /
81	#define VTD_MMIO_OFF_PEADDR_REG 0x0e8 /*< Page Request Event Address. /
82	#define VTD_MMIO_OFF_PEUADDR_REG 0x0ec /*< Page Request Event Upper Address. /
83
84	#define VTD_MMIO_OFF_MTRRCAP_REG 0x100 /*< MTRR Capabliity. /
85	#define VTD_MMIO_OFF_MTRRDEF_REG 0x108 /*< MTRR Default Type. /
86
87	#define VTD_MMIO_OFF_MTRR_FIX64_00000_REG 0x120 /*< Fixed-range MTRR Register for 64K at 00000. /
88	#define VTD_MMIO_OFF_MTRR_FIX16K_80000_REG 0x128 /*< Fixed-range MTRR Register for 16K at 80000. /
89	#define VTD_MMIO_OFF_MTRR_FIX16K_A0000_REG 0x130 /*< Fixed-range MTRR Register for 16K at a0000. /
90	#define VTD_MMIO_OFF_MTRR_FIX4K_C0000_REG 0x138 /*< Fixed-range MTRR Register for 4K at c0000. /
91	#define VTD_MMIO_OFF_MTRR_FIX4K_C8000_REG 0x140 /*< Fixed-range MTRR Register for 4K at c8000. /
92	#define VTD_MMIO_OFF_MTRR_FIX4K_D0000_REG 0x148 /*< Fixed-range MTRR Register for 4K at d0000. /
93	#define VTD_MMIO_OFF_MTRR_FIX4K_D8000_REG 0x150 /*< Fixed-range MTRR Register for 4K at d8000. /
94	#define VTD_MMIO_OFF_MTRR_FIX4K_E0000_REG 0x158 /*< Fixed-range MTRR Register for 4K at e0000. /
95	#define VTD_MMIO_OFF_MTRR_FIX4K_E8000_REG 0x160 /*< Fixed-range MTRR Register for 4K at e8000. /
96	#define VTD_MMIO_OFF_MTRR_FIX4K_F0000_REG 0x168 /*< Fixed-range MTRR Register for 4K at f0000. /
97	#define VTD_MMIO_OFF_MTRR_FIX4K_F8000_REG 0x170 /*< Fixed-range MTRR Register for 4K at f8000. /
98
99	#define VTD_MMIO_OFF_MTRR_PHYSBASE0_REG 0x180 /*< Variable-range MTRR Base 0. /
100	#define VTD_MMIO_OFF_MTRR_PHYSMASK0_REG 0x188 /*< Variable-range MTRR Mask 0. /
101	#define VTD_MMIO_OFF_MTRR_PHYSBASE1_REG 0x190 /*< Variable-range MTRR Base 1. /
102	#define VTD_MMIO_OFF_MTRR_PHYSMASK1_REG 0x198 /*< Variable-range MTRR Mask 1. /
103	#define VTD_MMIO_OFF_MTRR_PHYSBASE2_REG 0x1a0 /*< Variable-range MTRR Base 2. /
104	#define VTD_MMIO_OFF_MTRR_PHYSMASK2_REG 0x1a8 /*< Variable-range MTRR Mask 2. /
105	#define VTD_MMIO_OFF_MTRR_PHYSBASE3_REG 0x1b0 /*< Variable-range MTRR Base 3. /
106	#define VTD_MMIO_OFF_MTRR_PHYSMASK3_REG 0x1b8 /*< Variable-range MTRR Mask 3. /
107	#define VTD_MMIO_OFF_MTRR_PHYSBASE4_REG 0x1c0 /*< Variable-range MTRR Base 4. /
108	#define VTD_MMIO_OFF_MTRR_PHYSMASK4_REG 0x1c8 /*< Variable-range MTRR Mask 4. /
109	#define VTD_MMIO_OFF_MTRR_PHYSBASE5_REG 0x1d0 /*< Variable-range MTRR Base 5. /
110	#define VTD_MMIO_OFF_MTRR_PHYSMASK5_REG 0x1d8 /*< Variable-range MTRR Mask 5. /
111	#define VTD_MMIO_OFF_MTRR_PHYSBASE6_REG 0x1e0 /*< Variable-range MTRR Base 6. /
112	#define VTD_MMIO_OFF_MTRR_PHYSMASK6_REG 0x1e8 /*< Variable-range MTRR Mask 6. /
113	#define VTD_MMIO_OFF_MTRR_PHYSBASE7_REG 0x1f0 /*< Variable-range MTRR Base 7. /
114	#define VTD_MMIO_OFF_MTRR_PHYSMASK7_REG 0x1f8 /*< Variable-range MTRR Mask 7. /
115	#define VTD_MMIO_OFF_MTRR_PHYSBASE8_REG 0x200 /*< Variable-range MTRR Base 8. /
116	#define VTD_MMIO_OFF_MTRR_PHYSMASK8_REG 0x208 /*< Variable-range MTRR Mask 8. /
117	#define VTD_MMIO_OFF_MTRR_PHYSBASE9_REG 0x210 /*< Variable-range MTRR Base 9. /
118	#define VTD_MMIO_OFF_MTRR_PHYSMASK9_REG 0x218 /*< Variable-range MTRR Mask 9. /
119
120	#define VTD_MMIO_OFF_VCCAP_REG 0xe00 /*< Virtual Command Capability. /
121	#define VTD_MMIO_OFF_VCMD_REG 0xe10 /*< Virtual Command. /
122	#define VTD_MMIO_OFF_VCMDRSVD_REG 0xe18 /*< Reserved for future for Virtual Command. /
123	#define VTD_MMIO_OFF_VCRSP_REG 0xe20 /*< Virtual Command Response. /
124	#define VTD_MMIO_OFF_VCRSPRSVD_REG 0xe28 /*< Reserved for future for Virtual Command Response. /
125	/** @} */
126
127
128	/** @name Root Entry.
129	* In accordance with the Intel spec.
130	* @{ */
131	/** P: Present. */
132	#define VTD_BF_0_ROOT_ENTRY_P_SHIFT 0
133	#define VTD_BF_0_ROOT_ENTRY_P_MASK UINT64_C(0x0000000000000001)
134	/** R: Reserved (bits 11:1). */
135	#define VTD_BF_0_ROOT_ENTRY_RSVD_11_1_SHIFT 1
136	#define VTD_BF_0_ROOT_ENTRY_RSVD_11_1_MASK UINT64_C(0x0000000000000ffe)
137	/** CTP: Context-Table Pointer. */
138	#define VTD_BF_0_ROOT_ENTRY_CTP_SHIFT 12
139	#define VTD_BF_0_ROOT_ENTRY_CTP_MASK UINT64_C(0xfffffffffffff000)
140	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_ROOT_ENTRY_, UINT64_C(0), UINT64_MAX,
141	(P, RSVD_11_1, CTP));
142
143	/** Root Entry. */
144	typedef struct VTD_ROOT_ENTRY_T
145	{
146	/** The qwords in the root entry. */
147	uint64_t au64[2];
148	} VTD_ROOT_ENTRY_T;
149	/** Pointer to a root entry. */
150	typedef VTD_ROOT_ENTRY_T *PVTD_ROOT_ENTRY_T;
151	/** Pointer to a const root entry. */
152	typedef VTD_ROOT_ENTRY_T const *PCVTD_ROOT_ENTRY_T;
153	/** @} */
154
155
156	/** @name Scalable-mode Root Entry.
157	* In accordance with the Intel spec.
158	* @{ */
159	/** LP: Lower Present. */
160	#define VTD_BF_0_SM_ROOT_ENTRY_LP_SHIFT 0
161	#define VTD_BF_0_SM_ROOT_ENTRY_LP_MASK UINT64_C(0x0000000000000001)
162	/** R: Reserved (bits 11:1). */
163	#define VTD_BF_0_SM_ROOT_ENTRY_RSVD_11_1_SHIFT 1
164	#define VTD_BF_0_SM_ROOT_ENTRY_RSVD_11_1_MASK UINT64_C(0x0000000000000ffe)
165	/** LCTP: Lower Context-Table Pointer */
166	#define VTD_BF_0_SM_ROOT_ENTRY_LCTP_SHIFT 12
167	#define VTD_BF_0_SM_ROOT_ENTRY_LCTP_MASK UINT64_C(0xfffffffffffff000)
168	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_SM_ROOT_ENTRY_, UINT64_C(0), UINT64_MAX,
169	(LP, RSVD_11_1, LCTP));
170
171	/** UP: Upper Present. */
172	#define VTD_BF_1_SM_ROOT_ENTRY_UP_SHIFT 0
173	#define VTD_BF_1_SM_ROOT_ENTRY_UP_MASK UINT64_C(0x0000000000000001)
174	/** R: Reserved (bits 11:1). */
175	#define VTD_BF_1_SM_ROOT_ENTRY_RSVD_11_1_SHIFT 1
176	#define VTD_BF_1_SM_ROOT_ENTRY_RSVD_11_1_MASK UINT64_C(0x0000000000000ffe)
177	/** UCTP: Upper Context-Table Pointer. */
178	#define VTD_BF_1_SM_ROOT_ENTRY_UCTP_SHIFT 12
179	#define VTD_BF_1_SM_ROOT_ENTRY_UCTP_MASK UINT64_C(0xfffffffffffff000)
180	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_SM_ROOT_ENTRY_, UINT64_C(0), UINT64_MAX,
181	(UP, RSVD_11_1, UCTP));
182
183	/** Scalable-mode root entry. */
184	typedef struct VTD_SM_ROOT_ENTRY_T
185	{
186	/** The lower scalable-mode root entry. */
187	uint64_t uLower;
188	/** The upper scalable-mode root entry. */
189	uint64_t uUpper;
190	} VTD_SM_ROOT_ENTRY_T;
191	/** Pointer to a scalable-mode root entry. */
192	typedef VTD_SM_ROOT_ENTRY_T *PVTD_SM_ROOT_ENTRY_T;
193	/** Pointer to a const scalable-mode root entry. */
194	typedef VTD_SM_ROOT_ENTRY_T const *PCVTD_SM_ROOT_ENTRY_T;
195	/** @} */
196
197
198	/** @name Context Entry.
199	* In accordance with the Intel spec.
200	* @{ */
201	/** P: Present. */
202	#define VTD_BF_0_CONTEXT_ENTRY_P_SHIFT 0
203	#define VTD_BF_0_CONTEXT_ENTRY_P_MASK UINT64_C(0x0000000000000001)
204	/** FPD: Fault Processing Disable. */
205	#define VTD_BF_0_CONTEXT_ENTRY_FPD_SHIFT 1
206	#define VTD_BF_0_CONTEXT_ENTRY_FPD_MASK UINT64_C(0x0000000000000002)
207	/** TT: Translation Type. */
208	#define VTD_BF_0_CONTEXT_ENTRY_TT_SHIFT 2
209	#define VTD_BF_0_CONTEXT_ENTRY_TT_MASK UINT64_C(0x000000000000000c)
210	/** R: Reserved (bits 11:4). */
211	#define VTD_BF_0_CONTEXT_ENTRY_RSVD_11_4_SHIFT 4
212	#define VTD_BF_0_CONTEXT_ENTRY_RSVD_11_4_MASK UINT64_C(0x0000000000000ff0)
213	/** SLPTPTR: Second Level Page Translation Pointer. */
214	#define VTD_BF_0_CONTEXT_ENTRY_SLPTPTR_SHIFT 12
215	#define VTD_BF_0_CONTEXT_ENTRY_SLPTPTR_MASK UINT64_C(0xfffffffffffff000)
216	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_CONTEXT_ENTRY_, UINT64_C(0), UINT64_MAX,
217	(P, FPD, TT, RSVD_11_4, SLPTPTR));
218
219	/** AW: Address Width. */
220	#define VTD_BF_1_CONTEXT_ENTRY_AW_SHIFT 0
221	#define VTD_BF_1_CONTEXT_ENTRY_AW_MASK UINT64_C(0x0000000000000007)
222	/** IGN: Ignored (bits 6:3). */
223	#define VTD_BF_1_CONTEXT_ENTRY_IGN_6_3_SHIFT 3
224	#define VTD_BF_1_CONTEXT_ENTRY_IGN_6_3_MASK UINT64_C(0x0000000000000078)
225	/** R: Reserved (bit 7). */
226	#define VTD_BF_1_CONTEXT_ENTRY_RSVD_7_SHIFT 7
227	#define VTD_BF_1_CONTEXT_ENTRY_RSVD_7_MASK UINT64_C(0x0000000000000080)
228	/** DID: Domain Identifier. */
229	#define VTD_BF_1_CONTEXT_ENTRY_DID_SHIFT 8
230	#define VTD_BF_1_CONTEXT_ENTRY_DID_MASK UINT64_C(0x0000000000ffff00)
231	/** R: Reserved (bits 63:24). */
232	#define VTD_BF_1_CONTEXT_ENTRY_RSVD_63_24_SHIFT 24
233	#define VTD_BF_1_CONTEXT_ENTRY_RSVD_63_24_MASK UINT64_C(0xffffffffff000000)
234	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_CONTEXT_ENTRY_, UINT64_C(0), UINT64_MAX,
235	(AW, IGN_6_3, RSVD_7, DID, RSVD_63_24));
236
237	/** Context Entry. */
238	typedef struct VTD_CONTEXT_ENTRY_T
239	{
240	/** The qwords in the context entry. */
241	uint64_t au64[2];
242	} VTD_CONTEXT_ENTRY_T;
243	/** Pointer to a context entry. */
244	typedef VTD_CONTEXT_ENTRY_T *PVTD_CONTEXT_ENTRY_T;
245	/** Pointer to a const context entry. */
246	typedef VTD_CONTEXT_ENTRY_T const *PCVTD_CONTEXT_ENTRY_T;
247	/** @} */
248
249
250	/** @name Scalable-mode Context Entry.
251	* In accordance with the Intel spec.
252	* @{ */
253	/** P: Present. */
254	#define VTD_BF_0_SM_CONTEXT_ENTRY_P_SHIFT 0
255	#define VTD_BF_0_SM_CONTEXT_ENTRY_P_MASK UINT64_C(0x0000000000000001)
256	/** FPD: Fault Processing Disable. */
257	#define VTD_BF_0_SM_CONTEXT_ENTRY_FPD_SHIFT 1
258	#define VTD_BF_0_SM_CONTEXT_ENTRY_FPD_MASK UINT64_C(0x0000000000000002)
259	/** DTE: Device-TLB Enable. */
260	#define VTD_BF_0_SM_CONTEXT_ENTRY_DTE_SHIFT 2
261	#define VTD_BF_0_SM_CONTEXT_ENTRY_DTE_MASK UINT64_C(0x0000000000000004)
262	/** PASIDE: PASID Enable. */
263	#define VTD_BF_0_SM_CONTEXT_ENTRY_PASIDE_SHIFT 3
264	#define VTD_BF_0_SM_CONTEXT_ENTRY_PASIDE_MASK UINT64_C(0x0000000000000008)
265	/** PRE: Page Request Enable. */
266	#define VTD_BF_0_SM_CONTEXT_ENTRY_PRE_SHIFT 4
267	#define VTD_BF_0_SM_CONTEXT_ENTRY_PRE_MASK UINT64_C(0x0000000000000010)
268	/** R: Reserved (bits 8:5). */
269	#define VTD_BF_0_SM_CONTEXT_ENTRY_RSVD_8_5_SHIFT 5
270	#define VTD_BF_0_SM_CONTEXT_ENTRY_RSVD_8_5_MASK UINT64_C(0x00000000000001e0)
271	/** PDTS: PASID Directory Size. */
272	#define VTD_BF_0_SM_CONTEXT_ENTRY_PDTS_SHIFT 9
273	#define VTD_BF_0_SM_CONTEXT_ENTRY_PDTS_MASK UINT64_C(0x0000000000000e00)
274	/** PASIDDIRPTR: PASID Directory Pointer. */
275	#define VTD_BF_0_SM_CONTEXT_ENTRY_PASIDDIRPTR_SHIFT 12
276	#define VTD_BF_0_SM_CONTEXT_ENTRY_PASIDDIRPTR_MASK UINT64_C(0xfffffffffffff000)
277	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_SM_CONTEXT_ENTRY_, UINT64_C(0), UINT64_MAX,
278	(P, FPD, DTE, PASIDE, PRE, RSVD_8_5, PDTS, PASIDDIRPTR));
279
280	/** RID_PASID: Requested Id to PASID assignment. */
281	#define VTD_BF_1_SM_CONTEXT_ENTRY_RID_PASID_SHIFT 0
282	#define VTD_BF_1_SM_CONTEXT_ENTRY_RID_PASID_MASK UINT64_C(0x00000000000fffff)
283	/** RID_PRIV: Requested Id to PrivilegeModeRequested assignment. */
284	#define VTD_BF_1_SM_CONTEXT_ENTRY_RID_PRIV_SHIFT 20
285	#define VTD_BF_1_SM_CONTEXT_ENTRY_RID_PRIV_MASK UINT64_C(0x0000000000100000)
286	/** R: Reserved (bits 63:21). */
287	#define VTD_BF_1_SM_CONTEXT_ENTRY_RSVD_63_21_SHIFT 21
288	#define VTD_BF_1_SM_CONTEXT_ENTRY_RSVD_63_21_MASK UINT64_C(0xffffffffffe00000)
289	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_SM_CONTEXT_ENTRY_, UINT64_C(0), UINT64_MAX,
290	(RID_PASID, RID_PRIV, RSVD_63_21));
291
292	/** Context Entry. */
293	typedef struct VTD_SM_CONTEXT_ENTRY_T
294	{
295	/** The qwords in the scalable-mode context entry. */
296	uint64_t au64[4];
297	} VTD_SM_CONTEXT_ENTRY_T;
298	/** Pointer to a scalable-mode context entry. */
299	typedef VTD_SM_CONTEXT_ENTRY_T *PVTD_SM_CONTEXT_ENTRY_T;
300	/** Pointer to a const scalable-mode context entry. */
301	typedef VTD_SM_CONTEXT_ENTRY_T const *PCVTD_SM_CONTEXT_ENTRY_T;
302	/** @} */
303
304
305	/** @name Scalable-mode PASID Directory Entry.
306	* In accordance with the Intel spec.
307	* @{ */
308	/** P: Present. */
309	#define VTD_BF_SM_PASID_DIR_ENTRY_P_SHIFT 0
310	#define VTD_BF_SM_PASID_DIR_ENTRY_P_MASK UINT64_C(0x0000000000000001)
311	/** FPD: Fault Processing Disable. */
312	#define VTD_BF_SM_PASID_DIR_ENTRY_FPD_SHIFT 1
313	#define VTD_BF_SM_PASID_DIR_ENTRY_FPD_MASK UINT64_C(0x0000000000000002)
314	/** R: Reserved (bits 11:2). */
315	#define VTD_BF_SM_PASID_DIR_ENTRY_RSVD_11_2_SHIFT 2
316	#define VTD_BF_SM_PASID_DIR_ENTRY_RSVD_11_2_MASK UINT64_C(0x0000000000000ffc)
317	/** SMPTBLPTR: Scalable Mode PASID Table Pointer. */
318	#define VTD_BF_SM_PASID_DIR_ENTRY_SMPTBLPTR_SHIFT 12
319	#define VTD_BF_SM_PASID_DIR_ENTRY_SMPTBLPTR_MASK UINT64_C(0xfffffffffffff000)
320	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_SM_PASID_DIR_ENTRY_, UINT64_C(0), UINT64_MAX,
321	(P, FPD, RSVD_11_2, SMPTBLPTR));
322
323	/** Scalable-mode PASID Directory Entry. */
324	typedef struct VTD_SM_PASID_DIR_ENTRY_T
325	{
326	/** The scalable-mode PASID directory entry. */
327	uint64_t u;
328	} VTD_SM_PASID_DIR_ENTRY_T;
329	/** Pointer to a scalable-mode PASID directory entry. */
330	typedef VTD_SM_PASID_DIR_ENTRY_T *PVTD_SM_PASID_DIR_ENTRY_T;
331	/** Pointer to a const scalable-mode PASID directory entry. */
332	typedef VTD_SM_PASID_DIR_ENTRY_T const *PCVTD_SM_PASID_DIR_ENTRY_T;
333	/** @} */
334
335
336	/** @name Scalable-mode PASID Table Entry.
337	* In accordance with the Intel spec.
338	* @{ */
339	/** P: Present. */
340	#define VTD_BF_0_SM_PASID_TBL_ENTRY_P_SHIFT 0
341	#define VTD_BF_0_SM_PASID_TBL_ENTRY_P_MASK UINT64_C(0x0000000000000001)
342	/** FPD: Fault Processing Disable. */
343	#define VTD_BF_0_SM_PASID_TBL_ENTRY_FPD_SHIFT 1
344	#define VTD_BF_0_SM_PASID_TBL_ENTRY_FPD_MASK UINT64_C(0x0000000000000002)
345	/** AW: Address Width. */
346	#define VTD_BF_0_SM_PASID_TBL_ENTRY_AW_SHIFT 2
347	#define VTD_BF_0_SM_PASID_TBL_ENTRY_AW_MASK UINT64_C(0x000000000000001c)
348	/** SLEE: Second-Level Execute Enable. */
349	#define VTD_BF_0_SM_PASID_TBL_ENTRY_SLEE_SHIFT 5
350	#define VTD_BF_0_SM_PASID_TBL_ENTRY_SLEE_MASK UINT64_C(0x0000000000000020)
351	/** PGTT: PASID Granular Translation Type. */
352	#define VTD_BF_0_SM_PASID_TBL_ENTRY_PGTT_SHIFT 6
353	#define VTD_BF_0_SM_PASID_TBL_ENTRY_PGTT_MASK UINT64_C(0x00000000000001c0)
354	/** SLADE: Second-Level Address/Dirty Enable. */
355	#define VTD_BF_0_SM_PASID_TBL_ENTRY_SLADE_SHIFT 9
356	#define VTD_BF_0_SM_PASID_TBL_ENTRY_SLADE_MASK UINT64_C(0x0000000000000200)
357	/** R: Reserved (bits 11:10). */
358	#define VTD_BF_0_SM_PASID_TBL_ENTRY_RSVD_11_10_SHIFT 10
359	#define VTD_BF_0_SM_PASID_TBL_ENTRY_RSVD_11_10_MASK UINT64_C(0x0000000000000c00)
360	/** SLPTPTR: Second-Level Page Table Pointer. */
361	#define VTD_BF_0_SM_PASID_TBL_ENTRY_SLPTPTR_SHIFT 12
362	#define VTD_BF_0_SM_PASID_TBL_ENTRY_SLPTPTR_MASK UINT64_C(0xfffffffffffff000)
363	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_SM_PASID_TBL_ENTRY_, UINT64_C(0), UINT64_MAX,
364	(P, FPD, AW, SLEE, PGTT, SLADE, RSVD_11_10, SLPTPTR));
365
366	/** DID: Domain Identifer. */
367	#define VTD_BF_1_SM_PASID_TBL_ENTRY_DID_SHIFT 0
368	#define VTD_BF_1_SM_PASID_TBL_ENTRY_DID_MASK UINT64_C(0x000000000000ffff)
369	/** R: Reserved (bits 22:16). */
370	#define VTD_BF_1_SM_PASID_TBL_ENTRY_RSVD_22_16_SHIFT 16
371	#define VTD_BF_1_SM_PASID_TBL_ENTRY_RSVD_22_16_MASK UINT64_C(0x00000000007f0000)
372	/** PWSNP: Page-Walk Snoop. */
373	#define VTD_BF_1_SM_PASID_TBL_ENTRY_PWSNP_SHIFT 23
374	#define VTD_BF_1_SM_PASID_TBL_ENTRY_PWSNP_MASK UINT64_C(0x0000000000800000)
375	/** PGSNP: Page Snoop. */
376	#define VTD_BF_1_SM_PASID_TBL_ENTRY_PGSNP_SHIFT 24
377	#define VTD_BF_1_SM_PASID_TBL_ENTRY_PGSNP_MASK UINT64_C(0x0000000001000000)
378	/** CD: Cache Disable. */
379	#define VTD_BF_1_SM_PASID_TBL_ENTRY_CD_SHIFT 25
380	#define VTD_BF_1_SM_PASID_TBL_ENTRY_CD_MASK UINT64_C(0x0000000002000000)
381	/** EMTE: Extended Memory Type Enable. */
382	#define VTD_BF_1_SM_PASID_TBL_ENTRY_EMTE_SHIFT 26
383	#define VTD_BF_1_SM_PASID_TBL_ENTRY_EMTE_MASK UINT64_C(0x0000000004000000)
384	/** EMT: Extended Memory Type. */
385	#define VTD_BF_1_SM_PASID_TBL_ENTRY_EMT_SHIFT 27
386	#define VTD_BF_1_SM_PASID_TBL_ENTRY_EMT_MASK UINT64_C(0x0000000038000000)
387	/** PWT: Page-Level Write Through. */
388	#define VTD_BF_1_SM_PASID_TBL_ENTRY_PWT_SHIFT 30
389	#define VTD_BF_1_SM_PASID_TBL_ENTRY_PWT_MASK UINT64_C(0x0000000040000000)
390	/** PCD: Page-Level Cache Disable. */
391	#define VTD_BF_1_SM_PASID_TBL_ENTRY_PCD_SHIFT 31
392	#define VTD_BF_1_SM_PASID_TBL_ENTRY_PCD_MASK UINT64_C(0x0000000080000000)
393	/** PAT: Page Attribute Table. */
394	#define VTD_BF_1_SM_PASID_TBL_ENTRY_PAT_SHIFT 32
395	#define VTD_BF_1_SM_PASID_TBL_ENTRY_PAT_MASK UINT64_C(0xffffffff00000000)
396	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_SM_PASID_TBL_ENTRY_, UINT64_C(0), UINT64_MAX,
397	(DID, RSVD_22_16, PWSNP, PGSNP, CD, EMTE, EMT, PWT, PCD, PAT));
398
399	/** SRE: Supervisor Request Enable. */
400	#define VTD_BF_2_SM_PASID_TBL_ENTRY_SRE_SHIFT 0
401	#define VTD_BF_2_SM_PASID_TBL_ENTRY_SRE_MASK UINT64_C(0x0000000000000001)
402	/** ERE: Execute Request Enable. */
403	#define VTD_BF_2_SM_PASID_TBL_ENTRY_ERE_SHIFT 1
404	#define VTD_BF_2_SM_PASID_TBL_ENTRY_ERE_MASK UINT64_C(0x0000000000000002)
405	/** FLPM: First Level Paging Mode. */
406	#define VTD_BF_2_SM_PASID_TBL_ENTRY_FLPM_SHIFT 2
407	#define VTD_BF_2_SM_PASID_TBL_ENTRY_FLPM_MASK UINT64_C(0x000000000000000c)
408	/** WPE: Write Protect Enable. */
409	#define VTD_BF_2_SM_PASID_TBL_ENTRY_WPE_SHIFT 4
410	#define VTD_BF_2_SM_PASID_TBL_ENTRY_WPE_MASK UINT64_C(0x0000000000000010)
411	/** NXE: No-Execute Enable. */
412	#define VTD_BF_2_SM_PASID_TBL_ENTRY_NXE_SHIFT 5
413	#define VTD_BF_2_SM_PASID_TBL_ENTRY_NXE_MASK UINT64_C(0x0000000000000020)
414	/** SMEP: Supervisor Mode Execute Prevent. */
415	#define VTD_BF_2_SM_PASID_TBL_ENTRY_SMPE_SHIFT 6
416	#define VTD_BF_2_SM_PASID_TBL_ENTRY_SMPE_MASK UINT64_C(0x0000000000000040)
417	/** EAFE: Extended Accessed Flag Enable. */
418	#define VTD_BF_2_SM_PASID_TBL_ENTRY_EAFE_SHIFT 7
419	#define VTD_BF_2_SM_PASID_TBL_ENTRY_EAFE_MASK UINT64_C(0x0000000000000080)
420	/** R: Reserved (bits 11:8). */
421	#define VTD_BF_2_SM_PASID_TBL_ENTRY_RSVD_11_8_SHIFT 8
422	#define VTD_BF_2_SM_PASID_TBL_ENTRY_RSVD_11_8_MASK UINT64_C(0x0000000000000f00)
423	/** FLPTPTR: First Level Page Table Pointer. */
424	#define VTD_BF_2_SM_PASID_TBL_ENTRY_FLPTPTR_SHIFT 12
425	#define VTD_BF_2_SM_PASID_TBL_ENTRY_FLPTPTR_MASK UINT64_C(0xfffffffffffff000)
426	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_2_SM_PASID_TBL_ENTRY_, UINT64_C(0), UINT64_MAX,
427	(SRE, ERE, FLPM, WPE, NXE, SMPE, EAFE, RSVD_11_8, FLPTPTR));
428
429	/** Scalable-mode PASID Table Entry. */
430	typedef struct VTD_SM_PASID_TBL_ENTRY_T
431	{
432	/** The qwords in the scalable-mode PASID table entry. */
433	uint64_t au64[8];
434	} VTD_SM_PASID_TBL_ENTRY_T;
435	/** Pointer to a scalable-mode PASID table entry. */
436	typedef VTD_SM_PASID_TBL_ENTRY_T *PVTD_SM_PASID_TBL_ENTRY_T;
437	/** Pointer to a const scalable-mode PASID table entry. */
438	typedef VTD_SM_PASID_TBL_ENTRY_T const *PCVTD_SM_PASID_TBL_ENTRY_T;
439	/** @} */
440
441
442	/** @name First-Level Paging Entry.
443	* In accordance with the Intel spec.
444	* @{ */
445	/** P: Present. */
446	#define VTD_BF_FLP_ENTRY_P_SHIFT 0
447	#define VTD_BF_FLP_ENTRY_P_MASK UINT64_C(0x0000000000000001)
448	/** R/W: Read/Write. */
449	#define VTD_BF_FLP_ENTRY_RW_SHIFT 1
450	#define VTD_BF_FLP_ENTRY_RW_MASK UINT64_C(0x0000000000000002)
451	/** U/S: User/Supervisor. */
452	#define VTD_BF_FLP_ENTRY_US_SHIFT 2
453	#define VTD_BF_FLP_ENTRY_US_MASK UINT64_C(0x0000000000000004)
454	/** PWT: Page-Level Write Through. */
455	#define VTD_BF_FLP_ENTRY_PWT_SHIFT 3
456	#define VTD_BF_FLP_ENTRY_PWT_MASK UINT64_C(0x0000000000000008)
457	/** PC: Page-Level Cache Disable. */
458	#define VTD_BF_FLP_ENTRY_PCD_SHIFT 4
459	#define VTD_BF_FLP_ENTRY_PCD_MASK UINT64_C(0x0000000000000010)
460	/** A: Accessed. */
461	#define VTD_BF_FLP_ENTRY_A_SHIFT 5
462	#define VTD_BF_FLP_ENTRY_A_MASK UINT64_C(0x0000000000000020)
463	/** IGN: Ignored (bit 6). */
464	#define VTD_BF_FLP_ENTRY_IGN_6_SHIFT 6
465	#define VTD_BF_FLP_ENTRY_IGN_6_MASK UINT64_C(0x0000000000000040)
466	/** R: Reserved (bit 7). */
467	#define VTD_BF_FLP_ENTRY_RSVD_7_SHIFT 7
468	#define VTD_BF_FLP_ENTRY_RSVD_7_MASK UINT64_C(0x0000000000000080)
469	/** IGN: Ignored (bits 9:8). */
470	#define VTD_BF_FLP_ENTRY_IGN_9_8_SHIFT 8
471	#define VTD_BF_FLP_ENTRY_IGN_9_8_MASK UINT64_C(0x0000000000000300)
472	/** EA: Extended Accessed. */
473	#define VTD_BF_FLP_ENTRY_EA_SHIFT 10
474	#define VTD_BF_FLP_ENTRY_EA_MASK UINT64_C(0x0000000000000400)
475	/** IGN: Ignored (bit 11). */
476	#define VTD_BF_FLP_ENTRY_IGN_11_SHIFT 11
477	#define VTD_BF_FLP_ENTRY_IGN_11_MASK UINT64_C(0x0000000000000800)
478	/** ADDR: Address. */
479	#define VTD_BF_FLP_ENTRY_ADDR_SHIFT 12
480	#define VTD_BF_FLP_ENTRY_ADDR_MASK UINT64_C(0x000ffffffffff000)
481	/** IGN: Ignored (bits 62:52). */
482	#define VTD_BF_FLP_ENTRY_IGN_62_52_SHIFT 52
483	#define VTD_BF_FLP_ENTRY_IGN_62_52_MASK UINT64_C(0x7ff0000000000000)
484	/** XD: Execute Disabled. */
485	#define VTD_BF_FLP_ENTRY_XD_SHIFT 63
486	#define VTD_BF_FLP_ENTRY_XD_MASK UINT64_C(0x8000000000000000)
487	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_FLP_ENTRY_, UINT64_C(0), UINT64_MAX,
488	(P, RW, US, PWT, PCD, A, IGN_6, RSVD_7, IGN_9_8, EA, IGN_11, ADDR, IGN_62_52, XD));
489
490	/** First-Level Paging Entry. */
491	typedef struct VTD_FLP_ENTRY_T
492	{
493	/** The first-level paging entry. */
494	uint64_t u;
495	} VTD_FLP_ENTRY_T;
496	/** Pointer to a first-level paging entry. */
497	typedef VTD_FLP_ENTRY_T *PVTD_FLP_ENTRY_T;
498	/** Pointer to a const first-level paging entry. */
499	typedef VTD_FLP_ENTRY_T const *PCVTD_FLP_ENTRY_T;
500	/** @} */
501
502
503	/** @name Second-Level Paging Entry.
504	* In accordance with the Intel spec.
505	* @{ */
506	/** R: Read. */
507	#define VTD_BF_SLP_ENTRY_R_SHIFT 0
508	#define VTD_BF_SLP_ENTRY_R_MASK UINT64_C(0x0000000000000001)
509	/** W: Write. */
510	#define VTD_BF_SLP_ENTRY_W_SHIFT 1
511	#define VTD_BF_SLP_ENTRY_W_MASK UINT64_C(0x0000000000000002)
512	/** X: Execute. */
513	#define VTD_BF_SLP_ENTRY_X_SHIFT 2
514	#define VTD_BF_SLP_ENTRY_X_MASK UINT64_C(0x0000000000000004)
515	/** IGN: Ignored (bits 6:3). */
516	#define VTD_BF_SLP_ENTRY_IGN_6_3_SHIFT 3
517	#define VTD_BF_SLP_ENTRY_IGN_6_3_MASK UINT64_C(0x0000000000000078)
518	/** R: Reserved (bit 7). */
519	#define VTD_BF_SLP_ENTRY_RSVD_7_SHIFT 7
520	#define VTD_BF_SLP_ENTRY_RSVD_7_MASK UINT64_C(0x0000000000000080)
521	/** A: Accessed. */
522	#define VTD_BF_SLP_ENTRY_A_SHIFT 8
523	#define VTD_BF_SLP_ENTRY_A_MASK UINT64_C(0x0000000000000100)
524	/** IGN: Ignored (bits 10:9). */
525	#define VTD_BF_SLP_ENTRY_IGN_10_9_SHIFT 9
526	#define VTD_BF_SLP_ENTRY_IGN_10_9_MASK UINT64_C(0x0000000000000600)
527	/** R: Reserved (bit 11). */
528	#define VTD_BF_SLP_ENTRY_RSVD_11_SHIFT 11
529	#define VTD_BF_SLP_ENTRY_RSVD_11_MASK UINT64_C(0x0000000000000800)
530	/** ADDR: Address. */
531	#define VTD_BF_SLP_ENTRY_ADDR_SHIFT 12
532	#define VTD_BF_SLP_ENTRY_ADDR_MASK UINT64_C(0x000ffffffffff000)
533	/** IGN: Ignored (bits 61:52). */
534	#define VTD_BF_SLP_ENTRY_IGN_61_52_SHIFT 52
535	#define VTD_BF_SLP_ENTRY_IGN_61_52_MASK UINT64_C(0x3ff0000000000000)
536	/** R: Reserved (bit 62). */
537	#define VTD_BF_SLP_ENTRY_RSVD_62_SHIFT 62
538	#define VTD_BF_SLP_ENTRY_RSVD_62_MASK UINT64_C(0x4000000000000000)
539	/** IGN: Ignored (bit 63). */
540	#define VTD_BF_SLP_ENTRY_IGN_63_SHIFT 63
541	#define VTD_BF_SLP_ENTRY_IGN_63_MASK UINT64_C(0x8000000000000000)
542	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_SLP_ENTRY_, UINT64_C(0), UINT64_MAX,
543	(R, W, X, IGN_6_3, RSVD_7, A, IGN_10_9, RSVD_11, ADDR, IGN_61_52, RSVD_62, IGN_63));
544
545	/** Second-Level Paging Entry. */
546	typedef struct VTD_SLP_ENTRY_T
547	{
548	/** The second-level paging entry. */
549	uint64_t u;
550	} VTD_SLP_ENTRY_T;
551	/** Pointer to a second-level paging entry. */
552	typedef VTD_SLP_ENTRY_T *PVTD_SLP_ENTRY_T;
553	/** Pointer to a const second-level paging entry. */
554	typedef VTD_SLP_ENTRY_T const *PCVTD_SLP_ENTRY_T;
555	/** @} */
556
557
558	/** @name Fault Record.
559	* In accordance with the Intel spec.
560	* @{ */
561	/** R: Reserved (bits 11:0). */
562	#define VTD_BF_0_FAULT_RECORD_RSVD_11_0_SHIFT 0
563	#define VTD_BF_0_FAULT_RECORD_RSVD_11_0_MASK UINT64_C(0x0000000000000fff)
564	/** FI: Fault Information. */
565	#define VTD_BF_0_FAULT_RECORD_FI_SHIFT 12
566	#define VTD_BF_0_FAULT_RECORD_FI_MASK UINT64_C(0xfffffffffffff000)
567	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_FAULT_RECORD_, UINT64_C(0), UINT64_MAX,
568	(RSVD_11_0, FI));
569
570	/** SID: Source identifier. */
571	#define VTD_BF_1_FAULT_RECORD_SID_SHIFT 0
572	#define VTD_BF_1_FAULT_RECORD_SID_MASK UINT64_C(0x000000000000ffff)
573	/** R: Reserved (bits 28:16). */
574	#define VTD_BF_1_FAULT_RECORD_RSVD_28_16_SHIFT 16
575	#define VTD_BF_1_FAULT_RECORD_RSVD_28_16_MASK UINT64_C(0x000000001fff0000)
576	/** PRIV: Privilege Mode Requested. */
577	#define VTD_BF_1_FAULT_RECORD_PRIV_SHIFT 29
578	#define VTD_BF_1_FAULT_RECORD_PRIV_MASK UINT64_C(0x0000000020000000)
579	/** EXE: Execute Permission Requested. */
580	#define VTD_BF_1_FAULT_RECORD_EXE_SHIFT 30
581	#define VTD_BF_1_FAULT_RECORD_EXE_MASK UINT64_C(0x0000000040000000)
582	/** PP: PASID Present. */
583	#define VTD_BF_1_FAULT_RECORD_PP_SHIFT 31
584	#define VTD_BF_1_FAULT_RECORD_PP_MASK UINT64_C(0x0000000080000000)
585	/** FR: Fault Reason. */
586	#define VTD_BF_1_FAULT_RECORD_FR_SHIFT 32
587	#define VTD_BF_1_FAULT_RECORD_FR_MASK UINT64_C(0x000000ff00000000)
588	/** PV: PASID Value. */
589	#define VTD_BF_1_FAULT_RECORD_PV_SHIFT 40
590	#define VTD_BF_1_FAULT_RECORD_PV_MASK UINT64_C(0x0fffff0000000000)
591	/** AT: Address Type. */
592	#define VTD_BF_1_FAULT_RECORD_AT_SHIFT 60
593	#define VTD_BF_1_FAULT_RECORD_AT_MASK UINT64_C(0x3000000000000000)
594	/** T: Type. */
595	#define VTD_BF_1_FAULT_RECORD_T_SHIFT 62
596	#define VTD_BF_1_FAULT_RECORD_T_MASK UINT64_C(0x4000000000000000)
597	/** R: Reserved (bit 127). */
598	#define VTD_BF_1_FAULT_RECORD_RSVD_63_SHIFT 63
599	#define VTD_BF_1_FAULT_RECORD_RSVD_63_MASK UINT64_C(0x8000000000000000)
600	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_FAULT_RECORD_, UINT64_C(0), UINT64_MAX,
601	(SID, RSVD_28_16, PRIV, EXE, PP, FR, PV, AT, T, RSVD_63));
602
603	/** Fault record. */
604	typedef struct VTD_FAULT_RECORD_T
605	{
606	/** The qwords in the fault record. */
607	uint64_t au64[2];
608	} VTD_FAULT_RECORD_T;
609	/** Pointer to a fault record. */
610	typedef VTD_FAULT_RECORD_T *PVTD_FAULT_RECORD_T;
611	/** Pointer to a const fault record. */
612	typedef VTD_FAULT_RECORD_T const *PCVTD_FAULT_RECORD_T;
613	/** @} */
614
615
616	/** @name Interrupt Remapping Table Entry (IRTE) for Remapped Interrupts.
617	* In accordance with the Intel spec.
618	* @{ */
619	/** P: Present. */
620	#define VTD_BF_0_IRTE_P_SHIFT 0
621	#define VTD_BF_0_IRTE_P_MASK UINT64_C(0x0000000000000001)
622	/** FPD: Fault Processing Disable. */
623	#define VTD_BF_0_IRTE_FPD_SHIFT 1
624	#define VTD_BF_0_IRTE_FPD_MASK UINT64_C(0x0000000000000002)
625	/** DM: Destination Mode (0=physical, 1=logical). */
626	#define VTD_BF_0_IRTE_DM_SHIFT 2
627	#define VTD_BF_0_IRTE_DM_MASK UINT64_C(0x0000000000000004)
628	/** RH: Redirection Hint. */
629	#define VTD_BF_0_IRTE_RH_SHIFT 3
630	#define VTD_BF_0_IRTE_RH_MASK UINT64_C(0x0000000000000008)
631	/** TM: Trigger Mode. */
632	#define VTD_BF_0_IRTE_TM_SHIFT 4
633	#define VTD_BF_0_IRTE_TM_MASK UINT64_C(0x0000000000000010)
634	/** DLM: Delivery Mode. */
635	#define VTD_BF_0_IRTE_DLM_SHIFT 5
636	#define VTD_BF_0_IRTE_DLM_MASK UINT64_C(0x00000000000000e0)
637	/** AVL: Available. */
638	#define VTD_BF_0_IRTE_AVAIL_SHIFT 8
639	#define VTD_BF_0_IRTE_AVAIL_MASK UINT64_C(0x0000000000000f00)
640	/** R: Reserved (bits 14:12). */
641	#define VTD_BF_0_IRTE_RSVD_14_12_SHIFT 12
642	#define VTD_BF_0_IRTE_RSVD_14_12_MASK UINT64_C(0x0000000000007000)
643	/** IM: IRTE Mode. */
644	#define VTD_BF_0_IRTE_IM_SHIFT 15
645	#define VTD_BF_0_IRTE_IM_MASK UINT64_C(0x0000000000008000)
646	/** V: Vector. */
647	#define VTD_BF_0_IRTE_V_SHIFT 16
648	#define VTD_BF_0_IRTE_V_MASK UINT64_C(0x0000000000ff0000)
649	/** R: Reserved (bits 31:24). */
650	#define VTD_BF_0_IRTE_RSVD_31_24_SHIFT 24
651	#define VTD_BF_0_IRTE_RSVD_31_24_MASK UINT64_C(0x00000000ff000000)
652	/** DST: Desination Id. */
653	#define VTD_BF_0_IRTE_DST_SHIFT 32
654	#define VTD_BF_0_IRTE_DST_MASK UINT64_C(0xffffffff00000000)
655	/** R: Reserved (bits 39:32) when EIME=0. */
656	#define VTD_BF_0_IRTE_RSVD_39_32_SHIFT 32
657	#define VTD_BF_0_IRTE_RSVD_39_32_MASK UINT64_C(0x000000ff00000000)
658	/** DST_XAPIC: Destination Id when EIME=0. */
659	#define VTD_BF_0_IRTE_DST_XAPIC_SHIFT 40
660	#define VTD_BF_0_IRTE_DST_XAPIC_MASK UINT64_C(0x0000ff0000000000)
661	/** R: Reserved (bits 63:48) when EIME=0. */
662	#define VTD_BF_0_IRTE_RSVD_63_48_SHIFT 48
663	#define VTD_BF_0_IRTE_RSVD_63_48_MASK UINT64_C(0xffff000000000000)
664	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_IRTE_, UINT64_C(0), UINT64_MAX,
665	(P, FPD, DM, RH, TM, DLM, AVAIL, RSVD_14_12, IM, V, RSVD_31_24, DST));
666	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_IRTE_, UINT64_C(0), UINT64_MAX,
667	(P, FPD, DM, RH, TM, DLM, AVAIL, RSVD_14_12, IM, V, RSVD_31_24, RSVD_39_32, DST_XAPIC, RSVD_63_48));
668
669	/** SID: Source Identifier. */
670	#define VTD_BF_1_IRTE_SID_SHIFT 0
671	#define VTD_BF_1_IRTE_SID_MASK UINT64_C(0x000000000000ffff)
672	/** SQ: Source-Id Qualifier. */
673	#define VTD_BF_1_IRTE_SQ_SHIFT 16
674	#define VTD_BF_1_IRTE_SQ_MASK UINT64_C(0x0000000000030000)
675	/** SVT: Source Validation Type. */
676	#define VTD_BF_1_IRTE_SVT_SHIFT 18
677	#define VTD_BF_1_IRTE_SVT_MASK UINT64_C(0x00000000000c0000)
678	/** R: Reserved (bits 127:84). */
679	#define VTD_BF_1_IRTE_RSVD_63_20_SHIFT 20
680	#define VTD_BF_1_IRTE_RSVD_63_20_MASK UINT64_C(0xfffffffffff00000)
681	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_IRTE_, UINT64_C(0), UINT64_MAX,
682	(SID, SQ, SVT, RSVD_63_20));
683
684	/** IRTE: Qword 0 valid mask when EIME=1. */
685	#define VTD_IRTE_0_X2APIC_VALID_MASK ( VTD_BF_0_IRTE_P_MASK \| VTD_BF_0_IRTE_FPD_MASK \
686	\| VTD_BF_0_IRTE_DM_MASK \| VTD_BF_0_IRTE_RH_MASK \
687	\| VTD_BF_0_IRTE_TM_MASK \| VTD_BF_0_IRTE_DLM_MASK \
688	\| VTD_BF_0_IRTE_AVAIL_MASK \| VTD_BF_0_IRTE_IM_MASK \
689	\| VTD_BF_0_IRTE_V_MASK \| VTD_BF_0_IRTE_DST_MASK)
690	/** IRTE: Qword 0 valid mask when EIME=0. */
691	#define VTD_IRTE_0_XAPIC_VALID_MASK ( VTD_BF_0_IRTE_P_MASK \| VTD_BF_0_IRTE_FPD_MASK \
692	\| VTD_BF_0_IRTE_DM_MASK \| VTD_BF_0_IRTE_RH_MASK \
693	\| VTD_BF_0_IRTE_TM_MASK \| VTD_BF_0_IRTE_DLM_MASK \
694	\| VTD_BF_0_IRTE_AVAIL_MASK \| VTD_BF_0_IRTE_IM_MASK \
695	\| VTD_BF_0_IRTE_V_MASK \| VTD_BF_0_IRTE_DST_XAPIC_MASK)
696	/** IRTE: Qword 1 valid mask. */
697	#define VTD_IRTE_1_VALID_MASK ( VTD_BF_1_IRTE_SID_MASK \| VTD_BF_1_IRTE_SQ_MASK \
698	\| VTD_BF_1_IRTE_SVT_MASK)
699
700	/** Interrupt Remapping Table Entry (IRTE) for remapped interrupts. */
701	typedef struct VTD_IRTE_T
702	{
703	/** The qwords in the IRTE. */
704	uint64_t au64[2];
705	} VTD_IRTE_T;
706	/** Pointer to an IRTE. */
707	typedef VTD_IRTE_T *PVTD_IRTE_T;
708	/** Pointer to a const IRTE. */
709	typedef VTD_IRTE_T const *PCVTD_IRTE_T;
710
711	/** IRTE SVT: No validation required. */
712	#define VTD_IRTE_SVT_NONE 0
713	/** IRTE SVT: Validate using a mask derived from SID and SQT. */
714	#define VTD_IRTE_SVT_VALIDATE_MASK 1
715	/** IRTE SVT: Validate using Bus range in the SID. */
716	#define VTD_IRTE_SVT_VALIDATE_BUS_RANGE 2
717	/** IRTE SVT: Reserved. */
718	#define VTD_IRTE_SVT_VALIDATE_RSVD 3
719	/** @} */
720
721
722	/** @name Version Register (VER_REG).
723	* In accordance with the Intel spec.
724	* @{ */
725	/** Min: Minor Version Number. */
726	#define VTD_BF_VER_REG_MIN_SHIFT 0
727	#define VTD_BF_VER_REG_MIN_MASK UINT32_C(0x0000000f)
728	/** Max: Major Version Number. */
729	#define VTD_BF_VER_REG_MAX_SHIFT 4
730	#define VTD_BF_VER_REG_MAX_MASK UINT32_C(0x000000f0)
731	/** R: Reserved (bits 31:8). */
732	#define VTD_BF_VER_REG_RSVD_31_8_SHIFT 8
733	#define VTD_BF_VER_REG_RSVD_31_8_MASK UINT32_C(0xffffff00)
734	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_VER_REG_, UINT32_C(0), UINT32_MAX,
735	(MIN, MAX, RSVD_31_8));
736	/** RW: Read/write mask. */
737	#define VTD_VER_REG_RW_MASK UINT32_C(0)
738	/** @} */
739
740
741	/** @name Capability Register (CAP_REG).
742	* In accordance with the Intel spec.
743	* @{ */
744	/** ND: Number of domains supported. */
745	#define VTD_BF_CAP_REG_ND_SHIFT 0
746	#define VTD_BF_CAP_REG_ND_MASK UINT64_C(0x0000000000000007)
747	/** AFL: Advanced Fault Logging. */
748	#define VTD_BF_CAP_REG_AFL_SHIFT 3
749	#define VTD_BF_CAP_REG_AFL_MASK UINT64_C(0x0000000000000008)
750	/** RWBF: Required Write-Buffer Flushing. */
751	#define VTD_BF_CAP_REG_RWBF_SHIFT 4
752	#define VTD_BF_CAP_REG_RWBF_MASK UINT64_C(0x0000000000000010)
753	/** PLMR: Protected Low-Memory Region. */
754	#define VTD_BF_CAP_REG_PLMR_SHIFT 5
755	#define VTD_BF_CAP_REG_PLMR_MASK UINT64_C(0x0000000000000020)
756	/** PHMR: Protected High-Memory Region. */
757	#define VTD_BF_CAP_REG_PHMR_SHIFT 6
758	#define VTD_BF_CAP_REG_PHMR_MASK UINT64_C(0x0000000000000040)
759	/** CM: Caching Mode. */
760	#define VTD_BF_CAP_REG_CM_SHIFT 7
761	#define VTD_BF_CAP_REG_CM_MASK UINT64_C(0x0000000000000080)
762	/** SAGAW: Supported Adjusted Guest Address Widths. */
763	#define VTD_BF_CAP_REG_SAGAW_SHIFT 8
764	#define VTD_BF_CAP_REG_SAGAW_MASK UINT64_C(0x0000000000001f00)
765	/** R: Reserved (bits 15:13). */
766	#define VTD_BF_CAP_REG_RSVD_15_13_SHIFT 13
767	#define VTD_BF_CAP_REG_RSVD_15_13_MASK UINT64_C(0x000000000000e000)
768	/** MGAW: Maximum Guest Address Width. */
769	#define VTD_BF_CAP_REG_MGAW_SHIFT 16
770	#define VTD_BF_CAP_REG_MGAW_MASK UINT64_C(0x00000000003f0000)
771	/** ZLR: Zero Length Read. */
772	#define VTD_BF_CAP_REG_ZLR_SHIFT 22
773	#define VTD_BF_CAP_REG_ZLR_MASK UINT64_C(0x0000000000400000)
774	/** DEP: Deprecated MBZ. Reserved (bit 23). */
775	#define VTD_BF_CAP_REG_RSVD_23_SHIFT 23
776	#define VTD_BF_CAP_REG_RSVD_23_MASK UINT64_C(0x0000000000800000)
777	/** FRO: Fault-recording Register Offset. */
778	#define VTD_BF_CAP_REG_FRO_SHIFT 24
779	#define VTD_BF_CAP_REG_FRO_MASK UINT64_C(0x00000003ff000000)
780	/** SLLPS: Second Level Large Page Support. */
781	#define VTD_BF_CAP_REG_SLLPS_SHIFT 34
782	#define VTD_BF_CAP_REG_SLLPS_MASK UINT64_C(0x0000003c00000000)
783	/** R: Reserved (bit 38). */
784	#define VTD_BF_CAP_REG_RSVD_38_SHIFT 38
785	#define VTD_BF_CAP_REG_RSVD_38_MASK UINT64_C(0x0000004000000000)
786	/** PSI: Page Selective Invalidation. */
787	#define VTD_BF_CAP_REG_PSI_SHIFT 39
788	#define VTD_BF_CAP_REG_PSI_MASK UINT64_C(0x0000008000000000)
789	/** NFR: Number of Fault-recording Registers. */
790	#define VTD_BF_CAP_REG_NFR_SHIFT 40
791	#define VTD_BF_CAP_REG_NFR_MASK UINT64_C(0x0000ff0000000000)
792	/** MAMV: Maximum Address Mask Value. */
793	#define VTD_BF_CAP_REG_MAMV_SHIFT 48
794	#define VTD_BF_CAP_REG_MAMV_MASK UINT64_C(0x003f000000000000)
795	/** DWD: Write Draining. */
796	#define VTD_BF_CAP_REG_DWD_SHIFT 54
797	#define VTD_BF_CAP_REG_DWD_MASK UINT64_C(0x0040000000000000)
798	/** DRD: Read Draining. */
799	#define VTD_BF_CAP_REG_DRD_SHIFT 55
800	#define VTD_BF_CAP_REG_DRD_MASK UINT64_C(0x0080000000000000)
801	/** FL1GP: First Level 1 GB Page Support. */
802	#define VTD_BF_CAP_REG_FL1GP_SHIFT 56
803	#define VTD_BF_CAP_REG_FL1GP_MASK UINT64_C(0x0100000000000000)
804	/** R: Reserved (bits 58:57). */
805	#define VTD_BF_CAP_REG_RSVD_58_57_SHIFT 57
806	#define VTD_BF_CAP_REG_RSVD_58_57_MASK UINT64_C(0x0600000000000000)
807	/** PI: Posted Interrupt Support. */
808	#define VTD_BF_CAP_REG_PI_SHIFT 59
809	#define VTD_BF_CAP_REG_PI_MASK UINT64_C(0x0800000000000000)
810	/** FL5LP: First Level 5-level Paging Support. */
811	#define VTD_BF_CAP_REG_FL5LP_SHIFT 60
812	#define VTD_BF_CAP_REG_FL5LP_MASK UINT64_C(0x1000000000000000)
813	/** R: Reserved (bit 61). */
814	#define VTD_BF_CAP_REG_RSVD_61_SHIFT 61
815	#define VTD_BF_CAP_REG_RSVD_61_MASK UINT64_C(0x2000000000000000)
816	/** ESIRTPS: Enhanced Set Interrupt Root Table Pointer Support. */
817	#define VTD_BF_CAP_REG_ESIRTPS_SHIFT 62
818	#define VTD_BF_CAP_REG_ESIRTPS_MASK UINT64_C(0x4000000000000000)
819	/** : Enhanced Set Root Table Pointer Support. */
820	#define VTD_BF_CAP_REG_ESRTPS_SHIFT 63
821	#define VTD_BF_CAP_REG_ESRTPS_MASK UINT64_C(0x8000000000000000)
822	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_CAP_REG_, UINT64_C(0), UINT64_MAX,
823	(ND, AFL, RWBF, PLMR, PHMR, CM, SAGAW, RSVD_15_13, MGAW, ZLR, RSVD_23, FRO, SLLPS, RSVD_38, PSI, NFR,
824	MAMV, DWD, DRD, FL1GP, RSVD_58_57, PI, FL5LP, RSVD_61, ESIRTPS, ESRTPS));
825
826	/** RW: Read/write mask. */
827	#define VTD_CAP_REG_RW_MASK UINT64_C(0)
828	/** @} */
829
830
831	/** @name Extended Capability Register (ECAP_REG).
832	* In accordance with the Intel spec.
833	* @{ */
834	/** C: Page-walk Coherence. */
835	#define VTD_BF_ECAP_REG_C_SHIFT 0
836	#define VTD_BF_ECAP_REG_C_MASK UINT64_C(0x0000000000000001)
837	/** QI: Queued Invalidation Support. */
838	#define VTD_BF_ECAP_REG_QI_SHIFT 1
839	#define VTD_BF_ECAP_REG_QI_MASK UINT64_C(0x0000000000000002)
840	/** DT: Device-TLB Support. */
841	#define VTD_BF_ECAP_REG_DT_SHIFT 2
842	#define VTD_BF_ECAP_REG_DT_MASK UINT64_C(0x0000000000000004)
843	/** IR: Interrupt Remapping Support. */
844	#define VTD_BF_ECAP_REG_IR_SHIFT 3
845	#define VTD_BF_ECAP_REG_IR_MASK UINT64_C(0x0000000000000008)
846	/** EIM: Extended Interrupt Mode. */
847	#define VTD_BF_ECAP_REG_EIM_SHIFT 4
848	#define VTD_BF_ECAP_REG_EIM_MASK UINT64_C(0x0000000000000010)
849	/** DEP: Deprecated MBZ. Reserved (bit 5). */
850	#define VTD_BF_ECAP_REG_RSVD_5_SHIFT 5
851	#define VTD_BF_ECAP_REG_RSVD_5_MASK UINT64_C(0x0000000000000020)
852	/** PT: Pass Through. */
853	#define VTD_BF_ECAP_REG_PT_SHIFT 6
854	#define VTD_BF_ECAP_REG_PT_MASK UINT64_C(0x0000000000000040)
855	/** SC: Snoop Control. */
856	#define VTD_BF_ECAP_REG_SC_SHIFT 7
857	#define VTD_BF_ECAP_REG_SC_MASK UINT64_C(0x0000000000000080)
858	/** IRO: IOTLB Register Offset. */
859	#define VTD_BF_ECAP_REG_IRO_SHIFT 8
860	#define VTD_BF_ECAP_REG_IRO_MASK UINT64_C(0x000000000003ff00)
861	/** R: Reserved (bits 19:18). */
862	#define VTD_BF_ECAP_REG_RSVD_19_18_SHIFT 18
863	#define VTD_BF_ECAP_REG_RSVD_19_18_MASK UINT64_C(0x00000000000c0000)
864	/** MHMV: Maximum Handle Mask Value. */
865	#define VTD_BF_ECAP_REG_MHMV_SHIFT 20
866	#define VTD_BF_ECAP_REG_MHMV_MASK UINT64_C(0x0000000000f00000)
867	/** DEP: Deprecated MBZ. Reserved (bit 24). */
868	#define VTD_BF_ECAP_REG_RSVD_24_SHIFT 24
869	#define VTD_BF_ECAP_REG_RSVD_24_MASK UINT64_C(0x0000000001000000)
870	/** MTS: Memory Type Support. */
871	#define VTD_BF_ECAP_REG_MTS_SHIFT 25
872	#define VTD_BF_ECAP_REG_MTS_MASK UINT64_C(0x0000000002000000)
873	/** NEST: Nested Translation Support. */
874	#define VTD_BF_ECAP_REG_NEST_SHIFT 26
875	#define VTD_BF_ECAP_REG_NEST_MASK UINT64_C(0x0000000004000000)
876	/** R: Reserved (bit 27). */
877	#define VTD_BF_ECAP_REG_RSVD_27_SHIFT 27
878	#define VTD_BF_ECAP_REG_RSVD_27_MASK UINT64_C(0x0000000008000000)
879	/** DEP: Deprecated MBZ. Reserved (bit 28). */
880	#define VTD_BF_ECAP_REG_RSVD_28_SHIFT 28
881	#define VTD_BF_ECAP_REG_RSVD_28_MASK UINT64_C(0x0000000010000000)
882	/** PRS: Page Request Support. */
883	#define VTD_BF_ECAP_REG_PRS_SHIFT 29
884	#define VTD_BF_ECAP_REG_PRS_MASK UINT64_C(0x0000000020000000)
885	/** ERS: Execute Request Support. */
886	#define VTD_BF_ECAP_REG_ERS_SHIFT 30
887	#define VTD_BF_ECAP_REG_ERS_MASK UINT64_C(0x0000000040000000)
888	/** SRS: Supervisor Request Support. */
889	#define VTD_BF_ECAP_REG_SRS_SHIFT 31
890	#define VTD_BF_ECAP_REG_SRS_MASK UINT64_C(0x0000000080000000)
891	/** R: Reserved (bit 32). */
892	#define VTD_BF_ECAP_REG_RSVD_32_SHIFT 32
893	#define VTD_BF_ECAP_REG_RSVD_32_MASK UINT64_C(0x0000000100000000)
894	/** NWFS: No Write Flag Support. */
895	#define VTD_BF_ECAP_REG_NWFS_SHIFT 33
896	#define VTD_BF_ECAP_REG_NWFS_MASK UINT64_C(0x0000000200000000)
897	/** EAFS: Extended Accessed Flags Support. */
898	#define VTD_BF_ECAP_REG_EAFS_SHIFT 34
899	#define VTD_BF_ECAP_REG_EAFS_MASK UINT64_C(0x0000000400000000)
900	/** PSS: PASID Size Supported. */
901	#define VTD_BF_ECAP_REG_PSS_SHIFT 35
902	#define VTD_BF_ECAP_REG_PSS_MASK UINT64_C(0x000000f800000000)
903	/** PASID: Process Address Space ID Support. */
904	#define VTD_BF_ECAP_REG_PASID_SHIFT 40
905	#define VTD_BF_ECAP_REG_PASID_MASK UINT64_C(0x0000010000000000)
906	/** DIT: Device-TLB Invalidation Throttle. */
907	#define VTD_BF_ECAP_REG_DIT_SHIFT 41
908	#define VTD_BF_ECAP_REG_DIT_MASK UINT64_C(0x0000020000000000)
909	/** PDS: Page-request Drain Support. */
910	#define VTD_BF_ECAP_REG_PDS_SHIFT 42
911	#define VTD_BF_ECAP_REG_PDS_MASK UINT64_C(0x0000040000000000)
912	/** SMTS: Scalable-Mode Translation Support. */
913	#define VTD_BF_ECAP_REG_SMTS_SHIFT 43
914	#define VTD_BF_ECAP_REG_SMTS_MASK UINT64_C(0x0000080000000000)
915	/** VCS: Virtual Command Support. */
916	#define VTD_BF_ECAP_REG_VCS_SHIFT 44
917	#define VTD_BF_ECAP_REG_VCS_MASK UINT64_C(0x0000100000000000)
918	/** SLADS: Second-Level Accessed/Dirty Support. */
919	#define VTD_BF_ECAP_REG_SLADS_SHIFT 45
920	#define VTD_BF_ECAP_REG_SLADS_MASK UINT64_C(0x0000200000000000)
921	/** SLTS: Second-Level Translation Support. */
922	#define VTD_BF_ECAP_REG_SLTS_SHIFT 46
923	#define VTD_BF_ECAP_REG_SLTS_MASK UINT64_C(0x0000400000000000)
924	/** FLTS: First-Level Translation Support. */
925	#define VTD_BF_ECAP_REG_FLTS_SHIFT 47
926	#define VTD_BF_ECAP_REG_FLTS_MASK UINT64_C(0x0000800000000000)
927	/** SMPWCS: Scalable-Mode Page-Walk Coherency Support. */
928	#define VTD_BF_ECAP_REG_SMPWCS_SHIFT 48
929	#define VTD_BF_ECAP_REG_SMPWCS_MASK UINT64_C(0x0001000000000000)
930	/** RPS: RID-PASID Support. */
931	#define VTD_BF_ECAP_REG_RPS_SHIFT 49
932	#define VTD_BF_ECAP_REG_RPS_MASK UINT64_C(0x0002000000000000)
933	/** R: Reserved (bits 51:50). */
934	#define VTD_BF_ECAP_REG_RSVD_51_50_SHIFT 50
935	#define VTD_BF_ECAP_REG_RSVD_51_50_MASK UINT64_C(0x000c000000000000)
936	/** ADMS: Abort DMA Mode Support. */
937	#define VTD_BF_ECAP_REG_ADMS_SHIFT 52
938	#define VTD_BF_ECAP_REG_ADMS_MASK UINT64_C(0x0010000000000000)
939	/** RPRIVS: RID_PRIV Support. */
940	#define VTD_BF_ECAP_REG_RPRIVS_SHIFT 53
941	#define VTD_BF_ECAP_REG_RPRIVS_MASK UINT64_C(0x0020000000000000)
942	/** R: Reserved (bits 63:54). */
943	#define VTD_BF_ECAP_REG_RSVD_63_54_SHIFT 54
944	#define VTD_BF_ECAP_REG_RSVD_63_54_MASK UINT64_C(0xffc0000000000000)
945	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_ECAP_REG_, UINT64_C(0), UINT64_MAX,
946	(C, QI, DT, IR, EIM, RSVD_5, PT, SC, IRO, RSVD_19_18, MHMV, RSVD_24, MTS, NEST, RSVD_27, RSVD_28,
947	PRS, ERS, SRS, RSVD_32, NWFS, EAFS, PSS, PASID, DIT, PDS, SMTS, VCS, SLADS, SLTS, FLTS, SMPWCS, RPS,
948	RSVD_51_50, ADMS, RPRIVS, RSVD_63_54));
949
950	/** RW: Read/write mask. */
951	#define VTD_ECAP_REG_RW_MASK UINT64_C(0)
952	/** @} */
953
954
955	/** @name Global Command Register (GCMD_REG).
956	* In accordance with the Intel spec.
957	* @{ */
958	/** R: Reserved (bits 22:0). */
959	#define VTD_BF_GCMD_REG_RSVD_22_0_SHIFT 0
960	#define VTD_BF_GCMD_REG_RSVD_22_0_MASK UINT32_C(0x007fffff)
961	/** CFI: Compatibility Format Interrupt. */
962	#define VTD_BF_GCMD_REG_CFI_SHIFT 23
963	#define VTD_BF_GCMD_REG_CFI_MASK UINT32_C(0x00800000)
964	/** SIRTP: Set Interrupt Table Remap Pointer. */
965	#define VTD_BF_GCMD_REG_SIRTP_SHIFT 24
966	#define VTD_BF_GCMD_REG_SIRTP_MASK UINT32_C(0x01000000)
967	/** IRE: Interrupt Remap Enable. */
968	#define VTD_BF_GCMD_REG_IRE_SHIFT 25
969	#define VTD_BF_GCMD_REG_IRE_MASK UINT32_C(0x02000000)
970	/** QIE: Queued Invalidation Enable. */
971	#define VTD_BF_GCMD_REG_QIE_SHIFT 26
972	#define VTD_BF_GCMD_REG_QIE_MASK UINT32_C(0x04000000)
973	/** WBF: Write Buffer Flush. */
974	#define VTD_BF_GCMD_REG_WBF_SHIFT 27
975	#define VTD_BF_GCMD_REG_WBF_MASK UINT32_C(0x08000000)
976	/** EAFL: Enable Advance Fault Logging. */
977	#define VTD_BF_GCMD_REG_EAFL_SHIFT 28
978	#define VTD_BF_GCMD_REG_EAFL_MASK UINT32_C(0x10000000)
979	/** SFL: Set Fault Log. */
980	#define VTD_BF_GCMD_REG_SFL_SHIFT 29
981	#define VTD_BF_GCMD_REG_SFL_MASK UINT32_C(0x20000000)
982	/** SRTP: Set Root Table Pointer. */
983	#define VTD_BF_GCMD_REG_SRTP_SHIFT 30
984	#define VTD_BF_GCMD_REG_SRTP_MASK UINT32_C(0x40000000)
985	/** TE: Translation Enable. */
986	#define VTD_BF_GCMD_REG_TE_SHIFT 31
987	#define VTD_BF_GCMD_REG_TE_MASK UINT32_C(0x80000000)
988	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_GCMD_REG_, UINT32_C(0), UINT32_MAX,
989	(RSVD_22_0, CFI, SIRTP, IRE, QIE, WBF, EAFL, SFL, SRTP, TE));
990
991	/** RW: Read/write mask. */
992	#define VTD_GCMD_REG_RW_MASK UINT32_C(0xff800000)
993	/** @} */
994
995
996	/** @name Global Status Register (GSTS_REG).
997	* In accordance with the Intel spec.
998	* @{ */
999	/** R: Reserved (bits 22:0). */
1000	#define VTD_BF_GSTS_REG_RSVD_22_0_SHIFT 0
1001	#define VTD_BF_GSTS_REG_RSVD_22_0_MASK UINT32_C(0x007fffff)
1002	/** CFIS: Compatibility Format Interrupt Status. */
1003	#define VTD_BF_GSTS_REG_CFIS_SHIFT 23
1004	#define VTD_BF_GSTS_REG_CFIS_MASK UINT32_C(0x00800000)
1005	/** IRTPS: Interrupt Remapping Table Pointer Status. */
1006	#define VTD_BF_GSTS_REG_IRTPS_SHIFT 24
1007	#define VTD_BF_GSTS_REG_IRTPS_MASK UINT32_C(0x01000000)
1008	/** IRES: Interrupt Remapping Enable Status. */
1009	#define VTD_BF_GSTS_REG_IRES_SHIFT 25
1010	#define VTD_BF_GSTS_REG_IRES_MASK UINT32_C(0x02000000)
1011	/** QIES: Queued Invalidation Enable Status. */
1012	#define VTD_BF_GSTS_REG_QIES_SHIFT 26
1013	#define VTD_BF_GSTS_REG_QIES_MASK UINT32_C(0x04000000)
1014	/** WBFS: Write Buffer Flush Status. */
1015	#define VTD_BF_GSTS_REG_WBFS_SHIFT 27
1016	#define VTD_BF_GSTS_REG_WBFS_MASK UINT32_C(0x08000000)
1017	/** AFLS: Advanced Fault Logging Status. */
1018	#define VTD_BF_GSTS_REG_AFLS_SHIFT 28
1019	#define VTD_BF_GSTS_REG_AFLS_MASK UINT32_C(0x10000000)
1020	/** FLS: Fault Log Status. */
1021	#define VTD_BF_GSTS_REG_FLS_SHIFT 29
1022	#define VTD_BF_GSTS_REG_FLS_MASK UINT32_C(0x20000000)
1023	/** RTPS: Root Table Pointer Status. */
1024	#define VTD_BF_GSTS_REG_RTPS_SHIFT 30
1025	#define VTD_BF_GSTS_REG_RTPS_MASK UINT32_C(0x40000000)
1026	/** TES: Translation Enable Status. */
1027	#define VTD_BF_GSTS_REG_TES_SHIFT 31
1028	#define VTD_BF_GSTS_REG_TES_MASK UINT32_C(0x80000000)
1029	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_GSTS_REG_, UINT32_C(0), UINT32_MAX,
1030	(RSVD_22_0, CFIS, IRTPS, IRES, QIES, WBFS, AFLS, FLS, RTPS, TES));
1031
1032	/** RW: Read/write mask. */
1033	#define VTD_GSTS_REG_RW_MASK UINT32_C(0)
1034	/** @} */
1035
1036
1037	/** @name Root Table Address Register (RTADDR_REG).
1038	* In accordance with the Intel spec.
1039	* @{ */
1040	/** R: Reserved (bits 9:0). */
1041	#define VTD_BF_RTADDR_REG_RSVD_9_0_SHIFT 0
1042	#define VTD_BF_RTADDR_REG_RSVD_9_0_MASK UINT64_C(0x00000000000003ff)
1043	/** TTM: Translation Table Mode. */
1044	#define VTD_BF_RTADDR_REG_TTM_SHIFT 10
1045	#define VTD_BF_RTADDR_REG_TTM_MASK UINT64_C(0x0000000000000c00)
1046	/** RTA: Root Table Address. */
1047	#define VTD_BF_RTADDR_REG_RTA_SHIFT 12
1048	#define VTD_BF_RTADDR_REG_RTA_MASK UINT64_C(0xfffffffffffff000)
1049	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_RTADDR_REG_, UINT64_C(0), UINT64_MAX,
1050	(RSVD_9_0, TTM, RTA));
1051
1052	/** RW: Read/write mask. */
1053	#define VTD_RTADDR_REG_RW_MASK UINT64_C(0xfffffffffffffc00)
1054
1055	/** RTADDR_REG.TTM: Legacy mode. */
1056	#define VTD_TTM_LEGACY_MODE 0
1057	/** RTADDR_REG.TTM: Scalable mode. */
1058	#define VTD_TTM_SCALABLE_MODE 1
1059	/** RTADDR_REG.TTM: Reserved. */
1060	#define VTD_TTM_RSVD 2
1061	/** RTADDR_REG.TTM: Abort DMA mode. */
1062	#define VTD_TTM_ABORT_DMA_MODE 3
1063	/** @} */
1064
1065
1066	/** @name Context Command Register (CCMD_REG).
1067	* In accordance with the Intel spec.
1068	* @{ */
1069	/** DID: Domain-ID. */
1070	#define VTD_BF_CCMD_REG_DID_SHIFT 0
1071	#define VTD_BF_CCMD_REG_DID_MASK UINT64_C(0x000000000000ffff)
1072	/** SID: Source-ID. */
1073	#define VTD_BF_CCMD_REG_SID_SHIFT 16
1074	#define VTD_BF_CCMD_REG_SID_MASK UINT64_C(0x00000000ffff0000)
1075	/** FM: Function Mask. */
1076	#define VTD_BF_CCMD_REG_FM_SHIFT 32
1077	#define VTD_BF_CCMD_REG_FM_MASK UINT64_C(0x0000000300000000)
1078	/** R: Reserved (bits 58:34). */
1079	#define VTD_BF_CCMD_REG_RSVD_58_34_SHIFT 34
1080	#define VTD_BF_CCMD_REG_RSVD_58_34_MASK UINT64_C(0x07fffffc00000000)
1081	/** CAIG: Context Actual Invalidation Granularity. */
1082	#define VTD_BF_CCMD_REG_CAIG_SHIFT 59
1083	#define VTD_BF_CCMD_REG_CAIG_MASK UINT64_C(0x1800000000000000)
1084	/** CIRG: Context Invalidation Request Granularity. */
1085	#define VTD_BF_CCMD_REG_CIRG_SHIFT 61
1086	#define VTD_BF_CCMD_REG_CIRG_MASK UINT64_C(0x6000000000000000)
1087	/** ICC: Invalidation Context Cache. */
1088	#define VTD_BF_CCMD_REG_ICC_SHIFT 63
1089	#define VTD_BF_CCMD_REG_ICC_MASK UINT64_C(0x8000000000000000)
1090	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_CCMD_REG_, UINT64_C(0), UINT64_MAX,
1091	(DID, SID, FM, RSVD_58_34, CAIG, CIRG, ICC));
1092
1093	/** RW: Read/write mask. */
1094	#define VTD_CCMD_REG_RW_MASK ( VTD_BF_CCMD_REG_DID_MASK \| VTD_BF_CCMD_REG_SID_MASK \
1095	\| VTD_BF_CCMD_REG_FM_MASK \| VTD_BF_CCMD_REG_CIRG_MASK \
1096	\| VTD_BF_CCMD_REG_ICC_MASK)
1097	/** @} */
1098
1099
1100	/** @name IOTLB Invalidation Register (IOTLB_REG).
1101	* In accordance with the Intel spec.
1102	* @{ */
1103	/** R: Reserved (bits 31:0). */
1104	#define VTD_BF_IOTLB_REG_RSVD_31_0_SHIFT 0
1105	#define VTD_BF_IOTLB_REG_RSVD_31_0_MASK UINT64_C(0x00000000ffffffff)
1106	/** DID: Domain-ID. */
1107	#define VTD_BF_IOTLB_REG_DID_SHIFT 32
1108	#define VTD_BF_IOTLB_REG_DID_MASK UINT64_C(0x0000ffff00000000)
1109	/** DW: Draining Writes. */
1110	#define VTD_BF_IOTLB_REG_DW_SHIFT 48
1111	#define VTD_BF_IOTLB_REG_DW_MASK UINT64_C(0x0001000000000000)
1112	/** DR: Draining Reads. */
1113	#define VTD_BF_IOTLB_REG_DR_SHIFT 49
1114	#define VTD_BF_IOTLB_REG_DR_MASK UINT64_C(0x0002000000000000)
1115	/** R: Reserved (bits 56:50). */
1116	#define VTD_BF_IOTLB_REG_RSVD_56_50_SHIFT 50
1117	#define VTD_BF_IOTLB_REG_RSVD_56_50_MASK UINT64_C(0x01fc000000000000)
1118	/** IAIG: IOTLB Actual Invalidation Granularity. */
1119	#define VTD_BF_IOTLB_REG_IAIG_SHIFT 57
1120	#define VTD_BF_IOTLB_REG_IAIG_MASK UINT64_C(0x0600000000000000)
1121	/** R: Reserved (bit 59). */
1122	#define VTD_BF_IOTLB_REG_RSVD_59_SHIFT 59
1123	#define VTD_BF_IOTLB_REG_RSVD_59_MASK UINT64_C(0x0800000000000000)
1124	/** IIRG: IOTLB Invalidation Request Granularity. */
1125	#define VTD_BF_IOTLB_REG_IIRG_SHIFT 60
1126	#define VTD_BF_IOTLB_REG_IIRG_MASK UINT64_C(0x3000000000000000)
1127	/** R: Reserved (bit 62). */
1128	#define VTD_BF_IOTLB_REG_RSVD_62_SHIFT 62
1129	#define VTD_BF_IOTLB_REG_RSVD_62_MASK UINT64_C(0x4000000000000000)
1130	/** IVT: Invalidate IOTLB. */
1131	#define VTD_BF_IOTLB_REG_IVT_SHIFT 63
1132	#define VTD_BF_IOTLB_REG_IVT_MASK UINT64_C(0x8000000000000000)
1133	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IOTLB_REG_, UINT64_C(0), UINT64_MAX,
1134	(RSVD_31_0, DID, DW, DR, RSVD_56_50, IAIG, RSVD_59, IIRG, RSVD_62, IVT));
1135
1136	/** RW: Read/write mask. */
1137	#define VTD_IOTLB_REG_RW_MASK ( VTD_BF_IOTLB_REG_DID_MASK \| VTD_BF_IOTLB_REG_DW_MASK \
1138	\| VTD_BF_IOTLB_REG_DR_MASK \| VTD_BF_IOTLB_REG_IIRG_MASK \
1139	\| VTD_BF_IOTLB_REG_IVT_MASK)
1140	/** @} */
1141
1142
1143	/** @name Invalidate Address Register (IVA_REG).
1144	* In accordance with the Intel spec.
1145	* @{ */
1146	/** AM: Address Mask. */
1147	#define VTD_BF_IVA_REG_AM_SHIFT 0
1148	#define VTD_BF_IVA_REG_AM_MASK UINT64_C(0x000000000000003f)
1149	/** IH: Invalidation Hint. */
1150	#define VTD_BF_IVA_REG_IH_SHIFT 6
1151	#define VTD_BF_IVA_REG_IH_MASK UINT64_C(0x0000000000000040)
1152	/** R: Reserved (bits 11:7). */
1153	#define VTD_BF_IVA_REG_RSVD_11_7_SHIFT 7
1154	#define VTD_BF_IVA_REG_RSVD_11_7_MASK UINT64_C(0x0000000000000f80)
1155	/** ADDR: Address. */
1156	#define VTD_BF_IVA_REG_ADDR_SHIFT 12
1157	#define VTD_BF_IVA_REG_ADDR_MASK UINT64_C(0xfffffffffffff000)
1158	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IVA_REG_, UINT64_C(0), UINT64_MAX,
1159	(AM, IH, RSVD_11_7, ADDR));
1160
1161	/** RW: Read/write mask. */
1162	#define VTD_IVA_REG_RW_MASK ( VTD_BF_IVA_REG_AM_MASK \| VTD_BF_IVA_REG_IH_MASK \
1163	\| VTD_BF_IVA_REG_ADDR_MASK)
1164	/** @} */
1165
1166
1167	/** @name Fault Status Register (FSTS_REG).
1168	* In accordance with the Intel spec.
1169	* @{ */
1170	/** PFO: Primary Fault Overflow. */
1171	#define VTD_BF_FSTS_REG_PFO_SHIFT 0
1172	#define VTD_BF_FSTS_REG_PFO_MASK UINT32_C(0x00000001)
1173	/** PPF: Primary Pending Fault. */
1174	#define VTD_BF_FSTS_REG_PPF_SHIFT 1
1175	#define VTD_BF_FSTS_REG_PPF_MASK UINT32_C(0x00000002)
1176	/** AFO: Advanced Fault Overflow. */
1177	#define VTD_BF_FSTS_REG_AFO_SHIFT 2
1178	#define VTD_BF_FSTS_REG_AFO_MASK UINT32_C(0x00000004)
1179	/** APF: Advanced Pending Fault. */
1180	#define VTD_BF_FSTS_REG_APF_SHIFT 3
1181	#define VTD_BF_FSTS_REG_APF_MASK UINT32_C(0x00000008)
1182	/** IQE: Invalidation Queue Error. */
1183	#define VTD_BF_FSTS_REG_IQE_SHIFT 4
1184	#define VTD_BF_FSTS_REG_IQE_MASK UINT32_C(0x00000010)
1185	/** ICE: Invalidation Completion Error. */
1186	#define VTD_BF_FSTS_REG_ICE_SHIFT 5
1187	#define VTD_BF_FSTS_REG_ICE_MASK UINT32_C(0x00000020)
1188	/** ITE: Invalidation Timeout Error. */
1189	#define VTD_BF_FSTS_REG_ITE_SHIFT 6
1190	#define VTD_BF_FSTS_REG_ITE_MASK UINT32_C(0x00000040)
1191	/** DEP: Deprecated MBZ. Reserved (bit 7). */
1192	#define VTD_BF_FSTS_REG_RSVD_7_SHIFT 7
1193	#define VTD_BF_FSTS_REG_RSVD_7_MASK UINT32_C(0x00000080)
1194	/** FRI: Fault Record Index. */
1195	#define VTD_BF_FSTS_REG_FRI_SHIFT 8
1196	#define VTD_BF_FSTS_REG_FRI_MASK UINT32_C(0x0000ff00)
1197	/** R: Reserved (bits 31:16). */
1198	#define VTD_BF_FSTS_REG_RSVD_31_16_SHIFT 16
1199	#define VTD_BF_FSTS_REG_RSVD_31_16_MASK UINT32_C(0xffff0000)
1200	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_FSTS_REG_, UINT32_C(0), UINT32_MAX,
1201	(PFO, PPF, AFO, APF, IQE, ICE, ITE, RSVD_7, FRI, RSVD_31_16));
1202
1203	/** RW: Read/write mask. */
1204	#define VTD_FSTS_REG_RW_MASK ( VTD_BF_FSTS_REG_PFO_MASK \| VTD_BF_FSTS_REG_AFO_MASK \
1205	\| VTD_BF_FSTS_REG_APF_MASK \| VTD_BF_FSTS_REG_IQE_MASK \
1206	\| VTD_BF_FSTS_REG_ICE_MASK \| VTD_BF_FSTS_REG_ITE_MASK)
1207	/** RW1C: Read-only-status, Write-1-to-clear status mask. */
1208	#define VTD_FSTS_REG_RW1C_MASK ( VTD_BF_FSTS_REG_PFO_MASK \| VTD_BF_FSTS_REG_AFO_MASK \
1209	\| VTD_BF_FSTS_REG_APF_MASK \| VTD_BF_FSTS_REG_IQE_MASK \
1210	\| VTD_BF_FSTS_REG_ICE_MASK \| VTD_BF_FSTS_REG_ITE_MASK)
1211	/** @} */
1212
1213
1214	/** @name Fault Event Control Register (FECTL_REG).
1215	* In accordance with the Intel spec.
1216	* @{ */
1217	/** R: Reserved (bits 29:0). */
1218	#define VTD_BF_FECTL_REG_RSVD_29_0_SHIFT 0
1219	#define VTD_BF_FECTL_REG_RSVD_29_0_MASK UINT32_C(0x3fffffff)
1220	/** IP: Interrupt Pending. */
1221	#define VTD_BF_FECTL_REG_IP_SHIFT 30
1222	#define VTD_BF_FECTL_REG_IP_MASK UINT32_C(0x40000000)
1223	/** IM: Interrupt Mask. */
1224	#define VTD_BF_FECTL_REG_IM_SHIFT 31
1225	#define VTD_BF_FECTL_REG_IM_MASK UINT32_C(0x80000000)
1226	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_FECTL_REG_, UINT32_C(0), UINT32_MAX,
1227	(RSVD_29_0, IP, IM));
1228
1229	/** RW: Read/write mask. */
1230	#define VTD_FECTL_REG_RW_MASK VTD_BF_FECTL_REG_IM_MASK
1231	/** @} */
1232
1233
1234	/** @name Fault Event Data Register (FEDATA_REG).
1235	* In accordance with the Intel spec.
1236	* @{ */
1237	/** IMD: Interrupt Message Data. */
1238	#define VTD_BF_FEDATA_REG_IMD_SHIFT 0
1239	#define VTD_BF_FEDATA_REG_IMD_MASK UINT32_C(0x0000ffff)
1240	/** R: Reserved (bits 31:16). VT-d specs. prior to 2021 had EIMD here. */
1241	#define VTD_BF_FEDATA_REG_RSVD_31_16_SHIFT 16
1242	#define VTD_BF_FEDATA_REG_RSVD_31_16_MASK UINT32_C(0xffff0000)
1243	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_FEDATA_REG_, UINT32_C(0), UINT32_MAX,
1244	(IMD, RSVD_31_16));
1245
1246	/** RW: Read/write mask. */
1247	#define VTD_FEDATA_REG_RW_MASK VTD_BF_FEDATA_REG_IMD_MASK
1248	/** @} */
1249
1250
1251	/** @name Fault Event Address Register (FEADDR_REG).
1252	* In accordance with the Intel spec.
1253	* @{ */
1254	/** R: Reserved (bits 1:0). */
1255	#define VTD_BF_FEADDR_REG_RSVD_1_0_SHIFT 0
1256	#define VTD_BF_FEADDR_REG_RSVD_1_0_MASK UINT32_C(0x00000003)
1257	/** MA: Message Address. */
1258	#define VTD_BF_FEADDR_REG_MA_SHIFT 2
1259	#define VTD_BF_FEADDR_REG_MA_MASK UINT32_C(0xfffffffc)
1260	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_FEADDR_REG_, UINT32_C(0), UINT32_MAX,
1261	(RSVD_1_0, MA));
1262
1263	/** RW: Read/write mask. */
1264	#define VTD_FEADDR_REG_RW_MASK VTD_BF_FEADDR_REG_MA_MASK
1265	/** @} */
1266
1267
1268	/** @name Fault Event Upper Address Register (FEUADDR_REG).
1269	* In accordance with the Intel spec.
1270	* @{ */
1271	/** MUA: Message Upper Address. */
1272	#define VTD_BF_FEUADDR_REG_MA_SHIFT 0
1273	#define VTD_BF_FEUADDR_REG_MA_MASK UINT32_C(0xffffffff)
1274
1275	/** RW: Read/write mask. */
1276	#define VTD_FEUADDR_REG_RW_MASK VTD_BF_FEUADDR_REG_MA_MASK
1277	/** @} */
1278
1279
1280	/** @name Fault Recording Register (FRCD_REG).
1281	* In accordance with the Intel spec.
1282	* @{ */
1283	/** R: Reserved (bits 11:0). */
1284	#define VTD_BF_0_FRCD_REG_RSVD_11_0_SHIFT 0
1285	#define VTD_BF_0_FRCD_REG_RSVD_11_0_MASK UINT64_C(0x0000000000000fff)
1286	/** FI: Fault Info. */
1287	#define VTD_BF_0_FRCD_REG_FI_SHIFT 12
1288	#define VTD_BF_0_FRCD_REG_FI_MASK UINT64_C(0xfffffffffffff000)
1289	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_FRCD_REG_, UINT64_C(0), UINT64_MAX,
1290	(RSVD_11_0, FI));
1291
1292	/** SID: Source Identifier. */
1293	#define VTD_BF_1_FRCD_REG_SID_SHIFT 0
1294	#define VTD_BF_1_FRCD_REG_SID_MASK UINT64_C(0x000000000000ffff)
1295	/** R: Reserved (bits 27:16). */
1296	#define VTD_BF_1_FRCD_REG_RSVD_27_16_SHIFT 16
1297	#define VTD_BF_1_FRCD_REG_RSVD_27_16_MASK UINT64_C(0x000000000fff0000)
1298	/** T2: Type bit 2. */
1299	#define VTD_BF_1_FRCD_REG_T2_SHIFT 28
1300	#define VTD_BF_1_FRCD_REG_T2_MASK UINT64_C(0x0000000010000000)
1301	/** PRIV: Privilege Mode. */
1302	#define VTD_BF_1_FRCD_REG_PRIV_SHIFT 29
1303	#define VTD_BF_1_FRCD_REG_PRIV_MASK UINT64_C(0x0000000020000000)
1304	/** EXE: Execute Permission Requested. */
1305	#define VTD_BF_1_FRCD_REG_EXE_SHIFT 30
1306	#define VTD_BF_1_FRCD_REG_EXE_MASK UINT64_C(0x0000000040000000)
1307	/** PP: PASID Present. */
1308	#define VTD_BF_1_FRCD_REG_PP_SHIFT 31
1309	#define VTD_BF_1_FRCD_REG_PP_MASK UINT64_C(0x0000000080000000)
1310	/** FR: Fault Reason. */
1311	#define VTD_BF_1_FRCD_REG_FR_SHIFT 32
1312	#define VTD_BF_1_FRCD_REG_FR_MASK UINT64_C(0x000000ff00000000)
1313	/** PV: PASID Value. */
1314	#define VTD_BF_1_FRCD_REG_PV_SHIFT 40
1315	#define VTD_BF_1_FRCD_REG_PV_MASK UINT64_C(0x0fffff0000000000)
1316	/** AT: Address Type. */
1317	#define VTD_BF_1_FRCD_REG_AT_SHIFT 60
1318	#define VTD_BF_1_FRCD_REG_AT_MASK UINT64_C(0x3000000000000000)
1319	/** T1: Type bit 1. */
1320	#define VTD_BF_1_FRCD_REG_T1_SHIFT 62
1321	#define VTD_BF_1_FRCD_REG_T1_MASK UINT64_C(0x4000000000000000)
1322	/** F: Fault. */
1323	#define VTD_BF_1_FRCD_REG_F_SHIFT 63
1324	#define VTD_BF_1_FRCD_REG_F_MASK UINT64_C(0x8000000000000000)
1325	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_FRCD_REG_, UINT64_C(0), UINT64_MAX,
1326	(SID, RSVD_27_16, T2, PRIV, EXE, PP, FR, PV, AT, T1, F));
1327
1328	/** RW: Read/write mask. */
1329	#define VTD_FRCD_REG_LO_RW_MASK UINT64_C(0)
1330	#define VTD_FRCD_REG_HI_RW_MASK VTD_BF_1_FRCD_REG_F_MASK
1331	/** RW1C: Read-only-status, Write-1-to-clear status mask. */
1332	#define VTD_FRCD_REG_LO_RW1C_MASK UINT64_C(0)
1333	#define VTD_FRCD_REG_HI_RW1C_MASK VTD_BF_1_FRCD_REG_F_MASK
1334	/** @} */
1335
1336
1337	/** @name Advanced Fault Log Register (AFLOG_REG).
1338	* In accordance with the Intel spec.
1339	* @{ */
1340	/** R: Reserved (bits 8:0). */
1341	#define VTD_BF_0_AFLOG_REG_RSVD_8_0_SHIFT 0
1342	#define VTD_BF_0_AFLOG_REG_RSVD_8_0_MASK UINT64_C(0x00000000000001ff)
1343	/** FLS: Fault Log Size. */
1344	#define VTD_BF_0_AFLOG_REG_FLS_SHIFT 9
1345	#define VTD_BF_0_AFLOG_REG_FLS_MASK UINT64_C(0x0000000000000e00)
1346	/** FLA: Fault Log Address. */
1347	#define VTD_BF_0_AFLOG_REG_FLA_SHIFT 12
1348	#define VTD_BF_0_AFLOG_REG_FLA_MASK UINT64_C(0xfffffffffffff000)
1349	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_AFLOG_REG_, UINT64_C(0), UINT64_MAX,
1350	(RSVD_8_0, FLS, FLA));
1351
1352	/** RW: Read/write mask. */
1353	#define VTD_AFLOG_REG_RW_MASK (VTD_BF_0_AFLOG_REG_FLS_MASK \| VTD_BF_0_AFLOG_REG_FLA_MASK)
1354	/** @} */
1355
1356
1357	/** @name Protected Memory Enable Register (PMEN_REG).
1358	* In accordance with the Intel spec.
1359	* @{ */
1360	/** PRS: Protected Region Status. */
1361	#define VTD_BF_PMEN_REG_PRS_SHIFT 0
1362	#define VTD_BF_PMEN_REG_PRS_MASK UINT32_C(0x00000001)
1363	/** R: Reserved (bits 30:1). */
1364	#define VTD_BF_PMEN_REG_RSVD_30_1_SHIFT 1
1365	#define VTD_BF_PMEN_REG_RSVD_30_1_MASK UINT32_C(0x7ffffffe)
1366	/** EPM: Enable Protected Memory. */
1367	#define VTD_BF_PMEN_REG_EPM_SHIFT 31
1368	#define VTD_BF_PMEN_REG_EPM_MASK UINT32_C(0x80000000)
1369	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_PMEN_REG_, UINT32_C(0), UINT32_MAX,
1370	(PRS, RSVD_30_1, EPM));
1371
1372	/** RW: Read/write mask. */
1373	#define VTD_PMEN_REG_RW_MASK VTD_BF_PMEN_REG_EPM_MASK
1374	/** @} */
1375
1376
1377	/** @name Invalidation Queue Head Register (IQH_REG).
1378	* In accordance with the Intel spec.
1379	* @{ */
1380	/** R: Reserved (bits 3:0). */
1381	#define VTD_BF_IQH_REG_RSVD_3_0_SHIFT 0
1382	#define VTD_BF_IQH_REG_RSVD_3_0_MASK UINT64_C(0x000000000000000f)
1383	/** QH: Queue Head. */
1384	#define VTD_BF_IQH_REG_QH_SHIFT 4
1385	#define VTD_BF_IQH_REG_QH_MASK UINT64_C(0x000000000007fff0)
1386	/** R: Reserved (bits 63:19). */
1387	#define VTD_BF_IQH_REG_RSVD_63_19_SHIFT 19
1388	#define VTD_BF_IQH_REG_RSVD_63_19_MASK UINT64_C(0xfffffffffff80000)
1389	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IQH_REG_, UINT64_C(0), UINT64_MAX,
1390	(RSVD_3_0, QH, RSVD_63_19));
1391
1392	/** RW: Read/write mask. */
1393	#define VTD_IQH_REG_RW_MASK UINT64_C(0x0)
1394	/** @} */
1395
1396
1397	/** @name Invalidation Queue Tail Register (IQT_REG).
1398	* In accordance with the Intel spec.
1399	* @{ */
1400	/** R: Reserved (bits 3:0). */
1401	#define VTD_BF_IQT_REG_RSVD_3_0_SHIFT 0
1402	#define VTD_BF_IQT_REG_RSVD_3_0_MASK UINT64_C(0x000000000000000f)
1403	/** QH: Queue Tail. */
1404	#define VTD_BF_IQT_REG_QT_SHIFT 4
1405	#define VTD_BF_IQT_REG_QT_MASK UINT64_C(0x000000000007fff0)
1406	/** R: Reserved (bits 63:19). */
1407	#define VTD_BF_IQT_REG_RSVD_63_19_SHIFT 19
1408	#define VTD_BF_IQT_REG_RSVD_63_19_MASK UINT64_C(0xfffffffffff80000)
1409	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IQT_REG_, UINT64_C(0), UINT64_MAX,
1410	(RSVD_3_0, QT, RSVD_63_19));
1411
1412	/** RW: Read/write mask. */
1413	#define VTD_IQT_REG_RW_MASK VTD_BF_IQT_REG_QT_MASK
1414	/** @} */
1415
1416
1417	/** @name Invalidation Queue Address Register (IQA_REG).
1418	* In accordance with the Intel spec.
1419	* @{ */
1420	/** QS: Queue Size. */
1421	#define VTD_BF_IQA_REG_QS_SHIFT 0
1422	#define VTD_BF_IQA_REG_QS_MASK UINT64_C(0x0000000000000007)
1423	/** R: Reserved (bits 10:3). */
1424	#define VTD_BF_IQA_REG_RSVD_10_3_SHIFT 3
1425	#define VTD_BF_IQA_REG_RSVD_10_3_MASK UINT64_C(0x00000000000007f8)
1426	/** DW: Descriptor Width. */
1427	#define VTD_BF_IQA_REG_DW_SHIFT 11
1428	#define VTD_BF_IQA_REG_DW_MASK UINT64_C(0x0000000000000800)
1429	/** IQA: Invalidation Queue Base Address. */
1430	#define VTD_BF_IQA_REG_IQA_SHIFT 12
1431	#define VTD_BF_IQA_REG_IQA_MASK UINT64_C(0xfffffffffffff000)
1432	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IQA_REG_, UINT64_C(0), UINT64_MAX,
1433	(QS, RSVD_10_3, DW, IQA));
1434
1435	/** RW: Read/write mask. */
1436	#define VTD_IQA_REG_RW_MASK ( VTD_BF_IQA_REG_QS_MASK \| VTD_BF_IQA_REG_DW_MASK \
1437	\| VTD_BF_IQA_REG_IQA_MASK)
1438	/** DW: 128-bit descriptor. */
1439	#define VTD_IQA_REG_DW_128_BIT 0
1440	/** DW: 256-bit descriptor. */
1441	#define VTD_IQA_REG_DW_256_BIT 1
1442	/** @} */
1443
1444
1445	/** @name Invalidation Completion Status Register (ICS_REG).
1446	* In accordance with the Intel spec.
1447	* @{ */
1448	/** IWC: Invalidation Wait Descriptor Complete. */
1449	#define VTD_BF_ICS_REG_IWC_SHIFT 0
1450	#define VTD_BF_ICS_REG_IWC_MASK UINT32_C(0x00000001)
1451	/** R: Reserved (bits 31:1). */
1452	#define VTD_BF_ICS_REG_RSVD_31_1_SHIFT 1
1453	#define VTD_BF_ICS_REG_RSVD_31_1_MASK UINT32_C(0xfffffffe)
1454	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_ICS_REG_, UINT32_C(0), UINT32_MAX,
1455	(IWC, RSVD_31_1));
1456
1457	/** RW: Read/write mask. */
1458	#define VTD_ICS_REG_RW_MASK VTD_BF_ICS_REG_IWC_MASK
1459	/** RW1C: Read-only-status, Write-1-to-clear status mask. */
1460	#define VTD_ICS_REG_RW1C_MASK VTD_BF_ICS_REG_IWC_MASK
1461	/** @} */
1462
1463
1464	/** @name Invalidation Event Control Register (IECTL_REG).
1465	* In accordance with the Intel spec.
1466	* @{ */
1467	/** R: Reserved (bits 29:0). */
1468	#define VTD_BF_IECTL_REG_RSVD_29_0_SHIFT 0
1469	#define VTD_BF_IECTL_REG_RSVD_29_0_MASK UINT32_C(0x3fffffff)
1470	/** IP: Interrupt Pending. */
1471	#define VTD_BF_IECTL_REG_IP_SHIFT 30
1472	#define VTD_BF_IECTL_REG_IP_MASK UINT32_C(0x40000000)
1473	/** IM: Interrupt Mask. */
1474	#define VTD_BF_IECTL_REG_IM_SHIFT 31
1475	#define VTD_BF_IECTL_REG_IM_MASK UINT32_C(0x80000000)
1476	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IECTL_REG_, UINT32_C(0), UINT32_MAX,
1477	(RSVD_29_0, IP, IM));
1478
1479	/** RW: Read/write mask. */
1480	#define VTD_IECTL_REG_RW_MASK VTD_BF_IECTL_REG_IM_MASK
1481	/** @} */
1482
1483
1484	/** @name Invalidation Event Data Register (IEDATA_REG).
1485	* In accordance with the Intel spec.
1486	* @{ */
1487	/** IMD: Interrupt Message Data. */
1488	#define VTD_BF_IEDATA_REG_IMD_SHIFT 0
1489	#define VTD_BF_IEDATA_REG_IMD_MASK UINT32_C(0x0000ffff)
1490	/** R: Reserved (bits 31:16). VT-d specs. prior to 2021 had EIMD here. */
1491	#define VTD_BF_IEDATA_REG_RSVD_31_16_SHIFT 16
1492	#define VTD_BF_IEDATA_REG_RSVD_31_16_MASK UINT32_C(0xffff0000)
1493	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IEDATA_REG_, UINT32_C(0), UINT32_MAX,
1494	(IMD, RSVD_31_16));
1495
1496	/** RW: Read/write mask. */
1497	#define VTD_IEDATA_REG_RW_MASK VTD_BF_IEDATA_REG_IMD_MASK
1498	/** @} */
1499
1500
1501	/** @name Invalidation Event Address Register (IEADDR_REG).
1502	* In accordance with the Intel spec.
1503	* @{ */
1504	/** R: Reserved (bits 1:0). */
1505	#define VTD_BF_IEADDR_REG_RSVD_1_0_SHIFT 0
1506	#define VTD_BF_IEADDR_REG_RSVD_1_0_MASK UINT32_C(0x00000003)
1507	/** MA: Message Address. */
1508	#define VTD_BF_IEADDR_REG_MA_SHIFT 2
1509	#define VTD_BF_IEADDR_REG_MA_MASK UINT32_C(0xfffffffc)
1510	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IEADDR_REG_, UINT32_C(0), UINT32_MAX,
1511	(RSVD_1_0, MA));
1512
1513	/** RW: Read/write mask. */
1514	#define VTD_IEADDR_REG_RW_MASK VTD_BF_IEADDR_REG_MA_MASK
1515	/** @} */
1516
1517
1518	/** @name Invalidation Event Upper Address Register (IEUADDR_REG).
1519	* @{ */
1520	/** MUA: Message Upper Address. */
1521	#define VTD_BF_IEUADDR_REG_MUA_SHIFT 0
1522	#define VTD_BF_IEUADDR_REG_MUA_MASK UINT32_C(0xffffffff)
1523
1524	/** RW: Read/write mask. */
1525	#define VTD_IEUADDR_REG_RW_MASK VTD_BF_IEUADDR_REG_MUA_MASK
1526	/** @} */
1527
1528
1529	/** @name Invalidation Queue Error Record Register (IQERCD_REG).
1530	* In accordance with the Intel spec.
1531	* @{ */
1532	/** IQEI: Invalidation Queue Error Info. */
1533	#define VTD_BF_IQERCD_REG_IQEI_SHIFT 0
1534	#define VTD_BF_IQERCD_REG_IQEI_MASK UINT64_C(0x000000000000000f)
1535	/** R: Reserved (bits 31:4). */
1536	#define VTD_BF_IQERCD_REG_RSVD_31_4_SHIFT 4
1537	#define VTD_BF_IQERCD_REG_RSVD_31_4_MASK UINT64_C(0x00000000fffffff0)
1538	/** ITESID: Invalidation Timeout Error Source Identifier. */
1539	#define VTD_BF_IQERCD_REG_ITESID_SHIFT 32
1540	#define VTD_BF_IQERCD_REG_ITESID_MASK UINT64_C(0x0000ffff00000000)
1541	/** ICESID: Invalidation Completion Error Source Identifier. */
1542	#define VTD_BF_IQERCD_REG_ICESID_SHIFT 48
1543	#define VTD_BF_IQERCD_REG_ICESID_MASK UINT64_C(0xffff000000000000)
1544	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IQERCD_REG_, UINT64_C(0), UINT64_MAX,
1545	(IQEI, RSVD_31_4, ITESID, ICESID));
1546
1547	/** RW: Read/write mask. */
1548	#define VTD_IQERCD_REG_RW_MASK UINT64_C(0)
1549
1550	/** Invalidation Queue Error Information. */
1551	typedef enum VTD_IQEI_T
1552	{
1553	kIqei_InfoNotAvailable = 0,
1554	kIqei_InvalidTailPointer,
1555	kIqei_FetchDescriptorError,
1556	kIqei_InvalidDescriptorType,
1557	kIqei_RsvdFieldViolation,
1558	kIqei_InvalidDescriptorWidth,
1559	kIqei_QueueTailNotAligned,
1560	kIqei_InvalidTtm
1561	} VTD_IQEI_T;
1562	/** @} */
1563
1564
1565	/** @name Interrupt Remapping Table Address Register (IRTA_REG).
1566	* In accordance with the Intel spec.
1567	* @{ */
1568	/** S: Size. */
1569	#define VTD_BF_IRTA_REG_S_SHIFT 0
1570	#define VTD_BF_IRTA_REG_S_MASK UINT64_C(0x000000000000000f)
1571	/** R: Reserved (bits 10:4). */
1572	#define VTD_BF_IRTA_REG_RSVD_10_4_SHIFT 4
1573	#define VTD_BF_IRTA_REG_RSVD_10_4_MASK UINT64_C(0x00000000000007f0)
1574	/** EIME: Extended Interrupt Mode Enable. */
1575	#define VTD_BF_IRTA_REG_EIME_SHIFT 11
1576	#define VTD_BF_IRTA_REG_EIME_MASK UINT64_C(0x0000000000000800)
1577	/** IRTA: Interrupt Remapping Table Address. */
1578	#define VTD_BF_IRTA_REG_IRTA_SHIFT 12
1579	#define VTD_BF_IRTA_REG_IRTA_MASK UINT64_C(0xfffffffffffff000)
1580	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IRTA_REG_, UINT64_C(0), UINT64_MAX,
1581	(S, RSVD_10_4, EIME, IRTA));
1582
1583	/** RW: Read/write mask. */
1584	#define VTD_IRTA_REG_RW_MASK ( VTD_BF_IRTA_REG_S_MASK \| VTD_BF_IRTA_REG_EIME_MASK \
1585	\| VTD_BF_IRTA_REG_IRTA_MASK)
1586	/** IRTA_REG: Get number of interrupt entries. */
1587	#define VTD_IRTA_REG_GET_ENTRIES(a) (UINT32_C(1) << (1 + ((a) & VTD_BF_IRTA_REG_S_MASK)))
1588	/** @} */
1589
1590
1591	/** @name Page Request Queue Head Register (PQH_REG).
1592	* In accordance with the Intel spec.
1593	* @{ */
1594	/** R: Reserved (bits 4:0). */
1595	#define VTD_BF_PQH_REG_RSVD_4_0_SHIFT 0
1596	#define VTD_BF_PQH_REG_RSVD_4_0_MASK UINT64_C(0x000000000000001f)
1597	/** PQH: Page Queue Head. */
1598	#define VTD_BF_PQH_REG_PQH_SHIFT 5
1599	#define VTD_BF_PQH_REG_PQH_MASK UINT64_C(0x000000000007ffe0)
1600	/** R: Reserved (bits 63:19). */
1601	#define VTD_BF_PQH_REG_RSVD_63_19_SHIFT 19
1602	#define VTD_BF_PQH_REG_RSVD_63_19_MASK UINT64_C(0xfffffffffff80000)
1603	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_PQH_REG_, UINT64_C(0), UINT64_MAX,
1604	(RSVD_4_0, PQH, RSVD_63_19));
1605
1606	/** RW: Read/write mask. */
1607	#define VTD_PQH_REG_RW_MASK VTD_BF_PQH_REG_PQH_MASK
1608	/** @} */
1609
1610
1611	/** @name Page Request Queue Tail Register (PQT_REG).
1612	* In accordance with the Intel spec.
1613	* @{ */
1614	/** R: Reserved (bits 4:0). */
1615	#define VTD_BF_PQT_REG_RSVD_4_0_SHIFT 0
1616	#define VTD_BF_PQT_REG_RSVD_4_0_MASK UINT64_C(0x000000000000001f)
1617	/** PQT: Page Queue Tail. */
1618	#define VTD_BF_PQT_REG_PQT_SHIFT 5
1619	#define VTD_BF_PQT_REG_PQT_MASK UINT64_C(0x000000000007ffe0)
1620	/** R: Reserved (bits 63:19). */
1621	#define VTD_BF_PQT_REG_RSVD_63_19_SHIFT 19
1622	#define VTD_BF_PQT_REG_RSVD_63_19_MASK UINT64_C(0xfffffffffff80000)
1623	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_PQT_REG_, UINT64_C(0), UINT64_MAX,
1624	(RSVD_4_0, PQT, RSVD_63_19));
1625
1626	/** RW: Read/write mask. */
1627	#define VTD_PQT_REG_RW_MASK VTD_BF_PQT_REG_PQT_MASK
1628	/** @} */
1629
1630
1631	/** @name Page Request Queue Address Register (PQA_REG).
1632	* In accordance with the Intel spec.
1633	* @{ */
1634	/** PQS: Page Queue Size. */
1635	#define VTD_BF_PQA_REG_PQS_SHIFT 0
1636	#define VTD_BF_PQA_REG_PQS_MASK UINT64_C(0x0000000000000007)
1637	/** R: Reserved bits (11:3). */
1638	#define VTD_BF_PQA_REG_RSVD_11_3_SHIFT 3
1639	#define VTD_BF_PQA_REG_RSVD_11_3_MASK UINT64_C(0x0000000000000ff8)
1640	/** PQA: Page Request Queue Base Address. */
1641	#define VTD_BF_PQA_REG_PQA_SHIFT 12
1642	#define VTD_BF_PQA_REG_PQA_MASK UINT64_C(0xfffffffffffff000)
1643	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_PQA_REG_, UINT64_C(0), UINT64_MAX,
1644	(PQS, RSVD_11_3, PQA));
1645
1646	/** RW: Read/write mask. */
1647	#define VTD_PQA_REG_RW_MASK (VTD_BF_PQA_REG_PQS_MASK \| VTD_BF_PQA_REG_PQA_MASK)
1648	/** @} */
1649
1650
1651	/** @name Page Request Status Register (PRS_REG).
1652	* In accordance with the Intel spec.
1653	* @{ */
1654	/** PPR: Pending Page Request. */
1655	#define VTD_BF_PRS_REG_PPR_SHIFT 0
1656	#define VTD_BF_PRS_REG_PPR_MASK UINT64_C(0x00000001)
1657	/** PRO: Page Request Overflow. */
1658	#define VTD_BF_PRS_REG_PRO_SHIFT 1
1659	#define VTD_BF_PRS_REG_PRO_MASK UINT64_C(0x00000002)
1660	/** R: Reserved (bits 31:2). */
1661	#define VTD_BF_PRS_REG_RSVD_31_2_SHIFT 2
1662	#define VTD_BF_PRS_REG_RSVD_31_2_MASK UINT64_C(0xfffffffc)
1663	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_PRS_REG_, UINT32_C(0), UINT32_MAX,
1664	(PPR, PRO, RSVD_31_2));
1665
1666	/** RW: Read/write mask. */
1667	#define VTD_PRS_REG_RW_MASK (VTD_BF_PRS_REG_PPR_MASK \| VTD_BF_PRS_REG_PRO_MASK)
1668	/** RW1C: Read-only-status, Write-1-to-clear status mask. */
1669	#define VTD_PRS_REG_RW1C_MASK (VTD_BF_PRS_REG_PPR_MASK \| VTD_BF_PRS_REG_PRO_MASK)
1670	/** @} */
1671
1672
1673	/** @name Page Request Event Control Register (PECTL_REG).
1674	* In accordance with the Intel spec.
1675	* @{ */
1676	/** R: Reserved (bits 29:0). */
1677	#define VTD_BF_PECTL_REG_RSVD_29_0_SHIFT 0
1678	#define VTD_BF_PECTL_REG_RSVD_29_0_MASK UINT32_C(0x3fffffff)
1679	/** IP: Interrupt Pending. */
1680	#define VTD_BF_PECTL_REG_IP_SHIFT 30
1681	#define VTD_BF_PECTL_REG_IP_MASK UINT32_C(0x40000000)
1682	/** IM: Interrupt Mask. */
1683	#define VTD_BF_PECTL_REG_IM_SHIFT 31
1684	#define VTD_BF_PECTL_REG_IM_MASK UINT32_C(0x80000000)
1685	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_PECTL_REG_, UINT32_C(0), UINT32_MAX,
1686	(RSVD_29_0, IP, IM));
1687
1688	/** RW: Read/write mask. */
1689	#define VTD_PECTL_REG_RW_MASK VTD_BF_PECTL_REG_IM_MASK
1690	/** @} */
1691
1692
1693	/** @name Page Request Event Data Register (PEDATA_REG).
1694	* In accordance with the Intel spec.
1695	* @{ */
1696	/** IMD: Interrupt Message Data. */
1697	#define VTD_BF_PEDATA_REG_IMD_SHIFT 0
1698	#define VTD_BF_PEDATA_REG_IMD_MASK UINT32_C(0x0000ffff)
1699	/** R: Reserved (bits 31:16). VT-d specs. prior to 2021 had EIMD here. */
1700	#define VTD_BF_PEDATA_REG_RSVD_31_16_SHIFT 16
1701	#define VTD_BF_PEDATA_REG_RSVD_31_16_MASK UINT32_C(0xffff0000)
1702	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_PEDATA_REG_, UINT32_C(0), UINT32_MAX,
1703	(IMD, RSVD_31_16));
1704
1705	/** RW: Read/write mask. */
1706	#define VTD_PEDATA_REG_RW_MASK VTD_BF_PEDATA_REG_IMD_MASK
1707	/** @} */
1708
1709
1710	/** @name Page Request Event Address Register (PEADDR_REG).
1711	* In accordance with the Intel spec.
1712	* @{ */
1713	/** R: Reserved (bits 1:0). */
1714	#define VTD_BF_PEADDR_REG_RSVD_1_0_SHIFT 0
1715	#define VTD_BF_PEADDR_REG_RSVD_1_0_MASK UINT32_C(0x00000003)
1716	/** MA: Message Address. */
1717	#define VTD_BF_PEADDR_REG_MA_SHIFT 2
1718	#define VTD_BF_PEADDR_REG_MA_MASK UINT32_C(0xfffffffc)
1719	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_PEADDR_REG_, UINT32_C(0), UINT32_MAX,
1720	(RSVD_1_0, MA));
1721
1722	/** RW: Read/write mask. */
1723	#define VTD_PEADDR_REG_RW_MASK VTD_BF_PEADDR_REG_MA_MASK
1724	/** @} */
1725
1726
1727
1728	/** @name Page Request Event Upper Address Register (PEUADDR_REG).
1729	* In accordance with the Intel spec.
1730	* @{ */
1731	/** MA: Message Address. */
1732	#define VTD_BF_PEUADDR_REG_MUA_SHIFT 0
1733	#define VTD_BF_PEUADDR_REG_MUA_MASK UINT32_C(0xffffffff)
1734
1735	/** RW: Read/write mask. */
1736	#define VTD_PEUADDR_REG_RW_MASK VTD_BF_PEUADDR_REG_MUA_MASK
1737	/** @} */
1738
1739
1740	/** @name MTRR Capability Register (MTRRCAP_REG).
1741	* In accordance with the Intel spec.
1742	* @{ */
1743	/** VCNT: Variable MTRR Count. */
1744	#define VTD_BF_MTRRCAP_REG_VCNT_SHIFT 0
1745	#define VTD_BF_MTRRCAP_REG_VCNT_MASK UINT64_C(0x00000000000000ff)
1746	/** FIX: Fixed range MTRRs Supported. */
1747	#define VTD_BF_MTRRCAP_REG_FIX_SHIFT 8
1748	#define VTD_BF_MTRRCAP_REG_FIX_MASK UINT64_C(0x0000000000000100)
1749	/** R: Reserved (bit 9). */
1750	#define VTD_BF_MTRRCAP_REG_RSVD_9_SHIFT 9
1751	#define VTD_BF_MTRRCAP_REG_RSVD_9_MASK UINT64_C(0x0000000000000200)
1752	/** WC: Write Combining. */
1753	#define VTD_BF_MTRRCAP_REG_WC_SHIFT 10
1754	#define VTD_BF_MTRRCAP_REG_WC_MASK UINT64_C(0x0000000000000400)
1755	/** R: Reserved (bits 63:11). */
1756	#define VTD_BF_MTRRCAP_REG_RSVD_63_11_SHIFT 11
1757	#define VTD_BF_MTRRCAP_REG_RSVD_63_11_MASK UINT64_C(0xfffffffffffff800)
1758	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_MTRRCAP_REG_, UINT64_C(0), UINT64_MAX,
1759	(VCNT, FIX, RSVD_9, WC, RSVD_63_11));
1760
1761	/** RW: Read/write mask. */
1762	#define VTD_MTRRCAP_REG_RW_MASK UINT64_C(0)
1763	/** @} */
1764
1765
1766	/** @name MTRR Default Type Register (MTRRDEF_REG).
1767	* In accordance with the Intel spec.
1768	* @{ */
1769	/** TYPE: Default Memory Type. */
1770	#define VTD_BF_MTRRDEF_REG_TYPE_SHIFT 0
1771	#define VTD_BF_MTRRDEF_REG_TYPE_MASK UINT64_C(0x00000000000000ff)
1772	/** R: Reserved (bits 9:8). */
1773	#define VTD_BF_MTRRDEF_REG_RSVD_9_8_SHIFT 8
1774	#define VTD_BF_MTRRDEF_REG_RSVD_9_8_MASK UINT64_C(0x0000000000000300)
1775	/** FE: Fixed Range MTRR Enable. */
1776	#define VTD_BF_MTRRDEF_REG_FE_SHIFT 10
1777	#define VTD_BF_MTRRDEF_REG_FE_MASK UINT64_C(0x0000000000000400)
1778	/** E: MTRR Enable. */
1779	#define VTD_BF_MTRRDEF_REG_E_SHIFT 11
1780	#define VTD_BF_MTRRDEF_REG_E_MASK UINT64_C(0x0000000000000800)
1781	/** R: Reserved (bits 63:12). */
1782	#define VTD_BF_MTRRDEF_REG_RSVD_63_12_SHIFT 12
1783	#define VTD_BF_MTRRDEF_REG_RSVD_63_12_MASK UINT64_C(0xfffffffffffff000)
1784	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_MTRRDEF_REG_, UINT64_C(0), UINT64_MAX,
1785	(TYPE, RSVD_9_8, FE, E, RSVD_63_12));
1786
1787	/** RW: Read/write mask. */
1788	#define VTD_MTRRDEF_REG_RW_MASK ( VTD_BF_MTRRDEF_REG_TYPE_MASK \| VTD_BF_MTRRDEF_REG_FE_MASK \
1789	\| VTD_BF_MTRRDEF_REG_E_MASK)
1790	/** @} */
1791
1792
1793	/** @name Virtual Command Capability Register (VCCAP_REG).
1794	* In accordance with the Intel spec.
1795	* @{ */
1796	/** PAS: PASID Support. */
1797	#define VTD_BF_VCCAP_REG_PAS_SHIFT 0
1798	#define VTD_BF_VCCAP_REG_PAS_MASK UINT64_C(0x0000000000000001)
1799	/** R: Reserved (bits 63:1). */
1800	#define VTD_BF_VCCAP_REG_RSVD_63_1_SHIFT 1
1801	#define VTD_BF_VCCAP_REG_RSVD_63_1_MASK UINT64_C(0xfffffffffffffffe)
1802	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_VCCAP_REG_, UINT64_C(0), UINT64_MAX,
1803	(PAS, RSVD_63_1));
1804
1805	/** RW: Read/write mask. */
1806	#define VTD_VCCAP_REG_RW_MASK UINT64_C(0)
1807	/** @} */
1808
1809
1810	/** @name Virtual Command Extended Operand Register (VCMD_EO_REG).
1811	* In accordance with the Intel spec.
1812	* @{ */
1813	/** OB: Operand B. */
1814	#define VTD_BF_VCMD_EO_REG_OB_SHIFT 0
1815	#define VTD_BF_VCMD_EO_REG_OB_MASK UINT32_C(0xffffffffffffffff)
1816
1817	/** RW: Read/write mask. */
1818	#define VTD_VCMD_EO_REG_RW_MASK VTD_BF_VCMD_EO_REG_OB_MASK
1819	/** @} */
1820
1821
1822	/** @name Virtual Command Register (VCMD_REG).
1823	* In accordance with the Intel spec.
1824	* @{ */
1825	/** CMD: Command. */
1826	#define VTD_BF_VCMD_REG_CMD_SHIFT 0
1827	#define VTD_BF_VCMD_REG_CMD_MASK UINT64_C(0x00000000000000ff)
1828	/** OP: Operand. */
1829	#define VTD_BF_VCMD_REG_OP_SHIFT 8
1830	#define VTD_BF_VCMD_REG_OP_MASK UINT64_C(0xffffffffffffff00)
1831	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_VCMD_REG_, UINT64_C(0), UINT64_MAX,
1832	(CMD, OP));
1833
1834	/** RW: Read/write mask. */
1835	#define VTD_VCMD_REG_RW_MASK (VTD_BF_VCMD_REG_CMD_MASK \| VTD_BF_VCMD_REG_OP_MASK)
1836	/** @} */
1837
1838
1839	/** @name Virtual Command Response Register (VCRSP_REG).
1840	* In accordance with the Intel spec.
1841	* @{ */
1842	/** IP: In Progress. */
1843	#define VTD_BF_VCRSP_REG_IP_SHIFT 0
1844	#define VTD_BF_VCRSP_REG_IP_MASK UINT64_C(0x0000000000000001)
1845	/** SC: Status Code. */
1846	#define VTD_BF_VCRSP_REG_SC_SHIFT 1
1847	#define VTD_BF_VCRSP_REG_SC_MASK UINT64_C(0x0000000000000006)
1848	/** R: Reserved (bits 7:3). */
1849	#define VTD_BF_VCRSP_REG_RSVD_7_3_SHIFT 3
1850	#define VTD_BF_VCRSP_REG_RSVD_7_3_MASK UINT64_C(0x00000000000000f8)
1851	/** RSLT: Result. */
1852	#define VTD_BF_VCRSP_REG_RSLT_SHIFT 8
1853	#define VTD_BF_VCRSP_REG_RSLT_MASK UINT64_C(0xffffffffffffff00)
1854	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_VCRSP_REG_, UINT64_C(0), UINT64_MAX,
1855	(IP, SC, RSVD_7_3, RSLT));
1856
1857	/** RW: Read/write mask. */
1858	#define VTD_VCRSP_REG_RW_MASK UINT64_C(0)
1859	/** @} */
1860
1861
1862	/** @name Generic Invalidation Descriptor.
1863	* In accordance with the Intel spec.
1864	* Non-reserved fields here are common to all invalidation descriptors.
1865	* @{ */
1866	/** Type (Lo). */
1867	#define VTD_BF_0_GENERIC_INV_DSC_TYPE_LO_SHIFT 0
1868	#define VTD_BF_0_GENERIC_INV_DSC_TYPE_LO_MASK UINT64_C(0x000000000000000f)
1869	/** R: Reserved (bits 8:4). */
1870	#define VTD_BF_0_GENERIC_INV_DSC_RSVD_8_4_SHIFT 4
1871	#define VTD_BF_0_GENERIC_INV_DSC_RSVD_8_4_MASK UINT64_C(0x00000000000001f0)
1872	/** Type (Hi). */
1873	#define VTD_BF_0_GENERIC_INV_DSC_TYPE_HI_SHIFT 9
1874	#define VTD_BF_0_GENERIC_INV_DSC_TYPE_HI_MASK UINT64_C(0x0000000000000e00)
1875	/** R: Reserved (bits 63:12). */
1876	#define VTD_BF_0_GENERIC_INV_DSC_RSVD_63_12_SHIFT 12
1877	#define VTD_BF_0_GENERIC_INV_DSC_RSVD_63_12_MASK UINT64_C(0xfffffffffffff000)
1878	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_GENERIC_INV_DSC_, UINT64_C(0), UINT64_MAX,
1879	(TYPE_LO, RSVD_8_4, TYPE_HI, RSVD_63_12));
1880
1881	/** GENERIC_INV_DSC: Type. */
1882	#define VTD_GENERIC_INV_DSC_GET_TYPE(a) ((((a) & VTD_BF_0_GENERIC_INV_DSC_TYPE_HI_MASK) >> 5) \
1883	\| ((a) & VTD_BF_0_GENERIC_INV_DSC_TYPE_LO_MASK))
1884	/** @} */
1885
1886
1887	/** @name Context-Cache Invalidation Descriptor (cc_inv_dsc).
1888	* In accordance with the Intel spec.
1889	* @{ */
1890	/** Type (Lo). */
1891	#define VTD_BF_0_CC_INV_DSC_TYPE_LO_SHIFT 0
1892	#define VTD_BF_0_CC_INV_DSC_TYPE_LO_MASK UINT64_C(0x000000000000000f)
1893	/** G: Granularity. */
1894	#define VTD_BF_0_CC_INV_DSC_G_SHIFT 4
1895	#define VTD_BF_0_CC_INV_DSC_G_MASK UINT64_C(0x0000000000000030)
1896	/** R: Reserved (bits 8:6). */
1897	#define VTD_BF_0_CC_INV_DSC_RSVD_8_6_SHIFT 6
1898	#define VTD_BF_0_CC_INV_DSC_RSVD_8_6_MASK UINT64_C(0x00000000000001c0)
1899	/** Type (Hi). */
1900	#define VTD_BF_0_CC_INV_DSC_TYPE_HI_SHIFT 9
1901	#define VTD_BF_0_CC_INV_DSC_TYPE_HI_MASK UINT64_C(0x0000000000000e00)
1902	/** R: Reserved (bits 15:12). */
1903	#define VTD_BF_0_CC_INV_DSC_RSVD_15_12_SHIFT 12
1904	#define VTD_BF_0_CC_INV_DSC_RSVD_15_12_MASK UINT64_C(0x000000000000f000)
1905	/** DID: Domain Id. */
1906	#define VTD_BF_0_CC_INV_DSC_DID_SHIFT 16
1907	#define VTD_BF_0_CC_INV_DSC_DID_MASK UINT64_C(0x00000000ffff0000)
1908	/** SID: Source Id. */
1909	#define VTD_BF_0_CC_INV_DSC_SID_SHIFT 32
1910	#define VTD_BF_0_CC_INV_DSC_SID_MASK UINT64_C(0x0000ffff00000000)
1911	/** FM: Function Mask. */
1912	#define VTD_BF_0_CC_INV_DSC_FM_SHIFT 48
1913	#define VTD_BF_0_CC_INV_DSC_FM_MASK UINT64_C(0x0003000000000000)
1914	/** R: Reserved (bits 63:50). */
1915	#define VTD_BF_0_CC_INV_DSC_RSVD_63_50_SHIFT 50
1916	#define VTD_BF_0_CC_INV_DSC_RSVD_63_50_MASK UINT64_C(0xfffc000000000000)
1917	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_CC_INV_DSC_, UINT64_C(0), UINT64_MAX,
1918	(TYPE_LO, G, RSVD_8_6, TYPE_HI, RSVD_15_12, DID, SID, FM, RSVD_63_50));
1919	/** @} */
1920
1921
1922	/** @name PASID-Cache Invalidation Descriptor (pc_inv_dsc).
1923	* In accordance with the Intel spec.
1924	* @{ */
1925	/** Type (Lo). */
1926	#define VTD_BF_0_PC_INV_DSC_TYPE_LO_SHIFT 0
1927	#define VTD_BF_0_PC_INV_DSC_TYPE_LO_MASK UINT64_C(0x000000000000000f)
1928	/** G: Granularity. */
1929	#define VTD_BF_0_PC_INV_DSC_G_SHIFT 4
1930	#define VTD_BF_0_PC_INV_DSC_G_MASK UINT64_C(0x0000000000000030)
1931	/** R: Reserved (bits 8:6). */
1932	#define VTD_BF_0_PC_INV_DSC_RSVD_8_6_SHIFT 6
1933	#define VTD_BF_0_PC_INV_DSC_RSVD_8_6_MASK UINT64_C(0x00000000000001c0)
1934	/** Type (Hi). */
1935	#define VTD_BF_0_PC_INV_DSC_TYPE_HI_SHIFT 9
1936	#define VTD_BF_0_PC_INV_DSC_TYPE_HI_MASK UINT64_C(0x0000000000000e00)
1937	/** R: Reserved (bits 15:12). */
1938	#define VTD_BF_0_PC_INV_DSC_RSVD_15_12_SHIFT 12
1939	#define VTD_BF_0_PC_INV_DSC_RSVD_15_12_MASK UINT64_C(0x000000000000f000)
1940	/** DID: Domain Id. */
1941	#define VTD_BF_0_PC_INV_DSC_DID_SHIFT 16
1942	#define VTD_BF_0_PC_INV_DSC_DID_MASK UINT64_C(0x00000000ffff0000)
1943	/** PASID: Process Address-Space Id. */
1944	#define VTD_BF_0_PC_INV_DSC_PASID_SHIFT 32
1945	#define VTD_BF_0_PC_INV_DSC_PASID_MASK UINT64_C(0x000fffff00000000)
1946	/** R: Reserved (bits 63:52). */
1947	#define VTD_BF_0_PC_INV_DSC_RSVD_63_52_SHIFT 52
1948	#define VTD_BF_0_PC_INV_DSC_RSVD_63_52_MASK UINT64_C(0xfff0000000000000)
1949
1950	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_PC_INV_DSC_, UINT64_C(0), UINT64_MAX,
1951	(TYPE_LO, G, RSVD_8_6, TYPE_HI, RSVD_15_12, DID, PASID, RSVD_63_52));
1952	/** @} */
1953
1954
1955	/** @name IOTLB Invalidate Descriptor (iotlb_inv_dsc).
1956	* In accordance with the Intel spec.
1957	* @{ */
1958	/** Type (Lo). */
1959	#define VTD_BF_0_IOTLB_INV_DSC_TYPE_LO_SHIFT 0
1960	#define VTD_BF_0_IOTLB_INV_DSC_TYPE_LO_MASK UINT64_C(0x000000000000000f)
1961	/** G: Granularity. */
1962	#define VTD_BF_0_IOTLB_INV_DSC_G_SHIFT 4
1963	#define VTD_BF_0_IOTLB_INV_DSC_G_MASK UINT64_C(0x0000000000000030)
1964	/** DW: Drain Writes. */
1965	#define VTD_BF_0_IOTLB_INV_DSC_DW_SHIFT 6
1966	#define VTD_BF_0_IOTLB_INV_DSC_DW_MASK UINT64_C(0x0000000000000040)
1967	/** DR: Drain Reads. */
1968	#define VTD_BF_0_IOTLB_INV_DSC_DR_SHIFT 7
1969	#define VTD_BF_0_IOTLB_INV_DSC_DR_MASK UINT64_C(0x0000000000000080)
1970	/** R: Reserved (bit 8). */
1971	#define VTD_BF_0_IOTLB_INV_DSC_RSVD_8_SHIFT 8
1972	#define VTD_BF_0_IOTLB_INV_DSC_RSVD_8_MASK UINT64_C(0x0000000000000100)
1973	/** Type (Hi). */
1974	#define VTD_BF_0_IOTLB_INV_DSC_TYPE_HI_SHIFT 9
1975	#define VTD_BF_0_IOTLB_INV_DSC_TYPE_HI_MASK UINT64_C(0x0000000000000e00)
1976	/** R: Reserved (bits 15:12). */
1977	#define VTD_BF_0_IOTLB_INV_DSC_RSVD_15_12_SHIFT 12
1978	#define VTD_BF_0_IOTLB_INV_DSC_RSVD_15_12_MASK UINT64_C(0x000000000000f000)
1979	/** DID: Domain Id. */
1980	#define VTD_BF_0_IOTLB_INV_DSC_DID_SHIFT 16
1981	#define VTD_BF_0_IOTLB_INV_DSC_DID_MASK UINT64_C(0x00000000ffff0000)
1982	/** R: Reserved (bits 63:32). */
1983	#define VTD_BF_0_IOTLB_INV_DSC_RSVD_63_32_SHIFT 32
1984	#define VTD_BF_0_IOTLB_INV_DSC_RSVD_63_32_MASK UINT64_C(0xffffffff00000000)
1985	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_IOTLB_INV_DSC_, UINT64_C(0), UINT64_MAX,
1986	(TYPE_LO, G, DW, DR, RSVD_8, TYPE_HI, RSVD_15_12, DID, RSVD_63_32));
1987
1988	/** AM: Address Mask. */
1989	#define VTD_BF_1_IOTLB_INV_DSC_AM_SHIFT 0
1990	#define VTD_BF_1_IOTLB_INV_DSC_AM_MASK UINT64_C(0x000000000000003f)
1991	/** IH: Invalidation Hint. */
1992	#define VTD_BF_1_IOTLB_INV_DSC_IH_SHIFT 6
1993	#define VTD_BF_1_IOTLB_INV_DSC_IH_MASK UINT64_C(0x0000000000000040)
1994	/** R: Reserved (bits 11:7). */
1995	#define VTD_BF_1_IOTLB_INV_DSC_RSVD_11_7_SHIFT 7
1996	#define VTD_BF_1_IOTLB_INV_DSC_RSVD_11_7_MASK UINT64_C(0x0000000000000f80)
1997	/** ADDR: Address. */
1998	#define VTD_BF_1_IOTLB_INV_DSC_ADDR_SHIFT 12
1999	#define VTD_BF_1_IOTLB_INV_DSC_ADDR_MASK UINT64_C(0xfffffffffffff000)
2000	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_IOTLB_INV_DSC_, UINT64_C(0), UINT64_MAX,
2001	(AM, IH, RSVD_11_7, ADDR));
2002	/** @} */
2003
2004
2005	/** @name PASID-based IOTLB Invalidate Descriptor (p_iotlb_inv_dsc).
2006	* In accordance with the Intel spec.
2007	* @{ */
2008	/** Type (Lo). */
2009	#define VTD_BF_0_P_IOTLB_INV_DSC_TYPE_LO_SHIFT 0
2010	#define VTD_BF_0_P_IOTLB_INV_DSC_TYPE_LO_MASK UINT64_C(0x000000000000000f)
2011	/** G: Granularity. */
2012	#define VTD_BF_0_P_IOTLB_INV_DSC_G_SHIFT 4
2013	#define VTD_BF_0_P_IOTLB_INV_DSC_G_MASK UINT64_C(0x0000000000000030)
2014	/** R: Reserved (bits 8:6). */
2015	#define VTD_BF_0_P_IOTLB_INV_DSC_RSVD_8_6_SHIFT 6
2016	#define VTD_BF_0_P_IOTLB_INV_DSC_RSVD_8_6_MASK UINT64_C(0x00000000000001c0)
2017	/** Type (Hi). */
2018	#define VTD_BF_0_P_IOTLB_INV_DSC_TYPE_HI_SHIFT 9
2019	#define VTD_BF_0_P_IOTLB_INV_DSC_TYPE_HI_MASK UINT64_C(0x0000000000000e00)
2020	/** R: Reserved (bits 15:12). */
2021	#define VTD_BF_0_P_IOTLB_INV_DSC_RSVD_15_12_SHIFT 12
2022	#define VTD_BF_0_P_IOTLB_INV_DSC_RSVD_15_12_MASK UINT64_C(0x000000000000f000)
2023	/** DID: Domain Id. */
2024	#define VTD_BF_0_P_IOTLB_INV_DSC_DID_SHIFT 16
2025	#define VTD_BF_0_P_IOTLB_INV_DSC_DID_MASK UINT64_C(0x00000000ffff0000)
2026	/** PASID: Process Address-Space Id. */
2027	#define VTD_BF_0_P_IOTLB_INV_DSC_PASID_SHIFT 32
2028	#define VTD_BF_0_P_IOTLB_INV_DSC_PASID_MASK UINT64_C(0x000fffff00000000)
2029	/** R: Reserved (bits 63:52). */
2030	#define VTD_BF_0_P_IOTLB_INV_DSC_RSVD_63_52_SHIFT 52
2031	#define VTD_BF_0_P_IOTLB_INV_DSC_RSVD_63_52_MASK UINT64_C(0xfff0000000000000)
2032	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_P_IOTLB_INV_DSC_, UINT64_C(0), UINT64_MAX,
2033	(TYPE_LO, G, RSVD_8_6, TYPE_HI, RSVD_15_12, DID, PASID, RSVD_63_52));
2034
2035
2036	/** AM: Address Mask. */
2037	#define VTD_BF_1_P_IOTLB_INV_DSC_AM_SHIFT 0
2038	#define VTD_BF_1_P_IOTLB_INV_DSC_AM_MASK UINT64_C(0x000000000000003f)
2039	/** IH: Invalidation Hint. */
2040	#define VTD_BF_1_P_IOTLB_INV_DSC_IH_SHIFT 6
2041	#define VTD_BF_1_P_IOTLB_INV_DSC_IH_MASK UINT64_C(0x0000000000000040)
2042	/** R: Reserved (bits 11:7). */
2043	#define VTD_BF_1_P_IOTLB_INV_DSC_RSVD_11_7_SHIFT 7
2044	#define VTD_BF_1_P_IOTLB_INV_DSC_RSVD_11_7_MASK UINT64_C(0x0000000000000f80)
2045	/** ADDR: Address. */
2046	#define VTD_BF_1_P_IOTLB_INV_DSC_ADDR_SHIFT 12
2047	#define VTD_BF_1_P_IOTLB_INV_DSC_ADDR_MASK UINT64_C(0xfffffffffffff000)
2048	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_P_IOTLB_INV_DSC_, UINT64_C(0), UINT64_MAX,
2049	(AM, IH, RSVD_11_7, ADDR));
2050	/** @} */
2051
2052
2053	/** @name Device-TLB Invalidate Descriptor (dev_tlb_inv_dsc).
2054	* In accordance with the Intel spec.
2055	* @{ */
2056	/** Type (Lo). */
2057	#define VTD_BF_0_DEV_TLB_INV_DSC_TYPE_LO_SHIFT 0
2058	#define VTD_BF_0_DEV_TLB_INV_DSC_TYPE_LO_MASK UINT64_C(0x000000000000000f)
2059	/** R: Reserved (bits 8:4). */
2060	#define VTD_BF_0_DEV_TLB_INV_DSC_RSVD_8_4_SHIFT 4
2061	#define VTD_BF_0_DEV_TLB_INV_DSC_RSVD_8_4_MASK UINT64_C(0x00000000000001f0)
2062	/** Type (Hi). */
2063	#define VTD_BF_0_DEV_TLB_INV_DSC_TYPE_HI_SHIFT 9
2064	#define VTD_BF_0_DEV_TLB_INV_DSC_TYPE_HI_MASK UINT64_C(0x0000000000000e00)
2065	/** PFSID: Physical-Function Source Id (Lo). */
2066	#define VTD_BF_0_DEV_TLB_INV_DSC_PFSID_LO_SHIFT 12
2067	#define VTD_BF_0_DEV_TLB_INV_DSC_PFSID_LO_MASK UINT64_C(0x000000000000f000)
2068	/** MIP: Max Invalidations Pending. */
2069	#define VTD_BF_0_DEV_TLB_INV_DSC_MIP_SHIFT 16
2070	#define VTD_BF_0_DEV_TLB_INV_DSC_MIP_MASK UINT64_C(0x00000000001f0000)
2071	/** R: Reserved (bits 31:21). */
2072	#define VTD_BF_0_DEV_TLB_INV_DSC_RSVD_31_21_SHIFT 21
2073	#define VTD_BF_0_DEV_TLB_INV_DSC_RSVD_31_21_MASK UINT64_C(0x00000000ffe00000)
2074	/** SID: Source Id. */
2075	#define VTD_BF_0_DEV_TLB_INV_DSC_SID_SHIFT 32
2076	#define VTD_BF_0_DEV_TLB_INV_DSC_SID_MASK UINT64_C(0x0000ffff00000000)
2077	/** R: Reserved (bits 51:48). */
2078	#define VTD_BF_0_DEV_TLB_INV_DSC_RSVD_51_48_SHIFT 48
2079	#define VTD_BF_0_DEV_TLB_INV_DSC_RSVD_51_48_MASK UINT64_C(0x000f000000000000)
2080	/** PFSID: Physical-Function Source Id (Hi). */
2081	#define VTD_BF_0_DEV_TLB_INV_DSC_PFSID_HI_SHIFT 52
2082	#define VTD_BF_0_DEV_TLB_INV_DSC_PFSID_HI_MASK UINT64_C(0xfff0000000000000)
2083	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_DEV_TLB_INV_DSC_, UINT64_C(0), UINT64_MAX,
2084	(TYPE_LO, RSVD_8_4, TYPE_HI, PFSID_LO, MIP, RSVD_31_21, SID, RSVD_51_48, PFSID_HI));
2085
2086	/** S: Size. */
2087	#define VTD_BF_1_DEV_TLB_INV_DSC_S_SHIFT 0
2088	#define VTD_BF_1_DEV_TLB_INV_DSC_S_MASK UINT64_C(0x0000000000000001)
2089	/** R: Reserved (bits 11:1). */
2090	#define VTD_BF_1_DEV_TLB_INV_DSC_RSVD_11_1_SHIFT 1
2091	#define VTD_BF_1_DEV_TLB_INV_DSC_RSVD_11_1_MASK UINT64_C(0x0000000000000ffe)
2092	/** ADDR: Address. */
2093	#define VTD_BF_1_DEV_TLB_INV_DSC_ADDR_SHIFT 12
2094	#define VTD_BF_1_DEV_TLB_INV_DSC_ADDR_MASK UINT64_C(0xfffffffffffff000)
2095	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_DEV_TLB_INV_DSC_, UINT64_C(0), UINT64_MAX,
2096	(S, RSVD_11_1, ADDR));
2097	/** @} */
2098
2099
2100	/** @name PASID-based-device-TLB Invalidate Descriptor (p_dev_tlb_inv_dsc).
2101	* In accordance with the Intel spec.
2102	* @{ */
2103	/** Type (Lo). */
2104	#define VTD_BF_0_P_DEV_TLB_INV_DSC_TYPE_LO_SHIFT 0
2105	#define VTD_BF_0_P_DEV_TLB_INV_DSC_TYPE_LO_MASK UINT64_C(0x000000000000000f)
2106	/** MIP: Max Invalidations Pending. */
2107	#define VTD_BF_0_P_DEV_TLB_INV_DSC_MIP_SHIFT 4
2108	#define VTD_BF_0_P_DEV_TLB_INV_DSC_MIP_MASK UINT64_C(0x00000000000001f0)
2109	/** Type (Hi). */
2110	#define VTD_BF_0_P_DEV_TLB_INV_DSC_TYPE_HI_SHIFT 9
2111	#define VTD_BF_0_P_DEV_TLB_INV_DSC_TYPE_HI_MASK UINT64_C(0x0000000000000e00)
2112	/** PFSID: Physical-Function Source Id (Lo). */
2113	#define VTD_BF_0_P_DEV_TLB_INV_DSC_PFSID_LO_SHIFT 12
2114	#define VTD_BF_0_P_DEV_TLB_INV_DSC_PFSID_LO_MASK UINT64_C(0x000000000000f000)
2115	/** SID: Source Id. */
2116	#define VTD_BF_0_P_DEV_TLB_INV_DSC_SID_SHIFT 16
2117	#define VTD_BF_0_P_DEV_TLB_INV_DSC_SID_MASK UINT64_C(0x00000000ffff0000)
2118	/** PASID: Process Address-Space Id. */
2119	#define VTD_BF_0_P_DEV_TLB_INV_DSC_PASID_SHIFT 32
2120	#define VTD_BF_0_P_DEV_TLB_INV_DSC_PASID_MASK UINT64_C(0x000fffff00000000)
2121	/** PFSID: Physical-Function Source Id (Hi). */
2122	#define VTD_BF_0_P_DEV_TLB_INV_DSC_PFSID_HI_SHIFT 52
2123	#define VTD_BF_0_P_DEV_TLB_INV_DSC_PFSID_HI_MASK UINT64_C(0xfff0000000000000)
2124	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_P_DEV_TLB_INV_DSC_, UINT64_C(0), UINT64_MAX,
2125	(TYPE_LO, MIP, TYPE_HI, PFSID_LO, SID, PASID, PFSID_HI));
2126
2127	/** G: Granularity. */
2128	#define VTD_BF_1_P_DEV_TLB_INV_DSC_G_SHIFT 0
2129	#define VTD_BF_1_P_DEV_TLB_INV_DSC_G_MASK UINT64_C(0x0000000000000001)
2130	/** R: Reserved (bits 10:1). */
2131	#define VTD_BF_1_P_DEV_TLB_INV_DSC_RSVD_10_1_SHIFT 1
2132	#define VTD_BF_1_P_DEV_TLB_INV_DSC_RSVD_10_1_MASK UINT64_C(0x00000000000007fe)
2133	/** S: Size. */
2134	#define VTD_BF_1_P_DEV_TLB_INV_DSC_S_SHIFT 11
2135	#define VTD_BF_1_P_DEV_TLB_INV_DSC_S_MASK UINT64_C(0x0000000000000800)
2136	/** ADDR: Address. */
2137	#define VTD_BF_1_P_DEV_TLB_INV_DSC_ADDR_SHIFT 12
2138	#define VTD_BF_1_P_DEV_TLB_INV_DSC_ADDR_MASK UINT64_C(0xfffffffffffff000)
2139	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_P_DEV_TLB_INV_DSC_, UINT64_C(0), UINT64_MAX,
2140	(G, RSVD_10_1, S, ADDR));
2141	/** @} */
2142
2143
2144	/** @name Interrupt Entry Cache Invalidate Descriptor (iec_inv_dsc).
2145	* In accordance with the Intel spec.
2146	* @{ */
2147	/** Type (Lo). */
2148	#define VTD_BF_0_IEC_INV_DSC_TYPE_LO_SHIFT 0
2149	#define VTD_BF_0_IEC_INV_DSC_TYPE_LO_MASK UINT64_C(0x000000000000000f)
2150	/** G: Granularity. */
2151	#define VTD_BF_0_IEC_INV_DSC_G_SHIFT 4
2152	#define VTD_BF_0_IEC_INV_DSC_G_MASK UINT64_C(0x0000000000000010)
2153	/** R: Reserved (bits 8:5). */
2154	#define VTD_BF_0_IEC_INV_DSC_RSVD_8_5_SHIFT 5
2155	#define VTD_BF_0_IEC_INV_DSC_RSVD_8_5_MASK UINT64_C(0x00000000000001e0)
2156	/** Type (Hi). */
2157	#define VTD_BF_0_IEC_INV_DSC_TYPE_HI_SHIFT 9
2158	#define VTD_BF_0_IEC_INV_DSC_TYPE_HI_MASK UINT64_C(0x0000000000000e00)
2159	/** R: Reserved (bits 26:12). */
2160	#define VTD_BF_0_IEC_INV_DSC_RSVD_26_12_SHIFT 12
2161	#define VTD_BF_0_IEC_INV_DSC_RSVD_26_12_MASK UINT64_C(0x0000000007fff000)
2162	/** IM: Index Mask. */
2163	#define VTD_BF_0_IEC_INV_DSC_IM_SHIFT 27
2164	#define VTD_BF_0_IEC_INV_DSC_IM_MASK UINT64_C(0x00000000f8000000)
2165	/** IIDX: Interrupt Index. */
2166	#define VTD_BF_0_IEC_INV_DSC_IIDX_SHIFT 32
2167	#define VTD_BF_0_IEC_INV_DSC_IIDX_MASK UINT64_C(0x0000ffff00000000)
2168	/** R: Reserved (bits 63:48). */
2169	#define VTD_BF_0_IEC_INV_DSC_RSVD_63_48_SHIFT 48
2170	#define VTD_BF_0_IEC_INV_DSC_RSVD_63_48_MASK UINT64_C(0xffff000000000000)
2171	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_IEC_INV_DSC_, UINT64_C(0), UINT64_MAX,
2172	(TYPE_LO, G, RSVD_8_5, TYPE_HI, RSVD_26_12, IM, IIDX, RSVD_63_48));
2173	/** @} */
2174
2175
2176	/** @name Invalidation Wait Descriptor (inv_wait_dsc).
2177	* In accordance with the Intel spec.
2178	* @{ */
2179	/** Type (Lo). */
2180	#define VTD_BF_0_INV_WAIT_DSC_TYPE_LO_SHIFT 0
2181	#define VTD_BF_0_INV_WAIT_DSC_TYPE_LO_MASK UINT64_C(0x000000000000000f)
2182	/** IF: Interrupt Flag. */
2183	#define VTD_BF_0_INV_WAIT_DSC_IF_SHIFT 4
2184	#define VTD_BF_0_INV_WAIT_DSC_IF_MASK UINT64_C(0x0000000000000010)
2185	/** SW: Status Write. */
2186	#define VTD_BF_0_INV_WAIT_DSC_SW_SHIFT 5
2187	#define VTD_BF_0_INV_WAIT_DSC_SW_MASK UINT64_C(0x0000000000000020)
2188	/** FN: Fence Flag. */
2189	#define VTD_BF_0_INV_WAIT_DSC_FN_SHIFT 6
2190	#define VTD_BF_0_INV_WAIT_DSC_FN_MASK UINT64_C(0x0000000000000040)
2191	/** PD: Page-Request Drain. */
2192	#define VTD_BF_0_INV_WAIT_DSC_PD_SHIFT 7
2193	#define VTD_BF_0_INV_WAIT_DSC_PD_MASK UINT64_C(0x0000000000000080)
2194	/** R: Reserved (bit 8). */
2195	#define VTD_BF_0_INV_WAIT_DSC_RSVD_8_SHIFT 8
2196	#define VTD_BF_0_INV_WAIT_DSC_RSVD_8_MASK UINT64_C(0x0000000000000100)
2197	/** Type (Hi). */
2198	#define VTD_BF_0_INV_WAIT_DSC_TYPE_HI_SHIFT 9
2199	#define VTD_BF_0_INV_WAIT_DSC_TYPE_HI_MASK UINT64_C(0x0000000000000e00)
2200	/** R: Reserved (bits 31:12). */
2201	#define VTD_BF_0_INV_WAIT_DSC_RSVD_31_12_SHIFT 12
2202	#define VTD_BF_0_INV_WAIT_DSC_RSVD_31_12_MASK UINT64_C(0x00000000fffff000)
2203	/** STDATA: Status Data. */
2204	#define VTD_BF_0_INV_WAIT_DSC_STDATA_SHIFT 32
2205	#define VTD_BF_0_INV_WAIT_DSC_STDATA_MASK UINT64_C(0xffffffff00000000)
2206	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_INV_WAIT_DSC_, UINT64_C(0), UINT64_MAX,
2207	(TYPE_LO, IF, SW, FN, PD, RSVD_8, TYPE_HI, RSVD_31_12, STDATA));
2208
2209	/** R: Reserved (bits 1:0). */
2210	#define VTD_BF_1_INV_WAIT_DSC_RSVD_1_0_SHIFT 0
2211	#define VTD_BF_1_INV_WAIT_DSC_RSVD_1_0_MASK UINT64_C(0x0000000000000003)
2212	/** STADDR: Status Address. */
2213	#define VTD_BF_1_INV_WAIT_DSC_STADDR_SHIFT 2
2214	#define VTD_BF_1_INV_WAIT_DSC_STADDR_MASK UINT64_C(0xfffffffffffffffc)
2215	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_INV_WAIT_DSC_, UINT64_C(0), UINT64_MAX,
2216	(RSVD_1_0, STADDR));
2217
2218	/* INV_WAIT_DSC: Qword 0 valid mask. */
2219	#define VTD_INV_WAIT_DSC_0_VALID_MASK ( VTD_BF_0_INV_WAIT_DSC_TYPE_LO_MASK \
2220	\| VTD_BF_0_INV_WAIT_DSC_IF_MASK \
2221	\| VTD_BF_0_INV_WAIT_DSC_SW_MASK \
2222	\| VTD_BF_0_INV_WAIT_DSC_FN_MASK \
2223	\| VTD_BF_0_INV_WAIT_DSC_PD_MASK \
2224	\| VTD_BF_0_INV_WAIT_DSC_TYPE_HI_MASK \
2225	\| VTD_BF_0_INV_WAIT_DSC_STDATA_MASK)
2226	/* INV_WAIT_DSC: Qword 1 valid mask. */
2227	#define VTD_INV_WAIT_DSC_1_VALID_MASK VTD_BF_1_INV_WAIT_DSC_STADDR_MASK
2228	/** @} */
2229
2230
2231	/** @name Invalidation descriptor types.
2232	* In accordance with the Intel spec.
2233	* @{ */
2234	#define VTD_CC_INV_DSC_TYPE 1
2235	#define VTD_IOTLB_INV_DSC_TYPE 2
2236	#define VTD_DEV_TLB_INV_DSC_TYPE 3
2237	#define VTD_IEC_INV_DSC_TYPE 4
2238	#define VTD_INV_WAIT_DSC_TYPE 5
2239	#define VTD_P_IOTLB_INV_DSC_TYPE 6
2240	#define VTD_PC_INV_DSC_TYPE 7
2241	#define VTD_P_DEV_TLB_INV_DSC_TYPE 8
2242	/** @} */
2243
2244
2245	/** @name Remappable Format Interrupt Request.
2246	* In accordance with the Intel spec.
2247	* @{ */
2248	/** IGN: Ignored (bits 1:0). */
2249	#define VTD_BF_REMAPPABLE_MSI_ADDR_IGN_1_0_SHIFT 0
2250	#define VTD_BF_REMAPPABLE_MSI_ADDR_IGN_1_0_MASK UINT32_C(0x00000003)
2251	/** Handle (Hi). */
2252	#define VTD_BF_REMAPPABLE_MSI_ADDR_HANDLE_HI_SHIFT 2
2253	#define VTD_BF_REMAPPABLE_MSI_ADDR_HANDLE_HI_MASK UINT32_C(0x00000004)
2254	/** SHV: Subhandle Valid. */
2255	#define VTD_BF_REMAPPABLE_MSI_ADDR_SHV_SHIFT 3
2256	#define VTD_BF_REMAPPABLE_MSI_ADDR_SHV_MASK UINT32_C(0x00000008)
2257	/** Interrupt format. */
2258	#define VTD_BF_REMAPPABLE_MSI_ADDR_INTR_FMT_SHIFT 4
2259	#define VTD_BF_REMAPPABLE_MSI_ADDR_INTR_FMT_MASK UINT32_C(0x00000010)
2260	/** Handle (Lo). */
2261	#define VTD_BF_REMAPPABLE_MSI_ADDR_HANDLE_LO_SHIFT 5
2262	#define VTD_BF_REMAPPABLE_MSI_ADDR_HANDLE_LO_MASK UINT32_C(0x000fffe0)
2263	/** Address. */
2264	#define VTD_BF_REMAPPABLE_MSI_ADDR_ADDR_SHIFT 20
2265	#define VTD_BF_REMAPPABLE_MSI_ADDR_ADDR_MASK UINT32_C(0xfff00000)
2266	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_REMAPPABLE_MSI_ADDR_, UINT32_C(0), UINT32_MAX,
2267	(IGN_1_0, HANDLE_HI, SHV, INTR_FMT, HANDLE_LO, ADDR));
2268
2269	/** Subhandle. */
2270	#define VTD_BF_REMAPPABLE_MSI_DATA_SUBHANDLE_SHIFT 0
2271	#define VTD_BF_REMAPPABLE_MSI_DATA_SUBHANDLE_MASK UINT32_C(0x0000ffff)
2272	/** R: Reserved (bits 31:16). */
2273	#define VTD_BF_REMAPPABLE_MSI_DATA_RSVD_31_16_SHIFT 16
2274	#define VTD_BF_REMAPPABLE_MSI_DATA_RSVD_31_16_MASK UINT32_C(0xffff0000)
2275	RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_REMAPPABLE_MSI_DATA_, UINT32_C(0), UINT32_MAX,
2276	(SUBHANDLE, RSVD_31_16));
2277
2278	/** Remappable MSI Address: Valid mask. */
2279	#define VTD_REMAPPABLE_MSI_ADDR_VALID_MASK UINT32_MAX
2280	/** Remappable MSI Data: Valid mask. */
2281	#define VTD_REMAPPABLE_MSI_DATA_VALID_MASK VTD_BF_REMAPPABLE_MSI_DATA_SUBHANDLE_MASK
2282
2283	/** Gets the interrupt format from an MSI address. */
2284	#define VTD_MSI_ADDR_GET_INTR_FORMAT(a_uMsiAddr) ((a_uMsiAddr) & RT_BIT_64(4))
2285	/** Interrupt format: Compatibility. */
2286	#define VTD_INTR_FORMAT_COMPAT 0
2287	/** Interrupt format: Remappable. */
2288	#define VTD_INTR_FORMAT_REMAPPABLE 1
2289	/** @} */
2290
2291
2292	/** @name Interrupt Remapping Fault Conditions.
2293	* In accordance with the Intel spec.
2294	* @{ */
2295	typedef enum VTD_IR_FAULT_T
2296	{
2297	/** Reserved bits invalid in remappable interrupt. */
2298	kIrf_Remappable_Intr_Rsvd = 0x20,
2299	/** Interrupt index for remappable interrupt exceeds table size or referenced
2300	* address above host address width (HAW) */
2301	kIrf_Intr_Index_Invalid = 0x21,
2302	/** The IRTE is not present. */
2303	kIrf_Irte_Not_Present = 0x22,
2304	/** Reading IRTE from memory failed. */
2305	kIrf_Irte_Read_Failed = 0x23,
2306	/** IRTE reserved bits invalid for an IRTE with Present bit set. */
2307	kIrf_Irte_Present_Rsvd = 0x24,
2308	/** Compatibility format interrupt (CFI) blocked due to EIME is enabled or CFIs
2309	* disabled. */
2310	kIrf_Cfi_Blocked = 0x25,
2311	/** IRTE SID, SVT, SQ bits invalid for an IRTE with Present bit set. */
2312	kIrf_Irte_Present_Invalid = 0x26,
2313	/** Reading posted interrupt descriptor (PID) failed. */
2314	kIrf_Pid_Read_Failed = 0x27,
2315	/** PID reserved bits invalid. */
2316	kIrf_Pid_Rsvd = 0x28,
2317	/** Untranslated interrupt requested (without PASID) is invalid. */
2318	kIrf_Ir_Without_Pasid_Invalid = 0x29
2319	} VTD_IR_FAULT_T;
2320	/** @} */
2321
2322
2323	/** @name ACPI_DMAR_F_XXX: DMA Remapping Reporting Structure Flags.
2324	* In accordance with the Intel spec.
2325	* @{ */
2326	/** INTR_REMAP: Interrupt remapping supported. */
2327	#define ACPI_DMAR_F_INTR_REMAP RT_BIT(0)
2328	/** X2APIC_OPT_OUT: Request system software to opt-out of enabling x2APIC. */
2329	#define ACPI_DMAR_F_X2APIC_OPT_OUT RT_BIT(1)
2330	/** DMA_CTRL_PLATFORM_OPT_IN_FLAG: Firmware initiated DMA restricted to reserved
2331	* memory regions (RMRR). */
2332	#define ACPI_DMAR_F_DMA_CTRL_PLATFORM_OPT_IN RT_BIT(2)
2333	/** @} */
2334
2335
2336	/** @name ACPI_DRHD_F_XXX: DMA-Remapping Hardware Unit Definition Flags.
2337	* In accordance with the Intel spec.
2338	* @{ */
2339	/** INCLUDE_PCI_ALL: All PCI devices under scope. */
2340	#define ACPI_DRHD_F_INCLUDE_PCI_ALL RT_BIT(0)
2341	/** @} */
2342
2343
2344	/**
2345	* DRHD: DMA-Remapping Hardware Unit Definition.
2346	* In accordance with the Intel spec.
2347	*/
2348	#pragma pack(1)
2349	typedef struct ACPIDRHD
2350	{
2351	/** Type (must be 0=DRHD). */
2352	uint16_t uType;
2353	/** Length (must be 16 + size of device scope structure). */
2354	uint16_t cbLength;
2355	/** Flags, see ACPI_DRHD_F_XXX. */
2356	uint8_t fFlags;
2357	/** Reserved (MBZ). */
2358	uint8_t bRsvd;
2359	/** PCI segment number. */
2360	uint16_t uPciSegment;
2361	/** Register Base Address (MMIO). */
2362	uint64_t uRegBaseAddr;
2363	/* Device Scope[] Structures follow. */
2364	} ACPIDRHD;
2365	#pragma pack()
2366	AssertCompileSize(ACPIDRHD, 16);
2367	AssertCompileMemberOffset(ACPIDRHD, cbLength, 2);
2368	AssertCompileMemberOffset(ACPIDRHD, fFlags, 4);
2369	AssertCompileMemberOffset(ACPIDRHD, uPciSegment, 6);
2370	AssertCompileMemberOffset(ACPIDRHD, uRegBaseAddr, 8);
2371
2372
2373	/** @name ACPIDMARDEVSCOPE_TYPE_XXX: Device Type.
2374	* In accordance with the Intel spec.
2375	* @{ */
2376	#define ACPIDMARDEVSCOPE_TYPE_PCI_ENDPOINT 1
2377	#define ACPIDMARDEVSCOPE_TYPE_PCI_SUB_HIERARCHY 2
2378	#define ACPIDMARDEVSCOPE_TYPE_IOAPIC 3
2379	#define ACPIDMARDEVSCOPE_TYPE_MSI_CAP_HPET 4
2380	#define ACPIDMARDEVSCOPE_TYPE_ACPI_NAMESPACE_DEV 5
2381	/** @} */
2382
2383
2384	/**
2385	* ACPI Device Scope Structure - PCI device path.
2386	* In accordance with the Intel spec.
2387	*/
2388	typedef struct ACPIDEVSCOPEPATH
2389	{
2390	/** PCI device number. */
2391	uint8_t uDevice;
2392	/** PCI function number. */
2393	uint8_t uFunction;
2394	} ACPIDEVSCOPEPATH;
2395	AssertCompileSize(ACPIDEVSCOPEPATH, 2);
2396
2397
2398	/**
2399	* Device Scope Structure.
2400	* In accordance with the Intel spec.
2401	*/
2402	#pragma pack(1)
2403	typedef struct ACPIDMARDEVSCOPE
2404	{
2405	/** Type, see ACPIDMARDEVSCOPE_TYPE_XXX. */
2406	uint8_t uType;
2407	/** Length (must be 6 + size of auPath field). */
2408	uint8_t cbLength;
2409	/** Reserved (MBZ). */
2410	uint8_t abRsvd[2];
2411	/** Enumeration ID (for I/O APIC, HPET and ACPI namespace devices). */
2412	uint8_t idEnum;
2413	/** First bus number for this device. */
2414	uint8_t uStartBusNum;
2415	/** Hierarchical path from the Host Bridge to the device. */
2416	ACPIDEVSCOPEPATH Path;
2417	} ACPIDMARDEVSCOPE;
2418	#pragma pack()
2419	AssertCompileMemberOffset(ACPIDMARDEVSCOPE, cbLength, 1);
2420	AssertCompileMemberOffset(ACPIDMARDEVSCOPE, idEnum, 4);
2421	AssertCompileMemberOffset(ACPIDMARDEVSCOPE, uStartBusNum, 5);
2422	AssertCompileMemberOffset(ACPIDMARDEVSCOPE, Path, 6);
2423
2424	/** ACPI DMAR revision (not the OEM revision field).
2425	* In accordance with the Intel spec. */
2426	#define ACPI_DMAR_REVISION 1
2427
2428
2429	#endif /* !VBOX_INCLUDED_iommu_intel_h */
2430

Note: See TracBrowser for help on using the repository browser.

source: vbox/trunk/include/VBox/iommu-intel.h@ 88893

Download in other formats: