VirtualBox

source: vbox/trunk/include/VBox/iommu-intel.h@ 89235

Last change on this file since 89235 was 89235, checked in by vboxsync, 4 years ago

Intel IOMMU: bugref:9967 Address translation, WIP.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 131.5 KB
Line 
1/** @file
2 * IOMMU - Input/Output Memory Management Unit (Intel).
3 */
4
5/*
6 * Copyright (C) 2021 Oracle Corporation
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * The contents of this file may alternatively be used under the terms
17 * of the Common Development and Distribution License Version 1.0
18 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19 * VirtualBox OSE distribution, in which case the provisions of the
20 * CDDL are applicable instead of those of the GPL.
21 *
22 * You may elect to license modified versions of this file under the
23 * terms and conditions of either the GPL or the CDDL or both.
24 */
25
26#ifndef VBOX_INCLUDED_iommu_intel_h
27#define VBOX_INCLUDED_iommu_intel_h
28#ifndef RT_WITHOUT_PRAGMA_ONCE
29# pragma once
30#endif
31
32#include <iprt/assertcompile.h>
33#include <iprt/types.h>
34
35
36/**
37 * @name MMIO register offsets.
38 * In accordance with the Intel spec.
39 * @{
40 */
41#define VTD_MMIO_OFF_VER_REG 0x000 /**< Version. */
42#define VTD_MMIO_OFF_CAP_REG 0x008 /**< Capability. */
43#define VTD_MMIO_OFF_ECAP_REG 0x010 /**< Extended Capability. */
44#define VTD_MMIO_OFF_GCMD_REG 0x018 /**< Global Command. */
45#define VTD_MMIO_OFF_GSTS_REG 0x01c /**< Global Status. */
46#define VTD_MMIO_OFF_RTADDR_REG 0x020 /**< Root Table Address. */
47#define VTD_MMIO_OFF_CCMD_REG 0x028 /**< Context Command. */
48
49#define VTD_MMIO_OFF_FSTS_REG 0x034 /**< Fault Status.*/
50#define VTD_MMIO_OFF_FECTL_REG 0x038 /**< Fault Event Control.*/
51#define VTD_MMIO_OFF_FEDATA_REG 0x03c /**< Fault Event Data. */
52#define VTD_MMIO_OFF_FEADDR_REG 0x040 /**< Fault Event Address. */
53#define VTD_MMIO_OFF_FEUADDR_REG 0x044 /**< Fault Event Upper Address. */
54
55#define VTD_MMIO_OFF_AFLOG_REG 0x058 /**< Advance Fault Log. */
56
57#define VTD_MMIO_OFF_PMEN_REG 0x064 /**< Protected Memory Enable (PMEN). */
58#define VTD_MMIO_OFF_PLMBASE_REG 0x068 /**< Protected Low Memory Base. */
59#define VTD_MMIO_OFF_PLMLIMIT_REG 0x06c /**< Protected Low Memory Limit. */
60#define VTD_MMIO_OFF_PHMBASE_REG 0x070 /**< Protected High Memory Base. */
61#define VTD_MMIO_OFF_PHMLIMIT_REG 0x078 /**< Protected High Memory Limit. */
62
63#define VTD_MMIO_OFF_IQH_REG 0x080 /**< Invalidation Queue Head. */
64#define VTD_MMIO_OFF_IQT_REG 0x088 /**< Invalidation Queue Tail. */
65#define VTD_MMIO_OFF_IQA_REG 0x090 /**< Invalidation Queue Address. */
66#define VTD_MMIO_OFF_ICS_REG 0x09c /**< Invalidation Completion Status. */
67#define VTD_MMIO_OFF_IECTL_REG 0x0a0 /**< Invalidation Completion Event Control. */
68#define VTD_MMIO_OFF_IEDATA_REG 0x0a4 /**< Invalidation Completion Event Data. */
69#define VTD_MMIO_OFF_IEADDR_REG 0x0a8 /**< Invalidation Completion Event Address. */
70#define VTD_MMIO_OFF_IEUADDR_REG 0x0ac /**< Invalidation Completion Event Upper Address. */
71#define VTD_MMIO_OFF_IQERCD_REG 0x0b0 /**< Invalidation Queue Error Record. */
72
73#define VTD_MMIO_OFF_IRTA_REG 0x0b8 /**< Interrupt Remapping Table Address. */
74
75#define VTD_MMIO_OFF_PQH_REG 0x0c0 /**< Page Request Queue Head. */
76#define VTD_MMIO_OFF_PQT_REG 0x0c8 /**< Page Request Queue Tail. */
77#define VTD_MMIO_OFF_PQA_REG 0x0d0 /**< Page Request Queue Address. */
78#define VTD_MMIO_OFF_PRS_REG 0x0dc /**< Page Request Status. */
79#define VTD_MMIO_OFF_PECTL_REG 0x0e0 /**< Page Request Event Control. */
80#define VTD_MMIO_OFF_PEDATA_REG 0x0e4 /**< Page Request Event Data. */
81#define VTD_MMIO_OFF_PEADDR_REG 0x0e8 /**< Page Request Event Address. */
82#define VTD_MMIO_OFF_PEUADDR_REG 0x0ec /**< Page Request Event Upper Address. */
83
84#define VTD_MMIO_OFF_MTRRCAP_REG 0x100 /**< MTRR Capabliity. */
85#define VTD_MMIO_OFF_MTRRDEF_REG 0x108 /**< MTRR Default Type. */
86
87#define VTD_MMIO_OFF_MTRR_FIX64_00000_REG 0x120 /**< Fixed-range MTRR Register for 64K at 00000. */
88#define VTD_MMIO_OFF_MTRR_FIX16K_80000_REG 0x128 /**< Fixed-range MTRR Register for 16K at 80000. */
89#define VTD_MMIO_OFF_MTRR_FIX16K_A0000_REG 0x130 /**< Fixed-range MTRR Register for 16K at a0000. */
90#define VTD_MMIO_OFF_MTRR_FIX4K_C0000_REG 0x138 /**< Fixed-range MTRR Register for 4K at c0000. */
91#define VTD_MMIO_OFF_MTRR_FIX4K_C8000_REG 0x140 /**< Fixed-range MTRR Register for 4K at c8000. */
92#define VTD_MMIO_OFF_MTRR_FIX4K_D0000_REG 0x148 /**< Fixed-range MTRR Register for 4K at d0000. */
93#define VTD_MMIO_OFF_MTRR_FIX4K_D8000_REG 0x150 /**< Fixed-range MTRR Register for 4K at d8000. */
94#define VTD_MMIO_OFF_MTRR_FIX4K_E0000_REG 0x158 /**< Fixed-range MTRR Register for 4K at e0000. */
95#define VTD_MMIO_OFF_MTRR_FIX4K_E8000_REG 0x160 /**< Fixed-range MTRR Register for 4K at e8000. */
96#define VTD_MMIO_OFF_MTRR_FIX4K_F0000_REG 0x168 /**< Fixed-range MTRR Register for 4K at f0000. */
97#define VTD_MMIO_OFF_MTRR_FIX4K_F8000_REG 0x170 /**< Fixed-range MTRR Register for 4K at f8000. */
98
99#define VTD_MMIO_OFF_MTRR_PHYSBASE0_REG 0x180 /**< Variable-range MTRR Base 0. */
100#define VTD_MMIO_OFF_MTRR_PHYSMASK0_REG 0x188 /**< Variable-range MTRR Mask 0. */
101#define VTD_MMIO_OFF_MTRR_PHYSBASE1_REG 0x190 /**< Variable-range MTRR Base 1. */
102#define VTD_MMIO_OFF_MTRR_PHYSMASK1_REG 0x198 /**< Variable-range MTRR Mask 1. */
103#define VTD_MMIO_OFF_MTRR_PHYSBASE2_REG 0x1a0 /**< Variable-range MTRR Base 2. */
104#define VTD_MMIO_OFF_MTRR_PHYSMASK2_REG 0x1a8 /**< Variable-range MTRR Mask 2. */
105#define VTD_MMIO_OFF_MTRR_PHYSBASE3_REG 0x1b0 /**< Variable-range MTRR Base 3. */
106#define VTD_MMIO_OFF_MTRR_PHYSMASK3_REG 0x1b8 /**< Variable-range MTRR Mask 3. */
107#define VTD_MMIO_OFF_MTRR_PHYSBASE4_REG 0x1c0 /**< Variable-range MTRR Base 4. */
108#define VTD_MMIO_OFF_MTRR_PHYSMASK4_REG 0x1c8 /**< Variable-range MTRR Mask 4. */
109#define VTD_MMIO_OFF_MTRR_PHYSBASE5_REG 0x1d0 /**< Variable-range MTRR Base 5. */
110#define VTD_MMIO_OFF_MTRR_PHYSMASK5_REG 0x1d8 /**< Variable-range MTRR Mask 5. */
111#define VTD_MMIO_OFF_MTRR_PHYSBASE6_REG 0x1e0 /**< Variable-range MTRR Base 6. */
112#define VTD_MMIO_OFF_MTRR_PHYSMASK6_REG 0x1e8 /**< Variable-range MTRR Mask 6. */
113#define VTD_MMIO_OFF_MTRR_PHYSBASE7_REG 0x1f0 /**< Variable-range MTRR Base 7. */
114#define VTD_MMIO_OFF_MTRR_PHYSMASK7_REG 0x1f8 /**< Variable-range MTRR Mask 7. */
115#define VTD_MMIO_OFF_MTRR_PHYSBASE8_REG 0x200 /**< Variable-range MTRR Base 8. */
116#define VTD_MMIO_OFF_MTRR_PHYSMASK8_REG 0x208 /**< Variable-range MTRR Mask 8. */
117#define VTD_MMIO_OFF_MTRR_PHYSBASE9_REG 0x210 /**< Variable-range MTRR Base 9. */
118#define VTD_MMIO_OFF_MTRR_PHYSMASK9_REG 0x218 /**< Variable-range MTRR Mask 9. */
119
120#define VTD_MMIO_OFF_VCCAP_REG 0xe00 /**< Virtual Command Capability. */
121#define VTD_MMIO_OFF_VCMD_REG 0xe10 /**< Virtual Command. */
122#define VTD_MMIO_OFF_VCMDRSVD_REG 0xe18 /**< Reserved for future for Virtual Command. */
123#define VTD_MMIO_OFF_VCRSP_REG 0xe20 /**< Virtual Command Response. */
124#define VTD_MMIO_OFF_VCRSPRSVD_REG 0xe28 /**< Reserved for future for Virtual Command Response. */
125/** @} */
126
127
128/** @name Root Entry.
129 * In accordance with the Intel spec.
130 * @{ */
131/** P: Present. */
132#define VTD_BF_0_ROOT_ENTRY_P_SHIFT 0
133#define VTD_BF_0_ROOT_ENTRY_P_MASK UINT64_C(0x0000000000000001)
134/** R: Reserved (bits 11:1). */
135#define VTD_BF_0_ROOT_ENTRY_RSVD_11_1_SHIFT 1
136#define VTD_BF_0_ROOT_ENTRY_RSVD_11_1_MASK UINT64_C(0x0000000000000ffe)
137/** CTP: Context-Table Pointer. */
138#define VTD_BF_0_ROOT_ENTRY_CTP_SHIFT 12
139#define VTD_BF_0_ROOT_ENTRY_CTP_MASK UINT64_C(0xfffffffffffff000)
140RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_ROOT_ENTRY_, UINT64_C(0), UINT64_MAX,
141 (P, RSVD_11_1, CTP));
142
143/** Root Entry. */
144typedef struct VTD_ROOT_ENTRY_T
145{
146 /** The qwords in the root entry. */
147 uint64_t au64[2];
148} VTD_ROOT_ENTRY_T;
149/** Pointer to a root entry. */
150typedef VTD_ROOT_ENTRY_T *PVTD_ROOT_ENTRY_T;
151/** Pointer to a const root entry. */
152typedef VTD_ROOT_ENTRY_T const *PCVTD_ROOT_ENTRY_T;
153/** @} */
154
155
156/** @name Scalable-mode Root Entry.
157 * In accordance with the Intel spec.
158 * @{ */
159/** LP: Lower Present. */
160#define VTD_BF_0_SM_ROOT_ENTRY_LP_SHIFT 0
161#define VTD_BF_0_SM_ROOT_ENTRY_LP_MASK UINT64_C(0x0000000000000001)
162/** R: Reserved (bits 11:1). */
163#define VTD_BF_0_SM_ROOT_ENTRY_RSVD_11_1_SHIFT 1
164#define VTD_BF_0_SM_ROOT_ENTRY_RSVD_11_1_MASK UINT64_C(0x0000000000000ffe)
165/** LCTP: Lower Context-Table Pointer */
166#define VTD_BF_0_SM_ROOT_ENTRY_LCTP_SHIFT 12
167#define VTD_BF_0_SM_ROOT_ENTRY_LCTP_MASK UINT64_C(0xfffffffffffff000)
168RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_SM_ROOT_ENTRY_, UINT64_C(0), UINT64_MAX,
169 (LP, RSVD_11_1, LCTP));
170
171/** UP: Upper Present. */
172#define VTD_BF_1_SM_ROOT_ENTRY_UP_SHIFT 0
173#define VTD_BF_1_SM_ROOT_ENTRY_UP_MASK UINT64_C(0x0000000000000001)
174/** R: Reserved (bits 11:1). */
175#define VTD_BF_1_SM_ROOT_ENTRY_RSVD_11_1_SHIFT 1
176#define VTD_BF_1_SM_ROOT_ENTRY_RSVD_11_1_MASK UINT64_C(0x0000000000000ffe)
177/** UCTP: Upper Context-Table Pointer. */
178#define VTD_BF_1_SM_ROOT_ENTRY_UCTP_SHIFT 12
179#define VTD_BF_1_SM_ROOT_ENTRY_UCTP_MASK UINT64_C(0xfffffffffffff000)
180RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_SM_ROOT_ENTRY_, UINT64_C(0), UINT64_MAX,
181 (UP, RSVD_11_1, UCTP));
182
183/** Scalable-mode root entry. */
184typedef struct VTD_SM_ROOT_ENTRY_T
185{
186 /** The lower scalable-mode root entry. */
187 uint64_t uLower;
188 /** The upper scalable-mode root entry. */
189 uint64_t uUpper;
190} VTD_SM_ROOT_ENTRY_T;
191/** Pointer to a scalable-mode root entry. */
192typedef VTD_SM_ROOT_ENTRY_T *PVTD_SM_ROOT_ENTRY_T;
193/** Pointer to a const scalable-mode root entry. */
194typedef VTD_SM_ROOT_ENTRY_T const *PCVTD_SM_ROOT_ENTRY_T;
195/** @} */
196
197
198/** @name Context Entry.
199 * In accordance with the Intel spec.
200 * @{ */
201/** P: Present. */
202#define VTD_BF_0_CONTEXT_ENTRY_P_SHIFT 0
203#define VTD_BF_0_CONTEXT_ENTRY_P_MASK UINT64_C(0x0000000000000001)
204/** FPD: Fault Processing Disable. */
205#define VTD_BF_0_CONTEXT_ENTRY_FPD_SHIFT 1
206#define VTD_BF_0_CONTEXT_ENTRY_FPD_MASK UINT64_C(0x0000000000000002)
207/** TT: Translation Type. */
208#define VTD_BF_0_CONTEXT_ENTRY_TT_SHIFT 2
209#define VTD_BF_0_CONTEXT_ENTRY_TT_MASK UINT64_C(0x000000000000000c)
210/** R: Reserved (bits 11:4). */
211#define VTD_BF_0_CONTEXT_ENTRY_RSVD_11_4_SHIFT 4
212#define VTD_BF_0_CONTEXT_ENTRY_RSVD_11_4_MASK UINT64_C(0x0000000000000ff0)
213/** SLPTPTR: Second Level Page Translation Pointer. */
214#define VTD_BF_0_CONTEXT_ENTRY_SLPTPTR_SHIFT 12
215#define VTD_BF_0_CONTEXT_ENTRY_SLPTPTR_MASK UINT64_C(0xfffffffffffff000)
216RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_CONTEXT_ENTRY_, UINT64_C(0), UINT64_MAX,
217 (P, FPD, TT, RSVD_11_4, SLPTPTR));
218
219/** AW: Address Width. */
220#define VTD_BF_1_CONTEXT_ENTRY_AW_SHIFT 0
221#define VTD_BF_1_CONTEXT_ENTRY_AW_MASK UINT64_C(0x0000000000000007)
222/** IGN: Ignored (bits 6:3). */
223#define VTD_BF_1_CONTEXT_ENTRY_IGN_6_3_SHIFT 3
224#define VTD_BF_1_CONTEXT_ENTRY_IGN_6_3_MASK UINT64_C(0x0000000000000078)
225/** R: Reserved (bit 7). */
226#define VTD_BF_1_CONTEXT_ENTRY_RSVD_7_SHIFT 7
227#define VTD_BF_1_CONTEXT_ENTRY_RSVD_7_MASK UINT64_C(0x0000000000000080)
228/** DID: Domain Identifier. */
229#define VTD_BF_1_CONTEXT_ENTRY_DID_SHIFT 8
230#define VTD_BF_1_CONTEXT_ENTRY_DID_MASK UINT64_C(0x0000000000ffff00)
231/** R: Reserved (bits 63:24). */
232#define VTD_BF_1_CONTEXT_ENTRY_RSVD_63_24_SHIFT 24
233#define VTD_BF_1_CONTEXT_ENTRY_RSVD_63_24_MASK UINT64_C(0xffffffffff000000)
234RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_CONTEXT_ENTRY_, UINT64_C(0), UINT64_MAX,
235 (AW, IGN_6_3, RSVD_7, DID, RSVD_63_24));
236
237/** Context Entry. */
238typedef struct VTD_CONTEXT_ENTRY_T
239{
240 /** The qwords in the context entry. */
241 uint64_t au64[2];
242} VTD_CONTEXT_ENTRY_T;
243/** Pointer to a context entry. */
244typedef VTD_CONTEXT_ENTRY_T *PVTD_CONTEXT_ENTRY_T;
245/** Pointer to a const context entry. */
246typedef VTD_CONTEXT_ENTRY_T const *PCVTD_CONTEXT_ENTRY_T;
247/** @} */
248
249
250/** @name Scalable-mode Context Entry.
251 * In accordance with the Intel spec.
252 * @{ */
253/** P: Present. */
254#define VTD_BF_0_SM_CONTEXT_ENTRY_P_SHIFT 0
255#define VTD_BF_0_SM_CONTEXT_ENTRY_P_MASK UINT64_C(0x0000000000000001)
256/** FPD: Fault Processing Disable. */
257#define VTD_BF_0_SM_CONTEXT_ENTRY_FPD_SHIFT 1
258#define VTD_BF_0_SM_CONTEXT_ENTRY_FPD_MASK UINT64_C(0x0000000000000002)
259/** DTE: Device-TLB Enable. */
260#define VTD_BF_0_SM_CONTEXT_ENTRY_DTE_SHIFT 2
261#define VTD_BF_0_SM_CONTEXT_ENTRY_DTE_MASK UINT64_C(0x0000000000000004)
262/** PASIDE: PASID Enable. */
263#define VTD_BF_0_SM_CONTEXT_ENTRY_PASIDE_SHIFT 3
264#define VTD_BF_0_SM_CONTEXT_ENTRY_PASIDE_MASK UINT64_C(0x0000000000000008)
265/** PRE: Page Request Enable. */
266#define VTD_BF_0_SM_CONTEXT_ENTRY_PRE_SHIFT 4
267#define VTD_BF_0_SM_CONTEXT_ENTRY_PRE_MASK UINT64_C(0x0000000000000010)
268/** R: Reserved (bits 8:5). */
269#define VTD_BF_0_SM_CONTEXT_ENTRY_RSVD_8_5_SHIFT 5
270#define VTD_BF_0_SM_CONTEXT_ENTRY_RSVD_8_5_MASK UINT64_C(0x00000000000001e0)
271/** PDTS: PASID Directory Size. */
272#define VTD_BF_0_SM_CONTEXT_ENTRY_PDTS_SHIFT 9
273#define VTD_BF_0_SM_CONTEXT_ENTRY_PDTS_MASK UINT64_C(0x0000000000000e00)
274/** PASIDDIRPTR: PASID Directory Pointer. */
275#define VTD_BF_0_SM_CONTEXT_ENTRY_PASIDDIRPTR_SHIFT 12
276#define VTD_BF_0_SM_CONTEXT_ENTRY_PASIDDIRPTR_MASK UINT64_C(0xfffffffffffff000)
277RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_SM_CONTEXT_ENTRY_, UINT64_C(0), UINT64_MAX,
278 (P, FPD, DTE, PASIDE, PRE, RSVD_8_5, PDTS, PASIDDIRPTR));
279
280/** RID_PASID: Requested Id to PASID assignment. */
281#define VTD_BF_1_SM_CONTEXT_ENTRY_RID_PASID_SHIFT 0
282#define VTD_BF_1_SM_CONTEXT_ENTRY_RID_PASID_MASK UINT64_C(0x00000000000fffff)
283/** RID_PRIV: Requested Id to PrivilegeModeRequested assignment. */
284#define VTD_BF_1_SM_CONTEXT_ENTRY_RID_PRIV_SHIFT 20
285#define VTD_BF_1_SM_CONTEXT_ENTRY_RID_PRIV_MASK UINT64_C(0x0000000000100000)
286/** R: Reserved (bits 63:21). */
287#define VTD_BF_1_SM_CONTEXT_ENTRY_RSVD_63_21_SHIFT 21
288#define VTD_BF_1_SM_CONTEXT_ENTRY_RSVD_63_21_MASK UINT64_C(0xffffffffffe00000)
289RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_SM_CONTEXT_ENTRY_, UINT64_C(0), UINT64_MAX,
290 (RID_PASID, RID_PRIV, RSVD_63_21));
291
292/** Context Entry. */
293typedef struct VTD_SM_CONTEXT_ENTRY_T
294{
295 /** The qwords in the scalable-mode context entry. */
296 uint64_t au64[4];
297} VTD_SM_CONTEXT_ENTRY_T;
298/** Pointer to a scalable-mode context entry. */
299typedef VTD_SM_CONTEXT_ENTRY_T *PVTD_SM_CONTEXT_ENTRY_T;
300/** Pointer to a const scalable-mode context entry. */
301typedef VTD_SM_CONTEXT_ENTRY_T const *PCVTD_SM_CONTEXT_ENTRY_T;
302/** @} */
303
304
305/** @name Scalable-mode PASID Directory Entry.
306 * In accordance with the Intel spec.
307 * @{ */
308/** P: Present. */
309#define VTD_BF_SM_PASID_DIR_ENTRY_P_SHIFT 0
310#define VTD_BF_SM_PASID_DIR_ENTRY_P_MASK UINT64_C(0x0000000000000001)
311/** FPD: Fault Processing Disable. */
312#define VTD_BF_SM_PASID_DIR_ENTRY_FPD_SHIFT 1
313#define VTD_BF_SM_PASID_DIR_ENTRY_FPD_MASK UINT64_C(0x0000000000000002)
314/** R: Reserved (bits 11:2). */
315#define VTD_BF_SM_PASID_DIR_ENTRY_RSVD_11_2_SHIFT 2
316#define VTD_BF_SM_PASID_DIR_ENTRY_RSVD_11_2_MASK UINT64_C(0x0000000000000ffc)
317/** SMPTBLPTR: Scalable Mode PASID Table Pointer. */
318#define VTD_BF_SM_PASID_DIR_ENTRY_SMPTBLPTR_SHIFT 12
319#define VTD_BF_SM_PASID_DIR_ENTRY_SMPTBLPTR_MASK UINT64_C(0xfffffffffffff000)
320RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_SM_PASID_DIR_ENTRY_, UINT64_C(0), UINT64_MAX,
321 (P, FPD, RSVD_11_2, SMPTBLPTR));
322
323/** Scalable-mode PASID Directory Entry. */
324typedef struct VTD_SM_PASID_DIR_ENTRY_T
325{
326 /** The scalable-mode PASID directory entry. */
327 uint64_t u;
328} VTD_SM_PASID_DIR_ENTRY_T;
329/** Pointer to a scalable-mode PASID directory entry. */
330typedef VTD_SM_PASID_DIR_ENTRY_T *PVTD_SM_PASID_DIR_ENTRY_T;
331/** Pointer to a const scalable-mode PASID directory entry. */
332typedef VTD_SM_PASID_DIR_ENTRY_T const *PCVTD_SM_PASID_DIR_ENTRY_T;
333/** @} */
334
335
336/** @name Scalable-mode PASID Table Entry.
337 * In accordance with the Intel spec.
338 * @{ */
339/** P: Present. */
340#define VTD_BF_0_SM_PASID_TBL_ENTRY_P_SHIFT 0
341#define VTD_BF_0_SM_PASID_TBL_ENTRY_P_MASK UINT64_C(0x0000000000000001)
342/** FPD: Fault Processing Disable. */
343#define VTD_BF_0_SM_PASID_TBL_ENTRY_FPD_SHIFT 1
344#define VTD_BF_0_SM_PASID_TBL_ENTRY_FPD_MASK UINT64_C(0x0000000000000002)
345/** AW: Address Width. */
346#define VTD_BF_0_SM_PASID_TBL_ENTRY_AW_SHIFT 2
347#define VTD_BF_0_SM_PASID_TBL_ENTRY_AW_MASK UINT64_C(0x000000000000001c)
348/** SLEE: Second-Level Execute Enable. */
349#define VTD_BF_0_SM_PASID_TBL_ENTRY_SLEE_SHIFT 5
350#define VTD_BF_0_SM_PASID_TBL_ENTRY_SLEE_MASK UINT64_C(0x0000000000000020)
351/** PGTT: PASID Granular Translation Type. */
352#define VTD_BF_0_SM_PASID_TBL_ENTRY_PGTT_SHIFT 6
353#define VTD_BF_0_SM_PASID_TBL_ENTRY_PGTT_MASK UINT64_C(0x00000000000001c0)
354/** SLADE: Second-Level Address/Dirty Enable. */
355#define VTD_BF_0_SM_PASID_TBL_ENTRY_SLADE_SHIFT 9
356#define VTD_BF_0_SM_PASID_TBL_ENTRY_SLADE_MASK UINT64_C(0x0000000000000200)
357/** R: Reserved (bits 11:10). */
358#define VTD_BF_0_SM_PASID_TBL_ENTRY_RSVD_11_10_SHIFT 10
359#define VTD_BF_0_SM_PASID_TBL_ENTRY_RSVD_11_10_MASK UINT64_C(0x0000000000000c00)
360/** SLPTPTR: Second-Level Page Table Pointer. */
361#define VTD_BF_0_SM_PASID_TBL_ENTRY_SLPTPTR_SHIFT 12
362#define VTD_BF_0_SM_PASID_TBL_ENTRY_SLPTPTR_MASK UINT64_C(0xfffffffffffff000)
363RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_SM_PASID_TBL_ENTRY_, UINT64_C(0), UINT64_MAX,
364 (P, FPD, AW, SLEE, PGTT, SLADE, RSVD_11_10, SLPTPTR));
365
366/** DID: Domain Identifer. */
367#define VTD_BF_1_SM_PASID_TBL_ENTRY_DID_SHIFT 0
368#define VTD_BF_1_SM_PASID_TBL_ENTRY_DID_MASK UINT64_C(0x000000000000ffff)
369/** R: Reserved (bits 22:16). */
370#define VTD_BF_1_SM_PASID_TBL_ENTRY_RSVD_22_16_SHIFT 16
371#define VTD_BF_1_SM_PASID_TBL_ENTRY_RSVD_22_16_MASK UINT64_C(0x00000000007f0000)
372/** PWSNP: Page-Walk Snoop. */
373#define VTD_BF_1_SM_PASID_TBL_ENTRY_PWSNP_SHIFT 23
374#define VTD_BF_1_SM_PASID_TBL_ENTRY_PWSNP_MASK UINT64_C(0x0000000000800000)
375/** PGSNP: Page Snoop. */
376#define VTD_BF_1_SM_PASID_TBL_ENTRY_PGSNP_SHIFT 24
377#define VTD_BF_1_SM_PASID_TBL_ENTRY_PGSNP_MASK UINT64_C(0x0000000001000000)
378/** CD: Cache Disable. */
379#define VTD_BF_1_SM_PASID_TBL_ENTRY_CD_SHIFT 25
380#define VTD_BF_1_SM_PASID_TBL_ENTRY_CD_MASK UINT64_C(0x0000000002000000)
381/** EMTE: Extended Memory Type Enable. */
382#define VTD_BF_1_SM_PASID_TBL_ENTRY_EMTE_SHIFT 26
383#define VTD_BF_1_SM_PASID_TBL_ENTRY_EMTE_MASK UINT64_C(0x0000000004000000)
384/** EMT: Extended Memory Type. */
385#define VTD_BF_1_SM_PASID_TBL_ENTRY_EMT_SHIFT 27
386#define VTD_BF_1_SM_PASID_TBL_ENTRY_EMT_MASK UINT64_C(0x0000000038000000)
387/** PWT: Page-Level Write Through. */
388#define VTD_BF_1_SM_PASID_TBL_ENTRY_PWT_SHIFT 30
389#define VTD_BF_1_SM_PASID_TBL_ENTRY_PWT_MASK UINT64_C(0x0000000040000000)
390/** PCD: Page-Level Cache Disable. */
391#define VTD_BF_1_SM_PASID_TBL_ENTRY_PCD_SHIFT 31
392#define VTD_BF_1_SM_PASID_TBL_ENTRY_PCD_MASK UINT64_C(0x0000000080000000)
393/** PAT: Page Attribute Table. */
394#define VTD_BF_1_SM_PASID_TBL_ENTRY_PAT_SHIFT 32
395#define VTD_BF_1_SM_PASID_TBL_ENTRY_PAT_MASK UINT64_C(0xffffffff00000000)
396RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_SM_PASID_TBL_ENTRY_, UINT64_C(0), UINT64_MAX,
397 (DID, RSVD_22_16, PWSNP, PGSNP, CD, EMTE, EMT, PWT, PCD, PAT));
398
399/** SRE: Supervisor Request Enable. */
400#define VTD_BF_2_SM_PASID_TBL_ENTRY_SRE_SHIFT 0
401#define VTD_BF_2_SM_PASID_TBL_ENTRY_SRE_MASK UINT64_C(0x0000000000000001)
402/** ERE: Execute Request Enable. */
403#define VTD_BF_2_SM_PASID_TBL_ENTRY_ERE_SHIFT 1
404#define VTD_BF_2_SM_PASID_TBL_ENTRY_ERE_MASK UINT64_C(0x0000000000000002)
405/** FLPM: First Level Paging Mode. */
406#define VTD_BF_2_SM_PASID_TBL_ENTRY_FLPM_SHIFT 2
407#define VTD_BF_2_SM_PASID_TBL_ENTRY_FLPM_MASK UINT64_C(0x000000000000000c)
408/** WPE: Write Protect Enable. */
409#define VTD_BF_2_SM_PASID_TBL_ENTRY_WPE_SHIFT 4
410#define VTD_BF_2_SM_PASID_TBL_ENTRY_WPE_MASK UINT64_C(0x0000000000000010)
411/** NXE: No-Execute Enable. */
412#define VTD_BF_2_SM_PASID_TBL_ENTRY_NXE_SHIFT 5
413#define VTD_BF_2_SM_PASID_TBL_ENTRY_NXE_MASK UINT64_C(0x0000000000000020)
414/** SMEP: Supervisor Mode Execute Prevent. */
415#define VTD_BF_2_SM_PASID_TBL_ENTRY_SMPE_SHIFT 6
416#define VTD_BF_2_SM_PASID_TBL_ENTRY_SMPE_MASK UINT64_C(0x0000000000000040)
417/** EAFE: Extended Accessed Flag Enable. */
418#define VTD_BF_2_SM_PASID_TBL_ENTRY_EAFE_SHIFT 7
419#define VTD_BF_2_SM_PASID_TBL_ENTRY_EAFE_MASK UINT64_C(0x0000000000000080)
420/** R: Reserved (bits 11:8). */
421#define VTD_BF_2_SM_PASID_TBL_ENTRY_RSVD_11_8_SHIFT 8
422#define VTD_BF_2_SM_PASID_TBL_ENTRY_RSVD_11_8_MASK UINT64_C(0x0000000000000f00)
423/** FLPTPTR: First Level Page Table Pointer. */
424#define VTD_BF_2_SM_PASID_TBL_ENTRY_FLPTPTR_SHIFT 12
425#define VTD_BF_2_SM_PASID_TBL_ENTRY_FLPTPTR_MASK UINT64_C(0xfffffffffffff000)
426RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_2_SM_PASID_TBL_ENTRY_, UINT64_C(0), UINT64_MAX,
427 (SRE, ERE, FLPM, WPE, NXE, SMPE, EAFE, RSVD_11_8, FLPTPTR));
428
429/** Scalable-mode PASID Table Entry. */
430typedef struct VTD_SM_PASID_TBL_ENTRY_T
431{
432 /** The qwords in the scalable-mode PASID table entry. */
433 uint64_t au64[8];
434} VTD_SM_PASID_TBL_ENTRY_T;
435/** Pointer to a scalable-mode PASID table entry. */
436typedef VTD_SM_PASID_TBL_ENTRY_T *PVTD_SM_PASID_TBL_ENTRY_T;
437/** Pointer to a const scalable-mode PASID table entry. */
438typedef VTD_SM_PASID_TBL_ENTRY_T const *PCVTD_SM_PASID_TBL_ENTRY_T;
439/** @} */
440
441
442/** @name First-Level Paging Entry.
443 * In accordance with the Intel spec.
444 * @{ */
445/** P: Present. */
446#define VTD_BF_FLP_ENTRY_P_SHIFT 0
447#define VTD_BF_FLP_ENTRY_P_MASK UINT64_C(0x0000000000000001)
448/** R/W: Read/Write. */
449#define VTD_BF_FLP_ENTRY_RW_SHIFT 1
450#define VTD_BF_FLP_ENTRY_RW_MASK UINT64_C(0x0000000000000002)
451/** U/S: User/Supervisor. */
452#define VTD_BF_FLP_ENTRY_US_SHIFT 2
453#define VTD_BF_FLP_ENTRY_US_MASK UINT64_C(0x0000000000000004)
454/** PWT: Page-Level Write Through. */
455#define VTD_BF_FLP_ENTRY_PWT_SHIFT 3
456#define VTD_BF_FLP_ENTRY_PWT_MASK UINT64_C(0x0000000000000008)
457/** PC: Page-Level Cache Disable. */
458#define VTD_BF_FLP_ENTRY_PCD_SHIFT 4
459#define VTD_BF_FLP_ENTRY_PCD_MASK UINT64_C(0x0000000000000010)
460/** A: Accessed. */
461#define VTD_BF_FLP_ENTRY_A_SHIFT 5
462#define VTD_BF_FLP_ENTRY_A_MASK UINT64_C(0x0000000000000020)
463/** IGN: Ignored (bit 6). */
464#define VTD_BF_FLP_ENTRY_IGN_6_SHIFT 6
465#define VTD_BF_FLP_ENTRY_IGN_6_MASK UINT64_C(0x0000000000000040)
466/** R: Reserved (bit 7). */
467#define VTD_BF_FLP_ENTRY_RSVD_7_SHIFT 7
468#define VTD_BF_FLP_ENTRY_RSVD_7_MASK UINT64_C(0x0000000000000080)
469/** IGN: Ignored (bits 9:8). */
470#define VTD_BF_FLP_ENTRY_IGN_9_8_SHIFT 8
471#define VTD_BF_FLP_ENTRY_IGN_9_8_MASK UINT64_C(0x0000000000000300)
472/** EA: Extended Accessed. */
473#define VTD_BF_FLP_ENTRY_EA_SHIFT 10
474#define VTD_BF_FLP_ENTRY_EA_MASK UINT64_C(0x0000000000000400)
475/** IGN: Ignored (bit 11). */
476#define VTD_BF_FLP_ENTRY_IGN_11_SHIFT 11
477#define VTD_BF_FLP_ENTRY_IGN_11_MASK UINT64_C(0x0000000000000800)
478/** ADDR: Address. */
479#define VTD_BF_FLP_ENTRY_ADDR_SHIFT 12
480#define VTD_BF_FLP_ENTRY_ADDR_MASK UINT64_C(0x000ffffffffff000)
481/** IGN: Ignored (bits 62:52). */
482#define VTD_BF_FLP_ENTRY_IGN_62_52_SHIFT 52
483#define VTD_BF_FLP_ENTRY_IGN_62_52_MASK UINT64_C(0x7ff0000000000000)
484/** XD: Execute Disabled. */
485#define VTD_BF_FLP_ENTRY_XD_SHIFT 63
486#define VTD_BF_FLP_ENTRY_XD_MASK UINT64_C(0x8000000000000000)
487RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_FLP_ENTRY_, UINT64_C(0), UINT64_MAX,
488 (P, RW, US, PWT, PCD, A, IGN_6, RSVD_7, IGN_9_8, EA, IGN_11, ADDR, IGN_62_52, XD));
489
490/** First-Level Paging Entry. */
491typedef struct VTD_FLP_ENTRY_T
492{
493 /** The first-level paging entry. */
494 uint64_t u;
495} VTD_FLP_ENTRY_T;
496/** Pointer to a first-level paging entry. */
497typedef VTD_FLP_ENTRY_T *PVTD_FLP_ENTRY_T;
498/** Pointer to a const first-level paging entry. */
499typedef VTD_FLP_ENTRY_T const *PCVTD_FLP_ENTRY_T;
500/** @} */
501
502
503/** @name Second-Level Paging Entry.
504 * In accordance with the Intel spec.
505 * @{ */
506/** R: Read. */
507#define VTD_BF_SLP_ENTRY_R_SHIFT 0
508#define VTD_BF_SLP_ENTRY_R_MASK UINT64_C(0x0000000000000001)
509/** W: Write. */
510#define VTD_BF_SLP_ENTRY_W_SHIFT 1
511#define VTD_BF_SLP_ENTRY_W_MASK UINT64_C(0x0000000000000002)
512/** X: Execute. */
513#define VTD_BF_SLP_ENTRY_X_SHIFT 2
514#define VTD_BF_SLP_ENTRY_X_MASK UINT64_C(0x0000000000000004)
515/** IGN: Ignored (bits 6:3). */
516#define VTD_BF_SLP_ENTRY_IGN_6_3_SHIFT 3
517#define VTD_BF_SLP_ENTRY_IGN_6_3_MASK UINT64_C(0x0000000000000078)
518/** R: Reserved (bit 7). */
519#define VTD_BF_SLP_ENTRY_RSVD_7_SHIFT 7
520#define VTD_BF_SLP_ENTRY_RSVD_7_MASK UINT64_C(0x0000000000000080)
521/** A: Accessed. */
522#define VTD_BF_SLP_ENTRY_A_SHIFT 8
523#define VTD_BF_SLP_ENTRY_A_MASK UINT64_C(0x0000000000000100)
524/** IGN: Ignored (bits 10:9). */
525#define VTD_BF_SLP_ENTRY_IGN_10_9_SHIFT 9
526#define VTD_BF_SLP_ENTRY_IGN_10_9_MASK UINT64_C(0x0000000000000600)
527/** R: Reserved (bit 11). */
528#define VTD_BF_SLP_ENTRY_RSVD_11_SHIFT 11
529#define VTD_BF_SLP_ENTRY_RSVD_11_MASK UINT64_C(0x0000000000000800)
530/** ADDR: Address. */
531#define VTD_BF_SLP_ENTRY_ADDR_SHIFT 12
532#define VTD_BF_SLP_ENTRY_ADDR_MASK UINT64_C(0x000ffffffffff000)
533/** IGN: Ignored (bits 61:52). */
534#define VTD_BF_SLP_ENTRY_IGN_61_52_SHIFT 52
535#define VTD_BF_SLP_ENTRY_IGN_61_52_MASK UINT64_C(0x3ff0000000000000)
536/** R: Reserved (bit 62). */
537#define VTD_BF_SLP_ENTRY_RSVD_62_SHIFT 62
538#define VTD_BF_SLP_ENTRY_RSVD_62_MASK UINT64_C(0x4000000000000000)
539/** IGN: Ignored (bit 63). */
540#define VTD_BF_SLP_ENTRY_IGN_63_SHIFT 63
541#define VTD_BF_SLP_ENTRY_IGN_63_MASK UINT64_C(0x8000000000000000)
542RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_SLP_ENTRY_, UINT64_C(0), UINT64_MAX,
543 (R, W, X, IGN_6_3, RSVD_7, A, IGN_10_9, RSVD_11, ADDR, IGN_61_52, RSVD_62, IGN_63));
544
545/** Second-Level Paging Entry. */
546typedef struct VTD_SLP_ENTRY_T
547{
548 /** The second-level paging entry. */
549 uint64_t u;
550} VTD_SLP_ENTRY_T;
551/** Pointer to a second-level paging entry. */
552typedef VTD_SLP_ENTRY_T *PVTD_SLP_ENTRY_T;
553/** Pointer to a const second-level paging entry. */
554typedef VTD_SLP_ENTRY_T const *PCVTD_SLP_ENTRY_T;
555/** @} */
556
557
558/** @name Fault Record.
559 * In accordance with the Intel spec.
560 * @{ */
561/** R: Reserved (bits 11:0). */
562#define VTD_BF_0_FAULT_RECORD_RSVD_11_0_SHIFT 0
563#define VTD_BF_0_FAULT_RECORD_RSVD_11_0_MASK UINT64_C(0x0000000000000fff)
564/** FI: Fault Information. */
565#define VTD_BF_0_FAULT_RECORD_FI_SHIFT 12
566#define VTD_BF_0_FAULT_RECORD_FI_MASK UINT64_C(0xfffffffffffff000)
567RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_FAULT_RECORD_, UINT64_C(0), UINT64_MAX,
568 (RSVD_11_0, FI));
569
570/** SID: Source identifier. */
571#define VTD_BF_1_FAULT_RECORD_SID_SHIFT 0
572#define VTD_BF_1_FAULT_RECORD_SID_MASK UINT64_C(0x000000000000ffff)
573/** R: Reserved (bits 28:16). */
574#define VTD_BF_1_FAULT_RECORD_RSVD_28_16_SHIFT 16
575#define VTD_BF_1_FAULT_RECORD_RSVD_28_16_MASK UINT64_C(0x000000001fff0000)
576/** PRIV: Privilege Mode Requested. */
577#define VTD_BF_1_FAULT_RECORD_PRIV_SHIFT 29
578#define VTD_BF_1_FAULT_RECORD_PRIV_MASK UINT64_C(0x0000000020000000)
579/** EXE: Execute Permission Requested. */
580#define VTD_BF_1_FAULT_RECORD_EXE_SHIFT 30
581#define VTD_BF_1_FAULT_RECORD_EXE_MASK UINT64_C(0x0000000040000000)
582/** PP: PASID Present. */
583#define VTD_BF_1_FAULT_RECORD_PP_SHIFT 31
584#define VTD_BF_1_FAULT_RECORD_PP_MASK UINT64_C(0x0000000080000000)
585/** FR: Fault Reason. */
586#define VTD_BF_1_FAULT_RECORD_FR_SHIFT 32
587#define VTD_BF_1_FAULT_RECORD_FR_MASK UINT64_C(0x000000ff00000000)
588/** PV: PASID Value. */
589#define VTD_BF_1_FAULT_RECORD_PV_SHIFT 40
590#define VTD_BF_1_FAULT_RECORD_PV_MASK UINT64_C(0x0fffff0000000000)
591/** AT: Address Type. */
592#define VTD_BF_1_FAULT_RECORD_AT_SHIFT 60
593#define VTD_BF_1_FAULT_RECORD_AT_MASK UINT64_C(0x3000000000000000)
594/** T: Type. */
595#define VTD_BF_1_FAULT_RECORD_T_SHIFT 62
596#define VTD_BF_1_FAULT_RECORD_T_MASK UINT64_C(0x4000000000000000)
597/** R: Reserved (bit 127). */
598#define VTD_BF_1_FAULT_RECORD_RSVD_63_SHIFT 63
599#define VTD_BF_1_FAULT_RECORD_RSVD_63_MASK UINT64_C(0x8000000000000000)
600RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_FAULT_RECORD_, UINT64_C(0), UINT64_MAX,
601 (SID, RSVD_28_16, PRIV, EXE, PP, FR, PV, AT, T, RSVD_63));
602
603/** Fault record. */
604typedef struct VTD_FAULT_RECORD_T
605{
606 /** The qwords in the fault record. */
607 uint64_t au64[2];
608} VTD_FAULT_RECORD_T;
609/** Pointer to a fault record. */
610typedef VTD_FAULT_RECORD_T *PVTD_FAULT_RECORD_T;
611/** Pointer to a const fault record. */
612typedef VTD_FAULT_RECORD_T const *PCVTD_FAULT_RECORD_T;
613/** @} */
614
615
616/** @name Interrupt Remapping Table Entry (IRTE) for Remapped Interrupts.
617 * In accordance with the Intel spec.
618 * @{ */
619/** P: Present. */
620#define VTD_BF_0_IRTE_P_SHIFT 0
621#define VTD_BF_0_IRTE_P_MASK UINT64_C(0x0000000000000001)
622/** FPD: Fault Processing Disable. */
623#define VTD_BF_0_IRTE_FPD_SHIFT 1
624#define VTD_BF_0_IRTE_FPD_MASK UINT64_C(0x0000000000000002)
625/** DM: Destination Mode (0=physical, 1=logical). */
626#define VTD_BF_0_IRTE_DM_SHIFT 2
627#define VTD_BF_0_IRTE_DM_MASK UINT64_C(0x0000000000000004)
628/** RH: Redirection Hint. */
629#define VTD_BF_0_IRTE_RH_SHIFT 3
630#define VTD_BF_0_IRTE_RH_MASK UINT64_C(0x0000000000000008)
631/** TM: Trigger Mode. */
632#define VTD_BF_0_IRTE_TM_SHIFT 4
633#define VTD_BF_0_IRTE_TM_MASK UINT64_C(0x0000000000000010)
634/** DLM: Delivery Mode. */
635#define VTD_BF_0_IRTE_DLM_SHIFT 5
636#define VTD_BF_0_IRTE_DLM_MASK UINT64_C(0x00000000000000e0)
637/** AVL: Available. */
638#define VTD_BF_0_IRTE_AVAIL_SHIFT 8
639#define VTD_BF_0_IRTE_AVAIL_MASK UINT64_C(0x0000000000000f00)
640/** R: Reserved (bits 14:12). */
641#define VTD_BF_0_IRTE_RSVD_14_12_SHIFT 12
642#define VTD_BF_0_IRTE_RSVD_14_12_MASK UINT64_C(0x0000000000007000)
643/** IM: IRTE Mode. */
644#define VTD_BF_0_IRTE_IM_SHIFT 15
645#define VTD_BF_0_IRTE_IM_MASK UINT64_C(0x0000000000008000)
646/** V: Vector. */
647#define VTD_BF_0_IRTE_V_SHIFT 16
648#define VTD_BF_0_IRTE_V_MASK UINT64_C(0x0000000000ff0000)
649/** R: Reserved (bits 31:24). */
650#define VTD_BF_0_IRTE_RSVD_31_24_SHIFT 24
651#define VTD_BF_0_IRTE_RSVD_31_24_MASK UINT64_C(0x00000000ff000000)
652/** DST: Desination Id. */
653#define VTD_BF_0_IRTE_DST_SHIFT 32
654#define VTD_BF_0_IRTE_DST_MASK UINT64_C(0xffffffff00000000)
655/** R: Reserved (bits 39:32) when EIME=0. */
656#define VTD_BF_0_IRTE_RSVD_39_32_SHIFT 32
657#define VTD_BF_0_IRTE_RSVD_39_32_MASK UINT64_C(0x000000ff00000000)
658/** DST_XAPIC: Destination Id when EIME=0. */
659#define VTD_BF_0_IRTE_DST_XAPIC_SHIFT 40
660#define VTD_BF_0_IRTE_DST_XAPIC_MASK UINT64_C(0x0000ff0000000000)
661/** R: Reserved (bits 63:48) when EIME=0. */
662#define VTD_BF_0_IRTE_RSVD_63_48_SHIFT 48
663#define VTD_BF_0_IRTE_RSVD_63_48_MASK UINT64_C(0xffff000000000000)
664RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_IRTE_, UINT64_C(0), UINT64_MAX,
665 (P, FPD, DM, RH, TM, DLM, AVAIL, RSVD_14_12, IM, V, RSVD_31_24, DST));
666RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_IRTE_, UINT64_C(0), UINT64_MAX,
667 (P, FPD, DM, RH, TM, DLM, AVAIL, RSVD_14_12, IM, V, RSVD_31_24, RSVD_39_32, DST_XAPIC, RSVD_63_48));
668
669/** SID: Source Identifier. */
670#define VTD_BF_1_IRTE_SID_SHIFT 0
671#define VTD_BF_1_IRTE_SID_MASK UINT64_C(0x000000000000ffff)
672/** SQ: Source-Id Qualifier. */
673#define VTD_BF_1_IRTE_SQ_SHIFT 16
674#define VTD_BF_1_IRTE_SQ_MASK UINT64_C(0x0000000000030000)
675/** SVT: Source Validation Type. */
676#define VTD_BF_1_IRTE_SVT_SHIFT 18
677#define VTD_BF_1_IRTE_SVT_MASK UINT64_C(0x00000000000c0000)
678/** R: Reserved (bits 127:84). */
679#define VTD_BF_1_IRTE_RSVD_63_20_SHIFT 20
680#define VTD_BF_1_IRTE_RSVD_63_20_MASK UINT64_C(0xfffffffffff00000)
681RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_IRTE_, UINT64_C(0), UINT64_MAX,
682 (SID, SQ, SVT, RSVD_63_20));
683
684/** IRTE: Qword 0 valid mask when EIME=1. */
685#define VTD_IRTE_0_X2APIC_VALID_MASK ( VTD_BF_0_IRTE_P_MASK | VTD_BF_0_IRTE_FPD_MASK \
686 | VTD_BF_0_IRTE_DM_MASK | VTD_BF_0_IRTE_RH_MASK \
687 | VTD_BF_0_IRTE_TM_MASK | VTD_BF_0_IRTE_DLM_MASK \
688 | VTD_BF_0_IRTE_AVAIL_MASK | VTD_BF_0_IRTE_IM_MASK \
689 | VTD_BF_0_IRTE_V_MASK | VTD_BF_0_IRTE_DST_MASK)
690/** IRTE: Qword 0 valid mask when EIME=0. */
691#define VTD_IRTE_0_XAPIC_VALID_MASK ( VTD_BF_0_IRTE_P_MASK | VTD_BF_0_IRTE_FPD_MASK \
692 | VTD_BF_0_IRTE_DM_MASK | VTD_BF_0_IRTE_RH_MASK \
693 | VTD_BF_0_IRTE_TM_MASK | VTD_BF_0_IRTE_DLM_MASK \
694 | VTD_BF_0_IRTE_AVAIL_MASK | VTD_BF_0_IRTE_IM_MASK \
695 | VTD_BF_0_IRTE_V_MASK | VTD_BF_0_IRTE_DST_XAPIC_MASK)
696/** IRTE: Qword 1 valid mask. */
697#define VTD_IRTE_1_VALID_MASK ( VTD_BF_1_IRTE_SID_MASK | VTD_BF_1_IRTE_SQ_MASK \
698 | VTD_BF_1_IRTE_SVT_MASK)
699
700/** Interrupt Remapping Table Entry (IRTE) for remapped interrupts. */
701typedef struct VTD_IRTE_T
702{
703 /** The qwords in the IRTE. */
704 uint64_t au64[2];
705} VTD_IRTE_T;
706/** Pointer to an IRTE. */
707typedef VTD_IRTE_T *PVTD_IRTE_T;
708/** Pointer to a const IRTE. */
709typedef VTD_IRTE_T const *PCVTD_IRTE_T;
710
711/** IRTE SVT: No validation required. */
712#define VTD_IRTE_SVT_NONE 0
713/** IRTE SVT: Validate using a mask derived from SID and SQT. */
714#define VTD_IRTE_SVT_VALIDATE_MASK 1
715/** IRTE SVT: Validate using Bus range in the SID. */
716#define VTD_IRTE_SVT_VALIDATE_BUS_RANGE 2
717/** IRTE SVT: Reserved. */
718#define VTD_IRTE_SVT_VALIDATE_RSVD 3
719/** @} */
720
721
722/** @name Version Register (VER_REG).
723 * In accordance with the Intel spec.
724 * @{ */
725/** Min: Minor Version Number. */
726#define VTD_BF_VER_REG_MIN_SHIFT 0
727#define VTD_BF_VER_REG_MIN_MASK UINT32_C(0x0000000f)
728/** Max: Major Version Number. */
729#define VTD_BF_VER_REG_MAX_SHIFT 4
730#define VTD_BF_VER_REG_MAX_MASK UINT32_C(0x000000f0)
731/** R: Reserved (bits 31:8). */
732#define VTD_BF_VER_REG_RSVD_31_8_SHIFT 8
733#define VTD_BF_VER_REG_RSVD_31_8_MASK UINT32_C(0xffffff00)
734RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_VER_REG_, UINT32_C(0), UINT32_MAX,
735 (MIN, MAX, RSVD_31_8));
736/** RW: Read/write mask. */
737#define VTD_VER_REG_RW_MASK UINT32_C(0)
738/** @} */
739
740
741/** @name Capability Register (CAP_REG).
742 * In accordance with the Intel spec.
743 * @{ */
744/** ND: Number of domains supported. */
745#define VTD_BF_CAP_REG_ND_SHIFT 0
746#define VTD_BF_CAP_REG_ND_MASK UINT64_C(0x0000000000000007)
747/** AFL: Advanced Fault Logging. */
748#define VTD_BF_CAP_REG_AFL_SHIFT 3
749#define VTD_BF_CAP_REG_AFL_MASK UINT64_C(0x0000000000000008)
750/** RWBF: Required Write-Buffer Flushing. */
751#define VTD_BF_CAP_REG_RWBF_SHIFT 4
752#define VTD_BF_CAP_REG_RWBF_MASK UINT64_C(0x0000000000000010)
753/** PLMR: Protected Low-Memory Region. */
754#define VTD_BF_CAP_REG_PLMR_SHIFT 5
755#define VTD_BF_CAP_REG_PLMR_MASK UINT64_C(0x0000000000000020)
756/** PHMR: Protected High-Memory Region. */
757#define VTD_BF_CAP_REG_PHMR_SHIFT 6
758#define VTD_BF_CAP_REG_PHMR_MASK UINT64_C(0x0000000000000040)
759/** CM: Caching Mode. */
760#define VTD_BF_CAP_REG_CM_SHIFT 7
761#define VTD_BF_CAP_REG_CM_MASK UINT64_C(0x0000000000000080)
762/** SAGAW: Supported Adjusted Guest Address Widths. */
763#define VTD_BF_CAP_REG_SAGAW_SHIFT 8
764#define VTD_BF_CAP_REG_SAGAW_MASK UINT64_C(0x0000000000001f00)
765/** R: Reserved (bits 15:13). */
766#define VTD_BF_CAP_REG_RSVD_15_13_SHIFT 13
767#define VTD_BF_CAP_REG_RSVD_15_13_MASK UINT64_C(0x000000000000e000)
768/** MGAW: Maximum Guest Address Width. */
769#define VTD_BF_CAP_REG_MGAW_SHIFT 16
770#define VTD_BF_CAP_REG_MGAW_MASK UINT64_C(0x00000000003f0000)
771/** ZLR: Zero Length Read. */
772#define VTD_BF_CAP_REG_ZLR_SHIFT 22
773#define VTD_BF_CAP_REG_ZLR_MASK UINT64_C(0x0000000000400000)
774/** DEP: Deprecated MBZ. Reserved (bit 23). */
775#define VTD_BF_CAP_REG_RSVD_23_SHIFT 23
776#define VTD_BF_CAP_REG_RSVD_23_MASK UINT64_C(0x0000000000800000)
777/** FRO: Fault-recording Register Offset. */
778#define VTD_BF_CAP_REG_FRO_SHIFT 24
779#define VTD_BF_CAP_REG_FRO_MASK UINT64_C(0x00000003ff000000)
780/** SLLPS: Second Level Large Page Support. */
781#define VTD_BF_CAP_REG_SLLPS_SHIFT 34
782#define VTD_BF_CAP_REG_SLLPS_MASK UINT64_C(0x0000003c00000000)
783/** R: Reserved (bit 38). */
784#define VTD_BF_CAP_REG_RSVD_38_SHIFT 38
785#define VTD_BF_CAP_REG_RSVD_38_MASK UINT64_C(0x0000004000000000)
786/** PSI: Page Selective Invalidation. */
787#define VTD_BF_CAP_REG_PSI_SHIFT 39
788#define VTD_BF_CAP_REG_PSI_MASK UINT64_C(0x0000008000000000)
789/** NFR: Number of Fault-recording Registers. */
790#define VTD_BF_CAP_REG_NFR_SHIFT 40
791#define VTD_BF_CAP_REG_NFR_MASK UINT64_C(0x0000ff0000000000)
792/** MAMV: Maximum Address Mask Value. */
793#define VTD_BF_CAP_REG_MAMV_SHIFT 48
794#define VTD_BF_CAP_REG_MAMV_MASK UINT64_C(0x003f000000000000)
795/** DWD: Write Draining. */
796#define VTD_BF_CAP_REG_DWD_SHIFT 54
797#define VTD_BF_CAP_REG_DWD_MASK UINT64_C(0x0040000000000000)
798/** DRD: Read Draining. */
799#define VTD_BF_CAP_REG_DRD_SHIFT 55
800#define VTD_BF_CAP_REG_DRD_MASK UINT64_C(0x0080000000000000)
801/** FL1GP: First Level 1 GB Page Support. */
802#define VTD_BF_CAP_REG_FL1GP_SHIFT 56
803#define VTD_BF_CAP_REG_FL1GP_MASK UINT64_C(0x0100000000000000)
804/** R: Reserved (bits 58:57). */
805#define VTD_BF_CAP_REG_RSVD_58_57_SHIFT 57
806#define VTD_BF_CAP_REG_RSVD_58_57_MASK UINT64_C(0x0600000000000000)
807/** PI: Posted Interrupt Support. */
808#define VTD_BF_CAP_REG_PI_SHIFT 59
809#define VTD_BF_CAP_REG_PI_MASK UINT64_C(0x0800000000000000)
810/** FL5LP: First Level 5-level Paging Support. */
811#define VTD_BF_CAP_REG_FL5LP_SHIFT 60
812#define VTD_BF_CAP_REG_FL5LP_MASK UINT64_C(0x1000000000000000)
813/** R: Reserved (bit 61). */
814#define VTD_BF_CAP_REG_RSVD_61_SHIFT 61
815#define VTD_BF_CAP_REG_RSVD_61_MASK UINT64_C(0x2000000000000000)
816/** ESIRTPS: Enhanced Set Interrupt Root Table Pointer Support. */
817#define VTD_BF_CAP_REG_ESIRTPS_SHIFT 62
818#define VTD_BF_CAP_REG_ESIRTPS_MASK UINT64_C(0x4000000000000000)
819/** : Enhanced Set Root Table Pointer Support. */
820#define VTD_BF_CAP_REG_ESRTPS_SHIFT 63
821#define VTD_BF_CAP_REG_ESRTPS_MASK UINT64_C(0x8000000000000000)
822RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_CAP_REG_, UINT64_C(0), UINT64_MAX,
823 (ND, AFL, RWBF, PLMR, PHMR, CM, SAGAW, RSVD_15_13, MGAW, ZLR, RSVD_23, FRO, SLLPS, RSVD_38, PSI, NFR,
824 MAMV, DWD, DRD, FL1GP, RSVD_58_57, PI, FL5LP, RSVD_61, ESIRTPS, ESRTPS));
825
826/** RW: Read/write mask. */
827#define VTD_CAP_REG_RW_MASK UINT64_C(0)
828/** @} */
829
830
831/** @name Extended Capability Register (ECAP_REG).
832 * In accordance with the Intel spec.
833 * @{ */
834/** C: Page-walk Coherence. */
835#define VTD_BF_ECAP_REG_C_SHIFT 0
836#define VTD_BF_ECAP_REG_C_MASK UINT64_C(0x0000000000000001)
837/** QI: Queued Invalidation Support. */
838#define VTD_BF_ECAP_REG_QI_SHIFT 1
839#define VTD_BF_ECAP_REG_QI_MASK UINT64_C(0x0000000000000002)
840/** DT: Device-TLB Support. */
841#define VTD_BF_ECAP_REG_DT_SHIFT 2
842#define VTD_BF_ECAP_REG_DT_MASK UINT64_C(0x0000000000000004)
843/** IR: Interrupt Remapping Support. */
844#define VTD_BF_ECAP_REG_IR_SHIFT 3
845#define VTD_BF_ECAP_REG_IR_MASK UINT64_C(0x0000000000000008)
846/** EIM: Extended Interrupt Mode. */
847#define VTD_BF_ECAP_REG_EIM_SHIFT 4
848#define VTD_BF_ECAP_REG_EIM_MASK UINT64_C(0x0000000000000010)
849/** DEP: Deprecated MBZ. Reserved (bit 5). */
850#define VTD_BF_ECAP_REG_RSVD_5_SHIFT 5
851#define VTD_BF_ECAP_REG_RSVD_5_MASK UINT64_C(0x0000000000000020)
852/** PT: Pass Through. */
853#define VTD_BF_ECAP_REG_PT_SHIFT 6
854#define VTD_BF_ECAP_REG_PT_MASK UINT64_C(0x0000000000000040)
855/** SC: Snoop Control. */
856#define VTD_BF_ECAP_REG_SC_SHIFT 7
857#define VTD_BF_ECAP_REG_SC_MASK UINT64_C(0x0000000000000080)
858/** IRO: IOTLB Register Offset. */
859#define VTD_BF_ECAP_REG_IRO_SHIFT 8
860#define VTD_BF_ECAP_REG_IRO_MASK UINT64_C(0x000000000003ff00)
861/** R: Reserved (bits 19:18). */
862#define VTD_BF_ECAP_REG_RSVD_19_18_SHIFT 18
863#define VTD_BF_ECAP_REG_RSVD_19_18_MASK UINT64_C(0x00000000000c0000)
864/** MHMV: Maximum Handle Mask Value. */
865#define VTD_BF_ECAP_REG_MHMV_SHIFT 20
866#define VTD_BF_ECAP_REG_MHMV_MASK UINT64_C(0x0000000000f00000)
867/** DEP: Deprecated MBZ. Reserved (bit 24). */
868#define VTD_BF_ECAP_REG_RSVD_24_SHIFT 24
869#define VTD_BF_ECAP_REG_RSVD_24_MASK UINT64_C(0x0000000001000000)
870/** MTS: Memory Type Support. */
871#define VTD_BF_ECAP_REG_MTS_SHIFT 25
872#define VTD_BF_ECAP_REG_MTS_MASK UINT64_C(0x0000000002000000)
873/** NEST: Nested Translation Support. */
874#define VTD_BF_ECAP_REG_NEST_SHIFT 26
875#define VTD_BF_ECAP_REG_NEST_MASK UINT64_C(0x0000000004000000)
876/** R: Reserved (bit 27). */
877#define VTD_BF_ECAP_REG_RSVD_27_SHIFT 27
878#define VTD_BF_ECAP_REG_RSVD_27_MASK UINT64_C(0x0000000008000000)
879/** DEP: Deprecated MBZ. Reserved (bit 28). */
880#define VTD_BF_ECAP_REG_RSVD_28_SHIFT 28
881#define VTD_BF_ECAP_REG_RSVD_28_MASK UINT64_C(0x0000000010000000)
882/** PRS: Page Request Support. */
883#define VTD_BF_ECAP_REG_PRS_SHIFT 29
884#define VTD_BF_ECAP_REG_PRS_MASK UINT64_C(0x0000000020000000)
885/** ERS: Execute Request Support. */
886#define VTD_BF_ECAP_REG_ERS_SHIFT 30
887#define VTD_BF_ECAP_REG_ERS_MASK UINT64_C(0x0000000040000000)
888/** SRS: Supervisor Request Support. */
889#define VTD_BF_ECAP_REG_SRS_SHIFT 31
890#define VTD_BF_ECAP_REG_SRS_MASK UINT64_C(0x0000000080000000)
891/** R: Reserved (bit 32). */
892#define VTD_BF_ECAP_REG_RSVD_32_SHIFT 32
893#define VTD_BF_ECAP_REG_RSVD_32_MASK UINT64_C(0x0000000100000000)
894/** NWFS: No Write Flag Support. */
895#define VTD_BF_ECAP_REG_NWFS_SHIFT 33
896#define VTD_BF_ECAP_REG_NWFS_MASK UINT64_C(0x0000000200000000)
897/** EAFS: Extended Accessed Flags Support. */
898#define VTD_BF_ECAP_REG_EAFS_SHIFT 34
899#define VTD_BF_ECAP_REG_EAFS_MASK UINT64_C(0x0000000400000000)
900/** PSS: PASID Size Supported. */
901#define VTD_BF_ECAP_REG_PSS_SHIFT 35
902#define VTD_BF_ECAP_REG_PSS_MASK UINT64_C(0x000000f800000000)
903/** PASID: Process Address Space ID Support. */
904#define VTD_BF_ECAP_REG_PASID_SHIFT 40
905#define VTD_BF_ECAP_REG_PASID_MASK UINT64_C(0x0000010000000000)
906/** DIT: Device-TLB Invalidation Throttle. */
907#define VTD_BF_ECAP_REG_DIT_SHIFT 41
908#define VTD_BF_ECAP_REG_DIT_MASK UINT64_C(0x0000020000000000)
909/** PDS: Page-request Drain Support. */
910#define VTD_BF_ECAP_REG_PDS_SHIFT 42
911#define VTD_BF_ECAP_REG_PDS_MASK UINT64_C(0x0000040000000000)
912/** SMTS: Scalable-Mode Translation Support. */
913#define VTD_BF_ECAP_REG_SMTS_SHIFT 43
914#define VTD_BF_ECAP_REG_SMTS_MASK UINT64_C(0x0000080000000000)
915/** VCS: Virtual Command Support. */
916#define VTD_BF_ECAP_REG_VCS_SHIFT 44
917#define VTD_BF_ECAP_REG_VCS_MASK UINT64_C(0x0000100000000000)
918/** SLADS: Second-Level Accessed/Dirty Support. */
919#define VTD_BF_ECAP_REG_SLADS_SHIFT 45
920#define VTD_BF_ECAP_REG_SLADS_MASK UINT64_C(0x0000200000000000)
921/** SLTS: Second-Level Translation Support. */
922#define VTD_BF_ECAP_REG_SLTS_SHIFT 46
923#define VTD_BF_ECAP_REG_SLTS_MASK UINT64_C(0x0000400000000000)
924/** FLTS: First-Level Translation Support. */
925#define VTD_BF_ECAP_REG_FLTS_SHIFT 47
926#define VTD_BF_ECAP_REG_FLTS_MASK UINT64_C(0x0000800000000000)
927/** SMPWCS: Scalable-Mode Page-Walk Coherency Support. */
928#define VTD_BF_ECAP_REG_SMPWCS_SHIFT 48
929#define VTD_BF_ECAP_REG_SMPWCS_MASK UINT64_C(0x0001000000000000)
930/** RPS: RID-PASID Support. */
931#define VTD_BF_ECAP_REG_RPS_SHIFT 49
932#define VTD_BF_ECAP_REG_RPS_MASK UINT64_C(0x0002000000000000)
933/** R: Reserved (bits 51:50). */
934#define VTD_BF_ECAP_REG_RSVD_51_50_SHIFT 50
935#define VTD_BF_ECAP_REG_RSVD_51_50_MASK UINT64_C(0x000c000000000000)
936/** ADMS: Abort DMA Mode Support. */
937#define VTD_BF_ECAP_REG_ADMS_SHIFT 52
938#define VTD_BF_ECAP_REG_ADMS_MASK UINT64_C(0x0010000000000000)
939/** RPRIVS: RID_PRIV Support. */
940#define VTD_BF_ECAP_REG_RPRIVS_SHIFT 53
941#define VTD_BF_ECAP_REG_RPRIVS_MASK UINT64_C(0x0020000000000000)
942/** R: Reserved (bits 63:54). */
943#define VTD_BF_ECAP_REG_RSVD_63_54_SHIFT 54
944#define VTD_BF_ECAP_REG_RSVD_63_54_MASK UINT64_C(0xffc0000000000000)
945RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_ECAP_REG_, UINT64_C(0), UINT64_MAX,
946 (C, QI, DT, IR, EIM, RSVD_5, PT, SC, IRO, RSVD_19_18, MHMV, RSVD_24, MTS, NEST, RSVD_27, RSVD_28,
947 PRS, ERS, SRS, RSVD_32, NWFS, EAFS, PSS, PASID, DIT, PDS, SMTS, VCS, SLADS, SLTS, FLTS, SMPWCS, RPS,
948 RSVD_51_50, ADMS, RPRIVS, RSVD_63_54));
949
950/** RW: Read/write mask. */
951#define VTD_ECAP_REG_RW_MASK UINT64_C(0)
952/** @} */
953
954
955/** @name Global Command Register (GCMD_REG).
956 * In accordance with the Intel spec.
957 * @{ */
958/** R: Reserved (bits 22:0). */
959#define VTD_BF_GCMD_REG_RSVD_22_0_SHIFT 0
960#define VTD_BF_GCMD_REG_RSVD_22_0_MASK UINT32_C(0x007fffff)
961/** CFI: Compatibility Format Interrupt. */
962#define VTD_BF_GCMD_REG_CFI_SHIFT 23
963#define VTD_BF_GCMD_REG_CFI_MASK UINT32_C(0x00800000)
964/** SIRTP: Set Interrupt Table Remap Pointer. */
965#define VTD_BF_GCMD_REG_SIRTP_SHIFT 24
966#define VTD_BF_GCMD_REG_SIRTP_MASK UINT32_C(0x01000000)
967/** IRE: Interrupt Remap Enable. */
968#define VTD_BF_GCMD_REG_IRE_SHIFT 25
969#define VTD_BF_GCMD_REG_IRE_MASK UINT32_C(0x02000000)
970/** QIE: Queued Invalidation Enable. */
971#define VTD_BF_GCMD_REG_QIE_SHIFT 26
972#define VTD_BF_GCMD_REG_QIE_MASK UINT32_C(0x04000000)
973/** WBF: Write Buffer Flush. */
974#define VTD_BF_GCMD_REG_WBF_SHIFT 27
975#define VTD_BF_GCMD_REG_WBF_MASK UINT32_C(0x08000000)
976/** EAFL: Enable Advance Fault Logging. */
977#define VTD_BF_GCMD_REG_EAFL_SHIFT 28
978#define VTD_BF_GCMD_REG_EAFL_MASK UINT32_C(0x10000000)
979/** SFL: Set Fault Log. */
980#define VTD_BF_GCMD_REG_SFL_SHIFT 29
981#define VTD_BF_GCMD_REG_SFL_MASK UINT32_C(0x20000000)
982/** SRTP: Set Root Table Pointer. */
983#define VTD_BF_GCMD_REG_SRTP_SHIFT 30
984#define VTD_BF_GCMD_REG_SRTP_MASK UINT32_C(0x40000000)
985/** TE: Translation Enable. */
986#define VTD_BF_GCMD_REG_TE_SHIFT 31
987#define VTD_BF_GCMD_REG_TE_MASK UINT32_C(0x80000000)
988RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_GCMD_REG_, UINT32_C(0), UINT32_MAX,
989 (RSVD_22_0, CFI, SIRTP, IRE, QIE, WBF, EAFL, SFL, SRTP, TE));
990
991/** RW: Read/write mask. */
992#define VTD_GCMD_REG_RW_MASK ( VTD_BF_GCMD_REG_TE_MASK | VTD_BF_GCMD_REG_SRTP_MASK \
993 | VTD_BF_GCMD_REG_SFL_MASK | VTD_BF_GCMD_REG_EAFL_MASK \
994 | VTD_BF_GCMD_REG_WBF_MASK | VTD_BF_GCMD_REG_QIE_MASK \
995 | VTD_BF_GCMD_REG_IRE_MASK | VTD_BF_GCMD_REG_SIRTP_MASK \
996 | VTD_BF_GCMD_REG_CFI_MASK)
997/** @} */
998
999
1000/** @name Global Status Register (GSTS_REG).
1001 * In accordance with the Intel spec.
1002 * @{ */
1003/** R: Reserved (bits 22:0). */
1004#define VTD_BF_GSTS_REG_RSVD_22_0_SHIFT 0
1005#define VTD_BF_GSTS_REG_RSVD_22_0_MASK UINT32_C(0x007fffff)
1006/** CFIS: Compatibility Format Interrupt Status. */
1007#define VTD_BF_GSTS_REG_CFIS_SHIFT 23
1008#define VTD_BF_GSTS_REG_CFIS_MASK UINT32_C(0x00800000)
1009/** IRTPS: Interrupt Remapping Table Pointer Status. */
1010#define VTD_BF_GSTS_REG_IRTPS_SHIFT 24
1011#define VTD_BF_GSTS_REG_IRTPS_MASK UINT32_C(0x01000000)
1012/** IRES: Interrupt Remapping Enable Status. */
1013#define VTD_BF_GSTS_REG_IRES_SHIFT 25
1014#define VTD_BF_GSTS_REG_IRES_MASK UINT32_C(0x02000000)
1015/** QIES: Queued Invalidation Enable Status. */
1016#define VTD_BF_GSTS_REG_QIES_SHIFT 26
1017#define VTD_BF_GSTS_REG_QIES_MASK UINT32_C(0x04000000)
1018/** WBFS: Write Buffer Flush Status. */
1019#define VTD_BF_GSTS_REG_WBFS_SHIFT 27
1020#define VTD_BF_GSTS_REG_WBFS_MASK UINT32_C(0x08000000)
1021/** AFLS: Advanced Fault Logging Status. */
1022#define VTD_BF_GSTS_REG_AFLS_SHIFT 28
1023#define VTD_BF_GSTS_REG_AFLS_MASK UINT32_C(0x10000000)
1024/** FLS: Fault Log Status. */
1025#define VTD_BF_GSTS_REG_FLS_SHIFT 29
1026#define VTD_BF_GSTS_REG_FLS_MASK UINT32_C(0x20000000)
1027/** RTPS: Root Table Pointer Status. */
1028#define VTD_BF_GSTS_REG_RTPS_SHIFT 30
1029#define VTD_BF_GSTS_REG_RTPS_MASK UINT32_C(0x40000000)
1030/** TES: Translation Enable Status. */
1031#define VTD_BF_GSTS_REG_TES_SHIFT 31
1032#define VTD_BF_GSTS_REG_TES_MASK UINT32_C(0x80000000)
1033RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_GSTS_REG_, UINT32_C(0), UINT32_MAX,
1034 (RSVD_22_0, CFIS, IRTPS, IRES, QIES, WBFS, AFLS, FLS, RTPS, TES));
1035
1036/** RW: Read/write mask. */
1037#define VTD_GSTS_REG_RW_MASK UINT32_C(0)
1038/** @} */
1039
1040
1041/** @name Root Table Address Register (RTADDR_REG).
1042 * In accordance with the Intel spec.
1043 * @{ */
1044/** R: Reserved (bits 9:0). */
1045#define VTD_BF_RTADDR_REG_RSVD_9_0_SHIFT 0
1046#define VTD_BF_RTADDR_REG_RSVD_9_0_MASK UINT64_C(0x00000000000003ff)
1047/** TTM: Translation Table Mode. */
1048#define VTD_BF_RTADDR_REG_TTM_SHIFT 10
1049#define VTD_BF_RTADDR_REG_TTM_MASK UINT64_C(0x0000000000000c00)
1050/** RTA: Root Table Address. */
1051#define VTD_BF_RTADDR_REG_RTA_SHIFT 12
1052#define VTD_BF_RTADDR_REG_RTA_MASK UINT64_C(0xfffffffffffff000)
1053RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_RTADDR_REG_, UINT64_C(0), UINT64_MAX,
1054 (RSVD_9_0, TTM, RTA));
1055
1056/** RW: Read/write mask. */
1057#define VTD_RTADDR_REG_RW_MASK UINT64_C(0xfffffffffffffc00)
1058
1059/** RTADDR_REG.TTM: Legacy mode. */
1060#define VTD_TTM_LEGACY_MODE 0
1061/** RTADDR_REG.TTM: Scalable mode. */
1062#define VTD_TTM_SCALABLE_MODE 1
1063/** RTADDR_REG.TTM: Reserved. */
1064#define VTD_TTM_RSVD 2
1065/** RTADDR_REG.TTM: Abort DMA mode. */
1066#define VTD_TTM_ABORT_DMA_MODE 3
1067/** @} */
1068
1069
1070/** @name Context Command Register (CCMD_REG).
1071 * In accordance with the Intel spec.
1072 * @{ */
1073/** DID: Domain-ID. */
1074#define VTD_BF_CCMD_REG_DID_SHIFT 0
1075#define VTD_BF_CCMD_REG_DID_MASK UINT64_C(0x000000000000ffff)
1076/** SID: Source-ID. */
1077#define VTD_BF_CCMD_REG_SID_SHIFT 16
1078#define VTD_BF_CCMD_REG_SID_MASK UINT64_C(0x00000000ffff0000)
1079/** FM: Function Mask. */
1080#define VTD_BF_CCMD_REG_FM_SHIFT 32
1081#define VTD_BF_CCMD_REG_FM_MASK UINT64_C(0x0000000300000000)
1082/** R: Reserved (bits 58:34). */
1083#define VTD_BF_CCMD_REG_RSVD_58_34_SHIFT 34
1084#define VTD_BF_CCMD_REG_RSVD_58_34_MASK UINT64_C(0x07fffffc00000000)
1085/** CAIG: Context Actual Invalidation Granularity. */
1086#define VTD_BF_CCMD_REG_CAIG_SHIFT 59
1087#define VTD_BF_CCMD_REG_CAIG_MASK UINT64_C(0x1800000000000000)
1088/** CIRG: Context Invalidation Request Granularity. */
1089#define VTD_BF_CCMD_REG_CIRG_SHIFT 61
1090#define VTD_BF_CCMD_REG_CIRG_MASK UINT64_C(0x6000000000000000)
1091/** ICC: Invalidation Context Cache. */
1092#define VTD_BF_CCMD_REG_ICC_SHIFT 63
1093#define VTD_BF_CCMD_REG_ICC_MASK UINT64_C(0x8000000000000000)
1094RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_CCMD_REG_, UINT64_C(0), UINT64_MAX,
1095 (DID, SID, FM, RSVD_58_34, CAIG, CIRG, ICC));
1096
1097/** RW: Read/write mask. */
1098#define VTD_CCMD_REG_RW_MASK ( VTD_BF_CCMD_REG_DID_MASK | VTD_BF_CCMD_REG_SID_MASK \
1099 | VTD_BF_CCMD_REG_FM_MASK | VTD_BF_CCMD_REG_CIRG_MASK \
1100 | VTD_BF_CCMD_REG_ICC_MASK)
1101/** @} */
1102
1103
1104/** @name IOTLB Invalidation Register (IOTLB_REG).
1105 * In accordance with the Intel spec.
1106 * @{ */
1107/** R: Reserved (bits 31:0). */
1108#define VTD_BF_IOTLB_REG_RSVD_31_0_SHIFT 0
1109#define VTD_BF_IOTLB_REG_RSVD_31_0_MASK UINT64_C(0x00000000ffffffff)
1110/** DID: Domain-ID. */
1111#define VTD_BF_IOTLB_REG_DID_SHIFT 32
1112#define VTD_BF_IOTLB_REG_DID_MASK UINT64_C(0x0000ffff00000000)
1113/** DW: Draining Writes. */
1114#define VTD_BF_IOTLB_REG_DW_SHIFT 48
1115#define VTD_BF_IOTLB_REG_DW_MASK UINT64_C(0x0001000000000000)
1116/** DR: Draining Reads. */
1117#define VTD_BF_IOTLB_REG_DR_SHIFT 49
1118#define VTD_BF_IOTLB_REG_DR_MASK UINT64_C(0x0002000000000000)
1119/** R: Reserved (bits 56:50). */
1120#define VTD_BF_IOTLB_REG_RSVD_56_50_SHIFT 50
1121#define VTD_BF_IOTLB_REG_RSVD_56_50_MASK UINT64_C(0x01fc000000000000)
1122/** IAIG: IOTLB Actual Invalidation Granularity. */
1123#define VTD_BF_IOTLB_REG_IAIG_SHIFT 57
1124#define VTD_BF_IOTLB_REG_IAIG_MASK UINT64_C(0x0600000000000000)
1125/** R: Reserved (bit 59). */
1126#define VTD_BF_IOTLB_REG_RSVD_59_SHIFT 59
1127#define VTD_BF_IOTLB_REG_RSVD_59_MASK UINT64_C(0x0800000000000000)
1128/** IIRG: IOTLB Invalidation Request Granularity. */
1129#define VTD_BF_IOTLB_REG_IIRG_SHIFT 60
1130#define VTD_BF_IOTLB_REG_IIRG_MASK UINT64_C(0x3000000000000000)
1131/** R: Reserved (bit 62). */
1132#define VTD_BF_IOTLB_REG_RSVD_62_SHIFT 62
1133#define VTD_BF_IOTLB_REG_RSVD_62_MASK UINT64_C(0x4000000000000000)
1134/** IVT: Invalidate IOTLB. */
1135#define VTD_BF_IOTLB_REG_IVT_SHIFT 63
1136#define VTD_BF_IOTLB_REG_IVT_MASK UINT64_C(0x8000000000000000)
1137RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IOTLB_REG_, UINT64_C(0), UINT64_MAX,
1138 (RSVD_31_0, DID, DW, DR, RSVD_56_50, IAIG, RSVD_59, IIRG, RSVD_62, IVT));
1139
1140/** RW: Read/write mask. */
1141#define VTD_IOTLB_REG_RW_MASK ( VTD_BF_IOTLB_REG_DID_MASK | VTD_BF_IOTLB_REG_DW_MASK \
1142 | VTD_BF_IOTLB_REG_DR_MASK | VTD_BF_IOTLB_REG_IIRG_MASK \
1143 | VTD_BF_IOTLB_REG_IVT_MASK)
1144/** @} */
1145
1146
1147/** @name Invalidate Address Register (IVA_REG).
1148 * In accordance with the Intel spec.
1149 * @{ */
1150/** AM: Address Mask. */
1151#define VTD_BF_IVA_REG_AM_SHIFT 0
1152#define VTD_BF_IVA_REG_AM_MASK UINT64_C(0x000000000000003f)
1153/** IH: Invalidation Hint. */
1154#define VTD_BF_IVA_REG_IH_SHIFT 6
1155#define VTD_BF_IVA_REG_IH_MASK UINT64_C(0x0000000000000040)
1156/** R: Reserved (bits 11:7). */
1157#define VTD_BF_IVA_REG_RSVD_11_7_SHIFT 7
1158#define VTD_BF_IVA_REG_RSVD_11_7_MASK UINT64_C(0x0000000000000f80)
1159/** ADDR: Address. */
1160#define VTD_BF_IVA_REG_ADDR_SHIFT 12
1161#define VTD_BF_IVA_REG_ADDR_MASK UINT64_C(0xfffffffffffff000)
1162RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IVA_REG_, UINT64_C(0), UINT64_MAX,
1163 (AM, IH, RSVD_11_7, ADDR));
1164
1165/** RW: Read/write mask. */
1166#define VTD_IVA_REG_RW_MASK ( VTD_BF_IVA_REG_AM_MASK | VTD_BF_IVA_REG_IH_MASK \
1167 | VTD_BF_IVA_REG_ADDR_MASK)
1168/** @} */
1169
1170
1171/** @name Fault Status Register (FSTS_REG).
1172 * In accordance with the Intel spec.
1173 * @{ */
1174/** PFO: Primary Fault Overflow. */
1175#define VTD_BF_FSTS_REG_PFO_SHIFT 0
1176#define VTD_BF_FSTS_REG_PFO_MASK UINT32_C(0x00000001)
1177/** PPF: Primary Pending Fault. */
1178#define VTD_BF_FSTS_REG_PPF_SHIFT 1
1179#define VTD_BF_FSTS_REG_PPF_MASK UINT32_C(0x00000002)
1180/** AFO: Advanced Fault Overflow. */
1181#define VTD_BF_FSTS_REG_AFO_SHIFT 2
1182#define VTD_BF_FSTS_REG_AFO_MASK UINT32_C(0x00000004)
1183/** APF: Advanced Pending Fault. */
1184#define VTD_BF_FSTS_REG_APF_SHIFT 3
1185#define VTD_BF_FSTS_REG_APF_MASK UINT32_C(0x00000008)
1186/** IQE: Invalidation Queue Error. */
1187#define VTD_BF_FSTS_REG_IQE_SHIFT 4
1188#define VTD_BF_FSTS_REG_IQE_MASK UINT32_C(0x00000010)
1189/** ICE: Invalidation Completion Error. */
1190#define VTD_BF_FSTS_REG_ICE_SHIFT 5
1191#define VTD_BF_FSTS_REG_ICE_MASK UINT32_C(0x00000020)
1192/** ITE: Invalidation Timeout Error. */
1193#define VTD_BF_FSTS_REG_ITE_SHIFT 6
1194#define VTD_BF_FSTS_REG_ITE_MASK UINT32_C(0x00000040)
1195/** DEP: Deprecated MBZ. Reserved (bit 7). */
1196#define VTD_BF_FSTS_REG_RSVD_7_SHIFT 7
1197#define VTD_BF_FSTS_REG_RSVD_7_MASK UINT32_C(0x00000080)
1198/** FRI: Fault Record Index. */
1199#define VTD_BF_FSTS_REG_FRI_SHIFT 8
1200#define VTD_BF_FSTS_REG_FRI_MASK UINT32_C(0x0000ff00)
1201/** R: Reserved (bits 31:16). */
1202#define VTD_BF_FSTS_REG_RSVD_31_16_SHIFT 16
1203#define VTD_BF_FSTS_REG_RSVD_31_16_MASK UINT32_C(0xffff0000)
1204RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_FSTS_REG_, UINT32_C(0), UINT32_MAX,
1205 (PFO, PPF, AFO, APF, IQE, ICE, ITE, RSVD_7, FRI, RSVD_31_16));
1206
1207/** RW: Read/write mask. */
1208#define VTD_FSTS_REG_RW_MASK ( VTD_BF_FSTS_REG_PFO_MASK | VTD_BF_FSTS_REG_AFO_MASK \
1209 | VTD_BF_FSTS_REG_APF_MASK | VTD_BF_FSTS_REG_IQE_MASK \
1210 | VTD_BF_FSTS_REG_ICE_MASK | VTD_BF_FSTS_REG_ITE_MASK)
1211/** RW1C: Read-only-status, Write-1-to-clear status mask. */
1212#define VTD_FSTS_REG_RW1C_MASK ( VTD_BF_FSTS_REG_PFO_MASK | VTD_BF_FSTS_REG_AFO_MASK \
1213 | VTD_BF_FSTS_REG_APF_MASK | VTD_BF_FSTS_REG_IQE_MASK \
1214 | VTD_BF_FSTS_REG_ICE_MASK | VTD_BF_FSTS_REG_ITE_MASK)
1215/** @} */
1216
1217
1218/** @name Fault Event Control Register (FECTL_REG).
1219 * In accordance with the Intel spec.
1220 * @{ */
1221/** R: Reserved (bits 29:0). */
1222#define VTD_BF_FECTL_REG_RSVD_29_0_SHIFT 0
1223#define VTD_BF_FECTL_REG_RSVD_29_0_MASK UINT32_C(0x3fffffff)
1224/** IP: Interrupt Pending. */
1225#define VTD_BF_FECTL_REG_IP_SHIFT 30
1226#define VTD_BF_FECTL_REG_IP_MASK UINT32_C(0x40000000)
1227/** IM: Interrupt Mask. */
1228#define VTD_BF_FECTL_REG_IM_SHIFT 31
1229#define VTD_BF_FECTL_REG_IM_MASK UINT32_C(0x80000000)
1230RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_FECTL_REG_, UINT32_C(0), UINT32_MAX,
1231 (RSVD_29_0, IP, IM));
1232
1233/** RW: Read/write mask. */
1234#define VTD_FECTL_REG_RW_MASK VTD_BF_FECTL_REG_IM_MASK
1235/** @} */
1236
1237
1238/** @name Fault Event Data Register (FEDATA_REG).
1239 * In accordance with the Intel spec.
1240 * @{ */
1241/** IMD: Interrupt Message Data. */
1242#define VTD_BF_FEDATA_REG_IMD_SHIFT 0
1243#define VTD_BF_FEDATA_REG_IMD_MASK UINT32_C(0x0000ffff)
1244/** R: Reserved (bits 31:16). VT-d specs. prior to 2021 had EIMD here. */
1245#define VTD_BF_FEDATA_REG_RSVD_31_16_SHIFT 16
1246#define VTD_BF_FEDATA_REG_RSVD_31_16_MASK UINT32_C(0xffff0000)
1247RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_FEDATA_REG_, UINT32_C(0), UINT32_MAX,
1248 (IMD, RSVD_31_16));
1249
1250/** RW: Read/write mask, see 5.1.6 "Remapping Hardware Event Interrupt
1251 * Programming". */
1252#define VTD_FEDATA_REG_RW_MASK UINT32_C(0x000001ff)
1253/** @} */
1254
1255
1256/** @name Fault Event Address Register (FEADDR_REG).
1257 * In accordance with the Intel spec.
1258 * @{ */
1259/** R: Reserved (bits 1:0). */
1260#define VTD_BF_FEADDR_REG_RSVD_1_0_SHIFT 0
1261#define VTD_BF_FEADDR_REG_RSVD_1_0_MASK UINT32_C(0x00000003)
1262/** MA: Message Address. */
1263#define VTD_BF_FEADDR_REG_MA_SHIFT 2
1264#define VTD_BF_FEADDR_REG_MA_MASK UINT32_C(0xfffffffc)
1265RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_FEADDR_REG_, UINT32_C(0), UINT32_MAX,
1266 (RSVD_1_0, MA));
1267
1268/** RW: Read/write mask. */
1269#define VTD_FEADDR_REG_RW_MASK VTD_BF_FEADDR_REG_MA_MASK
1270/** @} */
1271
1272
1273/** @name Fault Event Upper Address Register (FEUADDR_REG).
1274 * In accordance with the Intel spec.
1275 * @{ */
1276/** MUA: Message Upper Address. */
1277#define VTD_BF_FEUADDR_REG_MA_SHIFT 0
1278#define VTD_BF_FEUADDR_REG_MA_MASK UINT32_C(0xffffffff)
1279
1280/** RW: Read/write mask. */
1281#define VTD_FEUADDR_REG_RW_MASK VTD_BF_FEUADDR_REG_MA_MASK
1282/** @} */
1283
1284
1285/** @name Fault Recording Register (FRCD_REG).
1286 * In accordance with the Intel spec.
1287 * @{ */
1288/** R: Reserved (bits 11:0). */
1289#define VTD_BF_0_FRCD_REG_RSVD_11_0_SHIFT 0
1290#define VTD_BF_0_FRCD_REG_RSVD_11_0_MASK UINT64_C(0x0000000000000fff)
1291/** FI: Fault Info. */
1292#define VTD_BF_0_FRCD_REG_FI_SHIFT 12
1293#define VTD_BF_0_FRCD_REG_FI_MASK UINT64_C(0xfffffffffffff000)
1294RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_FRCD_REG_, UINT64_C(0), UINT64_MAX,
1295 (RSVD_11_0, FI));
1296
1297/** SID: Source Identifier. */
1298#define VTD_BF_1_FRCD_REG_SID_SHIFT 0
1299#define VTD_BF_1_FRCD_REG_SID_MASK UINT64_C(0x000000000000ffff)
1300/** R: Reserved (bits 27:16). */
1301#define VTD_BF_1_FRCD_REG_RSVD_27_16_SHIFT 16
1302#define VTD_BF_1_FRCD_REG_RSVD_27_16_MASK UINT64_C(0x000000000fff0000)
1303/** T2: Type bit 2. */
1304#define VTD_BF_1_FRCD_REG_T2_SHIFT 28
1305#define VTD_BF_1_FRCD_REG_T2_MASK UINT64_C(0x0000000010000000)
1306/** PRIV: Privilege Mode. */
1307#define VTD_BF_1_FRCD_REG_PRIV_SHIFT 29
1308#define VTD_BF_1_FRCD_REG_PRIV_MASK UINT64_C(0x0000000020000000)
1309/** EXE: Execute Permission Requested. */
1310#define VTD_BF_1_FRCD_REG_EXE_SHIFT 30
1311#define VTD_BF_1_FRCD_REG_EXE_MASK UINT64_C(0x0000000040000000)
1312/** PP: PASID Present. */
1313#define VTD_BF_1_FRCD_REG_PP_SHIFT 31
1314#define VTD_BF_1_FRCD_REG_PP_MASK UINT64_C(0x0000000080000000)
1315/** FR: Fault Reason. */
1316#define VTD_BF_1_FRCD_REG_FR_SHIFT 32
1317#define VTD_BF_1_FRCD_REG_FR_MASK UINT64_C(0x000000ff00000000)
1318/** PV: PASID Value. */
1319#define VTD_BF_1_FRCD_REG_PV_SHIFT 40
1320#define VTD_BF_1_FRCD_REG_PV_MASK UINT64_C(0x0fffff0000000000)
1321/** AT: Address Type. */
1322#define VTD_BF_1_FRCD_REG_AT_SHIFT 60
1323#define VTD_BF_1_FRCD_REG_AT_MASK UINT64_C(0x3000000000000000)
1324/** T1: Type bit 1. */
1325#define VTD_BF_1_FRCD_REG_T1_SHIFT 62
1326#define VTD_BF_1_FRCD_REG_T1_MASK UINT64_C(0x4000000000000000)
1327/** F: Fault. */
1328#define VTD_BF_1_FRCD_REG_F_SHIFT 63
1329#define VTD_BF_1_FRCD_REG_F_MASK UINT64_C(0x8000000000000000)
1330RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_FRCD_REG_, UINT64_C(0), UINT64_MAX,
1331 (SID, RSVD_27_16, T2, PRIV, EXE, PP, FR, PV, AT, T1, F));
1332
1333/** RW: Read/write mask. */
1334#define VTD_FRCD_REG_LO_RW_MASK UINT64_C(0)
1335#define VTD_FRCD_REG_HI_RW_MASK VTD_BF_1_FRCD_REG_F_MASK
1336/** RW1C: Read-only-status, Write-1-to-clear status mask. */
1337#define VTD_FRCD_REG_LO_RW1C_MASK UINT64_C(0)
1338#define VTD_FRCD_REG_HI_RW1C_MASK VTD_BF_1_FRCD_REG_F_MASK
1339/** @} */
1340
1341
1342/**
1343 * VT-d faulted request types (FRCD_REG::T2).
1344 * In accordance with the Intel spec.
1345 */
1346typedef enum VTDREQTYPE
1347{
1348 VTDREQTYPE_WRITE = 0, /**< Memory access write request. */
1349 VTDREQTYPE_PAGE, /**< Page translation request. */
1350 VTDREQTYPE_READ, /**< Memory access read request. */
1351 VTDREQTYPE_ATOMIC_OP /**< Memory access atomic operation. */
1352} VTDREQTYPE;
1353
1354
1355/** @name VT-d faulted request attributes (FRCD_REG::EXE, FRCD_REG::PRIV).
1356 * In accordance with the Intel spec.
1357 * @{
1358 */
1359/** Supervisory privilege was requested. */
1360#define VTD_REQ_ATTR_PRIV RT_BIT(0)
1361/** Execute permission was requested. */
1362#define VTD_REQ_ATTR_EXE RT_BIT(1)
1363/** @} */
1364
1365
1366/** @name Advanced Fault Log Register (AFLOG_REG).
1367 * In accordance with the Intel spec.
1368 * @{ */
1369/** R: Reserved (bits 8:0). */
1370#define VTD_BF_0_AFLOG_REG_RSVD_8_0_SHIFT 0
1371#define VTD_BF_0_AFLOG_REG_RSVD_8_0_MASK UINT64_C(0x00000000000001ff)
1372/** FLS: Fault Log Size. */
1373#define VTD_BF_0_AFLOG_REG_FLS_SHIFT 9
1374#define VTD_BF_0_AFLOG_REG_FLS_MASK UINT64_C(0x0000000000000e00)
1375/** FLA: Fault Log Address. */
1376#define VTD_BF_0_AFLOG_REG_FLA_SHIFT 12
1377#define VTD_BF_0_AFLOG_REG_FLA_MASK UINT64_C(0xfffffffffffff000)
1378RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_AFLOG_REG_, UINT64_C(0), UINT64_MAX,
1379 (RSVD_8_0, FLS, FLA));
1380
1381/** RW: Read/write mask. */
1382#define VTD_AFLOG_REG_RW_MASK (VTD_BF_0_AFLOG_REG_FLS_MASK | VTD_BF_0_AFLOG_REG_FLA_MASK)
1383/** @} */
1384
1385
1386/** @name Protected Memory Enable Register (PMEN_REG).
1387 * In accordance with the Intel spec.
1388 * @{ */
1389/** PRS: Protected Region Status. */
1390#define VTD_BF_PMEN_REG_PRS_SHIFT 0
1391#define VTD_BF_PMEN_REG_PRS_MASK UINT32_C(0x00000001)
1392/** R: Reserved (bits 30:1). */
1393#define VTD_BF_PMEN_REG_RSVD_30_1_SHIFT 1
1394#define VTD_BF_PMEN_REG_RSVD_30_1_MASK UINT32_C(0x7ffffffe)
1395/** EPM: Enable Protected Memory. */
1396#define VTD_BF_PMEN_REG_EPM_SHIFT 31
1397#define VTD_BF_PMEN_REG_EPM_MASK UINT32_C(0x80000000)
1398RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_PMEN_REG_, UINT32_C(0), UINT32_MAX,
1399 (PRS, RSVD_30_1, EPM));
1400
1401/** RW: Read/write mask. */
1402#define VTD_PMEN_REG_RW_MASK VTD_BF_PMEN_REG_EPM_MASK
1403/** @} */
1404
1405
1406/** @name Invalidation Queue Head Register (IQH_REG).
1407 * In accordance with the Intel spec.
1408 * @{ */
1409/** R: Reserved (bits 3:0). */
1410#define VTD_BF_IQH_REG_RSVD_3_0_SHIFT 0
1411#define VTD_BF_IQH_REG_RSVD_3_0_MASK UINT64_C(0x000000000000000f)
1412/** QH: Queue Head. */
1413#define VTD_BF_IQH_REG_QH_SHIFT 4
1414#define VTD_BF_IQH_REG_QH_MASK UINT64_C(0x000000000007fff0)
1415/** R: Reserved (bits 63:19). */
1416#define VTD_BF_IQH_REG_RSVD_63_19_SHIFT 19
1417#define VTD_BF_IQH_REG_RSVD_63_19_MASK UINT64_C(0xfffffffffff80000)
1418RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IQH_REG_, UINT64_C(0), UINT64_MAX,
1419 (RSVD_3_0, QH, RSVD_63_19));
1420
1421/** RW: Read/write mask. */
1422#define VTD_IQH_REG_RW_MASK UINT64_C(0x0)
1423/** @} */
1424
1425
1426/** @name Invalidation Queue Tail Register (IQT_REG).
1427 * In accordance with the Intel spec.
1428 * @{ */
1429/** R: Reserved (bits 3:0). */
1430#define VTD_BF_IQT_REG_RSVD_3_0_SHIFT 0
1431#define VTD_BF_IQT_REG_RSVD_3_0_MASK UINT64_C(0x000000000000000f)
1432/** QH: Queue Tail. */
1433#define VTD_BF_IQT_REG_QT_SHIFT 4
1434#define VTD_BF_IQT_REG_QT_MASK UINT64_C(0x000000000007fff0)
1435/** R: Reserved (bits 63:19). */
1436#define VTD_BF_IQT_REG_RSVD_63_19_SHIFT 19
1437#define VTD_BF_IQT_REG_RSVD_63_19_MASK UINT64_C(0xfffffffffff80000)
1438RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IQT_REG_, UINT64_C(0), UINT64_MAX,
1439 (RSVD_3_0, QT, RSVD_63_19));
1440
1441/** RW: Read/write mask. */
1442#define VTD_IQT_REG_RW_MASK VTD_BF_IQT_REG_QT_MASK
1443/** @} */
1444
1445
1446/** @name Invalidation Queue Address Register (IQA_REG).
1447 * In accordance with the Intel spec.
1448 * @{ */
1449/** QS: Queue Size. */
1450#define VTD_BF_IQA_REG_QS_SHIFT 0
1451#define VTD_BF_IQA_REG_QS_MASK UINT64_C(0x0000000000000007)
1452/** R: Reserved (bits 10:3). */
1453#define VTD_BF_IQA_REG_RSVD_10_3_SHIFT 3
1454#define VTD_BF_IQA_REG_RSVD_10_3_MASK UINT64_C(0x00000000000007f8)
1455/** DW: Descriptor Width. */
1456#define VTD_BF_IQA_REG_DW_SHIFT 11
1457#define VTD_BF_IQA_REG_DW_MASK UINT64_C(0x0000000000000800)
1458/** IQA: Invalidation Queue Base Address. */
1459#define VTD_BF_IQA_REG_IQA_SHIFT 12
1460#define VTD_BF_IQA_REG_IQA_MASK UINT64_C(0xfffffffffffff000)
1461RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IQA_REG_, UINT64_C(0), UINT64_MAX,
1462 (QS, RSVD_10_3, DW, IQA));
1463
1464/** RW: Read/write mask. */
1465#define VTD_IQA_REG_RW_MASK ( VTD_BF_IQA_REG_QS_MASK | VTD_BF_IQA_REG_DW_MASK \
1466 | VTD_BF_IQA_REG_IQA_MASK)
1467/** DW: 128-bit descriptor. */
1468#define VTD_IQA_REG_DW_128_BIT 0
1469/** DW: 256-bit descriptor. */
1470#define VTD_IQA_REG_DW_256_BIT 1
1471/** @} */
1472
1473
1474/** @name Invalidation Completion Status Register (ICS_REG).
1475 * In accordance with the Intel spec.
1476 * @{ */
1477/** IWC: Invalidation Wait Descriptor Complete. */
1478#define VTD_BF_ICS_REG_IWC_SHIFT 0
1479#define VTD_BF_ICS_REG_IWC_MASK UINT32_C(0x00000001)
1480/** R: Reserved (bits 31:1). */
1481#define VTD_BF_ICS_REG_RSVD_31_1_SHIFT 1
1482#define VTD_BF_ICS_REG_RSVD_31_1_MASK UINT32_C(0xfffffffe)
1483RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_ICS_REG_, UINT32_C(0), UINT32_MAX,
1484 (IWC, RSVD_31_1));
1485
1486/** RW: Read/write mask. */
1487#define VTD_ICS_REG_RW_MASK VTD_BF_ICS_REG_IWC_MASK
1488/** RW1C: Read-only-status, Write-1-to-clear status mask. */
1489#define VTD_ICS_REG_RW1C_MASK VTD_BF_ICS_REG_IWC_MASK
1490/** @} */
1491
1492
1493/** @name Invalidation Event Control Register (IECTL_REG).
1494 * In accordance with the Intel spec.
1495 * @{ */
1496/** R: Reserved (bits 29:0). */
1497#define VTD_BF_IECTL_REG_RSVD_29_0_SHIFT 0
1498#define VTD_BF_IECTL_REG_RSVD_29_0_MASK UINT32_C(0x3fffffff)
1499/** IP: Interrupt Pending. */
1500#define VTD_BF_IECTL_REG_IP_SHIFT 30
1501#define VTD_BF_IECTL_REG_IP_MASK UINT32_C(0x40000000)
1502/** IM: Interrupt Mask. */
1503#define VTD_BF_IECTL_REG_IM_SHIFT 31
1504#define VTD_BF_IECTL_REG_IM_MASK UINT32_C(0x80000000)
1505RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IECTL_REG_, UINT32_C(0), UINT32_MAX,
1506 (RSVD_29_0, IP, IM));
1507
1508/** RW: Read/write mask. */
1509#define VTD_IECTL_REG_RW_MASK VTD_BF_IECTL_REG_IM_MASK
1510/** @} */
1511
1512
1513/** @name Invalidation Event Data Register (IEDATA_REG).
1514 * In accordance with the Intel spec.
1515 * @{ */
1516/** IMD: Interrupt Message Data. */
1517#define VTD_BF_IEDATA_REG_IMD_SHIFT 0
1518#define VTD_BF_IEDATA_REG_IMD_MASK UINT32_C(0x0000ffff)
1519/** R: Reserved (bits 31:16). VT-d specs. prior to 2021 had EIMD here. */
1520#define VTD_BF_IEDATA_REG_RSVD_31_16_SHIFT 16
1521#define VTD_BF_IEDATA_REG_RSVD_31_16_MASK UINT32_C(0xffff0000)
1522RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IEDATA_REG_, UINT32_C(0), UINT32_MAX,
1523 (IMD, RSVD_31_16));
1524
1525/** RW: Read/write mask, see 5.1.6 "Remapping Hardware Event Interrupt
1526 * Programming". */
1527#define VTD_IEDATA_REG_RW_MASK UINT32_C(0x000001ff)
1528/** @} */
1529
1530
1531/** @name Invalidation Event Address Register (IEADDR_REG).
1532 * In accordance with the Intel spec.
1533 * @{ */
1534/** R: Reserved (bits 1:0). */
1535#define VTD_BF_IEADDR_REG_RSVD_1_0_SHIFT 0
1536#define VTD_BF_IEADDR_REG_RSVD_1_0_MASK UINT32_C(0x00000003)
1537/** MA: Message Address. */
1538#define VTD_BF_IEADDR_REG_MA_SHIFT 2
1539#define VTD_BF_IEADDR_REG_MA_MASK UINT32_C(0xfffffffc)
1540RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IEADDR_REG_, UINT32_C(0), UINT32_MAX,
1541 (RSVD_1_0, MA));
1542
1543/** RW: Read/write mask. */
1544#define VTD_IEADDR_REG_RW_MASK VTD_BF_IEADDR_REG_MA_MASK
1545/** @} */
1546
1547
1548/** @name Invalidation Event Upper Address Register (IEUADDR_REG).
1549 * @{ */
1550/** MUA: Message Upper Address. */
1551#define VTD_BF_IEUADDR_REG_MUA_SHIFT 0
1552#define VTD_BF_IEUADDR_REG_MUA_MASK UINT32_C(0xffffffff)
1553
1554/** RW: Read/write mask. */
1555#define VTD_IEUADDR_REG_RW_MASK VTD_BF_IEUADDR_REG_MUA_MASK
1556/** @} */
1557
1558
1559/** @name Invalidation Queue Error Record Register (IQERCD_REG).
1560 * In accordance with the Intel spec.
1561 * @{ */
1562/** IQEI: Invalidation Queue Error Info. */
1563#define VTD_BF_IQERCD_REG_IQEI_SHIFT 0
1564#define VTD_BF_IQERCD_REG_IQEI_MASK UINT64_C(0x000000000000000f)
1565/** R: Reserved (bits 31:4). */
1566#define VTD_BF_IQERCD_REG_RSVD_31_4_SHIFT 4
1567#define VTD_BF_IQERCD_REG_RSVD_31_4_MASK UINT64_C(0x00000000fffffff0)
1568/** ITESID: Invalidation Timeout Error Source Identifier. */
1569#define VTD_BF_IQERCD_REG_ITESID_SHIFT 32
1570#define VTD_BF_IQERCD_REG_ITESID_MASK UINT64_C(0x0000ffff00000000)
1571/** ICESID: Invalidation Completion Error Source Identifier. */
1572#define VTD_BF_IQERCD_REG_ICESID_SHIFT 48
1573#define VTD_BF_IQERCD_REG_ICESID_MASK UINT64_C(0xffff000000000000)
1574RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IQERCD_REG_, UINT64_C(0), UINT64_MAX,
1575 (IQEI, RSVD_31_4, ITESID, ICESID));
1576
1577/** RW: Read/write mask. */
1578#define VTD_IQERCD_REG_RW_MASK UINT64_C(0)
1579
1580/** Invalidation Queue Error Information. */
1581typedef enum VTDIQEI
1582{
1583 VTDIQEI_INFO_NOT_AVAILABLE,
1584 VTDIQEI_INVALID_TAIL_PTR,
1585 VTDIQEI_FETCH_DESCRIPTOR_ERR,
1586 VTDIQEI_INVALID_DESCRIPTOR_TYPE,
1587 VTDIQEI_RSVD_FIELD_VIOLATION,
1588 VTDIQEI_INVALID_DESCRIPTOR_WIDTH,
1589 VTDIQEI_QUEUE_TAIL_MISALIGNED,
1590 VTDIQEI_INVALID_TTM
1591} VTDIQEI;
1592/** @} */
1593
1594
1595/** @name Interrupt Remapping Table Address Register (IRTA_REG).
1596 * In accordance with the Intel spec.
1597 * @{ */
1598/** S: Size. */
1599#define VTD_BF_IRTA_REG_S_SHIFT 0
1600#define VTD_BF_IRTA_REG_S_MASK UINT64_C(0x000000000000000f)
1601/** R: Reserved (bits 10:4). */
1602#define VTD_BF_IRTA_REG_RSVD_10_4_SHIFT 4
1603#define VTD_BF_IRTA_REG_RSVD_10_4_MASK UINT64_C(0x00000000000007f0)
1604/** EIME: Extended Interrupt Mode Enable. */
1605#define VTD_BF_IRTA_REG_EIME_SHIFT 11
1606#define VTD_BF_IRTA_REG_EIME_MASK UINT64_C(0x0000000000000800)
1607/** IRTA: Interrupt Remapping Table Address. */
1608#define VTD_BF_IRTA_REG_IRTA_SHIFT 12
1609#define VTD_BF_IRTA_REG_IRTA_MASK UINT64_C(0xfffffffffffff000)
1610RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IRTA_REG_, UINT64_C(0), UINT64_MAX,
1611 (S, RSVD_10_4, EIME, IRTA));
1612
1613/** RW: Read/write mask. */
1614#define VTD_IRTA_REG_RW_MASK ( VTD_BF_IRTA_REG_S_MASK | VTD_BF_IRTA_REG_EIME_MASK \
1615 | VTD_BF_IRTA_REG_IRTA_MASK)
1616/** IRTA_REG: Get number of interrupt entries. */
1617#define VTD_IRTA_REG_GET_ENTRY_COUNT(a) (UINT32_C(1) << (1 + ((a) & VTD_BF_IRTA_REG_S_MASK)))
1618/** @} */
1619
1620
1621/** @name Page Request Queue Head Register (PQH_REG).
1622 * In accordance with the Intel spec.
1623 * @{ */
1624/** R: Reserved (bits 4:0). */
1625#define VTD_BF_PQH_REG_RSVD_4_0_SHIFT 0
1626#define VTD_BF_PQH_REG_RSVD_4_0_MASK UINT64_C(0x000000000000001f)
1627/** PQH: Page Queue Head. */
1628#define VTD_BF_PQH_REG_PQH_SHIFT 5
1629#define VTD_BF_PQH_REG_PQH_MASK UINT64_C(0x000000000007ffe0)
1630/** R: Reserved (bits 63:19). */
1631#define VTD_BF_PQH_REG_RSVD_63_19_SHIFT 19
1632#define VTD_BF_PQH_REG_RSVD_63_19_MASK UINT64_C(0xfffffffffff80000)
1633RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_PQH_REG_, UINT64_C(0), UINT64_MAX,
1634 (RSVD_4_0, PQH, RSVD_63_19));
1635
1636/** RW: Read/write mask. */
1637#define VTD_PQH_REG_RW_MASK VTD_BF_PQH_REG_PQH_MASK
1638/** @} */
1639
1640
1641/** @name Page Request Queue Tail Register (PQT_REG).
1642 * In accordance with the Intel spec.
1643 * @{ */
1644/** R: Reserved (bits 4:0). */
1645#define VTD_BF_PQT_REG_RSVD_4_0_SHIFT 0
1646#define VTD_BF_PQT_REG_RSVD_4_0_MASK UINT64_C(0x000000000000001f)
1647/** PQT: Page Queue Tail. */
1648#define VTD_BF_PQT_REG_PQT_SHIFT 5
1649#define VTD_BF_PQT_REG_PQT_MASK UINT64_C(0x000000000007ffe0)
1650/** R: Reserved (bits 63:19). */
1651#define VTD_BF_PQT_REG_RSVD_63_19_SHIFT 19
1652#define VTD_BF_PQT_REG_RSVD_63_19_MASK UINT64_C(0xfffffffffff80000)
1653RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_PQT_REG_, UINT64_C(0), UINT64_MAX,
1654 (RSVD_4_0, PQT, RSVD_63_19));
1655
1656/** RW: Read/write mask. */
1657#define VTD_PQT_REG_RW_MASK VTD_BF_PQT_REG_PQT_MASK
1658/** @} */
1659
1660
1661/** @name Page Request Queue Address Register (PQA_REG).
1662 * In accordance with the Intel spec.
1663 * @{ */
1664/** PQS: Page Queue Size. */
1665#define VTD_BF_PQA_REG_PQS_SHIFT 0
1666#define VTD_BF_PQA_REG_PQS_MASK UINT64_C(0x0000000000000007)
1667/** R: Reserved bits (11:3). */
1668#define VTD_BF_PQA_REG_RSVD_11_3_SHIFT 3
1669#define VTD_BF_PQA_REG_RSVD_11_3_MASK UINT64_C(0x0000000000000ff8)
1670/** PQA: Page Request Queue Base Address. */
1671#define VTD_BF_PQA_REG_PQA_SHIFT 12
1672#define VTD_BF_PQA_REG_PQA_MASK UINT64_C(0xfffffffffffff000)
1673RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_PQA_REG_, UINT64_C(0), UINT64_MAX,
1674 (PQS, RSVD_11_3, PQA));
1675
1676/** RW: Read/write mask. */
1677#define VTD_PQA_REG_RW_MASK (VTD_BF_PQA_REG_PQS_MASK | VTD_BF_PQA_REG_PQA_MASK)
1678/** @} */
1679
1680
1681/** @name Page Request Status Register (PRS_REG).
1682 * In accordance with the Intel spec.
1683 * @{ */
1684/** PPR: Pending Page Request. */
1685#define VTD_BF_PRS_REG_PPR_SHIFT 0
1686#define VTD_BF_PRS_REG_PPR_MASK UINT64_C(0x00000001)
1687/** PRO: Page Request Overflow. */
1688#define VTD_BF_PRS_REG_PRO_SHIFT 1
1689#define VTD_BF_PRS_REG_PRO_MASK UINT64_C(0x00000002)
1690/** R: Reserved (bits 31:2). */
1691#define VTD_BF_PRS_REG_RSVD_31_2_SHIFT 2
1692#define VTD_BF_PRS_REG_RSVD_31_2_MASK UINT64_C(0xfffffffc)
1693RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_PRS_REG_, UINT32_C(0), UINT32_MAX,
1694 (PPR, PRO, RSVD_31_2));
1695
1696/** RW: Read/write mask. */
1697#define VTD_PRS_REG_RW_MASK (VTD_BF_PRS_REG_PPR_MASK | VTD_BF_PRS_REG_PRO_MASK)
1698/** RW1C: Read-only-status, Write-1-to-clear status mask. */
1699#define VTD_PRS_REG_RW1C_MASK (VTD_BF_PRS_REG_PPR_MASK | VTD_BF_PRS_REG_PRO_MASK)
1700/** @} */
1701
1702
1703/** @name Page Request Event Control Register (PECTL_REG).
1704 * In accordance with the Intel spec.
1705 * @{ */
1706/** R: Reserved (bits 29:0). */
1707#define VTD_BF_PECTL_REG_RSVD_29_0_SHIFT 0
1708#define VTD_BF_PECTL_REG_RSVD_29_0_MASK UINT32_C(0x3fffffff)
1709/** IP: Interrupt Pending. */
1710#define VTD_BF_PECTL_REG_IP_SHIFT 30
1711#define VTD_BF_PECTL_REG_IP_MASK UINT32_C(0x40000000)
1712/** IM: Interrupt Mask. */
1713#define VTD_BF_PECTL_REG_IM_SHIFT 31
1714#define VTD_BF_PECTL_REG_IM_MASK UINT32_C(0x80000000)
1715RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_PECTL_REG_, UINT32_C(0), UINT32_MAX,
1716 (RSVD_29_0, IP, IM));
1717
1718/** RW: Read/write mask. */
1719#define VTD_PECTL_REG_RW_MASK VTD_BF_PECTL_REG_IM_MASK
1720/** @} */
1721
1722
1723/** @name Page Request Event Data Register (PEDATA_REG).
1724 * In accordance with the Intel spec.
1725 * @{ */
1726/** IMD: Interrupt Message Data. */
1727#define VTD_BF_PEDATA_REG_IMD_SHIFT 0
1728#define VTD_BF_PEDATA_REG_IMD_MASK UINT32_C(0x0000ffff)
1729/** R: Reserved (bits 31:16). VT-d specs. prior to 2021 had EIMD here. */
1730#define VTD_BF_PEDATA_REG_RSVD_31_16_SHIFT 16
1731#define VTD_BF_PEDATA_REG_RSVD_31_16_MASK UINT32_C(0xffff0000)
1732RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_PEDATA_REG_, UINT32_C(0), UINT32_MAX,
1733 (IMD, RSVD_31_16));
1734
1735/** RW: Read/write mask, see 5.1.6 "Remapping Hardware Event Interrupt
1736 * Programming". */
1737#define VTD_PEDATA_REG_RW_MASK UINT32_C(0x000001ff)
1738/** @} */
1739
1740
1741/** @name Page Request Event Address Register (PEADDR_REG).
1742 * In accordance with the Intel spec.
1743 * @{ */
1744/** R: Reserved (bits 1:0). */
1745#define VTD_BF_PEADDR_REG_RSVD_1_0_SHIFT 0
1746#define VTD_BF_PEADDR_REG_RSVD_1_0_MASK UINT32_C(0x00000003)
1747/** MA: Message Address. */
1748#define VTD_BF_PEADDR_REG_MA_SHIFT 2
1749#define VTD_BF_PEADDR_REG_MA_MASK UINT32_C(0xfffffffc)
1750RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_PEADDR_REG_, UINT32_C(0), UINT32_MAX,
1751 (RSVD_1_0, MA));
1752
1753/** RW: Read/write mask. */
1754#define VTD_PEADDR_REG_RW_MASK VTD_BF_PEADDR_REG_MA_MASK
1755/** @} */
1756
1757
1758
1759/** @name Page Request Event Upper Address Register (PEUADDR_REG).
1760 * In accordance with the Intel spec.
1761 * @{ */
1762/** MA: Message Address. */
1763#define VTD_BF_PEUADDR_REG_MUA_SHIFT 0
1764#define VTD_BF_PEUADDR_REG_MUA_MASK UINT32_C(0xffffffff)
1765
1766/** RW: Read/write mask. */
1767#define VTD_PEUADDR_REG_RW_MASK VTD_BF_PEUADDR_REG_MUA_MASK
1768/** @} */
1769
1770
1771/** @name MTRR Capability Register (MTRRCAP_REG).
1772 * In accordance with the Intel spec.
1773 * @{ */
1774/** VCNT: Variable MTRR Count. */
1775#define VTD_BF_MTRRCAP_REG_VCNT_SHIFT 0
1776#define VTD_BF_MTRRCAP_REG_VCNT_MASK UINT64_C(0x00000000000000ff)
1777/** FIX: Fixed range MTRRs Supported. */
1778#define VTD_BF_MTRRCAP_REG_FIX_SHIFT 8
1779#define VTD_BF_MTRRCAP_REG_FIX_MASK UINT64_C(0x0000000000000100)
1780/** R: Reserved (bit 9). */
1781#define VTD_BF_MTRRCAP_REG_RSVD_9_SHIFT 9
1782#define VTD_BF_MTRRCAP_REG_RSVD_9_MASK UINT64_C(0x0000000000000200)
1783/** WC: Write Combining. */
1784#define VTD_BF_MTRRCAP_REG_WC_SHIFT 10
1785#define VTD_BF_MTRRCAP_REG_WC_MASK UINT64_C(0x0000000000000400)
1786/** R: Reserved (bits 63:11). */
1787#define VTD_BF_MTRRCAP_REG_RSVD_63_11_SHIFT 11
1788#define VTD_BF_MTRRCAP_REG_RSVD_63_11_MASK UINT64_C(0xfffffffffffff800)
1789RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_MTRRCAP_REG_, UINT64_C(0), UINT64_MAX,
1790 (VCNT, FIX, RSVD_9, WC, RSVD_63_11));
1791
1792/** RW: Read/write mask. */
1793#define VTD_MTRRCAP_REG_RW_MASK UINT64_C(0)
1794/** @} */
1795
1796
1797/** @name MTRR Default Type Register (MTRRDEF_REG).
1798 * In accordance with the Intel spec.
1799 * @{ */
1800/** TYPE: Default Memory Type. */
1801#define VTD_BF_MTRRDEF_REG_TYPE_SHIFT 0
1802#define VTD_BF_MTRRDEF_REG_TYPE_MASK UINT64_C(0x00000000000000ff)
1803/** R: Reserved (bits 9:8). */
1804#define VTD_BF_MTRRDEF_REG_RSVD_9_8_SHIFT 8
1805#define VTD_BF_MTRRDEF_REG_RSVD_9_8_MASK UINT64_C(0x0000000000000300)
1806/** FE: Fixed Range MTRR Enable. */
1807#define VTD_BF_MTRRDEF_REG_FE_SHIFT 10
1808#define VTD_BF_MTRRDEF_REG_FE_MASK UINT64_C(0x0000000000000400)
1809/** E: MTRR Enable. */
1810#define VTD_BF_MTRRDEF_REG_E_SHIFT 11
1811#define VTD_BF_MTRRDEF_REG_E_MASK UINT64_C(0x0000000000000800)
1812/** R: Reserved (bits 63:12). */
1813#define VTD_BF_MTRRDEF_REG_RSVD_63_12_SHIFT 12
1814#define VTD_BF_MTRRDEF_REG_RSVD_63_12_MASK UINT64_C(0xfffffffffffff000)
1815RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_MTRRDEF_REG_, UINT64_C(0), UINT64_MAX,
1816 (TYPE, RSVD_9_8, FE, E, RSVD_63_12));
1817
1818/** RW: Read/write mask. */
1819#define VTD_MTRRDEF_REG_RW_MASK ( VTD_BF_MTRRDEF_REG_TYPE_MASK | VTD_BF_MTRRDEF_REG_FE_MASK \
1820 | VTD_BF_MTRRDEF_REG_E_MASK)
1821/** @} */
1822
1823
1824/** @name Virtual Command Capability Register (VCCAP_REG).
1825 * In accordance with the Intel spec.
1826 * @{ */
1827/** PAS: PASID Support. */
1828#define VTD_BF_VCCAP_REG_PAS_SHIFT 0
1829#define VTD_BF_VCCAP_REG_PAS_MASK UINT64_C(0x0000000000000001)
1830/** R: Reserved (bits 63:1). */
1831#define VTD_BF_VCCAP_REG_RSVD_63_1_SHIFT 1
1832#define VTD_BF_VCCAP_REG_RSVD_63_1_MASK UINT64_C(0xfffffffffffffffe)
1833RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_VCCAP_REG_, UINT64_C(0), UINT64_MAX,
1834 (PAS, RSVD_63_1));
1835
1836/** RW: Read/write mask. */
1837#define VTD_VCCAP_REG_RW_MASK UINT64_C(0)
1838/** @} */
1839
1840
1841/** @name Virtual Command Extended Operand Register (VCMD_EO_REG).
1842 * In accordance with the Intel spec.
1843 * @{ */
1844/** OB: Operand B. */
1845#define VTD_BF_VCMD_EO_REG_OB_SHIFT 0
1846#define VTD_BF_VCMD_EO_REG_OB_MASK UINT32_C(0xffffffffffffffff)
1847
1848/** RW: Read/write mask. */
1849#define VTD_VCMD_EO_REG_RW_MASK VTD_BF_VCMD_EO_REG_OB_MASK
1850/** @} */
1851
1852
1853/** @name Virtual Command Register (VCMD_REG).
1854 * In accordance with the Intel spec.
1855 * @{ */
1856/** CMD: Command. */
1857#define VTD_BF_VCMD_REG_CMD_SHIFT 0
1858#define VTD_BF_VCMD_REG_CMD_MASK UINT64_C(0x00000000000000ff)
1859/** OP: Operand. */
1860#define VTD_BF_VCMD_REG_OP_SHIFT 8
1861#define VTD_BF_VCMD_REG_OP_MASK UINT64_C(0xffffffffffffff00)
1862RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_VCMD_REG_, UINT64_C(0), UINT64_MAX,
1863 (CMD, OP));
1864
1865/** RW: Read/write mask. */
1866#define VTD_VCMD_REG_RW_MASK (VTD_BF_VCMD_REG_CMD_MASK | VTD_BF_VCMD_REG_OP_MASK)
1867/** @} */
1868
1869
1870/** @name Virtual Command Response Register (VCRSP_REG).
1871 * In accordance with the Intel spec.
1872 * @{ */
1873/** IP: In Progress. */
1874#define VTD_BF_VCRSP_REG_IP_SHIFT 0
1875#define VTD_BF_VCRSP_REG_IP_MASK UINT64_C(0x0000000000000001)
1876/** SC: Status Code. */
1877#define VTD_BF_VCRSP_REG_SC_SHIFT 1
1878#define VTD_BF_VCRSP_REG_SC_MASK UINT64_C(0x0000000000000006)
1879/** R: Reserved (bits 7:3). */
1880#define VTD_BF_VCRSP_REG_RSVD_7_3_SHIFT 3
1881#define VTD_BF_VCRSP_REG_RSVD_7_3_MASK UINT64_C(0x00000000000000f8)
1882/** RSLT: Result. */
1883#define VTD_BF_VCRSP_REG_RSLT_SHIFT 8
1884#define VTD_BF_VCRSP_REG_RSLT_MASK UINT64_C(0xffffffffffffff00)
1885RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_VCRSP_REG_, UINT64_C(0), UINT64_MAX,
1886 (IP, SC, RSVD_7_3, RSLT));
1887
1888/** RW: Read/write mask. */
1889#define VTD_VCRSP_REG_RW_MASK UINT64_C(0)
1890/** @} */
1891
1892
1893/** @name Generic Invalidation Descriptor.
1894 * In accordance with the Intel spec.
1895 * Non-reserved fields here are common to all invalidation descriptors.
1896 * @{ */
1897/** Type (Lo). */
1898#define VTD_BF_0_GENERIC_INV_DSC_TYPE_LO_SHIFT 0
1899#define VTD_BF_0_GENERIC_INV_DSC_TYPE_LO_MASK UINT64_C(0x000000000000000f)
1900/** R: Reserved (bits 8:4). */
1901#define VTD_BF_0_GENERIC_INV_DSC_RSVD_8_4_SHIFT 4
1902#define VTD_BF_0_GENERIC_INV_DSC_RSVD_8_4_MASK UINT64_C(0x00000000000001f0)
1903/** Type (Hi). */
1904#define VTD_BF_0_GENERIC_INV_DSC_TYPE_HI_SHIFT 9
1905#define VTD_BF_0_GENERIC_INV_DSC_TYPE_HI_MASK UINT64_C(0x0000000000000e00)
1906/** R: Reserved (bits 63:12). */
1907#define VTD_BF_0_GENERIC_INV_DSC_RSVD_63_12_SHIFT 12
1908#define VTD_BF_0_GENERIC_INV_DSC_RSVD_63_12_MASK UINT64_C(0xfffffffffffff000)
1909RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_GENERIC_INV_DSC_, UINT64_C(0), UINT64_MAX,
1910 (TYPE_LO, RSVD_8_4, TYPE_HI, RSVD_63_12));
1911
1912/** GENERIC_INV_DSC: Type. */
1913#define VTD_GENERIC_INV_DSC_GET_TYPE(a) ((((a) & VTD_BF_0_GENERIC_INV_DSC_TYPE_HI_MASK) >> 5) \
1914 | ((a) & VTD_BF_0_GENERIC_INV_DSC_TYPE_LO_MASK))
1915/** @} */
1916
1917
1918/** @name Context-Cache Invalidation Descriptor (cc_inv_dsc).
1919 * In accordance with the Intel spec.
1920 * @{ */
1921/** Type (Lo). */
1922#define VTD_BF_0_CC_INV_DSC_TYPE_LO_SHIFT 0
1923#define VTD_BF_0_CC_INV_DSC_TYPE_LO_MASK UINT64_C(0x000000000000000f)
1924/** G: Granularity. */
1925#define VTD_BF_0_CC_INV_DSC_G_SHIFT 4
1926#define VTD_BF_0_CC_INV_DSC_G_MASK UINT64_C(0x0000000000000030)
1927/** R: Reserved (bits 8:6). */
1928#define VTD_BF_0_CC_INV_DSC_RSVD_8_6_SHIFT 6
1929#define VTD_BF_0_CC_INV_DSC_RSVD_8_6_MASK UINT64_C(0x00000000000001c0)
1930/** Type (Hi). */
1931#define VTD_BF_0_CC_INV_DSC_TYPE_HI_SHIFT 9
1932#define VTD_BF_0_CC_INV_DSC_TYPE_HI_MASK UINT64_C(0x0000000000000e00)
1933/** R: Reserved (bits 15:12). */
1934#define VTD_BF_0_CC_INV_DSC_RSVD_15_12_SHIFT 12
1935#define VTD_BF_0_CC_INV_DSC_RSVD_15_12_MASK UINT64_C(0x000000000000f000)
1936/** DID: Domain Id. */
1937#define VTD_BF_0_CC_INV_DSC_DID_SHIFT 16
1938#define VTD_BF_0_CC_INV_DSC_DID_MASK UINT64_C(0x00000000ffff0000)
1939/** SID: Source Id. */
1940#define VTD_BF_0_CC_INV_DSC_SID_SHIFT 32
1941#define VTD_BF_0_CC_INV_DSC_SID_MASK UINT64_C(0x0000ffff00000000)
1942/** FM: Function Mask. */
1943#define VTD_BF_0_CC_INV_DSC_FM_SHIFT 48
1944#define VTD_BF_0_CC_INV_DSC_FM_MASK UINT64_C(0x0003000000000000)
1945/** R: Reserved (bits 63:50). */
1946#define VTD_BF_0_CC_INV_DSC_RSVD_63_50_SHIFT 50
1947#define VTD_BF_0_CC_INV_DSC_RSVD_63_50_MASK UINT64_C(0xfffc000000000000)
1948RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_CC_INV_DSC_, UINT64_C(0), UINT64_MAX,
1949 (TYPE_LO, G, RSVD_8_6, TYPE_HI, RSVD_15_12, DID, SID, FM, RSVD_63_50));
1950/** @} */
1951
1952
1953/** @name PASID-Cache Invalidation Descriptor (pc_inv_dsc).
1954 * In accordance with the Intel spec.
1955 * @{ */
1956/** Type (Lo). */
1957#define VTD_BF_0_PC_INV_DSC_TYPE_LO_SHIFT 0
1958#define VTD_BF_0_PC_INV_DSC_TYPE_LO_MASK UINT64_C(0x000000000000000f)
1959/** G: Granularity. */
1960#define VTD_BF_0_PC_INV_DSC_G_SHIFT 4
1961#define VTD_BF_0_PC_INV_DSC_G_MASK UINT64_C(0x0000000000000030)
1962/** R: Reserved (bits 8:6). */
1963#define VTD_BF_0_PC_INV_DSC_RSVD_8_6_SHIFT 6
1964#define VTD_BF_0_PC_INV_DSC_RSVD_8_6_MASK UINT64_C(0x00000000000001c0)
1965/** Type (Hi). */
1966#define VTD_BF_0_PC_INV_DSC_TYPE_HI_SHIFT 9
1967#define VTD_BF_0_PC_INV_DSC_TYPE_HI_MASK UINT64_C(0x0000000000000e00)
1968/** R: Reserved (bits 15:12). */
1969#define VTD_BF_0_PC_INV_DSC_RSVD_15_12_SHIFT 12
1970#define VTD_BF_0_PC_INV_DSC_RSVD_15_12_MASK UINT64_C(0x000000000000f000)
1971/** DID: Domain Id. */
1972#define VTD_BF_0_PC_INV_DSC_DID_SHIFT 16
1973#define VTD_BF_0_PC_INV_DSC_DID_MASK UINT64_C(0x00000000ffff0000)
1974/** PASID: Process Address-Space Id. */
1975#define VTD_BF_0_PC_INV_DSC_PASID_SHIFT 32
1976#define VTD_BF_0_PC_INV_DSC_PASID_MASK UINT64_C(0x000fffff00000000)
1977/** R: Reserved (bits 63:52). */
1978#define VTD_BF_0_PC_INV_DSC_RSVD_63_52_SHIFT 52
1979#define VTD_BF_0_PC_INV_DSC_RSVD_63_52_MASK UINT64_C(0xfff0000000000000)
1980
1981RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_PC_INV_DSC_, UINT64_C(0), UINT64_MAX,
1982 (TYPE_LO, G, RSVD_8_6, TYPE_HI, RSVD_15_12, DID, PASID, RSVD_63_52));
1983/** @} */
1984
1985
1986/** @name IOTLB Invalidate Descriptor (iotlb_inv_dsc).
1987 * In accordance with the Intel spec.
1988 * @{ */
1989/** Type (Lo). */
1990#define VTD_BF_0_IOTLB_INV_DSC_TYPE_LO_SHIFT 0
1991#define VTD_BF_0_IOTLB_INV_DSC_TYPE_LO_MASK UINT64_C(0x000000000000000f)
1992/** G: Granularity. */
1993#define VTD_BF_0_IOTLB_INV_DSC_G_SHIFT 4
1994#define VTD_BF_0_IOTLB_INV_DSC_G_MASK UINT64_C(0x0000000000000030)
1995/** DW: Drain Writes. */
1996#define VTD_BF_0_IOTLB_INV_DSC_DW_SHIFT 6
1997#define VTD_BF_0_IOTLB_INV_DSC_DW_MASK UINT64_C(0x0000000000000040)
1998/** DR: Drain Reads. */
1999#define VTD_BF_0_IOTLB_INV_DSC_DR_SHIFT 7
2000#define VTD_BF_0_IOTLB_INV_DSC_DR_MASK UINT64_C(0x0000000000000080)
2001/** R: Reserved (bit 8). */
2002#define VTD_BF_0_IOTLB_INV_DSC_RSVD_8_SHIFT 8
2003#define VTD_BF_0_IOTLB_INV_DSC_RSVD_8_MASK UINT64_C(0x0000000000000100)
2004/** Type (Hi). */
2005#define VTD_BF_0_IOTLB_INV_DSC_TYPE_HI_SHIFT 9
2006#define VTD_BF_0_IOTLB_INV_DSC_TYPE_HI_MASK UINT64_C(0x0000000000000e00)
2007/** R: Reserved (bits 15:12). */
2008#define VTD_BF_0_IOTLB_INV_DSC_RSVD_15_12_SHIFT 12
2009#define VTD_BF_0_IOTLB_INV_DSC_RSVD_15_12_MASK UINT64_C(0x000000000000f000)
2010/** DID: Domain Id. */
2011#define VTD_BF_0_IOTLB_INV_DSC_DID_SHIFT 16
2012#define VTD_BF_0_IOTLB_INV_DSC_DID_MASK UINT64_C(0x00000000ffff0000)
2013/** R: Reserved (bits 63:32). */
2014#define VTD_BF_0_IOTLB_INV_DSC_RSVD_63_32_SHIFT 32
2015#define VTD_BF_0_IOTLB_INV_DSC_RSVD_63_32_MASK UINT64_C(0xffffffff00000000)
2016RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_IOTLB_INV_DSC_, UINT64_C(0), UINT64_MAX,
2017 (TYPE_LO, G, DW, DR, RSVD_8, TYPE_HI, RSVD_15_12, DID, RSVD_63_32));
2018
2019/** AM: Address Mask. */
2020#define VTD_BF_1_IOTLB_INV_DSC_AM_SHIFT 0
2021#define VTD_BF_1_IOTLB_INV_DSC_AM_MASK UINT64_C(0x000000000000003f)
2022/** IH: Invalidation Hint. */
2023#define VTD_BF_1_IOTLB_INV_DSC_IH_SHIFT 6
2024#define VTD_BF_1_IOTLB_INV_DSC_IH_MASK UINT64_C(0x0000000000000040)
2025/** R: Reserved (bits 11:7). */
2026#define VTD_BF_1_IOTLB_INV_DSC_RSVD_11_7_SHIFT 7
2027#define VTD_BF_1_IOTLB_INV_DSC_RSVD_11_7_MASK UINT64_C(0x0000000000000f80)
2028/** ADDR: Address. */
2029#define VTD_BF_1_IOTLB_INV_DSC_ADDR_SHIFT 12
2030#define VTD_BF_1_IOTLB_INV_DSC_ADDR_MASK UINT64_C(0xfffffffffffff000)
2031RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_IOTLB_INV_DSC_, UINT64_C(0), UINT64_MAX,
2032 (AM, IH, RSVD_11_7, ADDR));
2033/** @} */
2034
2035
2036/** @name PASID-based IOTLB Invalidate Descriptor (p_iotlb_inv_dsc).
2037 * In accordance with the Intel spec.
2038 * @{ */
2039/** Type (Lo). */
2040#define VTD_BF_0_P_IOTLB_INV_DSC_TYPE_LO_SHIFT 0
2041#define VTD_BF_0_P_IOTLB_INV_DSC_TYPE_LO_MASK UINT64_C(0x000000000000000f)
2042/** G: Granularity. */
2043#define VTD_BF_0_P_IOTLB_INV_DSC_G_SHIFT 4
2044#define VTD_BF_0_P_IOTLB_INV_DSC_G_MASK UINT64_C(0x0000000000000030)
2045/** R: Reserved (bits 8:6). */
2046#define VTD_BF_0_P_IOTLB_INV_DSC_RSVD_8_6_SHIFT 6
2047#define VTD_BF_0_P_IOTLB_INV_DSC_RSVD_8_6_MASK UINT64_C(0x00000000000001c0)
2048/** Type (Hi). */
2049#define VTD_BF_0_P_IOTLB_INV_DSC_TYPE_HI_SHIFT 9
2050#define VTD_BF_0_P_IOTLB_INV_DSC_TYPE_HI_MASK UINT64_C(0x0000000000000e00)
2051/** R: Reserved (bits 15:12). */
2052#define VTD_BF_0_P_IOTLB_INV_DSC_RSVD_15_12_SHIFT 12
2053#define VTD_BF_0_P_IOTLB_INV_DSC_RSVD_15_12_MASK UINT64_C(0x000000000000f000)
2054/** DID: Domain Id. */
2055#define VTD_BF_0_P_IOTLB_INV_DSC_DID_SHIFT 16
2056#define VTD_BF_0_P_IOTLB_INV_DSC_DID_MASK UINT64_C(0x00000000ffff0000)
2057/** PASID: Process Address-Space Id. */
2058#define VTD_BF_0_P_IOTLB_INV_DSC_PASID_SHIFT 32
2059#define VTD_BF_0_P_IOTLB_INV_DSC_PASID_MASK UINT64_C(0x000fffff00000000)
2060/** R: Reserved (bits 63:52). */
2061#define VTD_BF_0_P_IOTLB_INV_DSC_RSVD_63_52_SHIFT 52
2062#define VTD_BF_0_P_IOTLB_INV_DSC_RSVD_63_52_MASK UINT64_C(0xfff0000000000000)
2063RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_P_IOTLB_INV_DSC_, UINT64_C(0), UINT64_MAX,
2064 (TYPE_LO, G, RSVD_8_6, TYPE_HI, RSVD_15_12, DID, PASID, RSVD_63_52));
2065
2066
2067/** AM: Address Mask. */
2068#define VTD_BF_1_P_IOTLB_INV_DSC_AM_SHIFT 0
2069#define VTD_BF_1_P_IOTLB_INV_DSC_AM_MASK UINT64_C(0x000000000000003f)
2070/** IH: Invalidation Hint. */
2071#define VTD_BF_1_P_IOTLB_INV_DSC_IH_SHIFT 6
2072#define VTD_BF_1_P_IOTLB_INV_DSC_IH_MASK UINT64_C(0x0000000000000040)
2073/** R: Reserved (bits 11:7). */
2074#define VTD_BF_1_P_IOTLB_INV_DSC_RSVD_11_7_SHIFT 7
2075#define VTD_BF_1_P_IOTLB_INV_DSC_RSVD_11_7_MASK UINT64_C(0x0000000000000f80)
2076/** ADDR: Address. */
2077#define VTD_BF_1_P_IOTLB_INV_DSC_ADDR_SHIFT 12
2078#define VTD_BF_1_P_IOTLB_INV_DSC_ADDR_MASK UINT64_C(0xfffffffffffff000)
2079RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_P_IOTLB_INV_DSC_, UINT64_C(0), UINT64_MAX,
2080 (AM, IH, RSVD_11_7, ADDR));
2081/** @} */
2082
2083
2084/** @name Device-TLB Invalidate Descriptor (dev_tlb_inv_dsc).
2085 * In accordance with the Intel spec.
2086 * @{ */
2087/** Type (Lo). */
2088#define VTD_BF_0_DEV_TLB_INV_DSC_TYPE_LO_SHIFT 0
2089#define VTD_BF_0_DEV_TLB_INV_DSC_TYPE_LO_MASK UINT64_C(0x000000000000000f)
2090/** R: Reserved (bits 8:4). */
2091#define VTD_BF_0_DEV_TLB_INV_DSC_RSVD_8_4_SHIFT 4
2092#define VTD_BF_0_DEV_TLB_INV_DSC_RSVD_8_4_MASK UINT64_C(0x00000000000001f0)
2093/** Type (Hi). */
2094#define VTD_BF_0_DEV_TLB_INV_DSC_TYPE_HI_SHIFT 9
2095#define VTD_BF_0_DEV_TLB_INV_DSC_TYPE_HI_MASK UINT64_C(0x0000000000000e00)
2096/** PFSID: Physical-Function Source Id (Lo). */
2097#define VTD_BF_0_DEV_TLB_INV_DSC_PFSID_LO_SHIFT 12
2098#define VTD_BF_0_DEV_TLB_INV_DSC_PFSID_LO_MASK UINT64_C(0x000000000000f000)
2099/** MIP: Max Invalidations Pending. */
2100#define VTD_BF_0_DEV_TLB_INV_DSC_MIP_SHIFT 16
2101#define VTD_BF_0_DEV_TLB_INV_DSC_MIP_MASK UINT64_C(0x00000000001f0000)
2102/** R: Reserved (bits 31:21). */
2103#define VTD_BF_0_DEV_TLB_INV_DSC_RSVD_31_21_SHIFT 21
2104#define VTD_BF_0_DEV_TLB_INV_DSC_RSVD_31_21_MASK UINT64_C(0x00000000ffe00000)
2105/** SID: Source Id. */
2106#define VTD_BF_0_DEV_TLB_INV_DSC_SID_SHIFT 32
2107#define VTD_BF_0_DEV_TLB_INV_DSC_SID_MASK UINT64_C(0x0000ffff00000000)
2108/** R: Reserved (bits 51:48). */
2109#define VTD_BF_0_DEV_TLB_INV_DSC_RSVD_51_48_SHIFT 48
2110#define VTD_BF_0_DEV_TLB_INV_DSC_RSVD_51_48_MASK UINT64_C(0x000f000000000000)
2111/** PFSID: Physical-Function Source Id (Hi). */
2112#define VTD_BF_0_DEV_TLB_INV_DSC_PFSID_HI_SHIFT 52
2113#define VTD_BF_0_DEV_TLB_INV_DSC_PFSID_HI_MASK UINT64_C(0xfff0000000000000)
2114RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_DEV_TLB_INV_DSC_, UINT64_C(0), UINT64_MAX,
2115 (TYPE_LO, RSVD_8_4, TYPE_HI, PFSID_LO, MIP, RSVD_31_21, SID, RSVD_51_48, PFSID_HI));
2116
2117/** S: Size. */
2118#define VTD_BF_1_DEV_TLB_INV_DSC_S_SHIFT 0
2119#define VTD_BF_1_DEV_TLB_INV_DSC_S_MASK UINT64_C(0x0000000000000001)
2120/** R: Reserved (bits 11:1). */
2121#define VTD_BF_1_DEV_TLB_INV_DSC_RSVD_11_1_SHIFT 1
2122#define VTD_BF_1_DEV_TLB_INV_DSC_RSVD_11_1_MASK UINT64_C(0x0000000000000ffe)
2123/** ADDR: Address. */
2124#define VTD_BF_1_DEV_TLB_INV_DSC_ADDR_SHIFT 12
2125#define VTD_BF_1_DEV_TLB_INV_DSC_ADDR_MASK UINT64_C(0xfffffffffffff000)
2126RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_DEV_TLB_INV_DSC_, UINT64_C(0), UINT64_MAX,
2127 (S, RSVD_11_1, ADDR));
2128/** @} */
2129
2130
2131/** @name PASID-based-device-TLB Invalidate Descriptor (p_dev_tlb_inv_dsc).
2132 * In accordance with the Intel spec.
2133 * @{ */
2134/** Type (Lo). */
2135#define VTD_BF_0_P_DEV_TLB_INV_DSC_TYPE_LO_SHIFT 0
2136#define VTD_BF_0_P_DEV_TLB_INV_DSC_TYPE_LO_MASK UINT64_C(0x000000000000000f)
2137/** MIP: Max Invalidations Pending. */
2138#define VTD_BF_0_P_DEV_TLB_INV_DSC_MIP_SHIFT 4
2139#define VTD_BF_0_P_DEV_TLB_INV_DSC_MIP_MASK UINT64_C(0x00000000000001f0)
2140/** Type (Hi). */
2141#define VTD_BF_0_P_DEV_TLB_INV_DSC_TYPE_HI_SHIFT 9
2142#define VTD_BF_0_P_DEV_TLB_INV_DSC_TYPE_HI_MASK UINT64_C(0x0000000000000e00)
2143/** PFSID: Physical-Function Source Id (Lo). */
2144#define VTD_BF_0_P_DEV_TLB_INV_DSC_PFSID_LO_SHIFT 12
2145#define VTD_BF_0_P_DEV_TLB_INV_DSC_PFSID_LO_MASK UINT64_C(0x000000000000f000)
2146/** SID: Source Id. */
2147#define VTD_BF_0_P_DEV_TLB_INV_DSC_SID_SHIFT 16
2148#define VTD_BF_0_P_DEV_TLB_INV_DSC_SID_MASK UINT64_C(0x00000000ffff0000)
2149/** PASID: Process Address-Space Id. */
2150#define VTD_BF_0_P_DEV_TLB_INV_DSC_PASID_SHIFT 32
2151#define VTD_BF_0_P_DEV_TLB_INV_DSC_PASID_MASK UINT64_C(0x000fffff00000000)
2152/** PFSID: Physical-Function Source Id (Hi). */
2153#define VTD_BF_0_P_DEV_TLB_INV_DSC_PFSID_HI_SHIFT 52
2154#define VTD_BF_0_P_DEV_TLB_INV_DSC_PFSID_HI_MASK UINT64_C(0xfff0000000000000)
2155RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_P_DEV_TLB_INV_DSC_, UINT64_C(0), UINT64_MAX,
2156 (TYPE_LO, MIP, TYPE_HI, PFSID_LO, SID, PASID, PFSID_HI));
2157
2158/** G: Granularity. */
2159#define VTD_BF_1_P_DEV_TLB_INV_DSC_G_SHIFT 0
2160#define VTD_BF_1_P_DEV_TLB_INV_DSC_G_MASK UINT64_C(0x0000000000000001)
2161/** R: Reserved (bits 10:1). */
2162#define VTD_BF_1_P_DEV_TLB_INV_DSC_RSVD_10_1_SHIFT 1
2163#define VTD_BF_1_P_DEV_TLB_INV_DSC_RSVD_10_1_MASK UINT64_C(0x00000000000007fe)
2164/** S: Size. */
2165#define VTD_BF_1_P_DEV_TLB_INV_DSC_S_SHIFT 11
2166#define VTD_BF_1_P_DEV_TLB_INV_DSC_S_MASK UINT64_C(0x0000000000000800)
2167/** ADDR: Address. */
2168#define VTD_BF_1_P_DEV_TLB_INV_DSC_ADDR_SHIFT 12
2169#define VTD_BF_1_P_DEV_TLB_INV_DSC_ADDR_MASK UINT64_C(0xfffffffffffff000)
2170RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_P_DEV_TLB_INV_DSC_, UINT64_C(0), UINT64_MAX,
2171 (G, RSVD_10_1, S, ADDR));
2172/** @} */
2173
2174
2175/** @name Interrupt Entry Cache Invalidate Descriptor (iec_inv_dsc).
2176 * In accordance with the Intel spec.
2177 * @{ */
2178/** Type (Lo). */
2179#define VTD_BF_0_IEC_INV_DSC_TYPE_LO_SHIFT 0
2180#define VTD_BF_0_IEC_INV_DSC_TYPE_LO_MASK UINT64_C(0x000000000000000f)
2181/** G: Granularity. */
2182#define VTD_BF_0_IEC_INV_DSC_G_SHIFT 4
2183#define VTD_BF_0_IEC_INV_DSC_G_MASK UINT64_C(0x0000000000000010)
2184/** R: Reserved (bits 8:5). */
2185#define VTD_BF_0_IEC_INV_DSC_RSVD_8_5_SHIFT 5
2186#define VTD_BF_0_IEC_INV_DSC_RSVD_8_5_MASK UINT64_C(0x00000000000001e0)
2187/** Type (Hi). */
2188#define VTD_BF_0_IEC_INV_DSC_TYPE_HI_SHIFT 9
2189#define VTD_BF_0_IEC_INV_DSC_TYPE_HI_MASK UINT64_C(0x0000000000000e00)
2190/** R: Reserved (bits 26:12). */
2191#define VTD_BF_0_IEC_INV_DSC_RSVD_26_12_SHIFT 12
2192#define VTD_BF_0_IEC_INV_DSC_RSVD_26_12_MASK UINT64_C(0x0000000007fff000)
2193/** IM: Index Mask. */
2194#define VTD_BF_0_IEC_INV_DSC_IM_SHIFT 27
2195#define VTD_BF_0_IEC_INV_DSC_IM_MASK UINT64_C(0x00000000f8000000)
2196/** IIDX: Interrupt Index. */
2197#define VTD_BF_0_IEC_INV_DSC_IIDX_SHIFT 32
2198#define VTD_BF_0_IEC_INV_DSC_IIDX_MASK UINT64_C(0x0000ffff00000000)
2199/** R: Reserved (bits 63:48). */
2200#define VTD_BF_0_IEC_INV_DSC_RSVD_63_48_SHIFT 48
2201#define VTD_BF_0_IEC_INV_DSC_RSVD_63_48_MASK UINT64_C(0xffff000000000000)
2202RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_IEC_INV_DSC_, UINT64_C(0), UINT64_MAX,
2203 (TYPE_LO, G, RSVD_8_5, TYPE_HI, RSVD_26_12, IM, IIDX, RSVD_63_48));
2204/** @} */
2205
2206
2207/** @name Invalidation Wait Descriptor (inv_wait_dsc).
2208 * In accordance with the Intel spec.
2209 * @{ */
2210/** Type (Lo). */
2211#define VTD_BF_0_INV_WAIT_DSC_TYPE_LO_SHIFT 0
2212#define VTD_BF_0_INV_WAIT_DSC_TYPE_LO_MASK UINT64_C(0x000000000000000f)
2213/** IF: Interrupt Flag. */
2214#define VTD_BF_0_INV_WAIT_DSC_IF_SHIFT 4
2215#define VTD_BF_0_INV_WAIT_DSC_IF_MASK UINT64_C(0x0000000000000010)
2216/** SW: Status Write. */
2217#define VTD_BF_0_INV_WAIT_DSC_SW_SHIFT 5
2218#define VTD_BF_0_INV_WAIT_DSC_SW_MASK UINT64_C(0x0000000000000020)
2219/** FN: Fence Flag. */
2220#define VTD_BF_0_INV_WAIT_DSC_FN_SHIFT 6
2221#define VTD_BF_0_INV_WAIT_DSC_FN_MASK UINT64_C(0x0000000000000040)
2222/** PD: Page-Request Drain. */
2223#define VTD_BF_0_INV_WAIT_DSC_PD_SHIFT 7
2224#define VTD_BF_0_INV_WAIT_DSC_PD_MASK UINT64_C(0x0000000000000080)
2225/** R: Reserved (bit 8). */
2226#define VTD_BF_0_INV_WAIT_DSC_RSVD_8_SHIFT 8
2227#define VTD_BF_0_INV_WAIT_DSC_RSVD_8_MASK UINT64_C(0x0000000000000100)
2228/** Type (Hi). */
2229#define VTD_BF_0_INV_WAIT_DSC_TYPE_HI_SHIFT 9
2230#define VTD_BF_0_INV_WAIT_DSC_TYPE_HI_MASK UINT64_C(0x0000000000000e00)
2231/** R: Reserved (bits 31:12). */
2232#define VTD_BF_0_INV_WAIT_DSC_RSVD_31_12_SHIFT 12
2233#define VTD_BF_0_INV_WAIT_DSC_RSVD_31_12_MASK UINT64_C(0x00000000fffff000)
2234/** STDATA: Status Data. */
2235#define VTD_BF_0_INV_WAIT_DSC_STDATA_SHIFT 32
2236#define VTD_BF_0_INV_WAIT_DSC_STDATA_MASK UINT64_C(0xffffffff00000000)
2237RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_INV_WAIT_DSC_, UINT64_C(0), UINT64_MAX,
2238 (TYPE_LO, IF, SW, FN, PD, RSVD_8, TYPE_HI, RSVD_31_12, STDATA));
2239
2240/** R: Reserved (bits 1:0). */
2241#define VTD_BF_1_INV_WAIT_DSC_RSVD_1_0_SHIFT 0
2242#define VTD_BF_1_INV_WAIT_DSC_RSVD_1_0_MASK UINT64_C(0x0000000000000003)
2243/** STADDR: Status Address. */
2244#define VTD_BF_1_INV_WAIT_DSC_STADDR_SHIFT 2
2245#define VTD_BF_1_INV_WAIT_DSC_STADDR_MASK UINT64_C(0xfffffffffffffffc)
2246RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_INV_WAIT_DSC_, UINT64_C(0), UINT64_MAX,
2247 (RSVD_1_0, STADDR));
2248
2249/* INV_WAIT_DSC: Qword 0 valid mask. */
2250#define VTD_INV_WAIT_DSC_0_VALID_MASK ( VTD_BF_0_INV_WAIT_DSC_TYPE_LO_MASK \
2251 | VTD_BF_0_INV_WAIT_DSC_IF_MASK \
2252 | VTD_BF_0_INV_WAIT_DSC_SW_MASK \
2253 | VTD_BF_0_INV_WAIT_DSC_FN_MASK \
2254 | VTD_BF_0_INV_WAIT_DSC_PD_MASK \
2255 | VTD_BF_0_INV_WAIT_DSC_TYPE_HI_MASK \
2256 | VTD_BF_0_INV_WAIT_DSC_STDATA_MASK)
2257/* INV_WAIT_DSC: Qword 1 valid mask. */
2258#define VTD_INV_WAIT_DSC_1_VALID_MASK VTD_BF_1_INV_WAIT_DSC_STADDR_MASK
2259/** @} */
2260
2261
2262/** @name Invalidation descriptor types.
2263 * In accordance with the Intel spec.
2264 * @{ */
2265#define VTD_CC_INV_DSC_TYPE 1
2266#define VTD_IOTLB_INV_DSC_TYPE 2
2267#define VTD_DEV_TLB_INV_DSC_TYPE 3
2268#define VTD_IEC_INV_DSC_TYPE 4
2269#define VTD_INV_WAIT_DSC_TYPE 5
2270#define VTD_P_IOTLB_INV_DSC_TYPE 6
2271#define VTD_PC_INV_DSC_TYPE 7
2272#define VTD_P_DEV_TLB_INV_DSC_TYPE 8
2273/** @} */
2274
2275
2276/** @name Remappable Format Interrupt Request.
2277 * In accordance with the Intel spec.
2278 * @{ */
2279/** IGN: Ignored (bits 1:0). */
2280#define VTD_BF_REMAPPABLE_MSI_ADDR_IGN_1_0_SHIFT 0
2281#define VTD_BF_REMAPPABLE_MSI_ADDR_IGN_1_0_MASK UINT32_C(0x00000003)
2282/** Handle (Hi). */
2283#define VTD_BF_REMAPPABLE_MSI_ADDR_HANDLE_HI_SHIFT 2
2284#define VTD_BF_REMAPPABLE_MSI_ADDR_HANDLE_HI_MASK UINT32_C(0x00000004)
2285/** SHV: Subhandle Valid. */
2286#define VTD_BF_REMAPPABLE_MSI_ADDR_SHV_SHIFT 3
2287#define VTD_BF_REMAPPABLE_MSI_ADDR_SHV_MASK UINT32_C(0x00000008)
2288/** Interrupt format. */
2289#define VTD_BF_REMAPPABLE_MSI_ADDR_INTR_FMT_SHIFT 4
2290#define VTD_BF_REMAPPABLE_MSI_ADDR_INTR_FMT_MASK UINT32_C(0x00000010)
2291/** Handle (Lo). */
2292#define VTD_BF_REMAPPABLE_MSI_ADDR_HANDLE_LO_SHIFT 5
2293#define VTD_BF_REMAPPABLE_MSI_ADDR_HANDLE_LO_MASK UINT32_C(0x000fffe0)
2294/** Address. */
2295#define VTD_BF_REMAPPABLE_MSI_ADDR_ADDR_SHIFT 20
2296#define VTD_BF_REMAPPABLE_MSI_ADDR_ADDR_MASK UINT32_C(0xfff00000)
2297RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_REMAPPABLE_MSI_ADDR_, UINT32_C(0), UINT32_MAX,
2298 (IGN_1_0, HANDLE_HI, SHV, INTR_FMT, HANDLE_LO, ADDR));
2299
2300/** Subhandle. */
2301#define VTD_BF_REMAPPABLE_MSI_DATA_SUBHANDLE_SHIFT 0
2302#define VTD_BF_REMAPPABLE_MSI_DATA_SUBHANDLE_MASK UINT32_C(0x0000ffff)
2303/** R: Reserved (bits 31:16). */
2304#define VTD_BF_REMAPPABLE_MSI_DATA_RSVD_31_16_SHIFT 16
2305#define VTD_BF_REMAPPABLE_MSI_DATA_RSVD_31_16_MASK UINT32_C(0xffff0000)
2306RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_REMAPPABLE_MSI_DATA_, UINT32_C(0), UINT32_MAX,
2307 (SUBHANDLE, RSVD_31_16));
2308
2309/** Remappable MSI Address: Valid mask. */
2310#define VTD_REMAPPABLE_MSI_ADDR_VALID_MASK UINT32_MAX
2311/** Remappable MSI Data: Valid mask. */
2312#define VTD_REMAPPABLE_MSI_DATA_VALID_MASK VTD_BF_REMAPPABLE_MSI_DATA_SUBHANDLE_MASK
2313
2314/** Interrupt format: Compatibility. */
2315#define VTD_INTR_FORMAT_COMPAT 0
2316/** Interrupt format: Remappable. */
2317#define VTD_INTR_FORMAT_REMAPPABLE 1
2318/** @} */
2319
2320
2321/** @name Interrupt Remapping Fault Conditions.
2322 * In accordance with the Intel spec.
2323 * @{ */
2324typedef enum VTDINTRFAULT
2325{
2326 /** Reserved bits invalid in remappable interrupt. */
2327 VTDINTRFAULT_REMAPPABLE_INTR_RSVD = 0x20,
2328 /** Interrupt index for remappable interrupt exceeds table size or referenced
2329 * address above host address width (HAW) */
2330 VTDINTRFAULT_INTR_INDEX_INVALID = 0x21,
2331 /** The IRTE is not present. */
2332 VTDINTRFAULT_IRTE_NOT_PRESENT = 0x22,
2333 /** Reading IRTE from memory failed. */
2334 VTDINTRFAULT_IRTE_READ_FAILED = 0x23,
2335 /** IRTE reserved bits invalid for an IRTE with Present bit set. */
2336 VTDINTRFAULT_IRTE_PRESENT_RSVD = 0x24,
2337 /** Compatibility format interrupt (CFI) blocked due to EIME being enabled or CFIs
2338 * were disabled. */
2339 VTDINTRFAULT_CFI_BLOCKED = 0x25,
2340 /** IRTE SID, SVT, SQ bits invalid for an IRTE with Present bit set. */
2341 VTDINTRFAULT_IRTE_PRESENT_INVALID = 0x26,
2342 /** Reading posted interrupt descriptor (PID) failed. */
2343 VTDINTRFAULT_PID_READ_FAILED = 0x27,
2344 /** PID reserved bits invalid. */
2345 VTDINTRFAULT_PID_RSVD = 0x28,
2346 /** Untranslated interrupt requested (without PASID) is invalid. */
2347 VTDINTRFAULT_IR_WITHOUT_PASID_INVALID = 0x29
2348} VTDINTRFAULT;
2349AssertCompileSize(VTDINTRFAULT, 4);
2350/** @} */
2351
2352
2353/** @name Address Translation Fault Conditions.
2354 * In accordance with the Intel spec.
2355 * @{ */
2356typedef enum VTDADDRFAULT
2357{
2358 /* Legacy root table faults (LRT). */
2359 VTDADDRFAULT_LRT_1 = 0x8,
2360 VTDADDRFAULT_LRT_2 = 0x1,
2361 VTDADDRFAULT_LRT_3 = 0xa,
2362
2363 /* Legacy Context-Table Faults (LCT). */
2364 VTDADDRFAULT_LCT_1 = 0x9,
2365 VTDADDRFAULT_LCT_2 = 0x2,
2366 VTDADDRFAULT_LCT_3 = 0xb,
2367 VTDADDRFAULT_LCT_4_0 = 0x3,
2368 VTDADDRFAULT_LCT_4_1 = 0x3,
2369 VTDADDRFAULT_LCT_4_2 = 0x3,
2370 VTDADDRFAULT_LCT_4_3 = 0x3,
2371 VTDADDRFAULT_LCT_5 = 0xd,
2372
2373 /* Legacy Second-Level Table Faults (LSL). */
2374 VTDADDRFAULT_LSL_1 = 0x7,
2375 VTDADDRFAULT_LSL_2 = 0xc,
2376
2377 /* Legacy General Faults (LGN). */
2378 VTDADDRFAULT_LGN_1_0 = 0x4,
2379 VTDADDRFAULT_LGN_1_1 = 0x4,
2380 VTDADDRFAULT_LGN_1_2 = 0x4,
2381 VTDADDRFAULT_LGN_1_3 = 0x4,
2382 VTDADDRFAULT_LGN_2 = 0x5,
2383 VTDADDRFAULT_LGN_3 = 0x6,
2384 VTDADDRFAULT_LGN_4 = 0xe,
2385
2386 /* Root-Table Address Register Faults (RTA). */
2387 VTDADDRFAULT_RTA_1_0 = 0x30,
2388 VTDADDRFAULT_RTA_1_1 = 0x30,
2389 VTDADDRFAULT_RTA_1_2 = 0x30,
2390 VTDADDRFAULT_RTA_1_3 = 0x30,
2391 VTDADDRFAULT_RTA_2 = 0x31,
2392 VTDADDRFAULT_RTA_3 = 0x32,
2393 VTDADDRFAULT_RTA_4 = 0x33,
2394
2395 /* Scalable-Mode Root-Table Faults (SRT). */
2396 VTDADDRFAULT_SRT_1 = 0x38,
2397 VTDADDRFAULT_SRT_2 = 0x39,
2398 VTDADDRFAULT_SRT_3 = 0x3a,
2399
2400 /* Scalable-Mode Context-Table Faults (SCT). */
2401 VTDADDRFAULT_SCT_1 = 0x40,
2402 VTDADDRFAULT_SCT_2 = 0x41,
2403 VTDADDRFAULT_SCT_3 = 0x42,
2404 VTDADDRFAULT_SCT_4_0 = 0x43,
2405 VTDADDRFAULT_SCT_4_1 = 0x43,
2406 VTDADDRFAULT_SCT_4_2 = 0x43,
2407 VTDADDRFAULT_SCT_5 = 0x44,
2408 VTDADDRFAULT_SCT_6 = 0x45,
2409 VTDADDRFAULT_SCT_7 = 0x46,
2410 VTDADDRFAULT_SCT_8 = 0x47,
2411 VTDADDRFAULT_SCT_9 = 0x48,
2412
2413 /* Scalable-Mode PASID-Directory Faults (SPD). */
2414 VTDADDRFAULT_SPD_1 = 0x50,
2415 VTDADDRFAULT_SPD_2 = 0x51,
2416 VTDADDRFAULT_SPD_3 = 0x52,
2417
2418 /* Scalable-Mode PASID-Table Faults (SPT). */
2419 VTDADDRFAULT_SPT_1 = 0x58,
2420 VTDADDRFAULT_SPT_2 = 0x59,
2421 VTDADDRFAULT_SPT_3 = 0x5a,
2422 VTDADDRFAULT_SPT_4_0 = 0x5b,
2423 VTDADDRFAULT_SPT_4_1 = 0x5b,
2424 VTDADDRFAULT_SPT_4_2 = 0x5b,
2425 VTDADDRFAULT_SPT_4_3 = 0x5b,
2426 VTDADDRFAULT_SPT_4_4 = 0x5b,
2427 VTDADDRFAULT_SPT_5 = 0x5c,
2428 VTDADDRFAULT_SPT_6 = 0x5d,
2429
2430 /* Scalable-Mode First-Level Table Faults (SFL). */
2431 VTDADDRFAULT_SFL_1 = 0x70,
2432 VTDADDRFAULT_SFL_2 = 0x71,
2433 VTDADDRFAULT_SFL_3 = 0x72,
2434 VTDADDRFAULT_SFL_4 = 0x73,
2435 VTDADDRFAULT_SFL_5 = 0x74,
2436 VTDADDRFAULT_SFL_6 = 0x75,
2437 VTDADDRFAULT_SFL_7 = 0x76,
2438 VTDADDRFAULT_SFL_8 = 0x77,
2439 VTDADDRFAULT_SFL_9 = 0x90,
2440 VTDADDRFAULT_SFL_10 = 0x91,
2441
2442 /* Scalable-Mode Second-Level Table Faults (SSL). */
2443 VTDADDRFAULT_SSL_1 = 0x78,
2444 VTDADDRFAULT_SSL_2 = 0x79,
2445 VTDADDRFAULT_SSL_3 = 0x7a,
2446 VTDADDRFAULT_SSL_4 = 0x7b,
2447 VTDADDRFAULT_SSL_5 = 0x7c,
2448 VTDADDRFAULT_SSL_6 = 0x7d,
2449
2450 /* Scalable-Mode General Faults (SGN). */
2451 VTDADDRFAULT_SGN_1 = 0x80,
2452 VTDADDRFAULT_SGN_2 = 0x81,
2453 VTDADDRFAULT_SGN_3 = 0x82,
2454 VTDADDRFAULT_SGN_4_0 = 0x83,
2455 VTDADDRFAULT_SGN_4_1 = 0x83,
2456 VTDADDRFAULT_SGN_4_2 = 0x83,
2457 VTDADDRFAULT_SGN_5 = 0x84,
2458 VTDADDRFAULT_SGN_6 = 0x85,
2459 VTDADDRFAULT_SGN_7 = 0x86,
2460 VTDADDRFAULT_SGN_8 = 0x87,
2461 VTDADDRFAULT_SGN_9 = 0x88,
2462 VTDADDRFAULT_SGN_10 = 0x89
2463} VTDADDRFAULT;
2464AssertCompileSize(VTDADDRFAULT, 4);
2465/** @} */
2466
2467
2468/** @name ACPI_DMAR_F_XXX: DMA Remapping Reporting Structure Flags.
2469 * In accordance with the Intel spec.
2470 * @{ */
2471/** INTR_REMAP: Interrupt remapping supported. */
2472#define ACPI_DMAR_F_INTR_REMAP RT_BIT(0)
2473/** X2APIC_OPT_OUT: Request system software to opt-out of enabling x2APIC. */
2474#define ACPI_DMAR_F_X2APIC_OPT_OUT RT_BIT(1)
2475/** DMA_CTRL_PLATFORM_OPT_IN_FLAG: Firmware initiated DMA restricted to reserved
2476 * memory regions (RMRR). */
2477#define ACPI_DMAR_F_DMA_CTRL_PLATFORM_OPT_IN RT_BIT(2)
2478/** @} */
2479
2480
2481/** @name ACPI_DRHD_F_XXX: DMA-Remapping Hardware Unit Definition Flags.
2482 * In accordance with the Intel spec.
2483 * @{ */
2484/** INCLUDE_PCI_ALL: All PCI devices under scope. */
2485#define ACPI_DRHD_F_INCLUDE_PCI_ALL RT_BIT(0)
2486/** @} */
2487
2488
2489/**
2490 * DRHD: DMA-Remapping Hardware Unit Definition.
2491 * In accordance with the Intel spec.
2492 */
2493#pragma pack(1)
2494typedef struct ACPIDRHD
2495{
2496 /** Type (must be 0=DRHD). */
2497 uint16_t uType;
2498 /** Length (must be 16 + size of device scope structure). */
2499 uint16_t cbLength;
2500 /** Flags, see ACPI_DRHD_F_XXX. */
2501 uint8_t fFlags;
2502 /** Reserved (MBZ). */
2503 uint8_t bRsvd;
2504 /** PCI segment number. */
2505 uint16_t uPciSegment;
2506 /** Register Base Address (MMIO). */
2507 uint64_t uRegBaseAddr;
2508 /* Device Scope[] Structures follow. */
2509} ACPIDRHD;
2510#pragma pack()
2511AssertCompileSize(ACPIDRHD, 16);
2512AssertCompileMemberOffset(ACPIDRHD, cbLength, 2);
2513AssertCompileMemberOffset(ACPIDRHD, fFlags, 4);
2514AssertCompileMemberOffset(ACPIDRHD, uPciSegment, 6);
2515AssertCompileMemberOffset(ACPIDRHD, uRegBaseAddr, 8);
2516
2517
2518/** @name ACPIDMARDEVSCOPE_TYPE_XXX: Device Type.
2519 * In accordance with the Intel spec.
2520 * @{ */
2521#define ACPIDMARDEVSCOPE_TYPE_PCI_ENDPOINT 1
2522#define ACPIDMARDEVSCOPE_TYPE_PCI_SUB_HIERARCHY 2
2523#define ACPIDMARDEVSCOPE_TYPE_IOAPIC 3
2524#define ACPIDMARDEVSCOPE_TYPE_MSI_CAP_HPET 4
2525#define ACPIDMARDEVSCOPE_TYPE_ACPI_NAMESPACE_DEV 5
2526/** @} */
2527
2528
2529/**
2530 * ACPI Device Scope Structure - PCI device path.
2531 * In accordance with the Intel spec.
2532 */
2533typedef struct ACPIDEVSCOPEPATH
2534{
2535 /** PCI device number. */
2536 uint8_t uDevice;
2537 /** PCI function number. */
2538 uint8_t uFunction;
2539} ACPIDEVSCOPEPATH;
2540AssertCompileSize(ACPIDEVSCOPEPATH, 2);
2541
2542
2543/**
2544 * Device Scope Structure.
2545 * In accordance with the Intel spec.
2546 */
2547#pragma pack(1)
2548typedef struct ACPIDMARDEVSCOPE
2549{
2550 /** Type, see ACPIDMARDEVSCOPE_TYPE_XXX. */
2551 uint8_t uType;
2552 /** Length (must be 6 + size of auPath field). */
2553 uint8_t cbLength;
2554 /** Reserved (MBZ). */
2555 uint8_t abRsvd[2];
2556 /** Enumeration ID (for I/O APIC, HPET and ACPI namespace devices). */
2557 uint8_t idEnum;
2558 /** First bus number for this device. */
2559 uint8_t uStartBusNum;
2560 /** Hierarchical path from the Host Bridge to the device. */
2561 ACPIDEVSCOPEPATH Path;
2562} ACPIDMARDEVSCOPE;
2563#pragma pack()
2564AssertCompileMemberOffset(ACPIDMARDEVSCOPE, cbLength, 1);
2565AssertCompileMemberOffset(ACPIDMARDEVSCOPE, idEnum, 4);
2566AssertCompileMemberOffset(ACPIDMARDEVSCOPE, uStartBusNum, 5);
2567AssertCompileMemberOffset(ACPIDMARDEVSCOPE, Path, 6);
2568
2569/** ACPI DMAR revision (not the OEM revision field).
2570 * In accordance with the Intel spec. */
2571#define ACPI_DMAR_REVISION 1
2572
2573
2574#endif /* !VBOX_INCLUDED_iommu_intel_h */
2575
Note: See TracBrowser for help on using the repository browser.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette