VirtualBox

source: vbox/trunk/include/VBox/iommu-intel.h@ 89256

Last change on this file since 89256 was 89256, checked in by vboxsync, 4 years ago

Intel IOMMU: bugref:9967 Address translation, WIP.
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File size: 132.4 KB
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1/** @file
2 * IOMMU - Input/Output Memory Management Unit (Intel).
3 */
4
5/*
6 * Copyright (C) 2021 Oracle Corporation
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * The contents of this file may alternatively be used under the terms
17 * of the Common Development and Distribution License Version 1.0
18 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19 * VirtualBox OSE distribution, in which case the provisions of the
20 * CDDL are applicable instead of those of the GPL.
21 *
22 * You may elect to license modified versions of this file under the
23 * terms and conditions of either the GPL or the CDDL or both.
24 */
25
26#ifndef VBOX_INCLUDED_iommu_intel_h
27#define VBOX_INCLUDED_iommu_intel_h
28#ifndef RT_WITHOUT_PRAGMA_ONCE
29# pragma once
30#endif
31
32#include <iprt/assertcompile.h>
33#include <iprt/types.h>
34
35
36/**
37 * @name MMIO register offsets.
38 * In accordance with the Intel spec.
39 * @{
40 */
41#define VTD_MMIO_OFF_VER_REG 0x000 /**< Version. */
42#define VTD_MMIO_OFF_CAP_REG 0x008 /**< Capability. */
43#define VTD_MMIO_OFF_ECAP_REG 0x010 /**< Extended Capability. */
44#define VTD_MMIO_OFF_GCMD_REG 0x018 /**< Global Command. */
45#define VTD_MMIO_OFF_GSTS_REG 0x01c /**< Global Status. */
46#define VTD_MMIO_OFF_RTADDR_REG 0x020 /**< Root Table Address. */
47#define VTD_MMIO_OFF_CCMD_REG 0x028 /**< Context Command. */
48
49#define VTD_MMIO_OFF_FSTS_REG 0x034 /**< Fault Status.*/
50#define VTD_MMIO_OFF_FECTL_REG 0x038 /**< Fault Event Control.*/
51#define VTD_MMIO_OFF_FEDATA_REG 0x03c /**< Fault Event Data. */
52#define VTD_MMIO_OFF_FEADDR_REG 0x040 /**< Fault Event Address. */
53#define VTD_MMIO_OFF_FEUADDR_REG 0x044 /**< Fault Event Upper Address. */
54
55#define VTD_MMIO_OFF_AFLOG_REG 0x058 /**< Advance Fault Log. */
56
57#define VTD_MMIO_OFF_PMEN_REG 0x064 /**< Protected Memory Enable (PMEN). */
58#define VTD_MMIO_OFF_PLMBASE_REG 0x068 /**< Protected Low Memory Base. */
59#define VTD_MMIO_OFF_PLMLIMIT_REG 0x06c /**< Protected Low Memory Limit. */
60#define VTD_MMIO_OFF_PHMBASE_REG 0x070 /**< Protected High Memory Base. */
61#define VTD_MMIO_OFF_PHMLIMIT_REG 0x078 /**< Protected High Memory Limit. */
62
63#define VTD_MMIO_OFF_IQH_REG 0x080 /**< Invalidation Queue Head. */
64#define VTD_MMIO_OFF_IQT_REG 0x088 /**< Invalidation Queue Tail. */
65#define VTD_MMIO_OFF_IQA_REG 0x090 /**< Invalidation Queue Address. */
66#define VTD_MMIO_OFF_ICS_REG 0x09c /**< Invalidation Completion Status. */
67#define VTD_MMIO_OFF_IECTL_REG 0x0a0 /**< Invalidation Completion Event Control. */
68#define VTD_MMIO_OFF_IEDATA_REG 0x0a4 /**< Invalidation Completion Event Data. */
69#define VTD_MMIO_OFF_IEADDR_REG 0x0a8 /**< Invalidation Completion Event Address. */
70#define VTD_MMIO_OFF_IEUADDR_REG 0x0ac /**< Invalidation Completion Event Upper Address. */
71#define VTD_MMIO_OFF_IQERCD_REG 0x0b0 /**< Invalidation Queue Error Record. */
72
73#define VTD_MMIO_OFF_IRTA_REG 0x0b8 /**< Interrupt Remapping Table Address. */
74
75#define VTD_MMIO_OFF_PQH_REG 0x0c0 /**< Page Request Queue Head. */
76#define VTD_MMIO_OFF_PQT_REG 0x0c8 /**< Page Request Queue Tail. */
77#define VTD_MMIO_OFF_PQA_REG 0x0d0 /**< Page Request Queue Address. */
78#define VTD_MMIO_OFF_PRS_REG 0x0dc /**< Page Request Status. */
79#define VTD_MMIO_OFF_PECTL_REG 0x0e0 /**< Page Request Event Control. */
80#define VTD_MMIO_OFF_PEDATA_REG 0x0e4 /**< Page Request Event Data. */
81#define VTD_MMIO_OFF_PEADDR_REG 0x0e8 /**< Page Request Event Address. */
82#define VTD_MMIO_OFF_PEUADDR_REG 0x0ec /**< Page Request Event Upper Address. */
83
84#define VTD_MMIO_OFF_MTRRCAP_REG 0x100 /**< MTRR Capabliity. */
85#define VTD_MMIO_OFF_MTRRDEF_REG 0x108 /**< MTRR Default Type. */
86
87#define VTD_MMIO_OFF_MTRR_FIX64_00000_REG 0x120 /**< Fixed-range MTRR Register for 64K at 00000. */
88#define VTD_MMIO_OFF_MTRR_FIX16K_80000_REG 0x128 /**< Fixed-range MTRR Register for 16K at 80000. */
89#define VTD_MMIO_OFF_MTRR_FIX16K_A0000_REG 0x130 /**< Fixed-range MTRR Register for 16K at a0000. */
90#define VTD_MMIO_OFF_MTRR_FIX4K_C0000_REG 0x138 /**< Fixed-range MTRR Register for 4K at c0000. */
91#define VTD_MMIO_OFF_MTRR_FIX4K_C8000_REG 0x140 /**< Fixed-range MTRR Register for 4K at c8000. */
92#define VTD_MMIO_OFF_MTRR_FIX4K_D0000_REG 0x148 /**< Fixed-range MTRR Register for 4K at d0000. */
93#define VTD_MMIO_OFF_MTRR_FIX4K_D8000_REG 0x150 /**< Fixed-range MTRR Register for 4K at d8000. */
94#define VTD_MMIO_OFF_MTRR_FIX4K_E0000_REG 0x158 /**< Fixed-range MTRR Register for 4K at e0000. */
95#define VTD_MMIO_OFF_MTRR_FIX4K_E8000_REG 0x160 /**< Fixed-range MTRR Register for 4K at e8000. */
96#define VTD_MMIO_OFF_MTRR_FIX4K_F0000_REG 0x168 /**< Fixed-range MTRR Register for 4K at f0000. */
97#define VTD_MMIO_OFF_MTRR_FIX4K_F8000_REG 0x170 /**< Fixed-range MTRR Register for 4K at f8000. */
98
99#define VTD_MMIO_OFF_MTRR_PHYSBASE0_REG 0x180 /**< Variable-range MTRR Base 0. */
100#define VTD_MMIO_OFF_MTRR_PHYSMASK0_REG 0x188 /**< Variable-range MTRR Mask 0. */
101#define VTD_MMIO_OFF_MTRR_PHYSBASE1_REG 0x190 /**< Variable-range MTRR Base 1. */
102#define VTD_MMIO_OFF_MTRR_PHYSMASK1_REG 0x198 /**< Variable-range MTRR Mask 1. */
103#define VTD_MMIO_OFF_MTRR_PHYSBASE2_REG 0x1a0 /**< Variable-range MTRR Base 2. */
104#define VTD_MMIO_OFF_MTRR_PHYSMASK2_REG 0x1a8 /**< Variable-range MTRR Mask 2. */
105#define VTD_MMIO_OFF_MTRR_PHYSBASE3_REG 0x1b0 /**< Variable-range MTRR Base 3. */
106#define VTD_MMIO_OFF_MTRR_PHYSMASK3_REG 0x1b8 /**< Variable-range MTRR Mask 3. */
107#define VTD_MMIO_OFF_MTRR_PHYSBASE4_REG 0x1c0 /**< Variable-range MTRR Base 4. */
108#define VTD_MMIO_OFF_MTRR_PHYSMASK4_REG 0x1c8 /**< Variable-range MTRR Mask 4. */
109#define VTD_MMIO_OFF_MTRR_PHYSBASE5_REG 0x1d0 /**< Variable-range MTRR Base 5. */
110#define VTD_MMIO_OFF_MTRR_PHYSMASK5_REG 0x1d8 /**< Variable-range MTRR Mask 5. */
111#define VTD_MMIO_OFF_MTRR_PHYSBASE6_REG 0x1e0 /**< Variable-range MTRR Base 6. */
112#define VTD_MMIO_OFF_MTRR_PHYSMASK6_REG 0x1e8 /**< Variable-range MTRR Mask 6. */
113#define VTD_MMIO_OFF_MTRR_PHYSBASE7_REG 0x1f0 /**< Variable-range MTRR Base 7. */
114#define VTD_MMIO_OFF_MTRR_PHYSMASK7_REG 0x1f8 /**< Variable-range MTRR Mask 7. */
115#define VTD_MMIO_OFF_MTRR_PHYSBASE8_REG 0x200 /**< Variable-range MTRR Base 8. */
116#define VTD_MMIO_OFF_MTRR_PHYSMASK8_REG 0x208 /**< Variable-range MTRR Mask 8. */
117#define VTD_MMIO_OFF_MTRR_PHYSBASE9_REG 0x210 /**< Variable-range MTRR Base 9. */
118#define VTD_MMIO_OFF_MTRR_PHYSMASK9_REG 0x218 /**< Variable-range MTRR Mask 9. */
119
120#define VTD_MMIO_OFF_VCCAP_REG 0xe00 /**< Virtual Command Capability. */
121#define VTD_MMIO_OFF_VCMD_REG 0xe10 /**< Virtual Command. */
122#define VTD_MMIO_OFF_VCMDRSVD_REG 0xe18 /**< Reserved for future for Virtual Command. */
123#define VTD_MMIO_OFF_VCRSP_REG 0xe20 /**< Virtual Command Response. */
124#define VTD_MMIO_OFF_VCRSPRSVD_REG 0xe28 /**< Reserved for future for Virtual Command Response. */
125/** @} */
126
127
128/** @name Root Entry.
129 * In accordance with the Intel spec.
130 * @{ */
131/** P: Present. */
132#define VTD_BF_0_ROOT_ENTRY_P_SHIFT 0
133#define VTD_BF_0_ROOT_ENTRY_P_MASK UINT64_C(0x0000000000000001)
134/** R: Reserved (bits 11:1). */
135#define VTD_BF_0_ROOT_ENTRY_RSVD_11_1_SHIFT 1
136#define VTD_BF_0_ROOT_ENTRY_RSVD_11_1_MASK UINT64_C(0x0000000000000ffe)
137/** CTP: Context-Table Pointer. */
138#define VTD_BF_0_ROOT_ENTRY_CTP_SHIFT 12
139#define VTD_BF_0_ROOT_ENTRY_CTP_MASK UINT64_C(0xfffffffffffff000)
140RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_ROOT_ENTRY_, UINT64_C(0), UINT64_MAX,
141 (P, RSVD_11_1, CTP));
142
143/** Root Entry. */
144typedef struct VTD_ROOT_ENTRY_T
145{
146 /** The qwords in the root entry. */
147 uint64_t au64[2];
148} VTD_ROOT_ENTRY_T;
149/** Pointer to a root entry. */
150typedef VTD_ROOT_ENTRY_T *PVTD_ROOT_ENTRY_T;
151/** Pointer to a const root entry. */
152typedef VTD_ROOT_ENTRY_T const *PCVTD_ROOT_ENTRY_T;
153
154/* Root Entry: Qword 0 valid mask. */
155#define VTD_ROOT_ENTRY_0_VALID_MASK (VTD_BF_0_ROOT_ENTRY_P_MASK | VTD_BF_0_ROOT_ENTRY_CTP_MASK)
156/* Root Entry: Qword 1 valid mask. */
157#define VTD_ROOT_ENTRY_1_VALID_MASK UINT64_C(0)
158/** @} */
159
160
161/** @name Scalable-mode Root Entry.
162 * In accordance with the Intel spec.
163 * @{ */
164/** LP: Lower Present. */
165#define VTD_BF_0_SM_ROOT_ENTRY_LP_SHIFT 0
166#define VTD_BF_0_SM_ROOT_ENTRY_LP_MASK UINT64_C(0x0000000000000001)
167/** R: Reserved (bits 11:1). */
168#define VTD_BF_0_SM_ROOT_ENTRY_RSVD_11_1_SHIFT 1
169#define VTD_BF_0_SM_ROOT_ENTRY_RSVD_11_1_MASK UINT64_C(0x0000000000000ffe)
170/** LCTP: Lower Context-Table Pointer */
171#define VTD_BF_0_SM_ROOT_ENTRY_LCTP_SHIFT 12
172#define VTD_BF_0_SM_ROOT_ENTRY_LCTP_MASK UINT64_C(0xfffffffffffff000)
173RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_SM_ROOT_ENTRY_, UINT64_C(0), UINT64_MAX,
174 (LP, RSVD_11_1, LCTP));
175
176/** UP: Upper Present. */
177#define VTD_BF_1_SM_ROOT_ENTRY_UP_SHIFT 0
178#define VTD_BF_1_SM_ROOT_ENTRY_UP_MASK UINT64_C(0x0000000000000001)
179/** R: Reserved (bits 11:1). */
180#define VTD_BF_1_SM_ROOT_ENTRY_RSVD_11_1_SHIFT 1
181#define VTD_BF_1_SM_ROOT_ENTRY_RSVD_11_1_MASK UINT64_C(0x0000000000000ffe)
182/** UCTP: Upper Context-Table Pointer. */
183#define VTD_BF_1_SM_ROOT_ENTRY_UCTP_SHIFT 12
184#define VTD_BF_1_SM_ROOT_ENTRY_UCTP_MASK UINT64_C(0xfffffffffffff000)
185RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_SM_ROOT_ENTRY_, UINT64_C(0), UINT64_MAX,
186 (UP, RSVD_11_1, UCTP));
187
188/** Scalable-mode root entry. */
189typedef struct VTD_SM_ROOT_ENTRY_T
190{
191 /** The lower scalable-mode root entry. */
192 uint64_t uLower;
193 /** The upper scalable-mode root entry. */
194 uint64_t uUpper;
195} VTD_SM_ROOT_ENTRY_T;
196/** Pointer to a scalable-mode root entry. */
197typedef VTD_SM_ROOT_ENTRY_T *PVTD_SM_ROOT_ENTRY_T;
198/** Pointer to a const scalable-mode root entry. */
199typedef VTD_SM_ROOT_ENTRY_T const *PCVTD_SM_ROOT_ENTRY_T;
200/** @} */
201
202
203/** @name Context Entry.
204 * In accordance with the Intel spec.
205 * @{ */
206/** P: Present. */
207#define VTD_BF_0_CONTEXT_ENTRY_P_SHIFT 0
208#define VTD_BF_0_CONTEXT_ENTRY_P_MASK UINT64_C(0x0000000000000001)
209/** FPD: Fault Processing Disable. */
210#define VTD_BF_0_CONTEXT_ENTRY_FPD_SHIFT 1
211#define VTD_BF_0_CONTEXT_ENTRY_FPD_MASK UINT64_C(0x0000000000000002)
212/** TT: Translation Type. */
213#define VTD_BF_0_CONTEXT_ENTRY_TT_SHIFT 2
214#define VTD_BF_0_CONTEXT_ENTRY_TT_MASK UINT64_C(0x000000000000000c)
215/** R: Reserved (bits 11:4). */
216#define VTD_BF_0_CONTEXT_ENTRY_RSVD_11_4_SHIFT 4
217#define VTD_BF_0_CONTEXT_ENTRY_RSVD_11_4_MASK UINT64_C(0x0000000000000ff0)
218/** SLPTPTR: Second Level Page Translation Pointer. */
219#define VTD_BF_0_CONTEXT_ENTRY_SLPTPTR_SHIFT 12
220#define VTD_BF_0_CONTEXT_ENTRY_SLPTPTR_MASK UINT64_C(0xfffffffffffff000)
221RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_CONTEXT_ENTRY_, UINT64_C(0), UINT64_MAX,
222 (P, FPD, TT, RSVD_11_4, SLPTPTR));
223
224/** AW: Address Width. */
225#define VTD_BF_1_CONTEXT_ENTRY_AW_SHIFT 0
226#define VTD_BF_1_CONTEXT_ENTRY_AW_MASK UINT64_C(0x0000000000000007)
227/** IGN: Ignored (bits 6:3). */
228#define VTD_BF_1_CONTEXT_ENTRY_IGN_6_3_SHIFT 3
229#define VTD_BF_1_CONTEXT_ENTRY_IGN_6_3_MASK UINT64_C(0x0000000000000078)
230/** R: Reserved (bit 7). */
231#define VTD_BF_1_CONTEXT_ENTRY_RSVD_7_SHIFT 7
232#define VTD_BF_1_CONTEXT_ENTRY_RSVD_7_MASK UINT64_C(0x0000000000000080)
233/** DID: Domain Identifier. */
234#define VTD_BF_1_CONTEXT_ENTRY_DID_SHIFT 8
235#define VTD_BF_1_CONTEXT_ENTRY_DID_MASK UINT64_C(0x0000000000ffff00)
236/** R: Reserved (bits 63:24). */
237#define VTD_BF_1_CONTEXT_ENTRY_RSVD_63_24_SHIFT 24
238#define VTD_BF_1_CONTEXT_ENTRY_RSVD_63_24_MASK UINT64_C(0xffffffffff000000)
239RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_CONTEXT_ENTRY_, UINT64_C(0), UINT64_MAX,
240 (AW, IGN_6_3, RSVD_7, DID, RSVD_63_24));
241
242/** Context Entry. */
243typedef struct VTD_CONTEXT_ENTRY_T
244{
245 /** The qwords in the context entry. */
246 uint64_t au64[2];
247} VTD_CONTEXT_ENTRY_T;
248/** Pointer to a context entry. */
249typedef VTD_CONTEXT_ENTRY_T *PVTD_CONTEXT_ENTRY_T;
250/** Pointer to a const context entry. */
251typedef VTD_CONTEXT_ENTRY_T const *PCVTD_CONTEXT_ENTRY_T;
252
253/* Context Entry: Qword 0 valid mask. */
254#define VTD_CONTEXT_ENTRY_0_VALID_MASK ( VTD_BF_0_CONTEXT_ENTRY_P_MASK \
255 | VTD_BF_0_CONTEXT_ENTRY_FPD_MASK \
256 | VTD_BF_0_CONTEXT_ENTRY_TT_MASK \
257 | VTD_BF_0_CONTEXT_ENTRY_SLPTPTR_MASK)
258/* Context Entry: Qword 1 valid mask. */
259#define VTD_CONTEXT_ENTRY_1_VALID_MASK ( VTD_BF_1_CONTEXT_ENTRY_AW_MASK \
260 | VTD_BF_1_CONTEXT_ENTRY_IGN_6_3_MASK \
261 | VTD_BF_1_CONTEXT_ENTRY_DID_MASK)
262/** @} */
263
264
265/** @name Scalable-mode Context Entry.
266 * In accordance with the Intel spec.
267 * @{ */
268/** P: Present. */
269#define VTD_BF_0_SM_CONTEXT_ENTRY_P_SHIFT 0
270#define VTD_BF_0_SM_CONTEXT_ENTRY_P_MASK UINT64_C(0x0000000000000001)
271/** FPD: Fault Processing Disable. */
272#define VTD_BF_0_SM_CONTEXT_ENTRY_FPD_SHIFT 1
273#define VTD_BF_0_SM_CONTEXT_ENTRY_FPD_MASK UINT64_C(0x0000000000000002)
274/** DTE: Device-TLB Enable. */
275#define VTD_BF_0_SM_CONTEXT_ENTRY_DTE_SHIFT 2
276#define VTD_BF_0_SM_CONTEXT_ENTRY_DTE_MASK UINT64_C(0x0000000000000004)
277/** PASIDE: PASID Enable. */
278#define VTD_BF_0_SM_CONTEXT_ENTRY_PASIDE_SHIFT 3
279#define VTD_BF_0_SM_CONTEXT_ENTRY_PASIDE_MASK UINT64_C(0x0000000000000008)
280/** PRE: Page Request Enable. */
281#define VTD_BF_0_SM_CONTEXT_ENTRY_PRE_SHIFT 4
282#define VTD_BF_0_SM_CONTEXT_ENTRY_PRE_MASK UINT64_C(0x0000000000000010)
283/** R: Reserved (bits 8:5). */
284#define VTD_BF_0_SM_CONTEXT_ENTRY_RSVD_8_5_SHIFT 5
285#define VTD_BF_0_SM_CONTEXT_ENTRY_RSVD_8_5_MASK UINT64_C(0x00000000000001e0)
286/** PDTS: PASID Directory Size. */
287#define VTD_BF_0_SM_CONTEXT_ENTRY_PDTS_SHIFT 9
288#define VTD_BF_0_SM_CONTEXT_ENTRY_PDTS_MASK UINT64_C(0x0000000000000e00)
289/** PASIDDIRPTR: PASID Directory Pointer. */
290#define VTD_BF_0_SM_CONTEXT_ENTRY_PASIDDIRPTR_SHIFT 12
291#define VTD_BF_0_SM_CONTEXT_ENTRY_PASIDDIRPTR_MASK UINT64_C(0xfffffffffffff000)
292RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_SM_CONTEXT_ENTRY_, UINT64_C(0), UINT64_MAX,
293 (P, FPD, DTE, PASIDE, PRE, RSVD_8_5, PDTS, PASIDDIRPTR));
294
295/** RID_PASID: Requested Id to PASID assignment. */
296#define VTD_BF_1_SM_CONTEXT_ENTRY_RID_PASID_SHIFT 0
297#define VTD_BF_1_SM_CONTEXT_ENTRY_RID_PASID_MASK UINT64_C(0x00000000000fffff)
298/** RID_PRIV: Requested Id to PrivilegeModeRequested assignment. */
299#define VTD_BF_1_SM_CONTEXT_ENTRY_RID_PRIV_SHIFT 20
300#define VTD_BF_1_SM_CONTEXT_ENTRY_RID_PRIV_MASK UINT64_C(0x0000000000100000)
301/** R: Reserved (bits 63:21). */
302#define VTD_BF_1_SM_CONTEXT_ENTRY_RSVD_63_21_SHIFT 21
303#define VTD_BF_1_SM_CONTEXT_ENTRY_RSVD_63_21_MASK UINT64_C(0xffffffffffe00000)
304RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_SM_CONTEXT_ENTRY_, UINT64_C(0), UINT64_MAX,
305 (RID_PASID, RID_PRIV, RSVD_63_21));
306
307/** Scalable-mode Context Entry. */
308typedef struct VTD_SM_CONTEXT_ENTRY_T
309{
310 /** The qwords in the scalable-mode context entry. */
311 uint64_t au64[4];
312} VTD_SM_CONTEXT_ENTRY_T;
313/** Pointer to a scalable-mode context entry. */
314typedef VTD_SM_CONTEXT_ENTRY_T *PVTD_SM_CONTEXT_ENTRY_T;
315/** Pointer to a const scalable-mode context entry. */
316typedef VTD_SM_CONTEXT_ENTRY_T const *PCVTD_SM_CONTEXT_ENTRY_T;
317/** @} */
318
319
320/** @name Scalable-mode PASID Directory Entry.
321 * In accordance with the Intel spec.
322 * @{ */
323/** P: Present. */
324#define VTD_BF_SM_PASID_DIR_ENTRY_P_SHIFT 0
325#define VTD_BF_SM_PASID_DIR_ENTRY_P_MASK UINT64_C(0x0000000000000001)
326/** FPD: Fault Processing Disable. */
327#define VTD_BF_SM_PASID_DIR_ENTRY_FPD_SHIFT 1
328#define VTD_BF_SM_PASID_DIR_ENTRY_FPD_MASK UINT64_C(0x0000000000000002)
329/** R: Reserved (bits 11:2). */
330#define VTD_BF_SM_PASID_DIR_ENTRY_RSVD_11_2_SHIFT 2
331#define VTD_BF_SM_PASID_DIR_ENTRY_RSVD_11_2_MASK UINT64_C(0x0000000000000ffc)
332/** SMPTBLPTR: Scalable Mode PASID Table Pointer. */
333#define VTD_BF_SM_PASID_DIR_ENTRY_SMPTBLPTR_SHIFT 12
334#define VTD_BF_SM_PASID_DIR_ENTRY_SMPTBLPTR_MASK UINT64_C(0xfffffffffffff000)
335RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_SM_PASID_DIR_ENTRY_, UINT64_C(0), UINT64_MAX,
336 (P, FPD, RSVD_11_2, SMPTBLPTR));
337
338/** Scalable-mode PASID Directory Entry. */
339typedef struct VTD_SM_PASID_DIR_ENTRY_T
340{
341 /** The scalable-mode PASID directory entry. */
342 uint64_t u;
343} VTD_SM_PASID_DIR_ENTRY_T;
344/** Pointer to a scalable-mode PASID directory entry. */
345typedef VTD_SM_PASID_DIR_ENTRY_T *PVTD_SM_PASID_DIR_ENTRY_T;
346/** Pointer to a const scalable-mode PASID directory entry. */
347typedef VTD_SM_PASID_DIR_ENTRY_T const *PCVTD_SM_PASID_DIR_ENTRY_T;
348/** @} */
349
350
351/** @name Scalable-mode PASID Table Entry.
352 * In accordance with the Intel spec.
353 * @{ */
354/** P: Present. */
355#define VTD_BF_0_SM_PASID_TBL_ENTRY_P_SHIFT 0
356#define VTD_BF_0_SM_PASID_TBL_ENTRY_P_MASK UINT64_C(0x0000000000000001)
357/** FPD: Fault Processing Disable. */
358#define VTD_BF_0_SM_PASID_TBL_ENTRY_FPD_SHIFT 1
359#define VTD_BF_0_SM_PASID_TBL_ENTRY_FPD_MASK UINT64_C(0x0000000000000002)
360/** AW: Address Width. */
361#define VTD_BF_0_SM_PASID_TBL_ENTRY_AW_SHIFT 2
362#define VTD_BF_0_SM_PASID_TBL_ENTRY_AW_MASK UINT64_C(0x000000000000001c)
363/** SLEE: Second-Level Execute Enable. */
364#define VTD_BF_0_SM_PASID_TBL_ENTRY_SLEE_SHIFT 5
365#define VTD_BF_0_SM_PASID_TBL_ENTRY_SLEE_MASK UINT64_C(0x0000000000000020)
366/** PGTT: PASID Granular Translation Type. */
367#define VTD_BF_0_SM_PASID_TBL_ENTRY_PGTT_SHIFT 6
368#define VTD_BF_0_SM_PASID_TBL_ENTRY_PGTT_MASK UINT64_C(0x00000000000001c0)
369/** SLADE: Second-Level Address/Dirty Enable. */
370#define VTD_BF_0_SM_PASID_TBL_ENTRY_SLADE_SHIFT 9
371#define VTD_BF_0_SM_PASID_TBL_ENTRY_SLADE_MASK UINT64_C(0x0000000000000200)
372/** R: Reserved (bits 11:10). */
373#define VTD_BF_0_SM_PASID_TBL_ENTRY_RSVD_11_10_SHIFT 10
374#define VTD_BF_0_SM_PASID_TBL_ENTRY_RSVD_11_10_MASK UINT64_C(0x0000000000000c00)
375/** SLPTPTR: Second-Level Page Table Pointer. */
376#define VTD_BF_0_SM_PASID_TBL_ENTRY_SLPTPTR_SHIFT 12
377#define VTD_BF_0_SM_PASID_TBL_ENTRY_SLPTPTR_MASK UINT64_C(0xfffffffffffff000)
378RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_SM_PASID_TBL_ENTRY_, UINT64_C(0), UINT64_MAX,
379 (P, FPD, AW, SLEE, PGTT, SLADE, RSVD_11_10, SLPTPTR));
380
381/** DID: Domain Identifer. */
382#define VTD_BF_1_SM_PASID_TBL_ENTRY_DID_SHIFT 0
383#define VTD_BF_1_SM_PASID_TBL_ENTRY_DID_MASK UINT64_C(0x000000000000ffff)
384/** R: Reserved (bits 22:16). */
385#define VTD_BF_1_SM_PASID_TBL_ENTRY_RSVD_22_16_SHIFT 16
386#define VTD_BF_1_SM_PASID_TBL_ENTRY_RSVD_22_16_MASK UINT64_C(0x00000000007f0000)
387/** PWSNP: Page-Walk Snoop. */
388#define VTD_BF_1_SM_PASID_TBL_ENTRY_PWSNP_SHIFT 23
389#define VTD_BF_1_SM_PASID_TBL_ENTRY_PWSNP_MASK UINT64_C(0x0000000000800000)
390/** PGSNP: Page Snoop. */
391#define VTD_BF_1_SM_PASID_TBL_ENTRY_PGSNP_SHIFT 24
392#define VTD_BF_1_SM_PASID_TBL_ENTRY_PGSNP_MASK UINT64_C(0x0000000001000000)
393/** CD: Cache Disable. */
394#define VTD_BF_1_SM_PASID_TBL_ENTRY_CD_SHIFT 25
395#define VTD_BF_1_SM_PASID_TBL_ENTRY_CD_MASK UINT64_C(0x0000000002000000)
396/** EMTE: Extended Memory Type Enable. */
397#define VTD_BF_1_SM_PASID_TBL_ENTRY_EMTE_SHIFT 26
398#define VTD_BF_1_SM_PASID_TBL_ENTRY_EMTE_MASK UINT64_C(0x0000000004000000)
399/** EMT: Extended Memory Type. */
400#define VTD_BF_1_SM_PASID_TBL_ENTRY_EMT_SHIFT 27
401#define VTD_BF_1_SM_PASID_TBL_ENTRY_EMT_MASK UINT64_C(0x0000000038000000)
402/** PWT: Page-Level Write Through. */
403#define VTD_BF_1_SM_PASID_TBL_ENTRY_PWT_SHIFT 30
404#define VTD_BF_1_SM_PASID_TBL_ENTRY_PWT_MASK UINT64_C(0x0000000040000000)
405/** PCD: Page-Level Cache Disable. */
406#define VTD_BF_1_SM_PASID_TBL_ENTRY_PCD_SHIFT 31
407#define VTD_BF_1_SM_PASID_TBL_ENTRY_PCD_MASK UINT64_C(0x0000000080000000)
408/** PAT: Page Attribute Table. */
409#define VTD_BF_1_SM_PASID_TBL_ENTRY_PAT_SHIFT 32
410#define VTD_BF_1_SM_PASID_TBL_ENTRY_PAT_MASK UINT64_C(0xffffffff00000000)
411RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_SM_PASID_TBL_ENTRY_, UINT64_C(0), UINT64_MAX,
412 (DID, RSVD_22_16, PWSNP, PGSNP, CD, EMTE, EMT, PWT, PCD, PAT));
413
414/** SRE: Supervisor Request Enable. */
415#define VTD_BF_2_SM_PASID_TBL_ENTRY_SRE_SHIFT 0
416#define VTD_BF_2_SM_PASID_TBL_ENTRY_SRE_MASK UINT64_C(0x0000000000000001)
417/** ERE: Execute Request Enable. */
418#define VTD_BF_2_SM_PASID_TBL_ENTRY_ERE_SHIFT 1
419#define VTD_BF_2_SM_PASID_TBL_ENTRY_ERE_MASK UINT64_C(0x0000000000000002)
420/** FLPM: First Level Paging Mode. */
421#define VTD_BF_2_SM_PASID_TBL_ENTRY_FLPM_SHIFT 2
422#define VTD_BF_2_SM_PASID_TBL_ENTRY_FLPM_MASK UINT64_C(0x000000000000000c)
423/** WPE: Write Protect Enable. */
424#define VTD_BF_2_SM_PASID_TBL_ENTRY_WPE_SHIFT 4
425#define VTD_BF_2_SM_PASID_TBL_ENTRY_WPE_MASK UINT64_C(0x0000000000000010)
426/** NXE: No-Execute Enable. */
427#define VTD_BF_2_SM_PASID_TBL_ENTRY_NXE_SHIFT 5
428#define VTD_BF_2_SM_PASID_TBL_ENTRY_NXE_MASK UINT64_C(0x0000000000000020)
429/** SMEP: Supervisor Mode Execute Prevent. */
430#define VTD_BF_2_SM_PASID_TBL_ENTRY_SMPE_SHIFT 6
431#define VTD_BF_2_SM_PASID_TBL_ENTRY_SMPE_MASK UINT64_C(0x0000000000000040)
432/** EAFE: Extended Accessed Flag Enable. */
433#define VTD_BF_2_SM_PASID_TBL_ENTRY_EAFE_SHIFT 7
434#define VTD_BF_2_SM_PASID_TBL_ENTRY_EAFE_MASK UINT64_C(0x0000000000000080)
435/** R: Reserved (bits 11:8). */
436#define VTD_BF_2_SM_PASID_TBL_ENTRY_RSVD_11_8_SHIFT 8
437#define VTD_BF_2_SM_PASID_TBL_ENTRY_RSVD_11_8_MASK UINT64_C(0x0000000000000f00)
438/** FLPTPTR: First Level Page Table Pointer. */
439#define VTD_BF_2_SM_PASID_TBL_ENTRY_FLPTPTR_SHIFT 12
440#define VTD_BF_2_SM_PASID_TBL_ENTRY_FLPTPTR_MASK UINT64_C(0xfffffffffffff000)
441RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_2_SM_PASID_TBL_ENTRY_, UINT64_C(0), UINT64_MAX,
442 (SRE, ERE, FLPM, WPE, NXE, SMPE, EAFE, RSVD_11_8, FLPTPTR));
443
444/** Scalable-mode PASID Table Entry. */
445typedef struct VTD_SM_PASID_TBL_ENTRY_T
446{
447 /** The qwords in the scalable-mode PASID table entry. */
448 uint64_t au64[8];
449} VTD_SM_PASID_TBL_ENTRY_T;
450/** Pointer to a scalable-mode PASID table entry. */
451typedef VTD_SM_PASID_TBL_ENTRY_T *PVTD_SM_PASID_TBL_ENTRY_T;
452/** Pointer to a const scalable-mode PASID table entry. */
453typedef VTD_SM_PASID_TBL_ENTRY_T const *PCVTD_SM_PASID_TBL_ENTRY_T;
454/** @} */
455
456
457/** @name First-Level Paging Entry.
458 * In accordance with the Intel spec.
459 * @{ */
460/** P: Present. */
461#define VTD_BF_FLP_ENTRY_P_SHIFT 0
462#define VTD_BF_FLP_ENTRY_P_MASK UINT64_C(0x0000000000000001)
463/** R/W: Read/Write. */
464#define VTD_BF_FLP_ENTRY_RW_SHIFT 1
465#define VTD_BF_FLP_ENTRY_RW_MASK UINT64_C(0x0000000000000002)
466/** U/S: User/Supervisor. */
467#define VTD_BF_FLP_ENTRY_US_SHIFT 2
468#define VTD_BF_FLP_ENTRY_US_MASK UINT64_C(0x0000000000000004)
469/** PWT: Page-Level Write Through. */
470#define VTD_BF_FLP_ENTRY_PWT_SHIFT 3
471#define VTD_BF_FLP_ENTRY_PWT_MASK UINT64_C(0x0000000000000008)
472/** PC: Page-Level Cache Disable. */
473#define VTD_BF_FLP_ENTRY_PCD_SHIFT 4
474#define VTD_BF_FLP_ENTRY_PCD_MASK UINT64_C(0x0000000000000010)
475/** A: Accessed. */
476#define VTD_BF_FLP_ENTRY_A_SHIFT 5
477#define VTD_BF_FLP_ENTRY_A_MASK UINT64_C(0x0000000000000020)
478/** IGN: Ignored (bit 6). */
479#define VTD_BF_FLP_ENTRY_IGN_6_SHIFT 6
480#define VTD_BF_FLP_ENTRY_IGN_6_MASK UINT64_C(0x0000000000000040)
481/** R: Reserved (bit 7). */
482#define VTD_BF_FLP_ENTRY_RSVD_7_SHIFT 7
483#define VTD_BF_FLP_ENTRY_RSVD_7_MASK UINT64_C(0x0000000000000080)
484/** IGN: Ignored (bits 9:8). */
485#define VTD_BF_FLP_ENTRY_IGN_9_8_SHIFT 8
486#define VTD_BF_FLP_ENTRY_IGN_9_8_MASK UINT64_C(0x0000000000000300)
487/** EA: Extended Accessed. */
488#define VTD_BF_FLP_ENTRY_EA_SHIFT 10
489#define VTD_BF_FLP_ENTRY_EA_MASK UINT64_C(0x0000000000000400)
490/** IGN: Ignored (bit 11). */
491#define VTD_BF_FLP_ENTRY_IGN_11_SHIFT 11
492#define VTD_BF_FLP_ENTRY_IGN_11_MASK UINT64_C(0x0000000000000800)
493/** ADDR: Address. */
494#define VTD_BF_FLP_ENTRY_ADDR_SHIFT 12
495#define VTD_BF_FLP_ENTRY_ADDR_MASK UINT64_C(0x000ffffffffff000)
496/** IGN: Ignored (bits 62:52). */
497#define VTD_BF_FLP_ENTRY_IGN_62_52_SHIFT 52
498#define VTD_BF_FLP_ENTRY_IGN_62_52_MASK UINT64_C(0x7ff0000000000000)
499/** XD: Execute Disabled. */
500#define VTD_BF_FLP_ENTRY_XD_SHIFT 63
501#define VTD_BF_FLP_ENTRY_XD_MASK UINT64_C(0x8000000000000000)
502RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_FLP_ENTRY_, UINT64_C(0), UINT64_MAX,
503 (P, RW, US, PWT, PCD, A, IGN_6, RSVD_7, IGN_9_8, EA, IGN_11, ADDR, IGN_62_52, XD));
504
505/** First-Level Paging Entry. */
506typedef struct VTD_FLP_ENTRY_T
507{
508 /** The first-level paging entry. */
509 uint64_t u;
510} VTD_FLP_ENTRY_T;
511/** Pointer to a first-level paging entry. */
512typedef VTD_FLP_ENTRY_T *PVTD_FLP_ENTRY_T;
513/** Pointer to a const first-level paging entry. */
514typedef VTD_FLP_ENTRY_T const *PCVTD_FLP_ENTRY_T;
515/** @} */
516
517
518/** @name Second-Level Paging Entry.
519 * In accordance with the Intel spec.
520 * @{ */
521/** R: Read. */
522#define VTD_BF_SLP_ENTRY_R_SHIFT 0
523#define VTD_BF_SLP_ENTRY_R_MASK UINT64_C(0x0000000000000001)
524/** W: Write. */
525#define VTD_BF_SLP_ENTRY_W_SHIFT 1
526#define VTD_BF_SLP_ENTRY_W_MASK UINT64_C(0x0000000000000002)
527/** X: Execute. */
528#define VTD_BF_SLP_ENTRY_X_SHIFT 2
529#define VTD_BF_SLP_ENTRY_X_MASK UINT64_C(0x0000000000000004)
530/** IGN: Ignored (bits 6:3). */
531#define VTD_BF_SLP_ENTRY_IGN_6_3_SHIFT 3
532#define VTD_BF_SLP_ENTRY_IGN_6_3_MASK UINT64_C(0x0000000000000078)
533/** R: Reserved (bit 7). */
534#define VTD_BF_SLP_ENTRY_RSVD_7_SHIFT 7
535#define VTD_BF_SLP_ENTRY_RSVD_7_MASK UINT64_C(0x0000000000000080)
536/** A: Accessed. */
537#define VTD_BF_SLP_ENTRY_A_SHIFT 8
538#define VTD_BF_SLP_ENTRY_A_MASK UINT64_C(0x0000000000000100)
539/** IGN: Ignored (bits 10:9). */
540#define VTD_BF_SLP_ENTRY_IGN_10_9_SHIFT 9
541#define VTD_BF_SLP_ENTRY_IGN_10_9_MASK UINT64_C(0x0000000000000600)
542/** R: Reserved (bit 11). */
543#define VTD_BF_SLP_ENTRY_RSVD_11_SHIFT 11
544#define VTD_BF_SLP_ENTRY_RSVD_11_MASK UINT64_C(0x0000000000000800)
545/** ADDR: Address. */
546#define VTD_BF_SLP_ENTRY_ADDR_SHIFT 12
547#define VTD_BF_SLP_ENTRY_ADDR_MASK UINT64_C(0x000ffffffffff000)
548/** IGN: Ignored (bits 61:52). */
549#define VTD_BF_SLP_ENTRY_IGN_61_52_SHIFT 52
550#define VTD_BF_SLP_ENTRY_IGN_61_52_MASK UINT64_C(0x3ff0000000000000)
551/** R: Reserved (bit 62). */
552#define VTD_BF_SLP_ENTRY_RSVD_62_SHIFT 62
553#define VTD_BF_SLP_ENTRY_RSVD_62_MASK UINT64_C(0x4000000000000000)
554/** IGN: Ignored (bit 63). */
555#define VTD_BF_SLP_ENTRY_IGN_63_SHIFT 63
556#define VTD_BF_SLP_ENTRY_IGN_63_MASK UINT64_C(0x8000000000000000)
557RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_SLP_ENTRY_, UINT64_C(0), UINT64_MAX,
558 (R, W, X, IGN_6_3, RSVD_7, A, IGN_10_9, RSVD_11, ADDR, IGN_61_52, RSVD_62, IGN_63));
559
560/** Second-Level Paging Entry. */
561typedef struct VTD_SLP_ENTRY_T
562{
563 /** The second-level paging entry. */
564 uint64_t u;
565} VTD_SLP_ENTRY_T;
566/** Pointer to a second-level paging entry. */
567typedef VTD_SLP_ENTRY_T *PVTD_SLP_ENTRY_T;
568/** Pointer to a const second-level paging entry. */
569typedef VTD_SLP_ENTRY_T const *PCVTD_SLP_ENTRY_T;
570/** @} */
571
572
573/** @name Fault Record.
574 * In accordance with the Intel spec.
575 * @{ */
576/** R: Reserved (bits 11:0). */
577#define VTD_BF_0_FAULT_RECORD_RSVD_11_0_SHIFT 0
578#define VTD_BF_0_FAULT_RECORD_RSVD_11_0_MASK UINT64_C(0x0000000000000fff)
579/** FI: Fault Information. */
580#define VTD_BF_0_FAULT_RECORD_FI_SHIFT 12
581#define VTD_BF_0_FAULT_RECORD_FI_MASK UINT64_C(0xfffffffffffff000)
582RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_FAULT_RECORD_, UINT64_C(0), UINT64_MAX,
583 (RSVD_11_0, FI));
584
585/** SID: Source identifier. */
586#define VTD_BF_1_FAULT_RECORD_SID_SHIFT 0
587#define VTD_BF_1_FAULT_RECORD_SID_MASK UINT64_C(0x000000000000ffff)
588/** R: Reserved (bits 28:16). */
589#define VTD_BF_1_FAULT_RECORD_RSVD_28_16_SHIFT 16
590#define VTD_BF_1_FAULT_RECORD_RSVD_28_16_MASK UINT64_C(0x000000001fff0000)
591/** PRIV: Privilege Mode Requested. */
592#define VTD_BF_1_FAULT_RECORD_PRIV_SHIFT 29
593#define VTD_BF_1_FAULT_RECORD_PRIV_MASK UINT64_C(0x0000000020000000)
594/** EXE: Execute Permission Requested. */
595#define VTD_BF_1_FAULT_RECORD_EXE_SHIFT 30
596#define VTD_BF_1_FAULT_RECORD_EXE_MASK UINT64_C(0x0000000040000000)
597/** PP: PASID Present. */
598#define VTD_BF_1_FAULT_RECORD_PP_SHIFT 31
599#define VTD_BF_1_FAULT_RECORD_PP_MASK UINT64_C(0x0000000080000000)
600/** FR: Fault Reason. */
601#define VTD_BF_1_FAULT_RECORD_FR_SHIFT 32
602#define VTD_BF_1_FAULT_RECORD_FR_MASK UINT64_C(0x000000ff00000000)
603/** PV: PASID Value. */
604#define VTD_BF_1_FAULT_RECORD_PV_SHIFT 40
605#define VTD_BF_1_FAULT_RECORD_PV_MASK UINT64_C(0x0fffff0000000000)
606/** AT: Address Type. */
607#define VTD_BF_1_FAULT_RECORD_AT_SHIFT 60
608#define VTD_BF_1_FAULT_RECORD_AT_MASK UINT64_C(0x3000000000000000)
609/** T: Type. */
610#define VTD_BF_1_FAULT_RECORD_T_SHIFT 62
611#define VTD_BF_1_FAULT_RECORD_T_MASK UINT64_C(0x4000000000000000)
612/** R: Reserved (bit 127). */
613#define VTD_BF_1_FAULT_RECORD_RSVD_63_SHIFT 63
614#define VTD_BF_1_FAULT_RECORD_RSVD_63_MASK UINT64_C(0x8000000000000000)
615RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_FAULT_RECORD_, UINT64_C(0), UINT64_MAX,
616 (SID, RSVD_28_16, PRIV, EXE, PP, FR, PV, AT, T, RSVD_63));
617
618/** Fault record. */
619typedef struct VTD_FAULT_RECORD_T
620{
621 /** The qwords in the fault record. */
622 uint64_t au64[2];
623} VTD_FAULT_RECORD_T;
624/** Pointer to a fault record. */
625typedef VTD_FAULT_RECORD_T *PVTD_FAULT_RECORD_T;
626/** Pointer to a const fault record. */
627typedef VTD_FAULT_RECORD_T const *PCVTD_FAULT_RECORD_T;
628/** @} */
629
630
631/** @name Interrupt Remapping Table Entry (IRTE) for Remapped Interrupts.
632 * In accordance with the Intel spec.
633 * @{ */
634/** P: Present. */
635#define VTD_BF_0_IRTE_P_SHIFT 0
636#define VTD_BF_0_IRTE_P_MASK UINT64_C(0x0000000000000001)
637/** FPD: Fault Processing Disable. */
638#define VTD_BF_0_IRTE_FPD_SHIFT 1
639#define VTD_BF_0_IRTE_FPD_MASK UINT64_C(0x0000000000000002)
640/** DM: Destination Mode (0=physical, 1=logical). */
641#define VTD_BF_0_IRTE_DM_SHIFT 2
642#define VTD_BF_0_IRTE_DM_MASK UINT64_C(0x0000000000000004)
643/** RH: Redirection Hint. */
644#define VTD_BF_0_IRTE_RH_SHIFT 3
645#define VTD_BF_0_IRTE_RH_MASK UINT64_C(0x0000000000000008)
646/** TM: Trigger Mode. */
647#define VTD_BF_0_IRTE_TM_SHIFT 4
648#define VTD_BF_0_IRTE_TM_MASK UINT64_C(0x0000000000000010)
649/** DLM: Delivery Mode. */
650#define VTD_BF_0_IRTE_DLM_SHIFT 5
651#define VTD_BF_0_IRTE_DLM_MASK UINT64_C(0x00000000000000e0)
652/** AVL: Available. */
653#define VTD_BF_0_IRTE_AVAIL_SHIFT 8
654#define VTD_BF_0_IRTE_AVAIL_MASK UINT64_C(0x0000000000000f00)
655/** R: Reserved (bits 14:12). */
656#define VTD_BF_0_IRTE_RSVD_14_12_SHIFT 12
657#define VTD_BF_0_IRTE_RSVD_14_12_MASK UINT64_C(0x0000000000007000)
658/** IM: IRTE Mode. */
659#define VTD_BF_0_IRTE_IM_SHIFT 15
660#define VTD_BF_0_IRTE_IM_MASK UINT64_C(0x0000000000008000)
661/** V: Vector. */
662#define VTD_BF_0_IRTE_V_SHIFT 16
663#define VTD_BF_0_IRTE_V_MASK UINT64_C(0x0000000000ff0000)
664/** R: Reserved (bits 31:24). */
665#define VTD_BF_0_IRTE_RSVD_31_24_SHIFT 24
666#define VTD_BF_0_IRTE_RSVD_31_24_MASK UINT64_C(0x00000000ff000000)
667/** DST: Desination Id. */
668#define VTD_BF_0_IRTE_DST_SHIFT 32
669#define VTD_BF_0_IRTE_DST_MASK UINT64_C(0xffffffff00000000)
670/** R: Reserved (bits 39:32) when EIME=0. */
671#define VTD_BF_0_IRTE_RSVD_39_32_SHIFT 32
672#define VTD_BF_0_IRTE_RSVD_39_32_MASK UINT64_C(0x000000ff00000000)
673/** DST_XAPIC: Destination Id when EIME=0. */
674#define VTD_BF_0_IRTE_DST_XAPIC_SHIFT 40
675#define VTD_BF_0_IRTE_DST_XAPIC_MASK UINT64_C(0x0000ff0000000000)
676/** R: Reserved (bits 63:48) when EIME=0. */
677#define VTD_BF_0_IRTE_RSVD_63_48_SHIFT 48
678#define VTD_BF_0_IRTE_RSVD_63_48_MASK UINT64_C(0xffff000000000000)
679RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_IRTE_, UINT64_C(0), UINT64_MAX,
680 (P, FPD, DM, RH, TM, DLM, AVAIL, RSVD_14_12, IM, V, RSVD_31_24, DST));
681RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_IRTE_, UINT64_C(0), UINT64_MAX,
682 (P, FPD, DM, RH, TM, DLM, AVAIL, RSVD_14_12, IM, V, RSVD_31_24, RSVD_39_32, DST_XAPIC, RSVD_63_48));
683
684/** SID: Source Identifier. */
685#define VTD_BF_1_IRTE_SID_SHIFT 0
686#define VTD_BF_1_IRTE_SID_MASK UINT64_C(0x000000000000ffff)
687/** SQ: Source-Id Qualifier. */
688#define VTD_BF_1_IRTE_SQ_SHIFT 16
689#define VTD_BF_1_IRTE_SQ_MASK UINT64_C(0x0000000000030000)
690/** SVT: Source Validation Type. */
691#define VTD_BF_1_IRTE_SVT_SHIFT 18
692#define VTD_BF_1_IRTE_SVT_MASK UINT64_C(0x00000000000c0000)
693/** R: Reserved (bits 127:84). */
694#define VTD_BF_1_IRTE_RSVD_63_20_SHIFT 20
695#define VTD_BF_1_IRTE_RSVD_63_20_MASK UINT64_C(0xfffffffffff00000)
696RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_IRTE_, UINT64_C(0), UINT64_MAX,
697 (SID, SQ, SVT, RSVD_63_20));
698
699/** IRTE: Qword 0 valid mask when EIME=1. */
700#define VTD_IRTE_0_X2APIC_VALID_MASK ( VTD_BF_0_IRTE_P_MASK | VTD_BF_0_IRTE_FPD_MASK \
701 | VTD_BF_0_IRTE_DM_MASK | VTD_BF_0_IRTE_RH_MASK \
702 | VTD_BF_0_IRTE_TM_MASK | VTD_BF_0_IRTE_DLM_MASK \
703 | VTD_BF_0_IRTE_AVAIL_MASK | VTD_BF_0_IRTE_IM_MASK \
704 | VTD_BF_0_IRTE_V_MASK | VTD_BF_0_IRTE_DST_MASK)
705/** IRTE: Qword 0 valid mask when EIME=0. */
706#define VTD_IRTE_0_XAPIC_VALID_MASK ( VTD_BF_0_IRTE_P_MASK | VTD_BF_0_IRTE_FPD_MASK \
707 | VTD_BF_0_IRTE_DM_MASK | VTD_BF_0_IRTE_RH_MASK \
708 | VTD_BF_0_IRTE_TM_MASK | VTD_BF_0_IRTE_DLM_MASK \
709 | VTD_BF_0_IRTE_AVAIL_MASK | VTD_BF_0_IRTE_IM_MASK \
710 | VTD_BF_0_IRTE_V_MASK | VTD_BF_0_IRTE_DST_XAPIC_MASK)
711/** IRTE: Qword 1 valid mask. */
712#define VTD_IRTE_1_VALID_MASK ( VTD_BF_1_IRTE_SID_MASK | VTD_BF_1_IRTE_SQ_MASK \
713 | VTD_BF_1_IRTE_SVT_MASK)
714
715/** Interrupt Remapping Table Entry (IRTE) for remapped interrupts. */
716typedef struct VTD_IRTE_T
717{
718 /** The qwords in the IRTE. */
719 uint64_t au64[2];
720} VTD_IRTE_T;
721/** Pointer to an IRTE. */
722typedef VTD_IRTE_T *PVTD_IRTE_T;
723/** Pointer to a const IRTE. */
724typedef VTD_IRTE_T const *PCVTD_IRTE_T;
725
726/** IRTE SVT: No validation required. */
727#define VTD_IRTE_SVT_NONE 0
728/** IRTE SVT: Validate using a mask derived from SID and SQT. */
729#define VTD_IRTE_SVT_VALIDATE_MASK 1
730/** IRTE SVT: Validate using Bus range in the SID. */
731#define VTD_IRTE_SVT_VALIDATE_BUS_RANGE 2
732/** IRTE SVT: Reserved. */
733#define VTD_IRTE_SVT_VALIDATE_RSVD 3
734/** @} */
735
736
737/** @name Version Register (VER_REG).
738 * In accordance with the Intel spec.
739 * @{ */
740/** Min: Minor Version Number. */
741#define VTD_BF_VER_REG_MIN_SHIFT 0
742#define VTD_BF_VER_REG_MIN_MASK UINT32_C(0x0000000f)
743/** Max: Major Version Number. */
744#define VTD_BF_VER_REG_MAX_SHIFT 4
745#define VTD_BF_VER_REG_MAX_MASK UINT32_C(0x000000f0)
746/** R: Reserved (bits 31:8). */
747#define VTD_BF_VER_REG_RSVD_31_8_SHIFT 8
748#define VTD_BF_VER_REG_RSVD_31_8_MASK UINT32_C(0xffffff00)
749RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_VER_REG_, UINT32_C(0), UINT32_MAX,
750 (MIN, MAX, RSVD_31_8));
751/** RW: Read/write mask. */
752#define VTD_VER_REG_RW_MASK UINT32_C(0)
753/** @} */
754
755
756/** @name Capability Register (CAP_REG).
757 * In accordance with the Intel spec.
758 * @{ */
759/** ND: Number of domains supported. */
760#define VTD_BF_CAP_REG_ND_SHIFT 0
761#define VTD_BF_CAP_REG_ND_MASK UINT64_C(0x0000000000000007)
762/** AFL: Advanced Fault Logging. */
763#define VTD_BF_CAP_REG_AFL_SHIFT 3
764#define VTD_BF_CAP_REG_AFL_MASK UINT64_C(0x0000000000000008)
765/** RWBF: Required Write-Buffer Flushing. */
766#define VTD_BF_CAP_REG_RWBF_SHIFT 4
767#define VTD_BF_CAP_REG_RWBF_MASK UINT64_C(0x0000000000000010)
768/** PLMR: Protected Low-Memory Region. */
769#define VTD_BF_CAP_REG_PLMR_SHIFT 5
770#define VTD_BF_CAP_REG_PLMR_MASK UINT64_C(0x0000000000000020)
771/** PHMR: Protected High-Memory Region. */
772#define VTD_BF_CAP_REG_PHMR_SHIFT 6
773#define VTD_BF_CAP_REG_PHMR_MASK UINT64_C(0x0000000000000040)
774/** CM: Caching Mode. */
775#define VTD_BF_CAP_REG_CM_SHIFT 7
776#define VTD_BF_CAP_REG_CM_MASK UINT64_C(0x0000000000000080)
777/** SAGAW: Supported Adjusted Guest Address Widths. */
778#define VTD_BF_CAP_REG_SAGAW_SHIFT 8
779#define VTD_BF_CAP_REG_SAGAW_MASK UINT64_C(0x0000000000001f00)
780/** R: Reserved (bits 15:13). */
781#define VTD_BF_CAP_REG_RSVD_15_13_SHIFT 13
782#define VTD_BF_CAP_REG_RSVD_15_13_MASK UINT64_C(0x000000000000e000)
783/** MGAW: Maximum Guest Address Width. */
784#define VTD_BF_CAP_REG_MGAW_SHIFT 16
785#define VTD_BF_CAP_REG_MGAW_MASK UINT64_C(0x00000000003f0000)
786/** ZLR: Zero Length Read. */
787#define VTD_BF_CAP_REG_ZLR_SHIFT 22
788#define VTD_BF_CAP_REG_ZLR_MASK UINT64_C(0x0000000000400000)
789/** DEP: Deprecated MBZ. Reserved (bit 23). */
790#define VTD_BF_CAP_REG_RSVD_23_SHIFT 23
791#define VTD_BF_CAP_REG_RSVD_23_MASK UINT64_C(0x0000000000800000)
792/** FRO: Fault-recording Register Offset. */
793#define VTD_BF_CAP_REG_FRO_SHIFT 24
794#define VTD_BF_CAP_REG_FRO_MASK UINT64_C(0x00000003ff000000)
795/** SLLPS: Second Level Large Page Support. */
796#define VTD_BF_CAP_REG_SLLPS_SHIFT 34
797#define VTD_BF_CAP_REG_SLLPS_MASK UINT64_C(0x0000003c00000000)
798/** R: Reserved (bit 38). */
799#define VTD_BF_CAP_REG_RSVD_38_SHIFT 38
800#define VTD_BF_CAP_REG_RSVD_38_MASK UINT64_C(0x0000004000000000)
801/** PSI: Page Selective Invalidation. */
802#define VTD_BF_CAP_REG_PSI_SHIFT 39
803#define VTD_BF_CAP_REG_PSI_MASK UINT64_C(0x0000008000000000)
804/** NFR: Number of Fault-recording Registers. */
805#define VTD_BF_CAP_REG_NFR_SHIFT 40
806#define VTD_BF_CAP_REG_NFR_MASK UINT64_C(0x0000ff0000000000)
807/** MAMV: Maximum Address Mask Value. */
808#define VTD_BF_CAP_REG_MAMV_SHIFT 48
809#define VTD_BF_CAP_REG_MAMV_MASK UINT64_C(0x003f000000000000)
810/** DWD: Write Draining. */
811#define VTD_BF_CAP_REG_DWD_SHIFT 54
812#define VTD_BF_CAP_REG_DWD_MASK UINT64_C(0x0040000000000000)
813/** DRD: Read Draining. */
814#define VTD_BF_CAP_REG_DRD_SHIFT 55
815#define VTD_BF_CAP_REG_DRD_MASK UINT64_C(0x0080000000000000)
816/** FL1GP: First Level 1 GB Page Support. */
817#define VTD_BF_CAP_REG_FL1GP_SHIFT 56
818#define VTD_BF_CAP_REG_FL1GP_MASK UINT64_C(0x0100000000000000)
819/** R: Reserved (bits 58:57). */
820#define VTD_BF_CAP_REG_RSVD_58_57_SHIFT 57
821#define VTD_BF_CAP_REG_RSVD_58_57_MASK UINT64_C(0x0600000000000000)
822/** PI: Posted Interrupt Support. */
823#define VTD_BF_CAP_REG_PI_SHIFT 59
824#define VTD_BF_CAP_REG_PI_MASK UINT64_C(0x0800000000000000)
825/** FL5LP: First Level 5-level Paging Support. */
826#define VTD_BF_CAP_REG_FL5LP_SHIFT 60
827#define VTD_BF_CAP_REG_FL5LP_MASK UINT64_C(0x1000000000000000)
828/** R: Reserved (bit 61). */
829#define VTD_BF_CAP_REG_RSVD_61_SHIFT 61
830#define VTD_BF_CAP_REG_RSVD_61_MASK UINT64_C(0x2000000000000000)
831/** ESIRTPS: Enhanced Set Interrupt Root Table Pointer Support. */
832#define VTD_BF_CAP_REG_ESIRTPS_SHIFT 62
833#define VTD_BF_CAP_REG_ESIRTPS_MASK UINT64_C(0x4000000000000000)
834/** : Enhanced Set Root Table Pointer Support. */
835#define VTD_BF_CAP_REG_ESRTPS_SHIFT 63
836#define VTD_BF_CAP_REG_ESRTPS_MASK UINT64_C(0x8000000000000000)
837RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_CAP_REG_, UINT64_C(0), UINT64_MAX,
838 (ND, AFL, RWBF, PLMR, PHMR, CM, SAGAW, RSVD_15_13, MGAW, ZLR, RSVD_23, FRO, SLLPS, RSVD_38, PSI, NFR,
839 MAMV, DWD, DRD, FL1GP, RSVD_58_57, PI, FL5LP, RSVD_61, ESIRTPS, ESRTPS));
840
841/** RW: Read/write mask. */
842#define VTD_CAP_REG_RW_MASK UINT64_C(0)
843/** @} */
844
845
846/** @name Extended Capability Register (ECAP_REG).
847 * In accordance with the Intel spec.
848 * @{ */
849/** C: Page-walk Coherence. */
850#define VTD_BF_ECAP_REG_C_SHIFT 0
851#define VTD_BF_ECAP_REG_C_MASK UINT64_C(0x0000000000000001)
852/** QI: Queued Invalidation Support. */
853#define VTD_BF_ECAP_REG_QI_SHIFT 1
854#define VTD_BF_ECAP_REG_QI_MASK UINT64_C(0x0000000000000002)
855/** DT: Device-TLB Support. */
856#define VTD_BF_ECAP_REG_DT_SHIFT 2
857#define VTD_BF_ECAP_REG_DT_MASK UINT64_C(0x0000000000000004)
858/** IR: Interrupt Remapping Support. */
859#define VTD_BF_ECAP_REG_IR_SHIFT 3
860#define VTD_BF_ECAP_REG_IR_MASK UINT64_C(0x0000000000000008)
861/** EIM: Extended Interrupt Mode. */
862#define VTD_BF_ECAP_REG_EIM_SHIFT 4
863#define VTD_BF_ECAP_REG_EIM_MASK UINT64_C(0x0000000000000010)
864/** DEP: Deprecated MBZ. Reserved (bit 5). */
865#define VTD_BF_ECAP_REG_RSVD_5_SHIFT 5
866#define VTD_BF_ECAP_REG_RSVD_5_MASK UINT64_C(0x0000000000000020)
867/** PT: Pass Through. */
868#define VTD_BF_ECAP_REG_PT_SHIFT 6
869#define VTD_BF_ECAP_REG_PT_MASK UINT64_C(0x0000000000000040)
870/** SC: Snoop Control. */
871#define VTD_BF_ECAP_REG_SC_SHIFT 7
872#define VTD_BF_ECAP_REG_SC_MASK UINT64_C(0x0000000000000080)
873/** IRO: IOTLB Register Offset. */
874#define VTD_BF_ECAP_REG_IRO_SHIFT 8
875#define VTD_BF_ECAP_REG_IRO_MASK UINT64_C(0x000000000003ff00)
876/** R: Reserved (bits 19:18). */
877#define VTD_BF_ECAP_REG_RSVD_19_18_SHIFT 18
878#define VTD_BF_ECAP_REG_RSVD_19_18_MASK UINT64_C(0x00000000000c0000)
879/** MHMV: Maximum Handle Mask Value. */
880#define VTD_BF_ECAP_REG_MHMV_SHIFT 20
881#define VTD_BF_ECAP_REG_MHMV_MASK UINT64_C(0x0000000000f00000)
882/** DEP: Deprecated MBZ. Reserved (bit 24). */
883#define VTD_BF_ECAP_REG_RSVD_24_SHIFT 24
884#define VTD_BF_ECAP_REG_RSVD_24_MASK UINT64_C(0x0000000001000000)
885/** MTS: Memory Type Support. */
886#define VTD_BF_ECAP_REG_MTS_SHIFT 25
887#define VTD_BF_ECAP_REG_MTS_MASK UINT64_C(0x0000000002000000)
888/** NEST: Nested Translation Support. */
889#define VTD_BF_ECAP_REG_NEST_SHIFT 26
890#define VTD_BF_ECAP_REG_NEST_MASK UINT64_C(0x0000000004000000)
891/** R: Reserved (bit 27). */
892#define VTD_BF_ECAP_REG_RSVD_27_SHIFT 27
893#define VTD_BF_ECAP_REG_RSVD_27_MASK UINT64_C(0x0000000008000000)
894/** DEP: Deprecated MBZ. Reserved (bit 28). */
895#define VTD_BF_ECAP_REG_RSVD_28_SHIFT 28
896#define VTD_BF_ECAP_REG_RSVD_28_MASK UINT64_C(0x0000000010000000)
897/** PRS: Page Request Support. */
898#define VTD_BF_ECAP_REG_PRS_SHIFT 29
899#define VTD_BF_ECAP_REG_PRS_MASK UINT64_C(0x0000000020000000)
900/** ERS: Execute Request Support. */
901#define VTD_BF_ECAP_REG_ERS_SHIFT 30
902#define VTD_BF_ECAP_REG_ERS_MASK UINT64_C(0x0000000040000000)
903/** SRS: Supervisor Request Support. */
904#define VTD_BF_ECAP_REG_SRS_SHIFT 31
905#define VTD_BF_ECAP_REG_SRS_MASK UINT64_C(0x0000000080000000)
906/** R: Reserved (bit 32). */
907#define VTD_BF_ECAP_REG_RSVD_32_SHIFT 32
908#define VTD_BF_ECAP_REG_RSVD_32_MASK UINT64_C(0x0000000100000000)
909/** NWFS: No Write Flag Support. */
910#define VTD_BF_ECAP_REG_NWFS_SHIFT 33
911#define VTD_BF_ECAP_REG_NWFS_MASK UINT64_C(0x0000000200000000)
912/** EAFS: Extended Accessed Flags Support. */
913#define VTD_BF_ECAP_REG_EAFS_SHIFT 34
914#define VTD_BF_ECAP_REG_EAFS_MASK UINT64_C(0x0000000400000000)
915/** PSS: PASID Size Supported. */
916#define VTD_BF_ECAP_REG_PSS_SHIFT 35
917#define VTD_BF_ECAP_REG_PSS_MASK UINT64_C(0x000000f800000000)
918/** PASID: Process Address Space ID Support. */
919#define VTD_BF_ECAP_REG_PASID_SHIFT 40
920#define VTD_BF_ECAP_REG_PASID_MASK UINT64_C(0x0000010000000000)
921/** DIT: Device-TLB Invalidation Throttle. */
922#define VTD_BF_ECAP_REG_DIT_SHIFT 41
923#define VTD_BF_ECAP_REG_DIT_MASK UINT64_C(0x0000020000000000)
924/** PDS: Page-request Drain Support. */
925#define VTD_BF_ECAP_REG_PDS_SHIFT 42
926#define VTD_BF_ECAP_REG_PDS_MASK UINT64_C(0x0000040000000000)
927/** SMTS: Scalable-Mode Translation Support. */
928#define VTD_BF_ECAP_REG_SMTS_SHIFT 43
929#define VTD_BF_ECAP_REG_SMTS_MASK UINT64_C(0x0000080000000000)
930/** VCS: Virtual Command Support. */
931#define VTD_BF_ECAP_REG_VCS_SHIFT 44
932#define VTD_BF_ECAP_REG_VCS_MASK UINT64_C(0x0000100000000000)
933/** SLADS: Second-Level Accessed/Dirty Support. */
934#define VTD_BF_ECAP_REG_SLADS_SHIFT 45
935#define VTD_BF_ECAP_REG_SLADS_MASK UINT64_C(0x0000200000000000)
936/** SLTS: Second-Level Translation Support. */
937#define VTD_BF_ECAP_REG_SLTS_SHIFT 46
938#define VTD_BF_ECAP_REG_SLTS_MASK UINT64_C(0x0000400000000000)
939/** FLTS: First-Level Translation Support. */
940#define VTD_BF_ECAP_REG_FLTS_SHIFT 47
941#define VTD_BF_ECAP_REG_FLTS_MASK UINT64_C(0x0000800000000000)
942/** SMPWCS: Scalable-Mode Page-Walk Coherency Support. */
943#define VTD_BF_ECAP_REG_SMPWCS_SHIFT 48
944#define VTD_BF_ECAP_REG_SMPWCS_MASK UINT64_C(0x0001000000000000)
945/** RPS: RID-PASID Support. */
946#define VTD_BF_ECAP_REG_RPS_SHIFT 49
947#define VTD_BF_ECAP_REG_RPS_MASK UINT64_C(0x0002000000000000)
948/** R: Reserved (bits 51:50). */
949#define VTD_BF_ECAP_REG_RSVD_51_50_SHIFT 50
950#define VTD_BF_ECAP_REG_RSVD_51_50_MASK UINT64_C(0x000c000000000000)
951/** ADMS: Abort DMA Mode Support. */
952#define VTD_BF_ECAP_REG_ADMS_SHIFT 52
953#define VTD_BF_ECAP_REG_ADMS_MASK UINT64_C(0x0010000000000000)
954/** RPRIVS: RID_PRIV Support. */
955#define VTD_BF_ECAP_REG_RPRIVS_SHIFT 53
956#define VTD_BF_ECAP_REG_RPRIVS_MASK UINT64_C(0x0020000000000000)
957/** R: Reserved (bits 63:54). */
958#define VTD_BF_ECAP_REG_RSVD_63_54_SHIFT 54
959#define VTD_BF_ECAP_REG_RSVD_63_54_MASK UINT64_C(0xffc0000000000000)
960RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_ECAP_REG_, UINT64_C(0), UINT64_MAX,
961 (C, QI, DT, IR, EIM, RSVD_5, PT, SC, IRO, RSVD_19_18, MHMV, RSVD_24, MTS, NEST, RSVD_27, RSVD_28,
962 PRS, ERS, SRS, RSVD_32, NWFS, EAFS, PSS, PASID, DIT, PDS, SMTS, VCS, SLADS, SLTS, FLTS, SMPWCS, RPS,
963 RSVD_51_50, ADMS, RPRIVS, RSVD_63_54));
964
965/** RW: Read/write mask. */
966#define VTD_ECAP_REG_RW_MASK UINT64_C(0)
967/** @} */
968
969
970/** @name Global Command Register (GCMD_REG).
971 * In accordance with the Intel spec.
972 * @{ */
973/** R: Reserved (bits 22:0). */
974#define VTD_BF_GCMD_REG_RSVD_22_0_SHIFT 0
975#define VTD_BF_GCMD_REG_RSVD_22_0_MASK UINT32_C(0x007fffff)
976/** CFI: Compatibility Format Interrupt. */
977#define VTD_BF_GCMD_REG_CFI_SHIFT 23
978#define VTD_BF_GCMD_REG_CFI_MASK UINT32_C(0x00800000)
979/** SIRTP: Set Interrupt Table Remap Pointer. */
980#define VTD_BF_GCMD_REG_SIRTP_SHIFT 24
981#define VTD_BF_GCMD_REG_SIRTP_MASK UINT32_C(0x01000000)
982/** IRE: Interrupt Remap Enable. */
983#define VTD_BF_GCMD_REG_IRE_SHIFT 25
984#define VTD_BF_GCMD_REG_IRE_MASK UINT32_C(0x02000000)
985/** QIE: Queued Invalidation Enable. */
986#define VTD_BF_GCMD_REG_QIE_SHIFT 26
987#define VTD_BF_GCMD_REG_QIE_MASK UINT32_C(0x04000000)
988/** WBF: Write Buffer Flush. */
989#define VTD_BF_GCMD_REG_WBF_SHIFT 27
990#define VTD_BF_GCMD_REG_WBF_MASK UINT32_C(0x08000000)
991/** EAFL: Enable Advance Fault Logging. */
992#define VTD_BF_GCMD_REG_EAFL_SHIFT 28
993#define VTD_BF_GCMD_REG_EAFL_MASK UINT32_C(0x10000000)
994/** SFL: Set Fault Log. */
995#define VTD_BF_GCMD_REG_SFL_SHIFT 29
996#define VTD_BF_GCMD_REG_SFL_MASK UINT32_C(0x20000000)
997/** SRTP: Set Root Table Pointer. */
998#define VTD_BF_GCMD_REG_SRTP_SHIFT 30
999#define VTD_BF_GCMD_REG_SRTP_MASK UINT32_C(0x40000000)
1000/** TE: Translation Enable. */
1001#define VTD_BF_GCMD_REG_TE_SHIFT 31
1002#define VTD_BF_GCMD_REG_TE_MASK UINT32_C(0x80000000)
1003RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_GCMD_REG_, UINT32_C(0), UINT32_MAX,
1004 (RSVD_22_0, CFI, SIRTP, IRE, QIE, WBF, EAFL, SFL, SRTP, TE));
1005
1006/** RW: Read/write mask. */
1007#define VTD_GCMD_REG_RW_MASK ( VTD_BF_GCMD_REG_TE_MASK | VTD_BF_GCMD_REG_SRTP_MASK \
1008 | VTD_BF_GCMD_REG_SFL_MASK | VTD_BF_GCMD_REG_EAFL_MASK \
1009 | VTD_BF_GCMD_REG_WBF_MASK | VTD_BF_GCMD_REG_QIE_MASK \
1010 | VTD_BF_GCMD_REG_IRE_MASK | VTD_BF_GCMD_REG_SIRTP_MASK \
1011 | VTD_BF_GCMD_REG_CFI_MASK)
1012/** @} */
1013
1014
1015/** @name Global Status Register (GSTS_REG).
1016 * In accordance with the Intel spec.
1017 * @{ */
1018/** R: Reserved (bits 22:0). */
1019#define VTD_BF_GSTS_REG_RSVD_22_0_SHIFT 0
1020#define VTD_BF_GSTS_REG_RSVD_22_0_MASK UINT32_C(0x007fffff)
1021/** CFIS: Compatibility Format Interrupt Status. */
1022#define VTD_BF_GSTS_REG_CFIS_SHIFT 23
1023#define VTD_BF_GSTS_REG_CFIS_MASK UINT32_C(0x00800000)
1024/** IRTPS: Interrupt Remapping Table Pointer Status. */
1025#define VTD_BF_GSTS_REG_IRTPS_SHIFT 24
1026#define VTD_BF_GSTS_REG_IRTPS_MASK UINT32_C(0x01000000)
1027/** IRES: Interrupt Remapping Enable Status. */
1028#define VTD_BF_GSTS_REG_IRES_SHIFT 25
1029#define VTD_BF_GSTS_REG_IRES_MASK UINT32_C(0x02000000)
1030/** QIES: Queued Invalidation Enable Status. */
1031#define VTD_BF_GSTS_REG_QIES_SHIFT 26
1032#define VTD_BF_GSTS_REG_QIES_MASK UINT32_C(0x04000000)
1033/** WBFS: Write Buffer Flush Status. */
1034#define VTD_BF_GSTS_REG_WBFS_SHIFT 27
1035#define VTD_BF_GSTS_REG_WBFS_MASK UINT32_C(0x08000000)
1036/** AFLS: Advanced Fault Logging Status. */
1037#define VTD_BF_GSTS_REG_AFLS_SHIFT 28
1038#define VTD_BF_GSTS_REG_AFLS_MASK UINT32_C(0x10000000)
1039/** FLS: Fault Log Status. */
1040#define VTD_BF_GSTS_REG_FLS_SHIFT 29
1041#define VTD_BF_GSTS_REG_FLS_MASK UINT32_C(0x20000000)
1042/** RTPS: Root Table Pointer Status. */
1043#define VTD_BF_GSTS_REG_RTPS_SHIFT 30
1044#define VTD_BF_GSTS_REG_RTPS_MASK UINT32_C(0x40000000)
1045/** TES: Translation Enable Status. */
1046#define VTD_BF_GSTS_REG_TES_SHIFT 31
1047#define VTD_BF_GSTS_REG_TES_MASK UINT32_C(0x80000000)
1048RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_GSTS_REG_, UINT32_C(0), UINT32_MAX,
1049 (RSVD_22_0, CFIS, IRTPS, IRES, QIES, WBFS, AFLS, FLS, RTPS, TES));
1050
1051/** RW: Read/write mask. */
1052#define VTD_GSTS_REG_RW_MASK UINT32_C(0)
1053/** @} */
1054
1055
1056/** @name Root Table Address Register (RTADDR_REG).
1057 * In accordance with the Intel spec.
1058 * @{ */
1059/** R: Reserved (bits 9:0). */
1060#define VTD_BF_RTADDR_REG_RSVD_9_0_SHIFT 0
1061#define VTD_BF_RTADDR_REG_RSVD_9_0_MASK UINT64_C(0x00000000000003ff)
1062/** TTM: Translation Table Mode. */
1063#define VTD_BF_RTADDR_REG_TTM_SHIFT 10
1064#define VTD_BF_RTADDR_REG_TTM_MASK UINT64_C(0x0000000000000c00)
1065/** RTA: Root Table Address. */
1066#define VTD_BF_RTADDR_REG_RTA_SHIFT 12
1067#define VTD_BF_RTADDR_REG_RTA_MASK UINT64_C(0xfffffffffffff000)
1068RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_RTADDR_REG_, UINT64_C(0), UINT64_MAX,
1069 (RSVD_9_0, TTM, RTA));
1070
1071/** RW: Read/write mask. */
1072#define VTD_RTADDR_REG_RW_MASK UINT64_C(0xfffffffffffffc00)
1073
1074/** RTADDR_REG.TTM: Legacy mode. */
1075#define VTD_TTM_LEGACY_MODE 0
1076/** RTADDR_REG.TTM: Scalable mode. */
1077#define VTD_TTM_SCALABLE_MODE 1
1078/** RTADDR_REG.TTM: Reserved. */
1079#define VTD_TTM_RSVD 2
1080/** RTADDR_REG.TTM: Abort DMA mode. */
1081#define VTD_TTM_ABORT_DMA_MODE 3
1082/** @} */
1083
1084
1085/** @name Context Command Register (CCMD_REG).
1086 * In accordance with the Intel spec.
1087 * @{ */
1088/** DID: Domain-ID. */
1089#define VTD_BF_CCMD_REG_DID_SHIFT 0
1090#define VTD_BF_CCMD_REG_DID_MASK UINT64_C(0x000000000000ffff)
1091/** SID: Source-ID. */
1092#define VTD_BF_CCMD_REG_SID_SHIFT 16
1093#define VTD_BF_CCMD_REG_SID_MASK UINT64_C(0x00000000ffff0000)
1094/** FM: Function Mask. */
1095#define VTD_BF_CCMD_REG_FM_SHIFT 32
1096#define VTD_BF_CCMD_REG_FM_MASK UINT64_C(0x0000000300000000)
1097/** R: Reserved (bits 58:34). */
1098#define VTD_BF_CCMD_REG_RSVD_58_34_SHIFT 34
1099#define VTD_BF_CCMD_REG_RSVD_58_34_MASK UINT64_C(0x07fffffc00000000)
1100/** CAIG: Context Actual Invalidation Granularity. */
1101#define VTD_BF_CCMD_REG_CAIG_SHIFT 59
1102#define VTD_BF_CCMD_REG_CAIG_MASK UINT64_C(0x1800000000000000)
1103/** CIRG: Context Invalidation Request Granularity. */
1104#define VTD_BF_CCMD_REG_CIRG_SHIFT 61
1105#define VTD_BF_CCMD_REG_CIRG_MASK UINT64_C(0x6000000000000000)
1106/** ICC: Invalidation Context Cache. */
1107#define VTD_BF_CCMD_REG_ICC_SHIFT 63
1108#define VTD_BF_CCMD_REG_ICC_MASK UINT64_C(0x8000000000000000)
1109RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_CCMD_REG_, UINT64_C(0), UINT64_MAX,
1110 (DID, SID, FM, RSVD_58_34, CAIG, CIRG, ICC));
1111
1112/** RW: Read/write mask. */
1113#define VTD_CCMD_REG_RW_MASK ( VTD_BF_CCMD_REG_DID_MASK | VTD_BF_CCMD_REG_SID_MASK \
1114 | VTD_BF_CCMD_REG_FM_MASK | VTD_BF_CCMD_REG_CIRG_MASK \
1115 | VTD_BF_CCMD_REG_ICC_MASK)
1116/** @} */
1117
1118
1119/** @name IOTLB Invalidation Register (IOTLB_REG).
1120 * In accordance with the Intel spec.
1121 * @{ */
1122/** R: Reserved (bits 31:0). */
1123#define VTD_BF_IOTLB_REG_RSVD_31_0_SHIFT 0
1124#define VTD_BF_IOTLB_REG_RSVD_31_0_MASK UINT64_C(0x00000000ffffffff)
1125/** DID: Domain-ID. */
1126#define VTD_BF_IOTLB_REG_DID_SHIFT 32
1127#define VTD_BF_IOTLB_REG_DID_MASK UINT64_C(0x0000ffff00000000)
1128/** DW: Draining Writes. */
1129#define VTD_BF_IOTLB_REG_DW_SHIFT 48
1130#define VTD_BF_IOTLB_REG_DW_MASK UINT64_C(0x0001000000000000)
1131/** DR: Draining Reads. */
1132#define VTD_BF_IOTLB_REG_DR_SHIFT 49
1133#define VTD_BF_IOTLB_REG_DR_MASK UINT64_C(0x0002000000000000)
1134/** R: Reserved (bits 56:50). */
1135#define VTD_BF_IOTLB_REG_RSVD_56_50_SHIFT 50
1136#define VTD_BF_IOTLB_REG_RSVD_56_50_MASK UINT64_C(0x01fc000000000000)
1137/** IAIG: IOTLB Actual Invalidation Granularity. */
1138#define VTD_BF_IOTLB_REG_IAIG_SHIFT 57
1139#define VTD_BF_IOTLB_REG_IAIG_MASK UINT64_C(0x0600000000000000)
1140/** R: Reserved (bit 59). */
1141#define VTD_BF_IOTLB_REG_RSVD_59_SHIFT 59
1142#define VTD_BF_IOTLB_REG_RSVD_59_MASK UINT64_C(0x0800000000000000)
1143/** IIRG: IOTLB Invalidation Request Granularity. */
1144#define VTD_BF_IOTLB_REG_IIRG_SHIFT 60
1145#define VTD_BF_IOTLB_REG_IIRG_MASK UINT64_C(0x3000000000000000)
1146/** R: Reserved (bit 62). */
1147#define VTD_BF_IOTLB_REG_RSVD_62_SHIFT 62
1148#define VTD_BF_IOTLB_REG_RSVD_62_MASK UINT64_C(0x4000000000000000)
1149/** IVT: Invalidate IOTLB. */
1150#define VTD_BF_IOTLB_REG_IVT_SHIFT 63
1151#define VTD_BF_IOTLB_REG_IVT_MASK UINT64_C(0x8000000000000000)
1152RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IOTLB_REG_, UINT64_C(0), UINT64_MAX,
1153 (RSVD_31_0, DID, DW, DR, RSVD_56_50, IAIG, RSVD_59, IIRG, RSVD_62, IVT));
1154
1155/** RW: Read/write mask. */
1156#define VTD_IOTLB_REG_RW_MASK ( VTD_BF_IOTLB_REG_DID_MASK | VTD_BF_IOTLB_REG_DW_MASK \
1157 | VTD_BF_IOTLB_REG_DR_MASK | VTD_BF_IOTLB_REG_IIRG_MASK \
1158 | VTD_BF_IOTLB_REG_IVT_MASK)
1159/** @} */
1160
1161
1162/** @name Invalidate Address Register (IVA_REG).
1163 * In accordance with the Intel spec.
1164 * @{ */
1165/** AM: Address Mask. */
1166#define VTD_BF_IVA_REG_AM_SHIFT 0
1167#define VTD_BF_IVA_REG_AM_MASK UINT64_C(0x000000000000003f)
1168/** IH: Invalidation Hint. */
1169#define VTD_BF_IVA_REG_IH_SHIFT 6
1170#define VTD_BF_IVA_REG_IH_MASK UINT64_C(0x0000000000000040)
1171/** R: Reserved (bits 11:7). */
1172#define VTD_BF_IVA_REG_RSVD_11_7_SHIFT 7
1173#define VTD_BF_IVA_REG_RSVD_11_7_MASK UINT64_C(0x0000000000000f80)
1174/** ADDR: Address. */
1175#define VTD_BF_IVA_REG_ADDR_SHIFT 12
1176#define VTD_BF_IVA_REG_ADDR_MASK UINT64_C(0xfffffffffffff000)
1177RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IVA_REG_, UINT64_C(0), UINT64_MAX,
1178 (AM, IH, RSVD_11_7, ADDR));
1179
1180/** RW: Read/write mask. */
1181#define VTD_IVA_REG_RW_MASK ( VTD_BF_IVA_REG_AM_MASK | VTD_BF_IVA_REG_IH_MASK \
1182 | VTD_BF_IVA_REG_ADDR_MASK)
1183/** @} */
1184
1185
1186/** @name Fault Status Register (FSTS_REG).
1187 * In accordance with the Intel spec.
1188 * @{ */
1189/** PFO: Primary Fault Overflow. */
1190#define VTD_BF_FSTS_REG_PFO_SHIFT 0
1191#define VTD_BF_FSTS_REG_PFO_MASK UINT32_C(0x00000001)
1192/** PPF: Primary Pending Fault. */
1193#define VTD_BF_FSTS_REG_PPF_SHIFT 1
1194#define VTD_BF_FSTS_REG_PPF_MASK UINT32_C(0x00000002)
1195/** AFO: Advanced Fault Overflow. */
1196#define VTD_BF_FSTS_REG_AFO_SHIFT 2
1197#define VTD_BF_FSTS_REG_AFO_MASK UINT32_C(0x00000004)
1198/** APF: Advanced Pending Fault. */
1199#define VTD_BF_FSTS_REG_APF_SHIFT 3
1200#define VTD_BF_FSTS_REG_APF_MASK UINT32_C(0x00000008)
1201/** IQE: Invalidation Queue Error. */
1202#define VTD_BF_FSTS_REG_IQE_SHIFT 4
1203#define VTD_BF_FSTS_REG_IQE_MASK UINT32_C(0x00000010)
1204/** ICE: Invalidation Completion Error. */
1205#define VTD_BF_FSTS_REG_ICE_SHIFT 5
1206#define VTD_BF_FSTS_REG_ICE_MASK UINT32_C(0x00000020)
1207/** ITE: Invalidation Timeout Error. */
1208#define VTD_BF_FSTS_REG_ITE_SHIFT 6
1209#define VTD_BF_FSTS_REG_ITE_MASK UINT32_C(0x00000040)
1210/** DEP: Deprecated MBZ. Reserved (bit 7). */
1211#define VTD_BF_FSTS_REG_RSVD_7_SHIFT 7
1212#define VTD_BF_FSTS_REG_RSVD_7_MASK UINT32_C(0x00000080)
1213/** FRI: Fault Record Index. */
1214#define VTD_BF_FSTS_REG_FRI_SHIFT 8
1215#define VTD_BF_FSTS_REG_FRI_MASK UINT32_C(0x0000ff00)
1216/** R: Reserved (bits 31:16). */
1217#define VTD_BF_FSTS_REG_RSVD_31_16_SHIFT 16
1218#define VTD_BF_FSTS_REG_RSVD_31_16_MASK UINT32_C(0xffff0000)
1219RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_FSTS_REG_, UINT32_C(0), UINT32_MAX,
1220 (PFO, PPF, AFO, APF, IQE, ICE, ITE, RSVD_7, FRI, RSVD_31_16));
1221
1222/** RW: Read/write mask. */
1223#define VTD_FSTS_REG_RW_MASK ( VTD_BF_FSTS_REG_PFO_MASK | VTD_BF_FSTS_REG_AFO_MASK \
1224 | VTD_BF_FSTS_REG_APF_MASK | VTD_BF_FSTS_REG_IQE_MASK \
1225 | VTD_BF_FSTS_REG_ICE_MASK | VTD_BF_FSTS_REG_ITE_MASK)
1226/** RW1C: Read-only-status, Write-1-to-clear status mask. */
1227#define VTD_FSTS_REG_RW1C_MASK ( VTD_BF_FSTS_REG_PFO_MASK | VTD_BF_FSTS_REG_AFO_MASK \
1228 | VTD_BF_FSTS_REG_APF_MASK | VTD_BF_FSTS_REG_IQE_MASK \
1229 | VTD_BF_FSTS_REG_ICE_MASK | VTD_BF_FSTS_REG_ITE_MASK)
1230/** @} */
1231
1232
1233/** @name Fault Event Control Register (FECTL_REG).
1234 * In accordance with the Intel spec.
1235 * @{ */
1236/** R: Reserved (bits 29:0). */
1237#define VTD_BF_FECTL_REG_RSVD_29_0_SHIFT 0
1238#define VTD_BF_FECTL_REG_RSVD_29_0_MASK UINT32_C(0x3fffffff)
1239/** IP: Interrupt Pending. */
1240#define VTD_BF_FECTL_REG_IP_SHIFT 30
1241#define VTD_BF_FECTL_REG_IP_MASK UINT32_C(0x40000000)
1242/** IM: Interrupt Mask. */
1243#define VTD_BF_FECTL_REG_IM_SHIFT 31
1244#define VTD_BF_FECTL_REG_IM_MASK UINT32_C(0x80000000)
1245RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_FECTL_REG_, UINT32_C(0), UINT32_MAX,
1246 (RSVD_29_0, IP, IM));
1247
1248/** RW: Read/write mask. */
1249#define VTD_FECTL_REG_RW_MASK VTD_BF_FECTL_REG_IM_MASK
1250/** @} */
1251
1252
1253/** @name Fault Event Data Register (FEDATA_REG).
1254 * In accordance with the Intel spec.
1255 * @{ */
1256/** IMD: Interrupt Message Data. */
1257#define VTD_BF_FEDATA_REG_IMD_SHIFT 0
1258#define VTD_BF_FEDATA_REG_IMD_MASK UINT32_C(0x0000ffff)
1259/** R: Reserved (bits 31:16). VT-d specs. prior to 2021 had EIMD here. */
1260#define VTD_BF_FEDATA_REG_RSVD_31_16_SHIFT 16
1261#define VTD_BF_FEDATA_REG_RSVD_31_16_MASK UINT32_C(0xffff0000)
1262RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_FEDATA_REG_, UINT32_C(0), UINT32_MAX,
1263 (IMD, RSVD_31_16));
1264
1265/** RW: Read/write mask, see 5.1.6 "Remapping Hardware Event Interrupt
1266 * Programming". */
1267#define VTD_FEDATA_REG_RW_MASK UINT32_C(0x000001ff)
1268/** @} */
1269
1270
1271/** @name Fault Event Address Register (FEADDR_REG).
1272 * In accordance with the Intel spec.
1273 * @{ */
1274/** R: Reserved (bits 1:0). */
1275#define VTD_BF_FEADDR_REG_RSVD_1_0_SHIFT 0
1276#define VTD_BF_FEADDR_REG_RSVD_1_0_MASK UINT32_C(0x00000003)
1277/** MA: Message Address. */
1278#define VTD_BF_FEADDR_REG_MA_SHIFT 2
1279#define VTD_BF_FEADDR_REG_MA_MASK UINT32_C(0xfffffffc)
1280RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_FEADDR_REG_, UINT32_C(0), UINT32_MAX,
1281 (RSVD_1_0, MA));
1282
1283/** RW: Read/write mask. */
1284#define VTD_FEADDR_REG_RW_MASK VTD_BF_FEADDR_REG_MA_MASK
1285/** @} */
1286
1287
1288/** @name Fault Event Upper Address Register (FEUADDR_REG).
1289 * In accordance with the Intel spec.
1290 * @{ */
1291/** MUA: Message Upper Address. */
1292#define VTD_BF_FEUADDR_REG_MA_SHIFT 0
1293#define VTD_BF_FEUADDR_REG_MA_MASK UINT32_C(0xffffffff)
1294
1295/** RW: Read/write mask. */
1296#define VTD_FEUADDR_REG_RW_MASK VTD_BF_FEUADDR_REG_MA_MASK
1297/** @} */
1298
1299
1300/** @name Fault Recording Register (FRCD_REG).
1301 * In accordance with the Intel spec.
1302 * @{ */
1303/** R: Reserved (bits 11:0). */
1304#define VTD_BF_0_FRCD_REG_RSVD_11_0_SHIFT 0
1305#define VTD_BF_0_FRCD_REG_RSVD_11_0_MASK UINT64_C(0x0000000000000fff)
1306/** FI: Fault Info. */
1307#define VTD_BF_0_FRCD_REG_FI_SHIFT 12
1308#define VTD_BF_0_FRCD_REG_FI_MASK UINT64_C(0xfffffffffffff000)
1309RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_FRCD_REG_, UINT64_C(0), UINT64_MAX,
1310 (RSVD_11_0, FI));
1311
1312/** SID: Source Identifier. */
1313#define VTD_BF_1_FRCD_REG_SID_SHIFT 0
1314#define VTD_BF_1_FRCD_REG_SID_MASK UINT64_C(0x000000000000ffff)
1315/** R: Reserved (bits 27:16). */
1316#define VTD_BF_1_FRCD_REG_RSVD_27_16_SHIFT 16
1317#define VTD_BF_1_FRCD_REG_RSVD_27_16_MASK UINT64_C(0x000000000fff0000)
1318/** T2: Type bit 2. */
1319#define VTD_BF_1_FRCD_REG_T2_SHIFT 28
1320#define VTD_BF_1_FRCD_REG_T2_MASK UINT64_C(0x0000000010000000)
1321/** PRIV: Privilege Mode. */
1322#define VTD_BF_1_FRCD_REG_PRIV_SHIFT 29
1323#define VTD_BF_1_FRCD_REG_PRIV_MASK UINT64_C(0x0000000020000000)
1324/** EXE: Execute Permission Requested. */
1325#define VTD_BF_1_FRCD_REG_EXE_SHIFT 30
1326#define VTD_BF_1_FRCD_REG_EXE_MASK UINT64_C(0x0000000040000000)
1327/** PP: PASID Present. */
1328#define VTD_BF_1_FRCD_REG_PP_SHIFT 31
1329#define VTD_BF_1_FRCD_REG_PP_MASK UINT64_C(0x0000000080000000)
1330/** FR: Fault Reason. */
1331#define VTD_BF_1_FRCD_REG_FR_SHIFT 32
1332#define VTD_BF_1_FRCD_REG_FR_MASK UINT64_C(0x000000ff00000000)
1333/** PV: PASID Value. */
1334#define VTD_BF_1_FRCD_REG_PV_SHIFT 40
1335#define VTD_BF_1_FRCD_REG_PV_MASK UINT64_C(0x0fffff0000000000)
1336/** AT: Address Type. */
1337#define VTD_BF_1_FRCD_REG_AT_SHIFT 60
1338#define VTD_BF_1_FRCD_REG_AT_MASK UINT64_C(0x3000000000000000)
1339/** T1: Type bit 1. */
1340#define VTD_BF_1_FRCD_REG_T1_SHIFT 62
1341#define VTD_BF_1_FRCD_REG_T1_MASK UINT64_C(0x4000000000000000)
1342/** F: Fault. */
1343#define VTD_BF_1_FRCD_REG_F_SHIFT 63
1344#define VTD_BF_1_FRCD_REG_F_MASK UINT64_C(0x8000000000000000)
1345RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_FRCD_REG_, UINT64_C(0), UINT64_MAX,
1346 (SID, RSVD_27_16, T2, PRIV, EXE, PP, FR, PV, AT, T1, F));
1347
1348/** RW: Read/write mask. */
1349#define VTD_FRCD_REG_LO_RW_MASK UINT64_C(0)
1350#define VTD_FRCD_REG_HI_RW_MASK VTD_BF_1_FRCD_REG_F_MASK
1351/** RW1C: Read-only-status, Write-1-to-clear status mask. */
1352#define VTD_FRCD_REG_LO_RW1C_MASK UINT64_C(0)
1353#define VTD_FRCD_REG_HI_RW1C_MASK VTD_BF_1_FRCD_REG_F_MASK
1354/** @} */
1355
1356
1357/**
1358 * VT-d faulted address translation request types (FRCD_REG::T2).
1359 * In accordance with the Intel spec.
1360 */
1361typedef enum VTDREQTYPE
1362{
1363 VTDREQTYPE_WRITE = 0, /**< Memory access write request. */
1364 VTDREQTYPE_PAGE, /**< Page translation request. */
1365 VTDREQTYPE_READ, /**< Memory access read request. */
1366 VTDREQTYPE_ATOMIC_OP /**< Memory access atomic operation. */
1367} VTDREQTYPE;
1368
1369
1370/** @name VT-d faulted request attributes (FRCD_REG::EXE, FRCD_REG::PRIV).
1371 * In accordance with the Intel spec.
1372 * @{
1373 */
1374/** Supervisory privilege was requested. */
1375#define VTD_REQ_ATTR_PRIV RT_BIT(0)
1376/** Execute permission was requested. */
1377#define VTD_REQ_ATTR_EXE RT_BIT(1)
1378/** @} */
1379
1380
1381/** @name Advanced Fault Log Register (AFLOG_REG).
1382 * In accordance with the Intel spec.
1383 * @{ */
1384/** R: Reserved (bits 8:0). */
1385#define VTD_BF_0_AFLOG_REG_RSVD_8_0_SHIFT 0
1386#define VTD_BF_0_AFLOG_REG_RSVD_8_0_MASK UINT64_C(0x00000000000001ff)
1387/** FLS: Fault Log Size. */
1388#define VTD_BF_0_AFLOG_REG_FLS_SHIFT 9
1389#define VTD_BF_0_AFLOG_REG_FLS_MASK UINT64_C(0x0000000000000e00)
1390/** FLA: Fault Log Address. */
1391#define VTD_BF_0_AFLOG_REG_FLA_SHIFT 12
1392#define VTD_BF_0_AFLOG_REG_FLA_MASK UINT64_C(0xfffffffffffff000)
1393RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_AFLOG_REG_, UINT64_C(0), UINT64_MAX,
1394 (RSVD_8_0, FLS, FLA));
1395
1396/** RW: Read/write mask. */
1397#define VTD_AFLOG_REG_RW_MASK (VTD_BF_0_AFLOG_REG_FLS_MASK | VTD_BF_0_AFLOG_REG_FLA_MASK)
1398/** @} */
1399
1400
1401/** @name Protected Memory Enable Register (PMEN_REG).
1402 * In accordance with the Intel spec.
1403 * @{ */
1404/** PRS: Protected Region Status. */
1405#define VTD_BF_PMEN_REG_PRS_SHIFT 0
1406#define VTD_BF_PMEN_REG_PRS_MASK UINT32_C(0x00000001)
1407/** R: Reserved (bits 30:1). */
1408#define VTD_BF_PMEN_REG_RSVD_30_1_SHIFT 1
1409#define VTD_BF_PMEN_REG_RSVD_30_1_MASK UINT32_C(0x7ffffffe)
1410/** EPM: Enable Protected Memory. */
1411#define VTD_BF_PMEN_REG_EPM_SHIFT 31
1412#define VTD_BF_PMEN_REG_EPM_MASK UINT32_C(0x80000000)
1413RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_PMEN_REG_, UINT32_C(0), UINT32_MAX,
1414 (PRS, RSVD_30_1, EPM));
1415
1416/** RW: Read/write mask. */
1417#define VTD_PMEN_REG_RW_MASK VTD_BF_PMEN_REG_EPM_MASK
1418/** @} */
1419
1420
1421/** @name Invalidation Queue Head Register (IQH_REG).
1422 * In accordance with the Intel spec.
1423 * @{ */
1424/** R: Reserved (bits 3:0). */
1425#define VTD_BF_IQH_REG_RSVD_3_0_SHIFT 0
1426#define VTD_BF_IQH_REG_RSVD_3_0_MASK UINT64_C(0x000000000000000f)
1427/** QH: Queue Head. */
1428#define VTD_BF_IQH_REG_QH_SHIFT 4
1429#define VTD_BF_IQH_REG_QH_MASK UINT64_C(0x000000000007fff0)
1430/** R: Reserved (bits 63:19). */
1431#define VTD_BF_IQH_REG_RSVD_63_19_SHIFT 19
1432#define VTD_BF_IQH_REG_RSVD_63_19_MASK UINT64_C(0xfffffffffff80000)
1433RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IQH_REG_, UINT64_C(0), UINT64_MAX,
1434 (RSVD_3_0, QH, RSVD_63_19));
1435
1436/** RW: Read/write mask. */
1437#define VTD_IQH_REG_RW_MASK UINT64_C(0x0)
1438/** @} */
1439
1440
1441/** @name Invalidation Queue Tail Register (IQT_REG).
1442 * In accordance with the Intel spec.
1443 * @{ */
1444/** R: Reserved (bits 3:0). */
1445#define VTD_BF_IQT_REG_RSVD_3_0_SHIFT 0
1446#define VTD_BF_IQT_REG_RSVD_3_0_MASK UINT64_C(0x000000000000000f)
1447/** QH: Queue Tail. */
1448#define VTD_BF_IQT_REG_QT_SHIFT 4
1449#define VTD_BF_IQT_REG_QT_MASK UINT64_C(0x000000000007fff0)
1450/** R: Reserved (bits 63:19). */
1451#define VTD_BF_IQT_REG_RSVD_63_19_SHIFT 19
1452#define VTD_BF_IQT_REG_RSVD_63_19_MASK UINT64_C(0xfffffffffff80000)
1453RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IQT_REG_, UINT64_C(0), UINT64_MAX,
1454 (RSVD_3_0, QT, RSVD_63_19));
1455
1456/** RW: Read/write mask. */
1457#define VTD_IQT_REG_RW_MASK VTD_BF_IQT_REG_QT_MASK
1458/** @} */
1459
1460
1461/** @name Invalidation Queue Address Register (IQA_REG).
1462 * In accordance with the Intel spec.
1463 * @{ */
1464/** QS: Queue Size. */
1465#define VTD_BF_IQA_REG_QS_SHIFT 0
1466#define VTD_BF_IQA_REG_QS_MASK UINT64_C(0x0000000000000007)
1467/** R: Reserved (bits 10:3). */
1468#define VTD_BF_IQA_REG_RSVD_10_3_SHIFT 3
1469#define VTD_BF_IQA_REG_RSVD_10_3_MASK UINT64_C(0x00000000000007f8)
1470/** DW: Descriptor Width. */
1471#define VTD_BF_IQA_REG_DW_SHIFT 11
1472#define VTD_BF_IQA_REG_DW_MASK UINT64_C(0x0000000000000800)
1473/** IQA: Invalidation Queue Base Address. */
1474#define VTD_BF_IQA_REG_IQA_SHIFT 12
1475#define VTD_BF_IQA_REG_IQA_MASK UINT64_C(0xfffffffffffff000)
1476RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IQA_REG_, UINT64_C(0), UINT64_MAX,
1477 (QS, RSVD_10_3, DW, IQA));
1478
1479/** RW: Read/write mask. */
1480#define VTD_IQA_REG_RW_MASK ( VTD_BF_IQA_REG_QS_MASK | VTD_BF_IQA_REG_DW_MASK \
1481 | VTD_BF_IQA_REG_IQA_MASK)
1482/** DW: 128-bit descriptor. */
1483#define VTD_IQA_REG_DW_128_BIT 0
1484/** DW: 256-bit descriptor. */
1485#define VTD_IQA_REG_DW_256_BIT 1
1486/** @} */
1487
1488
1489/** @name Invalidation Completion Status Register (ICS_REG).
1490 * In accordance with the Intel spec.
1491 * @{ */
1492/** IWC: Invalidation Wait Descriptor Complete. */
1493#define VTD_BF_ICS_REG_IWC_SHIFT 0
1494#define VTD_BF_ICS_REG_IWC_MASK UINT32_C(0x00000001)
1495/** R: Reserved (bits 31:1). */
1496#define VTD_BF_ICS_REG_RSVD_31_1_SHIFT 1
1497#define VTD_BF_ICS_REG_RSVD_31_1_MASK UINT32_C(0xfffffffe)
1498RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_ICS_REG_, UINT32_C(0), UINT32_MAX,
1499 (IWC, RSVD_31_1));
1500
1501/** RW: Read/write mask. */
1502#define VTD_ICS_REG_RW_MASK VTD_BF_ICS_REG_IWC_MASK
1503/** RW1C: Read-only-status, Write-1-to-clear status mask. */
1504#define VTD_ICS_REG_RW1C_MASK VTD_BF_ICS_REG_IWC_MASK
1505/** @} */
1506
1507
1508/** @name Invalidation Event Control Register (IECTL_REG).
1509 * In accordance with the Intel spec.
1510 * @{ */
1511/** R: Reserved (bits 29:0). */
1512#define VTD_BF_IECTL_REG_RSVD_29_0_SHIFT 0
1513#define VTD_BF_IECTL_REG_RSVD_29_0_MASK UINT32_C(0x3fffffff)
1514/** IP: Interrupt Pending. */
1515#define VTD_BF_IECTL_REG_IP_SHIFT 30
1516#define VTD_BF_IECTL_REG_IP_MASK UINT32_C(0x40000000)
1517/** IM: Interrupt Mask. */
1518#define VTD_BF_IECTL_REG_IM_SHIFT 31
1519#define VTD_BF_IECTL_REG_IM_MASK UINT32_C(0x80000000)
1520RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IECTL_REG_, UINT32_C(0), UINT32_MAX,
1521 (RSVD_29_0, IP, IM));
1522
1523/** RW: Read/write mask. */
1524#define VTD_IECTL_REG_RW_MASK VTD_BF_IECTL_REG_IM_MASK
1525/** @} */
1526
1527
1528/** @name Invalidation Event Data Register (IEDATA_REG).
1529 * In accordance with the Intel spec.
1530 * @{ */
1531/** IMD: Interrupt Message Data. */
1532#define VTD_BF_IEDATA_REG_IMD_SHIFT 0
1533#define VTD_BF_IEDATA_REG_IMD_MASK UINT32_C(0x0000ffff)
1534/** R: Reserved (bits 31:16). VT-d specs. prior to 2021 had EIMD here. */
1535#define VTD_BF_IEDATA_REG_RSVD_31_16_SHIFT 16
1536#define VTD_BF_IEDATA_REG_RSVD_31_16_MASK UINT32_C(0xffff0000)
1537RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IEDATA_REG_, UINT32_C(0), UINT32_MAX,
1538 (IMD, RSVD_31_16));
1539
1540/** RW: Read/write mask, see 5.1.6 "Remapping Hardware Event Interrupt
1541 * Programming". */
1542#define VTD_IEDATA_REG_RW_MASK UINT32_C(0x000001ff)
1543/** @} */
1544
1545
1546/** @name Invalidation Event Address Register (IEADDR_REG).
1547 * In accordance with the Intel spec.
1548 * @{ */
1549/** R: Reserved (bits 1:0). */
1550#define VTD_BF_IEADDR_REG_RSVD_1_0_SHIFT 0
1551#define VTD_BF_IEADDR_REG_RSVD_1_0_MASK UINT32_C(0x00000003)
1552/** MA: Message Address. */
1553#define VTD_BF_IEADDR_REG_MA_SHIFT 2
1554#define VTD_BF_IEADDR_REG_MA_MASK UINT32_C(0xfffffffc)
1555RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IEADDR_REG_, UINT32_C(0), UINT32_MAX,
1556 (RSVD_1_0, MA));
1557
1558/** RW: Read/write mask. */
1559#define VTD_IEADDR_REG_RW_MASK VTD_BF_IEADDR_REG_MA_MASK
1560/** @} */
1561
1562
1563/** @name Invalidation Event Upper Address Register (IEUADDR_REG).
1564 * @{ */
1565/** MUA: Message Upper Address. */
1566#define VTD_BF_IEUADDR_REG_MUA_SHIFT 0
1567#define VTD_BF_IEUADDR_REG_MUA_MASK UINT32_C(0xffffffff)
1568
1569/** RW: Read/write mask. */
1570#define VTD_IEUADDR_REG_RW_MASK VTD_BF_IEUADDR_REG_MUA_MASK
1571/** @} */
1572
1573
1574/** @name Invalidation Queue Error Record Register (IQERCD_REG).
1575 * In accordance with the Intel spec.
1576 * @{ */
1577/** IQEI: Invalidation Queue Error Info. */
1578#define VTD_BF_IQERCD_REG_IQEI_SHIFT 0
1579#define VTD_BF_IQERCD_REG_IQEI_MASK UINT64_C(0x000000000000000f)
1580/** R: Reserved (bits 31:4). */
1581#define VTD_BF_IQERCD_REG_RSVD_31_4_SHIFT 4
1582#define VTD_BF_IQERCD_REG_RSVD_31_4_MASK UINT64_C(0x00000000fffffff0)
1583/** ITESID: Invalidation Timeout Error Source Identifier. */
1584#define VTD_BF_IQERCD_REG_ITESID_SHIFT 32
1585#define VTD_BF_IQERCD_REG_ITESID_MASK UINT64_C(0x0000ffff00000000)
1586/** ICESID: Invalidation Completion Error Source Identifier. */
1587#define VTD_BF_IQERCD_REG_ICESID_SHIFT 48
1588#define VTD_BF_IQERCD_REG_ICESID_MASK UINT64_C(0xffff000000000000)
1589RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IQERCD_REG_, UINT64_C(0), UINT64_MAX,
1590 (IQEI, RSVD_31_4, ITESID, ICESID));
1591
1592/** RW: Read/write mask. */
1593#define VTD_IQERCD_REG_RW_MASK UINT64_C(0)
1594
1595/** Invalidation Queue Error Information. */
1596typedef enum VTDIQEI
1597{
1598 VTDIQEI_INFO_NOT_AVAILABLE,
1599 VTDIQEI_INVALID_TAIL_PTR,
1600 VTDIQEI_FETCH_DESCRIPTOR_ERR,
1601 VTDIQEI_INVALID_DESCRIPTOR_TYPE,
1602 VTDIQEI_RSVD_FIELD_VIOLATION,
1603 VTDIQEI_INVALID_DESCRIPTOR_WIDTH,
1604 VTDIQEI_QUEUE_TAIL_MISALIGNED,
1605 VTDIQEI_INVALID_TTM
1606} VTDIQEI;
1607/** @} */
1608
1609
1610/** @name Interrupt Remapping Table Address Register (IRTA_REG).
1611 * In accordance with the Intel spec.
1612 * @{ */
1613/** S: Size. */
1614#define VTD_BF_IRTA_REG_S_SHIFT 0
1615#define VTD_BF_IRTA_REG_S_MASK UINT64_C(0x000000000000000f)
1616/** R: Reserved (bits 10:4). */
1617#define VTD_BF_IRTA_REG_RSVD_10_4_SHIFT 4
1618#define VTD_BF_IRTA_REG_RSVD_10_4_MASK UINT64_C(0x00000000000007f0)
1619/** EIME: Extended Interrupt Mode Enable. */
1620#define VTD_BF_IRTA_REG_EIME_SHIFT 11
1621#define VTD_BF_IRTA_REG_EIME_MASK UINT64_C(0x0000000000000800)
1622/** IRTA: Interrupt Remapping Table Address. */
1623#define VTD_BF_IRTA_REG_IRTA_SHIFT 12
1624#define VTD_BF_IRTA_REG_IRTA_MASK UINT64_C(0xfffffffffffff000)
1625RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IRTA_REG_, UINT64_C(0), UINT64_MAX,
1626 (S, RSVD_10_4, EIME, IRTA));
1627
1628/** RW: Read/write mask. */
1629#define VTD_IRTA_REG_RW_MASK ( VTD_BF_IRTA_REG_S_MASK | VTD_BF_IRTA_REG_EIME_MASK \
1630 | VTD_BF_IRTA_REG_IRTA_MASK)
1631/** IRTA_REG: Get number of interrupt entries. */
1632#define VTD_IRTA_REG_GET_ENTRY_COUNT(a) (UINT32_C(1) << (1 + ((a) & VTD_BF_IRTA_REG_S_MASK)))
1633/** @} */
1634
1635
1636/** @name Page Request Queue Head Register (PQH_REG).
1637 * In accordance with the Intel spec.
1638 * @{ */
1639/** R: Reserved (bits 4:0). */
1640#define VTD_BF_PQH_REG_RSVD_4_0_SHIFT 0
1641#define VTD_BF_PQH_REG_RSVD_4_0_MASK UINT64_C(0x000000000000001f)
1642/** PQH: Page Queue Head. */
1643#define VTD_BF_PQH_REG_PQH_SHIFT 5
1644#define VTD_BF_PQH_REG_PQH_MASK UINT64_C(0x000000000007ffe0)
1645/** R: Reserved (bits 63:19). */
1646#define VTD_BF_PQH_REG_RSVD_63_19_SHIFT 19
1647#define VTD_BF_PQH_REG_RSVD_63_19_MASK UINT64_C(0xfffffffffff80000)
1648RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_PQH_REG_, UINT64_C(0), UINT64_MAX,
1649 (RSVD_4_0, PQH, RSVD_63_19));
1650
1651/** RW: Read/write mask. */
1652#define VTD_PQH_REG_RW_MASK VTD_BF_PQH_REG_PQH_MASK
1653/** @} */
1654
1655
1656/** @name Page Request Queue Tail Register (PQT_REG).
1657 * In accordance with the Intel spec.
1658 * @{ */
1659/** R: Reserved (bits 4:0). */
1660#define VTD_BF_PQT_REG_RSVD_4_0_SHIFT 0
1661#define VTD_BF_PQT_REG_RSVD_4_0_MASK UINT64_C(0x000000000000001f)
1662/** PQT: Page Queue Tail. */
1663#define VTD_BF_PQT_REG_PQT_SHIFT 5
1664#define VTD_BF_PQT_REG_PQT_MASK UINT64_C(0x000000000007ffe0)
1665/** R: Reserved (bits 63:19). */
1666#define VTD_BF_PQT_REG_RSVD_63_19_SHIFT 19
1667#define VTD_BF_PQT_REG_RSVD_63_19_MASK UINT64_C(0xfffffffffff80000)
1668RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_PQT_REG_, UINT64_C(0), UINT64_MAX,
1669 (RSVD_4_0, PQT, RSVD_63_19));
1670
1671/** RW: Read/write mask. */
1672#define VTD_PQT_REG_RW_MASK VTD_BF_PQT_REG_PQT_MASK
1673/** @} */
1674
1675
1676/** @name Page Request Queue Address Register (PQA_REG).
1677 * In accordance with the Intel spec.
1678 * @{ */
1679/** PQS: Page Queue Size. */
1680#define VTD_BF_PQA_REG_PQS_SHIFT 0
1681#define VTD_BF_PQA_REG_PQS_MASK UINT64_C(0x0000000000000007)
1682/** R: Reserved bits (11:3). */
1683#define VTD_BF_PQA_REG_RSVD_11_3_SHIFT 3
1684#define VTD_BF_PQA_REG_RSVD_11_3_MASK UINT64_C(0x0000000000000ff8)
1685/** PQA: Page Request Queue Base Address. */
1686#define VTD_BF_PQA_REG_PQA_SHIFT 12
1687#define VTD_BF_PQA_REG_PQA_MASK UINT64_C(0xfffffffffffff000)
1688RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_PQA_REG_, UINT64_C(0), UINT64_MAX,
1689 (PQS, RSVD_11_3, PQA));
1690
1691/** RW: Read/write mask. */
1692#define VTD_PQA_REG_RW_MASK (VTD_BF_PQA_REG_PQS_MASK | VTD_BF_PQA_REG_PQA_MASK)
1693/** @} */
1694
1695
1696/** @name Page Request Status Register (PRS_REG).
1697 * In accordance with the Intel spec.
1698 * @{ */
1699/** PPR: Pending Page Request. */
1700#define VTD_BF_PRS_REG_PPR_SHIFT 0
1701#define VTD_BF_PRS_REG_PPR_MASK UINT64_C(0x00000001)
1702/** PRO: Page Request Overflow. */
1703#define VTD_BF_PRS_REG_PRO_SHIFT 1
1704#define VTD_BF_PRS_REG_PRO_MASK UINT64_C(0x00000002)
1705/** R: Reserved (bits 31:2). */
1706#define VTD_BF_PRS_REG_RSVD_31_2_SHIFT 2
1707#define VTD_BF_PRS_REG_RSVD_31_2_MASK UINT64_C(0xfffffffc)
1708RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_PRS_REG_, UINT32_C(0), UINT32_MAX,
1709 (PPR, PRO, RSVD_31_2));
1710
1711/** RW: Read/write mask. */
1712#define VTD_PRS_REG_RW_MASK (VTD_BF_PRS_REG_PPR_MASK | VTD_BF_PRS_REG_PRO_MASK)
1713/** RW1C: Read-only-status, Write-1-to-clear status mask. */
1714#define VTD_PRS_REG_RW1C_MASK (VTD_BF_PRS_REG_PPR_MASK | VTD_BF_PRS_REG_PRO_MASK)
1715/** @} */
1716
1717
1718/** @name Page Request Event Control Register (PECTL_REG).
1719 * In accordance with the Intel spec.
1720 * @{ */
1721/** R: Reserved (bits 29:0). */
1722#define VTD_BF_PECTL_REG_RSVD_29_0_SHIFT 0
1723#define VTD_BF_PECTL_REG_RSVD_29_0_MASK UINT32_C(0x3fffffff)
1724/** IP: Interrupt Pending. */
1725#define VTD_BF_PECTL_REG_IP_SHIFT 30
1726#define VTD_BF_PECTL_REG_IP_MASK UINT32_C(0x40000000)
1727/** IM: Interrupt Mask. */
1728#define VTD_BF_PECTL_REG_IM_SHIFT 31
1729#define VTD_BF_PECTL_REG_IM_MASK UINT32_C(0x80000000)
1730RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_PECTL_REG_, UINT32_C(0), UINT32_MAX,
1731 (RSVD_29_0, IP, IM));
1732
1733/** RW: Read/write mask. */
1734#define VTD_PECTL_REG_RW_MASK VTD_BF_PECTL_REG_IM_MASK
1735/** @} */
1736
1737
1738/** @name Page Request Event Data Register (PEDATA_REG).
1739 * In accordance with the Intel spec.
1740 * @{ */
1741/** IMD: Interrupt Message Data. */
1742#define VTD_BF_PEDATA_REG_IMD_SHIFT 0
1743#define VTD_BF_PEDATA_REG_IMD_MASK UINT32_C(0x0000ffff)
1744/** R: Reserved (bits 31:16). VT-d specs. prior to 2021 had EIMD here. */
1745#define VTD_BF_PEDATA_REG_RSVD_31_16_SHIFT 16
1746#define VTD_BF_PEDATA_REG_RSVD_31_16_MASK UINT32_C(0xffff0000)
1747RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_PEDATA_REG_, UINT32_C(0), UINT32_MAX,
1748 (IMD, RSVD_31_16));
1749
1750/** RW: Read/write mask, see 5.1.6 "Remapping Hardware Event Interrupt
1751 * Programming". */
1752#define VTD_PEDATA_REG_RW_MASK UINT32_C(0x000001ff)
1753/** @} */
1754
1755
1756/** @name Page Request Event Address Register (PEADDR_REG).
1757 * In accordance with the Intel spec.
1758 * @{ */
1759/** R: Reserved (bits 1:0). */
1760#define VTD_BF_PEADDR_REG_RSVD_1_0_SHIFT 0
1761#define VTD_BF_PEADDR_REG_RSVD_1_0_MASK UINT32_C(0x00000003)
1762/** MA: Message Address. */
1763#define VTD_BF_PEADDR_REG_MA_SHIFT 2
1764#define VTD_BF_PEADDR_REG_MA_MASK UINT32_C(0xfffffffc)
1765RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_PEADDR_REG_, UINT32_C(0), UINT32_MAX,
1766 (RSVD_1_0, MA));
1767
1768/** RW: Read/write mask. */
1769#define VTD_PEADDR_REG_RW_MASK VTD_BF_PEADDR_REG_MA_MASK
1770/** @} */
1771
1772
1773
1774/** @name Page Request Event Upper Address Register (PEUADDR_REG).
1775 * In accordance with the Intel spec.
1776 * @{ */
1777/** MA: Message Address. */
1778#define VTD_BF_PEUADDR_REG_MUA_SHIFT 0
1779#define VTD_BF_PEUADDR_REG_MUA_MASK UINT32_C(0xffffffff)
1780
1781/** RW: Read/write mask. */
1782#define VTD_PEUADDR_REG_RW_MASK VTD_BF_PEUADDR_REG_MUA_MASK
1783/** @} */
1784
1785
1786/** @name MTRR Capability Register (MTRRCAP_REG).
1787 * In accordance with the Intel spec.
1788 * @{ */
1789/** VCNT: Variable MTRR Count. */
1790#define VTD_BF_MTRRCAP_REG_VCNT_SHIFT 0
1791#define VTD_BF_MTRRCAP_REG_VCNT_MASK UINT64_C(0x00000000000000ff)
1792/** FIX: Fixed range MTRRs Supported. */
1793#define VTD_BF_MTRRCAP_REG_FIX_SHIFT 8
1794#define VTD_BF_MTRRCAP_REG_FIX_MASK UINT64_C(0x0000000000000100)
1795/** R: Reserved (bit 9). */
1796#define VTD_BF_MTRRCAP_REG_RSVD_9_SHIFT 9
1797#define VTD_BF_MTRRCAP_REG_RSVD_9_MASK UINT64_C(0x0000000000000200)
1798/** WC: Write Combining. */
1799#define VTD_BF_MTRRCAP_REG_WC_SHIFT 10
1800#define VTD_BF_MTRRCAP_REG_WC_MASK UINT64_C(0x0000000000000400)
1801/** R: Reserved (bits 63:11). */
1802#define VTD_BF_MTRRCAP_REG_RSVD_63_11_SHIFT 11
1803#define VTD_BF_MTRRCAP_REG_RSVD_63_11_MASK UINT64_C(0xfffffffffffff800)
1804RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_MTRRCAP_REG_, UINT64_C(0), UINT64_MAX,
1805 (VCNT, FIX, RSVD_9, WC, RSVD_63_11));
1806
1807/** RW: Read/write mask. */
1808#define VTD_MTRRCAP_REG_RW_MASK UINT64_C(0)
1809/** @} */
1810
1811
1812/** @name MTRR Default Type Register (MTRRDEF_REG).
1813 * In accordance with the Intel spec.
1814 * @{ */
1815/** TYPE: Default Memory Type. */
1816#define VTD_BF_MTRRDEF_REG_TYPE_SHIFT 0
1817#define VTD_BF_MTRRDEF_REG_TYPE_MASK UINT64_C(0x00000000000000ff)
1818/** R: Reserved (bits 9:8). */
1819#define VTD_BF_MTRRDEF_REG_RSVD_9_8_SHIFT 8
1820#define VTD_BF_MTRRDEF_REG_RSVD_9_8_MASK UINT64_C(0x0000000000000300)
1821/** FE: Fixed Range MTRR Enable. */
1822#define VTD_BF_MTRRDEF_REG_FE_SHIFT 10
1823#define VTD_BF_MTRRDEF_REG_FE_MASK UINT64_C(0x0000000000000400)
1824/** E: MTRR Enable. */
1825#define VTD_BF_MTRRDEF_REG_E_SHIFT 11
1826#define VTD_BF_MTRRDEF_REG_E_MASK UINT64_C(0x0000000000000800)
1827/** R: Reserved (bits 63:12). */
1828#define VTD_BF_MTRRDEF_REG_RSVD_63_12_SHIFT 12
1829#define VTD_BF_MTRRDEF_REG_RSVD_63_12_MASK UINT64_C(0xfffffffffffff000)
1830RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_MTRRDEF_REG_, UINT64_C(0), UINT64_MAX,
1831 (TYPE, RSVD_9_8, FE, E, RSVD_63_12));
1832
1833/** RW: Read/write mask. */
1834#define VTD_MTRRDEF_REG_RW_MASK ( VTD_BF_MTRRDEF_REG_TYPE_MASK | VTD_BF_MTRRDEF_REG_FE_MASK \
1835 | VTD_BF_MTRRDEF_REG_E_MASK)
1836/** @} */
1837
1838
1839/** @name Virtual Command Capability Register (VCCAP_REG).
1840 * In accordance with the Intel spec.
1841 * @{ */
1842/** PAS: PASID Support. */
1843#define VTD_BF_VCCAP_REG_PAS_SHIFT 0
1844#define VTD_BF_VCCAP_REG_PAS_MASK UINT64_C(0x0000000000000001)
1845/** R: Reserved (bits 63:1). */
1846#define VTD_BF_VCCAP_REG_RSVD_63_1_SHIFT 1
1847#define VTD_BF_VCCAP_REG_RSVD_63_1_MASK UINT64_C(0xfffffffffffffffe)
1848RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_VCCAP_REG_, UINT64_C(0), UINT64_MAX,
1849 (PAS, RSVD_63_1));
1850
1851/** RW: Read/write mask. */
1852#define VTD_VCCAP_REG_RW_MASK UINT64_C(0)
1853/** @} */
1854
1855
1856/** @name Virtual Command Extended Operand Register (VCMD_EO_REG).
1857 * In accordance with the Intel spec.
1858 * @{ */
1859/** OB: Operand B. */
1860#define VTD_BF_VCMD_EO_REG_OB_SHIFT 0
1861#define VTD_BF_VCMD_EO_REG_OB_MASK UINT32_C(0xffffffffffffffff)
1862
1863/** RW: Read/write mask. */
1864#define VTD_VCMD_EO_REG_RW_MASK VTD_BF_VCMD_EO_REG_OB_MASK
1865/** @} */
1866
1867
1868/** @name Virtual Command Register (VCMD_REG).
1869 * In accordance with the Intel spec.
1870 * @{ */
1871/** CMD: Command. */
1872#define VTD_BF_VCMD_REG_CMD_SHIFT 0
1873#define VTD_BF_VCMD_REG_CMD_MASK UINT64_C(0x00000000000000ff)
1874/** OP: Operand. */
1875#define VTD_BF_VCMD_REG_OP_SHIFT 8
1876#define VTD_BF_VCMD_REG_OP_MASK UINT64_C(0xffffffffffffff00)
1877RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_VCMD_REG_, UINT64_C(0), UINT64_MAX,
1878 (CMD, OP));
1879
1880/** RW: Read/write mask. */
1881#define VTD_VCMD_REG_RW_MASK (VTD_BF_VCMD_REG_CMD_MASK | VTD_BF_VCMD_REG_OP_MASK)
1882/** @} */
1883
1884
1885/** @name Virtual Command Response Register (VCRSP_REG).
1886 * In accordance with the Intel spec.
1887 * @{ */
1888/** IP: In Progress. */
1889#define VTD_BF_VCRSP_REG_IP_SHIFT 0
1890#define VTD_BF_VCRSP_REG_IP_MASK UINT64_C(0x0000000000000001)
1891/** SC: Status Code. */
1892#define VTD_BF_VCRSP_REG_SC_SHIFT 1
1893#define VTD_BF_VCRSP_REG_SC_MASK UINT64_C(0x0000000000000006)
1894/** R: Reserved (bits 7:3). */
1895#define VTD_BF_VCRSP_REG_RSVD_7_3_SHIFT 3
1896#define VTD_BF_VCRSP_REG_RSVD_7_3_MASK UINT64_C(0x00000000000000f8)
1897/** RSLT: Result. */
1898#define VTD_BF_VCRSP_REG_RSLT_SHIFT 8
1899#define VTD_BF_VCRSP_REG_RSLT_MASK UINT64_C(0xffffffffffffff00)
1900RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_VCRSP_REG_, UINT64_C(0), UINT64_MAX,
1901 (IP, SC, RSVD_7_3, RSLT));
1902
1903/** RW: Read/write mask. */
1904#define VTD_VCRSP_REG_RW_MASK UINT64_C(0)
1905/** @} */
1906
1907
1908/** @name Generic Invalidation Descriptor.
1909 * In accordance with the Intel spec.
1910 * Non-reserved fields here are common to all invalidation descriptors.
1911 * @{ */
1912/** Type (Lo). */
1913#define VTD_BF_0_GENERIC_INV_DSC_TYPE_LO_SHIFT 0
1914#define VTD_BF_0_GENERIC_INV_DSC_TYPE_LO_MASK UINT64_C(0x000000000000000f)
1915/** R: Reserved (bits 8:4). */
1916#define VTD_BF_0_GENERIC_INV_DSC_RSVD_8_4_SHIFT 4
1917#define VTD_BF_0_GENERIC_INV_DSC_RSVD_8_4_MASK UINT64_C(0x00000000000001f0)
1918/** Type (Hi). */
1919#define VTD_BF_0_GENERIC_INV_DSC_TYPE_HI_SHIFT 9
1920#define VTD_BF_0_GENERIC_INV_DSC_TYPE_HI_MASK UINT64_C(0x0000000000000e00)
1921/** R: Reserved (bits 63:12). */
1922#define VTD_BF_0_GENERIC_INV_DSC_RSVD_63_12_SHIFT 12
1923#define VTD_BF_0_GENERIC_INV_DSC_RSVD_63_12_MASK UINT64_C(0xfffffffffffff000)
1924RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_GENERIC_INV_DSC_, UINT64_C(0), UINT64_MAX,
1925 (TYPE_LO, RSVD_8_4, TYPE_HI, RSVD_63_12));
1926
1927/** GENERIC_INV_DSC: Type. */
1928#define VTD_GENERIC_INV_DSC_GET_TYPE(a) ((((a) & VTD_BF_0_GENERIC_INV_DSC_TYPE_HI_MASK) >> 5) \
1929 | ((a) & VTD_BF_0_GENERIC_INV_DSC_TYPE_LO_MASK))
1930/** @} */
1931
1932
1933/** @name Context-Cache Invalidation Descriptor (cc_inv_dsc).
1934 * In accordance with the Intel spec.
1935 * @{ */
1936/** Type (Lo). */
1937#define VTD_BF_0_CC_INV_DSC_TYPE_LO_SHIFT 0
1938#define VTD_BF_0_CC_INV_DSC_TYPE_LO_MASK UINT64_C(0x000000000000000f)
1939/** G: Granularity. */
1940#define VTD_BF_0_CC_INV_DSC_G_SHIFT 4
1941#define VTD_BF_0_CC_INV_DSC_G_MASK UINT64_C(0x0000000000000030)
1942/** R: Reserved (bits 8:6). */
1943#define VTD_BF_0_CC_INV_DSC_RSVD_8_6_SHIFT 6
1944#define VTD_BF_0_CC_INV_DSC_RSVD_8_6_MASK UINT64_C(0x00000000000001c0)
1945/** Type (Hi). */
1946#define VTD_BF_0_CC_INV_DSC_TYPE_HI_SHIFT 9
1947#define VTD_BF_0_CC_INV_DSC_TYPE_HI_MASK UINT64_C(0x0000000000000e00)
1948/** R: Reserved (bits 15:12). */
1949#define VTD_BF_0_CC_INV_DSC_RSVD_15_12_SHIFT 12
1950#define VTD_BF_0_CC_INV_DSC_RSVD_15_12_MASK UINT64_C(0x000000000000f000)
1951/** DID: Domain Id. */
1952#define VTD_BF_0_CC_INV_DSC_DID_SHIFT 16
1953#define VTD_BF_0_CC_INV_DSC_DID_MASK UINT64_C(0x00000000ffff0000)
1954/** SID: Source Id. */
1955#define VTD_BF_0_CC_INV_DSC_SID_SHIFT 32
1956#define VTD_BF_0_CC_INV_DSC_SID_MASK UINT64_C(0x0000ffff00000000)
1957/** FM: Function Mask. */
1958#define VTD_BF_0_CC_INV_DSC_FM_SHIFT 48
1959#define VTD_BF_0_CC_INV_DSC_FM_MASK UINT64_C(0x0003000000000000)
1960/** R: Reserved (bits 63:50). */
1961#define VTD_BF_0_CC_INV_DSC_RSVD_63_50_SHIFT 50
1962#define VTD_BF_0_CC_INV_DSC_RSVD_63_50_MASK UINT64_C(0xfffc000000000000)
1963RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_CC_INV_DSC_, UINT64_C(0), UINT64_MAX,
1964 (TYPE_LO, G, RSVD_8_6, TYPE_HI, RSVD_15_12, DID, SID, FM, RSVD_63_50));
1965/** @} */
1966
1967
1968/** @name PASID-Cache Invalidation Descriptor (pc_inv_dsc).
1969 * In accordance with the Intel spec.
1970 * @{ */
1971/** Type (Lo). */
1972#define VTD_BF_0_PC_INV_DSC_TYPE_LO_SHIFT 0
1973#define VTD_BF_0_PC_INV_DSC_TYPE_LO_MASK UINT64_C(0x000000000000000f)
1974/** G: Granularity. */
1975#define VTD_BF_0_PC_INV_DSC_G_SHIFT 4
1976#define VTD_BF_0_PC_INV_DSC_G_MASK UINT64_C(0x0000000000000030)
1977/** R: Reserved (bits 8:6). */
1978#define VTD_BF_0_PC_INV_DSC_RSVD_8_6_SHIFT 6
1979#define VTD_BF_0_PC_INV_DSC_RSVD_8_6_MASK UINT64_C(0x00000000000001c0)
1980/** Type (Hi). */
1981#define VTD_BF_0_PC_INV_DSC_TYPE_HI_SHIFT 9
1982#define VTD_BF_0_PC_INV_DSC_TYPE_HI_MASK UINT64_C(0x0000000000000e00)
1983/** R: Reserved (bits 15:12). */
1984#define VTD_BF_0_PC_INV_DSC_RSVD_15_12_SHIFT 12
1985#define VTD_BF_0_PC_INV_DSC_RSVD_15_12_MASK UINT64_C(0x000000000000f000)
1986/** DID: Domain Id. */
1987#define VTD_BF_0_PC_INV_DSC_DID_SHIFT 16
1988#define VTD_BF_0_PC_INV_DSC_DID_MASK UINT64_C(0x00000000ffff0000)
1989/** PASID: Process Address-Space Id. */
1990#define VTD_BF_0_PC_INV_DSC_PASID_SHIFT 32
1991#define VTD_BF_0_PC_INV_DSC_PASID_MASK UINT64_C(0x000fffff00000000)
1992/** R: Reserved (bits 63:52). */
1993#define VTD_BF_0_PC_INV_DSC_RSVD_63_52_SHIFT 52
1994#define VTD_BF_0_PC_INV_DSC_RSVD_63_52_MASK UINT64_C(0xfff0000000000000)
1995
1996RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_PC_INV_DSC_, UINT64_C(0), UINT64_MAX,
1997 (TYPE_LO, G, RSVD_8_6, TYPE_HI, RSVD_15_12, DID, PASID, RSVD_63_52));
1998/** @} */
1999
2000
2001/** @name IOTLB Invalidate Descriptor (iotlb_inv_dsc).
2002 * In accordance with the Intel spec.
2003 * @{ */
2004/** Type (Lo). */
2005#define VTD_BF_0_IOTLB_INV_DSC_TYPE_LO_SHIFT 0
2006#define VTD_BF_0_IOTLB_INV_DSC_TYPE_LO_MASK UINT64_C(0x000000000000000f)
2007/** G: Granularity. */
2008#define VTD_BF_0_IOTLB_INV_DSC_G_SHIFT 4
2009#define VTD_BF_0_IOTLB_INV_DSC_G_MASK UINT64_C(0x0000000000000030)
2010/** DW: Drain Writes. */
2011#define VTD_BF_0_IOTLB_INV_DSC_DW_SHIFT 6
2012#define VTD_BF_0_IOTLB_INV_DSC_DW_MASK UINT64_C(0x0000000000000040)
2013/** DR: Drain Reads. */
2014#define VTD_BF_0_IOTLB_INV_DSC_DR_SHIFT 7
2015#define VTD_BF_0_IOTLB_INV_DSC_DR_MASK UINT64_C(0x0000000000000080)
2016/** R: Reserved (bit 8). */
2017#define VTD_BF_0_IOTLB_INV_DSC_RSVD_8_SHIFT 8
2018#define VTD_BF_0_IOTLB_INV_DSC_RSVD_8_MASK UINT64_C(0x0000000000000100)
2019/** Type (Hi). */
2020#define VTD_BF_0_IOTLB_INV_DSC_TYPE_HI_SHIFT 9
2021#define VTD_BF_0_IOTLB_INV_DSC_TYPE_HI_MASK UINT64_C(0x0000000000000e00)
2022/** R: Reserved (bits 15:12). */
2023#define VTD_BF_0_IOTLB_INV_DSC_RSVD_15_12_SHIFT 12
2024#define VTD_BF_0_IOTLB_INV_DSC_RSVD_15_12_MASK UINT64_C(0x000000000000f000)
2025/** DID: Domain Id. */
2026#define VTD_BF_0_IOTLB_INV_DSC_DID_SHIFT 16
2027#define VTD_BF_0_IOTLB_INV_DSC_DID_MASK UINT64_C(0x00000000ffff0000)
2028/** R: Reserved (bits 63:32). */
2029#define VTD_BF_0_IOTLB_INV_DSC_RSVD_63_32_SHIFT 32
2030#define VTD_BF_0_IOTLB_INV_DSC_RSVD_63_32_MASK UINT64_C(0xffffffff00000000)
2031RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_IOTLB_INV_DSC_, UINT64_C(0), UINT64_MAX,
2032 (TYPE_LO, G, DW, DR, RSVD_8, TYPE_HI, RSVD_15_12, DID, RSVD_63_32));
2033
2034/** AM: Address Mask. */
2035#define VTD_BF_1_IOTLB_INV_DSC_AM_SHIFT 0
2036#define VTD_BF_1_IOTLB_INV_DSC_AM_MASK UINT64_C(0x000000000000003f)
2037/** IH: Invalidation Hint. */
2038#define VTD_BF_1_IOTLB_INV_DSC_IH_SHIFT 6
2039#define VTD_BF_1_IOTLB_INV_DSC_IH_MASK UINT64_C(0x0000000000000040)
2040/** R: Reserved (bits 11:7). */
2041#define VTD_BF_1_IOTLB_INV_DSC_RSVD_11_7_SHIFT 7
2042#define VTD_BF_1_IOTLB_INV_DSC_RSVD_11_7_MASK UINT64_C(0x0000000000000f80)
2043/** ADDR: Address. */
2044#define VTD_BF_1_IOTLB_INV_DSC_ADDR_SHIFT 12
2045#define VTD_BF_1_IOTLB_INV_DSC_ADDR_MASK UINT64_C(0xfffffffffffff000)
2046RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_IOTLB_INV_DSC_, UINT64_C(0), UINT64_MAX,
2047 (AM, IH, RSVD_11_7, ADDR));
2048/** @} */
2049
2050
2051/** @name PASID-based IOTLB Invalidate Descriptor (p_iotlb_inv_dsc).
2052 * In accordance with the Intel spec.
2053 * @{ */
2054/** Type (Lo). */
2055#define VTD_BF_0_P_IOTLB_INV_DSC_TYPE_LO_SHIFT 0
2056#define VTD_BF_0_P_IOTLB_INV_DSC_TYPE_LO_MASK UINT64_C(0x000000000000000f)
2057/** G: Granularity. */
2058#define VTD_BF_0_P_IOTLB_INV_DSC_G_SHIFT 4
2059#define VTD_BF_0_P_IOTLB_INV_DSC_G_MASK UINT64_C(0x0000000000000030)
2060/** R: Reserved (bits 8:6). */
2061#define VTD_BF_0_P_IOTLB_INV_DSC_RSVD_8_6_SHIFT 6
2062#define VTD_BF_0_P_IOTLB_INV_DSC_RSVD_8_6_MASK UINT64_C(0x00000000000001c0)
2063/** Type (Hi). */
2064#define VTD_BF_0_P_IOTLB_INV_DSC_TYPE_HI_SHIFT 9
2065#define VTD_BF_0_P_IOTLB_INV_DSC_TYPE_HI_MASK UINT64_C(0x0000000000000e00)
2066/** R: Reserved (bits 15:12). */
2067#define VTD_BF_0_P_IOTLB_INV_DSC_RSVD_15_12_SHIFT 12
2068#define VTD_BF_0_P_IOTLB_INV_DSC_RSVD_15_12_MASK UINT64_C(0x000000000000f000)
2069/** DID: Domain Id. */
2070#define VTD_BF_0_P_IOTLB_INV_DSC_DID_SHIFT 16
2071#define VTD_BF_0_P_IOTLB_INV_DSC_DID_MASK UINT64_C(0x00000000ffff0000)
2072/** PASID: Process Address-Space Id. */
2073#define VTD_BF_0_P_IOTLB_INV_DSC_PASID_SHIFT 32
2074#define VTD_BF_0_P_IOTLB_INV_DSC_PASID_MASK UINT64_C(0x000fffff00000000)
2075/** R: Reserved (bits 63:52). */
2076#define VTD_BF_0_P_IOTLB_INV_DSC_RSVD_63_52_SHIFT 52
2077#define VTD_BF_0_P_IOTLB_INV_DSC_RSVD_63_52_MASK UINT64_C(0xfff0000000000000)
2078RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_P_IOTLB_INV_DSC_, UINT64_C(0), UINT64_MAX,
2079 (TYPE_LO, G, RSVD_8_6, TYPE_HI, RSVD_15_12, DID, PASID, RSVD_63_52));
2080
2081
2082/** AM: Address Mask. */
2083#define VTD_BF_1_P_IOTLB_INV_DSC_AM_SHIFT 0
2084#define VTD_BF_1_P_IOTLB_INV_DSC_AM_MASK UINT64_C(0x000000000000003f)
2085/** IH: Invalidation Hint. */
2086#define VTD_BF_1_P_IOTLB_INV_DSC_IH_SHIFT 6
2087#define VTD_BF_1_P_IOTLB_INV_DSC_IH_MASK UINT64_C(0x0000000000000040)
2088/** R: Reserved (bits 11:7). */
2089#define VTD_BF_1_P_IOTLB_INV_DSC_RSVD_11_7_SHIFT 7
2090#define VTD_BF_1_P_IOTLB_INV_DSC_RSVD_11_7_MASK UINT64_C(0x0000000000000f80)
2091/** ADDR: Address. */
2092#define VTD_BF_1_P_IOTLB_INV_DSC_ADDR_SHIFT 12
2093#define VTD_BF_1_P_IOTLB_INV_DSC_ADDR_MASK UINT64_C(0xfffffffffffff000)
2094RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_P_IOTLB_INV_DSC_, UINT64_C(0), UINT64_MAX,
2095 (AM, IH, RSVD_11_7, ADDR));
2096/** @} */
2097
2098
2099/** @name Device-TLB Invalidate Descriptor (dev_tlb_inv_dsc).
2100 * In accordance with the Intel spec.
2101 * @{ */
2102/** Type (Lo). */
2103#define VTD_BF_0_DEV_TLB_INV_DSC_TYPE_LO_SHIFT 0
2104#define VTD_BF_0_DEV_TLB_INV_DSC_TYPE_LO_MASK UINT64_C(0x000000000000000f)
2105/** R: Reserved (bits 8:4). */
2106#define VTD_BF_0_DEV_TLB_INV_DSC_RSVD_8_4_SHIFT 4
2107#define VTD_BF_0_DEV_TLB_INV_DSC_RSVD_8_4_MASK UINT64_C(0x00000000000001f0)
2108/** Type (Hi). */
2109#define VTD_BF_0_DEV_TLB_INV_DSC_TYPE_HI_SHIFT 9
2110#define VTD_BF_0_DEV_TLB_INV_DSC_TYPE_HI_MASK UINT64_C(0x0000000000000e00)
2111/** PFSID: Physical-Function Source Id (Lo). */
2112#define VTD_BF_0_DEV_TLB_INV_DSC_PFSID_LO_SHIFT 12
2113#define VTD_BF_0_DEV_TLB_INV_DSC_PFSID_LO_MASK UINT64_C(0x000000000000f000)
2114/** MIP: Max Invalidations Pending. */
2115#define VTD_BF_0_DEV_TLB_INV_DSC_MIP_SHIFT 16
2116#define VTD_BF_0_DEV_TLB_INV_DSC_MIP_MASK UINT64_C(0x00000000001f0000)
2117/** R: Reserved (bits 31:21). */
2118#define VTD_BF_0_DEV_TLB_INV_DSC_RSVD_31_21_SHIFT 21
2119#define VTD_BF_0_DEV_TLB_INV_DSC_RSVD_31_21_MASK UINT64_C(0x00000000ffe00000)
2120/** SID: Source Id. */
2121#define VTD_BF_0_DEV_TLB_INV_DSC_SID_SHIFT 32
2122#define VTD_BF_0_DEV_TLB_INV_DSC_SID_MASK UINT64_C(0x0000ffff00000000)
2123/** R: Reserved (bits 51:48). */
2124#define VTD_BF_0_DEV_TLB_INV_DSC_RSVD_51_48_SHIFT 48
2125#define VTD_BF_0_DEV_TLB_INV_DSC_RSVD_51_48_MASK UINT64_C(0x000f000000000000)
2126/** PFSID: Physical-Function Source Id (Hi). */
2127#define VTD_BF_0_DEV_TLB_INV_DSC_PFSID_HI_SHIFT 52
2128#define VTD_BF_0_DEV_TLB_INV_DSC_PFSID_HI_MASK UINT64_C(0xfff0000000000000)
2129RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_DEV_TLB_INV_DSC_, UINT64_C(0), UINT64_MAX,
2130 (TYPE_LO, RSVD_8_4, TYPE_HI, PFSID_LO, MIP, RSVD_31_21, SID, RSVD_51_48, PFSID_HI));
2131
2132/** S: Size. */
2133#define VTD_BF_1_DEV_TLB_INV_DSC_S_SHIFT 0
2134#define VTD_BF_1_DEV_TLB_INV_DSC_S_MASK UINT64_C(0x0000000000000001)
2135/** R: Reserved (bits 11:1). */
2136#define VTD_BF_1_DEV_TLB_INV_DSC_RSVD_11_1_SHIFT 1
2137#define VTD_BF_1_DEV_TLB_INV_DSC_RSVD_11_1_MASK UINT64_C(0x0000000000000ffe)
2138/** ADDR: Address. */
2139#define VTD_BF_1_DEV_TLB_INV_DSC_ADDR_SHIFT 12
2140#define VTD_BF_1_DEV_TLB_INV_DSC_ADDR_MASK UINT64_C(0xfffffffffffff000)
2141RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_DEV_TLB_INV_DSC_, UINT64_C(0), UINT64_MAX,
2142 (S, RSVD_11_1, ADDR));
2143/** @} */
2144
2145
2146/** @name PASID-based-device-TLB Invalidate Descriptor (p_dev_tlb_inv_dsc).
2147 * In accordance with the Intel spec.
2148 * @{ */
2149/** Type (Lo). */
2150#define VTD_BF_0_P_DEV_TLB_INV_DSC_TYPE_LO_SHIFT 0
2151#define VTD_BF_0_P_DEV_TLB_INV_DSC_TYPE_LO_MASK UINT64_C(0x000000000000000f)
2152/** MIP: Max Invalidations Pending. */
2153#define VTD_BF_0_P_DEV_TLB_INV_DSC_MIP_SHIFT 4
2154#define VTD_BF_0_P_DEV_TLB_INV_DSC_MIP_MASK UINT64_C(0x00000000000001f0)
2155/** Type (Hi). */
2156#define VTD_BF_0_P_DEV_TLB_INV_DSC_TYPE_HI_SHIFT 9
2157#define VTD_BF_0_P_DEV_TLB_INV_DSC_TYPE_HI_MASK UINT64_C(0x0000000000000e00)
2158/** PFSID: Physical-Function Source Id (Lo). */
2159#define VTD_BF_0_P_DEV_TLB_INV_DSC_PFSID_LO_SHIFT 12
2160#define VTD_BF_0_P_DEV_TLB_INV_DSC_PFSID_LO_MASK UINT64_C(0x000000000000f000)
2161/** SID: Source Id. */
2162#define VTD_BF_0_P_DEV_TLB_INV_DSC_SID_SHIFT 16
2163#define VTD_BF_0_P_DEV_TLB_INV_DSC_SID_MASK UINT64_C(0x00000000ffff0000)
2164/** PASID: Process Address-Space Id. */
2165#define VTD_BF_0_P_DEV_TLB_INV_DSC_PASID_SHIFT 32
2166#define VTD_BF_0_P_DEV_TLB_INV_DSC_PASID_MASK UINT64_C(0x000fffff00000000)
2167/** PFSID: Physical-Function Source Id (Hi). */
2168#define VTD_BF_0_P_DEV_TLB_INV_DSC_PFSID_HI_SHIFT 52
2169#define VTD_BF_0_P_DEV_TLB_INV_DSC_PFSID_HI_MASK UINT64_C(0xfff0000000000000)
2170RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_P_DEV_TLB_INV_DSC_, UINT64_C(0), UINT64_MAX,
2171 (TYPE_LO, MIP, TYPE_HI, PFSID_LO, SID, PASID, PFSID_HI));
2172
2173/** G: Granularity. */
2174#define VTD_BF_1_P_DEV_TLB_INV_DSC_G_SHIFT 0
2175#define VTD_BF_1_P_DEV_TLB_INV_DSC_G_MASK UINT64_C(0x0000000000000001)
2176/** R: Reserved (bits 10:1). */
2177#define VTD_BF_1_P_DEV_TLB_INV_DSC_RSVD_10_1_SHIFT 1
2178#define VTD_BF_1_P_DEV_TLB_INV_DSC_RSVD_10_1_MASK UINT64_C(0x00000000000007fe)
2179/** S: Size. */
2180#define VTD_BF_1_P_DEV_TLB_INV_DSC_S_SHIFT 11
2181#define VTD_BF_1_P_DEV_TLB_INV_DSC_S_MASK UINT64_C(0x0000000000000800)
2182/** ADDR: Address. */
2183#define VTD_BF_1_P_DEV_TLB_INV_DSC_ADDR_SHIFT 12
2184#define VTD_BF_1_P_DEV_TLB_INV_DSC_ADDR_MASK UINT64_C(0xfffffffffffff000)
2185RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_P_DEV_TLB_INV_DSC_, UINT64_C(0), UINT64_MAX,
2186 (G, RSVD_10_1, S, ADDR));
2187/** @} */
2188
2189
2190/** @name Interrupt Entry Cache Invalidate Descriptor (iec_inv_dsc).
2191 * In accordance with the Intel spec.
2192 * @{ */
2193/** Type (Lo). */
2194#define VTD_BF_0_IEC_INV_DSC_TYPE_LO_SHIFT 0
2195#define VTD_BF_0_IEC_INV_DSC_TYPE_LO_MASK UINT64_C(0x000000000000000f)
2196/** G: Granularity. */
2197#define VTD_BF_0_IEC_INV_DSC_G_SHIFT 4
2198#define VTD_BF_0_IEC_INV_DSC_G_MASK UINT64_C(0x0000000000000010)
2199/** R: Reserved (bits 8:5). */
2200#define VTD_BF_0_IEC_INV_DSC_RSVD_8_5_SHIFT 5
2201#define VTD_BF_0_IEC_INV_DSC_RSVD_8_5_MASK UINT64_C(0x00000000000001e0)
2202/** Type (Hi). */
2203#define VTD_BF_0_IEC_INV_DSC_TYPE_HI_SHIFT 9
2204#define VTD_BF_0_IEC_INV_DSC_TYPE_HI_MASK UINT64_C(0x0000000000000e00)
2205/** R: Reserved (bits 26:12). */
2206#define VTD_BF_0_IEC_INV_DSC_RSVD_26_12_SHIFT 12
2207#define VTD_BF_0_IEC_INV_DSC_RSVD_26_12_MASK UINT64_C(0x0000000007fff000)
2208/** IM: Index Mask. */
2209#define VTD_BF_0_IEC_INV_DSC_IM_SHIFT 27
2210#define VTD_BF_0_IEC_INV_DSC_IM_MASK UINT64_C(0x00000000f8000000)
2211/** IIDX: Interrupt Index. */
2212#define VTD_BF_0_IEC_INV_DSC_IIDX_SHIFT 32
2213#define VTD_BF_0_IEC_INV_DSC_IIDX_MASK UINT64_C(0x0000ffff00000000)
2214/** R: Reserved (bits 63:48). */
2215#define VTD_BF_0_IEC_INV_DSC_RSVD_63_48_SHIFT 48
2216#define VTD_BF_0_IEC_INV_DSC_RSVD_63_48_MASK UINT64_C(0xffff000000000000)
2217RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_IEC_INV_DSC_, UINT64_C(0), UINT64_MAX,
2218 (TYPE_LO, G, RSVD_8_5, TYPE_HI, RSVD_26_12, IM, IIDX, RSVD_63_48));
2219/** @} */
2220
2221
2222/** @name Invalidation Wait Descriptor (inv_wait_dsc).
2223 * In accordance with the Intel spec.
2224 * @{ */
2225/** Type (Lo). */
2226#define VTD_BF_0_INV_WAIT_DSC_TYPE_LO_SHIFT 0
2227#define VTD_BF_0_INV_WAIT_DSC_TYPE_LO_MASK UINT64_C(0x000000000000000f)
2228/** IF: Interrupt Flag. */
2229#define VTD_BF_0_INV_WAIT_DSC_IF_SHIFT 4
2230#define VTD_BF_0_INV_WAIT_DSC_IF_MASK UINT64_C(0x0000000000000010)
2231/** SW: Status Write. */
2232#define VTD_BF_0_INV_WAIT_DSC_SW_SHIFT 5
2233#define VTD_BF_0_INV_WAIT_DSC_SW_MASK UINT64_C(0x0000000000000020)
2234/** FN: Fence Flag. */
2235#define VTD_BF_0_INV_WAIT_DSC_FN_SHIFT 6
2236#define VTD_BF_0_INV_WAIT_DSC_FN_MASK UINT64_C(0x0000000000000040)
2237/** PD: Page-Request Drain. */
2238#define VTD_BF_0_INV_WAIT_DSC_PD_SHIFT 7
2239#define VTD_BF_0_INV_WAIT_DSC_PD_MASK UINT64_C(0x0000000000000080)
2240/** R: Reserved (bit 8). */
2241#define VTD_BF_0_INV_WAIT_DSC_RSVD_8_SHIFT 8
2242#define VTD_BF_0_INV_WAIT_DSC_RSVD_8_MASK UINT64_C(0x0000000000000100)
2243/** Type (Hi). */
2244#define VTD_BF_0_INV_WAIT_DSC_TYPE_HI_SHIFT 9
2245#define VTD_BF_0_INV_WAIT_DSC_TYPE_HI_MASK UINT64_C(0x0000000000000e00)
2246/** R: Reserved (bits 31:12). */
2247#define VTD_BF_0_INV_WAIT_DSC_RSVD_31_12_SHIFT 12
2248#define VTD_BF_0_INV_WAIT_DSC_RSVD_31_12_MASK UINT64_C(0x00000000fffff000)
2249/** STDATA: Status Data. */
2250#define VTD_BF_0_INV_WAIT_DSC_STDATA_SHIFT 32
2251#define VTD_BF_0_INV_WAIT_DSC_STDATA_MASK UINT64_C(0xffffffff00000000)
2252RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_INV_WAIT_DSC_, UINT64_C(0), UINT64_MAX,
2253 (TYPE_LO, IF, SW, FN, PD, RSVD_8, TYPE_HI, RSVD_31_12, STDATA));
2254
2255/** R: Reserved (bits 1:0). */
2256#define VTD_BF_1_INV_WAIT_DSC_RSVD_1_0_SHIFT 0
2257#define VTD_BF_1_INV_WAIT_DSC_RSVD_1_0_MASK UINT64_C(0x0000000000000003)
2258/** STADDR: Status Address. */
2259#define VTD_BF_1_INV_WAIT_DSC_STADDR_SHIFT 2
2260#define VTD_BF_1_INV_WAIT_DSC_STADDR_MASK UINT64_C(0xfffffffffffffffc)
2261RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_INV_WAIT_DSC_, UINT64_C(0), UINT64_MAX,
2262 (RSVD_1_0, STADDR));
2263
2264/* INV_WAIT_DSC: Qword 0 valid mask. */
2265#define VTD_INV_WAIT_DSC_0_VALID_MASK ( VTD_BF_0_INV_WAIT_DSC_TYPE_LO_MASK \
2266 | VTD_BF_0_INV_WAIT_DSC_IF_MASK \
2267 | VTD_BF_0_INV_WAIT_DSC_SW_MASK \
2268 | VTD_BF_0_INV_WAIT_DSC_FN_MASK \
2269 | VTD_BF_0_INV_WAIT_DSC_PD_MASK \
2270 | VTD_BF_0_INV_WAIT_DSC_TYPE_HI_MASK \
2271 | VTD_BF_0_INV_WAIT_DSC_STDATA_MASK)
2272/* INV_WAIT_DSC: Qword 1 valid mask. */
2273#define VTD_INV_WAIT_DSC_1_VALID_MASK VTD_BF_1_INV_WAIT_DSC_STADDR_MASK
2274/** @} */
2275
2276
2277/** @name Invalidation descriptor types.
2278 * In accordance with the Intel spec.
2279 * @{ */
2280#define VTD_CC_INV_DSC_TYPE 1
2281#define VTD_IOTLB_INV_DSC_TYPE 2
2282#define VTD_DEV_TLB_INV_DSC_TYPE 3
2283#define VTD_IEC_INV_DSC_TYPE 4
2284#define VTD_INV_WAIT_DSC_TYPE 5
2285#define VTD_P_IOTLB_INV_DSC_TYPE 6
2286#define VTD_PC_INV_DSC_TYPE 7
2287#define VTD_P_DEV_TLB_INV_DSC_TYPE 8
2288/** @} */
2289
2290
2291/** @name Remappable Format Interrupt Request.
2292 * In accordance with the Intel spec.
2293 * @{ */
2294/** IGN: Ignored (bits 1:0). */
2295#define VTD_BF_REMAPPABLE_MSI_ADDR_IGN_1_0_SHIFT 0
2296#define VTD_BF_REMAPPABLE_MSI_ADDR_IGN_1_0_MASK UINT32_C(0x00000003)
2297/** Handle (Hi). */
2298#define VTD_BF_REMAPPABLE_MSI_ADDR_HANDLE_HI_SHIFT 2
2299#define VTD_BF_REMAPPABLE_MSI_ADDR_HANDLE_HI_MASK UINT32_C(0x00000004)
2300/** SHV: Subhandle Valid. */
2301#define VTD_BF_REMAPPABLE_MSI_ADDR_SHV_SHIFT 3
2302#define VTD_BF_REMAPPABLE_MSI_ADDR_SHV_MASK UINT32_C(0x00000008)
2303/** Interrupt format. */
2304#define VTD_BF_REMAPPABLE_MSI_ADDR_INTR_FMT_SHIFT 4
2305#define VTD_BF_REMAPPABLE_MSI_ADDR_INTR_FMT_MASK UINT32_C(0x00000010)
2306/** Handle (Lo). */
2307#define VTD_BF_REMAPPABLE_MSI_ADDR_HANDLE_LO_SHIFT 5
2308#define VTD_BF_REMAPPABLE_MSI_ADDR_HANDLE_LO_MASK UINT32_C(0x000fffe0)
2309/** Address. */
2310#define VTD_BF_REMAPPABLE_MSI_ADDR_ADDR_SHIFT 20
2311#define VTD_BF_REMAPPABLE_MSI_ADDR_ADDR_MASK UINT32_C(0xfff00000)
2312RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_REMAPPABLE_MSI_ADDR_, UINT32_C(0), UINT32_MAX,
2313 (IGN_1_0, HANDLE_HI, SHV, INTR_FMT, HANDLE_LO, ADDR));
2314
2315/** Subhandle. */
2316#define VTD_BF_REMAPPABLE_MSI_DATA_SUBHANDLE_SHIFT 0
2317#define VTD_BF_REMAPPABLE_MSI_DATA_SUBHANDLE_MASK UINT32_C(0x0000ffff)
2318/** R: Reserved (bits 31:16). */
2319#define VTD_BF_REMAPPABLE_MSI_DATA_RSVD_31_16_SHIFT 16
2320#define VTD_BF_REMAPPABLE_MSI_DATA_RSVD_31_16_MASK UINT32_C(0xffff0000)
2321RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_REMAPPABLE_MSI_DATA_, UINT32_C(0), UINT32_MAX,
2322 (SUBHANDLE, RSVD_31_16));
2323
2324/** Remappable MSI Address: Valid mask. */
2325#define VTD_REMAPPABLE_MSI_ADDR_VALID_MASK UINT32_MAX
2326/** Remappable MSI Data: Valid mask. */
2327#define VTD_REMAPPABLE_MSI_DATA_VALID_MASK VTD_BF_REMAPPABLE_MSI_DATA_SUBHANDLE_MASK
2328
2329/** Interrupt format: Compatibility. */
2330#define VTD_INTR_FORMAT_COMPAT 0
2331/** Interrupt format: Remappable. */
2332#define VTD_INTR_FORMAT_REMAPPABLE 1
2333/** @} */
2334
2335
2336/** @name Interrupt Remapping Fault Conditions.
2337 * In accordance with the Intel spec.
2338 * @{ */
2339typedef enum VTDIRFAULT
2340{
2341 /** Reserved bits invalid in remappable interrupt. */
2342 VTDIRFAULT_REMAPPABLE_INTR_RSVD = 0x20,
2343
2344 /** Interrupt index for remappable interrupt exceeds table size or referenced
2345 * address above host address width (HAW) */
2346 VTDIRFAULT_INTR_INDEX_INVALID = 0x21,
2347
2348 /** The IRTE is not present. */
2349 VTDIRFAULT_IRTE_NOT_PRESENT = 0x22,
2350 /** Reading IRTE from memory failed. */
2351 VTDIRFAULT_IRTE_READ_FAILED = 0x23,
2352 /** IRTE reserved bits invalid for an IRTE with Present bit set. */
2353 VTDIRFAULT_IRTE_PRESENT_RSVD = 0x24,
2354
2355 /** Compatibility format interrupt (CFI) blocked due to EIME being enabled or CFIs
2356 * were disabled. */
2357 VTDIRFAULT_CFI_BLOCKED = 0x25,
2358
2359 /** IRTE SID, SVT, SQ bits invalid for an IRTE with Present bit set. */
2360 VTDIRFAULT_IRTE_PRESENT_INVALID = 0x26,
2361
2362 /** Reading posted interrupt descriptor (PID) failed. */
2363 VTDIRFAULT_PID_READ_FAILED = 0x27,
2364 /** PID reserved bits invalid. */
2365 VTDIRFAULT_PID_RSVD = 0x28,
2366
2367 /** Untranslated interrupt requested (without PASID) is invalid. */
2368 VTDIRFAULT_IR_WITHOUT_PASID_INVALID = 0x29
2369} VTDIRFAULT;
2370AssertCompileSize(VTDIRFAULT, 4);
2371/** @} */
2372
2373
2374/** @name Address Translation Fault Conditions.
2375 * In accordance with the Intel spec.
2376 * @{ */
2377typedef enum VTDATFAULT
2378{
2379 /* Legacy root table faults (LRT). */
2380 VTDATFAULT_LRT_1 = 0x8,
2381 VTDATFAULT_LRT_2 = 0x1,
2382 VTDATFAULT_LRT_3 = 0xa,
2383
2384 /* Legacy Context-Table Faults (LCT). */
2385 VTDATFAULT_LCT_1 = 0x9,
2386 VTDATFAULT_LCT_2 = 0x2,
2387 VTDATFAULT_LCT_3 = 0xb,
2388 VTDATFAULT_LCT_4_0 = 0x3,
2389 VTDATFAULT_LCT_4_1 = 0x3,
2390 VTDATFAULT_LCT_4_2 = 0x3,
2391 VTDATFAULT_LCT_4_3 = 0x3,
2392 VTDATFAULT_LCT_5 = 0xd,
2393
2394 /* Legacy Second-Level Table Faults (LSL). */
2395 VTDATFAULT_LSL_1 = 0x7,
2396 VTDATFAULT_LSL_2 = 0xc,
2397
2398 /* Legacy General Faults (LGN). */
2399 VTDATFAULT_LGN_1_0 = 0x4,
2400 VTDATFAULT_LGN_1_1 = 0x4,
2401 VTDATFAULT_LGN_1_2 = 0x4,
2402 VTDATFAULT_LGN_1_3 = 0x4,
2403 VTDATFAULT_LGN_2 = 0x5,
2404 VTDATFAULT_LGN_3 = 0x6,
2405 VTDATFAULT_LGN_4 = 0xe,
2406
2407 /* Root-Table Address Register Faults (RTA). */
2408 VTDATFAULT_RTA_1_0 = 0x30,
2409 VTDATFAULT_RTA_1_1 = 0x30,
2410 VTDATFAULT_RTA_1_2 = 0x30,
2411 VTDATFAULT_RTA_1_3 = 0x30,
2412 VTDATFAULT_RTA_2 = 0x31,
2413 VTDATFAULT_RTA_3 = 0x32,
2414 VTDATFAULT_RTA_4 = 0x33,
2415
2416 /* Scalable-Mode Root-Table Faults (SRT). */
2417 VTDATFAULT_SRT_1 = 0x38,
2418 VTDATFAULT_SRT_2 = 0x39,
2419 VTDATFAULT_SRT_3 = 0x3a,
2420
2421 /* Scalable-Mode Context-Table Faults (SCT). */
2422 VTDATFAULT_SCT_1 = 0x40,
2423 VTDATFAULT_SCT_2 = 0x41,
2424 VTDATFAULT_SCT_3 = 0x42,
2425 VTDATFAULT_SCT_4_0 = 0x43,
2426 VTDATFAULT_SCT_4_1 = 0x43,
2427 VTDATFAULT_SCT_4_2 = 0x43,
2428 VTDATFAULT_SCT_5 = 0x44,
2429 VTDATFAULT_SCT_6 = 0x45,
2430 VTDATFAULT_SCT_7 = 0x46,
2431 VTDATFAULT_SCT_8 = 0x47,
2432 VTDATFAULT_SCT_9 = 0x48,
2433
2434 /* Scalable-Mode PASID-Directory Faults (SPD). */
2435 VTDATFAULT_SPD_1 = 0x50,
2436 VTDATFAULT_SPD_2 = 0x51,
2437 VTDATFAULT_SPD_3 = 0x52,
2438
2439 /* Scalable-Mode PASID-Table Faults (SPT). */
2440 VTDATFAULT_SPT_1 = 0x58,
2441 VTDATFAULT_SPT_2 = 0x59,
2442 VTDATFAULT_SPT_3 = 0x5a,
2443 VTDATFAULT_SPT_4_0 = 0x5b,
2444 VTDATFAULT_SPT_4_1 = 0x5b,
2445 VTDATFAULT_SPT_4_2 = 0x5b,
2446 VTDATFAULT_SPT_4_3 = 0x5b,
2447 VTDATFAULT_SPT_4_4 = 0x5b,
2448 VTDATFAULT_SPT_5 = 0x5c,
2449 VTDATFAULT_SPT_6 = 0x5d,
2450
2451 /* Scalable-Mode First-Level Table Faults (SFL). */
2452 VTDATFAULT_SFL_1 = 0x70,
2453 VTDATFAULT_SFL_2 = 0x71,
2454 VTDATFAULT_SFL_3 = 0x72,
2455 VTDATFAULT_SFL_4 = 0x73,
2456 VTDATFAULT_SFL_5 = 0x74,
2457 VTDATFAULT_SFL_6 = 0x75,
2458 VTDATFAULT_SFL_7 = 0x76,
2459 VTDATFAULT_SFL_8 = 0x77,
2460 VTDATFAULT_SFL_9 = 0x90,
2461 VTDATFAULT_SFL_10 = 0x91,
2462
2463 /* Scalable-Mode Second-Level Table Faults (SSL). */
2464 VTDATFAULT_SSL_1 = 0x78,
2465 VTDATFAULT_SSL_2 = 0x79,
2466 VTDATFAULT_SSL_3 = 0x7a,
2467 VTDATFAULT_SSL_4 = 0x7b,
2468 VTDATFAULT_SSL_5 = 0x7c,
2469 VTDATFAULT_SSL_6 = 0x7d,
2470
2471 /* Scalable-Mode General Faults (SGN). */
2472 VTDATFAULT_SGN_1 = 0x80,
2473 VTDATFAULT_SGN_2 = 0x81,
2474 VTDATFAULT_SGN_3 = 0x82,
2475 VTDATFAULT_SGN_4_0 = 0x83,
2476 VTDATFAULT_SGN_4_1 = 0x83,
2477 VTDATFAULT_SGN_4_2 = 0x83,
2478 VTDATFAULT_SGN_5 = 0x84,
2479 VTDATFAULT_SGN_6 = 0x85,
2480 VTDATFAULT_SGN_7 = 0x86,
2481 VTDATFAULT_SGN_8 = 0x87,
2482 VTDATFAULT_SGN_9 = 0x88,
2483 VTDATFAULT_SGN_10 = 0x89
2484} VTDATFAULT;
2485AssertCompileSize(VTDATFAULT, 4);
2486/** @} */
2487
2488
2489/** @name ACPI_DMAR_F_XXX: DMA Remapping Reporting Structure Flags.
2490 * In accordance with the Intel spec.
2491 * @{ */
2492/** INTR_REMAP: Interrupt remapping supported. */
2493#define ACPI_DMAR_F_INTR_REMAP RT_BIT(0)
2494/** X2APIC_OPT_OUT: Request system software to opt-out of enabling x2APIC. */
2495#define ACPI_DMAR_F_X2APIC_OPT_OUT RT_BIT(1)
2496/** DMA_CTRL_PLATFORM_OPT_IN_FLAG: Firmware initiated DMA restricted to reserved
2497 * memory regions (RMRR). */
2498#define ACPI_DMAR_F_DMA_CTRL_PLATFORM_OPT_IN RT_BIT(2)
2499/** @} */
2500
2501
2502/** @name ACPI_DRHD_F_XXX: DMA-Remapping Hardware Unit Definition Flags.
2503 * In accordance with the Intel spec.
2504 * @{ */
2505/** INCLUDE_PCI_ALL: All PCI devices under scope. */
2506#define ACPI_DRHD_F_INCLUDE_PCI_ALL RT_BIT(0)
2507/** @} */
2508
2509
2510/**
2511 * DRHD: DMA-Remapping Hardware Unit Definition.
2512 * In accordance with the Intel spec.
2513 */
2514#pragma pack(1)
2515typedef struct ACPIDRHD
2516{
2517 /** Type (must be 0=DRHD). */
2518 uint16_t uType;
2519 /** Length (must be 16 + size of device scope structure). */
2520 uint16_t cbLength;
2521 /** Flags, see ACPI_DRHD_F_XXX. */
2522 uint8_t fFlags;
2523 /** Reserved (MBZ). */
2524 uint8_t bRsvd;
2525 /** PCI segment number. */
2526 uint16_t uPciSegment;
2527 /** Register Base Address (MMIO). */
2528 uint64_t uRegBaseAddr;
2529 /* Device Scope[] Structures follow. */
2530} ACPIDRHD;
2531#pragma pack()
2532AssertCompileSize(ACPIDRHD, 16);
2533AssertCompileMemberOffset(ACPIDRHD, cbLength, 2);
2534AssertCompileMemberOffset(ACPIDRHD, fFlags, 4);
2535AssertCompileMemberOffset(ACPIDRHD, uPciSegment, 6);
2536AssertCompileMemberOffset(ACPIDRHD, uRegBaseAddr, 8);
2537
2538
2539/** @name ACPIDMARDEVSCOPE_TYPE_XXX: Device Type.
2540 * In accordance with the Intel spec.
2541 * @{ */
2542#define ACPIDMARDEVSCOPE_TYPE_PCI_ENDPOINT 1
2543#define ACPIDMARDEVSCOPE_TYPE_PCI_SUB_HIERARCHY 2
2544#define ACPIDMARDEVSCOPE_TYPE_IOAPIC 3
2545#define ACPIDMARDEVSCOPE_TYPE_MSI_CAP_HPET 4
2546#define ACPIDMARDEVSCOPE_TYPE_ACPI_NAMESPACE_DEV 5
2547/** @} */
2548
2549
2550/**
2551 * ACPI Device Scope Structure - PCI device path.
2552 * In accordance with the Intel spec.
2553 */
2554typedef struct ACPIDEVSCOPEPATH
2555{
2556 /** PCI device number. */
2557 uint8_t uDevice;
2558 /** PCI function number. */
2559 uint8_t uFunction;
2560} ACPIDEVSCOPEPATH;
2561AssertCompileSize(ACPIDEVSCOPEPATH, 2);
2562
2563
2564/**
2565 * Device Scope Structure.
2566 * In accordance with the Intel spec.
2567 */
2568#pragma pack(1)
2569typedef struct ACPIDMARDEVSCOPE
2570{
2571 /** Type, see ACPIDMARDEVSCOPE_TYPE_XXX. */
2572 uint8_t uType;
2573 /** Length (must be 6 + size of auPath field). */
2574 uint8_t cbLength;
2575 /** Reserved (MBZ). */
2576 uint8_t abRsvd[2];
2577 /** Enumeration ID (for I/O APIC, HPET and ACPI namespace devices). */
2578 uint8_t idEnum;
2579 /** First bus number for this device. */
2580 uint8_t uStartBusNum;
2581 /** Hierarchical path from the Host Bridge to the device. */
2582 ACPIDEVSCOPEPATH Path;
2583} ACPIDMARDEVSCOPE;
2584#pragma pack()
2585AssertCompileMemberOffset(ACPIDMARDEVSCOPE, cbLength, 1);
2586AssertCompileMemberOffset(ACPIDMARDEVSCOPE, idEnum, 4);
2587AssertCompileMemberOffset(ACPIDMARDEVSCOPE, uStartBusNum, 5);
2588AssertCompileMemberOffset(ACPIDMARDEVSCOPE, Path, 6);
2589
2590/** ACPI DMAR revision (not the OEM revision field).
2591 * In accordance with the Intel spec. */
2592#define ACPI_DMAR_REVISION 1
2593
2594
2595#endif /* !VBOX_INCLUDED_iommu_intel_h */
2596
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