VirtualBox

source: vbox/trunk/include/VBox/iommu-intel.h@ 89365

Last change on this file since 89365 was 89365, checked in by vboxsync, 4 years ago

Intel IOMMU: bugref:9967 Address translation, WIP.
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File size: 133.2 KB
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1/** @file
2 * IOMMU - Input/Output Memory Management Unit (Intel).
3 */
4
5/*
6 * Copyright (C) 2021 Oracle Corporation
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * The contents of this file may alternatively be used under the terms
17 * of the Common Development and Distribution License Version 1.0
18 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19 * VirtualBox OSE distribution, in which case the provisions of the
20 * CDDL are applicable instead of those of the GPL.
21 *
22 * You may elect to license modified versions of this file under the
23 * terms and conditions of either the GPL or the CDDL or both.
24 */
25
26#ifndef VBOX_INCLUDED_iommu_intel_h
27#define VBOX_INCLUDED_iommu_intel_h
28#ifndef RT_WITHOUT_PRAGMA_ONCE
29# pragma once
30#endif
31
32#include <iprt/assertcompile.h>
33#include <iprt/types.h>
34
35
36/**
37 * @name MMIO register offsets.
38 * In accordance with the Intel spec.
39 * @{
40 */
41#define VTD_MMIO_OFF_VER_REG 0x000 /**< Version. */
42#define VTD_MMIO_OFF_CAP_REG 0x008 /**< Capability. */
43#define VTD_MMIO_OFF_ECAP_REG 0x010 /**< Extended Capability. */
44#define VTD_MMIO_OFF_GCMD_REG 0x018 /**< Global Command. */
45#define VTD_MMIO_OFF_GSTS_REG 0x01c /**< Global Status. */
46#define VTD_MMIO_OFF_RTADDR_REG 0x020 /**< Root Table Address. */
47#define VTD_MMIO_OFF_CCMD_REG 0x028 /**< Context Command. */
48
49#define VTD_MMIO_OFF_FSTS_REG 0x034 /**< Fault Status.*/
50#define VTD_MMIO_OFF_FECTL_REG 0x038 /**< Fault Event Control.*/
51#define VTD_MMIO_OFF_FEDATA_REG 0x03c /**< Fault Event Data. */
52#define VTD_MMIO_OFF_FEADDR_REG 0x040 /**< Fault Event Address. */
53#define VTD_MMIO_OFF_FEUADDR_REG 0x044 /**< Fault Event Upper Address. */
54
55#define VTD_MMIO_OFF_AFLOG_REG 0x058 /**< Advance Fault Log. */
56
57#define VTD_MMIO_OFF_PMEN_REG 0x064 /**< Protected Memory Enable (PMEN). */
58#define VTD_MMIO_OFF_PLMBASE_REG 0x068 /**< Protected Low Memory Base. */
59#define VTD_MMIO_OFF_PLMLIMIT_REG 0x06c /**< Protected Low Memory Limit. */
60#define VTD_MMIO_OFF_PHMBASE_REG 0x070 /**< Protected High Memory Base. */
61#define VTD_MMIO_OFF_PHMLIMIT_REG 0x078 /**< Protected High Memory Limit. */
62
63#define VTD_MMIO_OFF_IQH_REG 0x080 /**< Invalidation Queue Head. */
64#define VTD_MMIO_OFF_IQT_REG 0x088 /**< Invalidation Queue Tail. */
65#define VTD_MMIO_OFF_IQA_REG 0x090 /**< Invalidation Queue Address. */
66#define VTD_MMIO_OFF_ICS_REG 0x09c /**< Invalidation Completion Status. */
67#define VTD_MMIO_OFF_IECTL_REG 0x0a0 /**< Invalidation Completion Event Control. */
68#define VTD_MMIO_OFF_IEDATA_REG 0x0a4 /**< Invalidation Completion Event Data. */
69#define VTD_MMIO_OFF_IEADDR_REG 0x0a8 /**< Invalidation Completion Event Address. */
70#define VTD_MMIO_OFF_IEUADDR_REG 0x0ac /**< Invalidation Completion Event Upper Address. */
71#define VTD_MMIO_OFF_IQERCD_REG 0x0b0 /**< Invalidation Queue Error Record. */
72
73#define VTD_MMIO_OFF_IRTA_REG 0x0b8 /**< Interrupt Remapping Table Address. */
74
75#define VTD_MMIO_OFF_PQH_REG 0x0c0 /**< Page Request Queue Head. */
76#define VTD_MMIO_OFF_PQT_REG 0x0c8 /**< Page Request Queue Tail. */
77#define VTD_MMIO_OFF_PQA_REG 0x0d0 /**< Page Request Queue Address. */
78#define VTD_MMIO_OFF_PRS_REG 0x0dc /**< Page Request Status. */
79#define VTD_MMIO_OFF_PECTL_REG 0x0e0 /**< Page Request Event Control. */
80#define VTD_MMIO_OFF_PEDATA_REG 0x0e4 /**< Page Request Event Data. */
81#define VTD_MMIO_OFF_PEADDR_REG 0x0e8 /**< Page Request Event Address. */
82#define VTD_MMIO_OFF_PEUADDR_REG 0x0ec /**< Page Request Event Upper Address. */
83
84#define VTD_MMIO_OFF_MTRRCAP_REG 0x100 /**< MTRR Capabliity. */
85#define VTD_MMIO_OFF_MTRRDEF_REG 0x108 /**< MTRR Default Type. */
86
87#define VTD_MMIO_OFF_MTRR_FIX64_00000_REG 0x120 /**< Fixed-range MTRR Register for 64K at 00000. */
88#define VTD_MMIO_OFF_MTRR_FIX16K_80000_REG 0x128 /**< Fixed-range MTRR Register for 16K at 80000. */
89#define VTD_MMIO_OFF_MTRR_FIX16K_A0000_REG 0x130 /**< Fixed-range MTRR Register for 16K at a0000. */
90#define VTD_MMIO_OFF_MTRR_FIX4K_C0000_REG 0x138 /**< Fixed-range MTRR Register for 4K at c0000. */
91#define VTD_MMIO_OFF_MTRR_FIX4K_C8000_REG 0x140 /**< Fixed-range MTRR Register for 4K at c8000. */
92#define VTD_MMIO_OFF_MTRR_FIX4K_D0000_REG 0x148 /**< Fixed-range MTRR Register for 4K at d0000. */
93#define VTD_MMIO_OFF_MTRR_FIX4K_D8000_REG 0x150 /**< Fixed-range MTRR Register for 4K at d8000. */
94#define VTD_MMIO_OFF_MTRR_FIX4K_E0000_REG 0x158 /**< Fixed-range MTRR Register for 4K at e0000. */
95#define VTD_MMIO_OFF_MTRR_FIX4K_E8000_REG 0x160 /**< Fixed-range MTRR Register for 4K at e8000. */
96#define VTD_MMIO_OFF_MTRR_FIX4K_F0000_REG 0x168 /**< Fixed-range MTRR Register for 4K at f0000. */
97#define VTD_MMIO_OFF_MTRR_FIX4K_F8000_REG 0x170 /**< Fixed-range MTRR Register for 4K at f8000. */
98
99#define VTD_MMIO_OFF_MTRR_PHYSBASE0_REG 0x180 /**< Variable-range MTRR Base 0. */
100#define VTD_MMIO_OFF_MTRR_PHYSMASK0_REG 0x188 /**< Variable-range MTRR Mask 0. */
101#define VTD_MMIO_OFF_MTRR_PHYSBASE1_REG 0x190 /**< Variable-range MTRR Base 1. */
102#define VTD_MMIO_OFF_MTRR_PHYSMASK1_REG 0x198 /**< Variable-range MTRR Mask 1. */
103#define VTD_MMIO_OFF_MTRR_PHYSBASE2_REG 0x1a0 /**< Variable-range MTRR Base 2. */
104#define VTD_MMIO_OFF_MTRR_PHYSMASK2_REG 0x1a8 /**< Variable-range MTRR Mask 2. */
105#define VTD_MMIO_OFF_MTRR_PHYSBASE3_REG 0x1b0 /**< Variable-range MTRR Base 3. */
106#define VTD_MMIO_OFF_MTRR_PHYSMASK3_REG 0x1b8 /**< Variable-range MTRR Mask 3. */
107#define VTD_MMIO_OFF_MTRR_PHYSBASE4_REG 0x1c0 /**< Variable-range MTRR Base 4. */
108#define VTD_MMIO_OFF_MTRR_PHYSMASK4_REG 0x1c8 /**< Variable-range MTRR Mask 4. */
109#define VTD_MMIO_OFF_MTRR_PHYSBASE5_REG 0x1d0 /**< Variable-range MTRR Base 5. */
110#define VTD_MMIO_OFF_MTRR_PHYSMASK5_REG 0x1d8 /**< Variable-range MTRR Mask 5. */
111#define VTD_MMIO_OFF_MTRR_PHYSBASE6_REG 0x1e0 /**< Variable-range MTRR Base 6. */
112#define VTD_MMIO_OFF_MTRR_PHYSMASK6_REG 0x1e8 /**< Variable-range MTRR Mask 6. */
113#define VTD_MMIO_OFF_MTRR_PHYSBASE7_REG 0x1f0 /**< Variable-range MTRR Base 7. */
114#define VTD_MMIO_OFF_MTRR_PHYSMASK7_REG 0x1f8 /**< Variable-range MTRR Mask 7. */
115#define VTD_MMIO_OFF_MTRR_PHYSBASE8_REG 0x200 /**< Variable-range MTRR Base 8. */
116#define VTD_MMIO_OFF_MTRR_PHYSMASK8_REG 0x208 /**< Variable-range MTRR Mask 8. */
117#define VTD_MMIO_OFF_MTRR_PHYSBASE9_REG 0x210 /**< Variable-range MTRR Base 9. */
118#define VTD_MMIO_OFF_MTRR_PHYSMASK9_REG 0x218 /**< Variable-range MTRR Mask 9. */
119
120#define VTD_MMIO_OFF_VCCAP_REG 0xe00 /**< Virtual Command Capability. */
121#define VTD_MMIO_OFF_VCMD_REG 0xe10 /**< Virtual Command. */
122#define VTD_MMIO_OFF_VCMDRSVD_REG 0xe18 /**< Reserved for future for Virtual Command. */
123#define VTD_MMIO_OFF_VCRSP_REG 0xe20 /**< Virtual Command Response. */
124#define VTD_MMIO_OFF_VCRSPRSVD_REG 0xe28 /**< Reserved for future for Virtual Command Response. */
125/** @} */
126
127
128/** @name Root Entry.
129 * In accordance with the Intel spec.
130 * @{ */
131/** P: Present. */
132#define VTD_BF_0_ROOT_ENTRY_P_SHIFT 0
133#define VTD_BF_0_ROOT_ENTRY_P_MASK UINT64_C(0x0000000000000001)
134/** R: Reserved (bits 11:1). */
135#define VTD_BF_0_ROOT_ENTRY_RSVD_11_1_SHIFT 1
136#define VTD_BF_0_ROOT_ENTRY_RSVD_11_1_MASK UINT64_C(0x0000000000000ffe)
137/** CTP: Context-Table Pointer. */
138#define VTD_BF_0_ROOT_ENTRY_CTP_SHIFT 12
139#define VTD_BF_0_ROOT_ENTRY_CTP_MASK UINT64_C(0xfffffffffffff000)
140RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_ROOT_ENTRY_, UINT64_C(0), UINT64_MAX,
141 (P, RSVD_11_1, CTP));
142
143/** Root Entry. */
144typedef struct VTD_ROOT_ENTRY_T
145{
146 /** The qwords in the root entry. */
147 uint64_t au64[2];
148} VTD_ROOT_ENTRY_T;
149/** Pointer to a root entry. */
150typedef VTD_ROOT_ENTRY_T *PVTD_ROOT_ENTRY_T;
151/** Pointer to a const root entry. */
152typedef VTD_ROOT_ENTRY_T const *PCVTD_ROOT_ENTRY_T;
153
154/* Root Entry: Qword 0 valid mask. */
155#define VTD_ROOT_ENTRY_0_VALID_MASK (VTD_BF_0_ROOT_ENTRY_P_MASK | VTD_BF_0_ROOT_ENTRY_CTP_MASK)
156/* Root Entry: Qword 1 valid mask. */
157#define VTD_ROOT_ENTRY_1_VALID_MASK UINT64_C(0)
158/** @} */
159
160
161/** @name Scalable-mode Root Entry.
162 * In accordance with the Intel spec.
163 * @{ */
164/** LP: Lower Present. */
165#define VTD_BF_0_SM_ROOT_ENTRY_LP_SHIFT 0
166#define VTD_BF_0_SM_ROOT_ENTRY_LP_MASK UINT64_C(0x0000000000000001)
167/** R: Reserved (bits 11:1). */
168#define VTD_BF_0_SM_ROOT_ENTRY_RSVD_11_1_SHIFT 1
169#define VTD_BF_0_SM_ROOT_ENTRY_RSVD_11_1_MASK UINT64_C(0x0000000000000ffe)
170/** LCTP: Lower Context-Table Pointer */
171#define VTD_BF_0_SM_ROOT_ENTRY_LCTP_SHIFT 12
172#define VTD_BF_0_SM_ROOT_ENTRY_LCTP_MASK UINT64_C(0xfffffffffffff000)
173RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_SM_ROOT_ENTRY_, UINT64_C(0), UINT64_MAX,
174 (LP, RSVD_11_1, LCTP));
175
176/** UP: Upper Present. */
177#define VTD_BF_1_SM_ROOT_ENTRY_UP_SHIFT 0
178#define VTD_BF_1_SM_ROOT_ENTRY_UP_MASK UINT64_C(0x0000000000000001)
179/** R: Reserved (bits 11:1). */
180#define VTD_BF_1_SM_ROOT_ENTRY_RSVD_11_1_SHIFT 1
181#define VTD_BF_1_SM_ROOT_ENTRY_RSVD_11_1_MASK UINT64_C(0x0000000000000ffe)
182/** UCTP: Upper Context-Table Pointer. */
183#define VTD_BF_1_SM_ROOT_ENTRY_UCTP_SHIFT 12
184#define VTD_BF_1_SM_ROOT_ENTRY_UCTP_MASK UINT64_C(0xfffffffffffff000)
185RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_SM_ROOT_ENTRY_, UINT64_C(0), UINT64_MAX,
186 (UP, RSVD_11_1, UCTP));
187
188/** Scalable-mode root entry. */
189typedef struct VTD_SM_ROOT_ENTRY_T
190{
191 /** The lower scalable-mode root entry. */
192 uint64_t uLower;
193 /** The upper scalable-mode root entry. */
194 uint64_t uUpper;
195} VTD_SM_ROOT_ENTRY_T;
196/** Pointer to a scalable-mode root entry. */
197typedef VTD_SM_ROOT_ENTRY_T *PVTD_SM_ROOT_ENTRY_T;
198/** Pointer to a const scalable-mode root entry. */
199typedef VTD_SM_ROOT_ENTRY_T const *PCVTD_SM_ROOT_ENTRY_T;
200/** @} */
201
202
203/** @name Context Entry.
204 * In accordance with the Intel spec.
205 * @{ */
206/** P: Present. */
207#define VTD_BF_0_CONTEXT_ENTRY_P_SHIFT 0
208#define VTD_BF_0_CONTEXT_ENTRY_P_MASK UINT64_C(0x0000000000000001)
209/** FPD: Fault Processing Disable. */
210#define VTD_BF_0_CONTEXT_ENTRY_FPD_SHIFT 1
211#define VTD_BF_0_CONTEXT_ENTRY_FPD_MASK UINT64_C(0x0000000000000002)
212/** TT: Translation Type. */
213#define VTD_BF_0_CONTEXT_ENTRY_TT_SHIFT 2
214#define VTD_BF_0_CONTEXT_ENTRY_TT_MASK UINT64_C(0x000000000000000c)
215/** R: Reserved (bits 11:4). */
216#define VTD_BF_0_CONTEXT_ENTRY_RSVD_11_4_SHIFT 4
217#define VTD_BF_0_CONTEXT_ENTRY_RSVD_11_4_MASK UINT64_C(0x0000000000000ff0)
218/** SLPTPTR: Second Level Page Translation Pointer. */
219#define VTD_BF_0_CONTEXT_ENTRY_SLPTPTR_SHIFT 12
220#define VTD_BF_0_CONTEXT_ENTRY_SLPTPTR_MASK UINT64_C(0xfffffffffffff000)
221RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_CONTEXT_ENTRY_, UINT64_C(0), UINT64_MAX,
222 (P, FPD, TT, RSVD_11_4, SLPTPTR));
223
224/** AW: Address Width. */
225#define VTD_BF_1_CONTEXT_ENTRY_AW_SHIFT 0
226#define VTD_BF_1_CONTEXT_ENTRY_AW_MASK UINT64_C(0x0000000000000007)
227/** IGN: Ignored (bits 6:3). */
228#define VTD_BF_1_CONTEXT_ENTRY_IGN_6_3_SHIFT 3
229#define VTD_BF_1_CONTEXT_ENTRY_IGN_6_3_MASK UINT64_C(0x0000000000000078)
230/** R: Reserved (bit 7). */
231#define VTD_BF_1_CONTEXT_ENTRY_RSVD_7_SHIFT 7
232#define VTD_BF_1_CONTEXT_ENTRY_RSVD_7_MASK UINT64_C(0x0000000000000080)
233/** DID: Domain Identifier. */
234#define VTD_BF_1_CONTEXT_ENTRY_DID_SHIFT 8
235#define VTD_BF_1_CONTEXT_ENTRY_DID_MASK UINT64_C(0x0000000000ffff00)
236/** R: Reserved (bits 63:24). */
237#define VTD_BF_1_CONTEXT_ENTRY_RSVD_63_24_SHIFT 24
238#define VTD_BF_1_CONTEXT_ENTRY_RSVD_63_24_MASK UINT64_C(0xffffffffff000000)
239RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_CONTEXT_ENTRY_, UINT64_C(0), UINT64_MAX,
240 (AW, IGN_6_3, RSVD_7, DID, RSVD_63_24));
241
242/** Context Entry. */
243typedef struct VTD_CONTEXT_ENTRY_T
244{
245 /** The qwords in the context entry. */
246 uint64_t au64[2];
247} VTD_CONTEXT_ENTRY_T;
248/** Pointer to a context entry. */
249typedef VTD_CONTEXT_ENTRY_T *PVTD_CONTEXT_ENTRY_T;
250/** Pointer to a const context entry. */
251typedef VTD_CONTEXT_ENTRY_T const *PCVTD_CONTEXT_ENTRY_T;
252
253/** Context Entry: Qword 0 valid mask. */
254#define VTD_CONTEXT_ENTRY_0_VALID_MASK ( VTD_BF_0_CONTEXT_ENTRY_P_MASK \
255 | VTD_BF_0_CONTEXT_ENTRY_FPD_MASK \
256 | VTD_BF_0_CONTEXT_ENTRY_TT_MASK \
257 | VTD_BF_0_CONTEXT_ENTRY_SLPTPTR_MASK)
258/** Context Entry: Qword 1 valid mask. */
259#define VTD_CONTEXT_ENTRY_1_VALID_MASK ( VTD_BF_1_CONTEXT_ENTRY_AW_MASK \
260 | VTD_BF_1_CONTEXT_ENTRY_IGN_6_3_MASK \
261 | VTD_BF_1_CONTEXT_ENTRY_DID_MASK)
262
263/** Translation Type: Untranslated requests uses second-level paging. */
264#define VTD_TT_UNTRANSLATED_SLP 0
265/** Translation Type: Untranslated requests requires device-TLB support. */
266#define VTD_TT_UNTRANSLATED_DEV_TLB 1
267/** Translation Type: Untranslated requests are pass-through. */
268#define VTD_TT_UNTRANSLATED_PT 2
269/** Translation Type: Reserved. */
270#define VTD_TT_RSVD 3
271/** @} */
272
273
274/** @name Scalable-mode Context Entry.
275 * In accordance with the Intel spec.
276 * @{ */
277/** P: Present. */
278#define VTD_BF_0_SM_CONTEXT_ENTRY_P_SHIFT 0
279#define VTD_BF_0_SM_CONTEXT_ENTRY_P_MASK UINT64_C(0x0000000000000001)
280/** FPD: Fault Processing Disable. */
281#define VTD_BF_0_SM_CONTEXT_ENTRY_FPD_SHIFT 1
282#define VTD_BF_0_SM_CONTEXT_ENTRY_FPD_MASK UINT64_C(0x0000000000000002)
283/** DTE: Device-TLB Enable. */
284#define VTD_BF_0_SM_CONTEXT_ENTRY_DTE_SHIFT 2
285#define VTD_BF_0_SM_CONTEXT_ENTRY_DTE_MASK UINT64_C(0x0000000000000004)
286/** PASIDE: PASID Enable. */
287#define VTD_BF_0_SM_CONTEXT_ENTRY_PASIDE_SHIFT 3
288#define VTD_BF_0_SM_CONTEXT_ENTRY_PASIDE_MASK UINT64_C(0x0000000000000008)
289/** PRE: Page Request Enable. */
290#define VTD_BF_0_SM_CONTEXT_ENTRY_PRE_SHIFT 4
291#define VTD_BF_0_SM_CONTEXT_ENTRY_PRE_MASK UINT64_C(0x0000000000000010)
292/** R: Reserved (bits 8:5). */
293#define VTD_BF_0_SM_CONTEXT_ENTRY_RSVD_8_5_SHIFT 5
294#define VTD_BF_0_SM_CONTEXT_ENTRY_RSVD_8_5_MASK UINT64_C(0x00000000000001e0)
295/** PDTS: PASID Directory Size. */
296#define VTD_BF_0_SM_CONTEXT_ENTRY_PDTS_SHIFT 9
297#define VTD_BF_0_SM_CONTEXT_ENTRY_PDTS_MASK UINT64_C(0x0000000000000e00)
298/** PASIDDIRPTR: PASID Directory Pointer. */
299#define VTD_BF_0_SM_CONTEXT_ENTRY_PASIDDIRPTR_SHIFT 12
300#define VTD_BF_0_SM_CONTEXT_ENTRY_PASIDDIRPTR_MASK UINT64_C(0xfffffffffffff000)
301RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_SM_CONTEXT_ENTRY_, UINT64_C(0), UINT64_MAX,
302 (P, FPD, DTE, PASIDE, PRE, RSVD_8_5, PDTS, PASIDDIRPTR));
303
304/** RID_PASID: Requested Id to PASID assignment. */
305#define VTD_BF_1_SM_CONTEXT_ENTRY_RID_PASID_SHIFT 0
306#define VTD_BF_1_SM_CONTEXT_ENTRY_RID_PASID_MASK UINT64_C(0x00000000000fffff)
307/** RID_PRIV: Requested Id to PrivilegeModeRequested assignment. */
308#define VTD_BF_1_SM_CONTEXT_ENTRY_RID_PRIV_SHIFT 20
309#define VTD_BF_1_SM_CONTEXT_ENTRY_RID_PRIV_MASK UINT64_C(0x0000000000100000)
310/** R: Reserved (bits 63:21). */
311#define VTD_BF_1_SM_CONTEXT_ENTRY_RSVD_63_21_SHIFT 21
312#define VTD_BF_1_SM_CONTEXT_ENTRY_RSVD_63_21_MASK UINT64_C(0xffffffffffe00000)
313RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_SM_CONTEXT_ENTRY_, UINT64_C(0), UINT64_MAX,
314 (RID_PASID, RID_PRIV, RSVD_63_21));
315
316/** Scalable-mode Context Entry. */
317typedef struct VTD_SM_CONTEXT_ENTRY_T
318{
319 /** The qwords in the scalable-mode context entry. */
320 uint64_t au64[4];
321} VTD_SM_CONTEXT_ENTRY_T;
322/** Pointer to a scalable-mode context entry. */
323typedef VTD_SM_CONTEXT_ENTRY_T *PVTD_SM_CONTEXT_ENTRY_T;
324/** Pointer to a const scalable-mode context entry. */
325typedef VTD_SM_CONTEXT_ENTRY_T const *PCVTD_SM_CONTEXT_ENTRY_T;
326/** @} */
327
328
329/** @name Scalable-mode PASID Directory Entry.
330 * In accordance with the Intel spec.
331 * @{ */
332/** P: Present. */
333#define VTD_BF_SM_PASID_DIR_ENTRY_P_SHIFT 0
334#define VTD_BF_SM_PASID_DIR_ENTRY_P_MASK UINT64_C(0x0000000000000001)
335/** FPD: Fault Processing Disable. */
336#define VTD_BF_SM_PASID_DIR_ENTRY_FPD_SHIFT 1
337#define VTD_BF_SM_PASID_DIR_ENTRY_FPD_MASK UINT64_C(0x0000000000000002)
338/** R: Reserved (bits 11:2). */
339#define VTD_BF_SM_PASID_DIR_ENTRY_RSVD_11_2_SHIFT 2
340#define VTD_BF_SM_PASID_DIR_ENTRY_RSVD_11_2_MASK UINT64_C(0x0000000000000ffc)
341/** SMPTBLPTR: Scalable Mode PASID Table Pointer. */
342#define VTD_BF_SM_PASID_DIR_ENTRY_SMPTBLPTR_SHIFT 12
343#define VTD_BF_SM_PASID_DIR_ENTRY_SMPTBLPTR_MASK UINT64_C(0xfffffffffffff000)
344RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_SM_PASID_DIR_ENTRY_, UINT64_C(0), UINT64_MAX,
345 (P, FPD, RSVD_11_2, SMPTBLPTR));
346
347/** Scalable-mode PASID Directory Entry. */
348typedef struct VTD_SM_PASID_DIR_ENTRY_T
349{
350 /** The scalable-mode PASID directory entry. */
351 uint64_t u;
352} VTD_SM_PASID_DIR_ENTRY_T;
353/** Pointer to a scalable-mode PASID directory entry. */
354typedef VTD_SM_PASID_DIR_ENTRY_T *PVTD_SM_PASID_DIR_ENTRY_T;
355/** Pointer to a const scalable-mode PASID directory entry. */
356typedef VTD_SM_PASID_DIR_ENTRY_T const *PCVTD_SM_PASID_DIR_ENTRY_T;
357/** @} */
358
359
360/** @name Scalable-mode PASID Table Entry.
361 * In accordance with the Intel spec.
362 * @{ */
363/** P: Present. */
364#define VTD_BF_0_SM_PASID_TBL_ENTRY_P_SHIFT 0
365#define VTD_BF_0_SM_PASID_TBL_ENTRY_P_MASK UINT64_C(0x0000000000000001)
366/** FPD: Fault Processing Disable. */
367#define VTD_BF_0_SM_PASID_TBL_ENTRY_FPD_SHIFT 1
368#define VTD_BF_0_SM_PASID_TBL_ENTRY_FPD_MASK UINT64_C(0x0000000000000002)
369/** AW: Address Width. */
370#define VTD_BF_0_SM_PASID_TBL_ENTRY_AW_SHIFT 2
371#define VTD_BF_0_SM_PASID_TBL_ENTRY_AW_MASK UINT64_C(0x000000000000001c)
372/** SLEE: Second-Level Execute Enable. */
373#define VTD_BF_0_SM_PASID_TBL_ENTRY_SLEE_SHIFT 5
374#define VTD_BF_0_SM_PASID_TBL_ENTRY_SLEE_MASK UINT64_C(0x0000000000000020)
375/** PGTT: PASID Granular Translation Type. */
376#define VTD_BF_0_SM_PASID_TBL_ENTRY_PGTT_SHIFT 6
377#define VTD_BF_0_SM_PASID_TBL_ENTRY_PGTT_MASK UINT64_C(0x00000000000001c0)
378/** SLADE: Second-Level Address/Dirty Enable. */
379#define VTD_BF_0_SM_PASID_TBL_ENTRY_SLADE_SHIFT 9
380#define VTD_BF_0_SM_PASID_TBL_ENTRY_SLADE_MASK UINT64_C(0x0000000000000200)
381/** R: Reserved (bits 11:10). */
382#define VTD_BF_0_SM_PASID_TBL_ENTRY_RSVD_11_10_SHIFT 10
383#define VTD_BF_0_SM_PASID_TBL_ENTRY_RSVD_11_10_MASK UINT64_C(0x0000000000000c00)
384/** SLPTPTR: Second-Level Page Table Pointer. */
385#define VTD_BF_0_SM_PASID_TBL_ENTRY_SLPTPTR_SHIFT 12
386#define VTD_BF_0_SM_PASID_TBL_ENTRY_SLPTPTR_MASK UINT64_C(0xfffffffffffff000)
387RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_SM_PASID_TBL_ENTRY_, UINT64_C(0), UINT64_MAX,
388 (P, FPD, AW, SLEE, PGTT, SLADE, RSVD_11_10, SLPTPTR));
389
390/** DID: Domain Identifer. */
391#define VTD_BF_1_SM_PASID_TBL_ENTRY_DID_SHIFT 0
392#define VTD_BF_1_SM_PASID_TBL_ENTRY_DID_MASK UINT64_C(0x000000000000ffff)
393/** R: Reserved (bits 22:16). */
394#define VTD_BF_1_SM_PASID_TBL_ENTRY_RSVD_22_16_SHIFT 16
395#define VTD_BF_1_SM_PASID_TBL_ENTRY_RSVD_22_16_MASK UINT64_C(0x00000000007f0000)
396/** PWSNP: Page-Walk Snoop. */
397#define VTD_BF_1_SM_PASID_TBL_ENTRY_PWSNP_SHIFT 23
398#define VTD_BF_1_SM_PASID_TBL_ENTRY_PWSNP_MASK UINT64_C(0x0000000000800000)
399/** PGSNP: Page Snoop. */
400#define VTD_BF_1_SM_PASID_TBL_ENTRY_PGSNP_SHIFT 24
401#define VTD_BF_1_SM_PASID_TBL_ENTRY_PGSNP_MASK UINT64_C(0x0000000001000000)
402/** CD: Cache Disable. */
403#define VTD_BF_1_SM_PASID_TBL_ENTRY_CD_SHIFT 25
404#define VTD_BF_1_SM_PASID_TBL_ENTRY_CD_MASK UINT64_C(0x0000000002000000)
405/** EMTE: Extended Memory Type Enable. */
406#define VTD_BF_1_SM_PASID_TBL_ENTRY_EMTE_SHIFT 26
407#define VTD_BF_1_SM_PASID_TBL_ENTRY_EMTE_MASK UINT64_C(0x0000000004000000)
408/** EMT: Extended Memory Type. */
409#define VTD_BF_1_SM_PASID_TBL_ENTRY_EMT_SHIFT 27
410#define VTD_BF_1_SM_PASID_TBL_ENTRY_EMT_MASK UINT64_C(0x0000000038000000)
411/** PWT: Page-Level Write Through. */
412#define VTD_BF_1_SM_PASID_TBL_ENTRY_PWT_SHIFT 30
413#define VTD_BF_1_SM_PASID_TBL_ENTRY_PWT_MASK UINT64_C(0x0000000040000000)
414/** PCD: Page-Level Cache Disable. */
415#define VTD_BF_1_SM_PASID_TBL_ENTRY_PCD_SHIFT 31
416#define VTD_BF_1_SM_PASID_TBL_ENTRY_PCD_MASK UINT64_C(0x0000000080000000)
417/** PAT: Page Attribute Table. */
418#define VTD_BF_1_SM_PASID_TBL_ENTRY_PAT_SHIFT 32
419#define VTD_BF_1_SM_PASID_TBL_ENTRY_PAT_MASK UINT64_C(0xffffffff00000000)
420RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_SM_PASID_TBL_ENTRY_, UINT64_C(0), UINT64_MAX,
421 (DID, RSVD_22_16, PWSNP, PGSNP, CD, EMTE, EMT, PWT, PCD, PAT));
422
423/** SRE: Supervisor Request Enable. */
424#define VTD_BF_2_SM_PASID_TBL_ENTRY_SRE_SHIFT 0
425#define VTD_BF_2_SM_PASID_TBL_ENTRY_SRE_MASK UINT64_C(0x0000000000000001)
426/** ERE: Execute Request Enable. */
427#define VTD_BF_2_SM_PASID_TBL_ENTRY_ERE_SHIFT 1
428#define VTD_BF_2_SM_PASID_TBL_ENTRY_ERE_MASK UINT64_C(0x0000000000000002)
429/** FLPM: First Level Paging Mode. */
430#define VTD_BF_2_SM_PASID_TBL_ENTRY_FLPM_SHIFT 2
431#define VTD_BF_2_SM_PASID_TBL_ENTRY_FLPM_MASK UINT64_C(0x000000000000000c)
432/** WPE: Write Protect Enable. */
433#define VTD_BF_2_SM_PASID_TBL_ENTRY_WPE_SHIFT 4
434#define VTD_BF_2_SM_PASID_TBL_ENTRY_WPE_MASK UINT64_C(0x0000000000000010)
435/** NXE: No-Execute Enable. */
436#define VTD_BF_2_SM_PASID_TBL_ENTRY_NXE_SHIFT 5
437#define VTD_BF_2_SM_PASID_TBL_ENTRY_NXE_MASK UINT64_C(0x0000000000000020)
438/** SMEP: Supervisor Mode Execute Prevent. */
439#define VTD_BF_2_SM_PASID_TBL_ENTRY_SMPE_SHIFT 6
440#define VTD_BF_2_SM_PASID_TBL_ENTRY_SMPE_MASK UINT64_C(0x0000000000000040)
441/** EAFE: Extended Accessed Flag Enable. */
442#define VTD_BF_2_SM_PASID_TBL_ENTRY_EAFE_SHIFT 7
443#define VTD_BF_2_SM_PASID_TBL_ENTRY_EAFE_MASK UINT64_C(0x0000000000000080)
444/** R: Reserved (bits 11:8). */
445#define VTD_BF_2_SM_PASID_TBL_ENTRY_RSVD_11_8_SHIFT 8
446#define VTD_BF_2_SM_PASID_TBL_ENTRY_RSVD_11_8_MASK UINT64_C(0x0000000000000f00)
447/** FLPTPTR: First Level Page Table Pointer. */
448#define VTD_BF_2_SM_PASID_TBL_ENTRY_FLPTPTR_SHIFT 12
449#define VTD_BF_2_SM_PASID_TBL_ENTRY_FLPTPTR_MASK UINT64_C(0xfffffffffffff000)
450RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_2_SM_PASID_TBL_ENTRY_, UINT64_C(0), UINT64_MAX,
451 (SRE, ERE, FLPM, WPE, NXE, SMPE, EAFE, RSVD_11_8, FLPTPTR));
452
453/** Scalable-mode PASID Table Entry. */
454typedef struct VTD_SM_PASID_TBL_ENTRY_T
455{
456 /** The qwords in the scalable-mode PASID table entry. */
457 uint64_t au64[8];
458} VTD_SM_PASID_TBL_ENTRY_T;
459/** Pointer to a scalable-mode PASID table entry. */
460typedef VTD_SM_PASID_TBL_ENTRY_T *PVTD_SM_PASID_TBL_ENTRY_T;
461/** Pointer to a const scalable-mode PASID table entry. */
462typedef VTD_SM_PASID_TBL_ENTRY_T const *PCVTD_SM_PASID_TBL_ENTRY_T;
463/** @} */
464
465
466/** @name First-Level Paging Entry.
467 * In accordance with the Intel spec.
468 * @{ */
469/** P: Present. */
470#define VTD_BF_FLP_ENTRY_P_SHIFT 0
471#define VTD_BF_FLP_ENTRY_P_MASK UINT64_C(0x0000000000000001)
472/** R/W: Read/Write. */
473#define VTD_BF_FLP_ENTRY_RW_SHIFT 1
474#define VTD_BF_FLP_ENTRY_RW_MASK UINT64_C(0x0000000000000002)
475/** U/S: User/Supervisor. */
476#define VTD_BF_FLP_ENTRY_US_SHIFT 2
477#define VTD_BF_FLP_ENTRY_US_MASK UINT64_C(0x0000000000000004)
478/** PWT: Page-Level Write Through. */
479#define VTD_BF_FLP_ENTRY_PWT_SHIFT 3
480#define VTD_BF_FLP_ENTRY_PWT_MASK UINT64_C(0x0000000000000008)
481/** PC: Page-Level Cache Disable. */
482#define VTD_BF_FLP_ENTRY_PCD_SHIFT 4
483#define VTD_BF_FLP_ENTRY_PCD_MASK UINT64_C(0x0000000000000010)
484/** A: Accessed. */
485#define VTD_BF_FLP_ENTRY_A_SHIFT 5
486#define VTD_BF_FLP_ENTRY_A_MASK UINT64_C(0x0000000000000020)
487/** IGN: Ignored (bit 6). */
488#define VTD_BF_FLP_ENTRY_IGN_6_SHIFT 6
489#define VTD_BF_FLP_ENTRY_IGN_6_MASK UINT64_C(0x0000000000000040)
490/** R: Reserved (bit 7). */
491#define VTD_BF_FLP_ENTRY_RSVD_7_SHIFT 7
492#define VTD_BF_FLP_ENTRY_RSVD_7_MASK UINT64_C(0x0000000000000080)
493/** IGN: Ignored (bits 9:8). */
494#define VTD_BF_FLP_ENTRY_IGN_9_8_SHIFT 8
495#define VTD_BF_FLP_ENTRY_IGN_9_8_MASK UINT64_C(0x0000000000000300)
496/** EA: Extended Accessed. */
497#define VTD_BF_FLP_ENTRY_EA_SHIFT 10
498#define VTD_BF_FLP_ENTRY_EA_MASK UINT64_C(0x0000000000000400)
499/** IGN: Ignored (bit 11). */
500#define VTD_BF_FLP_ENTRY_IGN_11_SHIFT 11
501#define VTD_BF_FLP_ENTRY_IGN_11_MASK UINT64_C(0x0000000000000800)
502/** ADDR: Address. */
503#define VTD_BF_FLP_ENTRY_ADDR_SHIFT 12
504#define VTD_BF_FLP_ENTRY_ADDR_MASK UINT64_C(0x000ffffffffff000)
505/** IGN: Ignored (bits 62:52). */
506#define VTD_BF_FLP_ENTRY_IGN_62_52_SHIFT 52
507#define VTD_BF_FLP_ENTRY_IGN_62_52_MASK UINT64_C(0x7ff0000000000000)
508/** XD: Execute Disabled. */
509#define VTD_BF_FLP_ENTRY_XD_SHIFT 63
510#define VTD_BF_FLP_ENTRY_XD_MASK UINT64_C(0x8000000000000000)
511RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_FLP_ENTRY_, UINT64_C(0), UINT64_MAX,
512 (P, RW, US, PWT, PCD, A, IGN_6, RSVD_7, IGN_9_8, EA, IGN_11, ADDR, IGN_62_52, XD));
513
514/** First-Level Paging Entry. */
515typedef uint64_t VTD_FLP_ENTRY_T;
516/** @} */
517
518
519/** @name Second-Level Paging Entry.
520 * In accordance with the Intel spec.
521 * @{ */
522/** R: Read. */
523#define VTD_BF_SLP_ENTRY_R_SHIFT 0
524#define VTD_BF_SLP_ENTRY_R_MASK UINT64_C(0x0000000000000001)
525/** W: Write. */
526#define VTD_BF_SLP_ENTRY_W_SHIFT 1
527#define VTD_BF_SLP_ENTRY_W_MASK UINT64_C(0x0000000000000002)
528/** X: Execute. */
529#define VTD_BF_SLP_ENTRY_X_SHIFT 2
530#define VTD_BF_SLP_ENTRY_X_MASK UINT64_C(0x0000000000000004)
531/** IGN: Ignored (bits 6:3). */
532#define VTD_BF_SLP_ENTRY_IGN_6_3_SHIFT 3
533#define VTD_BF_SLP_ENTRY_IGN_6_3_MASK UINT64_C(0x0000000000000078)
534/** R: Reserved (bit 7). */
535#define VTD_BF_SLP_ENTRY_RSVD_7_SHIFT 7
536#define VTD_BF_SLP_ENTRY_RSVD_7_MASK UINT64_C(0x0000000000000080)
537/** A: Accessed. */
538#define VTD_BF_SLP_ENTRY_A_SHIFT 8
539#define VTD_BF_SLP_ENTRY_A_MASK UINT64_C(0x0000000000000100)
540/** IGN: Ignored (bits 10:9). */
541#define VTD_BF_SLP_ENTRY_IGN_10_9_SHIFT 9
542#define VTD_BF_SLP_ENTRY_IGN_10_9_MASK UINT64_C(0x0000000000000600)
543/** R: Reserved (bit 11). */
544#define VTD_BF_SLP_ENTRY_RSVD_11_SHIFT 11
545#define VTD_BF_SLP_ENTRY_RSVD_11_MASK UINT64_C(0x0000000000000800)
546/** ADDR: Address. */
547#define VTD_BF_SLP_ENTRY_ADDR_SHIFT 12
548#define VTD_BF_SLP_ENTRY_ADDR_MASK UINT64_C(0x000ffffffffff000)
549/** IGN: Ignored (bits 61:52). */
550#define VTD_BF_SLP_ENTRY_IGN_61_52_SHIFT 52
551#define VTD_BF_SLP_ENTRY_IGN_61_52_MASK UINT64_C(0x3ff0000000000000)
552/** R: Reserved (bit 62). */
553#define VTD_BF_SLP_ENTRY_RSVD_62_SHIFT 62
554#define VTD_BF_SLP_ENTRY_RSVD_62_MASK UINT64_C(0x4000000000000000)
555/** IGN: Ignored (bit 63). */
556#define VTD_BF_SLP_ENTRY_IGN_63_SHIFT 63
557#define VTD_BF_SLP_ENTRY_IGN_63_MASK UINT64_C(0x8000000000000000)
558RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_SLP_ENTRY_, UINT64_C(0), UINT64_MAX,
559 (R, W, X, IGN_6_3, RSVD_7, A, IGN_10_9, RSVD_11, ADDR, IGN_61_52, RSVD_62, IGN_63));
560
561/** SL-PML5E: Valid mask. */
562#define VTD_SLP_PML5E_VALID_MASK ( VTD_BF_SLP_ENTRY_R_MASK | VTD_BF_SLP_ENTRY_W_MASK \
563 | VTD_BF_SLP_ENTRY_X_MASK | VTD_BF_SLP_ENTRY_IGN_6_3_MASK \
564 | VTD_BF_SLP_ENTRY_A_MASK | VTD_BF_SLP_ENTRY_IGN_10_9_MASK \
565 | VTD_BF_SLP_ENTRY_ADDR_MASK | VTD_BF_SLP_ENTRY_IGN_61_52_MASK \
566 | VTD_BF_SLP_ENTRY_IGN_63_MASK)
567
568/** Second-Level Paging Entry. */
569typedef uint64_t VTD_SLP_ENTRY_T;
570/** Pointer to a second-level paging entry. */
571typedef uint64_t *PVTD_SLP_ENTRY_T;
572/** Pointer to a const second-level paging entry. */
573typedef uint64_t const *CPVTD_SLP_ENTRY_T;
574/** @} */
575
576
577/** @name Fault Record.
578 * In accordance with the Intel spec.
579 * @{ */
580/** R: Reserved (bits 11:0). */
581#define VTD_BF_0_FAULT_RECORD_RSVD_11_0_SHIFT 0
582#define VTD_BF_0_FAULT_RECORD_RSVD_11_0_MASK UINT64_C(0x0000000000000fff)
583/** FI: Fault Information. */
584#define VTD_BF_0_FAULT_RECORD_FI_SHIFT 12
585#define VTD_BF_0_FAULT_RECORD_FI_MASK UINT64_C(0xfffffffffffff000)
586RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_FAULT_RECORD_, UINT64_C(0), UINT64_MAX,
587 (RSVD_11_0, FI));
588
589/** SID: Source identifier. */
590#define VTD_BF_1_FAULT_RECORD_SID_SHIFT 0
591#define VTD_BF_1_FAULT_RECORD_SID_MASK UINT64_C(0x000000000000ffff)
592/** R: Reserved (bits 28:16). */
593#define VTD_BF_1_FAULT_RECORD_RSVD_28_16_SHIFT 16
594#define VTD_BF_1_FAULT_RECORD_RSVD_28_16_MASK UINT64_C(0x000000001fff0000)
595/** PRIV: Privilege Mode Requested. */
596#define VTD_BF_1_FAULT_RECORD_PRIV_SHIFT 29
597#define VTD_BF_1_FAULT_RECORD_PRIV_MASK UINT64_C(0x0000000020000000)
598/** EXE: Execute Permission Requested. */
599#define VTD_BF_1_FAULT_RECORD_EXE_SHIFT 30
600#define VTD_BF_1_FAULT_RECORD_EXE_MASK UINT64_C(0x0000000040000000)
601/** PP: PASID Present. */
602#define VTD_BF_1_FAULT_RECORD_PP_SHIFT 31
603#define VTD_BF_1_FAULT_RECORD_PP_MASK UINT64_C(0x0000000080000000)
604/** FR: Fault Reason. */
605#define VTD_BF_1_FAULT_RECORD_FR_SHIFT 32
606#define VTD_BF_1_FAULT_RECORD_FR_MASK UINT64_C(0x000000ff00000000)
607/** PV: PASID Value. */
608#define VTD_BF_1_FAULT_RECORD_PV_SHIFT 40
609#define VTD_BF_1_FAULT_RECORD_PV_MASK UINT64_C(0x0fffff0000000000)
610/** AT: Address Type. */
611#define VTD_BF_1_FAULT_RECORD_AT_SHIFT 60
612#define VTD_BF_1_FAULT_RECORD_AT_MASK UINT64_C(0x3000000000000000)
613/** T: Type. */
614#define VTD_BF_1_FAULT_RECORD_T_SHIFT 62
615#define VTD_BF_1_FAULT_RECORD_T_MASK UINT64_C(0x4000000000000000)
616/** R: Reserved (bit 127). */
617#define VTD_BF_1_FAULT_RECORD_RSVD_63_SHIFT 63
618#define VTD_BF_1_FAULT_RECORD_RSVD_63_MASK UINT64_C(0x8000000000000000)
619RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_FAULT_RECORD_, UINT64_C(0), UINT64_MAX,
620 (SID, RSVD_28_16, PRIV, EXE, PP, FR, PV, AT, T, RSVD_63));
621
622/** Fault record. */
623typedef struct VTD_FAULT_RECORD_T
624{
625 /** The qwords in the fault record. */
626 uint64_t au64[2];
627} VTD_FAULT_RECORD_T;
628/** Pointer to a fault record. */
629typedef VTD_FAULT_RECORD_T *PVTD_FAULT_RECORD_T;
630/** Pointer to a const fault record. */
631typedef VTD_FAULT_RECORD_T const *PCVTD_FAULT_RECORD_T;
632/** @} */
633
634
635/** @name Interrupt Remapping Table Entry (IRTE) for Remapped Interrupts.
636 * In accordance with the Intel spec.
637 * @{ */
638/** P: Present. */
639#define VTD_BF_0_IRTE_P_SHIFT 0
640#define VTD_BF_0_IRTE_P_MASK UINT64_C(0x0000000000000001)
641/** FPD: Fault Processing Disable. */
642#define VTD_BF_0_IRTE_FPD_SHIFT 1
643#define VTD_BF_0_IRTE_FPD_MASK UINT64_C(0x0000000000000002)
644/** DM: Destination Mode (0=physical, 1=logical). */
645#define VTD_BF_0_IRTE_DM_SHIFT 2
646#define VTD_BF_0_IRTE_DM_MASK UINT64_C(0x0000000000000004)
647/** RH: Redirection Hint. */
648#define VTD_BF_0_IRTE_RH_SHIFT 3
649#define VTD_BF_0_IRTE_RH_MASK UINT64_C(0x0000000000000008)
650/** TM: Trigger Mode. */
651#define VTD_BF_0_IRTE_TM_SHIFT 4
652#define VTD_BF_0_IRTE_TM_MASK UINT64_C(0x0000000000000010)
653/** DLM: Delivery Mode. */
654#define VTD_BF_0_IRTE_DLM_SHIFT 5
655#define VTD_BF_0_IRTE_DLM_MASK UINT64_C(0x00000000000000e0)
656/** AVL: Available. */
657#define VTD_BF_0_IRTE_AVAIL_SHIFT 8
658#define VTD_BF_0_IRTE_AVAIL_MASK UINT64_C(0x0000000000000f00)
659/** R: Reserved (bits 14:12). */
660#define VTD_BF_0_IRTE_RSVD_14_12_SHIFT 12
661#define VTD_BF_0_IRTE_RSVD_14_12_MASK UINT64_C(0x0000000000007000)
662/** IM: IRTE Mode. */
663#define VTD_BF_0_IRTE_IM_SHIFT 15
664#define VTD_BF_0_IRTE_IM_MASK UINT64_C(0x0000000000008000)
665/** V: Vector. */
666#define VTD_BF_0_IRTE_V_SHIFT 16
667#define VTD_BF_0_IRTE_V_MASK UINT64_C(0x0000000000ff0000)
668/** R: Reserved (bits 31:24). */
669#define VTD_BF_0_IRTE_RSVD_31_24_SHIFT 24
670#define VTD_BF_0_IRTE_RSVD_31_24_MASK UINT64_C(0x00000000ff000000)
671/** DST: Desination Id. */
672#define VTD_BF_0_IRTE_DST_SHIFT 32
673#define VTD_BF_0_IRTE_DST_MASK UINT64_C(0xffffffff00000000)
674/** R: Reserved (bits 39:32) when EIME=0. */
675#define VTD_BF_0_IRTE_RSVD_39_32_SHIFT 32
676#define VTD_BF_0_IRTE_RSVD_39_32_MASK UINT64_C(0x000000ff00000000)
677/** DST_XAPIC: Destination Id when EIME=0. */
678#define VTD_BF_0_IRTE_DST_XAPIC_SHIFT 40
679#define VTD_BF_0_IRTE_DST_XAPIC_MASK UINT64_C(0x0000ff0000000000)
680/** R: Reserved (bits 63:48) when EIME=0. */
681#define VTD_BF_0_IRTE_RSVD_63_48_SHIFT 48
682#define VTD_BF_0_IRTE_RSVD_63_48_MASK UINT64_C(0xffff000000000000)
683RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_IRTE_, UINT64_C(0), UINT64_MAX,
684 (P, FPD, DM, RH, TM, DLM, AVAIL, RSVD_14_12, IM, V, RSVD_31_24, DST));
685RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_IRTE_, UINT64_C(0), UINT64_MAX,
686 (P, FPD, DM, RH, TM, DLM, AVAIL, RSVD_14_12, IM, V, RSVD_31_24, RSVD_39_32, DST_XAPIC, RSVD_63_48));
687
688/** SID: Source Identifier. */
689#define VTD_BF_1_IRTE_SID_SHIFT 0
690#define VTD_BF_1_IRTE_SID_MASK UINT64_C(0x000000000000ffff)
691/** SQ: Source-Id Qualifier. */
692#define VTD_BF_1_IRTE_SQ_SHIFT 16
693#define VTD_BF_1_IRTE_SQ_MASK UINT64_C(0x0000000000030000)
694/** SVT: Source Validation Type. */
695#define VTD_BF_1_IRTE_SVT_SHIFT 18
696#define VTD_BF_1_IRTE_SVT_MASK UINT64_C(0x00000000000c0000)
697/** R: Reserved (bits 127:84). */
698#define VTD_BF_1_IRTE_RSVD_63_20_SHIFT 20
699#define VTD_BF_1_IRTE_RSVD_63_20_MASK UINT64_C(0xfffffffffff00000)
700RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_IRTE_, UINT64_C(0), UINT64_MAX,
701 (SID, SQ, SVT, RSVD_63_20));
702
703/** IRTE: Qword 0 valid mask when EIME=1. */
704#define VTD_IRTE_0_X2APIC_VALID_MASK ( VTD_BF_0_IRTE_P_MASK | VTD_BF_0_IRTE_FPD_MASK \
705 | VTD_BF_0_IRTE_DM_MASK | VTD_BF_0_IRTE_RH_MASK \
706 | VTD_BF_0_IRTE_TM_MASK | VTD_BF_0_IRTE_DLM_MASK \
707 | VTD_BF_0_IRTE_AVAIL_MASK | VTD_BF_0_IRTE_IM_MASK \
708 | VTD_BF_0_IRTE_V_MASK | VTD_BF_0_IRTE_DST_MASK)
709/** IRTE: Qword 0 valid mask when EIME=0. */
710#define VTD_IRTE_0_XAPIC_VALID_MASK ( VTD_BF_0_IRTE_P_MASK | VTD_BF_0_IRTE_FPD_MASK \
711 | VTD_BF_0_IRTE_DM_MASK | VTD_BF_0_IRTE_RH_MASK \
712 | VTD_BF_0_IRTE_TM_MASK | VTD_BF_0_IRTE_DLM_MASK \
713 | VTD_BF_0_IRTE_AVAIL_MASK | VTD_BF_0_IRTE_IM_MASK \
714 | VTD_BF_0_IRTE_V_MASK | VTD_BF_0_IRTE_DST_XAPIC_MASK)
715/** IRTE: Qword 1 valid mask. */
716#define VTD_IRTE_1_VALID_MASK ( VTD_BF_1_IRTE_SID_MASK | VTD_BF_1_IRTE_SQ_MASK \
717 | VTD_BF_1_IRTE_SVT_MASK)
718
719/** Interrupt Remapping Table Entry (IRTE) for remapped interrupts. */
720typedef struct VTD_IRTE_T
721{
722 /** The qwords in the IRTE. */
723 uint64_t au64[2];
724} VTD_IRTE_T;
725/** Pointer to an IRTE. */
726typedef VTD_IRTE_T *PVTD_IRTE_T;
727/** Pointer to a const IRTE. */
728typedef VTD_IRTE_T const *PCVTD_IRTE_T;
729
730/** IRTE SVT: No validation required. */
731#define VTD_IRTE_SVT_NONE 0
732/** IRTE SVT: Validate using a mask derived from SID and SQT. */
733#define VTD_IRTE_SVT_VALIDATE_MASK 1
734/** IRTE SVT: Validate using Bus range in the SID. */
735#define VTD_IRTE_SVT_VALIDATE_BUS_RANGE 2
736/** IRTE SVT: Reserved. */
737#define VTD_IRTE_SVT_VALIDATE_RSVD 3
738/** @} */
739
740
741/** @name Version Register (VER_REG).
742 * In accordance with the Intel spec.
743 * @{ */
744/** Min: Minor Version Number. */
745#define VTD_BF_VER_REG_MIN_SHIFT 0
746#define VTD_BF_VER_REG_MIN_MASK UINT32_C(0x0000000f)
747/** Max: Major Version Number. */
748#define VTD_BF_VER_REG_MAX_SHIFT 4
749#define VTD_BF_VER_REG_MAX_MASK UINT32_C(0x000000f0)
750/** R: Reserved (bits 31:8). */
751#define VTD_BF_VER_REG_RSVD_31_8_SHIFT 8
752#define VTD_BF_VER_REG_RSVD_31_8_MASK UINT32_C(0xffffff00)
753RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_VER_REG_, UINT32_C(0), UINT32_MAX,
754 (MIN, MAX, RSVD_31_8));
755/** RW: Read/write mask. */
756#define VTD_VER_REG_RW_MASK UINT32_C(0)
757/** @} */
758
759
760/** @name Capability Register (CAP_REG).
761 * In accordance with the Intel spec.
762 * @{ */
763/** ND: Number of domains supported. */
764#define VTD_BF_CAP_REG_ND_SHIFT 0
765#define VTD_BF_CAP_REG_ND_MASK UINT64_C(0x0000000000000007)
766/** AFL: Advanced Fault Logging. */
767#define VTD_BF_CAP_REG_AFL_SHIFT 3
768#define VTD_BF_CAP_REG_AFL_MASK UINT64_C(0x0000000000000008)
769/** RWBF: Required Write-Buffer Flushing. */
770#define VTD_BF_CAP_REG_RWBF_SHIFT 4
771#define VTD_BF_CAP_REG_RWBF_MASK UINT64_C(0x0000000000000010)
772/** PLMR: Protected Low-Memory Region. */
773#define VTD_BF_CAP_REG_PLMR_SHIFT 5
774#define VTD_BF_CAP_REG_PLMR_MASK UINT64_C(0x0000000000000020)
775/** PHMR: Protected High-Memory Region. */
776#define VTD_BF_CAP_REG_PHMR_SHIFT 6
777#define VTD_BF_CAP_REG_PHMR_MASK UINT64_C(0x0000000000000040)
778/** CM: Caching Mode. */
779#define VTD_BF_CAP_REG_CM_SHIFT 7
780#define VTD_BF_CAP_REG_CM_MASK UINT64_C(0x0000000000000080)
781/** SAGAW: Supported Adjusted Guest Address Widths. */
782#define VTD_BF_CAP_REG_SAGAW_SHIFT 8
783#define VTD_BF_CAP_REG_SAGAW_MASK UINT64_C(0x0000000000001f00)
784/** R: Reserved (bits 15:13). */
785#define VTD_BF_CAP_REG_RSVD_15_13_SHIFT 13
786#define VTD_BF_CAP_REG_RSVD_15_13_MASK UINT64_C(0x000000000000e000)
787/** MGAW: Maximum Guest Address Width. */
788#define VTD_BF_CAP_REG_MGAW_SHIFT 16
789#define VTD_BF_CAP_REG_MGAW_MASK UINT64_C(0x00000000003f0000)
790/** ZLR: Zero Length Read. */
791#define VTD_BF_CAP_REG_ZLR_SHIFT 22
792#define VTD_BF_CAP_REG_ZLR_MASK UINT64_C(0x0000000000400000)
793/** DEP: Deprecated MBZ. Reserved (bit 23). */
794#define VTD_BF_CAP_REG_RSVD_23_SHIFT 23
795#define VTD_BF_CAP_REG_RSVD_23_MASK UINT64_C(0x0000000000800000)
796/** FRO: Fault-recording Register Offset. */
797#define VTD_BF_CAP_REG_FRO_SHIFT 24
798#define VTD_BF_CAP_REG_FRO_MASK UINT64_C(0x00000003ff000000)
799/** SLLPS: Second Level Large Page Support. */
800#define VTD_BF_CAP_REG_SLLPS_SHIFT 34
801#define VTD_BF_CAP_REG_SLLPS_MASK UINT64_C(0x0000003c00000000)
802/** R: Reserved (bit 38). */
803#define VTD_BF_CAP_REG_RSVD_38_SHIFT 38
804#define VTD_BF_CAP_REG_RSVD_38_MASK UINT64_C(0x0000004000000000)
805/** PSI: Page Selective Invalidation. */
806#define VTD_BF_CAP_REG_PSI_SHIFT 39
807#define VTD_BF_CAP_REG_PSI_MASK UINT64_C(0x0000008000000000)
808/** NFR: Number of Fault-recording Registers. */
809#define VTD_BF_CAP_REG_NFR_SHIFT 40
810#define VTD_BF_CAP_REG_NFR_MASK UINT64_C(0x0000ff0000000000)
811/** MAMV: Maximum Address Mask Value. */
812#define VTD_BF_CAP_REG_MAMV_SHIFT 48
813#define VTD_BF_CAP_REG_MAMV_MASK UINT64_C(0x003f000000000000)
814/** DWD: Write Draining. */
815#define VTD_BF_CAP_REG_DWD_SHIFT 54
816#define VTD_BF_CAP_REG_DWD_MASK UINT64_C(0x0040000000000000)
817/** DRD: Read Draining. */
818#define VTD_BF_CAP_REG_DRD_SHIFT 55
819#define VTD_BF_CAP_REG_DRD_MASK UINT64_C(0x0080000000000000)
820/** FL1GP: First Level 1 GB Page Support. */
821#define VTD_BF_CAP_REG_FL1GP_SHIFT 56
822#define VTD_BF_CAP_REG_FL1GP_MASK UINT64_C(0x0100000000000000)
823/** R: Reserved (bits 58:57). */
824#define VTD_BF_CAP_REG_RSVD_58_57_SHIFT 57
825#define VTD_BF_CAP_REG_RSVD_58_57_MASK UINT64_C(0x0600000000000000)
826/** PI: Posted Interrupt Support. */
827#define VTD_BF_CAP_REG_PI_SHIFT 59
828#define VTD_BF_CAP_REG_PI_MASK UINT64_C(0x0800000000000000)
829/** FL5LP: First Level 5-level Paging Support. */
830#define VTD_BF_CAP_REG_FL5LP_SHIFT 60
831#define VTD_BF_CAP_REG_FL5LP_MASK UINT64_C(0x1000000000000000)
832/** R: Reserved (bit 61). */
833#define VTD_BF_CAP_REG_RSVD_61_SHIFT 61
834#define VTD_BF_CAP_REG_RSVD_61_MASK UINT64_C(0x2000000000000000)
835/** ESIRTPS: Enhanced Set Interrupt Root Table Pointer Support. */
836#define VTD_BF_CAP_REG_ESIRTPS_SHIFT 62
837#define VTD_BF_CAP_REG_ESIRTPS_MASK UINT64_C(0x4000000000000000)
838/** : Enhanced Set Root Table Pointer Support. */
839#define VTD_BF_CAP_REG_ESRTPS_SHIFT 63
840#define VTD_BF_CAP_REG_ESRTPS_MASK UINT64_C(0x8000000000000000)
841RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_CAP_REG_, UINT64_C(0), UINT64_MAX,
842 (ND, AFL, RWBF, PLMR, PHMR, CM, SAGAW, RSVD_15_13, MGAW, ZLR, RSVD_23, FRO, SLLPS, RSVD_38, PSI, NFR,
843 MAMV, DWD, DRD, FL1GP, RSVD_58_57, PI, FL5LP, RSVD_61, ESIRTPS, ESRTPS));
844
845/** RW: Read/write mask. */
846#define VTD_CAP_REG_RW_MASK UINT64_C(0)
847/** @} */
848
849
850/** @name Extended Capability Register (ECAP_REG).
851 * In accordance with the Intel spec.
852 * @{ */
853/** C: Page-walk Coherence. */
854#define VTD_BF_ECAP_REG_C_SHIFT 0
855#define VTD_BF_ECAP_REG_C_MASK UINT64_C(0x0000000000000001)
856/** QI: Queued Invalidation Support. */
857#define VTD_BF_ECAP_REG_QI_SHIFT 1
858#define VTD_BF_ECAP_REG_QI_MASK UINT64_C(0x0000000000000002)
859/** DT: Device-TLB Support. */
860#define VTD_BF_ECAP_REG_DT_SHIFT 2
861#define VTD_BF_ECAP_REG_DT_MASK UINT64_C(0x0000000000000004)
862/** IR: Interrupt Remapping Support. */
863#define VTD_BF_ECAP_REG_IR_SHIFT 3
864#define VTD_BF_ECAP_REG_IR_MASK UINT64_C(0x0000000000000008)
865/** EIM: Extended Interrupt Mode. */
866#define VTD_BF_ECAP_REG_EIM_SHIFT 4
867#define VTD_BF_ECAP_REG_EIM_MASK UINT64_C(0x0000000000000010)
868/** DEP: Deprecated MBZ. Reserved (bit 5). */
869#define VTD_BF_ECAP_REG_RSVD_5_SHIFT 5
870#define VTD_BF_ECAP_REG_RSVD_5_MASK UINT64_C(0x0000000000000020)
871/** PT: Pass Through. */
872#define VTD_BF_ECAP_REG_PT_SHIFT 6
873#define VTD_BF_ECAP_REG_PT_MASK UINT64_C(0x0000000000000040)
874/** SC: Snoop Control. */
875#define VTD_BF_ECAP_REG_SC_SHIFT 7
876#define VTD_BF_ECAP_REG_SC_MASK UINT64_C(0x0000000000000080)
877/** IRO: IOTLB Register Offset. */
878#define VTD_BF_ECAP_REG_IRO_SHIFT 8
879#define VTD_BF_ECAP_REG_IRO_MASK UINT64_C(0x000000000003ff00)
880/** R: Reserved (bits 19:18). */
881#define VTD_BF_ECAP_REG_RSVD_19_18_SHIFT 18
882#define VTD_BF_ECAP_REG_RSVD_19_18_MASK UINT64_C(0x00000000000c0000)
883/** MHMV: Maximum Handle Mask Value. */
884#define VTD_BF_ECAP_REG_MHMV_SHIFT 20
885#define VTD_BF_ECAP_REG_MHMV_MASK UINT64_C(0x0000000000f00000)
886/** DEP: Deprecated MBZ. Reserved (bit 24). */
887#define VTD_BF_ECAP_REG_RSVD_24_SHIFT 24
888#define VTD_BF_ECAP_REG_RSVD_24_MASK UINT64_C(0x0000000001000000)
889/** MTS: Memory Type Support. */
890#define VTD_BF_ECAP_REG_MTS_SHIFT 25
891#define VTD_BF_ECAP_REG_MTS_MASK UINT64_C(0x0000000002000000)
892/** NEST: Nested Translation Support. */
893#define VTD_BF_ECAP_REG_NEST_SHIFT 26
894#define VTD_BF_ECAP_REG_NEST_MASK UINT64_C(0x0000000004000000)
895/** R: Reserved (bit 27). */
896#define VTD_BF_ECAP_REG_RSVD_27_SHIFT 27
897#define VTD_BF_ECAP_REG_RSVD_27_MASK UINT64_C(0x0000000008000000)
898/** DEP: Deprecated MBZ. Reserved (bit 28). */
899#define VTD_BF_ECAP_REG_RSVD_28_SHIFT 28
900#define VTD_BF_ECAP_REG_RSVD_28_MASK UINT64_C(0x0000000010000000)
901/** PRS: Page Request Support. */
902#define VTD_BF_ECAP_REG_PRS_SHIFT 29
903#define VTD_BF_ECAP_REG_PRS_MASK UINT64_C(0x0000000020000000)
904/** ERS: Execute Request Support. */
905#define VTD_BF_ECAP_REG_ERS_SHIFT 30
906#define VTD_BF_ECAP_REG_ERS_MASK UINT64_C(0x0000000040000000)
907/** SRS: Supervisor Request Support. */
908#define VTD_BF_ECAP_REG_SRS_SHIFT 31
909#define VTD_BF_ECAP_REG_SRS_MASK UINT64_C(0x0000000080000000)
910/** R: Reserved (bit 32). */
911#define VTD_BF_ECAP_REG_RSVD_32_SHIFT 32
912#define VTD_BF_ECAP_REG_RSVD_32_MASK UINT64_C(0x0000000100000000)
913/** NWFS: No Write Flag Support. */
914#define VTD_BF_ECAP_REG_NWFS_SHIFT 33
915#define VTD_BF_ECAP_REG_NWFS_MASK UINT64_C(0x0000000200000000)
916/** EAFS: Extended Accessed Flags Support. */
917#define VTD_BF_ECAP_REG_EAFS_SHIFT 34
918#define VTD_BF_ECAP_REG_EAFS_MASK UINT64_C(0x0000000400000000)
919/** PSS: PASID Size Supported. */
920#define VTD_BF_ECAP_REG_PSS_SHIFT 35
921#define VTD_BF_ECAP_REG_PSS_MASK UINT64_C(0x000000f800000000)
922/** PASID: Process Address Space ID Support. */
923#define VTD_BF_ECAP_REG_PASID_SHIFT 40
924#define VTD_BF_ECAP_REG_PASID_MASK UINT64_C(0x0000010000000000)
925/** DIT: Device-TLB Invalidation Throttle. */
926#define VTD_BF_ECAP_REG_DIT_SHIFT 41
927#define VTD_BF_ECAP_REG_DIT_MASK UINT64_C(0x0000020000000000)
928/** PDS: Page-request Drain Support. */
929#define VTD_BF_ECAP_REG_PDS_SHIFT 42
930#define VTD_BF_ECAP_REG_PDS_MASK UINT64_C(0x0000040000000000)
931/** SMTS: Scalable-Mode Translation Support. */
932#define VTD_BF_ECAP_REG_SMTS_SHIFT 43
933#define VTD_BF_ECAP_REG_SMTS_MASK UINT64_C(0x0000080000000000)
934/** VCS: Virtual Command Support. */
935#define VTD_BF_ECAP_REG_VCS_SHIFT 44
936#define VTD_BF_ECAP_REG_VCS_MASK UINT64_C(0x0000100000000000)
937/** SLADS: Second-Level Accessed/Dirty Support. */
938#define VTD_BF_ECAP_REG_SLADS_SHIFT 45
939#define VTD_BF_ECAP_REG_SLADS_MASK UINT64_C(0x0000200000000000)
940/** SLTS: Second-Level Translation Support. */
941#define VTD_BF_ECAP_REG_SLTS_SHIFT 46
942#define VTD_BF_ECAP_REG_SLTS_MASK UINT64_C(0x0000400000000000)
943/** FLTS: First-Level Translation Support. */
944#define VTD_BF_ECAP_REG_FLTS_SHIFT 47
945#define VTD_BF_ECAP_REG_FLTS_MASK UINT64_C(0x0000800000000000)
946/** SMPWCS: Scalable-Mode Page-Walk Coherency Support. */
947#define VTD_BF_ECAP_REG_SMPWCS_SHIFT 48
948#define VTD_BF_ECAP_REG_SMPWCS_MASK UINT64_C(0x0001000000000000)
949/** RPS: RID-PASID Support. */
950#define VTD_BF_ECAP_REG_RPS_SHIFT 49
951#define VTD_BF_ECAP_REG_RPS_MASK UINT64_C(0x0002000000000000)
952/** R: Reserved (bits 51:50). */
953#define VTD_BF_ECAP_REG_RSVD_51_50_SHIFT 50
954#define VTD_BF_ECAP_REG_RSVD_51_50_MASK UINT64_C(0x000c000000000000)
955/** ADMS: Abort DMA Mode Support. */
956#define VTD_BF_ECAP_REG_ADMS_SHIFT 52
957#define VTD_BF_ECAP_REG_ADMS_MASK UINT64_C(0x0010000000000000)
958/** RPRIVS: RID_PRIV Support. */
959#define VTD_BF_ECAP_REG_RPRIVS_SHIFT 53
960#define VTD_BF_ECAP_REG_RPRIVS_MASK UINT64_C(0x0020000000000000)
961/** R: Reserved (bits 63:54). */
962#define VTD_BF_ECAP_REG_RSVD_63_54_SHIFT 54
963#define VTD_BF_ECAP_REG_RSVD_63_54_MASK UINT64_C(0xffc0000000000000)
964RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_ECAP_REG_, UINT64_C(0), UINT64_MAX,
965 (C, QI, DT, IR, EIM, RSVD_5, PT, SC, IRO, RSVD_19_18, MHMV, RSVD_24, MTS, NEST, RSVD_27, RSVD_28,
966 PRS, ERS, SRS, RSVD_32, NWFS, EAFS, PSS, PASID, DIT, PDS, SMTS, VCS, SLADS, SLTS, FLTS, SMPWCS, RPS,
967 RSVD_51_50, ADMS, RPRIVS, RSVD_63_54));
968
969/** RW: Read/write mask. */
970#define VTD_ECAP_REG_RW_MASK UINT64_C(0)
971/** @} */
972
973
974/** @name Global Command Register (GCMD_REG).
975 * In accordance with the Intel spec.
976 * @{ */
977/** R: Reserved (bits 22:0). */
978#define VTD_BF_GCMD_REG_RSVD_22_0_SHIFT 0
979#define VTD_BF_GCMD_REG_RSVD_22_0_MASK UINT32_C(0x007fffff)
980/** CFI: Compatibility Format Interrupt. */
981#define VTD_BF_GCMD_REG_CFI_SHIFT 23
982#define VTD_BF_GCMD_REG_CFI_MASK UINT32_C(0x00800000)
983/** SIRTP: Set Interrupt Table Remap Pointer. */
984#define VTD_BF_GCMD_REG_SIRTP_SHIFT 24
985#define VTD_BF_GCMD_REG_SIRTP_MASK UINT32_C(0x01000000)
986/** IRE: Interrupt Remap Enable. */
987#define VTD_BF_GCMD_REG_IRE_SHIFT 25
988#define VTD_BF_GCMD_REG_IRE_MASK UINT32_C(0x02000000)
989/** QIE: Queued Invalidation Enable. */
990#define VTD_BF_GCMD_REG_QIE_SHIFT 26
991#define VTD_BF_GCMD_REG_QIE_MASK UINT32_C(0x04000000)
992/** WBF: Write Buffer Flush. */
993#define VTD_BF_GCMD_REG_WBF_SHIFT 27
994#define VTD_BF_GCMD_REG_WBF_MASK UINT32_C(0x08000000)
995/** EAFL: Enable Advance Fault Logging. */
996#define VTD_BF_GCMD_REG_EAFL_SHIFT 28
997#define VTD_BF_GCMD_REG_EAFL_MASK UINT32_C(0x10000000)
998/** SFL: Set Fault Log. */
999#define VTD_BF_GCMD_REG_SFL_SHIFT 29
1000#define VTD_BF_GCMD_REG_SFL_MASK UINT32_C(0x20000000)
1001/** SRTP: Set Root Table Pointer. */
1002#define VTD_BF_GCMD_REG_SRTP_SHIFT 30
1003#define VTD_BF_GCMD_REG_SRTP_MASK UINT32_C(0x40000000)
1004/** TE: Translation Enable. */
1005#define VTD_BF_GCMD_REG_TE_SHIFT 31
1006#define VTD_BF_GCMD_REG_TE_MASK UINT32_C(0x80000000)
1007RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_GCMD_REG_, UINT32_C(0), UINT32_MAX,
1008 (RSVD_22_0, CFI, SIRTP, IRE, QIE, WBF, EAFL, SFL, SRTP, TE));
1009
1010/** RW: Read/write mask. */
1011#define VTD_GCMD_REG_RW_MASK ( VTD_BF_GCMD_REG_TE_MASK | VTD_BF_GCMD_REG_SRTP_MASK \
1012 | VTD_BF_GCMD_REG_SFL_MASK | VTD_BF_GCMD_REG_EAFL_MASK \
1013 | VTD_BF_GCMD_REG_WBF_MASK | VTD_BF_GCMD_REG_QIE_MASK \
1014 | VTD_BF_GCMD_REG_IRE_MASK | VTD_BF_GCMD_REG_SIRTP_MASK \
1015 | VTD_BF_GCMD_REG_CFI_MASK)
1016/** @} */
1017
1018
1019/** @name Global Status Register (GSTS_REG).
1020 * In accordance with the Intel spec.
1021 * @{ */
1022/** R: Reserved (bits 22:0). */
1023#define VTD_BF_GSTS_REG_RSVD_22_0_SHIFT 0
1024#define VTD_BF_GSTS_REG_RSVD_22_0_MASK UINT32_C(0x007fffff)
1025/** CFIS: Compatibility Format Interrupt Status. */
1026#define VTD_BF_GSTS_REG_CFIS_SHIFT 23
1027#define VTD_BF_GSTS_REG_CFIS_MASK UINT32_C(0x00800000)
1028/** IRTPS: Interrupt Remapping Table Pointer Status. */
1029#define VTD_BF_GSTS_REG_IRTPS_SHIFT 24
1030#define VTD_BF_GSTS_REG_IRTPS_MASK UINT32_C(0x01000000)
1031/** IRES: Interrupt Remapping Enable Status. */
1032#define VTD_BF_GSTS_REG_IRES_SHIFT 25
1033#define VTD_BF_GSTS_REG_IRES_MASK UINT32_C(0x02000000)
1034/** QIES: Queued Invalidation Enable Status. */
1035#define VTD_BF_GSTS_REG_QIES_SHIFT 26
1036#define VTD_BF_GSTS_REG_QIES_MASK UINT32_C(0x04000000)
1037/** WBFS: Write Buffer Flush Status. */
1038#define VTD_BF_GSTS_REG_WBFS_SHIFT 27
1039#define VTD_BF_GSTS_REG_WBFS_MASK UINT32_C(0x08000000)
1040/** AFLS: Advanced Fault Logging Status. */
1041#define VTD_BF_GSTS_REG_AFLS_SHIFT 28
1042#define VTD_BF_GSTS_REG_AFLS_MASK UINT32_C(0x10000000)
1043/** FLS: Fault Log Status. */
1044#define VTD_BF_GSTS_REG_FLS_SHIFT 29
1045#define VTD_BF_GSTS_REG_FLS_MASK UINT32_C(0x20000000)
1046/** RTPS: Root Table Pointer Status. */
1047#define VTD_BF_GSTS_REG_RTPS_SHIFT 30
1048#define VTD_BF_GSTS_REG_RTPS_MASK UINT32_C(0x40000000)
1049/** TES: Translation Enable Status. */
1050#define VTD_BF_GSTS_REG_TES_SHIFT 31
1051#define VTD_BF_GSTS_REG_TES_MASK UINT32_C(0x80000000)
1052RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_GSTS_REG_, UINT32_C(0), UINT32_MAX,
1053 (RSVD_22_0, CFIS, IRTPS, IRES, QIES, WBFS, AFLS, FLS, RTPS, TES));
1054
1055/** RW: Read/write mask. */
1056#define VTD_GSTS_REG_RW_MASK UINT32_C(0)
1057/** @} */
1058
1059
1060/** @name Root Table Address Register (RTADDR_REG).
1061 * In accordance with the Intel spec.
1062 * @{ */
1063/** R: Reserved (bits 9:0). */
1064#define VTD_BF_RTADDR_REG_RSVD_9_0_SHIFT 0
1065#define VTD_BF_RTADDR_REG_RSVD_9_0_MASK UINT64_C(0x00000000000003ff)
1066/** TTM: Translation Table Mode. */
1067#define VTD_BF_RTADDR_REG_TTM_SHIFT 10
1068#define VTD_BF_RTADDR_REG_TTM_MASK UINT64_C(0x0000000000000c00)
1069/** RTA: Root Table Address. */
1070#define VTD_BF_RTADDR_REG_RTA_SHIFT 12
1071#define VTD_BF_RTADDR_REG_RTA_MASK UINT64_C(0xfffffffffffff000)
1072RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_RTADDR_REG_, UINT64_C(0), UINT64_MAX,
1073 (RSVD_9_0, TTM, RTA));
1074
1075/** RW: Read/write mask. */
1076#define VTD_RTADDR_REG_RW_MASK UINT64_C(0xfffffffffffffc00)
1077
1078/** RTADDR_REG.TTM: Legacy mode. */
1079#define VTD_TTM_LEGACY_MODE 0
1080/** RTADDR_REG.TTM: Scalable mode. */
1081#define VTD_TTM_SCALABLE_MODE 1
1082/** RTADDR_REG.TTM: Reserved. */
1083#define VTD_TTM_RSVD 2
1084/** RTADDR_REG.TTM: Abort DMA mode. */
1085#define VTD_TTM_ABORT_DMA_MODE 3
1086/** @} */
1087
1088
1089/** @name Context Command Register (CCMD_REG).
1090 * In accordance with the Intel spec.
1091 * @{ */
1092/** DID: Domain-ID. */
1093#define VTD_BF_CCMD_REG_DID_SHIFT 0
1094#define VTD_BF_CCMD_REG_DID_MASK UINT64_C(0x000000000000ffff)
1095/** SID: Source-ID. */
1096#define VTD_BF_CCMD_REG_SID_SHIFT 16
1097#define VTD_BF_CCMD_REG_SID_MASK UINT64_C(0x00000000ffff0000)
1098/** FM: Function Mask. */
1099#define VTD_BF_CCMD_REG_FM_SHIFT 32
1100#define VTD_BF_CCMD_REG_FM_MASK UINT64_C(0x0000000300000000)
1101/** R: Reserved (bits 58:34). */
1102#define VTD_BF_CCMD_REG_RSVD_58_34_SHIFT 34
1103#define VTD_BF_CCMD_REG_RSVD_58_34_MASK UINT64_C(0x07fffffc00000000)
1104/** CAIG: Context Actual Invalidation Granularity. */
1105#define VTD_BF_CCMD_REG_CAIG_SHIFT 59
1106#define VTD_BF_CCMD_REG_CAIG_MASK UINT64_C(0x1800000000000000)
1107/** CIRG: Context Invalidation Request Granularity. */
1108#define VTD_BF_CCMD_REG_CIRG_SHIFT 61
1109#define VTD_BF_CCMD_REG_CIRG_MASK UINT64_C(0x6000000000000000)
1110/** ICC: Invalidation Context Cache. */
1111#define VTD_BF_CCMD_REG_ICC_SHIFT 63
1112#define VTD_BF_CCMD_REG_ICC_MASK UINT64_C(0x8000000000000000)
1113RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_CCMD_REG_, UINT64_C(0), UINT64_MAX,
1114 (DID, SID, FM, RSVD_58_34, CAIG, CIRG, ICC));
1115
1116/** RW: Read/write mask. */
1117#define VTD_CCMD_REG_RW_MASK ( VTD_BF_CCMD_REG_DID_MASK | VTD_BF_CCMD_REG_SID_MASK \
1118 | VTD_BF_CCMD_REG_FM_MASK | VTD_BF_CCMD_REG_CIRG_MASK \
1119 | VTD_BF_CCMD_REG_ICC_MASK)
1120/** @} */
1121
1122
1123/** @name IOTLB Invalidation Register (IOTLB_REG).
1124 * In accordance with the Intel spec.
1125 * @{ */
1126/** R: Reserved (bits 31:0). */
1127#define VTD_BF_IOTLB_REG_RSVD_31_0_SHIFT 0
1128#define VTD_BF_IOTLB_REG_RSVD_31_0_MASK UINT64_C(0x00000000ffffffff)
1129/** DID: Domain-ID. */
1130#define VTD_BF_IOTLB_REG_DID_SHIFT 32
1131#define VTD_BF_IOTLB_REG_DID_MASK UINT64_C(0x0000ffff00000000)
1132/** DW: Draining Writes. */
1133#define VTD_BF_IOTLB_REG_DW_SHIFT 48
1134#define VTD_BF_IOTLB_REG_DW_MASK UINT64_C(0x0001000000000000)
1135/** DR: Draining Reads. */
1136#define VTD_BF_IOTLB_REG_DR_SHIFT 49
1137#define VTD_BF_IOTLB_REG_DR_MASK UINT64_C(0x0002000000000000)
1138/** R: Reserved (bits 56:50). */
1139#define VTD_BF_IOTLB_REG_RSVD_56_50_SHIFT 50
1140#define VTD_BF_IOTLB_REG_RSVD_56_50_MASK UINT64_C(0x01fc000000000000)
1141/** IAIG: IOTLB Actual Invalidation Granularity. */
1142#define VTD_BF_IOTLB_REG_IAIG_SHIFT 57
1143#define VTD_BF_IOTLB_REG_IAIG_MASK UINT64_C(0x0600000000000000)
1144/** R: Reserved (bit 59). */
1145#define VTD_BF_IOTLB_REG_RSVD_59_SHIFT 59
1146#define VTD_BF_IOTLB_REG_RSVD_59_MASK UINT64_C(0x0800000000000000)
1147/** IIRG: IOTLB Invalidation Request Granularity. */
1148#define VTD_BF_IOTLB_REG_IIRG_SHIFT 60
1149#define VTD_BF_IOTLB_REG_IIRG_MASK UINT64_C(0x3000000000000000)
1150/** R: Reserved (bit 62). */
1151#define VTD_BF_IOTLB_REG_RSVD_62_SHIFT 62
1152#define VTD_BF_IOTLB_REG_RSVD_62_MASK UINT64_C(0x4000000000000000)
1153/** IVT: Invalidate IOTLB. */
1154#define VTD_BF_IOTLB_REG_IVT_SHIFT 63
1155#define VTD_BF_IOTLB_REG_IVT_MASK UINT64_C(0x8000000000000000)
1156RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IOTLB_REG_, UINT64_C(0), UINT64_MAX,
1157 (RSVD_31_0, DID, DW, DR, RSVD_56_50, IAIG, RSVD_59, IIRG, RSVD_62, IVT));
1158
1159/** RW: Read/write mask. */
1160#define VTD_IOTLB_REG_RW_MASK ( VTD_BF_IOTLB_REG_DID_MASK | VTD_BF_IOTLB_REG_DW_MASK \
1161 | VTD_BF_IOTLB_REG_DR_MASK | VTD_BF_IOTLB_REG_IIRG_MASK \
1162 | VTD_BF_IOTLB_REG_IVT_MASK)
1163/** @} */
1164
1165
1166/** @name Invalidate Address Register (IVA_REG).
1167 * In accordance with the Intel spec.
1168 * @{ */
1169/** AM: Address Mask. */
1170#define VTD_BF_IVA_REG_AM_SHIFT 0
1171#define VTD_BF_IVA_REG_AM_MASK UINT64_C(0x000000000000003f)
1172/** IH: Invalidation Hint. */
1173#define VTD_BF_IVA_REG_IH_SHIFT 6
1174#define VTD_BF_IVA_REG_IH_MASK UINT64_C(0x0000000000000040)
1175/** R: Reserved (bits 11:7). */
1176#define VTD_BF_IVA_REG_RSVD_11_7_SHIFT 7
1177#define VTD_BF_IVA_REG_RSVD_11_7_MASK UINT64_C(0x0000000000000f80)
1178/** ADDR: Address. */
1179#define VTD_BF_IVA_REG_ADDR_SHIFT 12
1180#define VTD_BF_IVA_REG_ADDR_MASK UINT64_C(0xfffffffffffff000)
1181RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IVA_REG_, UINT64_C(0), UINT64_MAX,
1182 (AM, IH, RSVD_11_7, ADDR));
1183
1184/** RW: Read/write mask. */
1185#define VTD_IVA_REG_RW_MASK ( VTD_BF_IVA_REG_AM_MASK | VTD_BF_IVA_REG_IH_MASK \
1186 | VTD_BF_IVA_REG_ADDR_MASK)
1187/** @} */
1188
1189
1190/** @name Fault Status Register (FSTS_REG).
1191 * In accordance with the Intel spec.
1192 * @{ */
1193/** PFO: Primary Fault Overflow. */
1194#define VTD_BF_FSTS_REG_PFO_SHIFT 0
1195#define VTD_BF_FSTS_REG_PFO_MASK UINT32_C(0x00000001)
1196/** PPF: Primary Pending Fault. */
1197#define VTD_BF_FSTS_REG_PPF_SHIFT 1
1198#define VTD_BF_FSTS_REG_PPF_MASK UINT32_C(0x00000002)
1199/** AFO: Advanced Fault Overflow. */
1200#define VTD_BF_FSTS_REG_AFO_SHIFT 2
1201#define VTD_BF_FSTS_REG_AFO_MASK UINT32_C(0x00000004)
1202/** APF: Advanced Pending Fault. */
1203#define VTD_BF_FSTS_REG_APF_SHIFT 3
1204#define VTD_BF_FSTS_REG_APF_MASK UINT32_C(0x00000008)
1205/** IQE: Invalidation Queue Error. */
1206#define VTD_BF_FSTS_REG_IQE_SHIFT 4
1207#define VTD_BF_FSTS_REG_IQE_MASK UINT32_C(0x00000010)
1208/** ICE: Invalidation Completion Error. */
1209#define VTD_BF_FSTS_REG_ICE_SHIFT 5
1210#define VTD_BF_FSTS_REG_ICE_MASK UINT32_C(0x00000020)
1211/** ITE: Invalidation Timeout Error. */
1212#define VTD_BF_FSTS_REG_ITE_SHIFT 6
1213#define VTD_BF_FSTS_REG_ITE_MASK UINT32_C(0x00000040)
1214/** DEP: Deprecated MBZ. Reserved (bit 7). */
1215#define VTD_BF_FSTS_REG_RSVD_7_SHIFT 7
1216#define VTD_BF_FSTS_REG_RSVD_7_MASK UINT32_C(0x00000080)
1217/** FRI: Fault Record Index. */
1218#define VTD_BF_FSTS_REG_FRI_SHIFT 8
1219#define VTD_BF_FSTS_REG_FRI_MASK UINT32_C(0x0000ff00)
1220/** R: Reserved (bits 31:16). */
1221#define VTD_BF_FSTS_REG_RSVD_31_16_SHIFT 16
1222#define VTD_BF_FSTS_REG_RSVD_31_16_MASK UINT32_C(0xffff0000)
1223RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_FSTS_REG_, UINT32_C(0), UINT32_MAX,
1224 (PFO, PPF, AFO, APF, IQE, ICE, ITE, RSVD_7, FRI, RSVD_31_16));
1225
1226/** RW: Read/write mask. */
1227#define VTD_FSTS_REG_RW_MASK ( VTD_BF_FSTS_REG_PFO_MASK | VTD_BF_FSTS_REG_AFO_MASK \
1228 | VTD_BF_FSTS_REG_APF_MASK | VTD_BF_FSTS_REG_IQE_MASK \
1229 | VTD_BF_FSTS_REG_ICE_MASK | VTD_BF_FSTS_REG_ITE_MASK)
1230/** RW1C: Read-only-status, Write-1-to-clear status mask. */
1231#define VTD_FSTS_REG_RW1C_MASK ( VTD_BF_FSTS_REG_PFO_MASK | VTD_BF_FSTS_REG_AFO_MASK \
1232 | VTD_BF_FSTS_REG_APF_MASK | VTD_BF_FSTS_REG_IQE_MASK \
1233 | VTD_BF_FSTS_REG_ICE_MASK | VTD_BF_FSTS_REG_ITE_MASK)
1234/** @} */
1235
1236
1237/** @name Fault Event Control Register (FECTL_REG).
1238 * In accordance with the Intel spec.
1239 * @{ */
1240/** R: Reserved (bits 29:0). */
1241#define VTD_BF_FECTL_REG_RSVD_29_0_SHIFT 0
1242#define VTD_BF_FECTL_REG_RSVD_29_0_MASK UINT32_C(0x3fffffff)
1243/** IP: Interrupt Pending. */
1244#define VTD_BF_FECTL_REG_IP_SHIFT 30
1245#define VTD_BF_FECTL_REG_IP_MASK UINT32_C(0x40000000)
1246/** IM: Interrupt Mask. */
1247#define VTD_BF_FECTL_REG_IM_SHIFT 31
1248#define VTD_BF_FECTL_REG_IM_MASK UINT32_C(0x80000000)
1249RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_FECTL_REG_, UINT32_C(0), UINT32_MAX,
1250 (RSVD_29_0, IP, IM));
1251
1252/** RW: Read/write mask. */
1253#define VTD_FECTL_REG_RW_MASK VTD_BF_FECTL_REG_IM_MASK
1254/** @} */
1255
1256
1257/** @name Fault Event Data Register (FEDATA_REG).
1258 * In accordance with the Intel spec.
1259 * @{ */
1260/** IMD: Interrupt Message Data. */
1261#define VTD_BF_FEDATA_REG_IMD_SHIFT 0
1262#define VTD_BF_FEDATA_REG_IMD_MASK UINT32_C(0x0000ffff)
1263/** R: Reserved (bits 31:16). VT-d specs. prior to 2021 had EIMD here. */
1264#define VTD_BF_FEDATA_REG_RSVD_31_16_SHIFT 16
1265#define VTD_BF_FEDATA_REG_RSVD_31_16_MASK UINT32_C(0xffff0000)
1266RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_FEDATA_REG_, UINT32_C(0), UINT32_MAX,
1267 (IMD, RSVD_31_16));
1268
1269/** RW: Read/write mask, see 5.1.6 "Remapping Hardware Event Interrupt
1270 * Programming". */
1271#define VTD_FEDATA_REG_RW_MASK UINT32_C(0x000001ff)
1272/** @} */
1273
1274
1275/** @name Fault Event Address Register (FEADDR_REG).
1276 * In accordance with the Intel spec.
1277 * @{ */
1278/** R: Reserved (bits 1:0). */
1279#define VTD_BF_FEADDR_REG_RSVD_1_0_SHIFT 0
1280#define VTD_BF_FEADDR_REG_RSVD_1_0_MASK UINT32_C(0x00000003)
1281/** MA: Message Address. */
1282#define VTD_BF_FEADDR_REG_MA_SHIFT 2
1283#define VTD_BF_FEADDR_REG_MA_MASK UINT32_C(0xfffffffc)
1284RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_FEADDR_REG_, UINT32_C(0), UINT32_MAX,
1285 (RSVD_1_0, MA));
1286
1287/** RW: Read/write mask. */
1288#define VTD_FEADDR_REG_RW_MASK VTD_BF_FEADDR_REG_MA_MASK
1289/** @} */
1290
1291
1292/** @name Fault Event Upper Address Register (FEUADDR_REG).
1293 * In accordance with the Intel spec.
1294 * @{ */
1295/** MUA: Message Upper Address. */
1296#define VTD_BF_FEUADDR_REG_MA_SHIFT 0
1297#define VTD_BF_FEUADDR_REG_MA_MASK UINT32_C(0xffffffff)
1298
1299/** RW: Read/write mask. */
1300#define VTD_FEUADDR_REG_RW_MASK VTD_BF_FEUADDR_REG_MA_MASK
1301/** @} */
1302
1303
1304/** @name Fault Recording Register (FRCD_REG).
1305 * In accordance with the Intel spec.
1306 * @{ */
1307/** R: Reserved (bits 11:0). */
1308#define VTD_BF_0_FRCD_REG_RSVD_11_0_SHIFT 0
1309#define VTD_BF_0_FRCD_REG_RSVD_11_0_MASK UINT64_C(0x0000000000000fff)
1310/** FI: Fault Info. */
1311#define VTD_BF_0_FRCD_REG_FI_SHIFT 12
1312#define VTD_BF_0_FRCD_REG_FI_MASK UINT64_C(0xfffffffffffff000)
1313RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_FRCD_REG_, UINT64_C(0), UINT64_MAX,
1314 (RSVD_11_0, FI));
1315
1316/** SID: Source Identifier. */
1317#define VTD_BF_1_FRCD_REG_SID_SHIFT 0
1318#define VTD_BF_1_FRCD_REG_SID_MASK UINT64_C(0x000000000000ffff)
1319/** R: Reserved (bits 27:16). */
1320#define VTD_BF_1_FRCD_REG_RSVD_27_16_SHIFT 16
1321#define VTD_BF_1_FRCD_REG_RSVD_27_16_MASK UINT64_C(0x000000000fff0000)
1322/** T2: Type bit 2. */
1323#define VTD_BF_1_FRCD_REG_T2_SHIFT 28
1324#define VTD_BF_1_FRCD_REG_T2_MASK UINT64_C(0x0000000010000000)
1325/** PRIV: Privilege Mode. */
1326#define VTD_BF_1_FRCD_REG_PRIV_SHIFT 29
1327#define VTD_BF_1_FRCD_REG_PRIV_MASK UINT64_C(0x0000000020000000)
1328/** EXE: Execute Permission Requested. */
1329#define VTD_BF_1_FRCD_REG_EXE_SHIFT 30
1330#define VTD_BF_1_FRCD_REG_EXE_MASK UINT64_C(0x0000000040000000)
1331/** PP: PASID Present. */
1332#define VTD_BF_1_FRCD_REG_PP_SHIFT 31
1333#define VTD_BF_1_FRCD_REG_PP_MASK UINT64_C(0x0000000080000000)
1334/** FR: Fault Reason. */
1335#define VTD_BF_1_FRCD_REG_FR_SHIFT 32
1336#define VTD_BF_1_FRCD_REG_FR_MASK UINT64_C(0x000000ff00000000)
1337/** PV: PASID Value. */
1338#define VTD_BF_1_FRCD_REG_PV_SHIFT 40
1339#define VTD_BF_1_FRCD_REG_PV_MASK UINT64_C(0x0fffff0000000000)
1340/** AT: Address Type. */
1341#define VTD_BF_1_FRCD_REG_AT_SHIFT 60
1342#define VTD_BF_1_FRCD_REG_AT_MASK UINT64_C(0x3000000000000000)
1343/** T1: Type bit 1. */
1344#define VTD_BF_1_FRCD_REG_T1_SHIFT 62
1345#define VTD_BF_1_FRCD_REG_T1_MASK UINT64_C(0x4000000000000000)
1346/** F: Fault. */
1347#define VTD_BF_1_FRCD_REG_F_SHIFT 63
1348#define VTD_BF_1_FRCD_REG_F_MASK UINT64_C(0x8000000000000000)
1349RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_FRCD_REG_, UINT64_C(0), UINT64_MAX,
1350 (SID, RSVD_27_16, T2, PRIV, EXE, PP, FR, PV, AT, T1, F));
1351
1352/** RW: Read/write mask. */
1353#define VTD_FRCD_REG_LO_RW_MASK UINT64_C(0)
1354#define VTD_FRCD_REG_HI_RW_MASK VTD_BF_1_FRCD_REG_F_MASK
1355/** RW1C: Read-only-status, Write-1-to-clear status mask. */
1356#define VTD_FRCD_REG_LO_RW1C_MASK UINT64_C(0)
1357#define VTD_FRCD_REG_HI_RW1C_MASK VTD_BF_1_FRCD_REG_F_MASK
1358/** @} */
1359
1360
1361/**
1362 * VT-d faulted address translation request types (FRCD_REG::T2).
1363 * In accordance with the Intel spec.
1364 */
1365typedef enum VTDREQTYPE
1366{
1367 VTDREQTYPE_WRITE = 0, /**< Memory access write request. */
1368 VTDREQTYPE_PAGE, /**< Page translation request. */
1369 VTDREQTYPE_READ, /**< Memory access read request. */
1370 VTDREQTYPE_ATOMIC_OP /**< Memory access atomic operation. */
1371} VTDREQTYPE;
1372
1373
1374/** @name VT-d faulted request attributes (FRCD_REG::EXE, FRCD_REG::PRIV).
1375 * In accordance with the Intel spec.
1376 * @{
1377 */
1378/** Supervisory privilege was requested. */
1379#define VTD_REQ_ATTR_PRIV RT_BIT(0)
1380/** Execute permission was requested. */
1381#define VTD_REQ_ATTR_EXE RT_BIT(1)
1382/** @} */
1383
1384
1385/** @name Advanced Fault Log Register (AFLOG_REG).
1386 * In accordance with the Intel spec.
1387 * @{ */
1388/** R: Reserved (bits 8:0). */
1389#define VTD_BF_0_AFLOG_REG_RSVD_8_0_SHIFT 0
1390#define VTD_BF_0_AFLOG_REG_RSVD_8_0_MASK UINT64_C(0x00000000000001ff)
1391/** FLS: Fault Log Size. */
1392#define VTD_BF_0_AFLOG_REG_FLS_SHIFT 9
1393#define VTD_BF_0_AFLOG_REG_FLS_MASK UINT64_C(0x0000000000000e00)
1394/** FLA: Fault Log Address. */
1395#define VTD_BF_0_AFLOG_REG_FLA_SHIFT 12
1396#define VTD_BF_0_AFLOG_REG_FLA_MASK UINT64_C(0xfffffffffffff000)
1397RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_AFLOG_REG_, UINT64_C(0), UINT64_MAX,
1398 (RSVD_8_0, FLS, FLA));
1399
1400/** RW: Read/write mask. */
1401#define VTD_AFLOG_REG_RW_MASK (VTD_BF_0_AFLOG_REG_FLS_MASK | VTD_BF_0_AFLOG_REG_FLA_MASK)
1402/** @} */
1403
1404
1405/** @name Protected Memory Enable Register (PMEN_REG).
1406 * In accordance with the Intel spec.
1407 * @{ */
1408/** PRS: Protected Region Status. */
1409#define VTD_BF_PMEN_REG_PRS_SHIFT 0
1410#define VTD_BF_PMEN_REG_PRS_MASK UINT32_C(0x00000001)
1411/** R: Reserved (bits 30:1). */
1412#define VTD_BF_PMEN_REG_RSVD_30_1_SHIFT 1
1413#define VTD_BF_PMEN_REG_RSVD_30_1_MASK UINT32_C(0x7ffffffe)
1414/** EPM: Enable Protected Memory. */
1415#define VTD_BF_PMEN_REG_EPM_SHIFT 31
1416#define VTD_BF_PMEN_REG_EPM_MASK UINT32_C(0x80000000)
1417RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_PMEN_REG_, UINT32_C(0), UINT32_MAX,
1418 (PRS, RSVD_30_1, EPM));
1419
1420/** RW: Read/write mask. */
1421#define VTD_PMEN_REG_RW_MASK VTD_BF_PMEN_REG_EPM_MASK
1422/** @} */
1423
1424
1425/** @name Invalidation Queue Head Register (IQH_REG).
1426 * In accordance with the Intel spec.
1427 * @{ */
1428/** R: Reserved (bits 3:0). */
1429#define VTD_BF_IQH_REG_RSVD_3_0_SHIFT 0
1430#define VTD_BF_IQH_REG_RSVD_3_0_MASK UINT64_C(0x000000000000000f)
1431/** QH: Queue Head. */
1432#define VTD_BF_IQH_REG_QH_SHIFT 4
1433#define VTD_BF_IQH_REG_QH_MASK UINT64_C(0x000000000007fff0)
1434/** R: Reserved (bits 63:19). */
1435#define VTD_BF_IQH_REG_RSVD_63_19_SHIFT 19
1436#define VTD_BF_IQH_REG_RSVD_63_19_MASK UINT64_C(0xfffffffffff80000)
1437RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IQH_REG_, UINT64_C(0), UINT64_MAX,
1438 (RSVD_3_0, QH, RSVD_63_19));
1439
1440/** RW: Read/write mask. */
1441#define VTD_IQH_REG_RW_MASK UINT64_C(0x0)
1442/** @} */
1443
1444
1445/** @name Invalidation Queue Tail Register (IQT_REG).
1446 * In accordance with the Intel spec.
1447 * @{ */
1448/** R: Reserved (bits 3:0). */
1449#define VTD_BF_IQT_REG_RSVD_3_0_SHIFT 0
1450#define VTD_BF_IQT_REG_RSVD_3_0_MASK UINT64_C(0x000000000000000f)
1451/** QH: Queue Tail. */
1452#define VTD_BF_IQT_REG_QT_SHIFT 4
1453#define VTD_BF_IQT_REG_QT_MASK UINT64_C(0x000000000007fff0)
1454/** R: Reserved (bits 63:19). */
1455#define VTD_BF_IQT_REG_RSVD_63_19_SHIFT 19
1456#define VTD_BF_IQT_REG_RSVD_63_19_MASK UINT64_C(0xfffffffffff80000)
1457RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IQT_REG_, UINT64_C(0), UINT64_MAX,
1458 (RSVD_3_0, QT, RSVD_63_19));
1459
1460/** RW: Read/write mask. */
1461#define VTD_IQT_REG_RW_MASK VTD_BF_IQT_REG_QT_MASK
1462/** @} */
1463
1464
1465/** @name Invalidation Queue Address Register (IQA_REG).
1466 * In accordance with the Intel spec.
1467 * @{ */
1468/** QS: Queue Size. */
1469#define VTD_BF_IQA_REG_QS_SHIFT 0
1470#define VTD_BF_IQA_REG_QS_MASK UINT64_C(0x0000000000000007)
1471/** R: Reserved (bits 10:3). */
1472#define VTD_BF_IQA_REG_RSVD_10_3_SHIFT 3
1473#define VTD_BF_IQA_REG_RSVD_10_3_MASK UINT64_C(0x00000000000007f8)
1474/** DW: Descriptor Width. */
1475#define VTD_BF_IQA_REG_DW_SHIFT 11
1476#define VTD_BF_IQA_REG_DW_MASK UINT64_C(0x0000000000000800)
1477/** IQA: Invalidation Queue Base Address. */
1478#define VTD_BF_IQA_REG_IQA_SHIFT 12
1479#define VTD_BF_IQA_REG_IQA_MASK UINT64_C(0xfffffffffffff000)
1480RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IQA_REG_, UINT64_C(0), UINT64_MAX,
1481 (QS, RSVD_10_3, DW, IQA));
1482
1483/** RW: Read/write mask. */
1484#define VTD_IQA_REG_RW_MASK ( VTD_BF_IQA_REG_QS_MASK | VTD_BF_IQA_REG_DW_MASK \
1485 | VTD_BF_IQA_REG_IQA_MASK)
1486/** DW: 128-bit descriptor. */
1487#define VTD_IQA_REG_DW_128_BIT 0
1488/** DW: 256-bit descriptor. */
1489#define VTD_IQA_REG_DW_256_BIT 1
1490/** @} */
1491
1492
1493/** @name Invalidation Completion Status Register (ICS_REG).
1494 * In accordance with the Intel spec.
1495 * @{ */
1496/** IWC: Invalidation Wait Descriptor Complete. */
1497#define VTD_BF_ICS_REG_IWC_SHIFT 0
1498#define VTD_BF_ICS_REG_IWC_MASK UINT32_C(0x00000001)
1499/** R: Reserved (bits 31:1). */
1500#define VTD_BF_ICS_REG_RSVD_31_1_SHIFT 1
1501#define VTD_BF_ICS_REG_RSVD_31_1_MASK UINT32_C(0xfffffffe)
1502RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_ICS_REG_, UINT32_C(0), UINT32_MAX,
1503 (IWC, RSVD_31_1));
1504
1505/** RW: Read/write mask. */
1506#define VTD_ICS_REG_RW_MASK VTD_BF_ICS_REG_IWC_MASK
1507/** RW1C: Read-only-status, Write-1-to-clear status mask. */
1508#define VTD_ICS_REG_RW1C_MASK VTD_BF_ICS_REG_IWC_MASK
1509/** @} */
1510
1511
1512/** @name Invalidation Event Control Register (IECTL_REG).
1513 * In accordance with the Intel spec.
1514 * @{ */
1515/** R: Reserved (bits 29:0). */
1516#define VTD_BF_IECTL_REG_RSVD_29_0_SHIFT 0
1517#define VTD_BF_IECTL_REG_RSVD_29_0_MASK UINT32_C(0x3fffffff)
1518/** IP: Interrupt Pending. */
1519#define VTD_BF_IECTL_REG_IP_SHIFT 30
1520#define VTD_BF_IECTL_REG_IP_MASK UINT32_C(0x40000000)
1521/** IM: Interrupt Mask. */
1522#define VTD_BF_IECTL_REG_IM_SHIFT 31
1523#define VTD_BF_IECTL_REG_IM_MASK UINT32_C(0x80000000)
1524RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IECTL_REG_, UINT32_C(0), UINT32_MAX,
1525 (RSVD_29_0, IP, IM));
1526
1527/** RW: Read/write mask. */
1528#define VTD_IECTL_REG_RW_MASK VTD_BF_IECTL_REG_IM_MASK
1529/** @} */
1530
1531
1532/** @name Invalidation Event Data Register (IEDATA_REG).
1533 * In accordance with the Intel spec.
1534 * @{ */
1535/** IMD: Interrupt Message Data. */
1536#define VTD_BF_IEDATA_REG_IMD_SHIFT 0
1537#define VTD_BF_IEDATA_REG_IMD_MASK UINT32_C(0x0000ffff)
1538/** R: Reserved (bits 31:16). VT-d specs. prior to 2021 had EIMD here. */
1539#define VTD_BF_IEDATA_REG_RSVD_31_16_SHIFT 16
1540#define VTD_BF_IEDATA_REG_RSVD_31_16_MASK UINT32_C(0xffff0000)
1541RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IEDATA_REG_, UINT32_C(0), UINT32_MAX,
1542 (IMD, RSVD_31_16));
1543
1544/** RW: Read/write mask, see 5.1.6 "Remapping Hardware Event Interrupt
1545 * Programming". */
1546#define VTD_IEDATA_REG_RW_MASK UINT32_C(0x000001ff)
1547/** @} */
1548
1549
1550/** @name Invalidation Event Address Register (IEADDR_REG).
1551 * In accordance with the Intel spec.
1552 * @{ */
1553/** R: Reserved (bits 1:0). */
1554#define VTD_BF_IEADDR_REG_RSVD_1_0_SHIFT 0
1555#define VTD_BF_IEADDR_REG_RSVD_1_0_MASK UINT32_C(0x00000003)
1556/** MA: Message Address. */
1557#define VTD_BF_IEADDR_REG_MA_SHIFT 2
1558#define VTD_BF_IEADDR_REG_MA_MASK UINT32_C(0xfffffffc)
1559RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IEADDR_REG_, UINT32_C(0), UINT32_MAX,
1560 (RSVD_1_0, MA));
1561
1562/** RW: Read/write mask. */
1563#define VTD_IEADDR_REG_RW_MASK VTD_BF_IEADDR_REG_MA_MASK
1564/** @} */
1565
1566
1567/** @name Invalidation Event Upper Address Register (IEUADDR_REG).
1568 * @{ */
1569/** MUA: Message Upper Address. */
1570#define VTD_BF_IEUADDR_REG_MUA_SHIFT 0
1571#define VTD_BF_IEUADDR_REG_MUA_MASK UINT32_C(0xffffffff)
1572
1573/** RW: Read/write mask. */
1574#define VTD_IEUADDR_REG_RW_MASK VTD_BF_IEUADDR_REG_MUA_MASK
1575/** @} */
1576
1577
1578/** @name Invalidation Queue Error Record Register (IQERCD_REG).
1579 * In accordance with the Intel spec.
1580 * @{ */
1581/** IQEI: Invalidation Queue Error Info. */
1582#define VTD_BF_IQERCD_REG_IQEI_SHIFT 0
1583#define VTD_BF_IQERCD_REG_IQEI_MASK UINT64_C(0x000000000000000f)
1584/** R: Reserved (bits 31:4). */
1585#define VTD_BF_IQERCD_REG_RSVD_31_4_SHIFT 4
1586#define VTD_BF_IQERCD_REG_RSVD_31_4_MASK UINT64_C(0x00000000fffffff0)
1587/** ITESID: Invalidation Timeout Error Source Identifier. */
1588#define VTD_BF_IQERCD_REG_ITESID_SHIFT 32
1589#define VTD_BF_IQERCD_REG_ITESID_MASK UINT64_C(0x0000ffff00000000)
1590/** ICESID: Invalidation Completion Error Source Identifier. */
1591#define VTD_BF_IQERCD_REG_ICESID_SHIFT 48
1592#define VTD_BF_IQERCD_REG_ICESID_MASK UINT64_C(0xffff000000000000)
1593RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IQERCD_REG_, UINT64_C(0), UINT64_MAX,
1594 (IQEI, RSVD_31_4, ITESID, ICESID));
1595
1596/** RW: Read/write mask. */
1597#define VTD_IQERCD_REG_RW_MASK UINT64_C(0)
1598
1599/** Invalidation Queue Error Information. */
1600typedef enum VTDIQEI
1601{
1602 VTDIQEI_INFO_NOT_AVAILABLE,
1603 VTDIQEI_INVALID_TAIL_PTR,
1604 VTDIQEI_FETCH_DESCRIPTOR_ERR,
1605 VTDIQEI_INVALID_DESCRIPTOR_TYPE,
1606 VTDIQEI_RSVD_FIELD_VIOLATION,
1607 VTDIQEI_INVALID_DESCRIPTOR_WIDTH,
1608 VTDIQEI_QUEUE_TAIL_MISALIGNED,
1609 VTDIQEI_INVALID_TTM
1610} VTDIQEI;
1611/** @} */
1612
1613
1614/** @name Interrupt Remapping Table Address Register (IRTA_REG).
1615 * In accordance with the Intel spec.
1616 * @{ */
1617/** S: Size. */
1618#define VTD_BF_IRTA_REG_S_SHIFT 0
1619#define VTD_BF_IRTA_REG_S_MASK UINT64_C(0x000000000000000f)
1620/** R: Reserved (bits 10:4). */
1621#define VTD_BF_IRTA_REG_RSVD_10_4_SHIFT 4
1622#define VTD_BF_IRTA_REG_RSVD_10_4_MASK UINT64_C(0x00000000000007f0)
1623/** EIME: Extended Interrupt Mode Enable. */
1624#define VTD_BF_IRTA_REG_EIME_SHIFT 11
1625#define VTD_BF_IRTA_REG_EIME_MASK UINT64_C(0x0000000000000800)
1626/** IRTA: Interrupt Remapping Table Address. */
1627#define VTD_BF_IRTA_REG_IRTA_SHIFT 12
1628#define VTD_BF_IRTA_REG_IRTA_MASK UINT64_C(0xfffffffffffff000)
1629RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IRTA_REG_, UINT64_C(0), UINT64_MAX,
1630 (S, RSVD_10_4, EIME, IRTA));
1631
1632/** RW: Read/write mask. */
1633#define VTD_IRTA_REG_RW_MASK ( VTD_BF_IRTA_REG_S_MASK | VTD_BF_IRTA_REG_EIME_MASK \
1634 | VTD_BF_IRTA_REG_IRTA_MASK)
1635/** IRTA_REG: Get number of interrupt entries. */
1636#define VTD_IRTA_REG_GET_ENTRY_COUNT(a) (UINT32_C(1) << (1 + ((a) & VTD_BF_IRTA_REG_S_MASK)))
1637/** @} */
1638
1639
1640/** @name Page Request Queue Head Register (PQH_REG).
1641 * In accordance with the Intel spec.
1642 * @{ */
1643/** R: Reserved (bits 4:0). */
1644#define VTD_BF_PQH_REG_RSVD_4_0_SHIFT 0
1645#define VTD_BF_PQH_REG_RSVD_4_0_MASK UINT64_C(0x000000000000001f)
1646/** PQH: Page Queue Head. */
1647#define VTD_BF_PQH_REG_PQH_SHIFT 5
1648#define VTD_BF_PQH_REG_PQH_MASK UINT64_C(0x000000000007ffe0)
1649/** R: Reserved (bits 63:19). */
1650#define VTD_BF_PQH_REG_RSVD_63_19_SHIFT 19
1651#define VTD_BF_PQH_REG_RSVD_63_19_MASK UINT64_C(0xfffffffffff80000)
1652RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_PQH_REG_, UINT64_C(0), UINT64_MAX,
1653 (RSVD_4_0, PQH, RSVD_63_19));
1654
1655/** RW: Read/write mask. */
1656#define VTD_PQH_REG_RW_MASK VTD_BF_PQH_REG_PQH_MASK
1657/** @} */
1658
1659
1660/** @name Page Request Queue Tail Register (PQT_REG).
1661 * In accordance with the Intel spec.
1662 * @{ */
1663/** R: Reserved (bits 4:0). */
1664#define VTD_BF_PQT_REG_RSVD_4_0_SHIFT 0
1665#define VTD_BF_PQT_REG_RSVD_4_0_MASK UINT64_C(0x000000000000001f)
1666/** PQT: Page Queue Tail. */
1667#define VTD_BF_PQT_REG_PQT_SHIFT 5
1668#define VTD_BF_PQT_REG_PQT_MASK UINT64_C(0x000000000007ffe0)
1669/** R: Reserved (bits 63:19). */
1670#define VTD_BF_PQT_REG_RSVD_63_19_SHIFT 19
1671#define VTD_BF_PQT_REG_RSVD_63_19_MASK UINT64_C(0xfffffffffff80000)
1672RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_PQT_REG_, UINT64_C(0), UINT64_MAX,
1673 (RSVD_4_0, PQT, RSVD_63_19));
1674
1675/** RW: Read/write mask. */
1676#define VTD_PQT_REG_RW_MASK VTD_BF_PQT_REG_PQT_MASK
1677/** @} */
1678
1679
1680/** @name Page Request Queue Address Register (PQA_REG).
1681 * In accordance with the Intel spec.
1682 * @{ */
1683/** PQS: Page Queue Size. */
1684#define VTD_BF_PQA_REG_PQS_SHIFT 0
1685#define VTD_BF_PQA_REG_PQS_MASK UINT64_C(0x0000000000000007)
1686/** R: Reserved bits (11:3). */
1687#define VTD_BF_PQA_REG_RSVD_11_3_SHIFT 3
1688#define VTD_BF_PQA_REG_RSVD_11_3_MASK UINT64_C(0x0000000000000ff8)
1689/** PQA: Page Request Queue Base Address. */
1690#define VTD_BF_PQA_REG_PQA_SHIFT 12
1691#define VTD_BF_PQA_REG_PQA_MASK UINT64_C(0xfffffffffffff000)
1692RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_PQA_REG_, UINT64_C(0), UINT64_MAX,
1693 (PQS, RSVD_11_3, PQA));
1694
1695/** RW: Read/write mask. */
1696#define VTD_PQA_REG_RW_MASK (VTD_BF_PQA_REG_PQS_MASK | VTD_BF_PQA_REG_PQA_MASK)
1697/** @} */
1698
1699
1700/** @name Page Request Status Register (PRS_REG).
1701 * In accordance with the Intel spec.
1702 * @{ */
1703/** PPR: Pending Page Request. */
1704#define VTD_BF_PRS_REG_PPR_SHIFT 0
1705#define VTD_BF_PRS_REG_PPR_MASK UINT64_C(0x00000001)
1706/** PRO: Page Request Overflow. */
1707#define VTD_BF_PRS_REG_PRO_SHIFT 1
1708#define VTD_BF_PRS_REG_PRO_MASK UINT64_C(0x00000002)
1709/** R: Reserved (bits 31:2). */
1710#define VTD_BF_PRS_REG_RSVD_31_2_SHIFT 2
1711#define VTD_BF_PRS_REG_RSVD_31_2_MASK UINT64_C(0xfffffffc)
1712RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_PRS_REG_, UINT32_C(0), UINT32_MAX,
1713 (PPR, PRO, RSVD_31_2));
1714
1715/** RW: Read/write mask. */
1716#define VTD_PRS_REG_RW_MASK (VTD_BF_PRS_REG_PPR_MASK | VTD_BF_PRS_REG_PRO_MASK)
1717/** RW1C: Read-only-status, Write-1-to-clear status mask. */
1718#define VTD_PRS_REG_RW1C_MASK (VTD_BF_PRS_REG_PPR_MASK | VTD_BF_PRS_REG_PRO_MASK)
1719/** @} */
1720
1721
1722/** @name Page Request Event Control Register (PECTL_REG).
1723 * In accordance with the Intel spec.
1724 * @{ */
1725/** R: Reserved (bits 29:0). */
1726#define VTD_BF_PECTL_REG_RSVD_29_0_SHIFT 0
1727#define VTD_BF_PECTL_REG_RSVD_29_0_MASK UINT32_C(0x3fffffff)
1728/** IP: Interrupt Pending. */
1729#define VTD_BF_PECTL_REG_IP_SHIFT 30
1730#define VTD_BF_PECTL_REG_IP_MASK UINT32_C(0x40000000)
1731/** IM: Interrupt Mask. */
1732#define VTD_BF_PECTL_REG_IM_SHIFT 31
1733#define VTD_BF_PECTL_REG_IM_MASK UINT32_C(0x80000000)
1734RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_PECTL_REG_, UINT32_C(0), UINT32_MAX,
1735 (RSVD_29_0, IP, IM));
1736
1737/** RW: Read/write mask. */
1738#define VTD_PECTL_REG_RW_MASK VTD_BF_PECTL_REG_IM_MASK
1739/** @} */
1740
1741
1742/** @name Page Request Event Data Register (PEDATA_REG).
1743 * In accordance with the Intel spec.
1744 * @{ */
1745/** IMD: Interrupt Message Data. */
1746#define VTD_BF_PEDATA_REG_IMD_SHIFT 0
1747#define VTD_BF_PEDATA_REG_IMD_MASK UINT32_C(0x0000ffff)
1748/** R: Reserved (bits 31:16). VT-d specs. prior to 2021 had EIMD here. */
1749#define VTD_BF_PEDATA_REG_RSVD_31_16_SHIFT 16
1750#define VTD_BF_PEDATA_REG_RSVD_31_16_MASK UINT32_C(0xffff0000)
1751RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_PEDATA_REG_, UINT32_C(0), UINT32_MAX,
1752 (IMD, RSVD_31_16));
1753
1754/** RW: Read/write mask, see 5.1.6 "Remapping Hardware Event Interrupt
1755 * Programming". */
1756#define VTD_PEDATA_REG_RW_MASK UINT32_C(0x000001ff)
1757/** @} */
1758
1759
1760/** @name Page Request Event Address Register (PEADDR_REG).
1761 * In accordance with the Intel spec.
1762 * @{ */
1763/** R: Reserved (bits 1:0). */
1764#define VTD_BF_PEADDR_REG_RSVD_1_0_SHIFT 0
1765#define VTD_BF_PEADDR_REG_RSVD_1_0_MASK UINT32_C(0x00000003)
1766/** MA: Message Address. */
1767#define VTD_BF_PEADDR_REG_MA_SHIFT 2
1768#define VTD_BF_PEADDR_REG_MA_MASK UINT32_C(0xfffffffc)
1769RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_PEADDR_REG_, UINT32_C(0), UINT32_MAX,
1770 (RSVD_1_0, MA));
1771
1772/** RW: Read/write mask. */
1773#define VTD_PEADDR_REG_RW_MASK VTD_BF_PEADDR_REG_MA_MASK
1774/** @} */
1775
1776
1777
1778/** @name Page Request Event Upper Address Register (PEUADDR_REG).
1779 * In accordance with the Intel spec.
1780 * @{ */
1781/** MA: Message Address. */
1782#define VTD_BF_PEUADDR_REG_MUA_SHIFT 0
1783#define VTD_BF_PEUADDR_REG_MUA_MASK UINT32_C(0xffffffff)
1784
1785/** RW: Read/write mask. */
1786#define VTD_PEUADDR_REG_RW_MASK VTD_BF_PEUADDR_REG_MUA_MASK
1787/** @} */
1788
1789
1790/** @name MTRR Capability Register (MTRRCAP_REG).
1791 * In accordance with the Intel spec.
1792 * @{ */
1793/** VCNT: Variable MTRR Count. */
1794#define VTD_BF_MTRRCAP_REG_VCNT_SHIFT 0
1795#define VTD_BF_MTRRCAP_REG_VCNT_MASK UINT64_C(0x00000000000000ff)
1796/** FIX: Fixed range MTRRs Supported. */
1797#define VTD_BF_MTRRCAP_REG_FIX_SHIFT 8
1798#define VTD_BF_MTRRCAP_REG_FIX_MASK UINT64_C(0x0000000000000100)
1799/** R: Reserved (bit 9). */
1800#define VTD_BF_MTRRCAP_REG_RSVD_9_SHIFT 9
1801#define VTD_BF_MTRRCAP_REG_RSVD_9_MASK UINT64_C(0x0000000000000200)
1802/** WC: Write Combining. */
1803#define VTD_BF_MTRRCAP_REG_WC_SHIFT 10
1804#define VTD_BF_MTRRCAP_REG_WC_MASK UINT64_C(0x0000000000000400)
1805/** R: Reserved (bits 63:11). */
1806#define VTD_BF_MTRRCAP_REG_RSVD_63_11_SHIFT 11
1807#define VTD_BF_MTRRCAP_REG_RSVD_63_11_MASK UINT64_C(0xfffffffffffff800)
1808RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_MTRRCAP_REG_, UINT64_C(0), UINT64_MAX,
1809 (VCNT, FIX, RSVD_9, WC, RSVD_63_11));
1810
1811/** RW: Read/write mask. */
1812#define VTD_MTRRCAP_REG_RW_MASK UINT64_C(0)
1813/** @} */
1814
1815
1816/** @name MTRR Default Type Register (MTRRDEF_REG).
1817 * In accordance with the Intel spec.
1818 * @{ */
1819/** TYPE: Default Memory Type. */
1820#define VTD_BF_MTRRDEF_REG_TYPE_SHIFT 0
1821#define VTD_BF_MTRRDEF_REG_TYPE_MASK UINT64_C(0x00000000000000ff)
1822/** R: Reserved (bits 9:8). */
1823#define VTD_BF_MTRRDEF_REG_RSVD_9_8_SHIFT 8
1824#define VTD_BF_MTRRDEF_REG_RSVD_9_8_MASK UINT64_C(0x0000000000000300)
1825/** FE: Fixed Range MTRR Enable. */
1826#define VTD_BF_MTRRDEF_REG_FE_SHIFT 10
1827#define VTD_BF_MTRRDEF_REG_FE_MASK UINT64_C(0x0000000000000400)
1828/** E: MTRR Enable. */
1829#define VTD_BF_MTRRDEF_REG_E_SHIFT 11
1830#define VTD_BF_MTRRDEF_REG_E_MASK UINT64_C(0x0000000000000800)
1831/** R: Reserved (bits 63:12). */
1832#define VTD_BF_MTRRDEF_REG_RSVD_63_12_SHIFT 12
1833#define VTD_BF_MTRRDEF_REG_RSVD_63_12_MASK UINT64_C(0xfffffffffffff000)
1834RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_MTRRDEF_REG_, UINT64_C(0), UINT64_MAX,
1835 (TYPE, RSVD_9_8, FE, E, RSVD_63_12));
1836
1837/** RW: Read/write mask. */
1838#define VTD_MTRRDEF_REG_RW_MASK ( VTD_BF_MTRRDEF_REG_TYPE_MASK | VTD_BF_MTRRDEF_REG_FE_MASK \
1839 | VTD_BF_MTRRDEF_REG_E_MASK)
1840/** @} */
1841
1842
1843/** @name Virtual Command Capability Register (VCCAP_REG).
1844 * In accordance with the Intel spec.
1845 * @{ */
1846/** PAS: PASID Support. */
1847#define VTD_BF_VCCAP_REG_PAS_SHIFT 0
1848#define VTD_BF_VCCAP_REG_PAS_MASK UINT64_C(0x0000000000000001)
1849/** R: Reserved (bits 63:1). */
1850#define VTD_BF_VCCAP_REG_RSVD_63_1_SHIFT 1
1851#define VTD_BF_VCCAP_REG_RSVD_63_1_MASK UINT64_C(0xfffffffffffffffe)
1852RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_VCCAP_REG_, UINT64_C(0), UINT64_MAX,
1853 (PAS, RSVD_63_1));
1854
1855/** RW: Read/write mask. */
1856#define VTD_VCCAP_REG_RW_MASK UINT64_C(0)
1857/** @} */
1858
1859
1860/** @name Virtual Command Extended Operand Register (VCMD_EO_REG).
1861 * In accordance with the Intel spec.
1862 * @{ */
1863/** OB: Operand B. */
1864#define VTD_BF_VCMD_EO_REG_OB_SHIFT 0
1865#define VTD_BF_VCMD_EO_REG_OB_MASK UINT32_C(0xffffffffffffffff)
1866
1867/** RW: Read/write mask. */
1868#define VTD_VCMD_EO_REG_RW_MASK VTD_BF_VCMD_EO_REG_OB_MASK
1869/** @} */
1870
1871
1872/** @name Virtual Command Register (VCMD_REG).
1873 * In accordance with the Intel spec.
1874 * @{ */
1875/** CMD: Command. */
1876#define VTD_BF_VCMD_REG_CMD_SHIFT 0
1877#define VTD_BF_VCMD_REG_CMD_MASK UINT64_C(0x00000000000000ff)
1878/** OP: Operand. */
1879#define VTD_BF_VCMD_REG_OP_SHIFT 8
1880#define VTD_BF_VCMD_REG_OP_MASK UINT64_C(0xffffffffffffff00)
1881RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_VCMD_REG_, UINT64_C(0), UINT64_MAX,
1882 (CMD, OP));
1883
1884/** RW: Read/write mask. */
1885#define VTD_VCMD_REG_RW_MASK (VTD_BF_VCMD_REG_CMD_MASK | VTD_BF_VCMD_REG_OP_MASK)
1886/** @} */
1887
1888
1889/** @name Virtual Command Response Register (VCRSP_REG).
1890 * In accordance with the Intel spec.
1891 * @{ */
1892/** IP: In Progress. */
1893#define VTD_BF_VCRSP_REG_IP_SHIFT 0
1894#define VTD_BF_VCRSP_REG_IP_MASK UINT64_C(0x0000000000000001)
1895/** SC: Status Code. */
1896#define VTD_BF_VCRSP_REG_SC_SHIFT 1
1897#define VTD_BF_VCRSP_REG_SC_MASK UINT64_C(0x0000000000000006)
1898/** R: Reserved (bits 7:3). */
1899#define VTD_BF_VCRSP_REG_RSVD_7_3_SHIFT 3
1900#define VTD_BF_VCRSP_REG_RSVD_7_3_MASK UINT64_C(0x00000000000000f8)
1901/** RSLT: Result. */
1902#define VTD_BF_VCRSP_REG_RSLT_SHIFT 8
1903#define VTD_BF_VCRSP_REG_RSLT_MASK UINT64_C(0xffffffffffffff00)
1904RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_VCRSP_REG_, UINT64_C(0), UINT64_MAX,
1905 (IP, SC, RSVD_7_3, RSLT));
1906
1907/** RW: Read/write mask. */
1908#define VTD_VCRSP_REG_RW_MASK UINT64_C(0)
1909/** @} */
1910
1911
1912/** @name Generic Invalidation Descriptor.
1913 * In accordance with the Intel spec.
1914 * Non-reserved fields here are common to all invalidation descriptors.
1915 * @{ */
1916/** Type (Lo). */
1917#define VTD_BF_0_GENERIC_INV_DSC_TYPE_LO_SHIFT 0
1918#define VTD_BF_0_GENERIC_INV_DSC_TYPE_LO_MASK UINT64_C(0x000000000000000f)
1919/** R: Reserved (bits 8:4). */
1920#define VTD_BF_0_GENERIC_INV_DSC_RSVD_8_4_SHIFT 4
1921#define VTD_BF_0_GENERIC_INV_DSC_RSVD_8_4_MASK UINT64_C(0x00000000000001f0)
1922/** Type (Hi). */
1923#define VTD_BF_0_GENERIC_INV_DSC_TYPE_HI_SHIFT 9
1924#define VTD_BF_0_GENERIC_INV_DSC_TYPE_HI_MASK UINT64_C(0x0000000000000e00)
1925/** R: Reserved (bits 63:12). */
1926#define VTD_BF_0_GENERIC_INV_DSC_RSVD_63_12_SHIFT 12
1927#define VTD_BF_0_GENERIC_INV_DSC_RSVD_63_12_MASK UINT64_C(0xfffffffffffff000)
1928RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_GENERIC_INV_DSC_, UINT64_C(0), UINT64_MAX,
1929 (TYPE_LO, RSVD_8_4, TYPE_HI, RSVD_63_12));
1930
1931/** GENERIC_INV_DSC: Type. */
1932#define VTD_GENERIC_INV_DSC_GET_TYPE(a) ((((a) & VTD_BF_0_GENERIC_INV_DSC_TYPE_HI_MASK) >> 5) \
1933 | ((a) & VTD_BF_0_GENERIC_INV_DSC_TYPE_LO_MASK))
1934/** @} */
1935
1936
1937/** @name Context-Cache Invalidation Descriptor (cc_inv_dsc).
1938 * In accordance with the Intel spec.
1939 * @{ */
1940/** Type (Lo). */
1941#define VTD_BF_0_CC_INV_DSC_TYPE_LO_SHIFT 0
1942#define VTD_BF_0_CC_INV_DSC_TYPE_LO_MASK UINT64_C(0x000000000000000f)
1943/** G: Granularity. */
1944#define VTD_BF_0_CC_INV_DSC_G_SHIFT 4
1945#define VTD_BF_0_CC_INV_DSC_G_MASK UINT64_C(0x0000000000000030)
1946/** R: Reserved (bits 8:6). */
1947#define VTD_BF_0_CC_INV_DSC_RSVD_8_6_SHIFT 6
1948#define VTD_BF_0_CC_INV_DSC_RSVD_8_6_MASK UINT64_C(0x00000000000001c0)
1949/** Type (Hi). */
1950#define VTD_BF_0_CC_INV_DSC_TYPE_HI_SHIFT 9
1951#define VTD_BF_0_CC_INV_DSC_TYPE_HI_MASK UINT64_C(0x0000000000000e00)
1952/** R: Reserved (bits 15:12). */
1953#define VTD_BF_0_CC_INV_DSC_RSVD_15_12_SHIFT 12
1954#define VTD_BF_0_CC_INV_DSC_RSVD_15_12_MASK UINT64_C(0x000000000000f000)
1955/** DID: Domain Id. */
1956#define VTD_BF_0_CC_INV_DSC_DID_SHIFT 16
1957#define VTD_BF_0_CC_INV_DSC_DID_MASK UINT64_C(0x00000000ffff0000)
1958/** SID: Source Id. */
1959#define VTD_BF_0_CC_INV_DSC_SID_SHIFT 32
1960#define VTD_BF_0_CC_INV_DSC_SID_MASK UINT64_C(0x0000ffff00000000)
1961/** FM: Function Mask. */
1962#define VTD_BF_0_CC_INV_DSC_FM_SHIFT 48
1963#define VTD_BF_0_CC_INV_DSC_FM_MASK UINT64_C(0x0003000000000000)
1964/** R: Reserved (bits 63:50). */
1965#define VTD_BF_0_CC_INV_DSC_RSVD_63_50_SHIFT 50
1966#define VTD_BF_0_CC_INV_DSC_RSVD_63_50_MASK UINT64_C(0xfffc000000000000)
1967RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_CC_INV_DSC_, UINT64_C(0), UINT64_MAX,
1968 (TYPE_LO, G, RSVD_8_6, TYPE_HI, RSVD_15_12, DID, SID, FM, RSVD_63_50));
1969/** @} */
1970
1971
1972/** @name PASID-Cache Invalidation Descriptor (pc_inv_dsc).
1973 * In accordance with the Intel spec.
1974 * @{ */
1975/** Type (Lo). */
1976#define VTD_BF_0_PC_INV_DSC_TYPE_LO_SHIFT 0
1977#define VTD_BF_0_PC_INV_DSC_TYPE_LO_MASK UINT64_C(0x000000000000000f)
1978/** G: Granularity. */
1979#define VTD_BF_0_PC_INV_DSC_G_SHIFT 4
1980#define VTD_BF_0_PC_INV_DSC_G_MASK UINT64_C(0x0000000000000030)
1981/** R: Reserved (bits 8:6). */
1982#define VTD_BF_0_PC_INV_DSC_RSVD_8_6_SHIFT 6
1983#define VTD_BF_0_PC_INV_DSC_RSVD_8_6_MASK UINT64_C(0x00000000000001c0)
1984/** Type (Hi). */
1985#define VTD_BF_0_PC_INV_DSC_TYPE_HI_SHIFT 9
1986#define VTD_BF_0_PC_INV_DSC_TYPE_HI_MASK UINT64_C(0x0000000000000e00)
1987/** R: Reserved (bits 15:12). */
1988#define VTD_BF_0_PC_INV_DSC_RSVD_15_12_SHIFT 12
1989#define VTD_BF_0_PC_INV_DSC_RSVD_15_12_MASK UINT64_C(0x000000000000f000)
1990/** DID: Domain Id. */
1991#define VTD_BF_0_PC_INV_DSC_DID_SHIFT 16
1992#define VTD_BF_0_PC_INV_DSC_DID_MASK UINT64_C(0x00000000ffff0000)
1993/** PASID: Process Address-Space Id. */
1994#define VTD_BF_0_PC_INV_DSC_PASID_SHIFT 32
1995#define VTD_BF_0_PC_INV_DSC_PASID_MASK UINT64_C(0x000fffff00000000)
1996/** R: Reserved (bits 63:52). */
1997#define VTD_BF_0_PC_INV_DSC_RSVD_63_52_SHIFT 52
1998#define VTD_BF_0_PC_INV_DSC_RSVD_63_52_MASK UINT64_C(0xfff0000000000000)
1999
2000RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_PC_INV_DSC_, UINT64_C(0), UINT64_MAX,
2001 (TYPE_LO, G, RSVD_8_6, TYPE_HI, RSVD_15_12, DID, PASID, RSVD_63_52));
2002/** @} */
2003
2004
2005/** @name IOTLB Invalidate Descriptor (iotlb_inv_dsc).
2006 * In accordance with the Intel spec.
2007 * @{ */
2008/** Type (Lo). */
2009#define VTD_BF_0_IOTLB_INV_DSC_TYPE_LO_SHIFT 0
2010#define VTD_BF_0_IOTLB_INV_DSC_TYPE_LO_MASK UINT64_C(0x000000000000000f)
2011/** G: Granularity. */
2012#define VTD_BF_0_IOTLB_INV_DSC_G_SHIFT 4
2013#define VTD_BF_0_IOTLB_INV_DSC_G_MASK UINT64_C(0x0000000000000030)
2014/** DW: Drain Writes. */
2015#define VTD_BF_0_IOTLB_INV_DSC_DW_SHIFT 6
2016#define VTD_BF_0_IOTLB_INV_DSC_DW_MASK UINT64_C(0x0000000000000040)
2017/** DR: Drain Reads. */
2018#define VTD_BF_0_IOTLB_INV_DSC_DR_SHIFT 7
2019#define VTD_BF_0_IOTLB_INV_DSC_DR_MASK UINT64_C(0x0000000000000080)
2020/** R: Reserved (bit 8). */
2021#define VTD_BF_0_IOTLB_INV_DSC_RSVD_8_SHIFT 8
2022#define VTD_BF_0_IOTLB_INV_DSC_RSVD_8_MASK UINT64_C(0x0000000000000100)
2023/** Type (Hi). */
2024#define VTD_BF_0_IOTLB_INV_DSC_TYPE_HI_SHIFT 9
2025#define VTD_BF_0_IOTLB_INV_DSC_TYPE_HI_MASK UINT64_C(0x0000000000000e00)
2026/** R: Reserved (bits 15:12). */
2027#define VTD_BF_0_IOTLB_INV_DSC_RSVD_15_12_SHIFT 12
2028#define VTD_BF_0_IOTLB_INV_DSC_RSVD_15_12_MASK UINT64_C(0x000000000000f000)
2029/** DID: Domain Id. */
2030#define VTD_BF_0_IOTLB_INV_DSC_DID_SHIFT 16
2031#define VTD_BF_0_IOTLB_INV_DSC_DID_MASK UINT64_C(0x00000000ffff0000)
2032/** R: Reserved (bits 63:32). */
2033#define VTD_BF_0_IOTLB_INV_DSC_RSVD_63_32_SHIFT 32
2034#define VTD_BF_0_IOTLB_INV_DSC_RSVD_63_32_MASK UINT64_C(0xffffffff00000000)
2035RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_IOTLB_INV_DSC_, UINT64_C(0), UINT64_MAX,
2036 (TYPE_LO, G, DW, DR, RSVD_8, TYPE_HI, RSVD_15_12, DID, RSVD_63_32));
2037
2038/** AM: Address Mask. */
2039#define VTD_BF_1_IOTLB_INV_DSC_AM_SHIFT 0
2040#define VTD_BF_1_IOTLB_INV_DSC_AM_MASK UINT64_C(0x000000000000003f)
2041/** IH: Invalidation Hint. */
2042#define VTD_BF_1_IOTLB_INV_DSC_IH_SHIFT 6
2043#define VTD_BF_1_IOTLB_INV_DSC_IH_MASK UINT64_C(0x0000000000000040)
2044/** R: Reserved (bits 11:7). */
2045#define VTD_BF_1_IOTLB_INV_DSC_RSVD_11_7_SHIFT 7
2046#define VTD_BF_1_IOTLB_INV_DSC_RSVD_11_7_MASK UINT64_C(0x0000000000000f80)
2047/** ADDR: Address. */
2048#define VTD_BF_1_IOTLB_INV_DSC_ADDR_SHIFT 12
2049#define VTD_BF_1_IOTLB_INV_DSC_ADDR_MASK UINT64_C(0xfffffffffffff000)
2050RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_IOTLB_INV_DSC_, UINT64_C(0), UINT64_MAX,
2051 (AM, IH, RSVD_11_7, ADDR));
2052/** @} */
2053
2054
2055/** @name PASID-based IOTLB Invalidate Descriptor (p_iotlb_inv_dsc).
2056 * In accordance with the Intel spec.
2057 * @{ */
2058/** Type (Lo). */
2059#define VTD_BF_0_P_IOTLB_INV_DSC_TYPE_LO_SHIFT 0
2060#define VTD_BF_0_P_IOTLB_INV_DSC_TYPE_LO_MASK UINT64_C(0x000000000000000f)
2061/** G: Granularity. */
2062#define VTD_BF_0_P_IOTLB_INV_DSC_G_SHIFT 4
2063#define VTD_BF_0_P_IOTLB_INV_DSC_G_MASK UINT64_C(0x0000000000000030)
2064/** R: Reserved (bits 8:6). */
2065#define VTD_BF_0_P_IOTLB_INV_DSC_RSVD_8_6_SHIFT 6
2066#define VTD_BF_0_P_IOTLB_INV_DSC_RSVD_8_6_MASK UINT64_C(0x00000000000001c0)
2067/** Type (Hi). */
2068#define VTD_BF_0_P_IOTLB_INV_DSC_TYPE_HI_SHIFT 9
2069#define VTD_BF_0_P_IOTLB_INV_DSC_TYPE_HI_MASK UINT64_C(0x0000000000000e00)
2070/** R: Reserved (bits 15:12). */
2071#define VTD_BF_0_P_IOTLB_INV_DSC_RSVD_15_12_SHIFT 12
2072#define VTD_BF_0_P_IOTLB_INV_DSC_RSVD_15_12_MASK UINT64_C(0x000000000000f000)
2073/** DID: Domain Id. */
2074#define VTD_BF_0_P_IOTLB_INV_DSC_DID_SHIFT 16
2075#define VTD_BF_0_P_IOTLB_INV_DSC_DID_MASK UINT64_C(0x00000000ffff0000)
2076/** PASID: Process Address-Space Id. */
2077#define VTD_BF_0_P_IOTLB_INV_DSC_PASID_SHIFT 32
2078#define VTD_BF_0_P_IOTLB_INV_DSC_PASID_MASK UINT64_C(0x000fffff00000000)
2079/** R: Reserved (bits 63:52). */
2080#define VTD_BF_0_P_IOTLB_INV_DSC_RSVD_63_52_SHIFT 52
2081#define VTD_BF_0_P_IOTLB_INV_DSC_RSVD_63_52_MASK UINT64_C(0xfff0000000000000)
2082RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_P_IOTLB_INV_DSC_, UINT64_C(0), UINT64_MAX,
2083 (TYPE_LO, G, RSVD_8_6, TYPE_HI, RSVD_15_12, DID, PASID, RSVD_63_52));
2084
2085
2086/** AM: Address Mask. */
2087#define VTD_BF_1_P_IOTLB_INV_DSC_AM_SHIFT 0
2088#define VTD_BF_1_P_IOTLB_INV_DSC_AM_MASK UINT64_C(0x000000000000003f)
2089/** IH: Invalidation Hint. */
2090#define VTD_BF_1_P_IOTLB_INV_DSC_IH_SHIFT 6
2091#define VTD_BF_1_P_IOTLB_INV_DSC_IH_MASK UINT64_C(0x0000000000000040)
2092/** R: Reserved (bits 11:7). */
2093#define VTD_BF_1_P_IOTLB_INV_DSC_RSVD_11_7_SHIFT 7
2094#define VTD_BF_1_P_IOTLB_INV_DSC_RSVD_11_7_MASK UINT64_C(0x0000000000000f80)
2095/** ADDR: Address. */
2096#define VTD_BF_1_P_IOTLB_INV_DSC_ADDR_SHIFT 12
2097#define VTD_BF_1_P_IOTLB_INV_DSC_ADDR_MASK UINT64_C(0xfffffffffffff000)
2098RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_P_IOTLB_INV_DSC_, UINT64_C(0), UINT64_MAX,
2099 (AM, IH, RSVD_11_7, ADDR));
2100/** @} */
2101
2102
2103/** @name Device-TLB Invalidate Descriptor (dev_tlb_inv_dsc).
2104 * In accordance with the Intel spec.
2105 * @{ */
2106/** Type (Lo). */
2107#define VTD_BF_0_DEV_TLB_INV_DSC_TYPE_LO_SHIFT 0
2108#define VTD_BF_0_DEV_TLB_INV_DSC_TYPE_LO_MASK UINT64_C(0x000000000000000f)
2109/** R: Reserved (bits 8:4). */
2110#define VTD_BF_0_DEV_TLB_INV_DSC_RSVD_8_4_SHIFT 4
2111#define VTD_BF_0_DEV_TLB_INV_DSC_RSVD_8_4_MASK UINT64_C(0x00000000000001f0)
2112/** Type (Hi). */
2113#define VTD_BF_0_DEV_TLB_INV_DSC_TYPE_HI_SHIFT 9
2114#define VTD_BF_0_DEV_TLB_INV_DSC_TYPE_HI_MASK UINT64_C(0x0000000000000e00)
2115/** PFSID: Physical-Function Source Id (Lo). */
2116#define VTD_BF_0_DEV_TLB_INV_DSC_PFSID_LO_SHIFT 12
2117#define VTD_BF_0_DEV_TLB_INV_DSC_PFSID_LO_MASK UINT64_C(0x000000000000f000)
2118/** MIP: Max Invalidations Pending. */
2119#define VTD_BF_0_DEV_TLB_INV_DSC_MIP_SHIFT 16
2120#define VTD_BF_0_DEV_TLB_INV_DSC_MIP_MASK UINT64_C(0x00000000001f0000)
2121/** R: Reserved (bits 31:21). */
2122#define VTD_BF_0_DEV_TLB_INV_DSC_RSVD_31_21_SHIFT 21
2123#define VTD_BF_0_DEV_TLB_INV_DSC_RSVD_31_21_MASK UINT64_C(0x00000000ffe00000)
2124/** SID: Source Id. */
2125#define VTD_BF_0_DEV_TLB_INV_DSC_SID_SHIFT 32
2126#define VTD_BF_0_DEV_TLB_INV_DSC_SID_MASK UINT64_C(0x0000ffff00000000)
2127/** R: Reserved (bits 51:48). */
2128#define VTD_BF_0_DEV_TLB_INV_DSC_RSVD_51_48_SHIFT 48
2129#define VTD_BF_0_DEV_TLB_INV_DSC_RSVD_51_48_MASK UINT64_C(0x000f000000000000)
2130/** PFSID: Physical-Function Source Id (Hi). */
2131#define VTD_BF_0_DEV_TLB_INV_DSC_PFSID_HI_SHIFT 52
2132#define VTD_BF_0_DEV_TLB_INV_DSC_PFSID_HI_MASK UINT64_C(0xfff0000000000000)
2133RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_DEV_TLB_INV_DSC_, UINT64_C(0), UINT64_MAX,
2134 (TYPE_LO, RSVD_8_4, TYPE_HI, PFSID_LO, MIP, RSVD_31_21, SID, RSVD_51_48, PFSID_HI));
2135
2136/** S: Size. */
2137#define VTD_BF_1_DEV_TLB_INV_DSC_S_SHIFT 0
2138#define VTD_BF_1_DEV_TLB_INV_DSC_S_MASK UINT64_C(0x0000000000000001)
2139/** R: Reserved (bits 11:1). */
2140#define VTD_BF_1_DEV_TLB_INV_DSC_RSVD_11_1_SHIFT 1
2141#define VTD_BF_1_DEV_TLB_INV_DSC_RSVD_11_1_MASK UINT64_C(0x0000000000000ffe)
2142/** ADDR: Address. */
2143#define VTD_BF_1_DEV_TLB_INV_DSC_ADDR_SHIFT 12
2144#define VTD_BF_1_DEV_TLB_INV_DSC_ADDR_MASK UINT64_C(0xfffffffffffff000)
2145RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_DEV_TLB_INV_DSC_, UINT64_C(0), UINT64_MAX,
2146 (S, RSVD_11_1, ADDR));
2147/** @} */
2148
2149
2150/** @name PASID-based-device-TLB Invalidate Descriptor (p_dev_tlb_inv_dsc).
2151 * In accordance with the Intel spec.
2152 * @{ */
2153/** Type (Lo). */
2154#define VTD_BF_0_P_DEV_TLB_INV_DSC_TYPE_LO_SHIFT 0
2155#define VTD_BF_0_P_DEV_TLB_INV_DSC_TYPE_LO_MASK UINT64_C(0x000000000000000f)
2156/** MIP: Max Invalidations Pending. */
2157#define VTD_BF_0_P_DEV_TLB_INV_DSC_MIP_SHIFT 4
2158#define VTD_BF_0_P_DEV_TLB_INV_DSC_MIP_MASK UINT64_C(0x00000000000001f0)
2159/** Type (Hi). */
2160#define VTD_BF_0_P_DEV_TLB_INV_DSC_TYPE_HI_SHIFT 9
2161#define VTD_BF_0_P_DEV_TLB_INV_DSC_TYPE_HI_MASK UINT64_C(0x0000000000000e00)
2162/** PFSID: Physical-Function Source Id (Lo). */
2163#define VTD_BF_0_P_DEV_TLB_INV_DSC_PFSID_LO_SHIFT 12
2164#define VTD_BF_0_P_DEV_TLB_INV_DSC_PFSID_LO_MASK UINT64_C(0x000000000000f000)
2165/** SID: Source Id. */
2166#define VTD_BF_0_P_DEV_TLB_INV_DSC_SID_SHIFT 16
2167#define VTD_BF_0_P_DEV_TLB_INV_DSC_SID_MASK UINT64_C(0x00000000ffff0000)
2168/** PASID: Process Address-Space Id. */
2169#define VTD_BF_0_P_DEV_TLB_INV_DSC_PASID_SHIFT 32
2170#define VTD_BF_0_P_DEV_TLB_INV_DSC_PASID_MASK UINT64_C(0x000fffff00000000)
2171/** PFSID: Physical-Function Source Id (Hi). */
2172#define VTD_BF_0_P_DEV_TLB_INV_DSC_PFSID_HI_SHIFT 52
2173#define VTD_BF_0_P_DEV_TLB_INV_DSC_PFSID_HI_MASK UINT64_C(0xfff0000000000000)
2174RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_P_DEV_TLB_INV_DSC_, UINT64_C(0), UINT64_MAX,
2175 (TYPE_LO, MIP, TYPE_HI, PFSID_LO, SID, PASID, PFSID_HI));
2176
2177/** G: Granularity. */
2178#define VTD_BF_1_P_DEV_TLB_INV_DSC_G_SHIFT 0
2179#define VTD_BF_1_P_DEV_TLB_INV_DSC_G_MASK UINT64_C(0x0000000000000001)
2180/** R: Reserved (bits 10:1). */
2181#define VTD_BF_1_P_DEV_TLB_INV_DSC_RSVD_10_1_SHIFT 1
2182#define VTD_BF_1_P_DEV_TLB_INV_DSC_RSVD_10_1_MASK UINT64_C(0x00000000000007fe)
2183/** S: Size. */
2184#define VTD_BF_1_P_DEV_TLB_INV_DSC_S_SHIFT 11
2185#define VTD_BF_1_P_DEV_TLB_INV_DSC_S_MASK UINT64_C(0x0000000000000800)
2186/** ADDR: Address. */
2187#define VTD_BF_1_P_DEV_TLB_INV_DSC_ADDR_SHIFT 12
2188#define VTD_BF_1_P_DEV_TLB_INV_DSC_ADDR_MASK UINT64_C(0xfffffffffffff000)
2189RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_P_DEV_TLB_INV_DSC_, UINT64_C(0), UINT64_MAX,
2190 (G, RSVD_10_1, S, ADDR));
2191/** @} */
2192
2193
2194/** @name Interrupt Entry Cache Invalidate Descriptor (iec_inv_dsc).
2195 * In accordance with the Intel spec.
2196 * @{ */
2197/** Type (Lo). */
2198#define VTD_BF_0_IEC_INV_DSC_TYPE_LO_SHIFT 0
2199#define VTD_BF_0_IEC_INV_DSC_TYPE_LO_MASK UINT64_C(0x000000000000000f)
2200/** G: Granularity. */
2201#define VTD_BF_0_IEC_INV_DSC_G_SHIFT 4
2202#define VTD_BF_0_IEC_INV_DSC_G_MASK UINT64_C(0x0000000000000010)
2203/** R: Reserved (bits 8:5). */
2204#define VTD_BF_0_IEC_INV_DSC_RSVD_8_5_SHIFT 5
2205#define VTD_BF_0_IEC_INV_DSC_RSVD_8_5_MASK UINT64_C(0x00000000000001e0)
2206/** Type (Hi). */
2207#define VTD_BF_0_IEC_INV_DSC_TYPE_HI_SHIFT 9
2208#define VTD_BF_0_IEC_INV_DSC_TYPE_HI_MASK UINT64_C(0x0000000000000e00)
2209/** R: Reserved (bits 26:12). */
2210#define VTD_BF_0_IEC_INV_DSC_RSVD_26_12_SHIFT 12
2211#define VTD_BF_0_IEC_INV_DSC_RSVD_26_12_MASK UINT64_C(0x0000000007fff000)
2212/** IM: Index Mask. */
2213#define VTD_BF_0_IEC_INV_DSC_IM_SHIFT 27
2214#define VTD_BF_0_IEC_INV_DSC_IM_MASK UINT64_C(0x00000000f8000000)
2215/** IIDX: Interrupt Index. */
2216#define VTD_BF_0_IEC_INV_DSC_IIDX_SHIFT 32
2217#define VTD_BF_0_IEC_INV_DSC_IIDX_MASK UINT64_C(0x0000ffff00000000)
2218/** R: Reserved (bits 63:48). */
2219#define VTD_BF_0_IEC_INV_DSC_RSVD_63_48_SHIFT 48
2220#define VTD_BF_0_IEC_INV_DSC_RSVD_63_48_MASK UINT64_C(0xffff000000000000)
2221RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_IEC_INV_DSC_, UINT64_C(0), UINT64_MAX,
2222 (TYPE_LO, G, RSVD_8_5, TYPE_HI, RSVD_26_12, IM, IIDX, RSVD_63_48));
2223/** @} */
2224
2225
2226/** @name Invalidation Wait Descriptor (inv_wait_dsc).
2227 * In accordance with the Intel spec.
2228 * @{ */
2229/** Type (Lo). */
2230#define VTD_BF_0_INV_WAIT_DSC_TYPE_LO_SHIFT 0
2231#define VTD_BF_0_INV_WAIT_DSC_TYPE_LO_MASK UINT64_C(0x000000000000000f)
2232/** IF: Interrupt Flag. */
2233#define VTD_BF_0_INV_WAIT_DSC_IF_SHIFT 4
2234#define VTD_BF_0_INV_WAIT_DSC_IF_MASK UINT64_C(0x0000000000000010)
2235/** SW: Status Write. */
2236#define VTD_BF_0_INV_WAIT_DSC_SW_SHIFT 5
2237#define VTD_BF_0_INV_WAIT_DSC_SW_MASK UINT64_C(0x0000000000000020)
2238/** FN: Fence Flag. */
2239#define VTD_BF_0_INV_WAIT_DSC_FN_SHIFT 6
2240#define VTD_BF_0_INV_WAIT_DSC_FN_MASK UINT64_C(0x0000000000000040)
2241/** PD: Page-Request Drain. */
2242#define VTD_BF_0_INV_WAIT_DSC_PD_SHIFT 7
2243#define VTD_BF_0_INV_WAIT_DSC_PD_MASK UINT64_C(0x0000000000000080)
2244/** R: Reserved (bit 8). */
2245#define VTD_BF_0_INV_WAIT_DSC_RSVD_8_SHIFT 8
2246#define VTD_BF_0_INV_WAIT_DSC_RSVD_8_MASK UINT64_C(0x0000000000000100)
2247/** Type (Hi). */
2248#define VTD_BF_0_INV_WAIT_DSC_TYPE_HI_SHIFT 9
2249#define VTD_BF_0_INV_WAIT_DSC_TYPE_HI_MASK UINT64_C(0x0000000000000e00)
2250/** R: Reserved (bits 31:12). */
2251#define VTD_BF_0_INV_WAIT_DSC_RSVD_31_12_SHIFT 12
2252#define VTD_BF_0_INV_WAIT_DSC_RSVD_31_12_MASK UINT64_C(0x00000000fffff000)
2253/** STDATA: Status Data. */
2254#define VTD_BF_0_INV_WAIT_DSC_STDATA_SHIFT 32
2255#define VTD_BF_0_INV_WAIT_DSC_STDATA_MASK UINT64_C(0xffffffff00000000)
2256RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_INV_WAIT_DSC_, UINT64_C(0), UINT64_MAX,
2257 (TYPE_LO, IF, SW, FN, PD, RSVD_8, TYPE_HI, RSVD_31_12, STDATA));
2258
2259/** R: Reserved (bits 1:0). */
2260#define VTD_BF_1_INV_WAIT_DSC_RSVD_1_0_SHIFT 0
2261#define VTD_BF_1_INV_WAIT_DSC_RSVD_1_0_MASK UINT64_C(0x0000000000000003)
2262/** STADDR: Status Address. */
2263#define VTD_BF_1_INV_WAIT_DSC_STADDR_SHIFT 2
2264#define VTD_BF_1_INV_WAIT_DSC_STADDR_MASK UINT64_C(0xfffffffffffffffc)
2265RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_INV_WAIT_DSC_, UINT64_C(0), UINT64_MAX,
2266 (RSVD_1_0, STADDR));
2267
2268/* INV_WAIT_DSC: Qword 0 valid mask. */
2269#define VTD_INV_WAIT_DSC_0_VALID_MASK ( VTD_BF_0_INV_WAIT_DSC_TYPE_LO_MASK \
2270 | VTD_BF_0_INV_WAIT_DSC_IF_MASK \
2271 | VTD_BF_0_INV_WAIT_DSC_SW_MASK \
2272 | VTD_BF_0_INV_WAIT_DSC_FN_MASK \
2273 | VTD_BF_0_INV_WAIT_DSC_PD_MASK \
2274 | VTD_BF_0_INV_WAIT_DSC_TYPE_HI_MASK \
2275 | VTD_BF_0_INV_WAIT_DSC_STDATA_MASK)
2276/* INV_WAIT_DSC: Qword 1 valid mask. */
2277#define VTD_INV_WAIT_DSC_1_VALID_MASK VTD_BF_1_INV_WAIT_DSC_STADDR_MASK
2278/** @} */
2279
2280
2281/** @name Invalidation descriptor types.
2282 * In accordance with the Intel spec.
2283 * @{ */
2284#define VTD_CC_INV_DSC_TYPE 1
2285#define VTD_IOTLB_INV_DSC_TYPE 2
2286#define VTD_DEV_TLB_INV_DSC_TYPE 3
2287#define VTD_IEC_INV_DSC_TYPE 4
2288#define VTD_INV_WAIT_DSC_TYPE 5
2289#define VTD_P_IOTLB_INV_DSC_TYPE 6
2290#define VTD_PC_INV_DSC_TYPE 7
2291#define VTD_P_DEV_TLB_INV_DSC_TYPE 8
2292/** @} */
2293
2294
2295/** @name Remappable Format Interrupt Request.
2296 * In accordance with the Intel spec.
2297 * @{ */
2298/** IGN: Ignored (bits 1:0). */
2299#define VTD_BF_REMAPPABLE_MSI_ADDR_IGN_1_0_SHIFT 0
2300#define VTD_BF_REMAPPABLE_MSI_ADDR_IGN_1_0_MASK UINT32_C(0x00000003)
2301/** Handle (Hi). */
2302#define VTD_BF_REMAPPABLE_MSI_ADDR_HANDLE_HI_SHIFT 2
2303#define VTD_BF_REMAPPABLE_MSI_ADDR_HANDLE_HI_MASK UINT32_C(0x00000004)
2304/** SHV: Subhandle Valid. */
2305#define VTD_BF_REMAPPABLE_MSI_ADDR_SHV_SHIFT 3
2306#define VTD_BF_REMAPPABLE_MSI_ADDR_SHV_MASK UINT32_C(0x00000008)
2307/** Interrupt format. */
2308#define VTD_BF_REMAPPABLE_MSI_ADDR_INTR_FMT_SHIFT 4
2309#define VTD_BF_REMAPPABLE_MSI_ADDR_INTR_FMT_MASK UINT32_C(0x00000010)
2310/** Handle (Lo). */
2311#define VTD_BF_REMAPPABLE_MSI_ADDR_HANDLE_LO_SHIFT 5
2312#define VTD_BF_REMAPPABLE_MSI_ADDR_HANDLE_LO_MASK UINT32_C(0x000fffe0)
2313/** Address. */
2314#define VTD_BF_REMAPPABLE_MSI_ADDR_ADDR_SHIFT 20
2315#define VTD_BF_REMAPPABLE_MSI_ADDR_ADDR_MASK UINT32_C(0xfff00000)
2316RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_REMAPPABLE_MSI_ADDR_, UINT32_C(0), UINT32_MAX,
2317 (IGN_1_0, HANDLE_HI, SHV, INTR_FMT, HANDLE_LO, ADDR));
2318
2319/** Subhandle. */
2320#define VTD_BF_REMAPPABLE_MSI_DATA_SUBHANDLE_SHIFT 0
2321#define VTD_BF_REMAPPABLE_MSI_DATA_SUBHANDLE_MASK UINT32_C(0x0000ffff)
2322/** R: Reserved (bits 31:16). */
2323#define VTD_BF_REMAPPABLE_MSI_DATA_RSVD_31_16_SHIFT 16
2324#define VTD_BF_REMAPPABLE_MSI_DATA_RSVD_31_16_MASK UINT32_C(0xffff0000)
2325RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_REMAPPABLE_MSI_DATA_, UINT32_C(0), UINT32_MAX,
2326 (SUBHANDLE, RSVD_31_16));
2327
2328/** Remappable MSI Address: Valid mask. */
2329#define VTD_REMAPPABLE_MSI_ADDR_VALID_MASK UINT32_MAX
2330/** Remappable MSI Data: Valid mask. */
2331#define VTD_REMAPPABLE_MSI_DATA_VALID_MASK VTD_BF_REMAPPABLE_MSI_DATA_SUBHANDLE_MASK
2332
2333/** Interrupt format: Compatibility. */
2334#define VTD_INTR_FORMAT_COMPAT 0
2335/** Interrupt format: Remappable. */
2336#define VTD_INTR_FORMAT_REMAPPABLE 1
2337/** @} */
2338
2339
2340/** @name Interrupt Remapping Fault Conditions.
2341 * In accordance with the Intel spec.
2342 * @{ */
2343typedef enum VTDIRFAULT
2344{
2345 /** Reserved bits invalid in remappable interrupt. */
2346 VTDIRFAULT_REMAPPABLE_INTR_RSVD = 0x20,
2347
2348 /** Interrupt index for remappable interrupt exceeds table size or referenced
2349 * address above host address width (HAW) */
2350 VTDIRFAULT_INTR_INDEX_INVALID = 0x21,
2351
2352 /** The IRTE is not present. */
2353 VTDIRFAULT_IRTE_NOT_PRESENT = 0x22,
2354 /** Reading IRTE from memory failed. */
2355 VTDIRFAULT_IRTE_READ_FAILED = 0x23,
2356 /** IRTE reserved bits invalid for an IRTE with Present bit set. */
2357 VTDIRFAULT_IRTE_PRESENT_RSVD = 0x24,
2358
2359 /** Compatibility format interrupt (CFI) blocked due to EIME being enabled or CFIs
2360 * were disabled. */
2361 VTDIRFAULT_CFI_BLOCKED = 0x25,
2362
2363 /** IRTE SID, SVT, SQ bits invalid for an IRTE with Present bit set. */
2364 VTDIRFAULT_IRTE_PRESENT_INVALID = 0x26,
2365
2366 /** Reading posted interrupt descriptor (PID) failed. */
2367 VTDIRFAULT_PID_READ_FAILED = 0x27,
2368 /** PID reserved bits invalid. */
2369 VTDIRFAULT_PID_RSVD = 0x28,
2370
2371 /** Untranslated interrupt requested (without PASID) is invalid. */
2372 VTDIRFAULT_IR_WITHOUT_PASID_INVALID = 0x29
2373} VTDIRFAULT;
2374AssertCompileSize(VTDIRFAULT, 4);
2375/** @} */
2376
2377
2378/** @name Address Translation Fault Conditions.
2379 * In accordance with the Intel spec.
2380 * @{ */
2381typedef enum VTDATFAULT
2382{
2383 /* Legacy root table faults (LRT). */
2384 VTDATFAULT_LRT_1 = 0x8,
2385 VTDATFAULT_LRT_2 = 0x1,
2386 VTDATFAULT_LRT_3 = 0xa,
2387
2388 /* Legacy Context-Table Faults (LCT). */
2389 VTDATFAULT_LCT_1 = 0x9,
2390 VTDATFAULT_LCT_2 = 0x2,
2391 VTDATFAULT_LCT_3 = 0xb,
2392 VTDATFAULT_LCT_4_0 = 0x3,
2393 VTDATFAULT_LCT_4_1 = 0x3,
2394 VTDATFAULT_LCT_4_2 = 0x3,
2395 VTDATFAULT_LCT_4_3 = 0x3,
2396 VTDATFAULT_LCT_5 = 0xd,
2397
2398 /* Legacy Second-Level Table Faults (LSL). */
2399 VTDATFAULT_LSL_1 = 0x7,
2400 VTDATFAULT_LSL_2 = 0xc,
2401
2402 /* Legacy General Faults (LGN). */
2403 VTDATFAULT_LGN_1_0 = 0x4,
2404 VTDATFAULT_LGN_1_1 = 0x4,
2405 VTDATFAULT_LGN_1_2 = 0x4,
2406 VTDATFAULT_LGN_1_3 = 0x4,
2407 VTDATFAULT_LGN_2 = 0x5,
2408 VTDATFAULT_LGN_3 = 0x6,
2409 VTDATFAULT_LGN_4 = 0xe,
2410
2411 /* Root-Table Address Register Faults (RTA). */
2412 VTDATFAULT_RTA_1_0 = 0x30,
2413 VTDATFAULT_RTA_1_1 = 0x30,
2414 VTDATFAULT_RTA_1_2 = 0x30,
2415 VTDATFAULT_RTA_1_3 = 0x30,
2416 VTDATFAULT_RTA_2 = 0x31,
2417 VTDATFAULT_RTA_3 = 0x32,
2418 VTDATFAULT_RTA_4 = 0x33,
2419
2420 /* Scalable-Mode Root-Table Faults (SRT). */
2421 VTDATFAULT_SRT_1 = 0x38,
2422 VTDATFAULT_SRT_2 = 0x39,
2423 VTDATFAULT_SRT_3 = 0x3a,
2424
2425 /* Scalable-Mode Context-Table Faults (SCT). */
2426 VTDATFAULT_SCT_1 = 0x40,
2427 VTDATFAULT_SCT_2 = 0x41,
2428 VTDATFAULT_SCT_3 = 0x42,
2429 VTDATFAULT_SCT_4_0 = 0x43,
2430 VTDATFAULT_SCT_4_1 = 0x43,
2431 VTDATFAULT_SCT_4_2 = 0x43,
2432 VTDATFAULT_SCT_5 = 0x44,
2433 VTDATFAULT_SCT_6 = 0x45,
2434 VTDATFAULT_SCT_7 = 0x46,
2435 VTDATFAULT_SCT_8 = 0x47,
2436 VTDATFAULT_SCT_9 = 0x48,
2437
2438 /* Scalable-Mode PASID-Directory Faults (SPD). */
2439 VTDATFAULT_SPD_1 = 0x50,
2440 VTDATFAULT_SPD_2 = 0x51,
2441 VTDATFAULT_SPD_3 = 0x52,
2442
2443 /* Scalable-Mode PASID-Table Faults (SPT). */
2444 VTDATFAULT_SPT_1 = 0x58,
2445 VTDATFAULT_SPT_2 = 0x59,
2446 VTDATFAULT_SPT_3 = 0x5a,
2447 VTDATFAULT_SPT_4_0 = 0x5b,
2448 VTDATFAULT_SPT_4_1 = 0x5b,
2449 VTDATFAULT_SPT_4_2 = 0x5b,
2450 VTDATFAULT_SPT_4_3 = 0x5b,
2451 VTDATFAULT_SPT_4_4 = 0x5b,
2452 VTDATFAULT_SPT_5 = 0x5c,
2453 VTDATFAULT_SPT_6 = 0x5d,
2454
2455 /* Scalable-Mode First-Level Table Faults (SFL). */
2456 VTDATFAULT_SFL_1 = 0x70,
2457 VTDATFAULT_SFL_2 = 0x71,
2458 VTDATFAULT_SFL_3 = 0x72,
2459 VTDATFAULT_SFL_4 = 0x73,
2460 VTDATFAULT_SFL_5 = 0x74,
2461 VTDATFAULT_SFL_6 = 0x75,
2462 VTDATFAULT_SFL_7 = 0x76,
2463 VTDATFAULT_SFL_8 = 0x77,
2464 VTDATFAULT_SFL_9 = 0x90,
2465 VTDATFAULT_SFL_10 = 0x91,
2466
2467 /* Scalable-Mode Second-Level Table Faults (SSL). */
2468 VTDATFAULT_SSL_1 = 0x78,
2469 VTDATFAULT_SSL_2 = 0x79,
2470 VTDATFAULT_SSL_3 = 0x7a,
2471 VTDATFAULT_SSL_4 = 0x7b,
2472 VTDATFAULT_SSL_5 = 0x7c,
2473 VTDATFAULT_SSL_6 = 0x7d,
2474
2475 /* Scalable-Mode General Faults (SGN). */
2476 VTDATFAULT_SGN_1 = 0x80,
2477 VTDATFAULT_SGN_2 = 0x81,
2478 VTDATFAULT_SGN_3 = 0x82,
2479 VTDATFAULT_SGN_4_0 = 0x83,
2480 VTDATFAULT_SGN_4_1 = 0x83,
2481 VTDATFAULT_SGN_4_2 = 0x83,
2482 VTDATFAULT_SGN_5 = 0x84,
2483 VTDATFAULT_SGN_6 = 0x85,
2484 VTDATFAULT_SGN_7 = 0x86,
2485 VTDATFAULT_SGN_8 = 0x87,
2486 VTDATFAULT_SGN_9 = 0x88,
2487 VTDATFAULT_SGN_10 = 0x89
2488} VTDATFAULT;
2489AssertCompileSize(VTDATFAULT, 4);
2490/** @} */
2491
2492
2493/** @name ACPI_DMAR_F_XXX: DMA Remapping Reporting Structure Flags.
2494 * In accordance with the Intel spec.
2495 * @{ */
2496/** INTR_REMAP: Interrupt remapping supported. */
2497#define ACPI_DMAR_F_INTR_REMAP RT_BIT(0)
2498/** X2APIC_OPT_OUT: Request system software to opt-out of enabling x2APIC. */
2499#define ACPI_DMAR_F_X2APIC_OPT_OUT RT_BIT(1)
2500/** DMA_CTRL_PLATFORM_OPT_IN_FLAG: Firmware initiated DMA restricted to reserved
2501 * memory regions (RMRR). */
2502#define ACPI_DMAR_F_DMA_CTRL_PLATFORM_OPT_IN RT_BIT(2)
2503/** @} */
2504
2505
2506/** @name ACPI_DRHD_F_XXX: DMA-Remapping Hardware Unit Definition Flags.
2507 * In accordance with the Intel spec.
2508 * @{ */
2509/** INCLUDE_PCI_ALL: All PCI devices under scope. */
2510#define ACPI_DRHD_F_INCLUDE_PCI_ALL RT_BIT(0)
2511/** @} */
2512
2513
2514/**
2515 * DRHD: DMA-Remapping Hardware Unit Definition.
2516 * In accordance with the Intel spec.
2517 */
2518#pragma pack(1)
2519typedef struct ACPIDRHD
2520{
2521 /** Type (must be 0=DRHD). */
2522 uint16_t uType;
2523 /** Length (must be 16 + size of device scope structure). */
2524 uint16_t cbLength;
2525 /** Flags, see ACPI_DRHD_F_XXX. */
2526 uint8_t fFlags;
2527 /** Reserved (MBZ). */
2528 uint8_t bRsvd;
2529 /** PCI segment number. */
2530 uint16_t uPciSegment;
2531 /** Register Base Address (MMIO). */
2532 uint64_t uRegBaseAddr;
2533 /* Device Scope[] Structures follow. */
2534} ACPIDRHD;
2535#pragma pack()
2536AssertCompileSize(ACPIDRHD, 16);
2537AssertCompileMemberOffset(ACPIDRHD, cbLength, 2);
2538AssertCompileMemberOffset(ACPIDRHD, fFlags, 4);
2539AssertCompileMemberOffset(ACPIDRHD, uPciSegment, 6);
2540AssertCompileMemberOffset(ACPIDRHD, uRegBaseAddr, 8);
2541
2542
2543/** @name ACPIDMARDEVSCOPE_TYPE_XXX: Device Type.
2544 * In accordance with the Intel spec.
2545 * @{ */
2546#define ACPIDMARDEVSCOPE_TYPE_PCI_ENDPOINT 1
2547#define ACPIDMARDEVSCOPE_TYPE_PCI_SUB_HIERARCHY 2
2548#define ACPIDMARDEVSCOPE_TYPE_IOAPIC 3
2549#define ACPIDMARDEVSCOPE_TYPE_MSI_CAP_HPET 4
2550#define ACPIDMARDEVSCOPE_TYPE_ACPI_NAMESPACE_DEV 5
2551/** @} */
2552
2553
2554/**
2555 * ACPI Device Scope Structure - PCI device path.
2556 * In accordance with the Intel spec.
2557 */
2558typedef struct ACPIDEVSCOPEPATH
2559{
2560 /** PCI device number. */
2561 uint8_t uDevice;
2562 /** PCI function number. */
2563 uint8_t uFunction;
2564} ACPIDEVSCOPEPATH;
2565AssertCompileSize(ACPIDEVSCOPEPATH, 2);
2566
2567
2568/**
2569 * Device Scope Structure.
2570 * In accordance with the Intel spec.
2571 */
2572#pragma pack(1)
2573typedef struct ACPIDMARDEVSCOPE
2574{
2575 /** Type, see ACPIDMARDEVSCOPE_TYPE_XXX. */
2576 uint8_t uType;
2577 /** Length (must be 6 + size of auPath field). */
2578 uint8_t cbLength;
2579 /** Reserved (MBZ). */
2580 uint8_t abRsvd[2];
2581 /** Enumeration ID (for I/O APIC, HPET and ACPI namespace devices). */
2582 uint8_t idEnum;
2583 /** First bus number for this device. */
2584 uint8_t uStartBusNum;
2585 /** Hierarchical path from the Host Bridge to the device. */
2586 ACPIDEVSCOPEPATH Path;
2587} ACPIDMARDEVSCOPE;
2588#pragma pack()
2589AssertCompileMemberOffset(ACPIDMARDEVSCOPE, cbLength, 1);
2590AssertCompileMemberOffset(ACPIDMARDEVSCOPE, idEnum, 4);
2591AssertCompileMemberOffset(ACPIDMARDEVSCOPE, uStartBusNum, 5);
2592AssertCompileMemberOffset(ACPIDMARDEVSCOPE, Path, 6);
2593
2594/** ACPI DMAR revision (not the OEM revision field).
2595 * In accordance with the Intel spec. */
2596#define ACPI_DMAR_REVISION 1
2597
2598
2599#endif /* !VBOX_INCLUDED_iommu_intel_h */
2600
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