VirtualBox

source: vbox/trunk/include/VBox/iommu-intel.h@ 89418

Last change on this file since 89418 was 89418, checked in by vboxsync, 4 years ago

Intel IOMMU: bugref:9967 Address translation, WIP.
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File size: 152.7 KB
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1/** @file
2 * IOMMU - Input/Output Memory Management Unit (Intel).
3 */
4
5/*
6 * Copyright (C) 2021 Oracle Corporation
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * The contents of this file may alternatively be used under the terms
17 * of the Common Development and Distribution License Version 1.0
18 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19 * VirtualBox OSE distribution, in which case the provisions of the
20 * CDDL are applicable instead of those of the GPL.
21 *
22 * You may elect to license modified versions of this file under the
23 * terms and conditions of either the GPL or the CDDL or both.
24 */
25
26#ifndef VBOX_INCLUDED_iommu_intel_h
27#define VBOX_INCLUDED_iommu_intel_h
28#ifndef RT_WITHOUT_PRAGMA_ONCE
29# pragma once
30#endif
31
32#include <iprt/assertcompile.h>
33#include <iprt/types.h>
34
35
36/**
37 * @name MMIO register offsets.
38 * In accordance with the Intel spec.
39 * @{
40 */
41#define VTD_MMIO_OFF_VER_REG 0x000 /**< Version. */
42#define VTD_MMIO_OFF_CAP_REG 0x008 /**< Capability. */
43#define VTD_MMIO_OFF_ECAP_REG 0x010 /**< Extended Capability. */
44#define VTD_MMIO_OFF_GCMD_REG 0x018 /**< Global Command. */
45#define VTD_MMIO_OFF_GSTS_REG 0x01c /**< Global Status. */
46#define VTD_MMIO_OFF_RTADDR_REG 0x020 /**< Root Table Address. */
47#define VTD_MMIO_OFF_CCMD_REG 0x028 /**< Context Command. */
48
49#define VTD_MMIO_OFF_FSTS_REG 0x034 /**< Fault Status.*/
50#define VTD_MMIO_OFF_FECTL_REG 0x038 /**< Fault Event Control.*/
51#define VTD_MMIO_OFF_FEDATA_REG 0x03c /**< Fault Event Data. */
52#define VTD_MMIO_OFF_FEADDR_REG 0x040 /**< Fault Event Address. */
53#define VTD_MMIO_OFF_FEUADDR_REG 0x044 /**< Fault Event Upper Address. */
54
55#define VTD_MMIO_OFF_AFLOG_REG 0x058 /**< Advance Fault Log. */
56
57#define VTD_MMIO_OFF_PMEN_REG 0x064 /**< Protected Memory Enable (PMEN). */
58#define VTD_MMIO_OFF_PLMBASE_REG 0x068 /**< Protected Low Memory Base. */
59#define VTD_MMIO_OFF_PLMLIMIT_REG 0x06c /**< Protected Low Memory Limit. */
60#define VTD_MMIO_OFF_PHMBASE_REG 0x070 /**< Protected High Memory Base. */
61#define VTD_MMIO_OFF_PHMLIMIT_REG 0x078 /**< Protected High Memory Limit. */
62
63#define VTD_MMIO_OFF_IQH_REG 0x080 /**< Invalidation Queue Head. */
64#define VTD_MMIO_OFF_IQT_REG 0x088 /**< Invalidation Queue Tail. */
65#define VTD_MMIO_OFF_IQA_REG 0x090 /**< Invalidation Queue Address. */
66#define VTD_MMIO_OFF_ICS_REG 0x09c /**< Invalidation Completion Status. */
67#define VTD_MMIO_OFF_IECTL_REG 0x0a0 /**< Invalidation Completion Event Control. */
68#define VTD_MMIO_OFF_IEDATA_REG 0x0a4 /**< Invalidation Completion Event Data. */
69#define VTD_MMIO_OFF_IEADDR_REG 0x0a8 /**< Invalidation Completion Event Address. */
70#define VTD_MMIO_OFF_IEUADDR_REG 0x0ac /**< Invalidation Completion Event Upper Address. */
71#define VTD_MMIO_OFF_IQERCD_REG 0x0b0 /**< Invalidation Queue Error Record. */
72
73#define VTD_MMIO_OFF_IRTA_REG 0x0b8 /**< Interrupt Remapping Table Address. */
74
75#define VTD_MMIO_OFF_PQH_REG 0x0c0 /**< Page Request Queue Head. */
76#define VTD_MMIO_OFF_PQT_REG 0x0c8 /**< Page Request Queue Tail. */
77#define VTD_MMIO_OFF_PQA_REG 0x0d0 /**< Page Request Queue Address. */
78#define VTD_MMIO_OFF_PRS_REG 0x0dc /**< Page Request Status. */
79#define VTD_MMIO_OFF_PECTL_REG 0x0e0 /**< Page Request Event Control. */
80#define VTD_MMIO_OFF_PEDATA_REG 0x0e4 /**< Page Request Event Data. */
81#define VTD_MMIO_OFF_PEADDR_REG 0x0e8 /**< Page Request Event Address. */
82#define VTD_MMIO_OFF_PEUADDR_REG 0x0ec /**< Page Request Event Upper Address. */
83
84#define VTD_MMIO_OFF_MTRRCAP_REG 0x100 /**< MTRR Capabliity. */
85#define VTD_MMIO_OFF_MTRRDEF_REG 0x108 /**< MTRR Default Type. */
86
87#define VTD_MMIO_OFF_MTRR_FIX64_00000_REG 0x120 /**< Fixed-range MTRR Register for 64K at 00000. */
88#define VTD_MMIO_OFF_MTRR_FIX16K_80000_REG 0x128 /**< Fixed-range MTRR Register for 16K at 80000. */
89#define VTD_MMIO_OFF_MTRR_FIX16K_A0000_REG 0x130 /**< Fixed-range MTRR Register for 16K at a0000. */
90#define VTD_MMIO_OFF_MTRR_FIX4K_C0000_REG 0x138 /**< Fixed-range MTRR Register for 4K at c0000. */
91#define VTD_MMIO_OFF_MTRR_FIX4K_C8000_REG 0x140 /**< Fixed-range MTRR Register for 4K at c8000. */
92#define VTD_MMIO_OFF_MTRR_FIX4K_D0000_REG 0x148 /**< Fixed-range MTRR Register for 4K at d0000. */
93#define VTD_MMIO_OFF_MTRR_FIX4K_D8000_REG 0x150 /**< Fixed-range MTRR Register for 4K at d8000. */
94#define VTD_MMIO_OFF_MTRR_FIX4K_E0000_REG 0x158 /**< Fixed-range MTRR Register for 4K at e0000. */
95#define VTD_MMIO_OFF_MTRR_FIX4K_E8000_REG 0x160 /**< Fixed-range MTRR Register for 4K at e8000. */
96#define VTD_MMIO_OFF_MTRR_FIX4K_F0000_REG 0x168 /**< Fixed-range MTRR Register for 4K at f0000. */
97#define VTD_MMIO_OFF_MTRR_FIX4K_F8000_REG 0x170 /**< Fixed-range MTRR Register for 4K at f8000. */
98
99#define VTD_MMIO_OFF_MTRR_PHYSBASE0_REG 0x180 /**< Variable-range MTRR Base 0. */
100#define VTD_MMIO_OFF_MTRR_PHYSMASK0_REG 0x188 /**< Variable-range MTRR Mask 0. */
101#define VTD_MMIO_OFF_MTRR_PHYSBASE1_REG 0x190 /**< Variable-range MTRR Base 1. */
102#define VTD_MMIO_OFF_MTRR_PHYSMASK1_REG 0x198 /**< Variable-range MTRR Mask 1. */
103#define VTD_MMIO_OFF_MTRR_PHYSBASE2_REG 0x1a0 /**< Variable-range MTRR Base 2. */
104#define VTD_MMIO_OFF_MTRR_PHYSMASK2_REG 0x1a8 /**< Variable-range MTRR Mask 2. */
105#define VTD_MMIO_OFF_MTRR_PHYSBASE3_REG 0x1b0 /**< Variable-range MTRR Base 3. */
106#define VTD_MMIO_OFF_MTRR_PHYSMASK3_REG 0x1b8 /**< Variable-range MTRR Mask 3. */
107#define VTD_MMIO_OFF_MTRR_PHYSBASE4_REG 0x1c0 /**< Variable-range MTRR Base 4. */
108#define VTD_MMIO_OFF_MTRR_PHYSMASK4_REG 0x1c8 /**< Variable-range MTRR Mask 4. */
109#define VTD_MMIO_OFF_MTRR_PHYSBASE5_REG 0x1d0 /**< Variable-range MTRR Base 5. */
110#define VTD_MMIO_OFF_MTRR_PHYSMASK5_REG 0x1d8 /**< Variable-range MTRR Mask 5. */
111#define VTD_MMIO_OFF_MTRR_PHYSBASE6_REG 0x1e0 /**< Variable-range MTRR Base 6. */
112#define VTD_MMIO_OFF_MTRR_PHYSMASK6_REG 0x1e8 /**< Variable-range MTRR Mask 6. */
113#define VTD_MMIO_OFF_MTRR_PHYSBASE7_REG 0x1f0 /**< Variable-range MTRR Base 7. */
114#define VTD_MMIO_OFF_MTRR_PHYSMASK7_REG 0x1f8 /**< Variable-range MTRR Mask 7. */
115#define VTD_MMIO_OFF_MTRR_PHYSBASE8_REG 0x200 /**< Variable-range MTRR Base 8. */
116#define VTD_MMIO_OFF_MTRR_PHYSMASK8_REG 0x208 /**< Variable-range MTRR Mask 8. */
117#define VTD_MMIO_OFF_MTRR_PHYSBASE9_REG 0x210 /**< Variable-range MTRR Base 9. */
118#define VTD_MMIO_OFF_MTRR_PHYSMASK9_REG 0x218 /**< Variable-range MTRR Mask 9. */
119
120#define VTD_MMIO_OFF_VCCAP_REG 0xe00 /**< Virtual Command Capability. */
121#define VTD_MMIO_OFF_VCMD_REG 0xe10 /**< Virtual Command. */
122#define VTD_MMIO_OFF_VCMDRSVD_REG 0xe18 /**< Reserved for future for Virtual Command. */
123#define VTD_MMIO_OFF_VCRSP_REG 0xe20 /**< Virtual Command Response. */
124#define VTD_MMIO_OFF_VCRSPRSVD_REG 0xe28 /**< Reserved for future for Virtual Command Response. */
125/** @} */
126
127
128/** @name Root Entry.
129 * In accordance with the Intel spec.
130 * @{ */
131/** P: Present. */
132#define VTD_BF_0_ROOT_ENTRY_P_SHIFT 0
133#define VTD_BF_0_ROOT_ENTRY_P_MASK UINT64_C(0x0000000000000001)
134/** R: Reserved (bits 11:1). */
135#define VTD_BF_0_ROOT_ENTRY_RSVD_11_1_SHIFT 1
136#define VTD_BF_0_ROOT_ENTRY_RSVD_11_1_MASK UINT64_C(0x0000000000000ffe)
137/** CTP: Context-Table Pointer. */
138#define VTD_BF_0_ROOT_ENTRY_CTP_SHIFT 12
139#define VTD_BF_0_ROOT_ENTRY_CTP_MASK UINT64_C(0xfffffffffffff000)
140RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_ROOT_ENTRY_, UINT64_C(0), UINT64_MAX,
141 (P, RSVD_11_1, CTP));
142
143/** Root Entry. */
144typedef struct VTD_ROOT_ENTRY_T
145{
146 /** The qwords in the root entry. */
147 uint64_t au64[2];
148} VTD_ROOT_ENTRY_T;
149/** Pointer to a root entry. */
150typedef VTD_ROOT_ENTRY_T *PVTD_ROOT_ENTRY_T;
151/** Pointer to a const root entry. */
152typedef VTD_ROOT_ENTRY_T const *PCVTD_ROOT_ENTRY_T;
153
154/* Root Entry: Qword 0 valid mask. */
155#define VTD_ROOT_ENTRY_0_VALID_MASK (VTD_BF_0_ROOT_ENTRY_P_MASK | VTD_BF_0_ROOT_ENTRY_CTP_MASK)
156/* Root Entry: Qword 1 valid mask. */
157#define VTD_ROOT_ENTRY_1_VALID_MASK UINT64_C(0)
158/** @} */
159
160
161/** @name Scalable-mode Root Entry.
162 * In accordance with the Intel spec.
163 * @{ */
164/** LP: Lower Present. */
165#define VTD_BF_0_SM_ROOT_ENTRY_LP_SHIFT 0
166#define VTD_BF_0_SM_ROOT_ENTRY_LP_MASK UINT64_C(0x0000000000000001)
167/** R: Reserved (bits 11:1). */
168#define VTD_BF_0_SM_ROOT_ENTRY_RSVD_11_1_SHIFT 1
169#define VTD_BF_0_SM_ROOT_ENTRY_RSVD_11_1_MASK UINT64_C(0x0000000000000ffe)
170/** LCTP: Lower Context-Table Pointer */
171#define VTD_BF_0_SM_ROOT_ENTRY_LCTP_SHIFT 12
172#define VTD_BF_0_SM_ROOT_ENTRY_LCTP_MASK UINT64_C(0xfffffffffffff000)
173RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_SM_ROOT_ENTRY_, UINT64_C(0), UINT64_MAX,
174 (LP, RSVD_11_1, LCTP));
175
176/** UP: Upper Present. */
177#define VTD_BF_1_SM_ROOT_ENTRY_UP_SHIFT 0
178#define VTD_BF_1_SM_ROOT_ENTRY_UP_MASK UINT64_C(0x0000000000000001)
179/** R: Reserved (bits 11:1). */
180#define VTD_BF_1_SM_ROOT_ENTRY_RSVD_11_1_SHIFT 1
181#define VTD_BF_1_SM_ROOT_ENTRY_RSVD_11_1_MASK UINT64_C(0x0000000000000ffe)
182/** UCTP: Upper Context-Table Pointer. */
183#define VTD_BF_1_SM_ROOT_ENTRY_UCTP_SHIFT 12
184#define VTD_BF_1_SM_ROOT_ENTRY_UCTP_MASK UINT64_C(0xfffffffffffff000)
185RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_SM_ROOT_ENTRY_, UINT64_C(0), UINT64_MAX,
186 (UP, RSVD_11_1, UCTP));
187
188/** Scalable-mode root entry. */
189typedef struct VTD_SM_ROOT_ENTRY_T
190{
191 /** The lower scalable-mode root entry. */
192 uint64_t uLower;
193 /** The upper scalable-mode root entry. */
194 uint64_t uUpper;
195} VTD_SM_ROOT_ENTRY_T;
196/** Pointer to a scalable-mode root entry. */
197typedef VTD_SM_ROOT_ENTRY_T *PVTD_SM_ROOT_ENTRY_T;
198/** Pointer to a const scalable-mode root entry. */
199typedef VTD_SM_ROOT_ENTRY_T const *PCVTD_SM_ROOT_ENTRY_T;
200/** @} */
201
202
203/** @name Context Entry.
204 * In accordance with the Intel spec.
205 * @{ */
206/** P: Present. */
207#define VTD_BF_0_CONTEXT_ENTRY_P_SHIFT 0
208#define VTD_BF_0_CONTEXT_ENTRY_P_MASK UINT64_C(0x0000000000000001)
209/** FPD: Fault Processing Disable. */
210#define VTD_BF_0_CONTEXT_ENTRY_FPD_SHIFT 1
211#define VTD_BF_0_CONTEXT_ENTRY_FPD_MASK UINT64_C(0x0000000000000002)
212/** TT: Translation Type. */
213#define VTD_BF_0_CONTEXT_ENTRY_TT_SHIFT 2
214#define VTD_BF_0_CONTEXT_ENTRY_TT_MASK UINT64_C(0x000000000000000c)
215/** R: Reserved (bits 11:4). */
216#define VTD_BF_0_CONTEXT_ENTRY_RSVD_11_4_SHIFT 4
217#define VTD_BF_0_CONTEXT_ENTRY_RSVD_11_4_MASK UINT64_C(0x0000000000000ff0)
218/** SLPTPTR: Second Level Page Translation Pointer. */
219#define VTD_BF_0_CONTEXT_ENTRY_SLPTPTR_SHIFT 12
220#define VTD_BF_0_CONTEXT_ENTRY_SLPTPTR_MASK UINT64_C(0xfffffffffffff000)
221RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_CONTEXT_ENTRY_, UINT64_C(0), UINT64_MAX,
222 (P, FPD, TT, RSVD_11_4, SLPTPTR));
223
224/** AW: Address Width. */
225#define VTD_BF_1_CONTEXT_ENTRY_AW_SHIFT 0
226#define VTD_BF_1_CONTEXT_ENTRY_AW_MASK UINT64_C(0x0000000000000007)
227/** IGN: Ignored (bits 6:3). */
228#define VTD_BF_1_CONTEXT_ENTRY_IGN_6_3_SHIFT 3
229#define VTD_BF_1_CONTEXT_ENTRY_IGN_6_3_MASK UINT64_C(0x0000000000000078)
230/** R: Reserved (bit 7). */
231#define VTD_BF_1_CONTEXT_ENTRY_RSVD_7_SHIFT 7
232#define VTD_BF_1_CONTEXT_ENTRY_RSVD_7_MASK UINT64_C(0x0000000000000080)
233/** DID: Domain Identifier. */
234#define VTD_BF_1_CONTEXT_ENTRY_DID_SHIFT 8
235#define VTD_BF_1_CONTEXT_ENTRY_DID_MASK UINT64_C(0x0000000000ffff00)
236/** R: Reserved (bits 63:24). */
237#define VTD_BF_1_CONTEXT_ENTRY_RSVD_63_24_SHIFT 24
238#define VTD_BF_1_CONTEXT_ENTRY_RSVD_63_24_MASK UINT64_C(0xffffffffff000000)
239RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_CONTEXT_ENTRY_, UINT64_C(0), UINT64_MAX,
240 (AW, IGN_6_3, RSVD_7, DID, RSVD_63_24));
241
242/** Context Entry. */
243typedef struct VTD_CONTEXT_ENTRY_T
244{
245 /** The qwords in the context entry. */
246 uint64_t au64[2];
247} VTD_CONTEXT_ENTRY_T;
248/** Pointer to a context entry. */
249typedef VTD_CONTEXT_ENTRY_T *PVTD_CONTEXT_ENTRY_T;
250/** Pointer to a const context entry. */
251typedef VTD_CONTEXT_ENTRY_T const *PCVTD_CONTEXT_ENTRY_T;
252
253/** Context Entry: Qword 0 valid mask. */
254#define VTD_CONTEXT_ENTRY_0_VALID_MASK ( VTD_BF_0_CONTEXT_ENTRY_P_MASK \
255 | VTD_BF_0_CONTEXT_ENTRY_FPD_MASK \
256 | VTD_BF_0_CONTEXT_ENTRY_TT_MASK \
257 | VTD_BF_0_CONTEXT_ENTRY_SLPTPTR_MASK)
258/** Context Entry: Qword 1 valid mask. */
259#define VTD_CONTEXT_ENTRY_1_VALID_MASK ( VTD_BF_1_CONTEXT_ENTRY_AW_MASK \
260 | VTD_BF_1_CONTEXT_ENTRY_IGN_6_3_MASK \
261 | VTD_BF_1_CONTEXT_ENTRY_DID_MASK)
262
263/** Translation Type: Untranslated requests uses second-level paging. */
264#define VTD_TT_UNTRANSLATED_SLP 0
265/** Translation Type: Untranslated requests requires device-TLB support. */
266#define VTD_TT_UNTRANSLATED_DEV_TLB 1
267/** Translation Type: Untranslated requests are pass-through. */
268#define VTD_TT_UNTRANSLATED_PT 2
269/** Translation Type: Reserved. */
270#define VTD_TT_RSVD 3
271/** @} */
272
273
274/** @name Scalable-mode Context Entry.
275 * In accordance with the Intel spec.
276 * @{ */
277/** P: Present. */
278#define VTD_BF_0_SM_CONTEXT_ENTRY_P_SHIFT 0
279#define VTD_BF_0_SM_CONTEXT_ENTRY_P_MASK UINT64_C(0x0000000000000001)
280/** FPD: Fault Processing Disable. */
281#define VTD_BF_0_SM_CONTEXT_ENTRY_FPD_SHIFT 1
282#define VTD_BF_0_SM_CONTEXT_ENTRY_FPD_MASK UINT64_C(0x0000000000000002)
283/** DTE: Device-TLB Enable. */
284#define VTD_BF_0_SM_CONTEXT_ENTRY_DTE_SHIFT 2
285#define VTD_BF_0_SM_CONTEXT_ENTRY_DTE_MASK UINT64_C(0x0000000000000004)
286/** PASIDE: PASID Enable. */
287#define VTD_BF_0_SM_CONTEXT_ENTRY_PASIDE_SHIFT 3
288#define VTD_BF_0_SM_CONTEXT_ENTRY_PASIDE_MASK UINT64_C(0x0000000000000008)
289/** PRE: Page Request Enable. */
290#define VTD_BF_0_SM_CONTEXT_ENTRY_PRE_SHIFT 4
291#define VTD_BF_0_SM_CONTEXT_ENTRY_PRE_MASK UINT64_C(0x0000000000000010)
292/** R: Reserved (bits 8:5). */
293#define VTD_BF_0_SM_CONTEXT_ENTRY_RSVD_8_5_SHIFT 5
294#define VTD_BF_0_SM_CONTEXT_ENTRY_RSVD_8_5_MASK UINT64_C(0x00000000000001e0)
295/** PDTS: PASID Directory Size. */
296#define VTD_BF_0_SM_CONTEXT_ENTRY_PDTS_SHIFT 9
297#define VTD_BF_0_SM_CONTEXT_ENTRY_PDTS_MASK UINT64_C(0x0000000000000e00)
298/** PASIDDIRPTR: PASID Directory Pointer. */
299#define VTD_BF_0_SM_CONTEXT_ENTRY_PASIDDIRPTR_SHIFT 12
300#define VTD_BF_0_SM_CONTEXT_ENTRY_PASIDDIRPTR_MASK UINT64_C(0xfffffffffffff000)
301RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_SM_CONTEXT_ENTRY_, UINT64_C(0), UINT64_MAX,
302 (P, FPD, DTE, PASIDE, PRE, RSVD_8_5, PDTS, PASIDDIRPTR));
303
304/** RID_PASID: Requested Id to PASID assignment. */
305#define VTD_BF_1_SM_CONTEXT_ENTRY_RID_PASID_SHIFT 0
306#define VTD_BF_1_SM_CONTEXT_ENTRY_RID_PASID_MASK UINT64_C(0x00000000000fffff)
307/** RID_PRIV: Requested Id to PrivilegeModeRequested assignment. */
308#define VTD_BF_1_SM_CONTEXT_ENTRY_RID_PRIV_SHIFT 20
309#define VTD_BF_1_SM_CONTEXT_ENTRY_RID_PRIV_MASK UINT64_C(0x0000000000100000)
310/** R: Reserved (bits 63:21). */
311#define VTD_BF_1_SM_CONTEXT_ENTRY_RSVD_63_21_SHIFT 21
312#define VTD_BF_1_SM_CONTEXT_ENTRY_RSVD_63_21_MASK UINT64_C(0xffffffffffe00000)
313RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_SM_CONTEXT_ENTRY_, UINT64_C(0), UINT64_MAX,
314 (RID_PASID, RID_PRIV, RSVD_63_21));
315
316/** Scalable-mode Context Entry. */
317typedef struct VTD_SM_CONTEXT_ENTRY_T
318{
319 /** The qwords in the scalable-mode context entry. */
320 uint64_t au64[4];
321} VTD_SM_CONTEXT_ENTRY_T;
322/** Pointer to a scalable-mode context entry. */
323typedef VTD_SM_CONTEXT_ENTRY_T *PVTD_SM_CONTEXT_ENTRY_T;
324/** Pointer to a const scalable-mode context entry. */
325typedef VTD_SM_CONTEXT_ENTRY_T const *PCVTD_SM_CONTEXT_ENTRY_T;
326/** @} */
327
328
329/** @name Scalable-mode PASID Directory Entry.
330 * In accordance with the Intel spec.
331 * @{ */
332/** P: Present. */
333#define VTD_BF_SM_PASID_DIR_ENTRY_P_SHIFT 0
334#define VTD_BF_SM_PASID_DIR_ENTRY_P_MASK UINT64_C(0x0000000000000001)
335/** FPD: Fault Processing Disable. */
336#define VTD_BF_SM_PASID_DIR_ENTRY_FPD_SHIFT 1
337#define VTD_BF_SM_PASID_DIR_ENTRY_FPD_MASK UINT64_C(0x0000000000000002)
338/** R: Reserved (bits 11:2). */
339#define VTD_BF_SM_PASID_DIR_ENTRY_RSVD_11_2_SHIFT 2
340#define VTD_BF_SM_PASID_DIR_ENTRY_RSVD_11_2_MASK UINT64_C(0x0000000000000ffc)
341/** SMPTBLPTR: Scalable Mode PASID Table Pointer. */
342#define VTD_BF_SM_PASID_DIR_ENTRY_SMPTBLPTR_SHIFT 12
343#define VTD_BF_SM_PASID_DIR_ENTRY_SMPTBLPTR_MASK UINT64_C(0xfffffffffffff000)
344RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_SM_PASID_DIR_ENTRY_, UINT64_C(0), UINT64_MAX,
345 (P, FPD, RSVD_11_2, SMPTBLPTR));
346
347/** Scalable-mode PASID Directory Entry. */
348typedef struct VTD_SM_PASID_DIR_ENTRY_T
349{
350 /** The scalable-mode PASID directory entry. */
351 uint64_t u;
352} VTD_SM_PASID_DIR_ENTRY_T;
353/** Pointer to a scalable-mode PASID directory entry. */
354typedef VTD_SM_PASID_DIR_ENTRY_T *PVTD_SM_PASID_DIR_ENTRY_T;
355/** Pointer to a const scalable-mode PASID directory entry. */
356typedef VTD_SM_PASID_DIR_ENTRY_T const *PCVTD_SM_PASID_DIR_ENTRY_T;
357/** @} */
358
359
360/** @name Scalable-mode PASID Table Entry.
361 * In accordance with the Intel spec.
362 * @{ */
363/** P: Present. */
364#define VTD_BF_0_SM_PASID_TBL_ENTRY_P_SHIFT 0
365#define VTD_BF_0_SM_PASID_TBL_ENTRY_P_MASK UINT64_C(0x0000000000000001)
366/** FPD: Fault Processing Disable. */
367#define VTD_BF_0_SM_PASID_TBL_ENTRY_FPD_SHIFT 1
368#define VTD_BF_0_SM_PASID_TBL_ENTRY_FPD_MASK UINT64_C(0x0000000000000002)
369/** AW: Address Width. */
370#define VTD_BF_0_SM_PASID_TBL_ENTRY_AW_SHIFT 2
371#define VTD_BF_0_SM_PASID_TBL_ENTRY_AW_MASK UINT64_C(0x000000000000001c)
372/** SLEE: Second-Level Execute Enable. */
373#define VTD_BF_0_SM_PASID_TBL_ENTRY_SLEE_SHIFT 5
374#define VTD_BF_0_SM_PASID_TBL_ENTRY_SLEE_MASK UINT64_C(0x0000000000000020)
375/** PGTT: PASID Granular Translation Type. */
376#define VTD_BF_0_SM_PASID_TBL_ENTRY_PGTT_SHIFT 6
377#define VTD_BF_0_SM_PASID_TBL_ENTRY_PGTT_MASK UINT64_C(0x00000000000001c0)
378/** SLADE: Second-Level Address/Dirty Enable. */
379#define VTD_BF_0_SM_PASID_TBL_ENTRY_SLADE_SHIFT 9
380#define VTD_BF_0_SM_PASID_TBL_ENTRY_SLADE_MASK UINT64_C(0x0000000000000200)
381/** R: Reserved (bits 11:10). */
382#define VTD_BF_0_SM_PASID_TBL_ENTRY_RSVD_11_10_SHIFT 10
383#define VTD_BF_0_SM_PASID_TBL_ENTRY_RSVD_11_10_MASK UINT64_C(0x0000000000000c00)
384/** SLPTPTR: Second-Level Page Table Pointer. */
385#define VTD_BF_0_SM_PASID_TBL_ENTRY_SLPTPTR_SHIFT 12
386#define VTD_BF_0_SM_PASID_TBL_ENTRY_SLPTPTR_MASK UINT64_C(0xfffffffffffff000)
387RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_SM_PASID_TBL_ENTRY_, UINT64_C(0), UINT64_MAX,
388 (P, FPD, AW, SLEE, PGTT, SLADE, RSVD_11_10, SLPTPTR));
389
390/** DID: Domain Identifer. */
391#define VTD_BF_1_SM_PASID_TBL_ENTRY_DID_SHIFT 0
392#define VTD_BF_1_SM_PASID_TBL_ENTRY_DID_MASK UINT64_C(0x000000000000ffff)
393/** R: Reserved (bits 22:16). */
394#define VTD_BF_1_SM_PASID_TBL_ENTRY_RSVD_22_16_SHIFT 16
395#define VTD_BF_1_SM_PASID_TBL_ENTRY_RSVD_22_16_MASK UINT64_C(0x00000000007f0000)
396/** PWSNP: Page-Walk Snoop. */
397#define VTD_BF_1_SM_PASID_TBL_ENTRY_PWSNP_SHIFT 23
398#define VTD_BF_1_SM_PASID_TBL_ENTRY_PWSNP_MASK UINT64_C(0x0000000000800000)
399/** PGSNP: Page Snoop. */
400#define VTD_BF_1_SM_PASID_TBL_ENTRY_PGSNP_SHIFT 24
401#define VTD_BF_1_SM_PASID_TBL_ENTRY_PGSNP_MASK UINT64_C(0x0000000001000000)
402/** CD: Cache Disable. */
403#define VTD_BF_1_SM_PASID_TBL_ENTRY_CD_SHIFT 25
404#define VTD_BF_1_SM_PASID_TBL_ENTRY_CD_MASK UINT64_C(0x0000000002000000)
405/** EMTE: Extended Memory Type Enable. */
406#define VTD_BF_1_SM_PASID_TBL_ENTRY_EMTE_SHIFT 26
407#define VTD_BF_1_SM_PASID_TBL_ENTRY_EMTE_MASK UINT64_C(0x0000000004000000)
408/** EMT: Extended Memory Type. */
409#define VTD_BF_1_SM_PASID_TBL_ENTRY_EMT_SHIFT 27
410#define VTD_BF_1_SM_PASID_TBL_ENTRY_EMT_MASK UINT64_C(0x0000000038000000)
411/** PWT: Page-Level Write Through. */
412#define VTD_BF_1_SM_PASID_TBL_ENTRY_PWT_SHIFT 30
413#define VTD_BF_1_SM_PASID_TBL_ENTRY_PWT_MASK UINT64_C(0x0000000040000000)
414/** PCD: Page-Level Cache Disable. */
415#define VTD_BF_1_SM_PASID_TBL_ENTRY_PCD_SHIFT 31
416#define VTD_BF_1_SM_PASID_TBL_ENTRY_PCD_MASK UINT64_C(0x0000000080000000)
417/** PAT: Page Attribute Table. */
418#define VTD_BF_1_SM_PASID_TBL_ENTRY_PAT_SHIFT 32
419#define VTD_BF_1_SM_PASID_TBL_ENTRY_PAT_MASK UINT64_C(0xffffffff00000000)
420RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_SM_PASID_TBL_ENTRY_, UINT64_C(0), UINT64_MAX,
421 (DID, RSVD_22_16, PWSNP, PGSNP, CD, EMTE, EMT, PWT, PCD, PAT));
422
423/** SRE: Supervisor Request Enable. */
424#define VTD_BF_2_SM_PASID_TBL_ENTRY_SRE_SHIFT 0
425#define VTD_BF_2_SM_PASID_TBL_ENTRY_SRE_MASK UINT64_C(0x0000000000000001)
426/** ERE: Execute Request Enable. */
427#define VTD_BF_2_SM_PASID_TBL_ENTRY_ERE_SHIFT 1
428#define VTD_BF_2_SM_PASID_TBL_ENTRY_ERE_MASK UINT64_C(0x0000000000000002)
429/** FLPM: First Level Paging Mode. */
430#define VTD_BF_2_SM_PASID_TBL_ENTRY_FLPM_SHIFT 2
431#define VTD_BF_2_SM_PASID_TBL_ENTRY_FLPM_MASK UINT64_C(0x000000000000000c)
432/** WPE: Write Protect Enable. */
433#define VTD_BF_2_SM_PASID_TBL_ENTRY_WPE_SHIFT 4
434#define VTD_BF_2_SM_PASID_TBL_ENTRY_WPE_MASK UINT64_C(0x0000000000000010)
435/** NXE: No-Execute Enable. */
436#define VTD_BF_2_SM_PASID_TBL_ENTRY_NXE_SHIFT 5
437#define VTD_BF_2_SM_PASID_TBL_ENTRY_NXE_MASK UINT64_C(0x0000000000000020)
438/** SMEP: Supervisor Mode Execute Prevent. */
439#define VTD_BF_2_SM_PASID_TBL_ENTRY_SMPE_SHIFT 6
440#define VTD_BF_2_SM_PASID_TBL_ENTRY_SMPE_MASK UINT64_C(0x0000000000000040)
441/** EAFE: Extended Accessed Flag Enable. */
442#define VTD_BF_2_SM_PASID_TBL_ENTRY_EAFE_SHIFT 7
443#define VTD_BF_2_SM_PASID_TBL_ENTRY_EAFE_MASK UINT64_C(0x0000000000000080)
444/** R: Reserved (bits 11:8). */
445#define VTD_BF_2_SM_PASID_TBL_ENTRY_RSVD_11_8_SHIFT 8
446#define VTD_BF_2_SM_PASID_TBL_ENTRY_RSVD_11_8_MASK UINT64_C(0x0000000000000f00)
447/** FLPTPTR: First Level Page Table Pointer. */
448#define VTD_BF_2_SM_PASID_TBL_ENTRY_FLPTPTR_SHIFT 12
449#define VTD_BF_2_SM_PASID_TBL_ENTRY_FLPTPTR_MASK UINT64_C(0xfffffffffffff000)
450RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_2_SM_PASID_TBL_ENTRY_, UINT64_C(0), UINT64_MAX,
451 (SRE, ERE, FLPM, WPE, NXE, SMPE, EAFE, RSVD_11_8, FLPTPTR));
452
453/** Scalable-mode PASID Table Entry. */
454typedef struct VTD_SM_PASID_TBL_ENTRY_T
455{
456 /** The qwords in the scalable-mode PASID table entry. */
457 uint64_t au64[8];
458} VTD_SM_PASID_TBL_ENTRY_T;
459/** Pointer to a scalable-mode PASID table entry. */
460typedef VTD_SM_PASID_TBL_ENTRY_T *PVTD_SM_PASID_TBL_ENTRY_T;
461/** Pointer to a const scalable-mode PASID table entry. */
462typedef VTD_SM_PASID_TBL_ENTRY_T const *PCVTD_SM_PASID_TBL_ENTRY_T;
463/** @} */
464
465
466/** @name First-Level Paging Entry.
467 * In accordance with the Intel spec.
468 * @{ */
469/** P: Present. */
470#define VTD_BF_FLP_ENTRY_P_SHIFT 0
471#define VTD_BF_FLP_ENTRY_P_MASK UINT64_C(0x0000000000000001)
472/** R/W: Read/Write. */
473#define VTD_BF_FLP_ENTRY_RW_SHIFT 1
474#define VTD_BF_FLP_ENTRY_RW_MASK UINT64_C(0x0000000000000002)
475/** U/S: User/Supervisor. */
476#define VTD_BF_FLP_ENTRY_US_SHIFT 2
477#define VTD_BF_FLP_ENTRY_US_MASK UINT64_C(0x0000000000000004)
478/** PWT: Page-Level Write Through. */
479#define VTD_BF_FLP_ENTRY_PWT_SHIFT 3
480#define VTD_BF_FLP_ENTRY_PWT_MASK UINT64_C(0x0000000000000008)
481/** PC: Page-Level Cache Disable. */
482#define VTD_BF_FLP_ENTRY_PCD_SHIFT 4
483#define VTD_BF_FLP_ENTRY_PCD_MASK UINT64_C(0x0000000000000010)
484/** A: Accessed. */
485#define VTD_BF_FLP_ENTRY_A_SHIFT 5
486#define VTD_BF_FLP_ENTRY_A_MASK UINT64_C(0x0000000000000020)
487/** IGN: Ignored (bit 6). */
488#define VTD_BF_FLP_ENTRY_IGN_6_SHIFT 6
489#define VTD_BF_FLP_ENTRY_IGN_6_MASK UINT64_C(0x0000000000000040)
490/** R: Reserved (bit 7). */
491#define VTD_BF_FLP_ENTRY_RSVD_7_SHIFT 7
492#define VTD_BF_FLP_ENTRY_RSVD_7_MASK UINT64_C(0x0000000000000080)
493/** IGN: Ignored (bits 9:8). */
494#define VTD_BF_FLP_ENTRY_IGN_9_8_SHIFT 8
495#define VTD_BF_FLP_ENTRY_IGN_9_8_MASK UINT64_C(0x0000000000000300)
496/** EA: Extended Accessed. */
497#define VTD_BF_FLP_ENTRY_EA_SHIFT 10
498#define VTD_BF_FLP_ENTRY_EA_MASK UINT64_C(0x0000000000000400)
499/** IGN: Ignored (bit 11). */
500#define VTD_BF_FLP_ENTRY_IGN_11_SHIFT 11
501#define VTD_BF_FLP_ENTRY_IGN_11_MASK UINT64_C(0x0000000000000800)
502/** ADDR: Address. */
503#define VTD_BF_FLP_ENTRY_ADDR_SHIFT 12
504#define VTD_BF_FLP_ENTRY_ADDR_MASK UINT64_C(0x000ffffffffff000)
505/** IGN: Ignored (bits 62:52). */
506#define VTD_BF_FLP_ENTRY_IGN_62_52_SHIFT 52
507#define VTD_BF_FLP_ENTRY_IGN_62_52_MASK UINT64_C(0x7ff0000000000000)
508/** XD: Execute Disabled. */
509#define VTD_BF_FLP_ENTRY_XD_SHIFT 63
510#define VTD_BF_FLP_ENTRY_XD_MASK UINT64_C(0x8000000000000000)
511RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_FLP_ENTRY_, UINT64_C(0), UINT64_MAX,
512 (P, RW, US, PWT, PCD, A, IGN_6, RSVD_7, IGN_9_8, EA, IGN_11, ADDR, IGN_62_52, XD));
513
514/** First-Level Paging Entry. */
515typedef uint64_t VTD_FLP_ENTRY_T;
516/** @} */
517
518
519/** @name Second-Level PML5E.
520 * In accordance with the Intel spec.
521 * @{ */
522/** R: Read. */
523#define VTD_BF_SL_PML5E_R_SHIFT 0
524#define VTD_BF_SL_PML5E_R_MASK UINT64_C(0x0000000000000001)
525/** W: Write. */
526#define VTD_BF_SL_PML5E_W_SHIFT 1
527#define VTD_BF_SL_PML5E_W_MASK UINT64_C(0x0000000000000002)
528/** X: Execute. */
529#define VTD_BF_SL_PML5E_X_SHIFT 2
530#define VTD_BF_SL_PML5E_X_MASK UINT64_C(0x0000000000000004)
531/** IGN: Ignored (bits 6:3). */
532#define VTD_BF_SL_PML5E_IGN_6_3_SHIFT 3
533#define VTD_BF_SL_PML5E_IGN_6_3_MASK UINT64_C(0x0000000000000078)
534/** R: Reserved (bit 7). */
535#define VTD_BF_SL_PML5E_RSVD_7_SHIFT 7
536#define VTD_BF_SL_PML5E_RSVD_7_MASK UINT64_C(0x0000000000000080)
537/** A: Accessed. */
538#define VTD_BF_SL_PML5E_A_SHIFT 8
539#define VTD_BF_SL_PML5E_A_MASK UINT64_C(0x0000000000000100)
540/** IGN: Ignored (bits 10:9). */
541#define VTD_BF_SL_PML5E_IGN_10_9_SHIFT 9
542#define VTD_BF_SL_PML5E_IGN_10_9_MASK UINT64_C(0x0000000000000600)
543/** R: Reserved (bit 11). */
544#define VTD_BF_SL_PML5E_RSVD_11_SHIFT 11
545#define VTD_BF_SL_PML5E_RSVD_11_MASK UINT64_C(0x0000000000000800)
546/** ADDR: Address. */
547#define VTD_BF_SL_PML5E_ADDR_SHIFT 12
548#define VTD_BF_SL_PML5E_ADDR_MASK UINT64_C(0x000ffffffffff000)
549/** IGN: Ignored (bits 61:52). */
550#define VTD_BF_SL_PML5E_IGN_61_52_SHIFT 52
551#define VTD_BF_SL_PML5E_IGN_61_52_MASK UINT64_C(0x3ff0000000000000)
552/** R: Reserved (bit 62). */
553#define VTD_BF_SL_PML5E_RSVD_62_SHIFT 62
554#define VTD_BF_SL_PML5E_RSVD_62_MASK UINT64_C(0x4000000000000000)
555/** IGN: Ignored (bit 63). */
556#define VTD_BF_SL_PML5E_IGN_63_SHIFT 63
557#define VTD_BF_SL_PML5E_IGN_63_MASK UINT64_C(0x8000000000000000)
558RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_SL_PML5E_, UINT64_C(0), UINT64_MAX,
559 (R, W, X, IGN_6_3, RSVD_7, A, IGN_10_9, RSVD_11, ADDR, IGN_61_52, RSVD_62, IGN_63));
560
561/** Second-level PML5E valid mask. */
562#define VTD_SL_PML5E_VALID_MASK ( VTD_BF_SL_PML5E_R_MASK | VTD_BF_SL_PML5E_W_MASK \
563 | VTD_BF_SL_PML5E_X_MASK | VTD_BF_SL_PML5E_IGN_6_3_MASK \
564 | VTD_BF_SL_PML5E_A_MASK | VTD_BF_SL_PML5E_IGN_10_9_MASK \
565 | VTD_BF_SL_PML5E_ADDR_MASK | VTD_BF_SL_PML5E_IGN_61_52_MASK \
566 | VTD_BF_SL_PML5E_IGN_63_MASK)
567/** @} */
568
569
570/** @name Second-Level PML4E.
571 * In accordance with the Intel spec.
572 * @{ */
573/** R: Read. */
574#define VTD_BF_SL_PML4E_R_SHIFT 0
575#define VTD_BF_SL_PML4E_R_MASK UINT64_C(0x0000000000000001)
576/** W: Write. */
577#define VTD_BF_SL_PML4E_W_SHIFT 1
578#define VTD_BF_SL_PML4E_W_MASK UINT64_C(0x0000000000000002)
579/** X: Execute. */
580#define VTD_BF_SL_PML4E_X_SHIFT 2
581#define VTD_BF_SL_PML4E_X_MASK UINT64_C(0x0000000000000004)
582/** IGN: Ignored (bits 6:3). */
583#define VTD_BF_SL_PML4E_IGN_6_3_SHIFT 3
584#define VTD_BF_SL_PML4E_IGN_6_3_MASK UINT64_C(0x0000000000000078)
585/** R: Reserved (bit 7). */
586#define VTD_BF_SL_PML4E_RSVD_7_SHIFT 7
587#define VTD_BF_SL_PML4E_RSVD_7_MASK UINT64_C(0x0000000000000080)
588/** A: Accessed. */
589#define VTD_BF_SL_PML4E_A_SHIFT 8
590#define VTD_BF_SL_PML4E_A_MASK UINT64_C(0x0000000000000100)
591/** IGN: Ignored (bits 10:9). */
592#define VTD_BF_SL_PML4E_IGN_10_9_SHIFT 9
593#define VTD_BF_SL_PML4E_IGN_10_9_MASK UINT64_C(0x0000000000000600)
594/** R: Reserved (bit 11). */
595#define VTD_BF_SL_PML4E_RSVD_11_SHIFT 11
596#define VTD_BF_SL_PML4E_RSVD_11_MASK UINT64_C(0x0000000000000800)
597/** ADDR: Address. */
598#define VTD_BF_SL_PML4E_ADDR_SHIFT 12
599#define VTD_BF_SL_PML4E_ADDR_MASK UINT64_C(0x000ffffffffff000)
600/** IGN: Ignored (bits 61:52). */
601#define VTD_BF_SL_PML4E_IGN_61_52_SHIFT 52
602#define VTD_BF_SL_PML4E_IGN_61_52_MASK UINT64_C(0x3ff0000000000000)
603/** R: Reserved (bit 62). */
604#define VTD_BF_SL_PML4E_RSVD_62_SHIFT 62
605#define VTD_BF_SL_PML4E_RSVD_62_MASK UINT64_C(0x4000000000000000)
606/** IGN: Ignored (bit 63). */
607#define VTD_BF_SL_PML4E_IGN_63_SHIFT 63
608#define VTD_BF_SL_PML4E_IGN_63_MASK UINT64_C(0x8000000000000000)
609RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_SL_PML4E_, UINT64_C(0), UINT64_MAX,
610 (R, W, X, IGN_6_3, RSVD_7, A, IGN_10_9, RSVD_11, ADDR, IGN_61_52, RSVD_62, IGN_63));
611
612/** Second-level PML4E valid mask. */
613#define VTD_SL_PML4E_VALID_MASK VTD_SL_PML5E_VALID_MASK
614/** @} */
615
616
617/** @name Second-Level PDPE (1GB Page).
618 * In accordance with the Intel spec.
619 * @{ */
620/** R: Read. */
621#define VTD_BF_SL_PDPE1G_R_SHIFT 0
622#define VTD_BF_SL_PDPE1G_R_MASK UINT64_C(0x0000000000000001)
623/** W: Write. */
624#define VTD_BF_SL_PDPE1G_W_SHIFT 1
625#define VTD_BF_SL_PDPE1G_W_MASK UINT64_C(0x0000000000000002)
626/** X: Execute. */
627#define VTD_BF_SL_PDPE1G_X_SHIFT 2
628#define VTD_BF_SL_PDPE1G_X_MASK UINT64_C(0x0000000000000004)
629/** EMT: Extended Memory Type. */
630#define VTD_BF_SL_PDPE1G_EMT_SHIFT 3
631#define VTD_BF_SL_PDPE1G_EMT_MASK UINT64_C(0x0000000000000038)
632/** IPAT: Ignore PAT (Page Attribute Table). */
633#define VTD_BF_SL_PDPE1G_IPAT_SHIFT 6
634#define VTD_BF_SL_PDPE1G_IPAT_MASK UINT64_C(0x0000000000000040)
635/** PS: Page Size (MB1). */
636#define VTD_BF_SL_PDPE1G_PS_SHIFT 7
637#define VTD_BF_SL_PDPE1G_PS_MASK UINT64_C(0x0000000000000080)
638/** A: Accessed. */
639#define VTD_BF_SL_PDPE1G_A_SHIFT 8
640#define VTD_BF_SL_PDPE1G_A_MASK UINT64_C(0x0000000000000100)
641/** D: Dirty. */
642#define VTD_BF_SL_PDPE1G_D_SHIFT 9
643#define VTD_BF_SL_PDPE1G_D_MASK UINT64_C(0x0000000000000200)
644/** IGN: Ignored (bit 10). */
645#define VTD_BF_SL_PDPE1G_IGN_10_SHIFT 10
646#define VTD_BF_SL_PDPE1G_IGN_10_MASK UINT64_C(0x0000000000000400)
647/** R: Reserved (bit 11). */
648#define VTD_BF_SL_PDPE1G_RSVD_11_SHIFT 11
649#define VTD_BF_SL_PDPE1G_RSVD_11_MASK UINT64_C(0x0000000000000800)
650/** R: Reserved (bits 29:12). */
651#define VTD_BF_SL_PDPE1G_RSVD_29_12_SHIFT 12
652#define VTD_BF_SL_PDPE1G_RSVD_29_12_MASK UINT64_C(0x000000003ffff000)
653/** ADDR: Address of 1GB page. */
654#define VTD_BF_SL_PDPE1G_ADDR_SHIFT 30
655#define VTD_BF_SL_PDPE1G_ADDR_MASK UINT64_C(0x000fffffc0000000)
656/** IGN: Ignored (bits 61:52). */
657#define VTD_BF_SL_PDPE1G_IGN_61_52_SHIFT 52
658#define VTD_BF_SL_PDPE1G_IGN_61_52_MASK UINT64_C(0x3ff0000000000000)
659/** R: Reserved (bit 62). */
660#define VTD_BF_SL_PDPE1G_RSVD_62_SHIFT 62
661#define VTD_BF_SL_PDPE1G_RSVD_62_MASK UINT64_C(0x4000000000000000)
662/** IGN: Ignored (bit 63). */
663#define VTD_BF_SL_PDPE1G_IGN_63_SHIFT 63
664#define VTD_BF_SL_PDPE1G_IGN_63_MASK UINT64_C(0x8000000000000000)
665RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_SL_PDPE1G_, UINT64_C(0), UINT64_MAX,
666 (R, W, X, EMT, IPAT, PS, A, D, IGN_10, RSVD_11, RSVD_29_12, ADDR, IGN_61_52, RSVD_62, IGN_63));
667
668/** Second-level PDPE (1GB Page) valid mask. */
669#define VTD_SL_PDPE1G_VALID_MASK ( VTD_BF_SL_PDPE1G_R_MASK | VTD_BF_SL_PDPE1G_W_MASK \
670 | VTD_BF_SL_PDPE1G_X_MASK | VTD_BF_SL_PDPE1G_EMT_MASK \
671 | VTD_BF_SL_PDPE1G_IPAT_MASK | VTD_BF_SL_PDPE1G_PS_MASK \
672 | VTD_BF_SL_PDPE1G_A_MASK | VTD_BF_SL_PDPE1G_D_MASK \
673 | VTD_BF_SL_PDPE1G_IGN_10_MASK | VTD_BF_SL_PDPE1G_ADDR_MASK \
674 | VTD_BF_SL_PDPE1G_IGN_61_52_MASK | VTD_BF_SL_PDPE1G_IGN_63_MASK)
675/** @} */
676
677
678/** @name Second-Level PDPE.
679 * In accordance with the Intel spec.
680 * @{ */
681/** R: Read. */
682#define VTD_BF_SL_PDPE_R_SHIFT 0
683#define VTD_BF_SL_PDPE_R_MASK UINT64_C(0x0000000000000001)
684/** W: Write. */
685#define VTD_BF_SL_PDPE_W_SHIFT 1
686#define VTD_BF_SL_PDPE_W_MASK UINT64_C(0x0000000000000002)
687/** X: Execute. */
688#define VTD_BF_SL_PDPE_X_SHIFT 2
689#define VTD_BF_SL_PDPE_X_MASK UINT64_C(0x0000000000000004)
690/** IGN: Ignored (bits 6:3). */
691#define VTD_BF_SL_PDPE_IGN_6_3_SHIFT 3
692#define VTD_BF_SL_PDPE_IGN_6_3_MASK UINT64_C(0x0000000000000078)
693/** PS: Page Size (MBZ). */
694#define VTD_BF_SL_PDPE_PS_SHIFT 7
695#define VTD_BF_SL_PDPE_PS_MASK UINT64_C(0x0000000000000080)
696/** A: Accessed. */
697#define VTD_BF_SL_PDPE_A_SHIFT 8
698#define VTD_BF_SL_PDPE_A_MASK UINT64_C(0x0000000000000100)
699/** IGN: Ignored (bits 10:9). */
700#define VTD_BF_SL_PDPE_IGN_10_9_SHIFT 9
701#define VTD_BF_SL_PDPE_IGN_10_9_MASK UINT64_C(0x0000000000000600)
702/** R: Reserved (bit 11). */
703#define VTD_BF_SL_PDPE_RSVD_11_SHIFT 11
704#define VTD_BF_SL_PDPE_RSVD_11_MASK UINT64_C(0x0000000000000800)
705/** ADDR: Address of second-level PDT. */
706#define VTD_BF_SL_PDPE_ADDR_SHIFT 12
707#define VTD_BF_SL_PDPE_ADDR_MASK UINT64_C(0x000ffffffffff000)
708/** IGN: Ignored (bits 61:52). */
709#define VTD_BF_SL_PDPE_IGN_61_52_SHIFT 52
710#define VTD_BF_SL_PDPE_IGN_61_52_MASK UINT64_C(0x3ff0000000000000)
711/** R: Reserved (bit 62). */
712#define VTD_BF_SL_PDPE_RSVD_62_SHIFT 62
713#define VTD_BF_SL_PDPE_RSVD_62_MASK UINT64_C(0x4000000000000000)
714/** IGN: Ignored (bit 63). */
715#define VTD_BF_SL_PDPE_IGN_63_SHIFT 63
716#define VTD_BF_SL_PDPE_IGN_63_MASK UINT64_C(0x8000000000000000)
717RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_SL_PDPE_, UINT64_C(0), UINT64_MAX,
718 (R, W, X, IGN_6_3, PS, A, IGN_10_9, RSVD_11, ADDR, IGN_61_52, RSVD_62, IGN_63));
719
720/** Second-level PDPE valid mask. */
721#define VTD_SL_PDPE_VALID_MASK ( VTD_BF_SL_PDPE_R_MASK | VTD_BF_SL_PDPE_W_MASK \
722 | VTD_BF_SL_PDPE_X_MASK | VTD_BF_SL_PDPE_IGN_6_3_MASK \
723 | VTD_BF_SL_PDPE_PS_MASK | VTD_BF_SL_PDPE_A_MASK \
724 | VTD_BF_SL_PDPE_IGN_10_9_MASK | VTD_BF_SL_PDPE_ADDR_MASK \
725 | VTD_BF_SL_PDPE_IGN_61_52_MASK | VTD_BF_SL_PDPE_IGN_63_MASK)
726/** @} */
727
728
729/** @name Second-Level PDE (2MB Page).
730 * In accordance with the Intel spec.
731 * @{ */
732/** R: Read. */
733#define VTD_BF_SL_PDE2M_R_SHIFT 0
734#define VTD_BF_SL_PDE2M_R_MASK UINT64_C(0x0000000000000001)
735/** W: Write. */
736#define VTD_BF_SL_PDE2M_W_SHIFT 1
737#define VTD_BF_SL_PDE2M_W_MASK UINT64_C(0x0000000000000002)
738/** X: Execute. */
739#define VTD_BF_SL_PDE2M_X_SHIFT 2
740#define VTD_BF_SL_PDE2M_X_MASK UINT64_C(0x0000000000000004)
741/** EMT: Extended Memory Type. */
742#define VTD_BF_SL_PDE2M_EMT_SHIFT 3
743#define VTD_BF_SL_PDE2M_EMT_MASK UINT64_C(0x0000000000000038)
744/** IPAT: Ignore PAT (Page Attribute Table). */
745#define VTD_BF_SL_PDE2M_IPAT_SHIFT 6
746#define VTD_BF_SL_PDE2M_IPAT_MASK UINT64_C(0x0000000000000040)
747/** PS: Page Size (MB1). */
748#define VTD_BF_SL_PDE2M_PS_SHIFT 7
749#define VTD_BF_SL_PDE2M_PS_MASK UINT64_C(0x0000000000000080)
750/** A: Accessed. */
751#define VTD_BF_SL_PDE2M_A_SHIFT 8
752#define VTD_BF_SL_PDE2M_A_MASK UINT64_C(0x0000000000000100)
753/** D: Dirty. */
754#define VTD_BF_SL_PDE2M_D_SHIFT 9
755#define VTD_BF_SL_PDE2M_D_MASK UINT64_C(0x0000000000000200)
756/** IGN: Ignored (bit 10). */
757#define VTD_BF_SL_PDE2M_IGN_10_SHIFT 10
758#define VTD_BF_SL_PDE2M_IGN_10_MASK UINT64_C(0x0000000000000400)
759/** R: Reserved (bit 11). */
760#define VTD_BF_SL_PDE2M_RSVD_11_SHIFT 11
761#define VTD_BF_SL_PDE2M_RSVD_11_MASK UINT64_C(0x0000000000000800)
762/** R: Reserved (bits 20:12). */
763#define VTD_BF_SL_PDE2M_RSVD_20_12_SHIFT 12
764#define VTD_BF_SL_PDE2M_RSVD_20_12_MASK UINT64_C(0x00000000001ff000)
765/** ADDR: Address of 2MB page. */
766#define VTD_BF_SL_PDE2M_ADDR_SHIFT 21
767#define VTD_BF_SL_PDE2M_ADDR_MASK UINT64_C(0x000fffffffe00000)
768/** IGN: Ignored (bits 61:52). */
769#define VTD_BF_SL_PDE2M_IGN_61_52_SHIFT 52
770#define VTD_BF_SL_PDE2M_IGN_61_52_MASK UINT64_C(0x3ff0000000000000)
771/** R: Reserved (bit 62). */
772#define VTD_BF_SL_PDE2M_RSVD_62_SHIFT 62
773#define VTD_BF_SL_PDE2M_RSVD_62_MASK UINT64_C(0x4000000000000000)
774/** IGN: Ignored (bit 63). */
775#define VTD_BF_SL_PDE2M_IGN_63_SHIFT 63
776#define VTD_BF_SL_PDE2M_IGN_63_MASK UINT64_C(0x8000000000000000)
777RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_SL_PDE2M_, UINT64_C(0), UINT64_MAX,
778 (R, W, X, EMT, IPAT, PS, A, D, IGN_10, RSVD_11, RSVD_20_12, ADDR, IGN_61_52, RSVD_62, IGN_63));
779
780/** Second-level PDE (2MB page) valid mask. */
781#define VTD_SL_PDE2M_VALID_MASK ( VTD_BF_SL_PDE2M_R_MASK | VTD_BF_SL_PDE2M_W_MASK \
782 | VTD_BF_SL_PDE2M_X_MASK | VTD_BF_SL_PDE2M_EMT_MASK \
783 | VTD_BF_SL_PDE2M_IPAT_MASK | VTD_BF_SL_PDE2M_PS_MASK \
784 | VTD_BF_SL_PDE2M_A_MASK | VTD_BF_SL_PDE2M_D_MASK \
785 | VTD_BF_SL_PDE2M_IGN_10_MASK | VTD_BF_SL_PDE2M_ADDR_MASK \
786 | VTD_BF_SL_PDE2M_IGN_61_52_MASK | VTD_BF_SL_PDE2M_IGN_63_MASK)
787/** @} */
788
789
790/** @name Second-Level PDE.
791 * In accordance with the Intel spec.
792 * @{ */
793/** R: Read. */
794#define VTD_BF_SL_PDE_R_SHIFT 0
795#define VTD_BF_SL_PDE_R_MASK UINT64_C(0x0000000000000001)
796/** W: Write. */
797#define VTD_BF_SL_PDE_W_SHIFT 1
798#define VTD_BF_SL_PDE_W_MASK UINT64_C(0x0000000000000002)
799/** X: Execute. */
800#define VTD_BF_SL_PDE_X_SHIFT 2
801#define VTD_BF_SL_PDE_X_MASK UINT64_C(0x0000000000000004)
802/** IGN: Ignored (bits 6:3). */
803#define VTD_BF_SL_PDE_IGN_6_3_SHIFT 3
804#define VTD_BF_SL_PDE_IGN_6_3_MASK UINT64_C(0x0000000000000078)
805/** PS: Page Size (MBZ). */
806#define VTD_BF_SL_PDE_PS_SHIFT 7
807#define VTD_BF_SL_PDE_PS_MASK UINT64_C(0x0000000000000080)
808/** A: Accessed. */
809#define VTD_BF_SL_PDE_A_SHIFT 8
810#define VTD_BF_SL_PDE_A_MASK UINT64_C(0x0000000000000100)
811/** IGN: Ignored (bits 10:9). */
812#define VTD_BF_SL_PDE_IGN_10_9_SHIFT 9
813#define VTD_BF_SL_PDE_IGN_10_9_MASK UINT64_C(0x0000000000000600)
814/** R: Reserved (bit 11). */
815#define VTD_BF_SL_PDE_RSVD_11_SHIFT 11
816#define VTD_BF_SL_PDE_RSVD_11_MASK UINT64_C(0x0000000000000800)
817/** ADDR: Address of second-level PT. */
818#define VTD_BF_SL_PDE_ADDR_SHIFT 12
819#define VTD_BF_SL_PDE_ADDR_MASK UINT64_C(0x000ffffffffff000)
820/** IGN: Ignored (bits 61:52). */
821#define VTD_BF_SL_PDE_IGN_61_52_SHIFT 52
822#define VTD_BF_SL_PDE_IGN_61_52_MASK UINT64_C(0x3ff0000000000000)
823/** R: Reserved (bit 62). */
824#define VTD_BF_SL_PDE_RSVD_62_SHIFT 62
825#define VTD_BF_SL_PDE_RSVD_62_MASK UINT64_C(0x4000000000000000)
826/** IGN: Ignored (bit 63). */
827#define VTD_BF_SL_PDE_IGN_63_SHIFT 63
828#define VTD_BF_SL_PDE_IGN_63_MASK UINT64_C(0x8000000000000000)
829RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_SL_PDE_, UINT64_C(0), UINT64_MAX,
830 (R, W, X, IGN_6_3, PS, A, IGN_10_9, RSVD_11, ADDR, IGN_61_52, RSVD_62, IGN_63));
831
832/** Second-level PDE valid mask. */
833#define VTD_SL_PDE_VALID_MASK ( VTD_BF_SL_PDE_R_MASK | VTD_BF_SL_PDE_W_MASK \
834 | VTD_BF_SL_PDE_X_MASK | VTD_BF_SL_PDE_IGN_6_3_MASK \
835 | VTD_BF_SL_PDE_PS_MASK | VTD_BF_SL_PDE_A_MASK \
836 | VTD_BF_SL_PDE_IGN_10_9_MASK | VTD_BF_SL_PDE_ADDR_MASK \
837 | VTD_BF_SL_PDE_IGN_61_52_MASK | VTD_BF_SL_PDE_IGN_63_MASK)
838/** @} */
839
840
841/** @name Second-Level PTE.
842 * In accordance with the Intel spec.
843 * @{ */
844/** R: Read. */
845#define VTD_BF_SL_PTE_R_SHIFT 0
846#define VTD_BF_SL_PTE_R_MASK UINT64_C(0x0000000000000001)
847/** W: Write. */
848#define VTD_BF_SL_PTE_W_SHIFT 1
849#define VTD_BF_SL_PTE_W_MASK UINT64_C(0x0000000000000002)
850/** X: Execute. */
851#define VTD_BF_SL_PTE_X_SHIFT 2
852#define VTD_BF_SL_PTE_X_MASK UINT64_C(0x0000000000000004)
853/** EMT: Extended Memory Type. */
854#define VTD_BF_SL_PTE_EMT_SHIFT 3
855#define VTD_BF_SL_PTE_EMT_MASK UINT64_C(0x0000000000000038)
856/** IPAT: Ignore PAT (Page Attribute Table). */
857#define VTD_BF_SL_PTE_IPAT_SHIFT 6
858#define VTD_BF_SL_PTE_IPAT_MASK UINT64_C(0x0000000000000040)
859/** IGN: Ignored (bit 7). */
860#define VTD_BF_SL_PTE_IGN_7_SHIFT 7
861#define VTD_BF_SL_PTE_IGN_7_MASK UINT64_C(0x0000000000000080)
862/** A: Accessed. */
863#define VTD_BF_SL_PTE_A_SHIFT 8
864#define VTD_BF_SL_PTE_A_MASK UINT64_C(0x0000000000000100)
865/** D: Dirty. */
866#define VTD_BF_SL_PTE_D_SHIFT 9
867#define VTD_BF_SL_PTE_D_MASK UINT64_C(0x0000000000000200)
868/** IGN: Ignored (bit 10). */
869#define VTD_BF_SL_PTE_IGN_10_SHIFT 10
870#define VTD_BF_SL_PTE_IGN_10_MASK UINT64_C(0x0000000000000400)
871/** R: Reserved (bit 11). */
872#define VTD_BF_SL_PTE_RSVD_11_SHIFT 11
873#define VTD_BF_SL_PTE_RSVD_11_MASK UINT64_C(0x0000000000000800)
874/** ADDR: Address of 4K page. */
875#define VTD_BF_SL_PTE_ADDR_SHIFT 12
876#define VTD_BF_SL_PTE_ADDR_MASK UINT64_C(0x000ffffffffff000)
877/** IGN: Ignored (bits 61:52). */
878#define VTD_BF_SL_PTE_IGN_61_52_SHIFT 52
879#define VTD_BF_SL_PTE_IGN_61_52_MASK UINT64_C(0x3ff0000000000000)
880/** R: Reserved (bit 62). */
881#define VTD_BF_SL_PTE_RSVD_62_SHIFT 62
882#define VTD_BF_SL_PTE_RSVD_62_MASK UINT64_C(0x4000000000000000)
883/** IGN: Ignored (bit 63). */
884#define VTD_BF_SL_PTE_IGN_63_SHIFT 63
885#define VTD_BF_SL_PTE_IGN_63_MASK UINT64_C(0x8000000000000000)
886RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_SL_PTE_, UINT64_C(0), UINT64_MAX,
887 (R, W, X, EMT, IPAT, IGN_7, A, D, IGN_10, RSVD_11, ADDR, IGN_61_52, RSVD_62, IGN_63));
888
889/** Second-level PTE valid mask. */
890#define VTD_SL_PTE_VALID_MASK ( VTD_BF_SL_PTE_R_MASK | VTD_BF_SL_PTE_W_MASK \
891 | VTD_BF_SL_PTE_X_MASK | VTD_BF_SL_PTE_EMT_MASK \
892 | VTD_BF_SL_PTE_IPAT_MASK | VTD_BF_SL_PTE_IGN_7_MASK \
893 | VTD_BF_SL_PTE_A_MASK | VTD_BF_SL_PTE_D_MASK \
894 | VTD_BF_SL_PTE_IGN_10_MASK | VTD_BF_SL_PTE_RSVD_11_MASK \
895 | VTD_BF_SL_PTE_ADDR_MASK | VTD_BF_SL_PTE_IGN_61_52_MASK \
896 | VTD_BF_SL_PTE_RSVD_62_MASK | VTD_BF_SL_PTE_IGN_63_MASK)
897/** @} */
898
899
900/** @name Second-Level Generic Paging Entry.
901 * In accordance with the Intel spec.
902 * @{ */
903/** Second-Level Paging Entry. */
904typedef uint64_t VTD_SLP_ENTRY_T;
905/** Pointer to a second-level paging entry. */
906typedef uint64_t *PVTD_SLP_ENTRY_T;
907/** Pointer to a const second-level paging entry. */
908typedef uint64_t const *CPVTD_SLP_ENTRY_T;
909/** @} */
910
911
912/** @name Fault Record.
913 * In accordance with the Intel spec.
914 * @{ */
915/** R: Reserved (bits 11:0). */
916#define VTD_BF_0_FAULT_RECORD_RSVD_11_0_SHIFT 0
917#define VTD_BF_0_FAULT_RECORD_RSVD_11_0_MASK UINT64_C(0x0000000000000fff)
918/** FI: Fault Information. */
919#define VTD_BF_0_FAULT_RECORD_FI_SHIFT 12
920#define VTD_BF_0_FAULT_RECORD_FI_MASK UINT64_C(0xfffffffffffff000)
921RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_FAULT_RECORD_, UINT64_C(0), UINT64_MAX,
922 (RSVD_11_0, FI));
923
924/** SID: Source identifier. */
925#define VTD_BF_1_FAULT_RECORD_SID_SHIFT 0
926#define VTD_BF_1_FAULT_RECORD_SID_MASK UINT64_C(0x000000000000ffff)
927/** R: Reserved (bits 28:16). */
928#define VTD_BF_1_FAULT_RECORD_RSVD_28_16_SHIFT 16
929#define VTD_BF_1_FAULT_RECORD_RSVD_28_16_MASK UINT64_C(0x000000001fff0000)
930/** PRIV: Privilege Mode Requested. */
931#define VTD_BF_1_FAULT_RECORD_PRIV_SHIFT 29
932#define VTD_BF_1_FAULT_RECORD_PRIV_MASK UINT64_C(0x0000000020000000)
933/** EXE: Execute Permission Requested. */
934#define VTD_BF_1_FAULT_RECORD_EXE_SHIFT 30
935#define VTD_BF_1_FAULT_RECORD_EXE_MASK UINT64_C(0x0000000040000000)
936/** PP: PASID Present. */
937#define VTD_BF_1_FAULT_RECORD_PP_SHIFT 31
938#define VTD_BF_1_FAULT_RECORD_PP_MASK UINT64_C(0x0000000080000000)
939/** FR: Fault Reason. */
940#define VTD_BF_1_FAULT_RECORD_FR_SHIFT 32
941#define VTD_BF_1_FAULT_RECORD_FR_MASK UINT64_C(0x000000ff00000000)
942/** PV: PASID Value. */
943#define VTD_BF_1_FAULT_RECORD_PV_SHIFT 40
944#define VTD_BF_1_FAULT_RECORD_PV_MASK UINT64_C(0x0fffff0000000000)
945/** AT: Address Type. */
946#define VTD_BF_1_FAULT_RECORD_AT_SHIFT 60
947#define VTD_BF_1_FAULT_RECORD_AT_MASK UINT64_C(0x3000000000000000)
948/** T: Type. */
949#define VTD_BF_1_FAULT_RECORD_T_SHIFT 62
950#define VTD_BF_1_FAULT_RECORD_T_MASK UINT64_C(0x4000000000000000)
951/** R: Reserved (bit 127). */
952#define VTD_BF_1_FAULT_RECORD_RSVD_63_SHIFT 63
953#define VTD_BF_1_FAULT_RECORD_RSVD_63_MASK UINT64_C(0x8000000000000000)
954RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_FAULT_RECORD_, UINT64_C(0), UINT64_MAX,
955 (SID, RSVD_28_16, PRIV, EXE, PP, FR, PV, AT, T, RSVD_63));
956
957/** Fault record. */
958typedef struct VTD_FAULT_RECORD_T
959{
960 /** The qwords in the fault record. */
961 uint64_t au64[2];
962} VTD_FAULT_RECORD_T;
963/** Pointer to a fault record. */
964typedef VTD_FAULT_RECORD_T *PVTD_FAULT_RECORD_T;
965/** Pointer to a const fault record. */
966typedef VTD_FAULT_RECORD_T const *PCVTD_FAULT_RECORD_T;
967/** @} */
968
969
970/** @name Interrupt Remapping Table Entry (IRTE) for Remapped Interrupts.
971 * In accordance with the Intel spec.
972 * @{ */
973/** P: Present. */
974#define VTD_BF_0_IRTE_P_SHIFT 0
975#define VTD_BF_0_IRTE_P_MASK UINT64_C(0x0000000000000001)
976/** FPD: Fault Processing Disable. */
977#define VTD_BF_0_IRTE_FPD_SHIFT 1
978#define VTD_BF_0_IRTE_FPD_MASK UINT64_C(0x0000000000000002)
979/** DM: Destination Mode (0=physical, 1=logical). */
980#define VTD_BF_0_IRTE_DM_SHIFT 2
981#define VTD_BF_0_IRTE_DM_MASK UINT64_C(0x0000000000000004)
982/** RH: Redirection Hint. */
983#define VTD_BF_0_IRTE_RH_SHIFT 3
984#define VTD_BF_0_IRTE_RH_MASK UINT64_C(0x0000000000000008)
985/** TM: Trigger Mode. */
986#define VTD_BF_0_IRTE_TM_SHIFT 4
987#define VTD_BF_0_IRTE_TM_MASK UINT64_C(0x0000000000000010)
988/** DLM: Delivery Mode. */
989#define VTD_BF_0_IRTE_DLM_SHIFT 5
990#define VTD_BF_0_IRTE_DLM_MASK UINT64_C(0x00000000000000e0)
991/** AVL: Available. */
992#define VTD_BF_0_IRTE_AVAIL_SHIFT 8
993#define VTD_BF_0_IRTE_AVAIL_MASK UINT64_C(0x0000000000000f00)
994/** R: Reserved (bits 14:12). */
995#define VTD_BF_0_IRTE_RSVD_14_12_SHIFT 12
996#define VTD_BF_0_IRTE_RSVD_14_12_MASK UINT64_C(0x0000000000007000)
997/** IM: IRTE Mode. */
998#define VTD_BF_0_IRTE_IM_SHIFT 15
999#define VTD_BF_0_IRTE_IM_MASK UINT64_C(0x0000000000008000)
1000/** V: Vector. */
1001#define VTD_BF_0_IRTE_V_SHIFT 16
1002#define VTD_BF_0_IRTE_V_MASK UINT64_C(0x0000000000ff0000)
1003/** R: Reserved (bits 31:24). */
1004#define VTD_BF_0_IRTE_RSVD_31_24_SHIFT 24
1005#define VTD_BF_0_IRTE_RSVD_31_24_MASK UINT64_C(0x00000000ff000000)
1006/** DST: Desination Id. */
1007#define VTD_BF_0_IRTE_DST_SHIFT 32
1008#define VTD_BF_0_IRTE_DST_MASK UINT64_C(0xffffffff00000000)
1009/** R: Reserved (bits 39:32) when EIME=0. */
1010#define VTD_BF_0_IRTE_RSVD_39_32_SHIFT 32
1011#define VTD_BF_0_IRTE_RSVD_39_32_MASK UINT64_C(0x000000ff00000000)
1012/** DST_XAPIC: Destination Id when EIME=0. */
1013#define VTD_BF_0_IRTE_DST_XAPIC_SHIFT 40
1014#define VTD_BF_0_IRTE_DST_XAPIC_MASK UINT64_C(0x0000ff0000000000)
1015/** R: Reserved (bits 63:48) when EIME=0. */
1016#define VTD_BF_0_IRTE_RSVD_63_48_SHIFT 48
1017#define VTD_BF_0_IRTE_RSVD_63_48_MASK UINT64_C(0xffff000000000000)
1018RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_IRTE_, UINT64_C(0), UINT64_MAX,
1019 (P, FPD, DM, RH, TM, DLM, AVAIL, RSVD_14_12, IM, V, RSVD_31_24, DST));
1020RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_IRTE_, UINT64_C(0), UINT64_MAX,
1021 (P, FPD, DM, RH, TM, DLM, AVAIL, RSVD_14_12, IM, V, RSVD_31_24, RSVD_39_32, DST_XAPIC, RSVD_63_48));
1022
1023/** SID: Source Identifier. */
1024#define VTD_BF_1_IRTE_SID_SHIFT 0
1025#define VTD_BF_1_IRTE_SID_MASK UINT64_C(0x000000000000ffff)
1026/** SQ: Source-Id Qualifier. */
1027#define VTD_BF_1_IRTE_SQ_SHIFT 16
1028#define VTD_BF_1_IRTE_SQ_MASK UINT64_C(0x0000000000030000)
1029/** SVT: Source Validation Type. */
1030#define VTD_BF_1_IRTE_SVT_SHIFT 18
1031#define VTD_BF_1_IRTE_SVT_MASK UINT64_C(0x00000000000c0000)
1032/** R: Reserved (bits 127:84). */
1033#define VTD_BF_1_IRTE_RSVD_63_20_SHIFT 20
1034#define VTD_BF_1_IRTE_RSVD_63_20_MASK UINT64_C(0xfffffffffff00000)
1035RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_IRTE_, UINT64_C(0), UINT64_MAX,
1036 (SID, SQ, SVT, RSVD_63_20));
1037
1038/** IRTE: Qword 0 valid mask when EIME=1. */
1039#define VTD_IRTE_0_X2APIC_VALID_MASK ( VTD_BF_0_IRTE_P_MASK | VTD_BF_0_IRTE_FPD_MASK \
1040 | VTD_BF_0_IRTE_DM_MASK | VTD_BF_0_IRTE_RH_MASK \
1041 | VTD_BF_0_IRTE_TM_MASK | VTD_BF_0_IRTE_DLM_MASK \
1042 | VTD_BF_0_IRTE_AVAIL_MASK | VTD_BF_0_IRTE_IM_MASK \
1043 | VTD_BF_0_IRTE_V_MASK | VTD_BF_0_IRTE_DST_MASK)
1044/** IRTE: Qword 0 valid mask when EIME=0. */
1045#define VTD_IRTE_0_XAPIC_VALID_MASK ( VTD_BF_0_IRTE_P_MASK | VTD_BF_0_IRTE_FPD_MASK \
1046 | VTD_BF_0_IRTE_DM_MASK | VTD_BF_0_IRTE_RH_MASK \
1047 | VTD_BF_0_IRTE_TM_MASK | VTD_BF_0_IRTE_DLM_MASK \
1048 | VTD_BF_0_IRTE_AVAIL_MASK | VTD_BF_0_IRTE_IM_MASK \
1049 | VTD_BF_0_IRTE_V_MASK | VTD_BF_0_IRTE_DST_XAPIC_MASK)
1050/** IRTE: Qword 1 valid mask. */
1051#define VTD_IRTE_1_VALID_MASK ( VTD_BF_1_IRTE_SID_MASK | VTD_BF_1_IRTE_SQ_MASK \
1052 | VTD_BF_1_IRTE_SVT_MASK)
1053
1054/** Interrupt Remapping Table Entry (IRTE) for remapped interrupts. */
1055typedef struct VTD_IRTE_T
1056{
1057 /** The qwords in the IRTE. */
1058 uint64_t au64[2];
1059} VTD_IRTE_T;
1060/** Pointer to an IRTE. */
1061typedef VTD_IRTE_T *PVTD_IRTE_T;
1062/** Pointer to a const IRTE. */
1063typedef VTD_IRTE_T const *PCVTD_IRTE_T;
1064
1065/** IRTE SVT: No validation required. */
1066#define VTD_IRTE_SVT_NONE 0
1067/** IRTE SVT: Validate using a mask derived from SID and SQT. */
1068#define VTD_IRTE_SVT_VALIDATE_MASK 1
1069/** IRTE SVT: Validate using Bus range in the SID. */
1070#define VTD_IRTE_SVT_VALIDATE_BUS_RANGE 2
1071/** IRTE SVT: Reserved. */
1072#define VTD_IRTE_SVT_VALIDATE_RSVD 3
1073/** @} */
1074
1075
1076/** @name Version Register (VER_REG).
1077 * In accordance with the Intel spec.
1078 * @{ */
1079/** Min: Minor Version Number. */
1080#define VTD_BF_VER_REG_MIN_SHIFT 0
1081#define VTD_BF_VER_REG_MIN_MASK UINT32_C(0x0000000f)
1082/** Max: Major Version Number. */
1083#define VTD_BF_VER_REG_MAX_SHIFT 4
1084#define VTD_BF_VER_REG_MAX_MASK UINT32_C(0x000000f0)
1085/** R: Reserved (bits 31:8). */
1086#define VTD_BF_VER_REG_RSVD_31_8_SHIFT 8
1087#define VTD_BF_VER_REG_RSVD_31_8_MASK UINT32_C(0xffffff00)
1088RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_VER_REG_, UINT32_C(0), UINT32_MAX,
1089 (MIN, MAX, RSVD_31_8));
1090/** RW: Read/write mask. */
1091#define VTD_VER_REG_RW_MASK UINT32_C(0)
1092/** @} */
1093
1094
1095/** @name Capability Register (CAP_REG).
1096 * In accordance with the Intel spec.
1097 * @{ */
1098/** ND: Number of domains supported. */
1099#define VTD_BF_CAP_REG_ND_SHIFT 0
1100#define VTD_BF_CAP_REG_ND_MASK UINT64_C(0x0000000000000007)
1101/** AFL: Advanced Fault Logging. */
1102#define VTD_BF_CAP_REG_AFL_SHIFT 3
1103#define VTD_BF_CAP_REG_AFL_MASK UINT64_C(0x0000000000000008)
1104/** RWBF: Required Write-Buffer Flushing. */
1105#define VTD_BF_CAP_REG_RWBF_SHIFT 4
1106#define VTD_BF_CAP_REG_RWBF_MASK UINT64_C(0x0000000000000010)
1107/** PLMR: Protected Low-Memory Region. */
1108#define VTD_BF_CAP_REG_PLMR_SHIFT 5
1109#define VTD_BF_CAP_REG_PLMR_MASK UINT64_C(0x0000000000000020)
1110/** PHMR: Protected High-Memory Region. */
1111#define VTD_BF_CAP_REG_PHMR_SHIFT 6
1112#define VTD_BF_CAP_REG_PHMR_MASK UINT64_C(0x0000000000000040)
1113/** CM: Caching Mode. */
1114#define VTD_BF_CAP_REG_CM_SHIFT 7
1115#define VTD_BF_CAP_REG_CM_MASK UINT64_C(0x0000000000000080)
1116/** SAGAW: Supported Adjusted Guest Address Widths. */
1117#define VTD_BF_CAP_REG_SAGAW_SHIFT 8
1118#define VTD_BF_CAP_REG_SAGAW_MASK UINT64_C(0x0000000000001f00)
1119/** R: Reserved (bits 15:13). */
1120#define VTD_BF_CAP_REG_RSVD_15_13_SHIFT 13
1121#define VTD_BF_CAP_REG_RSVD_15_13_MASK UINT64_C(0x000000000000e000)
1122/** MGAW: Maximum Guest Address Width. */
1123#define VTD_BF_CAP_REG_MGAW_SHIFT 16
1124#define VTD_BF_CAP_REG_MGAW_MASK UINT64_C(0x00000000003f0000)
1125/** ZLR: Zero Length Read. */
1126#define VTD_BF_CAP_REG_ZLR_SHIFT 22
1127#define VTD_BF_CAP_REG_ZLR_MASK UINT64_C(0x0000000000400000)
1128/** DEP: Deprecated MBZ. Reserved (bit 23). */
1129#define VTD_BF_CAP_REG_RSVD_23_SHIFT 23
1130#define VTD_BF_CAP_REG_RSVD_23_MASK UINT64_C(0x0000000000800000)
1131/** FRO: Fault-recording Register Offset. */
1132#define VTD_BF_CAP_REG_FRO_SHIFT 24
1133#define VTD_BF_CAP_REG_FRO_MASK UINT64_C(0x00000003ff000000)
1134/** SLLPS: Second Level Large Page Support. */
1135#define VTD_BF_CAP_REG_SLLPS_SHIFT 34
1136#define VTD_BF_CAP_REG_SLLPS_MASK UINT64_C(0x0000003c00000000)
1137/** R: Reserved (bit 38). */
1138#define VTD_BF_CAP_REG_RSVD_38_SHIFT 38
1139#define VTD_BF_CAP_REG_RSVD_38_MASK UINT64_C(0x0000004000000000)
1140/** PSI: Page Selective Invalidation. */
1141#define VTD_BF_CAP_REG_PSI_SHIFT 39
1142#define VTD_BF_CAP_REG_PSI_MASK UINT64_C(0x0000008000000000)
1143/** NFR: Number of Fault-recording Registers. */
1144#define VTD_BF_CAP_REG_NFR_SHIFT 40
1145#define VTD_BF_CAP_REG_NFR_MASK UINT64_C(0x0000ff0000000000)
1146/** MAMV: Maximum Address Mask Value. */
1147#define VTD_BF_CAP_REG_MAMV_SHIFT 48
1148#define VTD_BF_CAP_REG_MAMV_MASK UINT64_C(0x003f000000000000)
1149/** DWD: Write Draining. */
1150#define VTD_BF_CAP_REG_DWD_SHIFT 54
1151#define VTD_BF_CAP_REG_DWD_MASK UINT64_C(0x0040000000000000)
1152/** DRD: Read Draining. */
1153#define VTD_BF_CAP_REG_DRD_SHIFT 55
1154#define VTD_BF_CAP_REG_DRD_MASK UINT64_C(0x0080000000000000)
1155/** FL1GP: First Level 1 GB Page Support. */
1156#define VTD_BF_CAP_REG_FL1GP_SHIFT 56
1157#define VTD_BF_CAP_REG_FL1GP_MASK UINT64_C(0x0100000000000000)
1158/** R: Reserved (bits 58:57). */
1159#define VTD_BF_CAP_REG_RSVD_58_57_SHIFT 57
1160#define VTD_BF_CAP_REG_RSVD_58_57_MASK UINT64_C(0x0600000000000000)
1161/** PI: Posted Interrupt Support. */
1162#define VTD_BF_CAP_REG_PI_SHIFT 59
1163#define VTD_BF_CAP_REG_PI_MASK UINT64_C(0x0800000000000000)
1164/** FL5LP: First Level 5-level Paging Support. */
1165#define VTD_BF_CAP_REG_FL5LP_SHIFT 60
1166#define VTD_BF_CAP_REG_FL5LP_MASK UINT64_C(0x1000000000000000)
1167/** R: Reserved (bit 61). */
1168#define VTD_BF_CAP_REG_RSVD_61_SHIFT 61
1169#define VTD_BF_CAP_REG_RSVD_61_MASK UINT64_C(0x2000000000000000)
1170/** ESIRTPS: Enhanced Set Interrupt Root Table Pointer Support. */
1171#define VTD_BF_CAP_REG_ESIRTPS_SHIFT 62
1172#define VTD_BF_CAP_REG_ESIRTPS_MASK UINT64_C(0x4000000000000000)
1173/** : Enhanced Set Root Table Pointer Support. */
1174#define VTD_BF_CAP_REG_ESRTPS_SHIFT 63
1175#define VTD_BF_CAP_REG_ESRTPS_MASK UINT64_C(0x8000000000000000)
1176RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_CAP_REG_, UINT64_C(0), UINT64_MAX,
1177 (ND, AFL, RWBF, PLMR, PHMR, CM, SAGAW, RSVD_15_13, MGAW, ZLR, RSVD_23, FRO, SLLPS, RSVD_38, PSI, NFR,
1178 MAMV, DWD, DRD, FL1GP, RSVD_58_57, PI, FL5LP, RSVD_61, ESIRTPS, ESRTPS));
1179
1180/** RW: Read/write mask. */
1181#define VTD_CAP_REG_RW_MASK UINT64_C(0)
1182/** @} */
1183
1184
1185/** @name Extended Capability Register (ECAP_REG).
1186 * In accordance with the Intel spec.
1187 * @{ */
1188/** C: Page-walk Coherence. */
1189#define VTD_BF_ECAP_REG_C_SHIFT 0
1190#define VTD_BF_ECAP_REG_C_MASK UINT64_C(0x0000000000000001)
1191/** QI: Queued Invalidation Support. */
1192#define VTD_BF_ECAP_REG_QI_SHIFT 1
1193#define VTD_BF_ECAP_REG_QI_MASK UINT64_C(0x0000000000000002)
1194/** DT: Device-TLB Support. */
1195#define VTD_BF_ECAP_REG_DT_SHIFT 2
1196#define VTD_BF_ECAP_REG_DT_MASK UINT64_C(0x0000000000000004)
1197/** IR: Interrupt Remapping Support. */
1198#define VTD_BF_ECAP_REG_IR_SHIFT 3
1199#define VTD_BF_ECAP_REG_IR_MASK UINT64_C(0x0000000000000008)
1200/** EIM: Extended Interrupt Mode. */
1201#define VTD_BF_ECAP_REG_EIM_SHIFT 4
1202#define VTD_BF_ECAP_REG_EIM_MASK UINT64_C(0x0000000000000010)
1203/** DEP: Deprecated MBZ. Reserved (bit 5). */
1204#define VTD_BF_ECAP_REG_RSVD_5_SHIFT 5
1205#define VTD_BF_ECAP_REG_RSVD_5_MASK UINT64_C(0x0000000000000020)
1206/** PT: Pass Through. */
1207#define VTD_BF_ECAP_REG_PT_SHIFT 6
1208#define VTD_BF_ECAP_REG_PT_MASK UINT64_C(0x0000000000000040)
1209/** SC: Snoop Control. */
1210#define VTD_BF_ECAP_REG_SC_SHIFT 7
1211#define VTD_BF_ECAP_REG_SC_MASK UINT64_C(0x0000000000000080)
1212/** IRO: IOTLB Register Offset. */
1213#define VTD_BF_ECAP_REG_IRO_SHIFT 8
1214#define VTD_BF_ECAP_REG_IRO_MASK UINT64_C(0x000000000003ff00)
1215/** R: Reserved (bits 19:18). */
1216#define VTD_BF_ECAP_REG_RSVD_19_18_SHIFT 18
1217#define VTD_BF_ECAP_REG_RSVD_19_18_MASK UINT64_C(0x00000000000c0000)
1218/** MHMV: Maximum Handle Mask Value. */
1219#define VTD_BF_ECAP_REG_MHMV_SHIFT 20
1220#define VTD_BF_ECAP_REG_MHMV_MASK UINT64_C(0x0000000000f00000)
1221/** DEP: Deprecated MBZ. Reserved (bit 24). */
1222#define VTD_BF_ECAP_REG_RSVD_24_SHIFT 24
1223#define VTD_BF_ECAP_REG_RSVD_24_MASK UINT64_C(0x0000000001000000)
1224/** MTS: Memory Type Support. */
1225#define VTD_BF_ECAP_REG_MTS_SHIFT 25
1226#define VTD_BF_ECAP_REG_MTS_MASK UINT64_C(0x0000000002000000)
1227/** NEST: Nested Translation Support. */
1228#define VTD_BF_ECAP_REG_NEST_SHIFT 26
1229#define VTD_BF_ECAP_REG_NEST_MASK UINT64_C(0x0000000004000000)
1230/** R: Reserved (bit 27). */
1231#define VTD_BF_ECAP_REG_RSVD_27_SHIFT 27
1232#define VTD_BF_ECAP_REG_RSVD_27_MASK UINT64_C(0x0000000008000000)
1233/** DEP: Deprecated MBZ. Reserved (bit 28). */
1234#define VTD_BF_ECAP_REG_RSVD_28_SHIFT 28
1235#define VTD_BF_ECAP_REG_RSVD_28_MASK UINT64_C(0x0000000010000000)
1236/** PRS: Page Request Support. */
1237#define VTD_BF_ECAP_REG_PRS_SHIFT 29
1238#define VTD_BF_ECAP_REG_PRS_MASK UINT64_C(0x0000000020000000)
1239/** ERS: Execute Request Support. */
1240#define VTD_BF_ECAP_REG_ERS_SHIFT 30
1241#define VTD_BF_ECAP_REG_ERS_MASK UINT64_C(0x0000000040000000)
1242/** SRS: Supervisor Request Support. */
1243#define VTD_BF_ECAP_REG_SRS_SHIFT 31
1244#define VTD_BF_ECAP_REG_SRS_MASK UINT64_C(0x0000000080000000)
1245/** R: Reserved (bit 32). */
1246#define VTD_BF_ECAP_REG_RSVD_32_SHIFT 32
1247#define VTD_BF_ECAP_REG_RSVD_32_MASK UINT64_C(0x0000000100000000)
1248/** NWFS: No Write Flag Support. */
1249#define VTD_BF_ECAP_REG_NWFS_SHIFT 33
1250#define VTD_BF_ECAP_REG_NWFS_MASK UINT64_C(0x0000000200000000)
1251/** EAFS: Extended Accessed Flags Support. */
1252#define VTD_BF_ECAP_REG_EAFS_SHIFT 34
1253#define VTD_BF_ECAP_REG_EAFS_MASK UINT64_C(0x0000000400000000)
1254/** PSS: PASID Size Supported. */
1255#define VTD_BF_ECAP_REG_PSS_SHIFT 35
1256#define VTD_BF_ECAP_REG_PSS_MASK UINT64_C(0x000000f800000000)
1257/** PASID: Process Address Space ID Support. */
1258#define VTD_BF_ECAP_REG_PASID_SHIFT 40
1259#define VTD_BF_ECAP_REG_PASID_MASK UINT64_C(0x0000010000000000)
1260/** DIT: Device-TLB Invalidation Throttle. */
1261#define VTD_BF_ECAP_REG_DIT_SHIFT 41
1262#define VTD_BF_ECAP_REG_DIT_MASK UINT64_C(0x0000020000000000)
1263/** PDS: Page-request Drain Support. */
1264#define VTD_BF_ECAP_REG_PDS_SHIFT 42
1265#define VTD_BF_ECAP_REG_PDS_MASK UINT64_C(0x0000040000000000)
1266/** SMTS: Scalable-Mode Translation Support. */
1267#define VTD_BF_ECAP_REG_SMTS_SHIFT 43
1268#define VTD_BF_ECAP_REG_SMTS_MASK UINT64_C(0x0000080000000000)
1269/** VCS: Virtual Command Support. */
1270#define VTD_BF_ECAP_REG_VCS_SHIFT 44
1271#define VTD_BF_ECAP_REG_VCS_MASK UINT64_C(0x0000100000000000)
1272/** SLADS: Second-Level Accessed/Dirty Support. */
1273#define VTD_BF_ECAP_REG_SLADS_SHIFT 45
1274#define VTD_BF_ECAP_REG_SLADS_MASK UINT64_C(0x0000200000000000)
1275/** SLTS: Second-Level Translation Support. */
1276#define VTD_BF_ECAP_REG_SLTS_SHIFT 46
1277#define VTD_BF_ECAP_REG_SLTS_MASK UINT64_C(0x0000400000000000)
1278/** FLTS: First-Level Translation Support. */
1279#define VTD_BF_ECAP_REG_FLTS_SHIFT 47
1280#define VTD_BF_ECAP_REG_FLTS_MASK UINT64_C(0x0000800000000000)
1281/** SMPWCS: Scalable-Mode Page-Walk Coherency Support. */
1282#define VTD_BF_ECAP_REG_SMPWCS_SHIFT 48
1283#define VTD_BF_ECAP_REG_SMPWCS_MASK UINT64_C(0x0001000000000000)
1284/** RPS: RID-PASID Support. */
1285#define VTD_BF_ECAP_REG_RPS_SHIFT 49
1286#define VTD_BF_ECAP_REG_RPS_MASK UINT64_C(0x0002000000000000)
1287/** R: Reserved (bits 51:50). */
1288#define VTD_BF_ECAP_REG_RSVD_51_50_SHIFT 50
1289#define VTD_BF_ECAP_REG_RSVD_51_50_MASK UINT64_C(0x000c000000000000)
1290/** ADMS: Abort DMA Mode Support. */
1291#define VTD_BF_ECAP_REG_ADMS_SHIFT 52
1292#define VTD_BF_ECAP_REG_ADMS_MASK UINT64_C(0x0010000000000000)
1293/** RPRIVS: RID_PRIV Support. */
1294#define VTD_BF_ECAP_REG_RPRIVS_SHIFT 53
1295#define VTD_BF_ECAP_REG_RPRIVS_MASK UINT64_C(0x0020000000000000)
1296/** R: Reserved (bits 63:54). */
1297#define VTD_BF_ECAP_REG_RSVD_63_54_SHIFT 54
1298#define VTD_BF_ECAP_REG_RSVD_63_54_MASK UINT64_C(0xffc0000000000000)
1299RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_ECAP_REG_, UINT64_C(0), UINT64_MAX,
1300 (C, QI, DT, IR, EIM, RSVD_5, PT, SC, IRO, RSVD_19_18, MHMV, RSVD_24, MTS, NEST, RSVD_27, RSVD_28,
1301 PRS, ERS, SRS, RSVD_32, NWFS, EAFS, PSS, PASID, DIT, PDS, SMTS, VCS, SLADS, SLTS, FLTS, SMPWCS, RPS,
1302 RSVD_51_50, ADMS, RPRIVS, RSVD_63_54));
1303
1304/** RW: Read/write mask. */
1305#define VTD_ECAP_REG_RW_MASK UINT64_C(0)
1306/** @} */
1307
1308
1309/** @name Global Command Register (GCMD_REG).
1310 * In accordance with the Intel spec.
1311 * @{ */
1312/** R: Reserved (bits 22:0). */
1313#define VTD_BF_GCMD_REG_RSVD_22_0_SHIFT 0
1314#define VTD_BF_GCMD_REG_RSVD_22_0_MASK UINT32_C(0x007fffff)
1315/** CFI: Compatibility Format Interrupt. */
1316#define VTD_BF_GCMD_REG_CFI_SHIFT 23
1317#define VTD_BF_GCMD_REG_CFI_MASK UINT32_C(0x00800000)
1318/** SIRTP: Set Interrupt Table Remap Pointer. */
1319#define VTD_BF_GCMD_REG_SIRTP_SHIFT 24
1320#define VTD_BF_GCMD_REG_SIRTP_MASK UINT32_C(0x01000000)
1321/** IRE: Interrupt Remap Enable. */
1322#define VTD_BF_GCMD_REG_IRE_SHIFT 25
1323#define VTD_BF_GCMD_REG_IRE_MASK UINT32_C(0x02000000)
1324/** QIE: Queued Invalidation Enable. */
1325#define VTD_BF_GCMD_REG_QIE_SHIFT 26
1326#define VTD_BF_GCMD_REG_QIE_MASK UINT32_C(0x04000000)
1327/** WBF: Write Buffer Flush. */
1328#define VTD_BF_GCMD_REG_WBF_SHIFT 27
1329#define VTD_BF_GCMD_REG_WBF_MASK UINT32_C(0x08000000)
1330/** EAFL: Enable Advance Fault Logging. */
1331#define VTD_BF_GCMD_REG_EAFL_SHIFT 28
1332#define VTD_BF_GCMD_REG_EAFL_MASK UINT32_C(0x10000000)
1333/** SFL: Set Fault Log. */
1334#define VTD_BF_GCMD_REG_SFL_SHIFT 29
1335#define VTD_BF_GCMD_REG_SFL_MASK UINT32_C(0x20000000)
1336/** SRTP: Set Root Table Pointer. */
1337#define VTD_BF_GCMD_REG_SRTP_SHIFT 30
1338#define VTD_BF_GCMD_REG_SRTP_MASK UINT32_C(0x40000000)
1339/** TE: Translation Enable. */
1340#define VTD_BF_GCMD_REG_TE_SHIFT 31
1341#define VTD_BF_GCMD_REG_TE_MASK UINT32_C(0x80000000)
1342RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_GCMD_REG_, UINT32_C(0), UINT32_MAX,
1343 (RSVD_22_0, CFI, SIRTP, IRE, QIE, WBF, EAFL, SFL, SRTP, TE));
1344
1345/** RW: Read/write mask. */
1346#define VTD_GCMD_REG_RW_MASK ( VTD_BF_GCMD_REG_TE_MASK | VTD_BF_GCMD_REG_SRTP_MASK \
1347 | VTD_BF_GCMD_REG_SFL_MASK | VTD_BF_GCMD_REG_EAFL_MASK \
1348 | VTD_BF_GCMD_REG_WBF_MASK | VTD_BF_GCMD_REG_QIE_MASK \
1349 | VTD_BF_GCMD_REG_IRE_MASK | VTD_BF_GCMD_REG_SIRTP_MASK \
1350 | VTD_BF_GCMD_REG_CFI_MASK)
1351/** @} */
1352
1353
1354/** @name Global Status Register (GSTS_REG).
1355 * In accordance with the Intel spec.
1356 * @{ */
1357/** R: Reserved (bits 22:0). */
1358#define VTD_BF_GSTS_REG_RSVD_22_0_SHIFT 0
1359#define VTD_BF_GSTS_REG_RSVD_22_0_MASK UINT32_C(0x007fffff)
1360/** CFIS: Compatibility Format Interrupt Status. */
1361#define VTD_BF_GSTS_REG_CFIS_SHIFT 23
1362#define VTD_BF_GSTS_REG_CFIS_MASK UINT32_C(0x00800000)
1363/** IRTPS: Interrupt Remapping Table Pointer Status. */
1364#define VTD_BF_GSTS_REG_IRTPS_SHIFT 24
1365#define VTD_BF_GSTS_REG_IRTPS_MASK UINT32_C(0x01000000)
1366/** IRES: Interrupt Remapping Enable Status. */
1367#define VTD_BF_GSTS_REG_IRES_SHIFT 25
1368#define VTD_BF_GSTS_REG_IRES_MASK UINT32_C(0x02000000)
1369/** QIES: Queued Invalidation Enable Status. */
1370#define VTD_BF_GSTS_REG_QIES_SHIFT 26
1371#define VTD_BF_GSTS_REG_QIES_MASK UINT32_C(0x04000000)
1372/** WBFS: Write Buffer Flush Status. */
1373#define VTD_BF_GSTS_REG_WBFS_SHIFT 27
1374#define VTD_BF_GSTS_REG_WBFS_MASK UINT32_C(0x08000000)
1375/** AFLS: Advanced Fault Logging Status. */
1376#define VTD_BF_GSTS_REG_AFLS_SHIFT 28
1377#define VTD_BF_GSTS_REG_AFLS_MASK UINT32_C(0x10000000)
1378/** FLS: Fault Log Status. */
1379#define VTD_BF_GSTS_REG_FLS_SHIFT 29
1380#define VTD_BF_GSTS_REG_FLS_MASK UINT32_C(0x20000000)
1381/** RTPS: Root Table Pointer Status. */
1382#define VTD_BF_GSTS_REG_RTPS_SHIFT 30
1383#define VTD_BF_GSTS_REG_RTPS_MASK UINT32_C(0x40000000)
1384/** TES: Translation Enable Status. */
1385#define VTD_BF_GSTS_REG_TES_SHIFT 31
1386#define VTD_BF_GSTS_REG_TES_MASK UINT32_C(0x80000000)
1387RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_GSTS_REG_, UINT32_C(0), UINT32_MAX,
1388 (RSVD_22_0, CFIS, IRTPS, IRES, QIES, WBFS, AFLS, FLS, RTPS, TES));
1389
1390/** RW: Read/write mask. */
1391#define VTD_GSTS_REG_RW_MASK UINT32_C(0)
1392/** @} */
1393
1394
1395/** @name Root Table Address Register (RTADDR_REG).
1396 * In accordance with the Intel spec.
1397 * @{ */
1398/** R: Reserved (bits 9:0). */
1399#define VTD_BF_RTADDR_REG_RSVD_9_0_SHIFT 0
1400#define VTD_BF_RTADDR_REG_RSVD_9_0_MASK UINT64_C(0x00000000000003ff)
1401/** TTM: Translation Table Mode. */
1402#define VTD_BF_RTADDR_REG_TTM_SHIFT 10
1403#define VTD_BF_RTADDR_REG_TTM_MASK UINT64_C(0x0000000000000c00)
1404/** RTA: Root Table Address. */
1405#define VTD_BF_RTADDR_REG_RTA_SHIFT 12
1406#define VTD_BF_RTADDR_REG_RTA_MASK UINT64_C(0xfffffffffffff000)
1407RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_RTADDR_REG_, UINT64_C(0), UINT64_MAX,
1408 (RSVD_9_0, TTM, RTA));
1409
1410/** RW: Read/write mask. */
1411#define VTD_RTADDR_REG_RW_MASK UINT64_C(0xfffffffffffffc00)
1412
1413/** RTADDR_REG.TTM: Legacy mode. */
1414#define VTD_TTM_LEGACY_MODE 0
1415/** RTADDR_REG.TTM: Scalable mode. */
1416#define VTD_TTM_SCALABLE_MODE 1
1417/** RTADDR_REG.TTM: Reserved. */
1418#define VTD_TTM_RSVD 2
1419/** RTADDR_REG.TTM: Abort DMA mode. */
1420#define VTD_TTM_ABORT_DMA_MODE 3
1421/** @} */
1422
1423
1424/** @name Context Command Register (CCMD_REG).
1425 * In accordance with the Intel spec.
1426 * @{ */
1427/** DID: Domain-ID. */
1428#define VTD_BF_CCMD_REG_DID_SHIFT 0
1429#define VTD_BF_CCMD_REG_DID_MASK UINT64_C(0x000000000000ffff)
1430/** SID: Source-ID. */
1431#define VTD_BF_CCMD_REG_SID_SHIFT 16
1432#define VTD_BF_CCMD_REG_SID_MASK UINT64_C(0x00000000ffff0000)
1433/** FM: Function Mask. */
1434#define VTD_BF_CCMD_REG_FM_SHIFT 32
1435#define VTD_BF_CCMD_REG_FM_MASK UINT64_C(0x0000000300000000)
1436/** R: Reserved (bits 58:34). */
1437#define VTD_BF_CCMD_REG_RSVD_58_34_SHIFT 34
1438#define VTD_BF_CCMD_REG_RSVD_58_34_MASK UINT64_C(0x07fffffc00000000)
1439/** CAIG: Context Actual Invalidation Granularity. */
1440#define VTD_BF_CCMD_REG_CAIG_SHIFT 59
1441#define VTD_BF_CCMD_REG_CAIG_MASK UINT64_C(0x1800000000000000)
1442/** CIRG: Context Invalidation Request Granularity. */
1443#define VTD_BF_CCMD_REG_CIRG_SHIFT 61
1444#define VTD_BF_CCMD_REG_CIRG_MASK UINT64_C(0x6000000000000000)
1445/** ICC: Invalidation Context Cache. */
1446#define VTD_BF_CCMD_REG_ICC_SHIFT 63
1447#define VTD_BF_CCMD_REG_ICC_MASK UINT64_C(0x8000000000000000)
1448RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_CCMD_REG_, UINT64_C(0), UINT64_MAX,
1449 (DID, SID, FM, RSVD_58_34, CAIG, CIRG, ICC));
1450
1451/** RW: Read/write mask. */
1452#define VTD_CCMD_REG_RW_MASK ( VTD_BF_CCMD_REG_DID_MASK | VTD_BF_CCMD_REG_SID_MASK \
1453 | VTD_BF_CCMD_REG_FM_MASK | VTD_BF_CCMD_REG_CIRG_MASK \
1454 | VTD_BF_CCMD_REG_ICC_MASK)
1455/** @} */
1456
1457
1458/** @name IOTLB Invalidation Register (IOTLB_REG).
1459 * In accordance with the Intel spec.
1460 * @{ */
1461/** R: Reserved (bits 31:0). */
1462#define VTD_BF_IOTLB_REG_RSVD_31_0_SHIFT 0
1463#define VTD_BF_IOTLB_REG_RSVD_31_0_MASK UINT64_C(0x00000000ffffffff)
1464/** DID: Domain-ID. */
1465#define VTD_BF_IOTLB_REG_DID_SHIFT 32
1466#define VTD_BF_IOTLB_REG_DID_MASK UINT64_C(0x0000ffff00000000)
1467/** DW: Draining Writes. */
1468#define VTD_BF_IOTLB_REG_DW_SHIFT 48
1469#define VTD_BF_IOTLB_REG_DW_MASK UINT64_C(0x0001000000000000)
1470/** DR: Draining Reads. */
1471#define VTD_BF_IOTLB_REG_DR_SHIFT 49
1472#define VTD_BF_IOTLB_REG_DR_MASK UINT64_C(0x0002000000000000)
1473/** R: Reserved (bits 56:50). */
1474#define VTD_BF_IOTLB_REG_RSVD_56_50_SHIFT 50
1475#define VTD_BF_IOTLB_REG_RSVD_56_50_MASK UINT64_C(0x01fc000000000000)
1476/** IAIG: IOTLB Actual Invalidation Granularity. */
1477#define VTD_BF_IOTLB_REG_IAIG_SHIFT 57
1478#define VTD_BF_IOTLB_REG_IAIG_MASK UINT64_C(0x0600000000000000)
1479/** R: Reserved (bit 59). */
1480#define VTD_BF_IOTLB_REG_RSVD_59_SHIFT 59
1481#define VTD_BF_IOTLB_REG_RSVD_59_MASK UINT64_C(0x0800000000000000)
1482/** IIRG: IOTLB Invalidation Request Granularity. */
1483#define VTD_BF_IOTLB_REG_IIRG_SHIFT 60
1484#define VTD_BF_IOTLB_REG_IIRG_MASK UINT64_C(0x3000000000000000)
1485/** R: Reserved (bit 62). */
1486#define VTD_BF_IOTLB_REG_RSVD_62_SHIFT 62
1487#define VTD_BF_IOTLB_REG_RSVD_62_MASK UINT64_C(0x4000000000000000)
1488/** IVT: Invalidate IOTLB. */
1489#define VTD_BF_IOTLB_REG_IVT_SHIFT 63
1490#define VTD_BF_IOTLB_REG_IVT_MASK UINT64_C(0x8000000000000000)
1491RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IOTLB_REG_, UINT64_C(0), UINT64_MAX,
1492 (RSVD_31_0, DID, DW, DR, RSVD_56_50, IAIG, RSVD_59, IIRG, RSVD_62, IVT));
1493
1494/** RW: Read/write mask. */
1495#define VTD_IOTLB_REG_RW_MASK ( VTD_BF_IOTLB_REG_DID_MASK | VTD_BF_IOTLB_REG_DW_MASK \
1496 | VTD_BF_IOTLB_REG_DR_MASK | VTD_BF_IOTLB_REG_IIRG_MASK \
1497 | VTD_BF_IOTLB_REG_IVT_MASK)
1498/** @} */
1499
1500
1501/** @name Invalidate Address Register (IVA_REG).
1502 * In accordance with the Intel spec.
1503 * @{ */
1504/** AM: Address Mask. */
1505#define VTD_BF_IVA_REG_AM_SHIFT 0
1506#define VTD_BF_IVA_REG_AM_MASK UINT64_C(0x000000000000003f)
1507/** IH: Invalidation Hint. */
1508#define VTD_BF_IVA_REG_IH_SHIFT 6
1509#define VTD_BF_IVA_REG_IH_MASK UINT64_C(0x0000000000000040)
1510/** R: Reserved (bits 11:7). */
1511#define VTD_BF_IVA_REG_RSVD_11_7_SHIFT 7
1512#define VTD_BF_IVA_REG_RSVD_11_7_MASK UINT64_C(0x0000000000000f80)
1513/** ADDR: Address. */
1514#define VTD_BF_IVA_REG_ADDR_SHIFT 12
1515#define VTD_BF_IVA_REG_ADDR_MASK UINT64_C(0xfffffffffffff000)
1516RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IVA_REG_, UINT64_C(0), UINT64_MAX,
1517 (AM, IH, RSVD_11_7, ADDR));
1518
1519/** RW: Read/write mask. */
1520#define VTD_IVA_REG_RW_MASK ( VTD_BF_IVA_REG_AM_MASK | VTD_BF_IVA_REG_IH_MASK \
1521 | VTD_BF_IVA_REG_ADDR_MASK)
1522/** @} */
1523
1524
1525/** @name Fault Status Register (FSTS_REG).
1526 * In accordance with the Intel spec.
1527 * @{ */
1528/** PFO: Primary Fault Overflow. */
1529#define VTD_BF_FSTS_REG_PFO_SHIFT 0
1530#define VTD_BF_FSTS_REG_PFO_MASK UINT32_C(0x00000001)
1531/** PPF: Primary Pending Fault. */
1532#define VTD_BF_FSTS_REG_PPF_SHIFT 1
1533#define VTD_BF_FSTS_REG_PPF_MASK UINT32_C(0x00000002)
1534/** AFO: Advanced Fault Overflow. */
1535#define VTD_BF_FSTS_REG_AFO_SHIFT 2
1536#define VTD_BF_FSTS_REG_AFO_MASK UINT32_C(0x00000004)
1537/** APF: Advanced Pending Fault. */
1538#define VTD_BF_FSTS_REG_APF_SHIFT 3
1539#define VTD_BF_FSTS_REG_APF_MASK UINT32_C(0x00000008)
1540/** IQE: Invalidation Queue Error. */
1541#define VTD_BF_FSTS_REG_IQE_SHIFT 4
1542#define VTD_BF_FSTS_REG_IQE_MASK UINT32_C(0x00000010)
1543/** ICE: Invalidation Completion Error. */
1544#define VTD_BF_FSTS_REG_ICE_SHIFT 5
1545#define VTD_BF_FSTS_REG_ICE_MASK UINT32_C(0x00000020)
1546/** ITE: Invalidation Timeout Error. */
1547#define VTD_BF_FSTS_REG_ITE_SHIFT 6
1548#define VTD_BF_FSTS_REG_ITE_MASK UINT32_C(0x00000040)
1549/** DEP: Deprecated MBZ. Reserved (bit 7). */
1550#define VTD_BF_FSTS_REG_RSVD_7_SHIFT 7
1551#define VTD_BF_FSTS_REG_RSVD_7_MASK UINT32_C(0x00000080)
1552/** FRI: Fault Record Index. */
1553#define VTD_BF_FSTS_REG_FRI_SHIFT 8
1554#define VTD_BF_FSTS_REG_FRI_MASK UINT32_C(0x0000ff00)
1555/** R: Reserved (bits 31:16). */
1556#define VTD_BF_FSTS_REG_RSVD_31_16_SHIFT 16
1557#define VTD_BF_FSTS_REG_RSVD_31_16_MASK UINT32_C(0xffff0000)
1558RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_FSTS_REG_, UINT32_C(0), UINT32_MAX,
1559 (PFO, PPF, AFO, APF, IQE, ICE, ITE, RSVD_7, FRI, RSVD_31_16));
1560
1561/** RW: Read/write mask. */
1562#define VTD_FSTS_REG_RW_MASK ( VTD_BF_FSTS_REG_PFO_MASK | VTD_BF_FSTS_REG_AFO_MASK \
1563 | VTD_BF_FSTS_REG_APF_MASK | VTD_BF_FSTS_REG_IQE_MASK \
1564 | VTD_BF_FSTS_REG_ICE_MASK | VTD_BF_FSTS_REG_ITE_MASK)
1565/** RW1C: Read-only-status, Write-1-to-clear status mask. */
1566#define VTD_FSTS_REG_RW1C_MASK ( VTD_BF_FSTS_REG_PFO_MASK | VTD_BF_FSTS_REG_AFO_MASK \
1567 | VTD_BF_FSTS_REG_APF_MASK | VTD_BF_FSTS_REG_IQE_MASK \
1568 | VTD_BF_FSTS_REG_ICE_MASK | VTD_BF_FSTS_REG_ITE_MASK)
1569/** @} */
1570
1571
1572/** @name Fault Event Control Register (FECTL_REG).
1573 * In accordance with the Intel spec.
1574 * @{ */
1575/** R: Reserved (bits 29:0). */
1576#define VTD_BF_FECTL_REG_RSVD_29_0_SHIFT 0
1577#define VTD_BF_FECTL_REG_RSVD_29_0_MASK UINT32_C(0x3fffffff)
1578/** IP: Interrupt Pending. */
1579#define VTD_BF_FECTL_REG_IP_SHIFT 30
1580#define VTD_BF_FECTL_REG_IP_MASK UINT32_C(0x40000000)
1581/** IM: Interrupt Mask. */
1582#define VTD_BF_FECTL_REG_IM_SHIFT 31
1583#define VTD_BF_FECTL_REG_IM_MASK UINT32_C(0x80000000)
1584RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_FECTL_REG_, UINT32_C(0), UINT32_MAX,
1585 (RSVD_29_0, IP, IM));
1586
1587/** RW: Read/write mask. */
1588#define VTD_FECTL_REG_RW_MASK VTD_BF_FECTL_REG_IM_MASK
1589/** @} */
1590
1591
1592/** @name Fault Event Data Register (FEDATA_REG).
1593 * In accordance with the Intel spec.
1594 * @{ */
1595/** IMD: Interrupt Message Data. */
1596#define VTD_BF_FEDATA_REG_IMD_SHIFT 0
1597#define VTD_BF_FEDATA_REG_IMD_MASK UINT32_C(0x0000ffff)
1598/** R: Reserved (bits 31:16). VT-d specs. prior to 2021 had EIMD here. */
1599#define VTD_BF_FEDATA_REG_RSVD_31_16_SHIFT 16
1600#define VTD_BF_FEDATA_REG_RSVD_31_16_MASK UINT32_C(0xffff0000)
1601RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_FEDATA_REG_, UINT32_C(0), UINT32_MAX,
1602 (IMD, RSVD_31_16));
1603
1604/** RW: Read/write mask, see 5.1.6 "Remapping Hardware Event Interrupt
1605 * Programming". */
1606#define VTD_FEDATA_REG_RW_MASK UINT32_C(0x000001ff)
1607/** @} */
1608
1609
1610/** @name Fault Event Address Register (FEADDR_REG).
1611 * In accordance with the Intel spec.
1612 * @{ */
1613/** R: Reserved (bits 1:0). */
1614#define VTD_BF_FEADDR_REG_RSVD_1_0_SHIFT 0
1615#define VTD_BF_FEADDR_REG_RSVD_1_0_MASK UINT32_C(0x00000003)
1616/** MA: Message Address. */
1617#define VTD_BF_FEADDR_REG_MA_SHIFT 2
1618#define VTD_BF_FEADDR_REG_MA_MASK UINT32_C(0xfffffffc)
1619RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_FEADDR_REG_, UINT32_C(0), UINT32_MAX,
1620 (RSVD_1_0, MA));
1621
1622/** RW: Read/write mask. */
1623#define VTD_FEADDR_REG_RW_MASK VTD_BF_FEADDR_REG_MA_MASK
1624/** @} */
1625
1626
1627/** @name Fault Event Upper Address Register (FEUADDR_REG).
1628 * In accordance with the Intel spec.
1629 * @{ */
1630/** MUA: Message Upper Address. */
1631#define VTD_BF_FEUADDR_REG_MA_SHIFT 0
1632#define VTD_BF_FEUADDR_REG_MA_MASK UINT32_C(0xffffffff)
1633
1634/** RW: Read/write mask. */
1635#define VTD_FEUADDR_REG_RW_MASK VTD_BF_FEUADDR_REG_MA_MASK
1636/** @} */
1637
1638
1639/** @name Fault Recording Register (FRCD_REG).
1640 * In accordance with the Intel spec.
1641 * @{ */
1642/** R: Reserved (bits 11:0). */
1643#define VTD_BF_0_FRCD_REG_RSVD_11_0_SHIFT 0
1644#define VTD_BF_0_FRCD_REG_RSVD_11_0_MASK UINT64_C(0x0000000000000fff)
1645/** FI: Fault Info. */
1646#define VTD_BF_0_FRCD_REG_FI_SHIFT 12
1647#define VTD_BF_0_FRCD_REG_FI_MASK UINT64_C(0xfffffffffffff000)
1648RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_FRCD_REG_, UINT64_C(0), UINT64_MAX,
1649 (RSVD_11_0, FI));
1650
1651/** SID: Source Identifier. */
1652#define VTD_BF_1_FRCD_REG_SID_SHIFT 0
1653#define VTD_BF_1_FRCD_REG_SID_MASK UINT64_C(0x000000000000ffff)
1654/** R: Reserved (bits 27:16). */
1655#define VTD_BF_1_FRCD_REG_RSVD_27_16_SHIFT 16
1656#define VTD_BF_1_FRCD_REG_RSVD_27_16_MASK UINT64_C(0x000000000fff0000)
1657/** T2: Type bit 2. */
1658#define VTD_BF_1_FRCD_REG_T2_SHIFT 28
1659#define VTD_BF_1_FRCD_REG_T2_MASK UINT64_C(0x0000000010000000)
1660/** PRIV: Privilege Mode. */
1661#define VTD_BF_1_FRCD_REG_PRIV_SHIFT 29
1662#define VTD_BF_1_FRCD_REG_PRIV_MASK UINT64_C(0x0000000020000000)
1663/** EXE: Execute Permission Requested. */
1664#define VTD_BF_1_FRCD_REG_EXE_SHIFT 30
1665#define VTD_BF_1_FRCD_REG_EXE_MASK UINT64_C(0x0000000040000000)
1666/** PP: PASID Present. */
1667#define VTD_BF_1_FRCD_REG_PP_SHIFT 31
1668#define VTD_BF_1_FRCD_REG_PP_MASK UINT64_C(0x0000000080000000)
1669/** FR: Fault Reason. */
1670#define VTD_BF_1_FRCD_REG_FR_SHIFT 32
1671#define VTD_BF_1_FRCD_REG_FR_MASK UINT64_C(0x000000ff00000000)
1672/** PV: PASID Value. */
1673#define VTD_BF_1_FRCD_REG_PV_SHIFT 40
1674#define VTD_BF_1_FRCD_REG_PV_MASK UINT64_C(0x0fffff0000000000)
1675/** AT: Address Type. */
1676#define VTD_BF_1_FRCD_REG_AT_SHIFT 60
1677#define VTD_BF_1_FRCD_REG_AT_MASK UINT64_C(0x3000000000000000)
1678/** T1: Type bit 1. */
1679#define VTD_BF_1_FRCD_REG_T1_SHIFT 62
1680#define VTD_BF_1_FRCD_REG_T1_MASK UINT64_C(0x4000000000000000)
1681/** F: Fault. */
1682#define VTD_BF_1_FRCD_REG_F_SHIFT 63
1683#define VTD_BF_1_FRCD_REG_F_MASK UINT64_C(0x8000000000000000)
1684RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_FRCD_REG_, UINT64_C(0), UINT64_MAX,
1685 (SID, RSVD_27_16, T2, PRIV, EXE, PP, FR, PV, AT, T1, F));
1686
1687/** RW: Read/write mask. */
1688#define VTD_FRCD_REG_LO_RW_MASK UINT64_C(0)
1689#define VTD_FRCD_REG_HI_RW_MASK VTD_BF_1_FRCD_REG_F_MASK
1690/** RW1C: Read-only-status, Write-1-to-clear status mask. */
1691#define VTD_FRCD_REG_LO_RW1C_MASK UINT64_C(0)
1692#define VTD_FRCD_REG_HI_RW1C_MASK VTD_BF_1_FRCD_REG_F_MASK
1693/** @} */
1694
1695
1696/**
1697 * VT-d faulted address translation request types (FRCD_REG::T2).
1698 * In accordance with the Intel spec.
1699 */
1700typedef enum VTDREQTYPE
1701{
1702 VTDREQTYPE_WRITE = 0, /**< Memory access write request. */
1703 VTDREQTYPE_PAGE, /**< Page translation request. */
1704 VTDREQTYPE_READ, /**< Memory access read request. */
1705 VTDREQTYPE_ATOMIC_OP /**< Memory access atomic operation. */
1706} VTDREQTYPE;
1707
1708
1709/** @name Advanced Fault Log Register (AFLOG_REG).
1710 * In accordance with the Intel spec.
1711 * @{ */
1712/** R: Reserved (bits 8:0). */
1713#define VTD_BF_0_AFLOG_REG_RSVD_8_0_SHIFT 0
1714#define VTD_BF_0_AFLOG_REG_RSVD_8_0_MASK UINT64_C(0x00000000000001ff)
1715/** FLS: Fault Log Size. */
1716#define VTD_BF_0_AFLOG_REG_FLS_SHIFT 9
1717#define VTD_BF_0_AFLOG_REG_FLS_MASK UINT64_C(0x0000000000000e00)
1718/** FLA: Fault Log Address. */
1719#define VTD_BF_0_AFLOG_REG_FLA_SHIFT 12
1720#define VTD_BF_0_AFLOG_REG_FLA_MASK UINT64_C(0xfffffffffffff000)
1721RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_AFLOG_REG_, UINT64_C(0), UINT64_MAX,
1722 (RSVD_8_0, FLS, FLA));
1723
1724/** RW: Read/write mask. */
1725#define VTD_AFLOG_REG_RW_MASK (VTD_BF_0_AFLOG_REG_FLS_MASK | VTD_BF_0_AFLOG_REG_FLA_MASK)
1726/** @} */
1727
1728
1729/** @name Protected Memory Enable Register (PMEN_REG).
1730 * In accordance with the Intel spec.
1731 * @{ */
1732/** PRS: Protected Region Status. */
1733#define VTD_BF_PMEN_REG_PRS_SHIFT 0
1734#define VTD_BF_PMEN_REG_PRS_MASK UINT32_C(0x00000001)
1735/** R: Reserved (bits 30:1). */
1736#define VTD_BF_PMEN_REG_RSVD_30_1_SHIFT 1
1737#define VTD_BF_PMEN_REG_RSVD_30_1_MASK UINT32_C(0x7ffffffe)
1738/** EPM: Enable Protected Memory. */
1739#define VTD_BF_PMEN_REG_EPM_SHIFT 31
1740#define VTD_BF_PMEN_REG_EPM_MASK UINT32_C(0x80000000)
1741RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_PMEN_REG_, UINT32_C(0), UINT32_MAX,
1742 (PRS, RSVD_30_1, EPM));
1743
1744/** RW: Read/write mask. */
1745#define VTD_PMEN_REG_RW_MASK VTD_BF_PMEN_REG_EPM_MASK
1746/** @} */
1747
1748
1749/** @name Invalidation Queue Head Register (IQH_REG).
1750 * In accordance with the Intel spec.
1751 * @{ */
1752/** R: Reserved (bits 3:0). */
1753#define VTD_BF_IQH_REG_RSVD_3_0_SHIFT 0
1754#define VTD_BF_IQH_REG_RSVD_3_0_MASK UINT64_C(0x000000000000000f)
1755/** QH: Queue Head. */
1756#define VTD_BF_IQH_REG_QH_SHIFT 4
1757#define VTD_BF_IQH_REG_QH_MASK UINT64_C(0x000000000007fff0)
1758/** R: Reserved (bits 63:19). */
1759#define VTD_BF_IQH_REG_RSVD_63_19_SHIFT 19
1760#define VTD_BF_IQH_REG_RSVD_63_19_MASK UINT64_C(0xfffffffffff80000)
1761RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IQH_REG_, UINT64_C(0), UINT64_MAX,
1762 (RSVD_3_0, QH, RSVD_63_19));
1763
1764/** RW: Read/write mask. */
1765#define VTD_IQH_REG_RW_MASK UINT64_C(0x0)
1766/** @} */
1767
1768
1769/** @name Invalidation Queue Tail Register (IQT_REG).
1770 * In accordance with the Intel spec.
1771 * @{ */
1772/** R: Reserved (bits 3:0). */
1773#define VTD_BF_IQT_REG_RSVD_3_0_SHIFT 0
1774#define VTD_BF_IQT_REG_RSVD_3_0_MASK UINT64_C(0x000000000000000f)
1775/** QH: Queue Tail. */
1776#define VTD_BF_IQT_REG_QT_SHIFT 4
1777#define VTD_BF_IQT_REG_QT_MASK UINT64_C(0x000000000007fff0)
1778/** R: Reserved (bits 63:19). */
1779#define VTD_BF_IQT_REG_RSVD_63_19_SHIFT 19
1780#define VTD_BF_IQT_REG_RSVD_63_19_MASK UINT64_C(0xfffffffffff80000)
1781RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IQT_REG_, UINT64_C(0), UINT64_MAX,
1782 (RSVD_3_0, QT, RSVD_63_19));
1783
1784/** RW: Read/write mask. */
1785#define VTD_IQT_REG_RW_MASK VTD_BF_IQT_REG_QT_MASK
1786/** @} */
1787
1788
1789/** @name Invalidation Queue Address Register (IQA_REG).
1790 * In accordance with the Intel spec.
1791 * @{ */
1792/** QS: Queue Size. */
1793#define VTD_BF_IQA_REG_QS_SHIFT 0
1794#define VTD_BF_IQA_REG_QS_MASK UINT64_C(0x0000000000000007)
1795/** R: Reserved (bits 10:3). */
1796#define VTD_BF_IQA_REG_RSVD_10_3_SHIFT 3
1797#define VTD_BF_IQA_REG_RSVD_10_3_MASK UINT64_C(0x00000000000007f8)
1798/** DW: Descriptor Width. */
1799#define VTD_BF_IQA_REG_DW_SHIFT 11
1800#define VTD_BF_IQA_REG_DW_MASK UINT64_C(0x0000000000000800)
1801/** IQA: Invalidation Queue Base Address. */
1802#define VTD_BF_IQA_REG_IQA_SHIFT 12
1803#define VTD_BF_IQA_REG_IQA_MASK UINT64_C(0xfffffffffffff000)
1804RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IQA_REG_, UINT64_C(0), UINT64_MAX,
1805 (QS, RSVD_10_3, DW, IQA));
1806
1807/** RW: Read/write mask. */
1808#define VTD_IQA_REG_RW_MASK ( VTD_BF_IQA_REG_QS_MASK | VTD_BF_IQA_REG_DW_MASK \
1809 | VTD_BF_IQA_REG_IQA_MASK)
1810/** DW: 128-bit descriptor. */
1811#define VTD_IQA_REG_DW_128_BIT 0
1812/** DW: 256-bit descriptor. */
1813#define VTD_IQA_REG_DW_256_BIT 1
1814/** @} */
1815
1816
1817/** @name Invalidation Completion Status Register (ICS_REG).
1818 * In accordance with the Intel spec.
1819 * @{ */
1820/** IWC: Invalidation Wait Descriptor Complete. */
1821#define VTD_BF_ICS_REG_IWC_SHIFT 0
1822#define VTD_BF_ICS_REG_IWC_MASK UINT32_C(0x00000001)
1823/** R: Reserved (bits 31:1). */
1824#define VTD_BF_ICS_REG_RSVD_31_1_SHIFT 1
1825#define VTD_BF_ICS_REG_RSVD_31_1_MASK UINT32_C(0xfffffffe)
1826RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_ICS_REG_, UINT32_C(0), UINT32_MAX,
1827 (IWC, RSVD_31_1));
1828
1829/** RW: Read/write mask. */
1830#define VTD_ICS_REG_RW_MASK VTD_BF_ICS_REG_IWC_MASK
1831/** RW1C: Read-only-status, Write-1-to-clear status mask. */
1832#define VTD_ICS_REG_RW1C_MASK VTD_BF_ICS_REG_IWC_MASK
1833/** @} */
1834
1835
1836/** @name Invalidation Event Control Register (IECTL_REG).
1837 * In accordance with the Intel spec.
1838 * @{ */
1839/** R: Reserved (bits 29:0). */
1840#define VTD_BF_IECTL_REG_RSVD_29_0_SHIFT 0
1841#define VTD_BF_IECTL_REG_RSVD_29_0_MASK UINT32_C(0x3fffffff)
1842/** IP: Interrupt Pending. */
1843#define VTD_BF_IECTL_REG_IP_SHIFT 30
1844#define VTD_BF_IECTL_REG_IP_MASK UINT32_C(0x40000000)
1845/** IM: Interrupt Mask. */
1846#define VTD_BF_IECTL_REG_IM_SHIFT 31
1847#define VTD_BF_IECTL_REG_IM_MASK UINT32_C(0x80000000)
1848RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IECTL_REG_, UINT32_C(0), UINT32_MAX,
1849 (RSVD_29_0, IP, IM));
1850
1851/** RW: Read/write mask. */
1852#define VTD_IECTL_REG_RW_MASK VTD_BF_IECTL_REG_IM_MASK
1853/** @} */
1854
1855
1856/** @name Invalidation Event Data Register (IEDATA_REG).
1857 * In accordance with the Intel spec.
1858 * @{ */
1859/** IMD: Interrupt Message Data. */
1860#define VTD_BF_IEDATA_REG_IMD_SHIFT 0
1861#define VTD_BF_IEDATA_REG_IMD_MASK UINT32_C(0x0000ffff)
1862/** R: Reserved (bits 31:16). VT-d specs. prior to 2021 had EIMD here. */
1863#define VTD_BF_IEDATA_REG_RSVD_31_16_SHIFT 16
1864#define VTD_BF_IEDATA_REG_RSVD_31_16_MASK UINT32_C(0xffff0000)
1865RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IEDATA_REG_, UINT32_C(0), UINT32_MAX,
1866 (IMD, RSVD_31_16));
1867
1868/** RW: Read/write mask, see 5.1.6 "Remapping Hardware Event Interrupt
1869 * Programming". */
1870#define VTD_IEDATA_REG_RW_MASK UINT32_C(0x000001ff)
1871/** @} */
1872
1873
1874/** @name Invalidation Event Address Register (IEADDR_REG).
1875 * In accordance with the Intel spec.
1876 * @{ */
1877/** R: Reserved (bits 1:0). */
1878#define VTD_BF_IEADDR_REG_RSVD_1_0_SHIFT 0
1879#define VTD_BF_IEADDR_REG_RSVD_1_0_MASK UINT32_C(0x00000003)
1880/** MA: Message Address. */
1881#define VTD_BF_IEADDR_REG_MA_SHIFT 2
1882#define VTD_BF_IEADDR_REG_MA_MASK UINT32_C(0xfffffffc)
1883RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IEADDR_REG_, UINT32_C(0), UINT32_MAX,
1884 (RSVD_1_0, MA));
1885
1886/** RW: Read/write mask. */
1887#define VTD_IEADDR_REG_RW_MASK VTD_BF_IEADDR_REG_MA_MASK
1888/** @} */
1889
1890
1891/** @name Invalidation Event Upper Address Register (IEUADDR_REG).
1892 * @{ */
1893/** MUA: Message Upper Address. */
1894#define VTD_BF_IEUADDR_REG_MUA_SHIFT 0
1895#define VTD_BF_IEUADDR_REG_MUA_MASK UINT32_C(0xffffffff)
1896
1897/** RW: Read/write mask. */
1898#define VTD_IEUADDR_REG_RW_MASK VTD_BF_IEUADDR_REG_MUA_MASK
1899/** @} */
1900
1901
1902/** @name Invalidation Queue Error Record Register (IQERCD_REG).
1903 * In accordance with the Intel spec.
1904 * @{ */
1905/** IQEI: Invalidation Queue Error Info. */
1906#define VTD_BF_IQERCD_REG_IQEI_SHIFT 0
1907#define VTD_BF_IQERCD_REG_IQEI_MASK UINT64_C(0x000000000000000f)
1908/** R: Reserved (bits 31:4). */
1909#define VTD_BF_IQERCD_REG_RSVD_31_4_SHIFT 4
1910#define VTD_BF_IQERCD_REG_RSVD_31_4_MASK UINT64_C(0x00000000fffffff0)
1911/** ITESID: Invalidation Timeout Error Source Identifier. */
1912#define VTD_BF_IQERCD_REG_ITESID_SHIFT 32
1913#define VTD_BF_IQERCD_REG_ITESID_MASK UINT64_C(0x0000ffff00000000)
1914/** ICESID: Invalidation Completion Error Source Identifier. */
1915#define VTD_BF_IQERCD_REG_ICESID_SHIFT 48
1916#define VTD_BF_IQERCD_REG_ICESID_MASK UINT64_C(0xffff000000000000)
1917RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IQERCD_REG_, UINT64_C(0), UINT64_MAX,
1918 (IQEI, RSVD_31_4, ITESID, ICESID));
1919
1920/** RW: Read/write mask. */
1921#define VTD_IQERCD_REG_RW_MASK UINT64_C(0)
1922
1923/** Invalidation Queue Error Information. */
1924typedef enum VTDIQEI
1925{
1926 VTDIQEI_INFO_NOT_AVAILABLE,
1927 VTDIQEI_INVALID_TAIL_PTR,
1928 VTDIQEI_FETCH_DESCRIPTOR_ERR,
1929 VTDIQEI_INVALID_DESCRIPTOR_TYPE,
1930 VTDIQEI_RSVD_FIELD_VIOLATION,
1931 VTDIQEI_INVALID_DESCRIPTOR_WIDTH,
1932 VTDIQEI_QUEUE_TAIL_MISALIGNED,
1933 VTDIQEI_INVALID_TTM
1934} VTDIQEI;
1935/** @} */
1936
1937
1938/** @name Interrupt Remapping Table Address Register (IRTA_REG).
1939 * In accordance with the Intel spec.
1940 * @{ */
1941/** S: Size. */
1942#define VTD_BF_IRTA_REG_S_SHIFT 0
1943#define VTD_BF_IRTA_REG_S_MASK UINT64_C(0x000000000000000f)
1944/** R: Reserved (bits 10:4). */
1945#define VTD_BF_IRTA_REG_RSVD_10_4_SHIFT 4
1946#define VTD_BF_IRTA_REG_RSVD_10_4_MASK UINT64_C(0x00000000000007f0)
1947/** EIME: Extended Interrupt Mode Enable. */
1948#define VTD_BF_IRTA_REG_EIME_SHIFT 11
1949#define VTD_BF_IRTA_REG_EIME_MASK UINT64_C(0x0000000000000800)
1950/** IRTA: Interrupt Remapping Table Address. */
1951#define VTD_BF_IRTA_REG_IRTA_SHIFT 12
1952#define VTD_BF_IRTA_REG_IRTA_MASK UINT64_C(0xfffffffffffff000)
1953RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IRTA_REG_, UINT64_C(0), UINT64_MAX,
1954 (S, RSVD_10_4, EIME, IRTA));
1955
1956/** RW: Read/write mask. */
1957#define VTD_IRTA_REG_RW_MASK ( VTD_BF_IRTA_REG_S_MASK | VTD_BF_IRTA_REG_EIME_MASK \
1958 | VTD_BF_IRTA_REG_IRTA_MASK)
1959/** IRTA_REG: Get number of interrupt entries. */
1960#define VTD_IRTA_REG_GET_ENTRY_COUNT(a) (UINT32_C(1) << (1 + ((a) & VTD_BF_IRTA_REG_S_MASK)))
1961/** @} */
1962
1963
1964/** @name Page Request Queue Head Register (PQH_REG).
1965 * In accordance with the Intel spec.
1966 * @{ */
1967/** R: Reserved (bits 4:0). */
1968#define VTD_BF_PQH_REG_RSVD_4_0_SHIFT 0
1969#define VTD_BF_PQH_REG_RSVD_4_0_MASK UINT64_C(0x000000000000001f)
1970/** PQH: Page Queue Head. */
1971#define VTD_BF_PQH_REG_PQH_SHIFT 5
1972#define VTD_BF_PQH_REG_PQH_MASK UINT64_C(0x000000000007ffe0)
1973/** R: Reserved (bits 63:19). */
1974#define VTD_BF_PQH_REG_RSVD_63_19_SHIFT 19
1975#define VTD_BF_PQH_REG_RSVD_63_19_MASK UINT64_C(0xfffffffffff80000)
1976RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_PQH_REG_, UINT64_C(0), UINT64_MAX,
1977 (RSVD_4_0, PQH, RSVD_63_19));
1978
1979/** RW: Read/write mask. */
1980#define VTD_PQH_REG_RW_MASK VTD_BF_PQH_REG_PQH_MASK
1981/** @} */
1982
1983
1984/** @name Page Request Queue Tail Register (PQT_REG).
1985 * In accordance with the Intel spec.
1986 * @{ */
1987/** R: Reserved (bits 4:0). */
1988#define VTD_BF_PQT_REG_RSVD_4_0_SHIFT 0
1989#define VTD_BF_PQT_REG_RSVD_4_0_MASK UINT64_C(0x000000000000001f)
1990/** PQT: Page Queue Tail. */
1991#define VTD_BF_PQT_REG_PQT_SHIFT 5
1992#define VTD_BF_PQT_REG_PQT_MASK UINT64_C(0x000000000007ffe0)
1993/** R: Reserved (bits 63:19). */
1994#define VTD_BF_PQT_REG_RSVD_63_19_SHIFT 19
1995#define VTD_BF_PQT_REG_RSVD_63_19_MASK UINT64_C(0xfffffffffff80000)
1996RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_PQT_REG_, UINT64_C(0), UINT64_MAX,
1997 (RSVD_4_0, PQT, RSVD_63_19));
1998
1999/** RW: Read/write mask. */
2000#define VTD_PQT_REG_RW_MASK VTD_BF_PQT_REG_PQT_MASK
2001/** @} */
2002
2003
2004/** @name Page Request Queue Address Register (PQA_REG).
2005 * In accordance with the Intel spec.
2006 * @{ */
2007/** PQS: Page Queue Size. */
2008#define VTD_BF_PQA_REG_PQS_SHIFT 0
2009#define VTD_BF_PQA_REG_PQS_MASK UINT64_C(0x0000000000000007)
2010/** R: Reserved bits (11:3). */
2011#define VTD_BF_PQA_REG_RSVD_11_3_SHIFT 3
2012#define VTD_BF_PQA_REG_RSVD_11_3_MASK UINT64_C(0x0000000000000ff8)
2013/** PQA: Page Request Queue Base Address. */
2014#define VTD_BF_PQA_REG_PQA_SHIFT 12
2015#define VTD_BF_PQA_REG_PQA_MASK UINT64_C(0xfffffffffffff000)
2016RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_PQA_REG_, UINT64_C(0), UINT64_MAX,
2017 (PQS, RSVD_11_3, PQA));
2018
2019/** RW: Read/write mask. */
2020#define VTD_PQA_REG_RW_MASK (VTD_BF_PQA_REG_PQS_MASK | VTD_BF_PQA_REG_PQA_MASK)
2021/** @} */
2022
2023
2024/** @name Page Request Status Register (PRS_REG).
2025 * In accordance with the Intel spec.
2026 * @{ */
2027/** PPR: Pending Page Request. */
2028#define VTD_BF_PRS_REG_PPR_SHIFT 0
2029#define VTD_BF_PRS_REG_PPR_MASK UINT64_C(0x00000001)
2030/** PRO: Page Request Overflow. */
2031#define VTD_BF_PRS_REG_PRO_SHIFT 1
2032#define VTD_BF_PRS_REG_PRO_MASK UINT64_C(0x00000002)
2033/** R: Reserved (bits 31:2). */
2034#define VTD_BF_PRS_REG_RSVD_31_2_SHIFT 2
2035#define VTD_BF_PRS_REG_RSVD_31_2_MASK UINT64_C(0xfffffffc)
2036RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_PRS_REG_, UINT32_C(0), UINT32_MAX,
2037 (PPR, PRO, RSVD_31_2));
2038
2039/** RW: Read/write mask. */
2040#define VTD_PRS_REG_RW_MASK (VTD_BF_PRS_REG_PPR_MASK | VTD_BF_PRS_REG_PRO_MASK)
2041/** RW1C: Read-only-status, Write-1-to-clear status mask. */
2042#define VTD_PRS_REG_RW1C_MASK (VTD_BF_PRS_REG_PPR_MASK | VTD_BF_PRS_REG_PRO_MASK)
2043/** @} */
2044
2045
2046/** @name Page Request Event Control Register (PECTL_REG).
2047 * In accordance with the Intel spec.
2048 * @{ */
2049/** R: Reserved (bits 29:0). */
2050#define VTD_BF_PECTL_REG_RSVD_29_0_SHIFT 0
2051#define VTD_BF_PECTL_REG_RSVD_29_0_MASK UINT32_C(0x3fffffff)
2052/** IP: Interrupt Pending. */
2053#define VTD_BF_PECTL_REG_IP_SHIFT 30
2054#define VTD_BF_PECTL_REG_IP_MASK UINT32_C(0x40000000)
2055/** IM: Interrupt Mask. */
2056#define VTD_BF_PECTL_REG_IM_SHIFT 31
2057#define VTD_BF_PECTL_REG_IM_MASK UINT32_C(0x80000000)
2058RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_PECTL_REG_, UINT32_C(0), UINT32_MAX,
2059 (RSVD_29_0, IP, IM));
2060
2061/** RW: Read/write mask. */
2062#define VTD_PECTL_REG_RW_MASK VTD_BF_PECTL_REG_IM_MASK
2063/** @} */
2064
2065
2066/** @name Page Request Event Data Register (PEDATA_REG).
2067 * In accordance with the Intel spec.
2068 * @{ */
2069/** IMD: Interrupt Message Data. */
2070#define VTD_BF_PEDATA_REG_IMD_SHIFT 0
2071#define VTD_BF_PEDATA_REG_IMD_MASK UINT32_C(0x0000ffff)
2072/** R: Reserved (bits 31:16). VT-d specs. prior to 2021 had EIMD here. */
2073#define VTD_BF_PEDATA_REG_RSVD_31_16_SHIFT 16
2074#define VTD_BF_PEDATA_REG_RSVD_31_16_MASK UINT32_C(0xffff0000)
2075RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_PEDATA_REG_, UINT32_C(0), UINT32_MAX,
2076 (IMD, RSVD_31_16));
2077
2078/** RW: Read/write mask, see 5.1.6 "Remapping Hardware Event Interrupt
2079 * Programming". */
2080#define VTD_PEDATA_REG_RW_MASK UINT32_C(0x000001ff)
2081/** @} */
2082
2083
2084/** @name Page Request Event Address Register (PEADDR_REG).
2085 * In accordance with the Intel spec.
2086 * @{ */
2087/** R: Reserved (bits 1:0). */
2088#define VTD_BF_PEADDR_REG_RSVD_1_0_SHIFT 0
2089#define VTD_BF_PEADDR_REG_RSVD_1_0_MASK UINT32_C(0x00000003)
2090/** MA: Message Address. */
2091#define VTD_BF_PEADDR_REG_MA_SHIFT 2
2092#define VTD_BF_PEADDR_REG_MA_MASK UINT32_C(0xfffffffc)
2093RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_PEADDR_REG_, UINT32_C(0), UINT32_MAX,
2094 (RSVD_1_0, MA));
2095
2096/** RW: Read/write mask. */
2097#define VTD_PEADDR_REG_RW_MASK VTD_BF_PEADDR_REG_MA_MASK
2098/** @} */
2099
2100
2101
2102/** @name Page Request Event Upper Address Register (PEUADDR_REG).
2103 * In accordance with the Intel spec.
2104 * @{ */
2105/** MA: Message Address. */
2106#define VTD_BF_PEUADDR_REG_MUA_SHIFT 0
2107#define VTD_BF_PEUADDR_REG_MUA_MASK UINT32_C(0xffffffff)
2108
2109/** RW: Read/write mask. */
2110#define VTD_PEUADDR_REG_RW_MASK VTD_BF_PEUADDR_REG_MUA_MASK
2111/** @} */
2112
2113
2114/** @name MTRR Capability Register (MTRRCAP_REG).
2115 * In accordance with the Intel spec.
2116 * @{ */
2117/** VCNT: Variable MTRR Count. */
2118#define VTD_BF_MTRRCAP_REG_VCNT_SHIFT 0
2119#define VTD_BF_MTRRCAP_REG_VCNT_MASK UINT64_C(0x00000000000000ff)
2120/** FIX: Fixed range MTRRs Supported. */
2121#define VTD_BF_MTRRCAP_REG_FIX_SHIFT 8
2122#define VTD_BF_MTRRCAP_REG_FIX_MASK UINT64_C(0x0000000000000100)
2123/** R: Reserved (bit 9). */
2124#define VTD_BF_MTRRCAP_REG_RSVD_9_SHIFT 9
2125#define VTD_BF_MTRRCAP_REG_RSVD_9_MASK UINT64_C(0x0000000000000200)
2126/** WC: Write Combining. */
2127#define VTD_BF_MTRRCAP_REG_WC_SHIFT 10
2128#define VTD_BF_MTRRCAP_REG_WC_MASK UINT64_C(0x0000000000000400)
2129/** R: Reserved (bits 63:11). */
2130#define VTD_BF_MTRRCAP_REG_RSVD_63_11_SHIFT 11
2131#define VTD_BF_MTRRCAP_REG_RSVD_63_11_MASK UINT64_C(0xfffffffffffff800)
2132RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_MTRRCAP_REG_, UINT64_C(0), UINT64_MAX,
2133 (VCNT, FIX, RSVD_9, WC, RSVD_63_11));
2134
2135/** RW: Read/write mask. */
2136#define VTD_MTRRCAP_REG_RW_MASK UINT64_C(0)
2137/** @} */
2138
2139
2140/** @name MTRR Default Type Register (MTRRDEF_REG).
2141 * In accordance with the Intel spec.
2142 * @{ */
2143/** TYPE: Default Memory Type. */
2144#define VTD_BF_MTRRDEF_REG_TYPE_SHIFT 0
2145#define VTD_BF_MTRRDEF_REG_TYPE_MASK UINT64_C(0x00000000000000ff)
2146/** R: Reserved (bits 9:8). */
2147#define VTD_BF_MTRRDEF_REG_RSVD_9_8_SHIFT 8
2148#define VTD_BF_MTRRDEF_REG_RSVD_9_8_MASK UINT64_C(0x0000000000000300)
2149/** FE: Fixed Range MTRR Enable. */
2150#define VTD_BF_MTRRDEF_REG_FE_SHIFT 10
2151#define VTD_BF_MTRRDEF_REG_FE_MASK UINT64_C(0x0000000000000400)
2152/** E: MTRR Enable. */
2153#define VTD_BF_MTRRDEF_REG_E_SHIFT 11
2154#define VTD_BF_MTRRDEF_REG_E_MASK UINT64_C(0x0000000000000800)
2155/** R: Reserved (bits 63:12). */
2156#define VTD_BF_MTRRDEF_REG_RSVD_63_12_SHIFT 12
2157#define VTD_BF_MTRRDEF_REG_RSVD_63_12_MASK UINT64_C(0xfffffffffffff000)
2158RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_MTRRDEF_REG_, UINT64_C(0), UINT64_MAX,
2159 (TYPE, RSVD_9_8, FE, E, RSVD_63_12));
2160
2161/** RW: Read/write mask. */
2162#define VTD_MTRRDEF_REG_RW_MASK ( VTD_BF_MTRRDEF_REG_TYPE_MASK | VTD_BF_MTRRDEF_REG_FE_MASK \
2163 | VTD_BF_MTRRDEF_REG_E_MASK)
2164/** @} */
2165
2166
2167/** @name Virtual Command Capability Register (VCCAP_REG).
2168 * In accordance with the Intel spec.
2169 * @{ */
2170/** PAS: PASID Support. */
2171#define VTD_BF_VCCAP_REG_PAS_SHIFT 0
2172#define VTD_BF_VCCAP_REG_PAS_MASK UINT64_C(0x0000000000000001)
2173/** R: Reserved (bits 63:1). */
2174#define VTD_BF_VCCAP_REG_RSVD_63_1_SHIFT 1
2175#define VTD_BF_VCCAP_REG_RSVD_63_1_MASK UINT64_C(0xfffffffffffffffe)
2176RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_VCCAP_REG_, UINT64_C(0), UINT64_MAX,
2177 (PAS, RSVD_63_1));
2178
2179/** RW: Read/write mask. */
2180#define VTD_VCCAP_REG_RW_MASK UINT64_C(0)
2181/** @} */
2182
2183
2184/** @name Virtual Command Extended Operand Register (VCMD_EO_REG).
2185 * In accordance with the Intel spec.
2186 * @{ */
2187/** OB: Operand B. */
2188#define VTD_BF_VCMD_EO_REG_OB_SHIFT 0
2189#define VTD_BF_VCMD_EO_REG_OB_MASK UINT32_C(0xffffffffffffffff)
2190
2191/** RW: Read/write mask. */
2192#define VTD_VCMD_EO_REG_RW_MASK VTD_BF_VCMD_EO_REG_OB_MASK
2193/** @} */
2194
2195
2196/** @name Virtual Command Register (VCMD_REG).
2197 * In accordance with the Intel spec.
2198 * @{ */
2199/** CMD: Command. */
2200#define VTD_BF_VCMD_REG_CMD_SHIFT 0
2201#define VTD_BF_VCMD_REG_CMD_MASK UINT64_C(0x00000000000000ff)
2202/** OP: Operand. */
2203#define VTD_BF_VCMD_REG_OP_SHIFT 8
2204#define VTD_BF_VCMD_REG_OP_MASK UINT64_C(0xffffffffffffff00)
2205RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_VCMD_REG_, UINT64_C(0), UINT64_MAX,
2206 (CMD, OP));
2207
2208/** RW: Read/write mask. */
2209#define VTD_VCMD_REG_RW_MASK (VTD_BF_VCMD_REG_CMD_MASK | VTD_BF_VCMD_REG_OP_MASK)
2210/** @} */
2211
2212
2213/** @name Virtual Command Response Register (VCRSP_REG).
2214 * In accordance with the Intel spec.
2215 * @{ */
2216/** IP: In Progress. */
2217#define VTD_BF_VCRSP_REG_IP_SHIFT 0
2218#define VTD_BF_VCRSP_REG_IP_MASK UINT64_C(0x0000000000000001)
2219/** SC: Status Code. */
2220#define VTD_BF_VCRSP_REG_SC_SHIFT 1
2221#define VTD_BF_VCRSP_REG_SC_MASK UINT64_C(0x0000000000000006)
2222/** R: Reserved (bits 7:3). */
2223#define VTD_BF_VCRSP_REG_RSVD_7_3_SHIFT 3
2224#define VTD_BF_VCRSP_REG_RSVD_7_3_MASK UINT64_C(0x00000000000000f8)
2225/** RSLT: Result. */
2226#define VTD_BF_VCRSP_REG_RSLT_SHIFT 8
2227#define VTD_BF_VCRSP_REG_RSLT_MASK UINT64_C(0xffffffffffffff00)
2228RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_VCRSP_REG_, UINT64_C(0), UINT64_MAX,
2229 (IP, SC, RSVD_7_3, RSLT));
2230
2231/** RW: Read/write mask. */
2232#define VTD_VCRSP_REG_RW_MASK UINT64_C(0)
2233/** @} */
2234
2235
2236/** @name Generic Invalidation Descriptor.
2237 * In accordance with the Intel spec.
2238 * Non-reserved fields here are common to all invalidation descriptors.
2239 * @{ */
2240/** Type (Lo). */
2241#define VTD_BF_0_GENERIC_INV_DSC_TYPE_LO_SHIFT 0
2242#define VTD_BF_0_GENERIC_INV_DSC_TYPE_LO_MASK UINT64_C(0x000000000000000f)
2243/** R: Reserved (bits 8:4). */
2244#define VTD_BF_0_GENERIC_INV_DSC_RSVD_8_4_SHIFT 4
2245#define VTD_BF_0_GENERIC_INV_DSC_RSVD_8_4_MASK UINT64_C(0x00000000000001f0)
2246/** Type (Hi). */
2247#define VTD_BF_0_GENERIC_INV_DSC_TYPE_HI_SHIFT 9
2248#define VTD_BF_0_GENERIC_INV_DSC_TYPE_HI_MASK UINT64_C(0x0000000000000e00)
2249/** R: Reserved (bits 63:12). */
2250#define VTD_BF_0_GENERIC_INV_DSC_RSVD_63_12_SHIFT 12
2251#define VTD_BF_0_GENERIC_INV_DSC_RSVD_63_12_MASK UINT64_C(0xfffffffffffff000)
2252RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_GENERIC_INV_DSC_, UINT64_C(0), UINT64_MAX,
2253 (TYPE_LO, RSVD_8_4, TYPE_HI, RSVD_63_12));
2254
2255/** GENERIC_INV_DSC: Type. */
2256#define VTD_GENERIC_INV_DSC_GET_TYPE(a) ((((a) & VTD_BF_0_GENERIC_INV_DSC_TYPE_HI_MASK) >> 5) \
2257 | ((a) & VTD_BF_0_GENERIC_INV_DSC_TYPE_LO_MASK))
2258/** @} */
2259
2260
2261/** @name Context-Cache Invalidation Descriptor (cc_inv_dsc).
2262 * In accordance with the Intel spec.
2263 * @{ */
2264/** Type (Lo). */
2265#define VTD_BF_0_CC_INV_DSC_TYPE_LO_SHIFT 0
2266#define VTD_BF_0_CC_INV_DSC_TYPE_LO_MASK UINT64_C(0x000000000000000f)
2267/** G: Granularity. */
2268#define VTD_BF_0_CC_INV_DSC_G_SHIFT 4
2269#define VTD_BF_0_CC_INV_DSC_G_MASK UINT64_C(0x0000000000000030)
2270/** R: Reserved (bits 8:6). */
2271#define VTD_BF_0_CC_INV_DSC_RSVD_8_6_SHIFT 6
2272#define VTD_BF_0_CC_INV_DSC_RSVD_8_6_MASK UINT64_C(0x00000000000001c0)
2273/** Type (Hi). */
2274#define VTD_BF_0_CC_INV_DSC_TYPE_HI_SHIFT 9
2275#define VTD_BF_0_CC_INV_DSC_TYPE_HI_MASK UINT64_C(0x0000000000000e00)
2276/** R: Reserved (bits 15:12). */
2277#define VTD_BF_0_CC_INV_DSC_RSVD_15_12_SHIFT 12
2278#define VTD_BF_0_CC_INV_DSC_RSVD_15_12_MASK UINT64_C(0x000000000000f000)
2279/** DID: Domain Id. */
2280#define VTD_BF_0_CC_INV_DSC_DID_SHIFT 16
2281#define VTD_BF_0_CC_INV_DSC_DID_MASK UINT64_C(0x00000000ffff0000)
2282/** SID: Source Id. */
2283#define VTD_BF_0_CC_INV_DSC_SID_SHIFT 32
2284#define VTD_BF_0_CC_INV_DSC_SID_MASK UINT64_C(0x0000ffff00000000)
2285/** FM: Function Mask. */
2286#define VTD_BF_0_CC_INV_DSC_FM_SHIFT 48
2287#define VTD_BF_0_CC_INV_DSC_FM_MASK UINT64_C(0x0003000000000000)
2288/** R: Reserved (bits 63:50). */
2289#define VTD_BF_0_CC_INV_DSC_RSVD_63_50_SHIFT 50
2290#define VTD_BF_0_CC_INV_DSC_RSVD_63_50_MASK UINT64_C(0xfffc000000000000)
2291RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_CC_INV_DSC_, UINT64_C(0), UINT64_MAX,
2292 (TYPE_LO, G, RSVD_8_6, TYPE_HI, RSVD_15_12, DID, SID, FM, RSVD_63_50));
2293/** @} */
2294
2295
2296/** @name PASID-Cache Invalidation Descriptor (pc_inv_dsc).
2297 * In accordance with the Intel spec.
2298 * @{ */
2299/** Type (Lo). */
2300#define VTD_BF_0_PC_INV_DSC_TYPE_LO_SHIFT 0
2301#define VTD_BF_0_PC_INV_DSC_TYPE_LO_MASK UINT64_C(0x000000000000000f)
2302/** G: Granularity. */
2303#define VTD_BF_0_PC_INV_DSC_G_SHIFT 4
2304#define VTD_BF_0_PC_INV_DSC_G_MASK UINT64_C(0x0000000000000030)
2305/** R: Reserved (bits 8:6). */
2306#define VTD_BF_0_PC_INV_DSC_RSVD_8_6_SHIFT 6
2307#define VTD_BF_0_PC_INV_DSC_RSVD_8_6_MASK UINT64_C(0x00000000000001c0)
2308/** Type (Hi). */
2309#define VTD_BF_0_PC_INV_DSC_TYPE_HI_SHIFT 9
2310#define VTD_BF_0_PC_INV_DSC_TYPE_HI_MASK UINT64_C(0x0000000000000e00)
2311/** R: Reserved (bits 15:12). */
2312#define VTD_BF_0_PC_INV_DSC_RSVD_15_12_SHIFT 12
2313#define VTD_BF_0_PC_INV_DSC_RSVD_15_12_MASK UINT64_C(0x000000000000f000)
2314/** DID: Domain Id. */
2315#define VTD_BF_0_PC_INV_DSC_DID_SHIFT 16
2316#define VTD_BF_0_PC_INV_DSC_DID_MASK UINT64_C(0x00000000ffff0000)
2317/** PASID: Process Address-Space Id. */
2318#define VTD_BF_0_PC_INV_DSC_PASID_SHIFT 32
2319#define VTD_BF_0_PC_INV_DSC_PASID_MASK UINT64_C(0x000fffff00000000)
2320/** R: Reserved (bits 63:52). */
2321#define VTD_BF_0_PC_INV_DSC_RSVD_63_52_SHIFT 52
2322#define VTD_BF_0_PC_INV_DSC_RSVD_63_52_MASK UINT64_C(0xfff0000000000000)
2323
2324RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_PC_INV_DSC_, UINT64_C(0), UINT64_MAX,
2325 (TYPE_LO, G, RSVD_8_6, TYPE_HI, RSVD_15_12, DID, PASID, RSVD_63_52));
2326/** @} */
2327
2328
2329/** @name IOTLB Invalidate Descriptor (iotlb_inv_dsc).
2330 * In accordance with the Intel spec.
2331 * @{ */
2332/** Type (Lo). */
2333#define VTD_BF_0_IOTLB_INV_DSC_TYPE_LO_SHIFT 0
2334#define VTD_BF_0_IOTLB_INV_DSC_TYPE_LO_MASK UINT64_C(0x000000000000000f)
2335/** G: Granularity. */
2336#define VTD_BF_0_IOTLB_INV_DSC_G_SHIFT 4
2337#define VTD_BF_0_IOTLB_INV_DSC_G_MASK UINT64_C(0x0000000000000030)
2338/** DW: Drain Writes. */
2339#define VTD_BF_0_IOTLB_INV_DSC_DW_SHIFT 6
2340#define VTD_BF_0_IOTLB_INV_DSC_DW_MASK UINT64_C(0x0000000000000040)
2341/** DR: Drain Reads. */
2342#define VTD_BF_0_IOTLB_INV_DSC_DR_SHIFT 7
2343#define VTD_BF_0_IOTLB_INV_DSC_DR_MASK UINT64_C(0x0000000000000080)
2344/** R: Reserved (bit 8). */
2345#define VTD_BF_0_IOTLB_INV_DSC_RSVD_8_SHIFT 8
2346#define VTD_BF_0_IOTLB_INV_DSC_RSVD_8_MASK UINT64_C(0x0000000000000100)
2347/** Type (Hi). */
2348#define VTD_BF_0_IOTLB_INV_DSC_TYPE_HI_SHIFT 9
2349#define VTD_BF_0_IOTLB_INV_DSC_TYPE_HI_MASK UINT64_C(0x0000000000000e00)
2350/** R: Reserved (bits 15:12). */
2351#define VTD_BF_0_IOTLB_INV_DSC_RSVD_15_12_SHIFT 12
2352#define VTD_BF_0_IOTLB_INV_DSC_RSVD_15_12_MASK UINT64_C(0x000000000000f000)
2353/** DID: Domain Id. */
2354#define VTD_BF_0_IOTLB_INV_DSC_DID_SHIFT 16
2355#define VTD_BF_0_IOTLB_INV_DSC_DID_MASK UINT64_C(0x00000000ffff0000)
2356/** R: Reserved (bits 63:32). */
2357#define VTD_BF_0_IOTLB_INV_DSC_RSVD_63_32_SHIFT 32
2358#define VTD_BF_0_IOTLB_INV_DSC_RSVD_63_32_MASK UINT64_C(0xffffffff00000000)
2359RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_IOTLB_INV_DSC_, UINT64_C(0), UINT64_MAX,
2360 (TYPE_LO, G, DW, DR, RSVD_8, TYPE_HI, RSVD_15_12, DID, RSVD_63_32));
2361
2362/** AM: Address Mask. */
2363#define VTD_BF_1_IOTLB_INV_DSC_AM_SHIFT 0
2364#define VTD_BF_1_IOTLB_INV_DSC_AM_MASK UINT64_C(0x000000000000003f)
2365/** IH: Invalidation Hint. */
2366#define VTD_BF_1_IOTLB_INV_DSC_IH_SHIFT 6
2367#define VTD_BF_1_IOTLB_INV_DSC_IH_MASK UINT64_C(0x0000000000000040)
2368/** R: Reserved (bits 11:7). */
2369#define VTD_BF_1_IOTLB_INV_DSC_RSVD_11_7_SHIFT 7
2370#define VTD_BF_1_IOTLB_INV_DSC_RSVD_11_7_MASK UINT64_C(0x0000000000000f80)
2371/** ADDR: Address. */
2372#define VTD_BF_1_IOTLB_INV_DSC_ADDR_SHIFT 12
2373#define VTD_BF_1_IOTLB_INV_DSC_ADDR_MASK UINT64_C(0xfffffffffffff000)
2374RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_IOTLB_INV_DSC_, UINT64_C(0), UINT64_MAX,
2375 (AM, IH, RSVD_11_7, ADDR));
2376/** @} */
2377
2378
2379/** @name PASID-based IOTLB Invalidate Descriptor (p_iotlb_inv_dsc).
2380 * In accordance with the Intel spec.
2381 * @{ */
2382/** Type (Lo). */
2383#define VTD_BF_0_P_IOTLB_INV_DSC_TYPE_LO_SHIFT 0
2384#define VTD_BF_0_P_IOTLB_INV_DSC_TYPE_LO_MASK UINT64_C(0x000000000000000f)
2385/** G: Granularity. */
2386#define VTD_BF_0_P_IOTLB_INV_DSC_G_SHIFT 4
2387#define VTD_BF_0_P_IOTLB_INV_DSC_G_MASK UINT64_C(0x0000000000000030)
2388/** R: Reserved (bits 8:6). */
2389#define VTD_BF_0_P_IOTLB_INV_DSC_RSVD_8_6_SHIFT 6
2390#define VTD_BF_0_P_IOTLB_INV_DSC_RSVD_8_6_MASK UINT64_C(0x00000000000001c0)
2391/** Type (Hi). */
2392#define VTD_BF_0_P_IOTLB_INV_DSC_TYPE_HI_SHIFT 9
2393#define VTD_BF_0_P_IOTLB_INV_DSC_TYPE_HI_MASK UINT64_C(0x0000000000000e00)
2394/** R: Reserved (bits 15:12). */
2395#define VTD_BF_0_P_IOTLB_INV_DSC_RSVD_15_12_SHIFT 12
2396#define VTD_BF_0_P_IOTLB_INV_DSC_RSVD_15_12_MASK UINT64_C(0x000000000000f000)
2397/** DID: Domain Id. */
2398#define VTD_BF_0_P_IOTLB_INV_DSC_DID_SHIFT 16
2399#define VTD_BF_0_P_IOTLB_INV_DSC_DID_MASK UINT64_C(0x00000000ffff0000)
2400/** PASID: Process Address-Space Id. */
2401#define VTD_BF_0_P_IOTLB_INV_DSC_PASID_SHIFT 32
2402#define VTD_BF_0_P_IOTLB_INV_DSC_PASID_MASK UINT64_C(0x000fffff00000000)
2403/** R: Reserved (bits 63:52). */
2404#define VTD_BF_0_P_IOTLB_INV_DSC_RSVD_63_52_SHIFT 52
2405#define VTD_BF_0_P_IOTLB_INV_DSC_RSVD_63_52_MASK UINT64_C(0xfff0000000000000)
2406RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_P_IOTLB_INV_DSC_, UINT64_C(0), UINT64_MAX,
2407 (TYPE_LO, G, RSVD_8_6, TYPE_HI, RSVD_15_12, DID, PASID, RSVD_63_52));
2408
2409
2410/** AM: Address Mask. */
2411#define VTD_BF_1_P_IOTLB_INV_DSC_AM_SHIFT 0
2412#define VTD_BF_1_P_IOTLB_INV_DSC_AM_MASK UINT64_C(0x000000000000003f)
2413/** IH: Invalidation Hint. */
2414#define VTD_BF_1_P_IOTLB_INV_DSC_IH_SHIFT 6
2415#define VTD_BF_1_P_IOTLB_INV_DSC_IH_MASK UINT64_C(0x0000000000000040)
2416/** R: Reserved (bits 11:7). */
2417#define VTD_BF_1_P_IOTLB_INV_DSC_RSVD_11_7_SHIFT 7
2418#define VTD_BF_1_P_IOTLB_INV_DSC_RSVD_11_7_MASK UINT64_C(0x0000000000000f80)
2419/** ADDR: Address. */
2420#define VTD_BF_1_P_IOTLB_INV_DSC_ADDR_SHIFT 12
2421#define VTD_BF_1_P_IOTLB_INV_DSC_ADDR_MASK UINT64_C(0xfffffffffffff000)
2422RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_P_IOTLB_INV_DSC_, UINT64_C(0), UINT64_MAX,
2423 (AM, IH, RSVD_11_7, ADDR));
2424/** @} */
2425
2426
2427/** @name Device-TLB Invalidate Descriptor (dev_tlb_inv_dsc).
2428 * In accordance with the Intel spec.
2429 * @{ */
2430/** Type (Lo). */
2431#define VTD_BF_0_DEV_TLB_INV_DSC_TYPE_LO_SHIFT 0
2432#define VTD_BF_0_DEV_TLB_INV_DSC_TYPE_LO_MASK UINT64_C(0x000000000000000f)
2433/** R: Reserved (bits 8:4). */
2434#define VTD_BF_0_DEV_TLB_INV_DSC_RSVD_8_4_SHIFT 4
2435#define VTD_BF_0_DEV_TLB_INV_DSC_RSVD_8_4_MASK UINT64_C(0x00000000000001f0)
2436/** Type (Hi). */
2437#define VTD_BF_0_DEV_TLB_INV_DSC_TYPE_HI_SHIFT 9
2438#define VTD_BF_0_DEV_TLB_INV_DSC_TYPE_HI_MASK UINT64_C(0x0000000000000e00)
2439/** PFSID: Physical-Function Source Id (Lo). */
2440#define VTD_BF_0_DEV_TLB_INV_DSC_PFSID_LO_SHIFT 12
2441#define VTD_BF_0_DEV_TLB_INV_DSC_PFSID_LO_MASK UINT64_C(0x000000000000f000)
2442/** MIP: Max Invalidations Pending. */
2443#define VTD_BF_0_DEV_TLB_INV_DSC_MIP_SHIFT 16
2444#define VTD_BF_0_DEV_TLB_INV_DSC_MIP_MASK UINT64_C(0x00000000001f0000)
2445/** R: Reserved (bits 31:21). */
2446#define VTD_BF_0_DEV_TLB_INV_DSC_RSVD_31_21_SHIFT 21
2447#define VTD_BF_0_DEV_TLB_INV_DSC_RSVD_31_21_MASK UINT64_C(0x00000000ffe00000)
2448/** SID: Source Id. */
2449#define VTD_BF_0_DEV_TLB_INV_DSC_SID_SHIFT 32
2450#define VTD_BF_0_DEV_TLB_INV_DSC_SID_MASK UINT64_C(0x0000ffff00000000)
2451/** R: Reserved (bits 51:48). */
2452#define VTD_BF_0_DEV_TLB_INV_DSC_RSVD_51_48_SHIFT 48
2453#define VTD_BF_0_DEV_TLB_INV_DSC_RSVD_51_48_MASK UINT64_C(0x000f000000000000)
2454/** PFSID: Physical-Function Source Id (Hi). */
2455#define VTD_BF_0_DEV_TLB_INV_DSC_PFSID_HI_SHIFT 52
2456#define VTD_BF_0_DEV_TLB_INV_DSC_PFSID_HI_MASK UINT64_C(0xfff0000000000000)
2457RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_DEV_TLB_INV_DSC_, UINT64_C(0), UINT64_MAX,
2458 (TYPE_LO, RSVD_8_4, TYPE_HI, PFSID_LO, MIP, RSVD_31_21, SID, RSVD_51_48, PFSID_HI));
2459
2460/** S: Size. */
2461#define VTD_BF_1_DEV_TLB_INV_DSC_S_SHIFT 0
2462#define VTD_BF_1_DEV_TLB_INV_DSC_S_MASK UINT64_C(0x0000000000000001)
2463/** R: Reserved (bits 11:1). */
2464#define VTD_BF_1_DEV_TLB_INV_DSC_RSVD_11_1_SHIFT 1
2465#define VTD_BF_1_DEV_TLB_INV_DSC_RSVD_11_1_MASK UINT64_C(0x0000000000000ffe)
2466/** ADDR: Address. */
2467#define VTD_BF_1_DEV_TLB_INV_DSC_ADDR_SHIFT 12
2468#define VTD_BF_1_DEV_TLB_INV_DSC_ADDR_MASK UINT64_C(0xfffffffffffff000)
2469RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_DEV_TLB_INV_DSC_, UINT64_C(0), UINT64_MAX,
2470 (S, RSVD_11_1, ADDR));
2471/** @} */
2472
2473
2474/** @name PASID-based-device-TLB Invalidate Descriptor (p_dev_tlb_inv_dsc).
2475 * In accordance with the Intel spec.
2476 * @{ */
2477/** Type (Lo). */
2478#define VTD_BF_0_P_DEV_TLB_INV_DSC_TYPE_LO_SHIFT 0
2479#define VTD_BF_0_P_DEV_TLB_INV_DSC_TYPE_LO_MASK UINT64_C(0x000000000000000f)
2480/** MIP: Max Invalidations Pending. */
2481#define VTD_BF_0_P_DEV_TLB_INV_DSC_MIP_SHIFT 4
2482#define VTD_BF_0_P_DEV_TLB_INV_DSC_MIP_MASK UINT64_C(0x00000000000001f0)
2483/** Type (Hi). */
2484#define VTD_BF_0_P_DEV_TLB_INV_DSC_TYPE_HI_SHIFT 9
2485#define VTD_BF_0_P_DEV_TLB_INV_DSC_TYPE_HI_MASK UINT64_C(0x0000000000000e00)
2486/** PFSID: Physical-Function Source Id (Lo). */
2487#define VTD_BF_0_P_DEV_TLB_INV_DSC_PFSID_LO_SHIFT 12
2488#define VTD_BF_0_P_DEV_TLB_INV_DSC_PFSID_LO_MASK UINT64_C(0x000000000000f000)
2489/** SID: Source Id. */
2490#define VTD_BF_0_P_DEV_TLB_INV_DSC_SID_SHIFT 16
2491#define VTD_BF_0_P_DEV_TLB_INV_DSC_SID_MASK UINT64_C(0x00000000ffff0000)
2492/** PASID: Process Address-Space Id. */
2493#define VTD_BF_0_P_DEV_TLB_INV_DSC_PASID_SHIFT 32
2494#define VTD_BF_0_P_DEV_TLB_INV_DSC_PASID_MASK UINT64_C(0x000fffff00000000)
2495/** PFSID: Physical-Function Source Id (Hi). */
2496#define VTD_BF_0_P_DEV_TLB_INV_DSC_PFSID_HI_SHIFT 52
2497#define VTD_BF_0_P_DEV_TLB_INV_DSC_PFSID_HI_MASK UINT64_C(0xfff0000000000000)
2498RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_P_DEV_TLB_INV_DSC_, UINT64_C(0), UINT64_MAX,
2499 (TYPE_LO, MIP, TYPE_HI, PFSID_LO, SID, PASID, PFSID_HI));
2500
2501/** G: Granularity. */
2502#define VTD_BF_1_P_DEV_TLB_INV_DSC_G_SHIFT 0
2503#define VTD_BF_1_P_DEV_TLB_INV_DSC_G_MASK UINT64_C(0x0000000000000001)
2504/** R: Reserved (bits 10:1). */
2505#define VTD_BF_1_P_DEV_TLB_INV_DSC_RSVD_10_1_SHIFT 1
2506#define VTD_BF_1_P_DEV_TLB_INV_DSC_RSVD_10_1_MASK UINT64_C(0x00000000000007fe)
2507/** S: Size. */
2508#define VTD_BF_1_P_DEV_TLB_INV_DSC_S_SHIFT 11
2509#define VTD_BF_1_P_DEV_TLB_INV_DSC_S_MASK UINT64_C(0x0000000000000800)
2510/** ADDR: Address. */
2511#define VTD_BF_1_P_DEV_TLB_INV_DSC_ADDR_SHIFT 12
2512#define VTD_BF_1_P_DEV_TLB_INV_DSC_ADDR_MASK UINT64_C(0xfffffffffffff000)
2513RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_P_DEV_TLB_INV_DSC_, UINT64_C(0), UINT64_MAX,
2514 (G, RSVD_10_1, S, ADDR));
2515/** @} */
2516
2517
2518/** @name Interrupt Entry Cache Invalidate Descriptor (iec_inv_dsc).
2519 * In accordance with the Intel spec.
2520 * @{ */
2521/** Type (Lo). */
2522#define VTD_BF_0_IEC_INV_DSC_TYPE_LO_SHIFT 0
2523#define VTD_BF_0_IEC_INV_DSC_TYPE_LO_MASK UINT64_C(0x000000000000000f)
2524/** G: Granularity. */
2525#define VTD_BF_0_IEC_INV_DSC_G_SHIFT 4
2526#define VTD_BF_0_IEC_INV_DSC_G_MASK UINT64_C(0x0000000000000010)
2527/** R: Reserved (bits 8:5). */
2528#define VTD_BF_0_IEC_INV_DSC_RSVD_8_5_SHIFT 5
2529#define VTD_BF_0_IEC_INV_DSC_RSVD_8_5_MASK UINT64_C(0x00000000000001e0)
2530/** Type (Hi). */
2531#define VTD_BF_0_IEC_INV_DSC_TYPE_HI_SHIFT 9
2532#define VTD_BF_0_IEC_INV_DSC_TYPE_HI_MASK UINT64_C(0x0000000000000e00)
2533/** R: Reserved (bits 26:12). */
2534#define VTD_BF_0_IEC_INV_DSC_RSVD_26_12_SHIFT 12
2535#define VTD_BF_0_IEC_INV_DSC_RSVD_26_12_MASK UINT64_C(0x0000000007fff000)
2536/** IM: Index Mask. */
2537#define VTD_BF_0_IEC_INV_DSC_IM_SHIFT 27
2538#define VTD_BF_0_IEC_INV_DSC_IM_MASK UINT64_C(0x00000000f8000000)
2539/** IIDX: Interrupt Index. */
2540#define VTD_BF_0_IEC_INV_DSC_IIDX_SHIFT 32
2541#define VTD_BF_0_IEC_INV_DSC_IIDX_MASK UINT64_C(0x0000ffff00000000)
2542/** R: Reserved (bits 63:48). */
2543#define VTD_BF_0_IEC_INV_DSC_RSVD_63_48_SHIFT 48
2544#define VTD_BF_0_IEC_INV_DSC_RSVD_63_48_MASK UINT64_C(0xffff000000000000)
2545RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_IEC_INV_DSC_, UINT64_C(0), UINT64_MAX,
2546 (TYPE_LO, G, RSVD_8_5, TYPE_HI, RSVD_26_12, IM, IIDX, RSVD_63_48));
2547/** @} */
2548
2549
2550/** @name Invalidation Wait Descriptor (inv_wait_dsc).
2551 * In accordance with the Intel spec.
2552 * @{ */
2553/** Type (Lo). */
2554#define VTD_BF_0_INV_WAIT_DSC_TYPE_LO_SHIFT 0
2555#define VTD_BF_0_INV_WAIT_DSC_TYPE_LO_MASK UINT64_C(0x000000000000000f)
2556/** IF: Interrupt Flag. */
2557#define VTD_BF_0_INV_WAIT_DSC_IF_SHIFT 4
2558#define VTD_BF_0_INV_WAIT_DSC_IF_MASK UINT64_C(0x0000000000000010)
2559/** SW: Status Write. */
2560#define VTD_BF_0_INV_WAIT_DSC_SW_SHIFT 5
2561#define VTD_BF_0_INV_WAIT_DSC_SW_MASK UINT64_C(0x0000000000000020)
2562/** FN: Fence Flag. */
2563#define VTD_BF_0_INV_WAIT_DSC_FN_SHIFT 6
2564#define VTD_BF_0_INV_WAIT_DSC_FN_MASK UINT64_C(0x0000000000000040)
2565/** PD: Page-Request Drain. */
2566#define VTD_BF_0_INV_WAIT_DSC_PD_SHIFT 7
2567#define VTD_BF_0_INV_WAIT_DSC_PD_MASK UINT64_C(0x0000000000000080)
2568/** R: Reserved (bit 8). */
2569#define VTD_BF_0_INV_WAIT_DSC_RSVD_8_SHIFT 8
2570#define VTD_BF_0_INV_WAIT_DSC_RSVD_8_MASK UINT64_C(0x0000000000000100)
2571/** Type (Hi). */
2572#define VTD_BF_0_INV_WAIT_DSC_TYPE_HI_SHIFT 9
2573#define VTD_BF_0_INV_WAIT_DSC_TYPE_HI_MASK UINT64_C(0x0000000000000e00)
2574/** R: Reserved (bits 31:12). */
2575#define VTD_BF_0_INV_WAIT_DSC_RSVD_31_12_SHIFT 12
2576#define VTD_BF_0_INV_WAIT_DSC_RSVD_31_12_MASK UINT64_C(0x00000000fffff000)
2577/** STDATA: Status Data. */
2578#define VTD_BF_0_INV_WAIT_DSC_STDATA_SHIFT 32
2579#define VTD_BF_0_INV_WAIT_DSC_STDATA_MASK UINT64_C(0xffffffff00000000)
2580RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_INV_WAIT_DSC_, UINT64_C(0), UINT64_MAX,
2581 (TYPE_LO, IF, SW, FN, PD, RSVD_8, TYPE_HI, RSVD_31_12, STDATA));
2582
2583/** R: Reserved (bits 1:0). */
2584#define VTD_BF_1_INV_WAIT_DSC_RSVD_1_0_SHIFT 0
2585#define VTD_BF_1_INV_WAIT_DSC_RSVD_1_0_MASK UINT64_C(0x0000000000000003)
2586/** STADDR: Status Address. */
2587#define VTD_BF_1_INV_WAIT_DSC_STADDR_SHIFT 2
2588#define VTD_BF_1_INV_WAIT_DSC_STADDR_MASK UINT64_C(0xfffffffffffffffc)
2589RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_INV_WAIT_DSC_, UINT64_C(0), UINT64_MAX,
2590 (RSVD_1_0, STADDR));
2591
2592/* INV_WAIT_DSC: Qword 0 valid mask. */
2593#define VTD_INV_WAIT_DSC_0_VALID_MASK ( VTD_BF_0_INV_WAIT_DSC_TYPE_LO_MASK \
2594 | VTD_BF_0_INV_WAIT_DSC_IF_MASK \
2595 | VTD_BF_0_INV_WAIT_DSC_SW_MASK \
2596 | VTD_BF_0_INV_WAIT_DSC_FN_MASK \
2597 | VTD_BF_0_INV_WAIT_DSC_PD_MASK \
2598 | VTD_BF_0_INV_WAIT_DSC_TYPE_HI_MASK \
2599 | VTD_BF_0_INV_WAIT_DSC_STDATA_MASK)
2600/* INV_WAIT_DSC: Qword 1 valid mask. */
2601#define VTD_INV_WAIT_DSC_1_VALID_MASK VTD_BF_1_INV_WAIT_DSC_STADDR_MASK
2602/** @} */
2603
2604
2605/** @name Invalidation descriptor types.
2606 * In accordance with the Intel spec.
2607 * @{ */
2608#define VTD_CC_INV_DSC_TYPE 1
2609#define VTD_IOTLB_INV_DSC_TYPE 2
2610#define VTD_DEV_TLB_INV_DSC_TYPE 3
2611#define VTD_IEC_INV_DSC_TYPE 4
2612#define VTD_INV_WAIT_DSC_TYPE 5
2613#define VTD_P_IOTLB_INV_DSC_TYPE 6
2614#define VTD_PC_INV_DSC_TYPE 7
2615#define VTD_P_DEV_TLB_INV_DSC_TYPE 8
2616/** @} */
2617
2618
2619/** @name Remappable Format Interrupt Request.
2620 * In accordance with the Intel spec.
2621 * @{ */
2622/** IGN: Ignored (bits 1:0). */
2623#define VTD_BF_REMAPPABLE_MSI_ADDR_IGN_1_0_SHIFT 0
2624#define VTD_BF_REMAPPABLE_MSI_ADDR_IGN_1_0_MASK UINT32_C(0x00000003)
2625/** Handle (Hi). */
2626#define VTD_BF_REMAPPABLE_MSI_ADDR_HANDLE_HI_SHIFT 2
2627#define VTD_BF_REMAPPABLE_MSI_ADDR_HANDLE_HI_MASK UINT32_C(0x00000004)
2628/** SHV: Subhandle Valid. */
2629#define VTD_BF_REMAPPABLE_MSI_ADDR_SHV_SHIFT 3
2630#define VTD_BF_REMAPPABLE_MSI_ADDR_SHV_MASK UINT32_C(0x00000008)
2631/** Interrupt format. */
2632#define VTD_BF_REMAPPABLE_MSI_ADDR_INTR_FMT_SHIFT 4
2633#define VTD_BF_REMAPPABLE_MSI_ADDR_INTR_FMT_MASK UINT32_C(0x00000010)
2634/** Handle (Lo). */
2635#define VTD_BF_REMAPPABLE_MSI_ADDR_HANDLE_LO_SHIFT 5
2636#define VTD_BF_REMAPPABLE_MSI_ADDR_HANDLE_LO_MASK UINT32_C(0x000fffe0)
2637/** Address. */
2638#define VTD_BF_REMAPPABLE_MSI_ADDR_ADDR_SHIFT 20
2639#define VTD_BF_REMAPPABLE_MSI_ADDR_ADDR_MASK UINT32_C(0xfff00000)
2640RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_REMAPPABLE_MSI_ADDR_, UINT32_C(0), UINT32_MAX,
2641 (IGN_1_0, HANDLE_HI, SHV, INTR_FMT, HANDLE_LO, ADDR));
2642
2643/** Subhandle. */
2644#define VTD_BF_REMAPPABLE_MSI_DATA_SUBHANDLE_SHIFT 0
2645#define VTD_BF_REMAPPABLE_MSI_DATA_SUBHANDLE_MASK UINT32_C(0x0000ffff)
2646/** R: Reserved (bits 31:16). */
2647#define VTD_BF_REMAPPABLE_MSI_DATA_RSVD_31_16_SHIFT 16
2648#define VTD_BF_REMAPPABLE_MSI_DATA_RSVD_31_16_MASK UINT32_C(0xffff0000)
2649RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_REMAPPABLE_MSI_DATA_, UINT32_C(0), UINT32_MAX,
2650 (SUBHANDLE, RSVD_31_16));
2651
2652/** Remappable MSI Address: Valid mask. */
2653#define VTD_REMAPPABLE_MSI_ADDR_VALID_MASK UINT32_MAX
2654/** Remappable MSI Data: Valid mask. */
2655#define VTD_REMAPPABLE_MSI_DATA_VALID_MASK VTD_BF_REMAPPABLE_MSI_DATA_SUBHANDLE_MASK
2656
2657/** Interrupt format: Compatibility. */
2658#define VTD_INTR_FORMAT_COMPAT 0
2659/** Interrupt format: Remappable. */
2660#define VTD_INTR_FORMAT_REMAPPABLE 1
2661/** @} */
2662
2663
2664/** @name Interrupt Remapping Fault Conditions.
2665 * In accordance with the Intel spec.
2666 * @{ */
2667typedef enum VTDIRFAULT
2668{
2669 /** Reserved bits invalid in remappable interrupt. */
2670 VTDIRFAULT_REMAPPABLE_INTR_RSVD = 0x20,
2671
2672 /** Interrupt index for remappable interrupt exceeds table size or referenced
2673 * address above host address width (HAW) */
2674 VTDIRFAULT_INTR_INDEX_INVALID = 0x21,
2675
2676 /** The IRTE is not present. */
2677 VTDIRFAULT_IRTE_NOT_PRESENT = 0x22,
2678 /** Reading IRTE from memory failed. */
2679 VTDIRFAULT_IRTE_READ_FAILED = 0x23,
2680 /** IRTE reserved bits invalid for an IRTE with Present bit set. */
2681 VTDIRFAULT_IRTE_PRESENT_RSVD = 0x24,
2682
2683 /** Compatibility format interrupt (CFI) blocked due to EIME being enabled or CFIs
2684 * were disabled. */
2685 VTDIRFAULT_CFI_BLOCKED = 0x25,
2686
2687 /** IRTE SID, SVT, SQ bits invalid for an IRTE with Present bit set. */
2688 VTDIRFAULT_IRTE_PRESENT_INVALID = 0x26,
2689
2690 /** Reading posted interrupt descriptor (PID) failed. */
2691 VTDIRFAULT_PID_READ_FAILED = 0x27,
2692 /** PID reserved bits invalid. */
2693 VTDIRFAULT_PID_RSVD = 0x28,
2694
2695 /** Untranslated interrupt requested (without PASID) is invalid. */
2696 VTDIRFAULT_IR_WITHOUT_PASID_INVALID = 0x29
2697} VTDIRFAULT;
2698AssertCompileSize(VTDIRFAULT, 4);
2699/** @} */
2700
2701
2702/** @name Address Translation Fault Conditions.
2703 * In accordance with the Intel spec.
2704 * @{ */
2705typedef enum VTDATFAULT
2706{
2707 /* Legacy root table faults (LRT). */
2708 VTDATFAULT_LRT_1 = 0x8,
2709 VTDATFAULT_LRT_2 = 0x1,
2710 VTDATFAULT_LRT_3 = 0xa,
2711
2712 /* Legacy Context-Table Faults (LCT). */
2713 VTDATFAULT_LCT_1 = 0x9,
2714 VTDATFAULT_LCT_2 = 0x2,
2715 VTDATFAULT_LCT_3 = 0xb,
2716 VTDATFAULT_LCT_4_1 = 0x3,
2717 VTDATFAULT_LCT_4_2 = 0x3,
2718 VTDATFAULT_LCT_4_3 = 0x3,
2719 VTDATFAULT_LCT_5 = 0xd,
2720
2721 /* Legacy Second-Level Table Faults (LSL). */
2722 VTDATFAULT_LSL_1 = 0x7,
2723 VTDATFAULT_LSL_2 = 0xc,
2724
2725 /* Legacy General Faults (LGN). */
2726 VTDATFAULT_LGN_1_1 = 0x4,
2727 VTDATFAULT_LGN_1_2 = 0x4,
2728 VTDATFAULT_LGN_1_3 = 0x4,
2729 VTDATFAULT_LGN_2 = 0x5,
2730 VTDATFAULT_LGN_3 = 0x6,
2731 VTDATFAULT_LGN_4 = 0xe,
2732
2733 /* Root-Table Address Register Faults (RTA). */
2734 VTDATFAULT_RTA_1_1 = 0x30,
2735 VTDATFAULT_RTA_1_2 = 0x30,
2736 VTDATFAULT_RTA_1_3 = 0x30,
2737 VTDATFAULT_RTA_2 = 0x31,
2738 VTDATFAULT_RTA_3 = 0x32,
2739 VTDATFAULT_RTA_4 = 0x33,
2740
2741 /* Scalable-Mode Root-Table Faults (SRT). */
2742 VTDATFAULT_SRT_1 = 0x38,
2743 VTDATFAULT_SRT_2 = 0x39,
2744 VTDATFAULT_SRT_3 = 0x3a,
2745
2746 /* Scalable-Mode Context-Table Faults (SCT). */
2747 VTDATFAULT_SCT_1 = 0x40,
2748 VTDATFAULT_SCT_2 = 0x41,
2749 VTDATFAULT_SCT_3 = 0x42,
2750 VTDATFAULT_SCT_4_1 = 0x43,
2751 VTDATFAULT_SCT_4_2 = 0x43,
2752 VTDATFAULT_SCT_5 = 0x44,
2753 VTDATFAULT_SCT_6 = 0x45,
2754 VTDATFAULT_SCT_7 = 0x46,
2755 VTDATFAULT_SCT_8 = 0x47,
2756 VTDATFAULT_SCT_9 = 0x48,
2757
2758 /* Scalable-Mode PASID-Directory Faults (SPD). */
2759 VTDATFAULT_SPD_1 = 0x50,
2760 VTDATFAULT_SPD_2 = 0x51,
2761 VTDATFAULT_SPD_3 = 0x52,
2762
2763 /* Scalable-Mode PASID-Table Faults (SPT). */
2764 VTDATFAULT_SPT_1 = 0x58,
2765 VTDATFAULT_SPT_2 = 0x59,
2766 VTDATFAULT_SPT_3 = 0x5a,
2767 VTDATFAULT_SPT_4_1 = 0x5b,
2768 VTDATFAULT_SPT_4_2 = 0x5b,
2769 VTDATFAULT_SPT_4_3 = 0x5b,
2770 VTDATFAULT_SPT_4_4 = 0x5b,
2771 VTDATFAULT_SPT_5 = 0x5c,
2772 VTDATFAULT_SPT_6 = 0x5d,
2773
2774 /* Scalable-Mode First-Level Table Faults (SFL). */
2775 VTDATFAULT_SFL_1 = 0x70,
2776 VTDATFAULT_SFL_2 = 0x71,
2777 VTDATFAULT_SFL_3 = 0x72,
2778 VTDATFAULT_SFL_4 = 0x73,
2779 VTDATFAULT_SFL_5 = 0x74,
2780 VTDATFAULT_SFL_6 = 0x75,
2781 VTDATFAULT_SFL_7 = 0x76,
2782 VTDATFAULT_SFL_8 = 0x77,
2783 VTDATFAULT_SFL_9 = 0x90,
2784 VTDATFAULT_SFL_10 = 0x91,
2785
2786 /* Scalable-Mode Second-Level Table Faults (SSL). */
2787 VTDATFAULT_SSL_1 = 0x78,
2788 VTDATFAULT_SSL_2 = 0x79,
2789 VTDATFAULT_SSL_3 = 0x7a,
2790 VTDATFAULT_SSL_4 = 0x7b,
2791 VTDATFAULT_SSL_5 = 0x7c,
2792 VTDATFAULT_SSL_6 = 0x7d,
2793
2794 /* Scalable-Mode General Faults (SGN). */
2795 VTDATFAULT_SGN_1 = 0x80,
2796 VTDATFAULT_SGN_2 = 0x81,
2797 VTDATFAULT_SGN_3 = 0x82,
2798 VTDATFAULT_SGN_4_1 = 0x83,
2799 VTDATFAULT_SGN_4_2 = 0x83,
2800 VTDATFAULT_SGN_5 = 0x84,
2801 VTDATFAULT_SGN_6 = 0x85,
2802 VTDATFAULT_SGN_7 = 0x86,
2803 VTDATFAULT_SGN_8 = 0x87,
2804 VTDATFAULT_SGN_9 = 0x88,
2805 VTDATFAULT_SGN_10 = 0x89
2806} VTDATFAULT;
2807AssertCompileSize(VTDATFAULT, 4);
2808/** @} */
2809
2810
2811/** @name ACPI_DMAR_F_XXX: DMA Remapping Reporting Structure Flags.
2812 * In accordance with the Intel spec.
2813 * @{ */
2814/** INTR_REMAP: Interrupt remapping supported. */
2815#define ACPI_DMAR_F_INTR_REMAP RT_BIT(0)
2816/** X2APIC_OPT_OUT: Request system software to opt-out of enabling x2APIC. */
2817#define ACPI_DMAR_F_X2APIC_OPT_OUT RT_BIT(1)
2818/** DMA_CTRL_PLATFORM_OPT_IN_FLAG: Firmware initiated DMA restricted to reserved
2819 * memory regions (RMRR). */
2820#define ACPI_DMAR_F_DMA_CTRL_PLATFORM_OPT_IN RT_BIT(2)
2821/** @} */
2822
2823
2824/** @name ACPI_DRHD_F_XXX: DMA-Remapping Hardware Unit Definition Flags.
2825 * In accordance with the Intel spec.
2826 * @{ */
2827/** INCLUDE_PCI_ALL: All PCI devices under scope. */
2828#define ACPI_DRHD_F_INCLUDE_PCI_ALL RT_BIT(0)
2829/** @} */
2830
2831
2832/**
2833 * DRHD: DMA-Remapping Hardware Unit Definition.
2834 * In accordance with the Intel spec.
2835 */
2836#pragma pack(1)
2837typedef struct ACPIDRHD
2838{
2839 /** Type (must be 0=DRHD). */
2840 uint16_t uType;
2841 /** Length (must be 16 + size of device scope structure). */
2842 uint16_t cbLength;
2843 /** Flags, see ACPI_DRHD_F_XXX. */
2844 uint8_t fFlags;
2845 /** Reserved (MBZ). */
2846 uint8_t bRsvd;
2847 /** PCI segment number. */
2848 uint16_t uPciSegment;
2849 /** Register Base Address (MMIO). */
2850 uint64_t uRegBaseAddr;
2851 /* Device Scope[] Structures follow. */
2852} ACPIDRHD;
2853#pragma pack()
2854AssertCompileSize(ACPIDRHD, 16);
2855AssertCompileMemberOffset(ACPIDRHD, cbLength, 2);
2856AssertCompileMemberOffset(ACPIDRHD, fFlags, 4);
2857AssertCompileMemberOffset(ACPIDRHD, uPciSegment, 6);
2858AssertCompileMemberOffset(ACPIDRHD, uRegBaseAddr, 8);
2859
2860
2861/** @name ACPIDMARDEVSCOPE_TYPE_XXX: Device Type.
2862 * In accordance with the Intel spec.
2863 * @{ */
2864#define ACPIDMARDEVSCOPE_TYPE_PCI_ENDPOINT 1
2865#define ACPIDMARDEVSCOPE_TYPE_PCI_SUB_HIERARCHY 2
2866#define ACPIDMARDEVSCOPE_TYPE_IOAPIC 3
2867#define ACPIDMARDEVSCOPE_TYPE_MSI_CAP_HPET 4
2868#define ACPIDMARDEVSCOPE_TYPE_ACPI_NAMESPACE_DEV 5
2869/** @} */
2870
2871
2872/**
2873 * ACPI Device Scope Structure - PCI device path.
2874 * In accordance with the Intel spec.
2875 */
2876typedef struct ACPIDEVSCOPEPATH
2877{
2878 /** PCI device number. */
2879 uint8_t uDevice;
2880 /** PCI function number. */
2881 uint8_t uFunction;
2882} ACPIDEVSCOPEPATH;
2883AssertCompileSize(ACPIDEVSCOPEPATH, 2);
2884
2885
2886/**
2887 * Device Scope Structure.
2888 * In accordance with the Intel spec.
2889 */
2890#pragma pack(1)
2891typedef struct ACPIDMARDEVSCOPE
2892{
2893 /** Type, see ACPIDMARDEVSCOPE_TYPE_XXX. */
2894 uint8_t uType;
2895 /** Length (must be 6 + size of auPath field). */
2896 uint8_t cbLength;
2897 /** Reserved (MBZ). */
2898 uint8_t abRsvd[2];
2899 /** Enumeration ID (for I/O APIC, HPET and ACPI namespace devices). */
2900 uint8_t idEnum;
2901 /** First bus number for this device. */
2902 uint8_t uStartBusNum;
2903 /** Hierarchical path from the Host Bridge to the device. */
2904 ACPIDEVSCOPEPATH Path;
2905} ACPIDMARDEVSCOPE;
2906#pragma pack()
2907AssertCompileMemberOffset(ACPIDMARDEVSCOPE, cbLength, 1);
2908AssertCompileMemberOffset(ACPIDMARDEVSCOPE, idEnum, 4);
2909AssertCompileMemberOffset(ACPIDMARDEVSCOPE, uStartBusNum, 5);
2910AssertCompileMemberOffset(ACPIDMARDEVSCOPE, Path, 6);
2911
2912/** ACPI DMAR revision (not the OEM revision field).
2913 * In accordance with the Intel spec. */
2914#define ACPI_DMAR_REVISION 1
2915
2916
2917#endif /* !VBOX_INCLUDED_iommu_intel_h */
2918
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