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source: vbox/trunk/include/VBox/iommu-intel.h@ 93941

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1/** @file
2 * IOMMU - Input/Output Memory Management Unit (Intel).
3 */
4
5/*
6 * Copyright (C) 2021-2022 Oracle Corporation
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * The contents of this file may alternatively be used under the terms
17 * of the Common Development and Distribution License Version 1.0
18 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19 * VirtualBox OSE distribution, in which case the provisions of the
20 * CDDL are applicable instead of those of the GPL.
21 *
22 * You may elect to license modified versions of this file under the
23 * terms and conditions of either the GPL or the CDDL or both.
24 */
25
26#ifndef VBOX_INCLUDED_iommu_intel_h
27#define VBOX_INCLUDED_iommu_intel_h
28#ifndef RT_WITHOUT_PRAGMA_ONCE
29# pragma once
30#endif
31
32#include <iprt/assertcompile.h>
33#include <iprt/types.h>
34
35
36/**
37 * @name MMIO register offsets.
38 * In accordance with the Intel spec.
39 * @{
40 */
41#define VTD_MMIO_OFF_VER_REG 0x000 /**< Version. */
42#define VTD_MMIO_OFF_CAP_REG 0x008 /**< Capability. */
43#define VTD_MMIO_OFF_ECAP_REG 0x010 /**< Extended Capability. */
44#define VTD_MMIO_OFF_GCMD_REG 0x018 /**< Global Command. */
45#define VTD_MMIO_OFF_GSTS_REG 0x01c /**< Global Status. */
46#define VTD_MMIO_OFF_RTADDR_REG 0x020 /**< Root Table Address. */
47#define VTD_MMIO_OFF_CCMD_REG 0x028 /**< Context Command. */
48
49#define VTD_MMIO_OFF_FSTS_REG 0x034 /**< Fault Status.*/
50#define VTD_MMIO_OFF_FECTL_REG 0x038 /**< Fault Event Control.*/
51#define VTD_MMIO_OFF_FEDATA_REG 0x03c /**< Fault Event Data. */
52#define VTD_MMIO_OFF_FEADDR_REG 0x040 /**< Fault Event Address. */
53#define VTD_MMIO_OFF_FEUADDR_REG 0x044 /**< Fault Event Upper Address. */
54
55#define VTD_MMIO_OFF_AFLOG_REG 0x058 /**< Advance Fault Log. */
56
57#define VTD_MMIO_OFF_PMEN_REG 0x064 /**< Protected Memory Enable (PMEN). */
58#define VTD_MMIO_OFF_PLMBASE_REG 0x068 /**< Protected Low Memory Base. */
59#define VTD_MMIO_OFF_PLMLIMIT_REG 0x06c /**< Protected Low Memory Limit. */
60#define VTD_MMIO_OFF_PHMBASE_REG 0x070 /**< Protected High Memory Base. */
61#define VTD_MMIO_OFF_PHMLIMIT_REG 0x078 /**< Protected High Memory Limit. */
62
63#define VTD_MMIO_OFF_IQH_REG 0x080 /**< Invalidation Queue Head. */
64#define VTD_MMIO_OFF_IQT_REG 0x088 /**< Invalidation Queue Tail. */
65#define VTD_MMIO_OFF_IQA_REG 0x090 /**< Invalidation Queue Address. */
66#define VTD_MMIO_OFF_ICS_REG 0x09c /**< Invalidation Completion Status. */
67#define VTD_MMIO_OFF_IECTL_REG 0x0a0 /**< Invalidation Completion Event Control. */
68#define VTD_MMIO_OFF_IEDATA_REG 0x0a4 /**< Invalidation Completion Event Data. */
69#define VTD_MMIO_OFF_IEADDR_REG 0x0a8 /**< Invalidation Completion Event Address. */
70#define VTD_MMIO_OFF_IEUADDR_REG 0x0ac /**< Invalidation Completion Event Upper Address. */
71#define VTD_MMIO_OFF_IQERCD_REG 0x0b0 /**< Invalidation Queue Error Record. */
72
73#define VTD_MMIO_OFF_IRTA_REG 0x0b8 /**< Interrupt Remapping Table Address. */
74
75#define VTD_MMIO_OFF_PQH_REG 0x0c0 /**< Page Request Queue Head. */
76#define VTD_MMIO_OFF_PQT_REG 0x0c8 /**< Page Request Queue Tail. */
77#define VTD_MMIO_OFF_PQA_REG 0x0d0 /**< Page Request Queue Address. */
78#define VTD_MMIO_OFF_PRS_REG 0x0dc /**< Page Request Status. */
79#define VTD_MMIO_OFF_PECTL_REG 0x0e0 /**< Page Request Event Control. */
80#define VTD_MMIO_OFF_PEDATA_REG 0x0e4 /**< Page Request Event Data. */
81#define VTD_MMIO_OFF_PEADDR_REG 0x0e8 /**< Page Request Event Address. */
82#define VTD_MMIO_OFF_PEUADDR_REG 0x0ec /**< Page Request Event Upper Address. */
83
84#define VTD_MMIO_OFF_MTRRCAP_REG 0x100 /**< MTRR Capabliity. */
85#define VTD_MMIO_OFF_MTRRDEF_REG 0x108 /**< MTRR Default Type. */
86
87#define VTD_MMIO_OFF_MTRR_FIX64_00000_REG 0x120 /**< Fixed-range MTRR Register for 64K at 00000. */
88#define VTD_MMIO_OFF_MTRR_FIX16K_80000_REG 0x128 /**< Fixed-range MTRR Register for 16K at 80000. */
89#define VTD_MMIO_OFF_MTRR_FIX16K_A0000_REG 0x130 /**< Fixed-range MTRR Register for 16K at a0000. */
90#define VTD_MMIO_OFF_MTRR_FIX4K_C0000_REG 0x138 /**< Fixed-range MTRR Register for 4K at c0000. */
91#define VTD_MMIO_OFF_MTRR_FIX4K_C8000_REG 0x140 /**< Fixed-range MTRR Register for 4K at c8000. */
92#define VTD_MMIO_OFF_MTRR_FIX4K_D0000_REG 0x148 /**< Fixed-range MTRR Register for 4K at d0000. */
93#define VTD_MMIO_OFF_MTRR_FIX4K_D8000_REG 0x150 /**< Fixed-range MTRR Register for 4K at d8000. */
94#define VTD_MMIO_OFF_MTRR_FIX4K_E0000_REG 0x158 /**< Fixed-range MTRR Register for 4K at e0000. */
95#define VTD_MMIO_OFF_MTRR_FIX4K_E8000_REG 0x160 /**< Fixed-range MTRR Register for 4K at e8000. */
96#define VTD_MMIO_OFF_MTRR_FIX4K_F0000_REG 0x168 /**< Fixed-range MTRR Register for 4K at f0000. */
97#define VTD_MMIO_OFF_MTRR_FIX4K_F8000_REG 0x170 /**< Fixed-range MTRR Register for 4K at f8000. */
98
99#define VTD_MMIO_OFF_MTRR_PHYSBASE0_REG 0x180 /**< Variable-range MTRR Base 0. */
100#define VTD_MMIO_OFF_MTRR_PHYSMASK0_REG 0x188 /**< Variable-range MTRR Mask 0. */
101#define VTD_MMIO_OFF_MTRR_PHYSBASE1_REG 0x190 /**< Variable-range MTRR Base 1. */
102#define VTD_MMIO_OFF_MTRR_PHYSMASK1_REG 0x198 /**< Variable-range MTRR Mask 1. */
103#define VTD_MMIO_OFF_MTRR_PHYSBASE2_REG 0x1a0 /**< Variable-range MTRR Base 2. */
104#define VTD_MMIO_OFF_MTRR_PHYSMASK2_REG 0x1a8 /**< Variable-range MTRR Mask 2. */
105#define VTD_MMIO_OFF_MTRR_PHYSBASE3_REG 0x1b0 /**< Variable-range MTRR Base 3. */
106#define VTD_MMIO_OFF_MTRR_PHYSMASK3_REG 0x1b8 /**< Variable-range MTRR Mask 3. */
107#define VTD_MMIO_OFF_MTRR_PHYSBASE4_REG 0x1c0 /**< Variable-range MTRR Base 4. */
108#define VTD_MMIO_OFF_MTRR_PHYSMASK4_REG 0x1c8 /**< Variable-range MTRR Mask 4. */
109#define VTD_MMIO_OFF_MTRR_PHYSBASE5_REG 0x1d0 /**< Variable-range MTRR Base 5. */
110#define VTD_MMIO_OFF_MTRR_PHYSMASK5_REG 0x1d8 /**< Variable-range MTRR Mask 5. */
111#define VTD_MMIO_OFF_MTRR_PHYSBASE6_REG 0x1e0 /**< Variable-range MTRR Base 6. */
112#define VTD_MMIO_OFF_MTRR_PHYSMASK6_REG 0x1e8 /**< Variable-range MTRR Mask 6. */
113#define VTD_MMIO_OFF_MTRR_PHYSBASE7_REG 0x1f0 /**< Variable-range MTRR Base 7. */
114#define VTD_MMIO_OFF_MTRR_PHYSMASK7_REG 0x1f8 /**< Variable-range MTRR Mask 7. */
115#define VTD_MMIO_OFF_MTRR_PHYSBASE8_REG 0x200 /**< Variable-range MTRR Base 8. */
116#define VTD_MMIO_OFF_MTRR_PHYSMASK8_REG 0x208 /**< Variable-range MTRR Mask 8. */
117#define VTD_MMIO_OFF_MTRR_PHYSBASE9_REG 0x210 /**< Variable-range MTRR Base 9. */
118#define VTD_MMIO_OFF_MTRR_PHYSMASK9_REG 0x218 /**< Variable-range MTRR Mask 9. */
119
120#define VTD_MMIO_OFF_VCCAP_REG 0xe00 /**< Virtual Command Capability. */
121#define VTD_MMIO_OFF_VCMD_REG 0xe10 /**< Virtual Command. */
122#define VTD_MMIO_OFF_VCMDRSVD_REG 0xe18 /**< Reserved for future for Virtual Command. */
123#define VTD_MMIO_OFF_VCRSP_REG 0xe20 /**< Virtual Command Response. */
124#define VTD_MMIO_OFF_VCRSPRSVD_REG 0xe28 /**< Reserved for future for Virtual Command Response. */
125/** @} */
126
127
128/** @name Root Entry.
129 * In accordance with the Intel spec.
130 * @{ */
131/** P: Present. */
132#define VTD_BF_0_ROOT_ENTRY_P_SHIFT 0
133#define VTD_BF_0_ROOT_ENTRY_P_MASK UINT64_C(0x0000000000000001)
134/** R: Reserved (bits 11:1). */
135#define VTD_BF_0_ROOT_ENTRY_RSVD_11_1_SHIFT 1
136#define VTD_BF_0_ROOT_ENTRY_RSVD_11_1_MASK UINT64_C(0x0000000000000ffe)
137/** CTP: Context-Table Pointer. */
138#define VTD_BF_0_ROOT_ENTRY_CTP_SHIFT 12
139#define VTD_BF_0_ROOT_ENTRY_CTP_MASK UINT64_C(0xfffffffffffff000)
140RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_ROOT_ENTRY_, UINT64_C(0), UINT64_MAX,
141 (P, RSVD_11_1, CTP));
142
143/** Root Entry. */
144typedef struct VTD_ROOT_ENTRY_T
145{
146 /** The qwords in the root entry. */
147 uint64_t au64[2];
148} VTD_ROOT_ENTRY_T;
149/** Pointer to a root entry. */
150typedef VTD_ROOT_ENTRY_T *PVTD_ROOT_ENTRY_T;
151/** Pointer to a const root entry. */
152typedef VTD_ROOT_ENTRY_T const *PCVTD_ROOT_ENTRY_T;
153
154/* Root Entry: Qword 0 valid mask. */
155#define VTD_ROOT_ENTRY_0_VALID_MASK (VTD_BF_0_ROOT_ENTRY_P_MASK | VTD_BF_0_ROOT_ENTRY_CTP_MASK)
156/* Root Entry: Qword 1 valid mask. */
157#define VTD_ROOT_ENTRY_1_VALID_MASK UINT64_C(0)
158/** @} */
159
160
161/** @name Scalable-mode Root Entry.
162 * In accordance with the Intel spec.
163 * @{ */
164/** LP: Lower Present. */
165#define VTD_BF_0_SM_ROOT_ENTRY_LP_SHIFT 0
166#define VTD_BF_0_SM_ROOT_ENTRY_LP_MASK UINT64_C(0x0000000000000001)
167/** R: Reserved (bits 11:1). */
168#define VTD_BF_0_SM_ROOT_ENTRY_RSVD_11_1_SHIFT 1
169#define VTD_BF_0_SM_ROOT_ENTRY_RSVD_11_1_MASK UINT64_C(0x0000000000000ffe)
170/** LCTP: Lower Context-Table Pointer */
171#define VTD_BF_0_SM_ROOT_ENTRY_LCTP_SHIFT 12
172#define VTD_BF_0_SM_ROOT_ENTRY_LCTP_MASK UINT64_C(0xfffffffffffff000)
173RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_SM_ROOT_ENTRY_, UINT64_C(0), UINT64_MAX,
174 (LP, RSVD_11_1, LCTP));
175
176/** UP: Upper Present. */
177#define VTD_BF_1_SM_ROOT_ENTRY_UP_SHIFT 0
178#define VTD_BF_1_SM_ROOT_ENTRY_UP_MASK UINT64_C(0x0000000000000001)
179/** R: Reserved (bits 11:1). */
180#define VTD_BF_1_SM_ROOT_ENTRY_RSVD_11_1_SHIFT 1
181#define VTD_BF_1_SM_ROOT_ENTRY_RSVD_11_1_MASK UINT64_C(0x0000000000000ffe)
182/** UCTP: Upper Context-Table Pointer. */
183#define VTD_BF_1_SM_ROOT_ENTRY_UCTP_SHIFT 12
184#define VTD_BF_1_SM_ROOT_ENTRY_UCTP_MASK UINT64_C(0xfffffffffffff000)
185RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_SM_ROOT_ENTRY_, UINT64_C(0), UINT64_MAX,
186 (UP, RSVD_11_1, UCTP));
187
188/** Scalable-mode root entry. */
189typedef struct VTD_SM_ROOT_ENTRY_T
190{
191 /** The lower scalable-mode root entry. */
192 uint64_t uLower;
193 /** The upper scalable-mode root entry. */
194 uint64_t uUpper;
195} VTD_SM_ROOT_ENTRY_T;
196/** Pointer to a scalable-mode root entry. */
197typedef VTD_SM_ROOT_ENTRY_T *PVTD_SM_ROOT_ENTRY_T;
198/** Pointer to a const scalable-mode root entry. */
199typedef VTD_SM_ROOT_ENTRY_T const *PCVTD_SM_ROOT_ENTRY_T;
200/** @} */
201
202
203/** @name Context Entry.
204 * In accordance with the Intel spec.
205 * @{ */
206/** P: Present. */
207#define VTD_BF_0_CONTEXT_ENTRY_P_SHIFT 0
208#define VTD_BF_0_CONTEXT_ENTRY_P_MASK UINT64_C(0x0000000000000001)
209/** FPD: Fault Processing Disable. */
210#define VTD_BF_0_CONTEXT_ENTRY_FPD_SHIFT 1
211#define VTD_BF_0_CONTEXT_ENTRY_FPD_MASK UINT64_C(0x0000000000000002)
212/** TT: Translation Type. */
213#define VTD_BF_0_CONTEXT_ENTRY_TT_SHIFT 2
214#define VTD_BF_0_CONTEXT_ENTRY_TT_MASK UINT64_C(0x000000000000000c)
215/** R: Reserved (bits 11:4). */
216#define VTD_BF_0_CONTEXT_ENTRY_RSVD_11_4_SHIFT 4
217#define VTD_BF_0_CONTEXT_ENTRY_RSVD_11_4_MASK UINT64_C(0x0000000000000ff0)
218/** SLPTPTR: Second Level Page Translation Pointer. */
219#define VTD_BF_0_CONTEXT_ENTRY_SLPTPTR_SHIFT 12
220#define VTD_BF_0_CONTEXT_ENTRY_SLPTPTR_MASK UINT64_C(0xfffffffffffff000)
221RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_CONTEXT_ENTRY_, UINT64_C(0), UINT64_MAX,
222 (P, FPD, TT, RSVD_11_4, SLPTPTR));
223
224/** AW: Address Width. */
225#define VTD_BF_1_CONTEXT_ENTRY_AW_SHIFT 0
226#define VTD_BF_1_CONTEXT_ENTRY_AW_MASK UINT64_C(0x0000000000000007)
227/** IGN: Ignored (bits 6:3). */
228#define VTD_BF_1_CONTEXT_ENTRY_IGN_6_3_SHIFT 3
229#define VTD_BF_1_CONTEXT_ENTRY_IGN_6_3_MASK UINT64_C(0x0000000000000078)
230/** R: Reserved (bit 7). */
231#define VTD_BF_1_CONTEXT_ENTRY_RSVD_7_SHIFT 7
232#define VTD_BF_1_CONTEXT_ENTRY_RSVD_7_MASK UINT64_C(0x0000000000000080)
233/** DID: Domain Identifier. */
234#define VTD_BF_1_CONTEXT_ENTRY_DID_SHIFT 8
235#define VTD_BF_1_CONTEXT_ENTRY_DID_MASK UINT64_C(0x0000000000ffff00)
236/** R: Reserved (bits 63:24). */
237#define VTD_BF_1_CONTEXT_ENTRY_RSVD_63_24_SHIFT 24
238#define VTD_BF_1_CONTEXT_ENTRY_RSVD_63_24_MASK UINT64_C(0xffffffffff000000)
239RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_CONTEXT_ENTRY_, UINT64_C(0), UINT64_MAX,
240 (AW, IGN_6_3, RSVD_7, DID, RSVD_63_24));
241
242/** Context Entry. */
243typedef struct VTD_CONTEXT_ENTRY_T
244{
245 /** The qwords in the context entry. */
246 uint64_t au64[2];
247} VTD_CONTEXT_ENTRY_T;
248/** Pointer to a context entry. */
249typedef VTD_CONTEXT_ENTRY_T *PVTD_CONTEXT_ENTRY_T;
250/** Pointer to a const context entry. */
251typedef VTD_CONTEXT_ENTRY_T const *PCVTD_CONTEXT_ENTRY_T;
252AssertCompileSize(VTD_CONTEXT_ENTRY_T, 16);
253
254/** Context Entry: Qword 0 valid mask. */
255#define VTD_CONTEXT_ENTRY_0_VALID_MASK ( VTD_BF_0_CONTEXT_ENTRY_P_MASK \
256 | VTD_BF_0_CONTEXT_ENTRY_FPD_MASK \
257 | VTD_BF_0_CONTEXT_ENTRY_TT_MASK \
258 | VTD_BF_0_CONTEXT_ENTRY_SLPTPTR_MASK)
259/** Context Entry: Qword 1 valid mask. */
260#define VTD_CONTEXT_ENTRY_1_VALID_MASK ( VTD_BF_1_CONTEXT_ENTRY_AW_MASK \
261 | VTD_BF_1_CONTEXT_ENTRY_IGN_6_3_MASK \
262 | VTD_BF_1_CONTEXT_ENTRY_DID_MASK)
263
264/** Translation Type: Untranslated requests uses second-level paging. */
265#define VTD_TT_UNTRANSLATED_SLP 0
266/** Translation Type: Untranslated requests requires device-TLB support. */
267#define VTD_TT_UNTRANSLATED_DEV_TLB 1
268/** Translation Type: Untranslated requests are pass-through. */
269#define VTD_TT_UNTRANSLATED_PT 2
270/** Translation Type: Reserved. */
271#define VTD_TT_RSVD 3
272/** @} */
273
274
275/** @name Scalable-mode Context Entry.
276 * In accordance with the Intel spec.
277 * @{ */
278/** P: Present. */
279#define VTD_BF_0_SM_CONTEXT_ENTRY_P_SHIFT 0
280#define VTD_BF_0_SM_CONTEXT_ENTRY_P_MASK UINT64_C(0x0000000000000001)
281/** FPD: Fault Processing Disable. */
282#define VTD_BF_0_SM_CONTEXT_ENTRY_FPD_SHIFT 1
283#define VTD_BF_0_SM_CONTEXT_ENTRY_FPD_MASK UINT64_C(0x0000000000000002)
284/** DTE: Device-TLB Enable. */
285#define VTD_BF_0_SM_CONTEXT_ENTRY_DTE_SHIFT 2
286#define VTD_BF_0_SM_CONTEXT_ENTRY_DTE_MASK UINT64_C(0x0000000000000004)
287/** PASIDE: PASID Enable. */
288#define VTD_BF_0_SM_CONTEXT_ENTRY_PASIDE_SHIFT 3
289#define VTD_BF_0_SM_CONTEXT_ENTRY_PASIDE_MASK UINT64_C(0x0000000000000008)
290/** PRE: Page Request Enable. */
291#define VTD_BF_0_SM_CONTEXT_ENTRY_PRE_SHIFT 4
292#define VTD_BF_0_SM_CONTEXT_ENTRY_PRE_MASK UINT64_C(0x0000000000000010)
293/** R: Reserved (bits 8:5). */
294#define VTD_BF_0_SM_CONTEXT_ENTRY_RSVD_8_5_SHIFT 5
295#define VTD_BF_0_SM_CONTEXT_ENTRY_RSVD_8_5_MASK UINT64_C(0x00000000000001e0)
296/** PDTS: PASID Directory Size. */
297#define VTD_BF_0_SM_CONTEXT_ENTRY_PDTS_SHIFT 9
298#define VTD_BF_0_SM_CONTEXT_ENTRY_PDTS_MASK UINT64_C(0x0000000000000e00)
299/** PASIDDIRPTR: PASID Directory Pointer. */
300#define VTD_BF_0_SM_CONTEXT_ENTRY_PASIDDIRPTR_SHIFT 12
301#define VTD_BF_0_SM_CONTEXT_ENTRY_PASIDDIRPTR_MASK UINT64_C(0xfffffffffffff000)
302RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_SM_CONTEXT_ENTRY_, UINT64_C(0), UINT64_MAX,
303 (P, FPD, DTE, PASIDE, PRE, RSVD_8_5, PDTS, PASIDDIRPTR));
304
305/** RID_PASID: Requested Id to PASID assignment. */
306#define VTD_BF_1_SM_CONTEXT_ENTRY_RID_PASID_SHIFT 0
307#define VTD_BF_1_SM_CONTEXT_ENTRY_RID_PASID_MASK UINT64_C(0x00000000000fffff)
308/** RID_PRIV: Requested Id to PrivilegeModeRequested assignment. */
309#define VTD_BF_1_SM_CONTEXT_ENTRY_RID_PRIV_SHIFT 20
310#define VTD_BF_1_SM_CONTEXT_ENTRY_RID_PRIV_MASK UINT64_C(0x0000000000100000)
311/** R: Reserved (bits 63:21). */
312#define VTD_BF_1_SM_CONTEXT_ENTRY_RSVD_63_21_SHIFT 21
313#define VTD_BF_1_SM_CONTEXT_ENTRY_RSVD_63_21_MASK UINT64_C(0xffffffffffe00000)
314RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_SM_CONTEXT_ENTRY_, UINT64_C(0), UINT64_MAX,
315 (RID_PASID, RID_PRIV, RSVD_63_21));
316
317/** Scalable-mode Context Entry. */
318typedef struct VTD_SM_CONTEXT_ENTRY_T
319{
320 /** The qwords in the scalable-mode context entry. */
321 uint64_t au64[4];
322} VTD_SM_CONTEXT_ENTRY_T;
323/** Pointer to a scalable-mode context entry. */
324typedef VTD_SM_CONTEXT_ENTRY_T *PVTD_SM_CONTEXT_ENTRY_T;
325/** Pointer to a const scalable-mode context entry. */
326typedef VTD_SM_CONTEXT_ENTRY_T const *PCVTD_SM_CONTEXT_ENTRY_T;
327/** @} */
328
329
330/** @name Scalable-mode PASID Directory Entry.
331 * In accordance with the Intel spec.
332 * @{ */
333/** P: Present. */
334#define VTD_BF_SM_PASID_DIR_ENTRY_P_SHIFT 0
335#define VTD_BF_SM_PASID_DIR_ENTRY_P_MASK UINT64_C(0x0000000000000001)
336/** FPD: Fault Processing Disable. */
337#define VTD_BF_SM_PASID_DIR_ENTRY_FPD_SHIFT 1
338#define VTD_BF_SM_PASID_DIR_ENTRY_FPD_MASK UINT64_C(0x0000000000000002)
339/** R: Reserved (bits 11:2). */
340#define VTD_BF_SM_PASID_DIR_ENTRY_RSVD_11_2_SHIFT 2
341#define VTD_BF_SM_PASID_DIR_ENTRY_RSVD_11_2_MASK UINT64_C(0x0000000000000ffc)
342/** SMPTBLPTR: Scalable Mode PASID Table Pointer. */
343#define VTD_BF_SM_PASID_DIR_ENTRY_SMPTBLPTR_SHIFT 12
344#define VTD_BF_SM_PASID_DIR_ENTRY_SMPTBLPTR_MASK UINT64_C(0xfffffffffffff000)
345RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_SM_PASID_DIR_ENTRY_, UINT64_C(0), UINT64_MAX,
346 (P, FPD, RSVD_11_2, SMPTBLPTR));
347
348/** Scalable-mode PASID Directory Entry. */
349typedef struct VTD_SM_PASID_DIR_ENTRY_T
350{
351 /** The scalable-mode PASID directory entry. */
352 uint64_t u;
353} VTD_SM_PASID_DIR_ENTRY_T;
354/** Pointer to a scalable-mode PASID directory entry. */
355typedef VTD_SM_PASID_DIR_ENTRY_T *PVTD_SM_PASID_DIR_ENTRY_T;
356/** Pointer to a const scalable-mode PASID directory entry. */
357typedef VTD_SM_PASID_DIR_ENTRY_T const *PCVTD_SM_PASID_DIR_ENTRY_T;
358/** @} */
359
360
361/** @name Scalable-mode PASID Table Entry.
362 * In accordance with the Intel spec.
363 * @{ */
364/** P: Present. */
365#define VTD_BF_0_SM_PASID_TBL_ENTRY_P_SHIFT 0
366#define VTD_BF_0_SM_PASID_TBL_ENTRY_P_MASK UINT64_C(0x0000000000000001)
367/** FPD: Fault Processing Disable. */
368#define VTD_BF_0_SM_PASID_TBL_ENTRY_FPD_SHIFT 1
369#define VTD_BF_0_SM_PASID_TBL_ENTRY_FPD_MASK UINT64_C(0x0000000000000002)
370/** AW: Address Width. */
371#define VTD_BF_0_SM_PASID_TBL_ENTRY_AW_SHIFT 2
372#define VTD_BF_0_SM_PASID_TBL_ENTRY_AW_MASK UINT64_C(0x000000000000001c)
373/** SLEE: Second-Level Execute Enable. */
374#define VTD_BF_0_SM_PASID_TBL_ENTRY_SLEE_SHIFT 5
375#define VTD_BF_0_SM_PASID_TBL_ENTRY_SLEE_MASK UINT64_C(0x0000000000000020)
376/** PGTT: PASID Granular Translation Type. */
377#define VTD_BF_0_SM_PASID_TBL_ENTRY_PGTT_SHIFT 6
378#define VTD_BF_0_SM_PASID_TBL_ENTRY_PGTT_MASK UINT64_C(0x00000000000001c0)
379/** SLADE: Second-Level Address/Dirty Enable. */
380#define VTD_BF_0_SM_PASID_TBL_ENTRY_SLADE_SHIFT 9
381#define VTD_BF_0_SM_PASID_TBL_ENTRY_SLADE_MASK UINT64_C(0x0000000000000200)
382/** R: Reserved (bits 11:10). */
383#define VTD_BF_0_SM_PASID_TBL_ENTRY_RSVD_11_10_SHIFT 10
384#define VTD_BF_0_SM_PASID_TBL_ENTRY_RSVD_11_10_MASK UINT64_C(0x0000000000000c00)
385/** SLPTPTR: Second-Level Page Table Pointer. */
386#define VTD_BF_0_SM_PASID_TBL_ENTRY_SLPTPTR_SHIFT 12
387#define VTD_BF_0_SM_PASID_TBL_ENTRY_SLPTPTR_MASK UINT64_C(0xfffffffffffff000)
388RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_SM_PASID_TBL_ENTRY_, UINT64_C(0), UINT64_MAX,
389 (P, FPD, AW, SLEE, PGTT, SLADE, RSVD_11_10, SLPTPTR));
390
391/** DID: Domain Identifer. */
392#define VTD_BF_1_SM_PASID_TBL_ENTRY_DID_SHIFT 0
393#define VTD_BF_1_SM_PASID_TBL_ENTRY_DID_MASK UINT64_C(0x000000000000ffff)
394/** R: Reserved (bits 22:16). */
395#define VTD_BF_1_SM_PASID_TBL_ENTRY_RSVD_22_16_SHIFT 16
396#define VTD_BF_1_SM_PASID_TBL_ENTRY_RSVD_22_16_MASK UINT64_C(0x00000000007f0000)
397/** PWSNP: Page-Walk Snoop. */
398#define VTD_BF_1_SM_PASID_TBL_ENTRY_PWSNP_SHIFT 23
399#define VTD_BF_1_SM_PASID_TBL_ENTRY_PWSNP_MASK UINT64_C(0x0000000000800000)
400/** PGSNP: Page Snoop. */
401#define VTD_BF_1_SM_PASID_TBL_ENTRY_PGSNP_SHIFT 24
402#define VTD_BF_1_SM_PASID_TBL_ENTRY_PGSNP_MASK UINT64_C(0x0000000001000000)
403/** CD: Cache Disable. */
404#define VTD_BF_1_SM_PASID_TBL_ENTRY_CD_SHIFT 25
405#define VTD_BF_1_SM_PASID_TBL_ENTRY_CD_MASK UINT64_C(0x0000000002000000)
406/** EMTE: Extended Memory Type Enable. */
407#define VTD_BF_1_SM_PASID_TBL_ENTRY_EMTE_SHIFT 26
408#define VTD_BF_1_SM_PASID_TBL_ENTRY_EMTE_MASK UINT64_C(0x0000000004000000)
409/** EMT: Extended Memory Type. */
410#define VTD_BF_1_SM_PASID_TBL_ENTRY_EMT_SHIFT 27
411#define VTD_BF_1_SM_PASID_TBL_ENTRY_EMT_MASK UINT64_C(0x0000000038000000)
412/** PWT: Page-Level Write Through. */
413#define VTD_BF_1_SM_PASID_TBL_ENTRY_PWT_SHIFT 30
414#define VTD_BF_1_SM_PASID_TBL_ENTRY_PWT_MASK UINT64_C(0x0000000040000000)
415/** PCD: Page-Level Cache Disable. */
416#define VTD_BF_1_SM_PASID_TBL_ENTRY_PCD_SHIFT 31
417#define VTD_BF_1_SM_PASID_TBL_ENTRY_PCD_MASK UINT64_C(0x0000000080000000)
418/** PAT: Page Attribute Table. */
419#define VTD_BF_1_SM_PASID_TBL_ENTRY_PAT_SHIFT 32
420#define VTD_BF_1_SM_PASID_TBL_ENTRY_PAT_MASK UINT64_C(0xffffffff00000000)
421RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_SM_PASID_TBL_ENTRY_, UINT64_C(0), UINT64_MAX,
422 (DID, RSVD_22_16, PWSNP, PGSNP, CD, EMTE, EMT, PWT, PCD, PAT));
423
424/** SRE: Supervisor Request Enable. */
425#define VTD_BF_2_SM_PASID_TBL_ENTRY_SRE_SHIFT 0
426#define VTD_BF_2_SM_PASID_TBL_ENTRY_SRE_MASK UINT64_C(0x0000000000000001)
427/** ERE: Execute Request Enable. */
428#define VTD_BF_2_SM_PASID_TBL_ENTRY_ERE_SHIFT 1
429#define VTD_BF_2_SM_PASID_TBL_ENTRY_ERE_MASK UINT64_C(0x0000000000000002)
430/** FLPM: First Level Paging Mode. */
431#define VTD_BF_2_SM_PASID_TBL_ENTRY_FLPM_SHIFT 2
432#define VTD_BF_2_SM_PASID_TBL_ENTRY_FLPM_MASK UINT64_C(0x000000000000000c)
433/** WPE: Write Protect Enable. */
434#define VTD_BF_2_SM_PASID_TBL_ENTRY_WPE_SHIFT 4
435#define VTD_BF_2_SM_PASID_TBL_ENTRY_WPE_MASK UINT64_C(0x0000000000000010)
436/** NXE: No-Execute Enable. */
437#define VTD_BF_2_SM_PASID_TBL_ENTRY_NXE_SHIFT 5
438#define VTD_BF_2_SM_PASID_TBL_ENTRY_NXE_MASK UINT64_C(0x0000000000000020)
439/** SMEP: Supervisor Mode Execute Prevent. */
440#define VTD_BF_2_SM_PASID_TBL_ENTRY_SMPE_SHIFT 6
441#define VTD_BF_2_SM_PASID_TBL_ENTRY_SMPE_MASK UINT64_C(0x0000000000000040)
442/** EAFE: Extended Accessed Flag Enable. */
443#define VTD_BF_2_SM_PASID_TBL_ENTRY_EAFE_SHIFT 7
444#define VTD_BF_2_SM_PASID_TBL_ENTRY_EAFE_MASK UINT64_C(0x0000000000000080)
445/** R: Reserved (bits 11:8). */
446#define VTD_BF_2_SM_PASID_TBL_ENTRY_RSVD_11_8_SHIFT 8
447#define VTD_BF_2_SM_PASID_TBL_ENTRY_RSVD_11_8_MASK UINT64_C(0x0000000000000f00)
448/** FLPTPTR: First Level Page Table Pointer. */
449#define VTD_BF_2_SM_PASID_TBL_ENTRY_FLPTPTR_SHIFT 12
450#define VTD_BF_2_SM_PASID_TBL_ENTRY_FLPTPTR_MASK UINT64_C(0xfffffffffffff000)
451RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_2_SM_PASID_TBL_ENTRY_, UINT64_C(0), UINT64_MAX,
452 (SRE, ERE, FLPM, WPE, NXE, SMPE, EAFE, RSVD_11_8, FLPTPTR));
453
454/** Scalable-mode PASID Table Entry. */
455typedef struct VTD_SM_PASID_TBL_ENTRY_T
456{
457 /** The qwords in the scalable-mode PASID table entry. */
458 uint64_t au64[8];
459} VTD_SM_PASID_TBL_ENTRY_T;
460/** Pointer to a scalable-mode PASID table entry. */
461typedef VTD_SM_PASID_TBL_ENTRY_T *PVTD_SM_PASID_TBL_ENTRY_T;
462/** Pointer to a const scalable-mode PASID table entry. */
463typedef VTD_SM_PASID_TBL_ENTRY_T const *PCVTD_SM_PASID_TBL_ENTRY_T;
464/** @} */
465
466
467/** @name First-Level Paging Entry.
468 * In accordance with the Intel spec.
469 * @{ */
470/** P: Present. */
471#define VTD_BF_FLP_ENTRY_P_SHIFT 0
472#define VTD_BF_FLP_ENTRY_P_MASK UINT64_C(0x0000000000000001)
473/** R/W: Read/Write. */
474#define VTD_BF_FLP_ENTRY_RW_SHIFT 1
475#define VTD_BF_FLP_ENTRY_RW_MASK UINT64_C(0x0000000000000002)
476/** U/S: User/Supervisor. */
477#define VTD_BF_FLP_ENTRY_US_SHIFT 2
478#define VTD_BF_FLP_ENTRY_US_MASK UINT64_C(0x0000000000000004)
479/** PWT: Page-Level Write Through. */
480#define VTD_BF_FLP_ENTRY_PWT_SHIFT 3
481#define VTD_BF_FLP_ENTRY_PWT_MASK UINT64_C(0x0000000000000008)
482/** PC: Page-Level Cache Disable. */
483#define VTD_BF_FLP_ENTRY_PCD_SHIFT 4
484#define VTD_BF_FLP_ENTRY_PCD_MASK UINT64_C(0x0000000000000010)
485/** A: Accessed. */
486#define VTD_BF_FLP_ENTRY_A_SHIFT 5
487#define VTD_BF_FLP_ENTRY_A_MASK UINT64_C(0x0000000000000020)
488/** IGN: Ignored (bit 6). */
489#define VTD_BF_FLP_ENTRY_IGN_6_SHIFT 6
490#define VTD_BF_FLP_ENTRY_IGN_6_MASK UINT64_C(0x0000000000000040)
491/** R: Reserved (bit 7). */
492#define VTD_BF_FLP_ENTRY_RSVD_7_SHIFT 7
493#define VTD_BF_FLP_ENTRY_RSVD_7_MASK UINT64_C(0x0000000000000080)
494/** IGN: Ignored (bits 9:8). */
495#define VTD_BF_FLP_ENTRY_IGN_9_8_SHIFT 8
496#define VTD_BF_FLP_ENTRY_IGN_9_8_MASK UINT64_C(0x0000000000000300)
497/** EA: Extended Accessed. */
498#define VTD_BF_FLP_ENTRY_EA_SHIFT 10
499#define VTD_BF_FLP_ENTRY_EA_MASK UINT64_C(0x0000000000000400)
500/** IGN: Ignored (bit 11). */
501#define VTD_BF_FLP_ENTRY_IGN_11_SHIFT 11
502#define VTD_BF_FLP_ENTRY_IGN_11_MASK UINT64_C(0x0000000000000800)
503/** ADDR: Address. */
504#define VTD_BF_FLP_ENTRY_ADDR_SHIFT 12
505#define VTD_BF_FLP_ENTRY_ADDR_MASK UINT64_C(0x000ffffffffff000)
506/** IGN: Ignored (bits 62:52). */
507#define VTD_BF_FLP_ENTRY_IGN_62_52_SHIFT 52
508#define VTD_BF_FLP_ENTRY_IGN_62_52_MASK UINT64_C(0x7ff0000000000000)
509/** XD: Execute Disabled. */
510#define VTD_BF_FLP_ENTRY_XD_SHIFT 63
511#define VTD_BF_FLP_ENTRY_XD_MASK UINT64_C(0x8000000000000000)
512RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_FLP_ENTRY_, UINT64_C(0), UINT64_MAX,
513 (P, RW, US, PWT, PCD, A, IGN_6, RSVD_7, IGN_9_8, EA, IGN_11, ADDR, IGN_62_52, XD));
514/** @} */
515
516
517/** @name Second-Level PML5E.
518 * In accordance with the Intel spec.
519 * @{ */
520/** R: Read. */
521#define VTD_BF_SL_PML5E_R_SHIFT 0
522#define VTD_BF_SL_PML5E_R_MASK UINT64_C(0x0000000000000001)
523/** W: Write. */
524#define VTD_BF_SL_PML5E_W_SHIFT 1
525#define VTD_BF_SL_PML5E_W_MASK UINT64_C(0x0000000000000002)
526/** X: Execute. */
527#define VTD_BF_SL_PML5E_X_SHIFT 2
528#define VTD_BF_SL_PML5E_X_MASK UINT64_C(0x0000000000000004)
529/** IGN: Ignored (bits 6:3). */
530#define VTD_BF_SL_PML5E_IGN_6_3_SHIFT 3
531#define VTD_BF_SL_PML5E_IGN_6_3_MASK UINT64_C(0x0000000000000078)
532/** R: Reserved (bit 7). */
533#define VTD_BF_SL_PML5E_RSVD_7_SHIFT 7
534#define VTD_BF_SL_PML5E_RSVD_7_MASK UINT64_C(0x0000000000000080)
535/** A: Accessed. */
536#define VTD_BF_SL_PML5E_A_SHIFT 8
537#define VTD_BF_SL_PML5E_A_MASK UINT64_C(0x0000000000000100)
538/** IGN: Ignored (bits 10:9). */
539#define VTD_BF_SL_PML5E_IGN_10_9_SHIFT 9
540#define VTD_BF_SL_PML5E_IGN_10_9_MASK UINT64_C(0x0000000000000600)
541/** R: Reserved (bit 11). */
542#define VTD_BF_SL_PML5E_RSVD_11_SHIFT 11
543#define VTD_BF_SL_PML5E_RSVD_11_MASK UINT64_C(0x0000000000000800)
544/** ADDR: Address. */
545#define VTD_BF_SL_PML5E_ADDR_SHIFT 12
546#define VTD_BF_SL_PML5E_ADDR_MASK UINT64_C(0x000ffffffffff000)
547/** IGN: Ignored (bits 61:52). */
548#define VTD_BF_SL_PML5E_IGN_61_52_SHIFT 52
549#define VTD_BF_SL_PML5E_IGN_61_52_MASK UINT64_C(0x3ff0000000000000)
550/** R: Reserved (bit 62). */
551#define VTD_BF_SL_PML5E_RSVD_62_SHIFT 62
552#define VTD_BF_SL_PML5E_RSVD_62_MASK UINT64_C(0x4000000000000000)
553/** IGN: Ignored (bit 63). */
554#define VTD_BF_SL_PML5E_IGN_63_SHIFT 63
555#define VTD_BF_SL_PML5E_IGN_63_MASK UINT64_C(0x8000000000000000)
556RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_SL_PML5E_, UINT64_C(0), UINT64_MAX,
557 (R, W, X, IGN_6_3, RSVD_7, A, IGN_10_9, RSVD_11, ADDR, IGN_61_52, RSVD_62, IGN_63));
558
559/** Second-level PML5E valid mask. */
560#define VTD_SL_PML5E_VALID_MASK ( VTD_BF_SL_PML5E_R_MASK | VTD_BF_SL_PML5E_W_MASK \
561 | VTD_BF_SL_PML5E_X_MASK | VTD_BF_SL_PML5E_IGN_6_3_MASK \
562 | VTD_BF_SL_PML5E_A_MASK | VTD_BF_SL_PML5E_IGN_10_9_MASK \
563 | VTD_BF_SL_PML5E_ADDR_MASK | VTD_BF_SL_PML5E_IGN_61_52_MASK \
564 | VTD_BF_SL_PML5E_IGN_63_MASK)
565/** @} */
566
567
568/** @name Second-Level PML4E.
569 * In accordance with the Intel spec.
570 * @{ */
571/** R: Read. */
572#define VTD_BF_SL_PML4E_R_SHIFT 0
573#define VTD_BF_SL_PML4E_R_MASK UINT64_C(0x0000000000000001)
574/** W: Write. */
575#define VTD_BF_SL_PML4E_W_SHIFT 1
576#define VTD_BF_SL_PML4E_W_MASK UINT64_C(0x0000000000000002)
577/** X: Execute. */
578#define VTD_BF_SL_PML4E_X_SHIFT 2
579#define VTD_BF_SL_PML4E_X_MASK UINT64_C(0x0000000000000004)
580/** IGN: Ignored (bits 6:3). */
581#define VTD_BF_SL_PML4E_IGN_6_3_SHIFT 3
582#define VTD_BF_SL_PML4E_IGN_6_3_MASK UINT64_C(0x0000000000000078)
583/** R: Reserved (bit 7). */
584#define VTD_BF_SL_PML4E_RSVD_7_SHIFT 7
585#define VTD_BF_SL_PML4E_RSVD_7_MASK UINT64_C(0x0000000000000080)
586/** A: Accessed. */
587#define VTD_BF_SL_PML4E_A_SHIFT 8
588#define VTD_BF_SL_PML4E_A_MASK UINT64_C(0x0000000000000100)
589/** IGN: Ignored (bits 10:9). */
590#define VTD_BF_SL_PML4E_IGN_10_9_SHIFT 9
591#define VTD_BF_SL_PML4E_IGN_10_9_MASK UINT64_C(0x0000000000000600)
592/** R: Reserved (bit 11). */
593#define VTD_BF_SL_PML4E_RSVD_11_SHIFT 11
594#define VTD_BF_SL_PML4E_RSVD_11_MASK UINT64_C(0x0000000000000800)
595/** ADDR: Address. */
596#define VTD_BF_SL_PML4E_ADDR_SHIFT 12
597#define VTD_BF_SL_PML4E_ADDR_MASK UINT64_C(0x000ffffffffff000)
598/** IGN: Ignored (bits 61:52). */
599#define VTD_BF_SL_PML4E_IGN_61_52_SHIFT 52
600#define VTD_BF_SL_PML4E_IGN_61_52_MASK UINT64_C(0x3ff0000000000000)
601/** R: Reserved (bit 62). */
602#define VTD_BF_SL_PML4E_RSVD_62_SHIFT 62
603#define VTD_BF_SL_PML4E_RSVD_62_MASK UINT64_C(0x4000000000000000)
604/** IGN: Ignored (bit 63). */
605#define VTD_BF_SL_PML4E_IGN_63_SHIFT 63
606#define VTD_BF_SL_PML4E_IGN_63_MASK UINT64_C(0x8000000000000000)
607RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_SL_PML4E_, UINT64_C(0), UINT64_MAX,
608 (R, W, X, IGN_6_3, RSVD_7, A, IGN_10_9, RSVD_11, ADDR, IGN_61_52, RSVD_62, IGN_63));
609
610/** Second-level PML4E valid mask. */
611#define VTD_SL_PML4E_VALID_MASK VTD_SL_PML5E_VALID_MASK
612/** @} */
613
614
615/** @name Second-Level PDPE (1GB Page).
616 * In accordance with the Intel spec.
617 * @{ */
618/** R: Read. */
619#define VTD_BF_SL_PDPE1G_R_SHIFT 0
620#define VTD_BF_SL_PDPE1G_R_MASK UINT64_C(0x0000000000000001)
621/** W: Write. */
622#define VTD_BF_SL_PDPE1G_W_SHIFT 1
623#define VTD_BF_SL_PDPE1G_W_MASK UINT64_C(0x0000000000000002)
624/** X: Execute. */
625#define VTD_BF_SL_PDPE1G_X_SHIFT 2
626#define VTD_BF_SL_PDPE1G_X_MASK UINT64_C(0x0000000000000004)
627/** EMT: Extended Memory Type. */
628#define VTD_BF_SL_PDPE1G_EMT_SHIFT 3
629#define VTD_BF_SL_PDPE1G_EMT_MASK UINT64_C(0x0000000000000038)
630/** IPAT: Ignore PAT (Page Attribute Table). */
631#define VTD_BF_SL_PDPE1G_IPAT_SHIFT 6
632#define VTD_BF_SL_PDPE1G_IPAT_MASK UINT64_C(0x0000000000000040)
633/** PS: Page Size (MB1). */
634#define VTD_BF_SL_PDPE1G_PS_SHIFT 7
635#define VTD_BF_SL_PDPE1G_PS_MASK UINT64_C(0x0000000000000080)
636/** A: Accessed. */
637#define VTD_BF_SL_PDPE1G_A_SHIFT 8
638#define VTD_BF_SL_PDPE1G_A_MASK UINT64_C(0x0000000000000100)
639/** D: Dirty. */
640#define VTD_BF_SL_PDPE1G_D_SHIFT 9
641#define VTD_BF_SL_PDPE1G_D_MASK UINT64_C(0x0000000000000200)
642/** IGN: Ignored (bit 10). */
643#define VTD_BF_SL_PDPE1G_IGN_10_SHIFT 10
644#define VTD_BF_SL_PDPE1G_IGN_10_MASK UINT64_C(0x0000000000000400)
645/** R: Reserved (bit 11). */
646#define VTD_BF_SL_PDPE1G_RSVD_11_SHIFT 11
647#define VTD_BF_SL_PDPE1G_RSVD_11_MASK UINT64_C(0x0000000000000800)
648/** R: Reserved (bits 29:12). */
649#define VTD_BF_SL_PDPE1G_RSVD_29_12_SHIFT 12
650#define VTD_BF_SL_PDPE1G_RSVD_29_12_MASK UINT64_C(0x000000003ffff000)
651/** ADDR: Address of 1GB page. */
652#define VTD_BF_SL_PDPE1G_ADDR_SHIFT 30
653#define VTD_BF_SL_PDPE1G_ADDR_MASK UINT64_C(0x000fffffc0000000)
654/** IGN: Ignored (bits 61:52). */
655#define VTD_BF_SL_PDPE1G_IGN_61_52_SHIFT 52
656#define VTD_BF_SL_PDPE1G_IGN_61_52_MASK UINT64_C(0x3ff0000000000000)
657/** R: Reserved (bit 62). */
658#define VTD_BF_SL_PDPE1G_RSVD_62_SHIFT 62
659#define VTD_BF_SL_PDPE1G_RSVD_62_MASK UINT64_C(0x4000000000000000)
660/** IGN: Ignored (bit 63). */
661#define VTD_BF_SL_PDPE1G_IGN_63_SHIFT 63
662#define VTD_BF_SL_PDPE1G_IGN_63_MASK UINT64_C(0x8000000000000000)
663RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_SL_PDPE1G_, UINT64_C(0), UINT64_MAX,
664 (R, W, X, EMT, IPAT, PS, A, D, IGN_10, RSVD_11, RSVD_29_12, ADDR, IGN_61_52, RSVD_62, IGN_63));
665
666/** Second-level PDPE (1GB Page) valid mask. */
667#define VTD_SL_PDPE1G_VALID_MASK ( VTD_BF_SL_PDPE1G_R_MASK | VTD_BF_SL_PDPE1G_W_MASK \
668 | VTD_BF_SL_PDPE1G_X_MASK | VTD_BF_SL_PDPE1G_EMT_MASK \
669 | VTD_BF_SL_PDPE1G_IPAT_MASK | VTD_BF_SL_PDPE1G_PS_MASK \
670 | VTD_BF_SL_PDPE1G_A_MASK | VTD_BF_SL_PDPE1G_D_MASK \
671 | VTD_BF_SL_PDPE1G_IGN_10_MASK | VTD_BF_SL_PDPE1G_ADDR_MASK \
672 | VTD_BF_SL_PDPE1G_IGN_61_52_MASK | VTD_BF_SL_PDPE1G_IGN_63_MASK)
673/** @} */
674
675
676/** @name Second-Level PDPE.
677 * In accordance with the Intel spec.
678 * @{ */
679/** R: Read. */
680#define VTD_BF_SL_PDPE_R_SHIFT 0
681#define VTD_BF_SL_PDPE_R_MASK UINT64_C(0x0000000000000001)
682/** W: Write. */
683#define VTD_BF_SL_PDPE_W_SHIFT 1
684#define VTD_BF_SL_PDPE_W_MASK UINT64_C(0x0000000000000002)
685/** X: Execute. */
686#define VTD_BF_SL_PDPE_X_SHIFT 2
687#define VTD_BF_SL_PDPE_X_MASK UINT64_C(0x0000000000000004)
688/** IGN: Ignored (bits 6:3). */
689#define VTD_BF_SL_PDPE_IGN_6_3_SHIFT 3
690#define VTD_BF_SL_PDPE_IGN_6_3_MASK UINT64_C(0x0000000000000078)
691/** PS: Page Size (MBZ). */
692#define VTD_BF_SL_PDPE_PS_SHIFT 7
693#define VTD_BF_SL_PDPE_PS_MASK UINT64_C(0x0000000000000080)
694/** A: Accessed. */
695#define VTD_BF_SL_PDPE_A_SHIFT 8
696#define VTD_BF_SL_PDPE_A_MASK UINT64_C(0x0000000000000100)
697/** IGN: Ignored (bits 10:9). */
698#define VTD_BF_SL_PDPE_IGN_10_9_SHIFT 9
699#define VTD_BF_SL_PDPE_IGN_10_9_MASK UINT64_C(0x0000000000000600)
700/** R: Reserved (bit 11). */
701#define VTD_BF_SL_PDPE_RSVD_11_SHIFT 11
702#define VTD_BF_SL_PDPE_RSVD_11_MASK UINT64_C(0x0000000000000800)
703/** ADDR: Address of second-level PDT. */
704#define VTD_BF_SL_PDPE_ADDR_SHIFT 12
705#define VTD_BF_SL_PDPE_ADDR_MASK UINT64_C(0x000ffffffffff000)
706/** IGN: Ignored (bits 61:52). */
707#define VTD_BF_SL_PDPE_IGN_61_52_SHIFT 52
708#define VTD_BF_SL_PDPE_IGN_61_52_MASK UINT64_C(0x3ff0000000000000)
709/** R: Reserved (bit 62). */
710#define VTD_BF_SL_PDPE_RSVD_62_SHIFT 62
711#define VTD_BF_SL_PDPE_RSVD_62_MASK UINT64_C(0x4000000000000000)
712/** IGN: Ignored (bit 63). */
713#define VTD_BF_SL_PDPE_IGN_63_SHIFT 63
714#define VTD_BF_SL_PDPE_IGN_63_MASK UINT64_C(0x8000000000000000)
715RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_SL_PDPE_, UINT64_C(0), UINT64_MAX,
716 (R, W, X, IGN_6_3, PS, A, IGN_10_9, RSVD_11, ADDR, IGN_61_52, RSVD_62, IGN_63));
717
718/** Second-level PDPE valid mask. */
719#define VTD_SL_PDPE_VALID_MASK ( VTD_BF_SL_PDPE_R_MASK | VTD_BF_SL_PDPE_W_MASK \
720 | VTD_BF_SL_PDPE_X_MASK | VTD_BF_SL_PDPE_IGN_6_3_MASK \
721 | VTD_BF_SL_PDPE_PS_MASK | VTD_BF_SL_PDPE_A_MASK \
722 | VTD_BF_SL_PDPE_IGN_10_9_MASK | VTD_BF_SL_PDPE_ADDR_MASK \
723 | VTD_BF_SL_PDPE_IGN_61_52_MASK | VTD_BF_SL_PDPE_IGN_63_MASK)
724/** @} */
725
726
727/** @name Second-Level PDE (2MB Page).
728 * In accordance with the Intel spec.
729 * @{ */
730/** R: Read. */
731#define VTD_BF_SL_PDE2M_R_SHIFT 0
732#define VTD_BF_SL_PDE2M_R_MASK UINT64_C(0x0000000000000001)
733/** W: Write. */
734#define VTD_BF_SL_PDE2M_W_SHIFT 1
735#define VTD_BF_SL_PDE2M_W_MASK UINT64_C(0x0000000000000002)
736/** X: Execute. */
737#define VTD_BF_SL_PDE2M_X_SHIFT 2
738#define VTD_BF_SL_PDE2M_X_MASK UINT64_C(0x0000000000000004)
739/** EMT: Extended Memory Type. */
740#define VTD_BF_SL_PDE2M_EMT_SHIFT 3
741#define VTD_BF_SL_PDE2M_EMT_MASK UINT64_C(0x0000000000000038)
742/** IPAT: Ignore PAT (Page Attribute Table). */
743#define VTD_BF_SL_PDE2M_IPAT_SHIFT 6
744#define VTD_BF_SL_PDE2M_IPAT_MASK UINT64_C(0x0000000000000040)
745/** PS: Page Size (MB1). */
746#define VTD_BF_SL_PDE2M_PS_SHIFT 7
747#define VTD_BF_SL_PDE2M_PS_MASK UINT64_C(0x0000000000000080)
748/** A: Accessed. */
749#define VTD_BF_SL_PDE2M_A_SHIFT 8
750#define VTD_BF_SL_PDE2M_A_MASK UINT64_C(0x0000000000000100)
751/** D: Dirty. */
752#define VTD_BF_SL_PDE2M_D_SHIFT 9
753#define VTD_BF_SL_PDE2M_D_MASK UINT64_C(0x0000000000000200)
754/** IGN: Ignored (bit 10). */
755#define VTD_BF_SL_PDE2M_IGN_10_SHIFT 10
756#define VTD_BF_SL_PDE2M_IGN_10_MASK UINT64_C(0x0000000000000400)
757/** R: Reserved (bit 11). */
758#define VTD_BF_SL_PDE2M_RSVD_11_SHIFT 11
759#define VTD_BF_SL_PDE2M_RSVD_11_MASK UINT64_C(0x0000000000000800)
760/** R: Reserved (bits 20:12). */
761#define VTD_BF_SL_PDE2M_RSVD_20_12_SHIFT 12
762#define VTD_BF_SL_PDE2M_RSVD_20_12_MASK UINT64_C(0x00000000001ff000)
763/** ADDR: Address of 2MB page. */
764#define VTD_BF_SL_PDE2M_ADDR_SHIFT 21
765#define VTD_BF_SL_PDE2M_ADDR_MASK UINT64_C(0x000fffffffe00000)
766/** IGN: Ignored (bits 61:52). */
767#define VTD_BF_SL_PDE2M_IGN_61_52_SHIFT 52
768#define VTD_BF_SL_PDE2M_IGN_61_52_MASK UINT64_C(0x3ff0000000000000)
769/** R: Reserved (bit 62). */
770#define VTD_BF_SL_PDE2M_RSVD_62_SHIFT 62
771#define VTD_BF_SL_PDE2M_RSVD_62_MASK UINT64_C(0x4000000000000000)
772/** IGN: Ignored (bit 63). */
773#define VTD_BF_SL_PDE2M_IGN_63_SHIFT 63
774#define VTD_BF_SL_PDE2M_IGN_63_MASK UINT64_C(0x8000000000000000)
775RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_SL_PDE2M_, UINT64_C(0), UINT64_MAX,
776 (R, W, X, EMT, IPAT, PS, A, D, IGN_10, RSVD_11, RSVD_20_12, ADDR, IGN_61_52, RSVD_62, IGN_63));
777
778/** Second-level PDE (2MB page) valid mask. */
779#define VTD_SL_PDE2M_VALID_MASK ( VTD_BF_SL_PDE2M_R_MASK | VTD_BF_SL_PDE2M_W_MASK \
780 | VTD_BF_SL_PDE2M_X_MASK | VTD_BF_SL_PDE2M_EMT_MASK \
781 | VTD_BF_SL_PDE2M_IPAT_MASK | VTD_BF_SL_PDE2M_PS_MASK \
782 | VTD_BF_SL_PDE2M_A_MASK | VTD_BF_SL_PDE2M_D_MASK \
783 | VTD_BF_SL_PDE2M_IGN_10_MASK | VTD_BF_SL_PDE2M_ADDR_MASK \
784 | VTD_BF_SL_PDE2M_IGN_61_52_MASK | VTD_BF_SL_PDE2M_IGN_63_MASK)
785/** @} */
786
787
788/** @name Second-Level PDE.
789 * In accordance with the Intel spec.
790 * @{ */
791/** R: Read. */
792#define VTD_BF_SL_PDE_R_SHIFT 0
793#define VTD_BF_SL_PDE_R_MASK UINT64_C(0x0000000000000001)
794/** W: Write. */
795#define VTD_BF_SL_PDE_W_SHIFT 1
796#define VTD_BF_SL_PDE_W_MASK UINT64_C(0x0000000000000002)
797/** X: Execute. */
798#define VTD_BF_SL_PDE_X_SHIFT 2
799#define VTD_BF_SL_PDE_X_MASK UINT64_C(0x0000000000000004)
800/** IGN: Ignored (bits 6:3). */
801#define VTD_BF_SL_PDE_IGN_6_3_SHIFT 3
802#define VTD_BF_SL_PDE_IGN_6_3_MASK UINT64_C(0x0000000000000078)
803/** PS: Page Size (MBZ). */
804#define VTD_BF_SL_PDE_PS_SHIFT 7
805#define VTD_BF_SL_PDE_PS_MASK UINT64_C(0x0000000000000080)
806/** A: Accessed. */
807#define VTD_BF_SL_PDE_A_SHIFT 8
808#define VTD_BF_SL_PDE_A_MASK UINT64_C(0x0000000000000100)
809/** IGN: Ignored (bits 10:9). */
810#define VTD_BF_SL_PDE_IGN_10_9_SHIFT 9
811#define VTD_BF_SL_PDE_IGN_10_9_MASK UINT64_C(0x0000000000000600)
812/** R: Reserved (bit 11). */
813#define VTD_BF_SL_PDE_RSVD_11_SHIFT 11
814#define VTD_BF_SL_PDE_RSVD_11_MASK UINT64_C(0x0000000000000800)
815/** ADDR: Address of second-level PT. */
816#define VTD_BF_SL_PDE_ADDR_SHIFT 12
817#define VTD_BF_SL_PDE_ADDR_MASK UINT64_C(0x000ffffffffff000)
818/** IGN: Ignored (bits 61:52). */
819#define VTD_BF_SL_PDE_IGN_61_52_SHIFT 52
820#define VTD_BF_SL_PDE_IGN_61_52_MASK UINT64_C(0x3ff0000000000000)
821/** R: Reserved (bit 62). */
822#define VTD_BF_SL_PDE_RSVD_62_SHIFT 62
823#define VTD_BF_SL_PDE_RSVD_62_MASK UINT64_C(0x4000000000000000)
824/** IGN: Ignored (bit 63). */
825#define VTD_BF_SL_PDE_IGN_63_SHIFT 63
826#define VTD_BF_SL_PDE_IGN_63_MASK UINT64_C(0x8000000000000000)
827RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_SL_PDE_, UINT64_C(0), UINT64_MAX,
828 (R, W, X, IGN_6_3, PS, A, IGN_10_9, RSVD_11, ADDR, IGN_61_52, RSVD_62, IGN_63));
829
830/** Second-level PDE valid mask. */
831#define VTD_SL_PDE_VALID_MASK ( VTD_BF_SL_PDE_R_MASK | VTD_BF_SL_PDE_W_MASK \
832 | VTD_BF_SL_PDE_X_MASK | VTD_BF_SL_PDE_IGN_6_3_MASK \
833 | VTD_BF_SL_PDE_PS_MASK | VTD_BF_SL_PDE_A_MASK \
834 | VTD_BF_SL_PDE_IGN_10_9_MASK | VTD_BF_SL_PDE_ADDR_MASK \
835 | VTD_BF_SL_PDE_IGN_61_52_MASK | VTD_BF_SL_PDE_IGN_63_MASK)
836/** @} */
837
838
839/** @name Second-Level PTE.
840 * In accordance with the Intel spec.
841 * @{ */
842/** R: Read. */
843#define VTD_BF_SL_PTE_R_SHIFT 0
844#define VTD_BF_SL_PTE_R_MASK UINT64_C(0x0000000000000001)
845/** W: Write. */
846#define VTD_BF_SL_PTE_W_SHIFT 1
847#define VTD_BF_SL_PTE_W_MASK UINT64_C(0x0000000000000002)
848/** X: Execute. */
849#define VTD_BF_SL_PTE_X_SHIFT 2
850#define VTD_BF_SL_PTE_X_MASK UINT64_C(0x0000000000000004)
851/** EMT: Extended Memory Type. */
852#define VTD_BF_SL_PTE_EMT_SHIFT 3
853#define VTD_BF_SL_PTE_EMT_MASK UINT64_C(0x0000000000000038)
854/** IPAT: Ignore PAT (Page Attribute Table). */
855#define VTD_BF_SL_PTE_IPAT_SHIFT 6
856#define VTD_BF_SL_PTE_IPAT_MASK UINT64_C(0x0000000000000040)
857/** IGN: Ignored (bit 7). */
858#define VTD_BF_SL_PTE_IGN_7_SHIFT 7
859#define VTD_BF_SL_PTE_IGN_7_MASK UINT64_C(0x0000000000000080)
860/** A: Accessed. */
861#define VTD_BF_SL_PTE_A_SHIFT 8
862#define VTD_BF_SL_PTE_A_MASK UINT64_C(0x0000000000000100)
863/** D: Dirty. */
864#define VTD_BF_SL_PTE_D_SHIFT 9
865#define VTD_BF_SL_PTE_D_MASK UINT64_C(0x0000000000000200)
866/** IGN: Ignored (bit 10). */
867#define VTD_BF_SL_PTE_IGN_10_SHIFT 10
868#define VTD_BF_SL_PTE_IGN_10_MASK UINT64_C(0x0000000000000400)
869/** R: Reserved (bit 11). */
870#define VTD_BF_SL_PTE_RSVD_11_SHIFT 11
871#define VTD_BF_SL_PTE_RSVD_11_MASK UINT64_C(0x0000000000000800)
872/** ADDR: Address of 4K page. */
873#define VTD_BF_SL_PTE_ADDR_SHIFT 12
874#define VTD_BF_SL_PTE_ADDR_MASK UINT64_C(0x000ffffffffff000)
875/** IGN: Ignored (bits 61:52). */
876#define VTD_BF_SL_PTE_IGN_61_52_SHIFT 52
877#define VTD_BF_SL_PTE_IGN_61_52_MASK UINT64_C(0x3ff0000000000000)
878/** R: Reserved (bit 62). */
879#define VTD_BF_SL_PTE_RSVD_62_SHIFT 62
880#define VTD_BF_SL_PTE_RSVD_62_MASK UINT64_C(0x4000000000000000)
881/** IGN: Ignored (bit 63). */
882#define VTD_BF_SL_PTE_IGN_63_SHIFT 63
883#define VTD_BF_SL_PTE_IGN_63_MASK UINT64_C(0x8000000000000000)
884RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_SL_PTE_, UINT64_C(0), UINT64_MAX,
885 (R, W, X, EMT, IPAT, IGN_7, A, D, IGN_10, RSVD_11, ADDR, IGN_61_52, RSVD_62, IGN_63));
886
887/** Second-level PTE valid mask. */
888#define VTD_SL_PTE_VALID_MASK ( VTD_BF_SL_PTE_R_MASK | VTD_BF_SL_PTE_W_MASK \
889 | VTD_BF_SL_PTE_X_MASK | VTD_BF_SL_PTE_EMT_MASK \
890 | VTD_BF_SL_PTE_IPAT_MASK | VTD_BF_SL_PTE_IGN_7_MASK \
891 | VTD_BF_SL_PTE_A_MASK | VTD_BF_SL_PTE_D_MASK \
892 | VTD_BF_SL_PTE_IGN_10_MASK | VTD_BF_SL_PTE_ADDR_MASK \
893 | VTD_BF_SL_PTE_IGN_61_52_MASK | VTD_BF_SL_PTE_IGN_63_MASK)
894/** @} */
895
896
897/** @name Fault Record.
898 * In accordance with the Intel spec.
899 * @{ */
900/** R: Reserved (bits 11:0). */
901#define VTD_BF_0_FAULT_RECORD_RSVD_11_0_SHIFT 0
902#define VTD_BF_0_FAULT_RECORD_RSVD_11_0_MASK UINT64_C(0x0000000000000fff)
903/** FI: Fault Information. */
904#define VTD_BF_0_FAULT_RECORD_FI_SHIFT 12
905#define VTD_BF_0_FAULT_RECORD_FI_MASK UINT64_C(0xfffffffffffff000)
906RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_FAULT_RECORD_, UINT64_C(0), UINT64_MAX,
907 (RSVD_11_0, FI));
908
909/** SID: Source identifier. */
910#define VTD_BF_1_FAULT_RECORD_SID_SHIFT 0
911#define VTD_BF_1_FAULT_RECORD_SID_MASK UINT64_C(0x000000000000ffff)
912/** R: Reserved (bits 28:16). */
913#define VTD_BF_1_FAULT_RECORD_RSVD_28_16_SHIFT 16
914#define VTD_BF_1_FAULT_RECORD_RSVD_28_16_MASK UINT64_C(0x000000001fff0000)
915/** PRIV: Privilege Mode Requested. */
916#define VTD_BF_1_FAULT_RECORD_PRIV_SHIFT 29
917#define VTD_BF_1_FAULT_RECORD_PRIV_MASK UINT64_C(0x0000000020000000)
918/** EXE: Execute Permission Requested. */
919#define VTD_BF_1_FAULT_RECORD_EXE_SHIFT 30
920#define VTD_BF_1_FAULT_RECORD_EXE_MASK UINT64_C(0x0000000040000000)
921/** PP: PASID Present. */
922#define VTD_BF_1_FAULT_RECORD_PP_SHIFT 31
923#define VTD_BF_1_FAULT_RECORD_PP_MASK UINT64_C(0x0000000080000000)
924/** FR: Fault Reason. */
925#define VTD_BF_1_FAULT_RECORD_FR_SHIFT 32
926#define VTD_BF_1_FAULT_RECORD_FR_MASK UINT64_C(0x000000ff00000000)
927/** PV: PASID Value. */
928#define VTD_BF_1_FAULT_RECORD_PV_SHIFT 40
929#define VTD_BF_1_FAULT_RECORD_PV_MASK UINT64_C(0x0fffff0000000000)
930/** AT: Address Type. */
931#define VTD_BF_1_FAULT_RECORD_AT_SHIFT 60
932#define VTD_BF_1_FAULT_RECORD_AT_MASK UINT64_C(0x3000000000000000)
933/** T: Type. */
934#define VTD_BF_1_FAULT_RECORD_T_SHIFT 62
935#define VTD_BF_1_FAULT_RECORD_T_MASK UINT64_C(0x4000000000000000)
936/** R: Reserved (bit 127). */
937#define VTD_BF_1_FAULT_RECORD_RSVD_63_SHIFT 63
938#define VTD_BF_1_FAULT_RECORD_RSVD_63_MASK UINT64_C(0x8000000000000000)
939RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_FAULT_RECORD_, UINT64_C(0), UINT64_MAX,
940 (SID, RSVD_28_16, PRIV, EXE, PP, FR, PV, AT, T, RSVD_63));
941
942/** Fault record. */
943typedef struct VTD_FAULT_RECORD_T
944{
945 /** The qwords in the fault record. */
946 uint64_t au64[2];
947} VTD_FAULT_RECORD_T;
948/** Pointer to a fault record. */
949typedef VTD_FAULT_RECORD_T *PVTD_FAULT_RECORD_T;
950/** Pointer to a const fault record. */
951typedef VTD_FAULT_RECORD_T const *PCVTD_FAULT_RECORD_T;
952/** @} */
953
954
955/** @name Interrupt Remapping Table Entry (IRTE) for Remapped Interrupts.
956 * In accordance with the Intel spec.
957 * @{ */
958/** P: Present. */
959#define VTD_BF_0_IRTE_P_SHIFT 0
960#define VTD_BF_0_IRTE_P_MASK UINT64_C(0x0000000000000001)
961/** FPD: Fault Processing Disable. */
962#define VTD_BF_0_IRTE_FPD_SHIFT 1
963#define VTD_BF_0_IRTE_FPD_MASK UINT64_C(0x0000000000000002)
964/** DM: Destination Mode (0=physical, 1=logical). */
965#define VTD_BF_0_IRTE_DM_SHIFT 2
966#define VTD_BF_0_IRTE_DM_MASK UINT64_C(0x0000000000000004)
967/** RH: Redirection Hint. */
968#define VTD_BF_0_IRTE_RH_SHIFT 3
969#define VTD_BF_0_IRTE_RH_MASK UINT64_C(0x0000000000000008)
970/** TM: Trigger Mode. */
971#define VTD_BF_0_IRTE_TM_SHIFT 4
972#define VTD_BF_0_IRTE_TM_MASK UINT64_C(0x0000000000000010)
973/** DLM: Delivery Mode. */
974#define VTD_BF_0_IRTE_DLM_SHIFT 5
975#define VTD_BF_0_IRTE_DLM_MASK UINT64_C(0x00000000000000e0)
976/** AVL: Available. */
977#define VTD_BF_0_IRTE_AVAIL_SHIFT 8
978#define VTD_BF_0_IRTE_AVAIL_MASK UINT64_C(0x0000000000000f00)
979/** R: Reserved (bits 14:12). */
980#define VTD_BF_0_IRTE_RSVD_14_12_SHIFT 12
981#define VTD_BF_0_IRTE_RSVD_14_12_MASK UINT64_C(0x0000000000007000)
982/** IM: IRTE Mode. */
983#define VTD_BF_0_IRTE_IM_SHIFT 15
984#define VTD_BF_0_IRTE_IM_MASK UINT64_C(0x0000000000008000)
985/** V: Vector. */
986#define VTD_BF_0_IRTE_V_SHIFT 16
987#define VTD_BF_0_IRTE_V_MASK UINT64_C(0x0000000000ff0000)
988/** R: Reserved (bits 31:24). */
989#define VTD_BF_0_IRTE_RSVD_31_24_SHIFT 24
990#define VTD_BF_0_IRTE_RSVD_31_24_MASK UINT64_C(0x00000000ff000000)
991/** DST: Desination Id. */
992#define VTD_BF_0_IRTE_DST_SHIFT 32
993#define VTD_BF_0_IRTE_DST_MASK UINT64_C(0xffffffff00000000)
994/** R: Reserved (bits 39:32) when EIME=0. */
995#define VTD_BF_0_IRTE_RSVD_39_32_SHIFT 32
996#define VTD_BF_0_IRTE_RSVD_39_32_MASK UINT64_C(0x000000ff00000000)
997/** DST_XAPIC: Destination Id when EIME=0. */
998#define VTD_BF_0_IRTE_DST_XAPIC_SHIFT 40
999#define VTD_BF_0_IRTE_DST_XAPIC_MASK UINT64_C(0x0000ff0000000000)
1000/** R: Reserved (bits 63:48) when EIME=0. */
1001#define VTD_BF_0_IRTE_RSVD_63_48_SHIFT 48
1002#define VTD_BF_0_IRTE_RSVD_63_48_MASK UINT64_C(0xffff000000000000)
1003RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_IRTE_, UINT64_C(0), UINT64_MAX,
1004 (P, FPD, DM, RH, TM, DLM, AVAIL, RSVD_14_12, IM, V, RSVD_31_24, DST));
1005RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_IRTE_, UINT64_C(0), UINT64_MAX,
1006 (P, FPD, DM, RH, TM, DLM, AVAIL, RSVD_14_12, IM, V, RSVD_31_24, RSVD_39_32, DST_XAPIC, RSVD_63_48));
1007
1008/** SID: Source Identifier. */
1009#define VTD_BF_1_IRTE_SID_SHIFT 0
1010#define VTD_BF_1_IRTE_SID_MASK UINT64_C(0x000000000000ffff)
1011/** SQ: Source-Id Qualifier. */
1012#define VTD_BF_1_IRTE_SQ_SHIFT 16
1013#define VTD_BF_1_IRTE_SQ_MASK UINT64_C(0x0000000000030000)
1014/** SVT: Source Validation Type. */
1015#define VTD_BF_1_IRTE_SVT_SHIFT 18
1016#define VTD_BF_1_IRTE_SVT_MASK UINT64_C(0x00000000000c0000)
1017/** R: Reserved (bits 127:84). */
1018#define VTD_BF_1_IRTE_RSVD_63_20_SHIFT 20
1019#define VTD_BF_1_IRTE_RSVD_63_20_MASK UINT64_C(0xfffffffffff00000)
1020RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_IRTE_, UINT64_C(0), UINT64_MAX,
1021 (SID, SQ, SVT, RSVD_63_20));
1022
1023/** IRTE: Qword 0 valid mask when EIME=1. */
1024#define VTD_IRTE_0_X2APIC_VALID_MASK ( VTD_BF_0_IRTE_P_MASK | VTD_BF_0_IRTE_FPD_MASK \
1025 | VTD_BF_0_IRTE_DM_MASK | VTD_BF_0_IRTE_RH_MASK \
1026 | VTD_BF_0_IRTE_TM_MASK | VTD_BF_0_IRTE_DLM_MASK \
1027 | VTD_BF_0_IRTE_AVAIL_MASK | VTD_BF_0_IRTE_IM_MASK \
1028 | VTD_BF_0_IRTE_V_MASK | VTD_BF_0_IRTE_DST_MASK)
1029/** IRTE: Qword 0 valid mask when EIME=0. */
1030#define VTD_IRTE_0_XAPIC_VALID_MASK ( VTD_BF_0_IRTE_P_MASK | VTD_BF_0_IRTE_FPD_MASK \
1031 | VTD_BF_0_IRTE_DM_MASK | VTD_BF_0_IRTE_RH_MASK \
1032 | VTD_BF_0_IRTE_TM_MASK | VTD_BF_0_IRTE_DLM_MASK \
1033 | VTD_BF_0_IRTE_AVAIL_MASK | VTD_BF_0_IRTE_IM_MASK \
1034 | VTD_BF_0_IRTE_V_MASK | VTD_BF_0_IRTE_DST_XAPIC_MASK)
1035/** IRTE: Qword 1 valid mask. */
1036#define VTD_IRTE_1_VALID_MASK ( VTD_BF_1_IRTE_SID_MASK | VTD_BF_1_IRTE_SQ_MASK \
1037 | VTD_BF_1_IRTE_SVT_MASK)
1038
1039/** Interrupt Remapping Table Entry (IRTE) for remapped interrupts. */
1040typedef struct VTD_IRTE_T
1041{
1042 /** The qwords in the IRTE. */
1043 uint64_t au64[2];
1044} VTD_IRTE_T;
1045/** Pointer to an IRTE. */
1046typedef VTD_IRTE_T *PVTD_IRTE_T;
1047/** Pointer to a const IRTE. */
1048typedef VTD_IRTE_T const *PCVTD_IRTE_T;
1049
1050/** IRTE SVT: No validation required. */
1051#define VTD_IRTE_SVT_NONE 0
1052/** IRTE SVT: Validate using a mask derived from SID and SQT. */
1053#define VTD_IRTE_SVT_VALIDATE_MASK 1
1054/** IRTE SVT: Validate using Bus range in the SID. */
1055#define VTD_IRTE_SVT_VALIDATE_BUS_RANGE 2
1056/** IRTE SVT: Reserved. */
1057#define VTD_IRTE_SVT_VALIDATE_RSVD 3
1058/** @} */
1059
1060
1061/** @name Version Register (VER_REG).
1062 * In accordance with the Intel spec.
1063 * @{ */
1064/** Min: Minor Version Number. */
1065#define VTD_BF_VER_REG_MIN_SHIFT 0
1066#define VTD_BF_VER_REG_MIN_MASK UINT32_C(0x0000000f)
1067/** Max: Major Version Number. */
1068#define VTD_BF_VER_REG_MAX_SHIFT 4
1069#define VTD_BF_VER_REG_MAX_MASK UINT32_C(0x000000f0)
1070/** R: Reserved (bits 31:8). */
1071#define VTD_BF_VER_REG_RSVD_31_8_SHIFT 8
1072#define VTD_BF_VER_REG_RSVD_31_8_MASK UINT32_C(0xffffff00)
1073RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_VER_REG_, UINT32_C(0), UINT32_MAX,
1074 (MIN, MAX, RSVD_31_8));
1075/** RW: Read/write mask. */
1076#define VTD_VER_REG_RW_MASK UINT32_C(0)
1077/** @} */
1078
1079
1080/** @name Capability Register (CAP_REG).
1081 * In accordance with the Intel spec.
1082 * @{ */
1083/** ND: Number of domains supported. */
1084#define VTD_BF_CAP_REG_ND_SHIFT 0
1085#define VTD_BF_CAP_REG_ND_MASK UINT64_C(0x0000000000000007)
1086/** AFL: Advanced Fault Logging. */
1087#define VTD_BF_CAP_REG_AFL_SHIFT 3
1088#define VTD_BF_CAP_REG_AFL_MASK UINT64_C(0x0000000000000008)
1089/** RWBF: Required Write-Buffer Flushing. */
1090#define VTD_BF_CAP_REG_RWBF_SHIFT 4
1091#define VTD_BF_CAP_REG_RWBF_MASK UINT64_C(0x0000000000000010)
1092/** PLMR: Protected Low-Memory Region. */
1093#define VTD_BF_CAP_REG_PLMR_SHIFT 5
1094#define VTD_BF_CAP_REG_PLMR_MASK UINT64_C(0x0000000000000020)
1095/** PHMR: Protected High-Memory Region. */
1096#define VTD_BF_CAP_REG_PHMR_SHIFT 6
1097#define VTD_BF_CAP_REG_PHMR_MASK UINT64_C(0x0000000000000040)
1098/** CM: Caching Mode. */
1099#define VTD_BF_CAP_REG_CM_SHIFT 7
1100#define VTD_BF_CAP_REG_CM_MASK UINT64_C(0x0000000000000080)
1101/** SAGAW: Supported Adjusted Guest Address Widths. */
1102#define VTD_BF_CAP_REG_SAGAW_SHIFT 8
1103#define VTD_BF_CAP_REG_SAGAW_MASK UINT64_C(0x0000000000001f00)
1104/** R: Reserved (bits 15:13). */
1105#define VTD_BF_CAP_REG_RSVD_15_13_SHIFT 13
1106#define VTD_BF_CAP_REG_RSVD_15_13_MASK UINT64_C(0x000000000000e000)
1107/** MGAW: Maximum Guest Address Width. */
1108#define VTD_BF_CAP_REG_MGAW_SHIFT 16
1109#define VTD_BF_CAP_REG_MGAW_MASK UINT64_C(0x00000000003f0000)
1110/** ZLR: Zero Length Read. */
1111#define VTD_BF_CAP_REG_ZLR_SHIFT 22
1112#define VTD_BF_CAP_REG_ZLR_MASK UINT64_C(0x0000000000400000)
1113/** DEP: Deprecated MBZ. Reserved (bit 23). */
1114#define VTD_BF_CAP_REG_RSVD_23_SHIFT 23
1115#define VTD_BF_CAP_REG_RSVD_23_MASK UINT64_C(0x0000000000800000)
1116/** FRO: Fault-recording Register Offset. */
1117#define VTD_BF_CAP_REG_FRO_SHIFT 24
1118#define VTD_BF_CAP_REG_FRO_MASK UINT64_C(0x00000003ff000000)
1119/** SLLPS: Second Level Large Page Support. */
1120#define VTD_BF_CAP_REG_SLLPS_SHIFT 34
1121#define VTD_BF_CAP_REG_SLLPS_MASK UINT64_C(0x0000003c00000000)
1122/** R: Reserved (bit 38). */
1123#define VTD_BF_CAP_REG_RSVD_38_SHIFT 38
1124#define VTD_BF_CAP_REG_RSVD_38_MASK UINT64_C(0x0000004000000000)
1125/** PSI: Page Selective Invalidation. */
1126#define VTD_BF_CAP_REG_PSI_SHIFT 39
1127#define VTD_BF_CAP_REG_PSI_MASK UINT64_C(0x0000008000000000)
1128/** NFR: Number of Fault-recording Registers. */
1129#define VTD_BF_CAP_REG_NFR_SHIFT 40
1130#define VTD_BF_CAP_REG_NFR_MASK UINT64_C(0x0000ff0000000000)
1131/** MAMV: Maximum Address Mask Value. */
1132#define VTD_BF_CAP_REG_MAMV_SHIFT 48
1133#define VTD_BF_CAP_REG_MAMV_MASK UINT64_C(0x003f000000000000)
1134/** DWD: Write Draining. */
1135#define VTD_BF_CAP_REG_DWD_SHIFT 54
1136#define VTD_BF_CAP_REG_DWD_MASK UINT64_C(0x0040000000000000)
1137/** DRD: Read Draining. */
1138#define VTD_BF_CAP_REG_DRD_SHIFT 55
1139#define VTD_BF_CAP_REG_DRD_MASK UINT64_C(0x0080000000000000)
1140/** FL1GP: First Level 1 GB Page Support. */
1141#define VTD_BF_CAP_REG_FL1GP_SHIFT 56
1142#define VTD_BF_CAP_REG_FL1GP_MASK UINT64_C(0x0100000000000000)
1143/** R: Reserved (bits 58:57). */
1144#define VTD_BF_CAP_REG_RSVD_58_57_SHIFT 57
1145#define VTD_BF_CAP_REG_RSVD_58_57_MASK UINT64_C(0x0600000000000000)
1146/** PI: Posted Interrupt Support. */
1147#define VTD_BF_CAP_REG_PI_SHIFT 59
1148#define VTD_BF_CAP_REG_PI_MASK UINT64_C(0x0800000000000000)
1149/** FL5LP: First Level 5-level Paging Support. */
1150#define VTD_BF_CAP_REG_FL5LP_SHIFT 60
1151#define VTD_BF_CAP_REG_FL5LP_MASK UINT64_C(0x1000000000000000)
1152/** R: Reserved (bit 61). */
1153#define VTD_BF_CAP_REG_RSVD_61_SHIFT 61
1154#define VTD_BF_CAP_REG_RSVD_61_MASK UINT64_C(0x2000000000000000)
1155/** ESIRTPS: Enhanced Set Interrupt Root Table Pointer Support. */
1156#define VTD_BF_CAP_REG_ESIRTPS_SHIFT 62
1157#define VTD_BF_CAP_REG_ESIRTPS_MASK UINT64_C(0x4000000000000000)
1158/** : Enhanced Set Root Table Pointer Support. */
1159#define VTD_BF_CAP_REG_ESRTPS_SHIFT 63
1160#define VTD_BF_CAP_REG_ESRTPS_MASK UINT64_C(0x8000000000000000)
1161RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_CAP_REG_, UINT64_C(0), UINT64_MAX,
1162 (ND, AFL, RWBF, PLMR, PHMR, CM, SAGAW, RSVD_15_13, MGAW, ZLR, RSVD_23, FRO, SLLPS, RSVD_38, PSI, NFR,
1163 MAMV, DWD, DRD, FL1GP, RSVD_58_57, PI, FL5LP, RSVD_61, ESIRTPS, ESRTPS));
1164
1165/** RW: Read/write mask. */
1166#define VTD_CAP_REG_RW_MASK UINT64_C(0)
1167/** @} */
1168
1169
1170/** @name Extended Capability Register (ECAP_REG).
1171 * In accordance with the Intel spec.
1172 * @{ */
1173/** C: Page-walk Coherence. */
1174#define VTD_BF_ECAP_REG_C_SHIFT 0
1175#define VTD_BF_ECAP_REG_C_MASK UINT64_C(0x0000000000000001)
1176/** QI: Queued Invalidation Support. */
1177#define VTD_BF_ECAP_REG_QI_SHIFT 1
1178#define VTD_BF_ECAP_REG_QI_MASK UINT64_C(0x0000000000000002)
1179/** DT: Device-TLB Support. */
1180#define VTD_BF_ECAP_REG_DT_SHIFT 2
1181#define VTD_BF_ECAP_REG_DT_MASK UINT64_C(0x0000000000000004)
1182/** IR: Interrupt Remapping Support. */
1183#define VTD_BF_ECAP_REG_IR_SHIFT 3
1184#define VTD_BF_ECAP_REG_IR_MASK UINT64_C(0x0000000000000008)
1185/** EIM: Extended Interrupt Mode. */
1186#define VTD_BF_ECAP_REG_EIM_SHIFT 4
1187#define VTD_BF_ECAP_REG_EIM_MASK UINT64_C(0x0000000000000010)
1188/** DEP: Deprecated MBZ. Reserved (bit 5). */
1189#define VTD_BF_ECAP_REG_RSVD_5_SHIFT 5
1190#define VTD_BF_ECAP_REG_RSVD_5_MASK UINT64_C(0x0000000000000020)
1191/** PT: Pass Through. */
1192#define VTD_BF_ECAP_REG_PT_SHIFT 6
1193#define VTD_BF_ECAP_REG_PT_MASK UINT64_C(0x0000000000000040)
1194/** SC: Snoop Control. */
1195#define VTD_BF_ECAP_REG_SC_SHIFT 7
1196#define VTD_BF_ECAP_REG_SC_MASK UINT64_C(0x0000000000000080)
1197/** IRO: IOTLB Register Offset. */
1198#define VTD_BF_ECAP_REG_IRO_SHIFT 8
1199#define VTD_BF_ECAP_REG_IRO_MASK UINT64_C(0x000000000003ff00)
1200/** R: Reserved (bits 19:18). */
1201#define VTD_BF_ECAP_REG_RSVD_19_18_SHIFT 18
1202#define VTD_BF_ECAP_REG_RSVD_19_18_MASK UINT64_C(0x00000000000c0000)
1203/** MHMV: Maximum Handle Mask Value. */
1204#define VTD_BF_ECAP_REG_MHMV_SHIFT 20
1205#define VTD_BF_ECAP_REG_MHMV_MASK UINT64_C(0x0000000000f00000)
1206/** DEP: Deprecated MBZ. Reserved (bit 24). */
1207#define VTD_BF_ECAP_REG_RSVD_24_SHIFT 24
1208#define VTD_BF_ECAP_REG_RSVD_24_MASK UINT64_C(0x0000000001000000)
1209/** MTS: Memory Type Support. */
1210#define VTD_BF_ECAP_REG_MTS_SHIFT 25
1211#define VTD_BF_ECAP_REG_MTS_MASK UINT64_C(0x0000000002000000)
1212/** NEST: Nested Translation Support. */
1213#define VTD_BF_ECAP_REG_NEST_SHIFT 26
1214#define VTD_BF_ECAP_REG_NEST_MASK UINT64_C(0x0000000004000000)
1215/** R: Reserved (bit 27). */
1216#define VTD_BF_ECAP_REG_RSVD_27_SHIFT 27
1217#define VTD_BF_ECAP_REG_RSVD_27_MASK UINT64_C(0x0000000008000000)
1218/** DEP: Deprecated MBZ. Reserved (bit 28). */
1219#define VTD_BF_ECAP_REG_RSVD_28_SHIFT 28
1220#define VTD_BF_ECAP_REG_RSVD_28_MASK UINT64_C(0x0000000010000000)
1221/** PRS: Page Request Support. */
1222#define VTD_BF_ECAP_REG_PRS_SHIFT 29
1223#define VTD_BF_ECAP_REG_PRS_MASK UINT64_C(0x0000000020000000)
1224/** ERS: Execute Request Support. */
1225#define VTD_BF_ECAP_REG_ERS_SHIFT 30
1226#define VTD_BF_ECAP_REG_ERS_MASK UINT64_C(0x0000000040000000)
1227/** SRS: Supervisor Request Support. */
1228#define VTD_BF_ECAP_REG_SRS_SHIFT 31
1229#define VTD_BF_ECAP_REG_SRS_MASK UINT64_C(0x0000000080000000)
1230/** R: Reserved (bit 32). */
1231#define VTD_BF_ECAP_REG_RSVD_32_SHIFT 32
1232#define VTD_BF_ECAP_REG_RSVD_32_MASK UINT64_C(0x0000000100000000)
1233/** NWFS: No Write Flag Support. */
1234#define VTD_BF_ECAP_REG_NWFS_SHIFT 33
1235#define VTD_BF_ECAP_REG_NWFS_MASK UINT64_C(0x0000000200000000)
1236/** EAFS: Extended Accessed Flags Support. */
1237#define VTD_BF_ECAP_REG_EAFS_SHIFT 34
1238#define VTD_BF_ECAP_REG_EAFS_MASK UINT64_C(0x0000000400000000)
1239/** PSS: PASID Size Supported. */
1240#define VTD_BF_ECAP_REG_PSS_SHIFT 35
1241#define VTD_BF_ECAP_REG_PSS_MASK UINT64_C(0x000000f800000000)
1242/** PASID: Process Address Space ID Support. */
1243#define VTD_BF_ECAP_REG_PASID_SHIFT 40
1244#define VTD_BF_ECAP_REG_PASID_MASK UINT64_C(0x0000010000000000)
1245/** DIT: Device-TLB Invalidation Throttle. */
1246#define VTD_BF_ECAP_REG_DIT_SHIFT 41
1247#define VTD_BF_ECAP_REG_DIT_MASK UINT64_C(0x0000020000000000)
1248/** PDS: Page-request Drain Support. */
1249#define VTD_BF_ECAP_REG_PDS_SHIFT 42
1250#define VTD_BF_ECAP_REG_PDS_MASK UINT64_C(0x0000040000000000)
1251/** SMTS: Scalable-Mode Translation Support. */
1252#define VTD_BF_ECAP_REG_SMTS_SHIFT 43
1253#define VTD_BF_ECAP_REG_SMTS_MASK UINT64_C(0x0000080000000000)
1254/** VCS: Virtual Command Support. */
1255#define VTD_BF_ECAP_REG_VCS_SHIFT 44
1256#define VTD_BF_ECAP_REG_VCS_MASK UINT64_C(0x0000100000000000)
1257/** SLADS: Second-Level Accessed/Dirty Support. */
1258#define VTD_BF_ECAP_REG_SLADS_SHIFT 45
1259#define VTD_BF_ECAP_REG_SLADS_MASK UINT64_C(0x0000200000000000)
1260/** SLTS: Second-Level Translation Support. */
1261#define VTD_BF_ECAP_REG_SLTS_SHIFT 46
1262#define VTD_BF_ECAP_REG_SLTS_MASK UINT64_C(0x0000400000000000)
1263/** FLTS: First-Level Translation Support. */
1264#define VTD_BF_ECAP_REG_FLTS_SHIFT 47
1265#define VTD_BF_ECAP_REG_FLTS_MASK UINT64_C(0x0000800000000000)
1266/** SMPWCS: Scalable-Mode Page-Walk Coherency Support. */
1267#define VTD_BF_ECAP_REG_SMPWCS_SHIFT 48
1268#define VTD_BF_ECAP_REG_SMPWCS_MASK UINT64_C(0x0001000000000000)
1269/** RPS: RID-PASID Support. */
1270#define VTD_BF_ECAP_REG_RPS_SHIFT 49
1271#define VTD_BF_ECAP_REG_RPS_MASK UINT64_C(0x0002000000000000)
1272/** R: Reserved (bits 51:50). */
1273#define VTD_BF_ECAP_REG_RSVD_51_50_SHIFT 50
1274#define VTD_BF_ECAP_REG_RSVD_51_50_MASK UINT64_C(0x000c000000000000)
1275/** ADMS: Abort DMA Mode Support. */
1276#define VTD_BF_ECAP_REG_ADMS_SHIFT 52
1277#define VTD_BF_ECAP_REG_ADMS_MASK UINT64_C(0x0010000000000000)
1278/** RPRIVS: RID_PRIV Support. */
1279#define VTD_BF_ECAP_REG_RPRIVS_SHIFT 53
1280#define VTD_BF_ECAP_REG_RPRIVS_MASK UINT64_C(0x0020000000000000)
1281/** R: Reserved (bits 63:54). */
1282#define VTD_BF_ECAP_REG_RSVD_63_54_SHIFT 54
1283#define VTD_BF_ECAP_REG_RSVD_63_54_MASK UINT64_C(0xffc0000000000000)
1284RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_ECAP_REG_, UINT64_C(0), UINT64_MAX,
1285 (C, QI, DT, IR, EIM, RSVD_5, PT, SC, IRO, RSVD_19_18, MHMV, RSVD_24, MTS, NEST, RSVD_27, RSVD_28,
1286 PRS, ERS, SRS, RSVD_32, NWFS, EAFS, PSS, PASID, DIT, PDS, SMTS, VCS, SLADS, SLTS, FLTS, SMPWCS, RPS,
1287 RSVD_51_50, ADMS, RPRIVS, RSVD_63_54));
1288
1289/** RW: Read/write mask. */
1290#define VTD_ECAP_REG_RW_MASK UINT64_C(0)
1291/** @} */
1292
1293
1294/** @name Global Command Register (GCMD_REG).
1295 * In accordance with the Intel spec.
1296 * @{ */
1297/** R: Reserved (bits 22:0). */
1298#define VTD_BF_GCMD_REG_RSVD_22_0_SHIFT 0
1299#define VTD_BF_GCMD_REG_RSVD_22_0_MASK UINT32_C(0x007fffff)
1300/** CFI: Compatibility Format Interrupt. */
1301#define VTD_BF_GCMD_REG_CFI_SHIFT 23
1302#define VTD_BF_GCMD_REG_CFI_MASK UINT32_C(0x00800000)
1303/** SIRTP: Set Interrupt Table Remap Pointer. */
1304#define VTD_BF_GCMD_REG_SIRTP_SHIFT 24
1305#define VTD_BF_GCMD_REG_SIRTP_MASK UINT32_C(0x01000000)
1306/** IRE: Interrupt Remap Enable. */
1307#define VTD_BF_GCMD_REG_IRE_SHIFT 25
1308#define VTD_BF_GCMD_REG_IRE_MASK UINT32_C(0x02000000)
1309/** QIE: Queued Invalidation Enable. */
1310#define VTD_BF_GCMD_REG_QIE_SHIFT 26
1311#define VTD_BF_GCMD_REG_QIE_MASK UINT32_C(0x04000000)
1312/** WBF: Write Buffer Flush. */
1313#define VTD_BF_GCMD_REG_WBF_SHIFT 27
1314#define VTD_BF_GCMD_REG_WBF_MASK UINT32_C(0x08000000)
1315/** EAFL: Enable Advance Fault Logging. */
1316#define VTD_BF_GCMD_REG_EAFL_SHIFT 28
1317#define VTD_BF_GCMD_REG_EAFL_MASK UINT32_C(0x10000000)
1318/** SFL: Set Fault Log. */
1319#define VTD_BF_GCMD_REG_SFL_SHIFT 29
1320#define VTD_BF_GCMD_REG_SFL_MASK UINT32_C(0x20000000)
1321/** SRTP: Set Root Table Pointer. */
1322#define VTD_BF_GCMD_REG_SRTP_SHIFT 30
1323#define VTD_BF_GCMD_REG_SRTP_MASK UINT32_C(0x40000000)
1324/** TE: Translation Enable. */
1325#define VTD_BF_GCMD_REG_TE_SHIFT 31
1326#define VTD_BF_GCMD_REG_TE_MASK UINT32_C(0x80000000)
1327RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_GCMD_REG_, UINT32_C(0), UINT32_MAX,
1328 (RSVD_22_0, CFI, SIRTP, IRE, QIE, WBF, EAFL, SFL, SRTP, TE));
1329
1330/** RW: Read/write mask. */
1331#define VTD_GCMD_REG_RW_MASK ( VTD_BF_GCMD_REG_TE_MASK | VTD_BF_GCMD_REG_SRTP_MASK \
1332 | VTD_BF_GCMD_REG_SFL_MASK | VTD_BF_GCMD_REG_EAFL_MASK \
1333 | VTD_BF_GCMD_REG_WBF_MASK | VTD_BF_GCMD_REG_QIE_MASK \
1334 | VTD_BF_GCMD_REG_IRE_MASK | VTD_BF_GCMD_REG_SIRTP_MASK \
1335 | VTD_BF_GCMD_REG_CFI_MASK)
1336/** @} */
1337
1338
1339/** @name Global Status Register (GSTS_REG).
1340 * In accordance with the Intel spec.
1341 * @{ */
1342/** R: Reserved (bits 22:0). */
1343#define VTD_BF_GSTS_REG_RSVD_22_0_SHIFT 0
1344#define VTD_BF_GSTS_REG_RSVD_22_0_MASK UINT32_C(0x007fffff)
1345/** CFIS: Compatibility Format Interrupt Status. */
1346#define VTD_BF_GSTS_REG_CFIS_SHIFT 23
1347#define VTD_BF_GSTS_REG_CFIS_MASK UINT32_C(0x00800000)
1348/** IRTPS: Interrupt Remapping Table Pointer Status. */
1349#define VTD_BF_GSTS_REG_IRTPS_SHIFT 24
1350#define VTD_BF_GSTS_REG_IRTPS_MASK UINT32_C(0x01000000)
1351/** IRES: Interrupt Remapping Enable Status. */
1352#define VTD_BF_GSTS_REG_IRES_SHIFT 25
1353#define VTD_BF_GSTS_REG_IRES_MASK UINT32_C(0x02000000)
1354/** QIES: Queued Invalidation Enable Status. */
1355#define VTD_BF_GSTS_REG_QIES_SHIFT 26
1356#define VTD_BF_GSTS_REG_QIES_MASK UINT32_C(0x04000000)
1357/** WBFS: Write Buffer Flush Status. */
1358#define VTD_BF_GSTS_REG_WBFS_SHIFT 27
1359#define VTD_BF_GSTS_REG_WBFS_MASK UINT32_C(0x08000000)
1360/** AFLS: Advanced Fault Logging Status. */
1361#define VTD_BF_GSTS_REG_AFLS_SHIFT 28
1362#define VTD_BF_GSTS_REG_AFLS_MASK UINT32_C(0x10000000)
1363/** FLS: Fault Log Status. */
1364#define VTD_BF_GSTS_REG_FLS_SHIFT 29
1365#define VTD_BF_GSTS_REG_FLS_MASK UINT32_C(0x20000000)
1366/** RTPS: Root Table Pointer Status. */
1367#define VTD_BF_GSTS_REG_RTPS_SHIFT 30
1368#define VTD_BF_GSTS_REG_RTPS_MASK UINT32_C(0x40000000)
1369/** TES: Translation Enable Status. */
1370#define VTD_BF_GSTS_REG_TES_SHIFT 31
1371#define VTD_BF_GSTS_REG_TES_MASK UINT32_C(0x80000000)
1372RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_GSTS_REG_, UINT32_C(0), UINT32_MAX,
1373 (RSVD_22_0, CFIS, IRTPS, IRES, QIES, WBFS, AFLS, FLS, RTPS, TES));
1374
1375/** RW: Read/write mask. */
1376#define VTD_GSTS_REG_RW_MASK UINT32_C(0)
1377/** @} */
1378
1379
1380/** @name Root Table Address Register (RTADDR_REG).
1381 * In accordance with the Intel spec.
1382 * @{ */
1383/** R: Reserved (bits 9:0). */
1384#define VTD_BF_RTADDR_REG_RSVD_9_0_SHIFT 0
1385#define VTD_BF_RTADDR_REG_RSVD_9_0_MASK UINT64_C(0x00000000000003ff)
1386/** TTM: Translation Table Mode. */
1387#define VTD_BF_RTADDR_REG_TTM_SHIFT 10
1388#define VTD_BF_RTADDR_REG_TTM_MASK UINT64_C(0x0000000000000c00)
1389/** RTA: Root Table Address. */
1390#define VTD_BF_RTADDR_REG_RTA_SHIFT 12
1391#define VTD_BF_RTADDR_REG_RTA_MASK UINT64_C(0xfffffffffffff000)
1392RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_RTADDR_REG_, UINT64_C(0), UINT64_MAX,
1393 (RSVD_9_0, TTM, RTA));
1394
1395/** RW: Read/write mask. */
1396#define VTD_RTADDR_REG_RW_MASK UINT64_C(0xfffffffffffffc00)
1397
1398/** RTADDR_REG.TTM: Legacy mode. */
1399#define VTD_TTM_LEGACY_MODE 0
1400/** RTADDR_REG.TTM: Scalable mode. */
1401#define VTD_TTM_SCALABLE_MODE 1
1402/** RTADDR_REG.TTM: Reserved. */
1403#define VTD_TTM_RSVD 2
1404/** RTADDR_REG.TTM: Abort DMA mode. */
1405#define VTD_TTM_ABORT_DMA_MODE 3
1406/** @} */
1407
1408
1409/** @name Context Command Register (CCMD_REG).
1410 * In accordance with the Intel spec.
1411 * @{ */
1412/** DID: Domain-ID. */
1413#define VTD_BF_CCMD_REG_DID_SHIFT 0
1414#define VTD_BF_CCMD_REG_DID_MASK UINT64_C(0x000000000000ffff)
1415/** SID: Source-ID. */
1416#define VTD_BF_CCMD_REG_SID_SHIFT 16
1417#define VTD_BF_CCMD_REG_SID_MASK UINT64_C(0x00000000ffff0000)
1418/** FM: Function Mask. */
1419#define VTD_BF_CCMD_REG_FM_SHIFT 32
1420#define VTD_BF_CCMD_REG_FM_MASK UINT64_C(0x0000000300000000)
1421/** R: Reserved (bits 58:34). */
1422#define VTD_BF_CCMD_REG_RSVD_58_34_SHIFT 34
1423#define VTD_BF_CCMD_REG_RSVD_58_34_MASK UINT64_C(0x07fffffc00000000)
1424/** CAIG: Context Actual Invalidation Granularity. */
1425#define VTD_BF_CCMD_REG_CAIG_SHIFT 59
1426#define VTD_BF_CCMD_REG_CAIG_MASK UINT64_C(0x1800000000000000)
1427/** CIRG: Context Invalidation Request Granularity. */
1428#define VTD_BF_CCMD_REG_CIRG_SHIFT 61
1429#define VTD_BF_CCMD_REG_CIRG_MASK UINT64_C(0x6000000000000000)
1430/** ICC: Invalidation Context Cache. */
1431#define VTD_BF_CCMD_REG_ICC_SHIFT 63
1432#define VTD_BF_CCMD_REG_ICC_MASK UINT64_C(0x8000000000000000)
1433RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_CCMD_REG_, UINT64_C(0), UINT64_MAX,
1434 (DID, SID, FM, RSVD_58_34, CAIG, CIRG, ICC));
1435
1436/** RW: Read/write mask. */
1437#define VTD_CCMD_REG_RW_MASK ( VTD_BF_CCMD_REG_DID_MASK | VTD_BF_CCMD_REG_SID_MASK \
1438 | VTD_BF_CCMD_REG_FM_MASK | VTD_BF_CCMD_REG_CIRG_MASK \
1439 | VTD_BF_CCMD_REG_ICC_MASK)
1440/** @} */
1441
1442
1443/** @name IOTLB Invalidation Register (IOTLB_REG).
1444 * In accordance with the Intel spec.
1445 * @{ */
1446/** R: Reserved (bits 31:0). */
1447#define VTD_BF_IOTLB_REG_RSVD_31_0_SHIFT 0
1448#define VTD_BF_IOTLB_REG_RSVD_31_0_MASK UINT64_C(0x00000000ffffffff)
1449/** DID: Domain-ID. */
1450#define VTD_BF_IOTLB_REG_DID_SHIFT 32
1451#define VTD_BF_IOTLB_REG_DID_MASK UINT64_C(0x0000ffff00000000)
1452/** DW: Draining Writes. */
1453#define VTD_BF_IOTLB_REG_DW_SHIFT 48
1454#define VTD_BF_IOTLB_REG_DW_MASK UINT64_C(0x0001000000000000)
1455/** DR: Draining Reads. */
1456#define VTD_BF_IOTLB_REG_DR_SHIFT 49
1457#define VTD_BF_IOTLB_REG_DR_MASK UINT64_C(0x0002000000000000)
1458/** R: Reserved (bits 56:50). */
1459#define VTD_BF_IOTLB_REG_RSVD_56_50_SHIFT 50
1460#define VTD_BF_IOTLB_REG_RSVD_56_50_MASK UINT64_C(0x01fc000000000000)
1461/** IAIG: IOTLB Actual Invalidation Granularity. */
1462#define VTD_BF_IOTLB_REG_IAIG_SHIFT 57
1463#define VTD_BF_IOTLB_REG_IAIG_MASK UINT64_C(0x0600000000000000)
1464/** R: Reserved (bit 59). */
1465#define VTD_BF_IOTLB_REG_RSVD_59_SHIFT 59
1466#define VTD_BF_IOTLB_REG_RSVD_59_MASK UINT64_C(0x0800000000000000)
1467/** IIRG: IOTLB Invalidation Request Granularity. */
1468#define VTD_BF_IOTLB_REG_IIRG_SHIFT 60
1469#define VTD_BF_IOTLB_REG_IIRG_MASK UINT64_C(0x3000000000000000)
1470/** R: Reserved (bit 62). */
1471#define VTD_BF_IOTLB_REG_RSVD_62_SHIFT 62
1472#define VTD_BF_IOTLB_REG_RSVD_62_MASK UINT64_C(0x4000000000000000)
1473/** IVT: Invalidate IOTLB. */
1474#define VTD_BF_IOTLB_REG_IVT_SHIFT 63
1475#define VTD_BF_IOTLB_REG_IVT_MASK UINT64_C(0x8000000000000000)
1476RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IOTLB_REG_, UINT64_C(0), UINT64_MAX,
1477 (RSVD_31_0, DID, DW, DR, RSVD_56_50, IAIG, RSVD_59, IIRG, RSVD_62, IVT));
1478
1479/** RW: Read/write mask. */
1480#define VTD_IOTLB_REG_RW_MASK ( VTD_BF_IOTLB_REG_DID_MASK | VTD_BF_IOTLB_REG_DW_MASK \
1481 | VTD_BF_IOTLB_REG_DR_MASK | VTD_BF_IOTLB_REG_IIRG_MASK \
1482 | VTD_BF_IOTLB_REG_IVT_MASK)
1483/** @} */
1484
1485
1486/** @name Invalidate Address Register (IVA_REG).
1487 * In accordance with the Intel spec.
1488 * @{ */
1489/** AM: Address Mask. */
1490#define VTD_BF_IVA_REG_AM_SHIFT 0
1491#define VTD_BF_IVA_REG_AM_MASK UINT64_C(0x000000000000003f)
1492/** IH: Invalidation Hint. */
1493#define VTD_BF_IVA_REG_IH_SHIFT 6
1494#define VTD_BF_IVA_REG_IH_MASK UINT64_C(0x0000000000000040)
1495/** R: Reserved (bits 11:7). */
1496#define VTD_BF_IVA_REG_RSVD_11_7_SHIFT 7
1497#define VTD_BF_IVA_REG_RSVD_11_7_MASK UINT64_C(0x0000000000000f80)
1498/** ADDR: Address. */
1499#define VTD_BF_IVA_REG_ADDR_SHIFT 12
1500#define VTD_BF_IVA_REG_ADDR_MASK UINT64_C(0xfffffffffffff000)
1501RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IVA_REG_, UINT64_C(0), UINT64_MAX,
1502 (AM, IH, RSVD_11_7, ADDR));
1503
1504/** RW: Read/write mask. */
1505#define VTD_IVA_REG_RW_MASK ( VTD_BF_IVA_REG_AM_MASK | VTD_BF_IVA_REG_IH_MASK \
1506 | VTD_BF_IVA_REG_ADDR_MASK)
1507/** @} */
1508
1509
1510/** @name Fault Status Register (FSTS_REG).
1511 * In accordance with the Intel spec.
1512 * @{ */
1513/** PFO: Primary Fault Overflow. */
1514#define VTD_BF_FSTS_REG_PFO_SHIFT 0
1515#define VTD_BF_FSTS_REG_PFO_MASK UINT32_C(0x00000001)
1516/** PPF: Primary Pending Fault. */
1517#define VTD_BF_FSTS_REG_PPF_SHIFT 1
1518#define VTD_BF_FSTS_REG_PPF_MASK UINT32_C(0x00000002)
1519/** AFO: Advanced Fault Overflow. */
1520#define VTD_BF_FSTS_REG_AFO_SHIFT 2
1521#define VTD_BF_FSTS_REG_AFO_MASK UINT32_C(0x00000004)
1522/** APF: Advanced Pending Fault. */
1523#define VTD_BF_FSTS_REG_APF_SHIFT 3
1524#define VTD_BF_FSTS_REG_APF_MASK UINT32_C(0x00000008)
1525/** IQE: Invalidation Queue Error. */
1526#define VTD_BF_FSTS_REG_IQE_SHIFT 4
1527#define VTD_BF_FSTS_REG_IQE_MASK UINT32_C(0x00000010)
1528/** ICE: Invalidation Completion Error. */
1529#define VTD_BF_FSTS_REG_ICE_SHIFT 5
1530#define VTD_BF_FSTS_REG_ICE_MASK UINT32_C(0x00000020)
1531/** ITE: Invalidation Timeout Error. */
1532#define VTD_BF_FSTS_REG_ITE_SHIFT 6
1533#define VTD_BF_FSTS_REG_ITE_MASK UINT32_C(0x00000040)
1534/** DEP: Deprecated MBZ. Reserved (bit 7). */
1535#define VTD_BF_FSTS_REG_RSVD_7_SHIFT 7
1536#define VTD_BF_FSTS_REG_RSVD_7_MASK UINT32_C(0x00000080)
1537/** FRI: Fault Record Index. */
1538#define VTD_BF_FSTS_REG_FRI_SHIFT 8
1539#define VTD_BF_FSTS_REG_FRI_MASK UINT32_C(0x0000ff00)
1540/** R: Reserved (bits 31:16). */
1541#define VTD_BF_FSTS_REG_RSVD_31_16_SHIFT 16
1542#define VTD_BF_FSTS_REG_RSVD_31_16_MASK UINT32_C(0xffff0000)
1543RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_FSTS_REG_, UINT32_C(0), UINT32_MAX,
1544 (PFO, PPF, AFO, APF, IQE, ICE, ITE, RSVD_7, FRI, RSVD_31_16));
1545
1546/** RW: Read/write mask. */
1547#define VTD_FSTS_REG_RW_MASK ( VTD_BF_FSTS_REG_PFO_MASK | VTD_BF_FSTS_REG_AFO_MASK \
1548 | VTD_BF_FSTS_REG_APF_MASK | VTD_BF_FSTS_REG_IQE_MASK \
1549 | VTD_BF_FSTS_REG_ICE_MASK | VTD_BF_FSTS_REG_ITE_MASK)
1550/** RW1C: Read-only-status, Write-1-to-clear status mask. */
1551#define VTD_FSTS_REG_RW1C_MASK ( VTD_BF_FSTS_REG_PFO_MASK | VTD_BF_FSTS_REG_AFO_MASK \
1552 | VTD_BF_FSTS_REG_APF_MASK | VTD_BF_FSTS_REG_IQE_MASK \
1553 | VTD_BF_FSTS_REG_ICE_MASK | VTD_BF_FSTS_REG_ITE_MASK)
1554/** @} */
1555
1556
1557/** @name Fault Event Control Register (FECTL_REG).
1558 * In accordance with the Intel spec.
1559 * @{ */
1560/** R: Reserved (bits 29:0). */
1561#define VTD_BF_FECTL_REG_RSVD_29_0_SHIFT 0
1562#define VTD_BF_FECTL_REG_RSVD_29_0_MASK UINT32_C(0x3fffffff)
1563/** IP: Interrupt Pending. */
1564#define VTD_BF_FECTL_REG_IP_SHIFT 30
1565#define VTD_BF_FECTL_REG_IP_MASK UINT32_C(0x40000000)
1566/** IM: Interrupt Mask. */
1567#define VTD_BF_FECTL_REG_IM_SHIFT 31
1568#define VTD_BF_FECTL_REG_IM_MASK UINT32_C(0x80000000)
1569RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_FECTL_REG_, UINT32_C(0), UINT32_MAX,
1570 (RSVD_29_0, IP, IM));
1571
1572/** RW: Read/write mask. */
1573#define VTD_FECTL_REG_RW_MASK VTD_BF_FECTL_REG_IM_MASK
1574/** @} */
1575
1576
1577/** @name Fault Event Data Register (FEDATA_REG).
1578 * In accordance with the Intel spec.
1579 * @{ */
1580/** IMD: Interrupt Message Data. */
1581#define VTD_BF_FEDATA_REG_IMD_SHIFT 0
1582#define VTD_BF_FEDATA_REG_IMD_MASK UINT32_C(0x0000ffff)
1583/** R: Reserved (bits 31:16). VT-d specs. prior to 2021 had EIMD here. */
1584#define VTD_BF_FEDATA_REG_RSVD_31_16_SHIFT 16
1585#define VTD_BF_FEDATA_REG_RSVD_31_16_MASK UINT32_C(0xffff0000)
1586RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_FEDATA_REG_, UINT32_C(0), UINT32_MAX,
1587 (IMD, RSVD_31_16));
1588
1589/** RW: Read/write mask, see 5.1.6 "Remapping Hardware Event Interrupt
1590 * Programming". */
1591#define VTD_FEDATA_REG_RW_MASK UINT32_C(0x000001ff)
1592/** @} */
1593
1594
1595/** @name Fault Event Address Register (FEADDR_REG).
1596 * In accordance with the Intel spec.
1597 * @{ */
1598/** R: Reserved (bits 1:0). */
1599#define VTD_BF_FEADDR_REG_RSVD_1_0_SHIFT 0
1600#define VTD_BF_FEADDR_REG_RSVD_1_0_MASK UINT32_C(0x00000003)
1601/** MA: Message Address. */
1602#define VTD_BF_FEADDR_REG_MA_SHIFT 2
1603#define VTD_BF_FEADDR_REG_MA_MASK UINT32_C(0xfffffffc)
1604RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_FEADDR_REG_, UINT32_C(0), UINT32_MAX,
1605 (RSVD_1_0, MA));
1606
1607/** RW: Read/write mask. */
1608#define VTD_FEADDR_REG_RW_MASK VTD_BF_FEADDR_REG_MA_MASK
1609/** @} */
1610
1611
1612/** @name Fault Event Upper Address Register (FEUADDR_REG).
1613 * In accordance with the Intel spec.
1614 * @{ */
1615/** MUA: Message Upper Address. */
1616#define VTD_BF_FEUADDR_REG_MA_SHIFT 0
1617#define VTD_BF_FEUADDR_REG_MA_MASK UINT32_C(0xffffffff)
1618
1619/** RW: Read/write mask. */
1620#define VTD_FEUADDR_REG_RW_MASK VTD_BF_FEUADDR_REG_MA_MASK
1621/** @} */
1622
1623
1624/** @name Fault Recording Register (FRCD_REG).
1625 * In accordance with the Intel spec.
1626 * @{ */
1627/** R: Reserved (bits 11:0). */
1628#define VTD_BF_0_FRCD_REG_RSVD_11_0_SHIFT 0
1629#define VTD_BF_0_FRCD_REG_RSVD_11_0_MASK UINT64_C(0x0000000000000fff)
1630/** FI: Fault Info. */
1631#define VTD_BF_0_FRCD_REG_FI_SHIFT 12
1632#define VTD_BF_0_FRCD_REG_FI_MASK UINT64_C(0xfffffffffffff000)
1633RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_FRCD_REG_, UINT64_C(0), UINT64_MAX,
1634 (RSVD_11_0, FI));
1635
1636/** SID: Source Identifier. */
1637#define VTD_BF_1_FRCD_REG_SID_SHIFT 0
1638#define VTD_BF_1_FRCD_REG_SID_MASK UINT64_C(0x000000000000ffff)
1639/** R: Reserved (bits 27:16). */
1640#define VTD_BF_1_FRCD_REG_RSVD_27_16_SHIFT 16
1641#define VTD_BF_1_FRCD_REG_RSVD_27_16_MASK UINT64_C(0x000000000fff0000)
1642/** T2: Type bit 2. */
1643#define VTD_BF_1_FRCD_REG_T2_SHIFT 28
1644#define VTD_BF_1_FRCD_REG_T2_MASK UINT64_C(0x0000000010000000)
1645/** PRIV: Privilege Mode. */
1646#define VTD_BF_1_FRCD_REG_PRIV_SHIFT 29
1647#define VTD_BF_1_FRCD_REG_PRIV_MASK UINT64_C(0x0000000020000000)
1648/** EXE: Execute Permission Requested. */
1649#define VTD_BF_1_FRCD_REG_EXE_SHIFT 30
1650#define VTD_BF_1_FRCD_REG_EXE_MASK UINT64_C(0x0000000040000000)
1651/** PP: PASID Present. */
1652#define VTD_BF_1_FRCD_REG_PP_SHIFT 31
1653#define VTD_BF_1_FRCD_REG_PP_MASK UINT64_C(0x0000000080000000)
1654/** FR: Fault Reason. */
1655#define VTD_BF_1_FRCD_REG_FR_SHIFT 32
1656#define VTD_BF_1_FRCD_REG_FR_MASK UINT64_C(0x000000ff00000000)
1657/** PV: PASID Value. */
1658#define VTD_BF_1_FRCD_REG_PV_SHIFT 40
1659#define VTD_BF_1_FRCD_REG_PV_MASK UINT64_C(0x0fffff0000000000)
1660/** AT: Address Type. */
1661#define VTD_BF_1_FRCD_REG_AT_SHIFT 60
1662#define VTD_BF_1_FRCD_REG_AT_MASK UINT64_C(0x3000000000000000)
1663/** T1: Type bit 1. */
1664#define VTD_BF_1_FRCD_REG_T1_SHIFT 62
1665#define VTD_BF_1_FRCD_REG_T1_MASK UINT64_C(0x4000000000000000)
1666/** F: Fault. */
1667#define VTD_BF_1_FRCD_REG_F_SHIFT 63
1668#define VTD_BF_1_FRCD_REG_F_MASK UINT64_C(0x8000000000000000)
1669RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_FRCD_REG_, UINT64_C(0), UINT64_MAX,
1670 (SID, RSVD_27_16, T2, PRIV, EXE, PP, FR, PV, AT, T1, F));
1671
1672/** RW: Read/write mask. */
1673#define VTD_FRCD_REG_LO_RW_MASK UINT64_C(0)
1674#define VTD_FRCD_REG_HI_RW_MASK VTD_BF_1_FRCD_REG_F_MASK
1675/** RW1C: Read-only-status, Write-1-to-clear status mask. */
1676#define VTD_FRCD_REG_LO_RW1C_MASK UINT64_C(0)
1677#define VTD_FRCD_REG_HI_RW1C_MASK VTD_BF_1_FRCD_REG_F_MASK
1678/** @} */
1679
1680
1681/**
1682 * VT-d faulted address translation request types (FRCD_REG::T2).
1683 * In accordance with the Intel spec.
1684 */
1685typedef enum VTDREQTYPE
1686{
1687 VTDREQTYPE_WRITE = 0, /**< Memory access write request. */
1688 VTDREQTYPE_PAGE, /**< Page translation request. */
1689 VTDREQTYPE_READ, /**< Memory access read request. */
1690 VTDREQTYPE_ATOMIC_OP /**< Memory access atomic operation. */
1691} VTDREQTYPE;
1692/** Pointer to a VTDREQTYPE. */
1693typedef VTDREQTYPE *PVTDREQTYPE;
1694
1695
1696/** @name Advanced Fault Log Register (AFLOG_REG).
1697 * In accordance with the Intel spec.
1698 * @{ */
1699/** R: Reserved (bits 8:0). */
1700#define VTD_BF_0_AFLOG_REG_RSVD_8_0_SHIFT 0
1701#define VTD_BF_0_AFLOG_REG_RSVD_8_0_MASK UINT64_C(0x00000000000001ff)
1702/** FLS: Fault Log Size. */
1703#define VTD_BF_0_AFLOG_REG_FLS_SHIFT 9
1704#define VTD_BF_0_AFLOG_REG_FLS_MASK UINT64_C(0x0000000000000e00)
1705/** FLA: Fault Log Address. */
1706#define VTD_BF_0_AFLOG_REG_FLA_SHIFT 12
1707#define VTD_BF_0_AFLOG_REG_FLA_MASK UINT64_C(0xfffffffffffff000)
1708RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_AFLOG_REG_, UINT64_C(0), UINT64_MAX,
1709 (RSVD_8_0, FLS, FLA));
1710
1711/** RW: Read/write mask. */
1712#define VTD_AFLOG_REG_RW_MASK (VTD_BF_0_AFLOG_REG_FLS_MASK | VTD_BF_0_AFLOG_REG_FLA_MASK)
1713/** @} */
1714
1715
1716/** @name Protected Memory Enable Register (PMEN_REG).
1717 * In accordance with the Intel spec.
1718 * @{ */
1719/** PRS: Protected Region Status. */
1720#define VTD_BF_PMEN_REG_PRS_SHIFT 0
1721#define VTD_BF_PMEN_REG_PRS_MASK UINT32_C(0x00000001)
1722/** R: Reserved (bits 30:1). */
1723#define VTD_BF_PMEN_REG_RSVD_30_1_SHIFT 1
1724#define VTD_BF_PMEN_REG_RSVD_30_1_MASK UINT32_C(0x7ffffffe)
1725/** EPM: Enable Protected Memory. */
1726#define VTD_BF_PMEN_REG_EPM_SHIFT 31
1727#define VTD_BF_PMEN_REG_EPM_MASK UINT32_C(0x80000000)
1728RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_PMEN_REG_, UINT32_C(0), UINT32_MAX,
1729 (PRS, RSVD_30_1, EPM));
1730
1731/** RW: Read/write mask. */
1732#define VTD_PMEN_REG_RW_MASK VTD_BF_PMEN_REG_EPM_MASK
1733/** @} */
1734
1735
1736/** @name Invalidation Queue Head Register (IQH_REG).
1737 * In accordance with the Intel spec.
1738 * @{ */
1739/** R: Reserved (bits 3:0). */
1740#define VTD_BF_IQH_REG_RSVD_3_0_SHIFT 0
1741#define VTD_BF_IQH_REG_RSVD_3_0_MASK UINT64_C(0x000000000000000f)
1742/** QH: Queue Head. */
1743#define VTD_BF_IQH_REG_QH_SHIFT 4
1744#define VTD_BF_IQH_REG_QH_MASK UINT64_C(0x000000000007fff0)
1745/** R: Reserved (bits 63:19). */
1746#define VTD_BF_IQH_REG_RSVD_63_19_SHIFT 19
1747#define VTD_BF_IQH_REG_RSVD_63_19_MASK UINT64_C(0xfffffffffff80000)
1748RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IQH_REG_, UINT64_C(0), UINT64_MAX,
1749 (RSVD_3_0, QH, RSVD_63_19));
1750
1751/** RW: Read/write mask. */
1752#define VTD_IQH_REG_RW_MASK UINT64_C(0x0)
1753/** @} */
1754
1755
1756/** @name Invalidation Queue Tail Register (IQT_REG).
1757 * In accordance with the Intel spec.
1758 * @{ */
1759/** R: Reserved (bits 3:0). */
1760#define VTD_BF_IQT_REG_RSVD_3_0_SHIFT 0
1761#define VTD_BF_IQT_REG_RSVD_3_0_MASK UINT64_C(0x000000000000000f)
1762/** QH: Queue Tail. */
1763#define VTD_BF_IQT_REG_QT_SHIFT 4
1764#define VTD_BF_IQT_REG_QT_MASK UINT64_C(0x000000000007fff0)
1765/** R: Reserved (bits 63:19). */
1766#define VTD_BF_IQT_REG_RSVD_63_19_SHIFT 19
1767#define VTD_BF_IQT_REG_RSVD_63_19_MASK UINT64_C(0xfffffffffff80000)
1768RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IQT_REG_, UINT64_C(0), UINT64_MAX,
1769 (RSVD_3_0, QT, RSVD_63_19));
1770
1771/** RW: Read/write mask. */
1772#define VTD_IQT_REG_RW_MASK VTD_BF_IQT_REG_QT_MASK
1773/** @} */
1774
1775
1776/** @name Invalidation Queue Address Register (IQA_REG).
1777 * In accordance with the Intel spec.
1778 * @{ */
1779/** QS: Queue Size. */
1780#define VTD_BF_IQA_REG_QS_SHIFT 0
1781#define VTD_BF_IQA_REG_QS_MASK UINT64_C(0x0000000000000007)
1782/** R: Reserved (bits 10:3). */
1783#define VTD_BF_IQA_REG_RSVD_10_3_SHIFT 3
1784#define VTD_BF_IQA_REG_RSVD_10_3_MASK UINT64_C(0x00000000000007f8)
1785/** DW: Descriptor Width. */
1786#define VTD_BF_IQA_REG_DW_SHIFT 11
1787#define VTD_BF_IQA_REG_DW_MASK UINT64_C(0x0000000000000800)
1788/** IQA: Invalidation Queue Base Address. */
1789#define VTD_BF_IQA_REG_IQA_SHIFT 12
1790#define VTD_BF_IQA_REG_IQA_MASK UINT64_C(0xfffffffffffff000)
1791RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IQA_REG_, UINT64_C(0), UINT64_MAX,
1792 (QS, RSVD_10_3, DW, IQA));
1793
1794/** RW: Read/write mask. */
1795#define VTD_IQA_REG_RW_MASK ( VTD_BF_IQA_REG_QS_MASK | VTD_BF_IQA_REG_DW_MASK \
1796 | VTD_BF_IQA_REG_IQA_MASK)
1797/** DW: 128-bit descriptor. */
1798#define VTD_IQA_REG_DW_128_BIT 0
1799/** DW: 256-bit descriptor. */
1800#define VTD_IQA_REG_DW_256_BIT 1
1801/** @} */
1802
1803
1804/** @name Invalidation Completion Status Register (ICS_REG).
1805 * In accordance with the Intel spec.
1806 * @{ */
1807/** IWC: Invalidation Wait Descriptor Complete. */
1808#define VTD_BF_ICS_REG_IWC_SHIFT 0
1809#define VTD_BF_ICS_REG_IWC_MASK UINT32_C(0x00000001)
1810/** R: Reserved (bits 31:1). */
1811#define VTD_BF_ICS_REG_RSVD_31_1_SHIFT 1
1812#define VTD_BF_ICS_REG_RSVD_31_1_MASK UINT32_C(0xfffffffe)
1813RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_ICS_REG_, UINT32_C(0), UINT32_MAX,
1814 (IWC, RSVD_31_1));
1815
1816/** RW: Read/write mask. */
1817#define VTD_ICS_REG_RW_MASK VTD_BF_ICS_REG_IWC_MASK
1818/** RW1C: Read-only-status, Write-1-to-clear status mask. */
1819#define VTD_ICS_REG_RW1C_MASK VTD_BF_ICS_REG_IWC_MASK
1820/** @} */
1821
1822
1823/** @name Invalidation Event Control Register (IECTL_REG).
1824 * In accordance with the Intel spec.
1825 * @{ */
1826/** R: Reserved (bits 29:0). */
1827#define VTD_BF_IECTL_REG_RSVD_29_0_SHIFT 0
1828#define VTD_BF_IECTL_REG_RSVD_29_0_MASK UINT32_C(0x3fffffff)
1829/** IP: Interrupt Pending. */
1830#define VTD_BF_IECTL_REG_IP_SHIFT 30
1831#define VTD_BF_IECTL_REG_IP_MASK UINT32_C(0x40000000)
1832/** IM: Interrupt Mask. */
1833#define VTD_BF_IECTL_REG_IM_SHIFT 31
1834#define VTD_BF_IECTL_REG_IM_MASK UINT32_C(0x80000000)
1835RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IECTL_REG_, UINT32_C(0), UINT32_MAX,
1836 (RSVD_29_0, IP, IM));
1837
1838/** RW: Read/write mask. */
1839#define VTD_IECTL_REG_RW_MASK VTD_BF_IECTL_REG_IM_MASK
1840/** @} */
1841
1842
1843/** @name Invalidation Event Data Register (IEDATA_REG).
1844 * In accordance with the Intel spec.
1845 * @{ */
1846/** IMD: Interrupt Message Data. */
1847#define VTD_BF_IEDATA_REG_IMD_SHIFT 0
1848#define VTD_BF_IEDATA_REG_IMD_MASK UINT32_C(0x0000ffff)
1849/** R: Reserved (bits 31:16). VT-d specs. prior to 2021 had EIMD here. */
1850#define VTD_BF_IEDATA_REG_RSVD_31_16_SHIFT 16
1851#define VTD_BF_IEDATA_REG_RSVD_31_16_MASK UINT32_C(0xffff0000)
1852RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IEDATA_REG_, UINT32_C(0), UINT32_MAX,
1853 (IMD, RSVD_31_16));
1854
1855/** RW: Read/write mask, see 5.1.6 "Remapping Hardware Event Interrupt
1856 * Programming". */
1857#define VTD_IEDATA_REG_RW_MASK UINT32_C(0x000001ff)
1858/** @} */
1859
1860
1861/** @name Invalidation Event Address Register (IEADDR_REG).
1862 * In accordance with the Intel spec.
1863 * @{ */
1864/** R: Reserved (bits 1:0). */
1865#define VTD_BF_IEADDR_REG_RSVD_1_0_SHIFT 0
1866#define VTD_BF_IEADDR_REG_RSVD_1_0_MASK UINT32_C(0x00000003)
1867/** MA: Message Address. */
1868#define VTD_BF_IEADDR_REG_MA_SHIFT 2
1869#define VTD_BF_IEADDR_REG_MA_MASK UINT32_C(0xfffffffc)
1870RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IEADDR_REG_, UINT32_C(0), UINT32_MAX,
1871 (RSVD_1_0, MA));
1872
1873/** RW: Read/write mask. */
1874#define VTD_IEADDR_REG_RW_MASK VTD_BF_IEADDR_REG_MA_MASK
1875/** @} */
1876
1877
1878/** @name Invalidation Event Upper Address Register (IEUADDR_REG).
1879 * @{ */
1880/** MUA: Message Upper Address. */
1881#define VTD_BF_IEUADDR_REG_MUA_SHIFT 0
1882#define VTD_BF_IEUADDR_REG_MUA_MASK UINT32_C(0xffffffff)
1883
1884/** RW: Read/write mask. */
1885#define VTD_IEUADDR_REG_RW_MASK VTD_BF_IEUADDR_REG_MUA_MASK
1886/** @} */
1887
1888
1889/** @name Invalidation Queue Error Record Register (IQERCD_REG).
1890 * In accordance with the Intel spec.
1891 * @{ */
1892/** IQEI: Invalidation Queue Error Info. */
1893#define VTD_BF_IQERCD_REG_IQEI_SHIFT 0
1894#define VTD_BF_IQERCD_REG_IQEI_MASK UINT64_C(0x000000000000000f)
1895/** R: Reserved (bits 31:4). */
1896#define VTD_BF_IQERCD_REG_RSVD_31_4_SHIFT 4
1897#define VTD_BF_IQERCD_REG_RSVD_31_4_MASK UINT64_C(0x00000000fffffff0)
1898/** ITESID: Invalidation Timeout Error Source Identifier. */
1899#define VTD_BF_IQERCD_REG_ITESID_SHIFT 32
1900#define VTD_BF_IQERCD_REG_ITESID_MASK UINT64_C(0x0000ffff00000000)
1901/** ICESID: Invalidation Completion Error Source Identifier. */
1902#define VTD_BF_IQERCD_REG_ICESID_SHIFT 48
1903#define VTD_BF_IQERCD_REG_ICESID_MASK UINT64_C(0xffff000000000000)
1904RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IQERCD_REG_, UINT64_C(0), UINT64_MAX,
1905 (IQEI, RSVD_31_4, ITESID, ICESID));
1906
1907/** RW: Read/write mask. */
1908#define VTD_IQERCD_REG_RW_MASK UINT64_C(0)
1909
1910/** Invalidation Queue Error Information. */
1911typedef enum VTDIQEI
1912{
1913 VTDIQEI_INFO_NOT_AVAILABLE,
1914 VTDIQEI_INVALID_TAIL_PTR,
1915 VTDIQEI_FETCH_DESCRIPTOR_ERR,
1916 VTDIQEI_INVALID_DESCRIPTOR_TYPE,
1917 VTDIQEI_RSVD_FIELD_VIOLATION,
1918 VTDIQEI_INVALID_DESCRIPTOR_WIDTH,
1919 VTDIQEI_QUEUE_TAIL_MISALIGNED,
1920 VTDIQEI_INVALID_TTM
1921} VTDIQEI;
1922/** @} */
1923
1924
1925/** @name Interrupt Remapping Table Address Register (IRTA_REG).
1926 * In accordance with the Intel spec.
1927 * @{ */
1928/** S: Size. */
1929#define VTD_BF_IRTA_REG_S_SHIFT 0
1930#define VTD_BF_IRTA_REG_S_MASK UINT64_C(0x000000000000000f)
1931/** R: Reserved (bits 10:4). */
1932#define VTD_BF_IRTA_REG_RSVD_10_4_SHIFT 4
1933#define VTD_BF_IRTA_REG_RSVD_10_4_MASK UINT64_C(0x00000000000007f0)
1934/** EIME: Extended Interrupt Mode Enable. */
1935#define VTD_BF_IRTA_REG_EIME_SHIFT 11
1936#define VTD_BF_IRTA_REG_EIME_MASK UINT64_C(0x0000000000000800)
1937/** IRTA: Interrupt Remapping Table Address. */
1938#define VTD_BF_IRTA_REG_IRTA_SHIFT 12
1939#define VTD_BF_IRTA_REG_IRTA_MASK UINT64_C(0xfffffffffffff000)
1940RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IRTA_REG_, UINT64_C(0), UINT64_MAX,
1941 (S, RSVD_10_4, EIME, IRTA));
1942
1943/** RW: Read/write mask. */
1944#define VTD_IRTA_REG_RW_MASK ( VTD_BF_IRTA_REG_S_MASK | VTD_BF_IRTA_REG_EIME_MASK \
1945 | VTD_BF_IRTA_REG_IRTA_MASK)
1946/** IRTA_REG: Get number of interrupt entries. */
1947#define VTD_IRTA_REG_GET_ENTRY_COUNT(a) (UINT32_C(1) << (1 + ((a) & VTD_BF_IRTA_REG_S_MASK)))
1948/** @} */
1949
1950
1951/** @name Page Request Queue Head Register (PQH_REG).
1952 * In accordance with the Intel spec.
1953 * @{ */
1954/** R: Reserved (bits 4:0). */
1955#define VTD_BF_PQH_REG_RSVD_4_0_SHIFT 0
1956#define VTD_BF_PQH_REG_RSVD_4_0_MASK UINT64_C(0x000000000000001f)
1957/** PQH: Page Queue Head. */
1958#define VTD_BF_PQH_REG_PQH_SHIFT 5
1959#define VTD_BF_PQH_REG_PQH_MASK UINT64_C(0x000000000007ffe0)
1960/** R: Reserved (bits 63:19). */
1961#define VTD_BF_PQH_REG_RSVD_63_19_SHIFT 19
1962#define VTD_BF_PQH_REG_RSVD_63_19_MASK UINT64_C(0xfffffffffff80000)
1963RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_PQH_REG_, UINT64_C(0), UINT64_MAX,
1964 (RSVD_4_0, PQH, RSVD_63_19));
1965
1966/** RW: Read/write mask. */
1967#define VTD_PQH_REG_RW_MASK VTD_BF_PQH_REG_PQH_MASK
1968/** @} */
1969
1970
1971/** @name Page Request Queue Tail Register (PQT_REG).
1972 * In accordance with the Intel spec.
1973 * @{ */
1974/** R: Reserved (bits 4:0). */
1975#define VTD_BF_PQT_REG_RSVD_4_0_SHIFT 0
1976#define VTD_BF_PQT_REG_RSVD_4_0_MASK UINT64_C(0x000000000000001f)
1977/** PQT: Page Queue Tail. */
1978#define VTD_BF_PQT_REG_PQT_SHIFT 5
1979#define VTD_BF_PQT_REG_PQT_MASK UINT64_C(0x000000000007ffe0)
1980/** R: Reserved (bits 63:19). */
1981#define VTD_BF_PQT_REG_RSVD_63_19_SHIFT 19
1982#define VTD_BF_PQT_REG_RSVD_63_19_MASK UINT64_C(0xfffffffffff80000)
1983RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_PQT_REG_, UINT64_C(0), UINT64_MAX,
1984 (RSVD_4_0, PQT, RSVD_63_19));
1985
1986/** RW: Read/write mask. */
1987#define VTD_PQT_REG_RW_MASK VTD_BF_PQT_REG_PQT_MASK
1988/** @} */
1989
1990
1991/** @name Page Request Queue Address Register (PQA_REG).
1992 * In accordance with the Intel spec.
1993 * @{ */
1994/** PQS: Page Queue Size. */
1995#define VTD_BF_PQA_REG_PQS_SHIFT 0
1996#define VTD_BF_PQA_REG_PQS_MASK UINT64_C(0x0000000000000007)
1997/** R: Reserved bits (11:3). */
1998#define VTD_BF_PQA_REG_RSVD_11_3_SHIFT 3
1999#define VTD_BF_PQA_REG_RSVD_11_3_MASK UINT64_C(0x0000000000000ff8)
2000/** PQA: Page Request Queue Base Address. */
2001#define VTD_BF_PQA_REG_PQA_SHIFT 12
2002#define VTD_BF_PQA_REG_PQA_MASK UINT64_C(0xfffffffffffff000)
2003RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_PQA_REG_, UINT64_C(0), UINT64_MAX,
2004 (PQS, RSVD_11_3, PQA));
2005
2006/** RW: Read/write mask. */
2007#define VTD_PQA_REG_RW_MASK (VTD_BF_PQA_REG_PQS_MASK | VTD_BF_PQA_REG_PQA_MASK)
2008/** @} */
2009
2010
2011/** @name Page Request Status Register (PRS_REG).
2012 * In accordance with the Intel spec.
2013 * @{ */
2014/** PPR: Pending Page Request. */
2015#define VTD_BF_PRS_REG_PPR_SHIFT 0
2016#define VTD_BF_PRS_REG_PPR_MASK UINT64_C(0x00000001)
2017/** PRO: Page Request Overflow. */
2018#define VTD_BF_PRS_REG_PRO_SHIFT 1
2019#define VTD_BF_PRS_REG_PRO_MASK UINT64_C(0x00000002)
2020/** R: Reserved (bits 31:2). */
2021#define VTD_BF_PRS_REG_RSVD_31_2_SHIFT 2
2022#define VTD_BF_PRS_REG_RSVD_31_2_MASK UINT64_C(0xfffffffc)
2023RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_PRS_REG_, UINT32_C(0), UINT32_MAX,
2024 (PPR, PRO, RSVD_31_2));
2025
2026/** RW: Read/write mask. */
2027#define VTD_PRS_REG_RW_MASK (VTD_BF_PRS_REG_PPR_MASK | VTD_BF_PRS_REG_PRO_MASK)
2028/** RW1C: Read-only-status, Write-1-to-clear status mask. */
2029#define VTD_PRS_REG_RW1C_MASK (VTD_BF_PRS_REG_PPR_MASK | VTD_BF_PRS_REG_PRO_MASK)
2030/** @} */
2031
2032
2033/** @name Page Request Event Control Register (PECTL_REG).
2034 * In accordance with the Intel spec.
2035 * @{ */
2036/** R: Reserved (bits 29:0). */
2037#define VTD_BF_PECTL_REG_RSVD_29_0_SHIFT 0
2038#define VTD_BF_PECTL_REG_RSVD_29_0_MASK UINT32_C(0x3fffffff)
2039/** IP: Interrupt Pending. */
2040#define VTD_BF_PECTL_REG_IP_SHIFT 30
2041#define VTD_BF_PECTL_REG_IP_MASK UINT32_C(0x40000000)
2042/** IM: Interrupt Mask. */
2043#define VTD_BF_PECTL_REG_IM_SHIFT 31
2044#define VTD_BF_PECTL_REG_IM_MASK UINT32_C(0x80000000)
2045RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_PECTL_REG_, UINT32_C(0), UINT32_MAX,
2046 (RSVD_29_0, IP, IM));
2047
2048/** RW: Read/write mask. */
2049#define VTD_PECTL_REG_RW_MASK VTD_BF_PECTL_REG_IM_MASK
2050/** @} */
2051
2052
2053/** @name Page Request Event Data Register (PEDATA_REG).
2054 * In accordance with the Intel spec.
2055 * @{ */
2056/** IMD: Interrupt Message Data. */
2057#define VTD_BF_PEDATA_REG_IMD_SHIFT 0
2058#define VTD_BF_PEDATA_REG_IMD_MASK UINT32_C(0x0000ffff)
2059/** R: Reserved (bits 31:16). VT-d specs. prior to 2021 had EIMD here. */
2060#define VTD_BF_PEDATA_REG_RSVD_31_16_SHIFT 16
2061#define VTD_BF_PEDATA_REG_RSVD_31_16_MASK UINT32_C(0xffff0000)
2062RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_PEDATA_REG_, UINT32_C(0), UINT32_MAX,
2063 (IMD, RSVD_31_16));
2064
2065/** RW: Read/write mask, see 5.1.6 "Remapping Hardware Event Interrupt
2066 * Programming". */
2067#define VTD_PEDATA_REG_RW_MASK UINT32_C(0x000001ff)
2068/** @} */
2069
2070
2071/** @name Page Request Event Address Register (PEADDR_REG).
2072 * In accordance with the Intel spec.
2073 * @{ */
2074/** R: Reserved (bits 1:0). */
2075#define VTD_BF_PEADDR_REG_RSVD_1_0_SHIFT 0
2076#define VTD_BF_PEADDR_REG_RSVD_1_0_MASK UINT32_C(0x00000003)
2077/** MA: Message Address. */
2078#define VTD_BF_PEADDR_REG_MA_SHIFT 2
2079#define VTD_BF_PEADDR_REG_MA_MASK UINT32_C(0xfffffffc)
2080RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_PEADDR_REG_, UINT32_C(0), UINT32_MAX,
2081 (RSVD_1_0, MA));
2082
2083/** RW: Read/write mask. */
2084#define VTD_PEADDR_REG_RW_MASK VTD_BF_PEADDR_REG_MA_MASK
2085/** @} */
2086
2087
2088
2089/** @name Page Request Event Upper Address Register (PEUADDR_REG).
2090 * In accordance with the Intel spec.
2091 * @{ */
2092/** MA: Message Address. */
2093#define VTD_BF_PEUADDR_REG_MUA_SHIFT 0
2094#define VTD_BF_PEUADDR_REG_MUA_MASK UINT32_C(0xffffffff)
2095
2096/** RW: Read/write mask. */
2097#define VTD_PEUADDR_REG_RW_MASK VTD_BF_PEUADDR_REG_MUA_MASK
2098/** @} */
2099
2100
2101/** @name MTRR Capability Register (MTRRCAP_REG).
2102 * In accordance with the Intel spec.
2103 * @{ */
2104/** VCNT: Variable MTRR Count. */
2105#define VTD_BF_MTRRCAP_REG_VCNT_SHIFT 0
2106#define VTD_BF_MTRRCAP_REG_VCNT_MASK UINT64_C(0x00000000000000ff)
2107/** FIX: Fixed range MTRRs Supported. */
2108#define VTD_BF_MTRRCAP_REG_FIX_SHIFT 8
2109#define VTD_BF_MTRRCAP_REG_FIX_MASK UINT64_C(0x0000000000000100)
2110/** R: Reserved (bit 9). */
2111#define VTD_BF_MTRRCAP_REG_RSVD_9_SHIFT 9
2112#define VTD_BF_MTRRCAP_REG_RSVD_9_MASK UINT64_C(0x0000000000000200)
2113/** WC: Write Combining. */
2114#define VTD_BF_MTRRCAP_REG_WC_SHIFT 10
2115#define VTD_BF_MTRRCAP_REG_WC_MASK UINT64_C(0x0000000000000400)
2116/** R: Reserved (bits 63:11). */
2117#define VTD_BF_MTRRCAP_REG_RSVD_63_11_SHIFT 11
2118#define VTD_BF_MTRRCAP_REG_RSVD_63_11_MASK UINT64_C(0xfffffffffffff800)
2119RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_MTRRCAP_REG_, UINT64_C(0), UINT64_MAX,
2120 (VCNT, FIX, RSVD_9, WC, RSVD_63_11));
2121
2122/** RW: Read/write mask. */
2123#define VTD_MTRRCAP_REG_RW_MASK UINT64_C(0)
2124/** @} */
2125
2126
2127/** @name MTRR Default Type Register (MTRRDEF_REG).
2128 * In accordance with the Intel spec.
2129 * @{ */
2130/** TYPE: Default Memory Type. */
2131#define VTD_BF_MTRRDEF_REG_TYPE_SHIFT 0
2132#define VTD_BF_MTRRDEF_REG_TYPE_MASK UINT64_C(0x00000000000000ff)
2133/** R: Reserved (bits 9:8). */
2134#define VTD_BF_MTRRDEF_REG_RSVD_9_8_SHIFT 8
2135#define VTD_BF_MTRRDEF_REG_RSVD_9_8_MASK UINT64_C(0x0000000000000300)
2136/** FE: Fixed Range MTRR Enable. */
2137#define VTD_BF_MTRRDEF_REG_FE_SHIFT 10
2138#define VTD_BF_MTRRDEF_REG_FE_MASK UINT64_C(0x0000000000000400)
2139/** E: MTRR Enable. */
2140#define VTD_BF_MTRRDEF_REG_E_SHIFT 11
2141#define VTD_BF_MTRRDEF_REG_E_MASK UINT64_C(0x0000000000000800)
2142/** R: Reserved (bits 63:12). */
2143#define VTD_BF_MTRRDEF_REG_RSVD_63_12_SHIFT 12
2144#define VTD_BF_MTRRDEF_REG_RSVD_63_12_MASK UINT64_C(0xfffffffffffff000)
2145RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_MTRRDEF_REG_, UINT64_C(0), UINT64_MAX,
2146 (TYPE, RSVD_9_8, FE, E, RSVD_63_12));
2147
2148/** RW: Read/write mask. */
2149#define VTD_MTRRDEF_REG_RW_MASK ( VTD_BF_MTRRDEF_REG_TYPE_MASK | VTD_BF_MTRRDEF_REG_FE_MASK \
2150 | VTD_BF_MTRRDEF_REG_E_MASK)
2151/** @} */
2152
2153
2154/** @name Virtual Command Capability Register (VCCAP_REG).
2155 * In accordance with the Intel spec.
2156 * @{ */
2157/** PAS: PASID Support. */
2158#define VTD_BF_VCCAP_REG_PAS_SHIFT 0
2159#define VTD_BF_VCCAP_REG_PAS_MASK UINT64_C(0x0000000000000001)
2160/** R: Reserved (bits 63:1). */
2161#define VTD_BF_VCCAP_REG_RSVD_63_1_SHIFT 1
2162#define VTD_BF_VCCAP_REG_RSVD_63_1_MASK UINT64_C(0xfffffffffffffffe)
2163RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_VCCAP_REG_, UINT64_C(0), UINT64_MAX,
2164 (PAS, RSVD_63_1));
2165
2166/** RW: Read/write mask. */
2167#define VTD_VCCAP_REG_RW_MASK UINT64_C(0)
2168/** @} */
2169
2170
2171/** @name Virtual Command Extended Operand Register (VCMD_EO_REG).
2172 * In accordance with the Intel spec.
2173 * @{ */
2174/** OB: Operand B. */
2175#define VTD_BF_VCMD_EO_REG_OB_SHIFT 0
2176#define VTD_BF_VCMD_EO_REG_OB_MASK UINT32_C(0xffffffffffffffff)
2177
2178/** RW: Read/write mask. */
2179#define VTD_VCMD_EO_REG_RW_MASK VTD_BF_VCMD_EO_REG_OB_MASK
2180/** @} */
2181
2182
2183/** @name Virtual Command Register (VCMD_REG).
2184 * In accordance with the Intel spec.
2185 * @{ */
2186/** CMD: Command. */
2187#define VTD_BF_VCMD_REG_CMD_SHIFT 0
2188#define VTD_BF_VCMD_REG_CMD_MASK UINT64_C(0x00000000000000ff)
2189/** OP: Operand. */
2190#define VTD_BF_VCMD_REG_OP_SHIFT 8
2191#define VTD_BF_VCMD_REG_OP_MASK UINT64_C(0xffffffffffffff00)
2192RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_VCMD_REG_, UINT64_C(0), UINT64_MAX,
2193 (CMD, OP));
2194
2195/** RW: Read/write mask. */
2196#define VTD_VCMD_REG_RW_MASK (VTD_BF_VCMD_REG_CMD_MASK | VTD_BF_VCMD_REG_OP_MASK)
2197/** @} */
2198
2199
2200/** @name Virtual Command Response Register (VCRSP_REG).
2201 * In accordance with the Intel spec.
2202 * @{ */
2203/** IP: In Progress. */
2204#define VTD_BF_VCRSP_REG_IP_SHIFT 0
2205#define VTD_BF_VCRSP_REG_IP_MASK UINT64_C(0x0000000000000001)
2206/** SC: Status Code. */
2207#define VTD_BF_VCRSP_REG_SC_SHIFT 1
2208#define VTD_BF_VCRSP_REG_SC_MASK UINT64_C(0x0000000000000006)
2209/** R: Reserved (bits 7:3). */
2210#define VTD_BF_VCRSP_REG_RSVD_7_3_SHIFT 3
2211#define VTD_BF_VCRSP_REG_RSVD_7_3_MASK UINT64_C(0x00000000000000f8)
2212/** RSLT: Result. */
2213#define VTD_BF_VCRSP_REG_RSLT_SHIFT 8
2214#define VTD_BF_VCRSP_REG_RSLT_MASK UINT64_C(0xffffffffffffff00)
2215RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_VCRSP_REG_, UINT64_C(0), UINT64_MAX,
2216 (IP, SC, RSVD_7_3, RSLT));
2217
2218/** RW: Read/write mask. */
2219#define VTD_VCRSP_REG_RW_MASK UINT64_C(0)
2220/** @} */
2221
2222
2223/** @name Generic Invalidation Descriptor.
2224 * In accordance with the Intel spec.
2225 * Non-reserved fields here are common to all invalidation descriptors.
2226 * @{ */
2227/** Type (Lo). */
2228#define VTD_BF_0_GENERIC_INV_DSC_TYPE_LO_SHIFT 0
2229#define VTD_BF_0_GENERIC_INV_DSC_TYPE_LO_MASK UINT64_C(0x000000000000000f)
2230/** R: Reserved (bits 8:4). */
2231#define VTD_BF_0_GENERIC_INV_DSC_RSVD_8_4_SHIFT 4
2232#define VTD_BF_0_GENERIC_INV_DSC_RSVD_8_4_MASK UINT64_C(0x00000000000001f0)
2233/** Type (Hi). */
2234#define VTD_BF_0_GENERIC_INV_DSC_TYPE_HI_SHIFT 9
2235#define VTD_BF_0_GENERIC_INV_DSC_TYPE_HI_MASK UINT64_C(0x0000000000000e00)
2236/** R: Reserved (bits 63:12). */
2237#define VTD_BF_0_GENERIC_INV_DSC_RSVD_63_12_SHIFT 12
2238#define VTD_BF_0_GENERIC_INV_DSC_RSVD_63_12_MASK UINT64_C(0xfffffffffffff000)
2239RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_GENERIC_INV_DSC_, UINT64_C(0), UINT64_MAX,
2240 (TYPE_LO, RSVD_8_4, TYPE_HI, RSVD_63_12));
2241
2242/** GENERIC_INV_DSC: Type. */
2243#define VTD_GENERIC_INV_DSC_GET_TYPE(a) ((((a) & VTD_BF_0_GENERIC_INV_DSC_TYPE_HI_MASK) >> 5) \
2244 | ((a) & VTD_BF_0_GENERIC_INV_DSC_TYPE_LO_MASK))
2245/** @} */
2246
2247
2248/** @name Context-Cache Invalidation Descriptor (cc_inv_dsc).
2249 * In accordance with the Intel spec.
2250 * @{ */
2251/** Type (Lo). */
2252#define VTD_BF_0_CC_INV_DSC_TYPE_LO_SHIFT 0
2253#define VTD_BF_0_CC_INV_DSC_TYPE_LO_MASK UINT64_C(0x000000000000000f)
2254/** G: Granularity. */
2255#define VTD_BF_0_CC_INV_DSC_G_SHIFT 4
2256#define VTD_BF_0_CC_INV_DSC_G_MASK UINT64_C(0x0000000000000030)
2257/** R: Reserved (bits 8:6). */
2258#define VTD_BF_0_CC_INV_DSC_RSVD_8_6_SHIFT 6
2259#define VTD_BF_0_CC_INV_DSC_RSVD_8_6_MASK UINT64_C(0x00000000000001c0)
2260/** Type (Hi). */
2261#define VTD_BF_0_CC_INV_DSC_TYPE_HI_SHIFT 9
2262#define VTD_BF_0_CC_INV_DSC_TYPE_HI_MASK UINT64_C(0x0000000000000e00)
2263/** R: Reserved (bits 15:12). */
2264#define VTD_BF_0_CC_INV_DSC_RSVD_15_12_SHIFT 12
2265#define VTD_BF_0_CC_INV_DSC_RSVD_15_12_MASK UINT64_C(0x000000000000f000)
2266/** DID: Domain Id. */
2267#define VTD_BF_0_CC_INV_DSC_DID_SHIFT 16
2268#define VTD_BF_0_CC_INV_DSC_DID_MASK UINT64_C(0x00000000ffff0000)
2269/** SID: Source Id. */
2270#define VTD_BF_0_CC_INV_DSC_SID_SHIFT 32
2271#define VTD_BF_0_CC_INV_DSC_SID_MASK UINT64_C(0x0000ffff00000000)
2272/** FM: Function Mask. */
2273#define VTD_BF_0_CC_INV_DSC_FM_SHIFT 48
2274#define VTD_BF_0_CC_INV_DSC_FM_MASK UINT64_C(0x0003000000000000)
2275/** R: Reserved (bits 63:50). */
2276#define VTD_BF_0_CC_INV_DSC_RSVD_63_50_SHIFT 50
2277#define VTD_BF_0_CC_INV_DSC_RSVD_63_50_MASK UINT64_C(0xfffc000000000000)
2278RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_CC_INV_DSC_, UINT64_C(0), UINT64_MAX,
2279 (TYPE_LO, G, RSVD_8_6, TYPE_HI, RSVD_15_12, DID, SID, FM, RSVD_63_50));
2280/** @} */
2281
2282
2283/** @name PASID-Cache Invalidation Descriptor (pc_inv_dsc).
2284 * In accordance with the Intel spec.
2285 * @{ */
2286/** Type (Lo). */
2287#define VTD_BF_0_PC_INV_DSC_TYPE_LO_SHIFT 0
2288#define VTD_BF_0_PC_INV_DSC_TYPE_LO_MASK UINT64_C(0x000000000000000f)
2289/** G: Granularity. */
2290#define VTD_BF_0_PC_INV_DSC_G_SHIFT 4
2291#define VTD_BF_0_PC_INV_DSC_G_MASK UINT64_C(0x0000000000000030)
2292/** R: Reserved (bits 8:6). */
2293#define VTD_BF_0_PC_INV_DSC_RSVD_8_6_SHIFT 6
2294#define VTD_BF_0_PC_INV_DSC_RSVD_8_6_MASK UINT64_C(0x00000000000001c0)
2295/** Type (Hi). */
2296#define VTD_BF_0_PC_INV_DSC_TYPE_HI_SHIFT 9
2297#define VTD_BF_0_PC_INV_DSC_TYPE_HI_MASK UINT64_C(0x0000000000000e00)
2298/** R: Reserved (bits 15:12). */
2299#define VTD_BF_0_PC_INV_DSC_RSVD_15_12_SHIFT 12
2300#define VTD_BF_0_PC_INV_DSC_RSVD_15_12_MASK UINT64_C(0x000000000000f000)
2301/** DID: Domain Id. */
2302#define VTD_BF_0_PC_INV_DSC_DID_SHIFT 16
2303#define VTD_BF_0_PC_INV_DSC_DID_MASK UINT64_C(0x00000000ffff0000)
2304/** PASID: Process Address-Space Id. */
2305#define VTD_BF_0_PC_INV_DSC_PASID_SHIFT 32
2306#define VTD_BF_0_PC_INV_DSC_PASID_MASK UINT64_C(0x000fffff00000000)
2307/** R: Reserved (bits 63:52). */
2308#define VTD_BF_0_PC_INV_DSC_RSVD_63_52_SHIFT 52
2309#define VTD_BF_0_PC_INV_DSC_RSVD_63_52_MASK UINT64_C(0xfff0000000000000)
2310
2311RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_PC_INV_DSC_, UINT64_C(0), UINT64_MAX,
2312 (TYPE_LO, G, RSVD_8_6, TYPE_HI, RSVD_15_12, DID, PASID, RSVD_63_52));
2313/** @} */
2314
2315
2316/** @name IOTLB Invalidate Descriptor (iotlb_inv_dsc).
2317 * In accordance with the Intel spec.
2318 * @{ */
2319/** Type (Lo). */
2320#define VTD_BF_0_IOTLB_INV_DSC_TYPE_LO_SHIFT 0
2321#define VTD_BF_0_IOTLB_INV_DSC_TYPE_LO_MASK UINT64_C(0x000000000000000f)
2322/** G: Granularity. */
2323#define VTD_BF_0_IOTLB_INV_DSC_G_SHIFT 4
2324#define VTD_BF_0_IOTLB_INV_DSC_G_MASK UINT64_C(0x0000000000000030)
2325/** DW: Drain Writes. */
2326#define VTD_BF_0_IOTLB_INV_DSC_DW_SHIFT 6
2327#define VTD_BF_0_IOTLB_INV_DSC_DW_MASK UINT64_C(0x0000000000000040)
2328/** DR: Drain Reads. */
2329#define VTD_BF_0_IOTLB_INV_DSC_DR_SHIFT 7
2330#define VTD_BF_0_IOTLB_INV_DSC_DR_MASK UINT64_C(0x0000000000000080)
2331/** R: Reserved (bit 8). */
2332#define VTD_BF_0_IOTLB_INV_DSC_RSVD_8_SHIFT 8
2333#define VTD_BF_0_IOTLB_INV_DSC_RSVD_8_MASK UINT64_C(0x0000000000000100)
2334/** Type (Hi). */
2335#define VTD_BF_0_IOTLB_INV_DSC_TYPE_HI_SHIFT 9
2336#define VTD_BF_0_IOTLB_INV_DSC_TYPE_HI_MASK UINT64_C(0x0000000000000e00)
2337/** R: Reserved (bits 15:12). */
2338#define VTD_BF_0_IOTLB_INV_DSC_RSVD_15_12_SHIFT 12
2339#define VTD_BF_0_IOTLB_INV_DSC_RSVD_15_12_MASK UINT64_C(0x000000000000f000)
2340/** DID: Domain Id. */
2341#define VTD_BF_0_IOTLB_INV_DSC_DID_SHIFT 16
2342#define VTD_BF_0_IOTLB_INV_DSC_DID_MASK UINT64_C(0x00000000ffff0000)
2343/** R: Reserved (bits 63:32). */
2344#define VTD_BF_0_IOTLB_INV_DSC_RSVD_63_32_SHIFT 32
2345#define VTD_BF_0_IOTLB_INV_DSC_RSVD_63_32_MASK UINT64_C(0xffffffff00000000)
2346RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_IOTLB_INV_DSC_, UINT64_C(0), UINT64_MAX,
2347 (TYPE_LO, G, DW, DR, RSVD_8, TYPE_HI, RSVD_15_12, DID, RSVD_63_32));
2348
2349/** AM: Address Mask. */
2350#define VTD_BF_1_IOTLB_INV_DSC_AM_SHIFT 0
2351#define VTD_BF_1_IOTLB_INV_DSC_AM_MASK UINT64_C(0x000000000000003f)
2352/** IH: Invalidation Hint. */
2353#define VTD_BF_1_IOTLB_INV_DSC_IH_SHIFT 6
2354#define VTD_BF_1_IOTLB_INV_DSC_IH_MASK UINT64_C(0x0000000000000040)
2355/** R: Reserved (bits 11:7). */
2356#define VTD_BF_1_IOTLB_INV_DSC_RSVD_11_7_SHIFT 7
2357#define VTD_BF_1_IOTLB_INV_DSC_RSVD_11_7_MASK UINT64_C(0x0000000000000f80)
2358/** ADDR: Address. */
2359#define VTD_BF_1_IOTLB_INV_DSC_ADDR_SHIFT 12
2360#define VTD_BF_1_IOTLB_INV_DSC_ADDR_MASK UINT64_C(0xfffffffffffff000)
2361RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_IOTLB_INV_DSC_, UINT64_C(0), UINT64_MAX,
2362 (AM, IH, RSVD_11_7, ADDR));
2363/** @} */
2364
2365
2366/** @name PASID-based IOTLB Invalidate Descriptor (p_iotlb_inv_dsc).
2367 * In accordance with the Intel spec.
2368 * @{ */
2369/** Type (Lo). */
2370#define VTD_BF_0_P_IOTLB_INV_DSC_TYPE_LO_SHIFT 0
2371#define VTD_BF_0_P_IOTLB_INV_DSC_TYPE_LO_MASK UINT64_C(0x000000000000000f)
2372/** G: Granularity. */
2373#define VTD_BF_0_P_IOTLB_INV_DSC_G_SHIFT 4
2374#define VTD_BF_0_P_IOTLB_INV_DSC_G_MASK UINT64_C(0x0000000000000030)
2375/** R: Reserved (bits 8:6). */
2376#define VTD_BF_0_P_IOTLB_INV_DSC_RSVD_8_6_SHIFT 6
2377#define VTD_BF_0_P_IOTLB_INV_DSC_RSVD_8_6_MASK UINT64_C(0x00000000000001c0)
2378/** Type (Hi). */
2379#define VTD_BF_0_P_IOTLB_INV_DSC_TYPE_HI_SHIFT 9
2380#define VTD_BF_0_P_IOTLB_INV_DSC_TYPE_HI_MASK UINT64_C(0x0000000000000e00)
2381/** R: Reserved (bits 15:12). */
2382#define VTD_BF_0_P_IOTLB_INV_DSC_RSVD_15_12_SHIFT 12
2383#define VTD_BF_0_P_IOTLB_INV_DSC_RSVD_15_12_MASK UINT64_C(0x000000000000f000)
2384/** DID: Domain Id. */
2385#define VTD_BF_0_P_IOTLB_INV_DSC_DID_SHIFT 16
2386#define VTD_BF_0_P_IOTLB_INV_DSC_DID_MASK UINT64_C(0x00000000ffff0000)
2387/** PASID: Process Address-Space Id. */
2388#define VTD_BF_0_P_IOTLB_INV_DSC_PASID_SHIFT 32
2389#define VTD_BF_0_P_IOTLB_INV_DSC_PASID_MASK UINT64_C(0x000fffff00000000)
2390/** R: Reserved (bits 63:52). */
2391#define VTD_BF_0_P_IOTLB_INV_DSC_RSVD_63_52_SHIFT 52
2392#define VTD_BF_0_P_IOTLB_INV_DSC_RSVD_63_52_MASK UINT64_C(0xfff0000000000000)
2393RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_P_IOTLB_INV_DSC_, UINT64_C(0), UINT64_MAX,
2394 (TYPE_LO, G, RSVD_8_6, TYPE_HI, RSVD_15_12, DID, PASID, RSVD_63_52));
2395
2396
2397/** AM: Address Mask. */
2398#define VTD_BF_1_P_IOTLB_INV_DSC_AM_SHIFT 0
2399#define VTD_BF_1_P_IOTLB_INV_DSC_AM_MASK UINT64_C(0x000000000000003f)
2400/** IH: Invalidation Hint. */
2401#define VTD_BF_1_P_IOTLB_INV_DSC_IH_SHIFT 6
2402#define VTD_BF_1_P_IOTLB_INV_DSC_IH_MASK UINT64_C(0x0000000000000040)
2403/** R: Reserved (bits 11:7). */
2404#define VTD_BF_1_P_IOTLB_INV_DSC_RSVD_11_7_SHIFT 7
2405#define VTD_BF_1_P_IOTLB_INV_DSC_RSVD_11_7_MASK UINT64_C(0x0000000000000f80)
2406/** ADDR: Address. */
2407#define VTD_BF_1_P_IOTLB_INV_DSC_ADDR_SHIFT 12
2408#define VTD_BF_1_P_IOTLB_INV_DSC_ADDR_MASK UINT64_C(0xfffffffffffff000)
2409RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_P_IOTLB_INV_DSC_, UINT64_C(0), UINT64_MAX,
2410 (AM, IH, RSVD_11_7, ADDR));
2411/** @} */
2412
2413
2414/** @name Device-TLB Invalidate Descriptor (dev_tlb_inv_dsc).
2415 * In accordance with the Intel spec.
2416 * @{ */
2417/** Type (Lo). */
2418#define VTD_BF_0_DEV_TLB_INV_DSC_TYPE_LO_SHIFT 0
2419#define VTD_BF_0_DEV_TLB_INV_DSC_TYPE_LO_MASK UINT64_C(0x000000000000000f)
2420/** R: Reserved (bits 8:4). */
2421#define VTD_BF_0_DEV_TLB_INV_DSC_RSVD_8_4_SHIFT 4
2422#define VTD_BF_0_DEV_TLB_INV_DSC_RSVD_8_4_MASK UINT64_C(0x00000000000001f0)
2423/** Type (Hi). */
2424#define VTD_BF_0_DEV_TLB_INV_DSC_TYPE_HI_SHIFT 9
2425#define VTD_BF_0_DEV_TLB_INV_DSC_TYPE_HI_MASK UINT64_C(0x0000000000000e00)
2426/** PFSID: Physical-Function Source Id (Lo). */
2427#define VTD_BF_0_DEV_TLB_INV_DSC_PFSID_LO_SHIFT 12
2428#define VTD_BF_0_DEV_TLB_INV_DSC_PFSID_LO_MASK UINT64_C(0x000000000000f000)
2429/** MIP: Max Invalidations Pending. */
2430#define VTD_BF_0_DEV_TLB_INV_DSC_MIP_SHIFT 16
2431#define VTD_BF_0_DEV_TLB_INV_DSC_MIP_MASK UINT64_C(0x00000000001f0000)
2432/** R: Reserved (bits 31:21). */
2433#define VTD_BF_0_DEV_TLB_INV_DSC_RSVD_31_21_SHIFT 21
2434#define VTD_BF_0_DEV_TLB_INV_DSC_RSVD_31_21_MASK UINT64_C(0x00000000ffe00000)
2435/** SID: Source Id. */
2436#define VTD_BF_0_DEV_TLB_INV_DSC_SID_SHIFT 32
2437#define VTD_BF_0_DEV_TLB_INV_DSC_SID_MASK UINT64_C(0x0000ffff00000000)
2438/** R: Reserved (bits 51:48). */
2439#define VTD_BF_0_DEV_TLB_INV_DSC_RSVD_51_48_SHIFT 48
2440#define VTD_BF_0_DEV_TLB_INV_DSC_RSVD_51_48_MASK UINT64_C(0x000f000000000000)
2441/** PFSID: Physical-Function Source Id (Hi). */
2442#define VTD_BF_0_DEV_TLB_INV_DSC_PFSID_HI_SHIFT 52
2443#define VTD_BF_0_DEV_TLB_INV_DSC_PFSID_HI_MASK UINT64_C(0xfff0000000000000)
2444RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_DEV_TLB_INV_DSC_, UINT64_C(0), UINT64_MAX,
2445 (TYPE_LO, RSVD_8_4, TYPE_HI, PFSID_LO, MIP, RSVD_31_21, SID, RSVD_51_48, PFSID_HI));
2446
2447/** S: Size. */
2448#define VTD_BF_1_DEV_TLB_INV_DSC_S_SHIFT 0
2449#define VTD_BF_1_DEV_TLB_INV_DSC_S_MASK UINT64_C(0x0000000000000001)
2450/** R: Reserved (bits 11:1). */
2451#define VTD_BF_1_DEV_TLB_INV_DSC_RSVD_11_1_SHIFT 1
2452#define VTD_BF_1_DEV_TLB_INV_DSC_RSVD_11_1_MASK UINT64_C(0x0000000000000ffe)
2453/** ADDR: Address. */
2454#define VTD_BF_1_DEV_TLB_INV_DSC_ADDR_SHIFT 12
2455#define VTD_BF_1_DEV_TLB_INV_DSC_ADDR_MASK UINT64_C(0xfffffffffffff000)
2456RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_DEV_TLB_INV_DSC_, UINT64_C(0), UINT64_MAX,
2457 (S, RSVD_11_1, ADDR));
2458/** @} */
2459
2460
2461/** @name PASID-based-device-TLB Invalidate Descriptor (p_dev_tlb_inv_dsc).
2462 * In accordance with the Intel spec.
2463 * @{ */
2464/** Type (Lo). */
2465#define VTD_BF_0_P_DEV_TLB_INV_DSC_TYPE_LO_SHIFT 0
2466#define VTD_BF_0_P_DEV_TLB_INV_DSC_TYPE_LO_MASK UINT64_C(0x000000000000000f)
2467/** MIP: Max Invalidations Pending. */
2468#define VTD_BF_0_P_DEV_TLB_INV_DSC_MIP_SHIFT 4
2469#define VTD_BF_0_P_DEV_TLB_INV_DSC_MIP_MASK UINT64_C(0x00000000000001f0)
2470/** Type (Hi). */
2471#define VTD_BF_0_P_DEV_TLB_INV_DSC_TYPE_HI_SHIFT 9
2472#define VTD_BF_0_P_DEV_TLB_INV_DSC_TYPE_HI_MASK UINT64_C(0x0000000000000e00)
2473/** PFSID: Physical-Function Source Id (Lo). */
2474#define VTD_BF_0_P_DEV_TLB_INV_DSC_PFSID_LO_SHIFT 12
2475#define VTD_BF_0_P_DEV_TLB_INV_DSC_PFSID_LO_MASK UINT64_C(0x000000000000f000)
2476/** SID: Source Id. */
2477#define VTD_BF_0_P_DEV_TLB_INV_DSC_SID_SHIFT 16
2478#define VTD_BF_0_P_DEV_TLB_INV_DSC_SID_MASK UINT64_C(0x00000000ffff0000)
2479/** PASID: Process Address-Space Id. */
2480#define VTD_BF_0_P_DEV_TLB_INV_DSC_PASID_SHIFT 32
2481#define VTD_BF_0_P_DEV_TLB_INV_DSC_PASID_MASK UINT64_C(0x000fffff00000000)
2482/** PFSID: Physical-Function Source Id (Hi). */
2483#define VTD_BF_0_P_DEV_TLB_INV_DSC_PFSID_HI_SHIFT 52
2484#define VTD_BF_0_P_DEV_TLB_INV_DSC_PFSID_HI_MASK UINT64_C(0xfff0000000000000)
2485RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_P_DEV_TLB_INV_DSC_, UINT64_C(0), UINT64_MAX,
2486 (TYPE_LO, MIP, TYPE_HI, PFSID_LO, SID, PASID, PFSID_HI));
2487
2488/** G: Granularity. */
2489#define VTD_BF_1_P_DEV_TLB_INV_DSC_G_SHIFT 0
2490#define VTD_BF_1_P_DEV_TLB_INV_DSC_G_MASK UINT64_C(0x0000000000000001)
2491/** R: Reserved (bits 10:1). */
2492#define VTD_BF_1_P_DEV_TLB_INV_DSC_RSVD_10_1_SHIFT 1
2493#define VTD_BF_1_P_DEV_TLB_INV_DSC_RSVD_10_1_MASK UINT64_C(0x00000000000007fe)
2494/** S: Size. */
2495#define VTD_BF_1_P_DEV_TLB_INV_DSC_S_SHIFT 11
2496#define VTD_BF_1_P_DEV_TLB_INV_DSC_S_MASK UINT64_C(0x0000000000000800)
2497/** ADDR: Address. */
2498#define VTD_BF_1_P_DEV_TLB_INV_DSC_ADDR_SHIFT 12
2499#define VTD_BF_1_P_DEV_TLB_INV_DSC_ADDR_MASK UINT64_C(0xfffffffffffff000)
2500RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_P_DEV_TLB_INV_DSC_, UINT64_C(0), UINT64_MAX,
2501 (G, RSVD_10_1, S, ADDR));
2502/** @} */
2503
2504
2505/** @name Interrupt Entry Cache Invalidate Descriptor (iec_inv_dsc).
2506 * In accordance with the Intel spec.
2507 * @{ */
2508/** Type (Lo). */
2509#define VTD_BF_0_IEC_INV_DSC_TYPE_LO_SHIFT 0
2510#define VTD_BF_0_IEC_INV_DSC_TYPE_LO_MASK UINT64_C(0x000000000000000f)
2511/** G: Granularity. */
2512#define VTD_BF_0_IEC_INV_DSC_G_SHIFT 4
2513#define VTD_BF_0_IEC_INV_DSC_G_MASK UINT64_C(0x0000000000000010)
2514/** R: Reserved (bits 8:5). */
2515#define VTD_BF_0_IEC_INV_DSC_RSVD_8_5_SHIFT 5
2516#define VTD_BF_0_IEC_INV_DSC_RSVD_8_5_MASK UINT64_C(0x00000000000001e0)
2517/** Type (Hi). */
2518#define VTD_BF_0_IEC_INV_DSC_TYPE_HI_SHIFT 9
2519#define VTD_BF_0_IEC_INV_DSC_TYPE_HI_MASK UINT64_C(0x0000000000000e00)
2520/** R: Reserved (bits 26:12). */
2521#define VTD_BF_0_IEC_INV_DSC_RSVD_26_12_SHIFT 12
2522#define VTD_BF_0_IEC_INV_DSC_RSVD_26_12_MASK UINT64_C(0x0000000007fff000)
2523/** IM: Index Mask. */
2524#define VTD_BF_0_IEC_INV_DSC_IM_SHIFT 27
2525#define VTD_BF_0_IEC_INV_DSC_IM_MASK UINT64_C(0x00000000f8000000)
2526/** IIDX: Interrupt Index. */
2527#define VTD_BF_0_IEC_INV_DSC_IIDX_SHIFT 32
2528#define VTD_BF_0_IEC_INV_DSC_IIDX_MASK UINT64_C(0x0000ffff00000000)
2529/** R: Reserved (bits 63:48). */
2530#define VTD_BF_0_IEC_INV_DSC_RSVD_63_48_SHIFT 48
2531#define VTD_BF_0_IEC_INV_DSC_RSVD_63_48_MASK UINT64_C(0xffff000000000000)
2532RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_IEC_INV_DSC_, UINT64_C(0), UINT64_MAX,
2533 (TYPE_LO, G, RSVD_8_5, TYPE_HI, RSVD_26_12, IM, IIDX, RSVD_63_48));
2534/** @} */
2535
2536
2537/** @name Invalidation Wait Descriptor (inv_wait_dsc).
2538 * In accordance with the Intel spec.
2539 * @{ */
2540/** Type (Lo). */
2541#define VTD_BF_0_INV_WAIT_DSC_TYPE_LO_SHIFT 0
2542#define VTD_BF_0_INV_WAIT_DSC_TYPE_LO_MASK UINT64_C(0x000000000000000f)
2543/** IF: Interrupt Flag. */
2544#define VTD_BF_0_INV_WAIT_DSC_IF_SHIFT 4
2545#define VTD_BF_0_INV_WAIT_DSC_IF_MASK UINT64_C(0x0000000000000010)
2546/** SW: Status Write. */
2547#define VTD_BF_0_INV_WAIT_DSC_SW_SHIFT 5
2548#define VTD_BF_0_INV_WAIT_DSC_SW_MASK UINT64_C(0x0000000000000020)
2549/** FN: Fence Flag. */
2550#define VTD_BF_0_INV_WAIT_DSC_FN_SHIFT 6
2551#define VTD_BF_0_INV_WAIT_DSC_FN_MASK UINT64_C(0x0000000000000040)
2552/** PD: Page-Request Drain. */
2553#define VTD_BF_0_INV_WAIT_DSC_PD_SHIFT 7
2554#define VTD_BF_0_INV_WAIT_DSC_PD_MASK UINT64_C(0x0000000000000080)
2555/** R: Reserved (bit 8). */
2556#define VTD_BF_0_INV_WAIT_DSC_RSVD_8_SHIFT 8
2557#define VTD_BF_0_INV_WAIT_DSC_RSVD_8_MASK UINT64_C(0x0000000000000100)
2558/** Type (Hi). */
2559#define VTD_BF_0_INV_WAIT_DSC_TYPE_HI_SHIFT 9
2560#define VTD_BF_0_INV_WAIT_DSC_TYPE_HI_MASK UINT64_C(0x0000000000000e00)
2561/** R: Reserved (bits 31:12). */
2562#define VTD_BF_0_INV_WAIT_DSC_RSVD_31_12_SHIFT 12
2563#define VTD_BF_0_INV_WAIT_DSC_RSVD_31_12_MASK UINT64_C(0x00000000fffff000)
2564/** STDATA: Status Data. */
2565#define VTD_BF_0_INV_WAIT_DSC_STDATA_SHIFT 32
2566#define VTD_BF_0_INV_WAIT_DSC_STDATA_MASK UINT64_C(0xffffffff00000000)
2567RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_INV_WAIT_DSC_, UINT64_C(0), UINT64_MAX,
2568 (TYPE_LO, IF, SW, FN, PD, RSVD_8, TYPE_HI, RSVD_31_12, STDATA));
2569
2570/** R: Reserved (bits 1:0). */
2571#define VTD_BF_1_INV_WAIT_DSC_RSVD_1_0_SHIFT 0
2572#define VTD_BF_1_INV_WAIT_DSC_RSVD_1_0_MASK UINT64_C(0x0000000000000003)
2573/** STADDR: Status Address. */
2574#define VTD_BF_1_INV_WAIT_DSC_STADDR_SHIFT 2
2575#define VTD_BF_1_INV_WAIT_DSC_STADDR_MASK UINT64_C(0xfffffffffffffffc)
2576RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_INV_WAIT_DSC_, UINT64_C(0), UINT64_MAX,
2577 (RSVD_1_0, STADDR));
2578
2579/* INV_WAIT_DSC: Qword 0 valid mask. */
2580#define VTD_INV_WAIT_DSC_0_VALID_MASK ( VTD_BF_0_INV_WAIT_DSC_TYPE_LO_MASK \
2581 | VTD_BF_0_INV_WAIT_DSC_IF_MASK \
2582 | VTD_BF_0_INV_WAIT_DSC_SW_MASK \
2583 | VTD_BF_0_INV_WAIT_DSC_FN_MASK \
2584 | VTD_BF_0_INV_WAIT_DSC_PD_MASK \
2585 | VTD_BF_0_INV_WAIT_DSC_TYPE_HI_MASK \
2586 | VTD_BF_0_INV_WAIT_DSC_STDATA_MASK)
2587/* INV_WAIT_DSC: Qword 1 valid mask. */
2588#define VTD_INV_WAIT_DSC_1_VALID_MASK VTD_BF_1_INV_WAIT_DSC_STADDR_MASK
2589/** @} */
2590
2591
2592/** @name Invalidation descriptor types.
2593 * In accordance with the Intel spec.
2594 * @{ */
2595#define VTD_CC_INV_DSC_TYPE 1
2596#define VTD_IOTLB_INV_DSC_TYPE 2
2597#define VTD_DEV_TLB_INV_DSC_TYPE 3
2598#define VTD_IEC_INV_DSC_TYPE 4
2599#define VTD_INV_WAIT_DSC_TYPE 5
2600#define VTD_P_IOTLB_INV_DSC_TYPE 6
2601#define VTD_PC_INV_DSC_TYPE 7
2602#define VTD_P_DEV_TLB_INV_DSC_TYPE 8
2603/** @} */
2604
2605
2606/** @name Remappable Format Interrupt Request.
2607 * In accordance with the Intel spec.
2608 * @{ */
2609/** IGN: Ignored (bits 1:0). */
2610#define VTD_BF_REMAPPABLE_MSI_ADDR_IGN_1_0_SHIFT 0
2611#define VTD_BF_REMAPPABLE_MSI_ADDR_IGN_1_0_MASK UINT32_C(0x00000003)
2612/** Handle (Hi). */
2613#define VTD_BF_REMAPPABLE_MSI_ADDR_HANDLE_HI_SHIFT 2
2614#define VTD_BF_REMAPPABLE_MSI_ADDR_HANDLE_HI_MASK UINT32_C(0x00000004)
2615/** SHV: Subhandle Valid. */
2616#define VTD_BF_REMAPPABLE_MSI_ADDR_SHV_SHIFT 3
2617#define VTD_BF_REMAPPABLE_MSI_ADDR_SHV_MASK UINT32_C(0x00000008)
2618/** Interrupt format. */
2619#define VTD_BF_REMAPPABLE_MSI_ADDR_INTR_FMT_SHIFT 4
2620#define VTD_BF_REMAPPABLE_MSI_ADDR_INTR_FMT_MASK UINT32_C(0x00000010)
2621/** Handle (Lo). */
2622#define VTD_BF_REMAPPABLE_MSI_ADDR_HANDLE_LO_SHIFT 5
2623#define VTD_BF_REMAPPABLE_MSI_ADDR_HANDLE_LO_MASK UINT32_C(0x000fffe0)
2624/** Address. */
2625#define VTD_BF_REMAPPABLE_MSI_ADDR_ADDR_SHIFT 20
2626#define VTD_BF_REMAPPABLE_MSI_ADDR_ADDR_MASK UINT32_C(0xfff00000)
2627RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_REMAPPABLE_MSI_ADDR_, UINT32_C(0), UINT32_MAX,
2628 (IGN_1_0, HANDLE_HI, SHV, INTR_FMT, HANDLE_LO, ADDR));
2629
2630/** Subhandle. */
2631#define VTD_BF_REMAPPABLE_MSI_DATA_SUBHANDLE_SHIFT 0
2632#define VTD_BF_REMAPPABLE_MSI_DATA_SUBHANDLE_MASK UINT32_C(0x0000ffff)
2633/** R: Reserved (bits 31:16). */
2634#define VTD_BF_REMAPPABLE_MSI_DATA_RSVD_31_16_SHIFT 16
2635#define VTD_BF_REMAPPABLE_MSI_DATA_RSVD_31_16_MASK UINT32_C(0xffff0000)
2636RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_REMAPPABLE_MSI_DATA_, UINT32_C(0), UINT32_MAX,
2637 (SUBHANDLE, RSVD_31_16));
2638
2639/** Remappable MSI Address: Valid mask. */
2640#define VTD_REMAPPABLE_MSI_ADDR_VALID_MASK UINT32_MAX
2641/** Remappable MSI Data: Valid mask. */
2642#define VTD_REMAPPABLE_MSI_DATA_VALID_MASK VTD_BF_REMAPPABLE_MSI_DATA_SUBHANDLE_MASK
2643
2644/** Interrupt format: Compatibility. */
2645#define VTD_INTR_FORMAT_COMPAT 0
2646/** Interrupt format: Remappable. */
2647#define VTD_INTR_FORMAT_REMAPPABLE 1
2648/** @} */
2649
2650
2651/** @name Interrupt Remapping Fault Conditions.
2652 * In accordance with the Intel spec.
2653 * @{ */
2654typedef enum VTDIRFAULT
2655{
2656 /** Reserved bits invalid in remappable interrupt. */
2657 VTDIRFAULT_REMAPPABLE_INTR_RSVD = 0x20,
2658
2659 /** Interrupt index for remappable interrupt exceeds table size or referenced
2660 * address above host address width (HAW) */
2661 VTDIRFAULT_INTR_INDEX_INVALID = 0x21,
2662
2663 /** The IRTE is not present. */
2664 VTDIRFAULT_IRTE_NOT_PRESENT = 0x22,
2665 /** Reading IRTE from memory failed. */
2666 VTDIRFAULT_IRTE_READ_FAILED = 0x23,
2667 /** IRTE reserved bits invalid for an IRTE with Present bit set. */
2668 VTDIRFAULT_IRTE_PRESENT_RSVD = 0x24,
2669
2670 /** Compatibility format interrupt (CFI) blocked due to EIME being enabled or CFIs
2671 * were disabled. */
2672 VTDIRFAULT_CFI_BLOCKED = 0x25,
2673
2674 /** IRTE SID, SVT, SQ bits invalid for an IRTE with Present bit set. */
2675 VTDIRFAULT_IRTE_PRESENT_INVALID = 0x26,
2676
2677 /** Reading posted interrupt descriptor (PID) failed. */
2678 VTDIRFAULT_PID_READ_FAILED = 0x27,
2679 /** PID reserved bits invalid. */
2680 VTDIRFAULT_PID_RSVD = 0x28,
2681
2682 /** Untranslated interrupt requested (without PASID) is invalid. */
2683 VTDIRFAULT_IR_WITHOUT_PASID_INVALID = 0x29
2684} VTDIRFAULT;
2685AssertCompileSize(VTDIRFAULT, 4);
2686/** @} */
2687
2688
2689/** @name Address Translation Fault Conditions.
2690 * In accordance with the Intel spec.
2691 * @{ */
2692typedef enum VTDATFAULT
2693{
2694 /* Legacy root table faults (LRT). */
2695 VTDATFAULT_LRT_1 = 0x8,
2696 VTDATFAULT_LRT_2 = 0x1,
2697 VTDATFAULT_LRT_3 = 0xa,
2698
2699 /* Legacy Context-Table Faults (LCT). */
2700 VTDATFAULT_LCT_1 = 0x9,
2701 VTDATFAULT_LCT_2 = 0x2,
2702 VTDATFAULT_LCT_3 = 0xb,
2703 VTDATFAULT_LCT_4_1 = 0x3,
2704 VTDATFAULT_LCT_4_2 = 0x3,
2705 VTDATFAULT_LCT_4_3 = 0x3,
2706 VTDATFAULT_LCT_5 = 0xd,
2707
2708 /* Legacy Second-Level Table Faults (LSL). */
2709 VTDATFAULT_LSL_1 = 0x7,
2710 VTDATFAULT_LSL_2 = 0xc,
2711
2712 /* Legacy General Faults (LGN). */
2713 VTDATFAULT_LGN_1_1 = 0x4,
2714 VTDATFAULT_LGN_1_2 = 0x4,
2715 VTDATFAULT_LGN_1_3 = 0x4,
2716 VTDATFAULT_LGN_2 = 0x5,
2717 VTDATFAULT_LGN_3 = 0x6,
2718 VTDATFAULT_LGN_4 = 0xe,
2719
2720 /* Root-Table Address Register Faults (RTA). */
2721 VTDATFAULT_RTA_1_1 = 0x30,
2722 VTDATFAULT_RTA_1_2 = 0x30,
2723 VTDATFAULT_RTA_1_3 = 0x30,
2724 VTDATFAULT_RTA_2 = 0x31,
2725 VTDATFAULT_RTA_3 = 0x32,
2726 VTDATFAULT_RTA_4 = 0x33,
2727
2728 /* Scalable-Mode Root-Table Faults (SRT). */
2729 VTDATFAULT_SRT_1 = 0x38,
2730 VTDATFAULT_SRT_2 = 0x39,
2731 VTDATFAULT_SRT_3 = 0x3a,
2732
2733 /* Scalable-Mode Context-Table Faults (SCT). */
2734 VTDATFAULT_SCT_1 = 0x40,
2735 VTDATFAULT_SCT_2 = 0x41,
2736 VTDATFAULT_SCT_3 = 0x42,
2737 VTDATFAULT_SCT_4_1 = 0x43,
2738 VTDATFAULT_SCT_4_2 = 0x43,
2739 VTDATFAULT_SCT_5 = 0x44,
2740 VTDATFAULT_SCT_6 = 0x45,
2741 VTDATFAULT_SCT_7 = 0x46,
2742 VTDATFAULT_SCT_8 = 0x47,
2743 VTDATFAULT_SCT_9 = 0x48,
2744
2745 /* Scalable-Mode PASID-Directory Faults (SPD). */
2746 VTDATFAULT_SPD_1 = 0x50,
2747 VTDATFAULT_SPD_2 = 0x51,
2748 VTDATFAULT_SPD_3 = 0x52,
2749
2750 /* Scalable-Mode PASID-Table Faults (SPT). */
2751 VTDATFAULT_SPT_1 = 0x58,
2752 VTDATFAULT_SPT_2 = 0x59,
2753 VTDATFAULT_SPT_3 = 0x5a,
2754 VTDATFAULT_SPT_4_1 = 0x5b,
2755 VTDATFAULT_SPT_4_2 = 0x5b,
2756 VTDATFAULT_SPT_4_3 = 0x5b,
2757 VTDATFAULT_SPT_4_4 = 0x5b,
2758 VTDATFAULT_SPT_5 = 0x5c,
2759 VTDATFAULT_SPT_6 = 0x5d,
2760
2761 /* Scalable-Mode First-Level Table Faults (SFL). */
2762 VTDATFAULT_SFL_1 = 0x70,
2763 VTDATFAULT_SFL_2 = 0x71,
2764 VTDATFAULT_SFL_3 = 0x72,
2765 VTDATFAULT_SFL_4 = 0x73,
2766 VTDATFAULT_SFL_5 = 0x74,
2767 VTDATFAULT_SFL_6 = 0x75,
2768 VTDATFAULT_SFL_7 = 0x76,
2769 VTDATFAULT_SFL_8 = 0x77,
2770 VTDATFAULT_SFL_9 = 0x90,
2771 VTDATFAULT_SFL_10 = 0x91,
2772
2773 /* Scalable-Mode Second-Level Table Faults (SSL). */
2774 VTDATFAULT_SSL_1 = 0x78,
2775 VTDATFAULT_SSL_2 = 0x79,
2776 VTDATFAULT_SSL_3 = 0x7a,
2777 VTDATFAULT_SSL_4 = 0x7b,
2778 VTDATFAULT_SSL_5 = 0x7c,
2779 VTDATFAULT_SSL_6 = 0x7d,
2780
2781 /* Scalable-Mode General Faults (SGN). */
2782 VTDATFAULT_SGN_1 = 0x80,
2783 VTDATFAULT_SGN_2 = 0x81,
2784 VTDATFAULT_SGN_3 = 0x82,
2785 VTDATFAULT_SGN_4_1 = 0x83,
2786 VTDATFAULT_SGN_4_2 = 0x83,
2787 VTDATFAULT_SGN_5 = 0x84,
2788 VTDATFAULT_SGN_6 = 0x85,
2789 VTDATFAULT_SGN_7 = 0x86,
2790 VTDATFAULT_SGN_8 = 0x87,
2791 VTDATFAULT_SGN_9 = 0x88,
2792 VTDATFAULT_SGN_10 = 0x89
2793} VTDATFAULT;
2794AssertCompileSize(VTDATFAULT, 4);
2795/** @} */
2796
2797
2798/** @name ACPI_DMAR_F_XXX: DMA Remapping Reporting Structure Flags.
2799 * In accordance with the Intel spec.
2800 * @{ */
2801/** INTR_REMAP: Interrupt remapping supported. */
2802#define ACPI_DMAR_F_INTR_REMAP RT_BIT(0)
2803/** X2APIC_OPT_OUT: Request system software to opt-out of enabling x2APIC. */
2804#define ACPI_DMAR_F_X2APIC_OPT_OUT RT_BIT(1)
2805/** DMA_CTRL_PLATFORM_OPT_IN_FLAG: Firmware initiated DMA restricted to reserved
2806 * memory regions (RMRR). */
2807#define ACPI_DMAR_F_DMA_CTRL_PLATFORM_OPT_IN RT_BIT(2)
2808/** @} */
2809
2810
2811/** @name ACPI_DRHD_F_XXX: DMA-Remapping Hardware Unit Definition Flags.
2812 * In accordance with the Intel spec.
2813 * @{ */
2814/** INCLUDE_PCI_ALL: All PCI devices under scope. */
2815#define ACPI_DRHD_F_INCLUDE_PCI_ALL RT_BIT(0)
2816/** @} */
2817
2818
2819/**
2820 * DRHD: DMA-Remapping Hardware Unit Definition.
2821 * In accordance with the Intel spec.
2822 */
2823#pragma pack(1)
2824typedef struct ACPIDRHD
2825{
2826 /** Type (must be 0=DRHD). */
2827 uint16_t uType;
2828 /** Length (must be 16 + size of device scope structure). */
2829 uint16_t cbLength;
2830 /** Flags, see ACPI_DRHD_F_XXX. */
2831 uint8_t fFlags;
2832 /** Reserved (MBZ). */
2833 uint8_t bRsvd;
2834 /** PCI segment number. */
2835 uint16_t uPciSegment;
2836 /** Register Base Address (MMIO). */
2837 uint64_t uRegBaseAddr;
2838 /* Device Scope[] Structures follow. */
2839} ACPIDRHD;
2840#pragma pack()
2841AssertCompileSize(ACPIDRHD, 16);
2842AssertCompileMemberOffset(ACPIDRHD, cbLength, 2);
2843AssertCompileMemberOffset(ACPIDRHD, fFlags, 4);
2844AssertCompileMemberOffset(ACPIDRHD, uPciSegment, 6);
2845AssertCompileMemberOffset(ACPIDRHD, uRegBaseAddr, 8);
2846
2847
2848/** @name ACPIDMARDEVSCOPE_TYPE_XXX: Device Type.
2849 * In accordance with the Intel spec.
2850 * @{ */
2851#define ACPIDMARDEVSCOPE_TYPE_PCI_ENDPOINT 1
2852#define ACPIDMARDEVSCOPE_TYPE_PCI_SUB_HIERARCHY 2
2853#define ACPIDMARDEVSCOPE_TYPE_IOAPIC 3
2854#define ACPIDMARDEVSCOPE_TYPE_MSI_CAP_HPET 4
2855#define ACPIDMARDEVSCOPE_TYPE_ACPI_NAMESPACE_DEV 5
2856/** @} */
2857
2858
2859/**
2860 * ACPI Device Scope Structure - PCI device path.
2861 * In accordance with the Intel spec.
2862 */
2863typedef struct ACPIDEVSCOPEPATH
2864{
2865 /** PCI device number. */
2866 uint8_t uDevice;
2867 /** PCI function number. */
2868 uint8_t uFunction;
2869} ACPIDEVSCOPEPATH;
2870AssertCompileSize(ACPIDEVSCOPEPATH, 2);
2871
2872
2873/**
2874 * Device Scope Structure.
2875 * In accordance with the Intel spec.
2876 */
2877#pragma pack(1)
2878typedef struct ACPIDMARDEVSCOPE
2879{
2880 /** Type, see ACPIDMARDEVSCOPE_TYPE_XXX. */
2881 uint8_t uType;
2882 /** Length (must be 6 + size of auPath field). */
2883 uint8_t cbLength;
2884 /** Reserved (MBZ). */
2885 uint8_t abRsvd[2];
2886 /** Enumeration ID (for I/O APIC, HPET and ACPI namespace devices). */
2887 uint8_t idEnum;
2888 /** First bus number for this device. */
2889 uint8_t uStartBusNum;
2890 /** Hierarchical path from the Host Bridge to the device. */
2891 ACPIDEVSCOPEPATH Path;
2892} ACPIDMARDEVSCOPE;
2893#pragma pack()
2894AssertCompileMemberOffset(ACPIDMARDEVSCOPE, cbLength, 1);
2895AssertCompileMemberOffset(ACPIDMARDEVSCOPE, idEnum, 4);
2896AssertCompileMemberOffset(ACPIDMARDEVSCOPE, uStartBusNum, 5);
2897AssertCompileMemberOffset(ACPIDMARDEVSCOPE, Path, 6);
2898
2899/** ACPI DMAR revision (not the OEM revision field).
2900 * In accordance with the Intel spec. */
2901#define ACPI_DMAR_REVISION 1
2902
2903
2904#endif /* !VBOX_INCLUDED_iommu_intel_h */
2905
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